drivers/event/octeontx2/otx2_evdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2019 Marvell International Ltd.
   3  */
   4
   5 #include <inttypes.h>
   6
   7 #include <rte_bus_pci.h>
   8 #include <rte_common.h>
   9 #include <rte_eal.h>
  10 #include <rte_eventdev_pmd_pci.h>
  11 #include <rte_kvargs.h>
  12 #include <rte_mbuf_pool_ops.h>
  13 #include <rte_pci.h>
  14
  15 #include "otx2_evdev_stats.h"
  16 #include "otx2_evdev.h"
  17 #include "otx2_irq.h"
  18 #include "otx2_tim_evdev.h"
  19
  20 static inline int
  21 sso_get_msix_offsets(const struct rte_eventdev *event_dev)
  22 {
  23         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
  24         uint8_t nb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);
  25         struct otx2_mbox *mbox = dev->mbox;
  26         struct msix_offset_rsp *msix_rsp;
  27         int i, rc;
  28
  29         /* Get SSO and SSOW MSIX vector offsets */
  30         otx2_mbox_alloc_msg_msix_offset(mbox);
  31         rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
  32
  33         for (i = 0; i < nb_ports; i++)
  34                 dev->ssow_msixoff[i] = msix_rsp->ssow_msixoff[i];
  35
  36         for (i = 0; i < dev->nb_event_queues; i++)
  37                 dev->sso_msixoff[i] = msix_rsp->sso_msixoff[i];
  38
  39         return rc;
  40 }
  41
  42 void
  43 sso_fastpath_fns_set(struct rte_eventdev *event_dev)
  44 {
  45         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
  46         /* Single WS modes */
  47         const event_dequeue_t ssogws_deq[2][2][2][2][2][2][2] = {
  48 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  49                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_ ##name,
  50 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  51 #undef R
  52         };
  53
  54         const event_dequeue_burst_t ssogws_deq_burst[2][2][2][2][2][2][2] = {
  55 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  56                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_burst_ ##name,
  57 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  58 #undef R
  59         };
  60
  61         const event_dequeue_t ssogws_deq_timeout[2][2][2][2][2][2][2] = {
  62 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  63                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_timeout_ ##name,
  64 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  65 #undef R
  66         };
  67
  68         const event_dequeue_burst_t
  69                 ssogws_deq_timeout_burst[2][2][2][2][2][2][2] = {
  70 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  71                 [f6][f5][f4][f3][f2][f1][f0] =                          \
  72                         otx2_ssogws_deq_timeout_burst_ ##name,
  73 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  74 #undef R
  75         };
  76
  77         const event_dequeue_t ssogws_deq_seg[2][2][2][2][2][2][2] = {
  78 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  79                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_seg_ ##name,
  80 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  81 #undef R
  82         };
  83
  84         const event_dequeue_burst_t
  85                 ssogws_deq_seg_burst[2][2][2][2][2][2][2] = {
  86 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  87                 [f6][f5][f4][f3][f2][f1][f0] =                          \
  88                         otx2_ssogws_deq_seg_burst_ ##name,
  89 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  90 #undef R
  91         };
  92
  93         const event_dequeue_t ssogws_deq_seg_timeout[2][2][2][2][2][2][2] = {
  94 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  95                 [f6][f5][f4][f3][f2][f1][f0] =                          \
  96                         otx2_ssogws_deq_seg_timeout_ ##name,
  97 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  98 #undef R
  99         };
 100
 101         const event_dequeue_burst_t
 102                 ssogws_deq_seg_timeout_burst[2][2][2][2][2][2][2] = {
 103 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 104                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 105                                 otx2_ssogws_deq_seg_timeout_burst_ ##name,
 106 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 107 #undef R
 108         };
 109
 110
 111         /* Dual WS modes */
 112         const event_dequeue_t ssogws_dual_deq[2][2][2][2][2][2][2] = {
 113 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 114                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_ ##name,
 115 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 116 #undef R
 117         };
 118
 119         const event_dequeue_burst_t
 120                 ssogws_dual_deq_burst[2][2][2][2][2][2][2] = {
 121 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 122                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 123                         otx2_ssogws_dual_deq_burst_ ##name,
 124 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 125 #undef R
 126         };
 127
 128         const event_dequeue_t ssogws_dual_deq_timeout[2][2][2][2][2][2][2] = {
 129 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 130                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 131                         otx2_ssogws_dual_deq_timeout_ ##name,
 132 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 133 #undef R
 134         };
 135
 136         const event_dequeue_burst_t
 137                 ssogws_dual_deq_timeout_burst[2][2][2][2][2][2][2] = {
 138 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 139         [f6][f5][f4][f3][f2][f1][f0] =                                  \
 140                         otx2_ssogws_dual_deq_timeout_burst_ ##name,
 141 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 142 #undef R
 143         };
 144
 145         const event_dequeue_t ssogws_dual_deq_seg[2][2][2][2][2][2][2] = {
 146 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 147                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_seg_ ##name,
 148 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 149 #undef R
 150         };
 151
 152         const event_dequeue_burst_t
 153                 ssogws_dual_deq_seg_burst[2][2][2][2][2][2][2] = {
 154 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 155                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 156                         otx2_ssogws_dual_deq_seg_burst_ ##name,
 157 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 158 #undef R
 159         };
 160
 161         const event_dequeue_t
 162                 ssogws_dual_deq_seg_timeout[2][2][2][2][2][2][2] = {
 163 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 164                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 165                         otx2_ssogws_dual_deq_seg_timeout_ ##name,
 166 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 167 #undef R
 168         };
 169
 170         const event_dequeue_burst_t
 171                 ssogws_dual_deq_seg_timeout_burst[2][2][2][2][2][2][2] = {
 172 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 173                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 174                         otx2_ssogws_dual_deq_seg_timeout_burst_ ##name,
 175 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 176 #undef R
 177         };
 178
 179         /* Tx modes */
 180         const event_tx_adapter_enqueue ssogws_tx_adptr_enq[2][2][2][2][2][2] = {
 181 #define T(name, f5, f4, f3, f2, f1, f0, sz, flags)                      \
 182                 [f5][f4][f3][f2][f1][f0] =  otx2_ssogws_tx_adptr_enq_ ## name,
 183 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
 184 #undef T
 185         };
 186
 187         const event_tx_adapter_enqueue
 188                 ssogws_tx_adptr_enq_seg[2][2][2][2][2][2] = {
 189 #define T(name, f5, f4, f3, f2, f1, f0, sz, flags)                      \
 190                 [f5][f4][f3][f2][f1][f0] =                              \
 191                         otx2_ssogws_tx_adptr_enq_seg_ ## name,
 192 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
 193 #undef T
 194         };
 195
 196         const event_tx_adapter_enqueue
 197                 ssogws_dual_tx_adptr_enq[2][2][2][2][2][2] = {
 198 #define T(name, f5, f4, f3, f2, f1, f0, sz, flags)                      \
 199                 [f5][f4][f3][f2][f1][f0] =                              \
 200                         otx2_ssogws_dual_tx_adptr_enq_ ## name,
 201 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
 202 #undef T
 203         };
 204
 205         const event_tx_adapter_enqueue
 206                 ssogws_dual_tx_adptr_enq_seg[2][2][2][2][2][2] = {
 207 #define T(name, f5, f4, f3, f2, f1, f0, sz, flags)                      \
 208                 [f5][f4][f3][f2][f1][f0] =                              \
 209                         otx2_ssogws_dual_tx_adptr_enq_seg_ ## name,
 210 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
 211 #undef T
 212         };
 213
 214         event_dev->enqueue                      = otx2_ssogws_enq;
 215         event_dev->enqueue_burst                = otx2_ssogws_enq_burst;
 216         event_dev->enqueue_new_burst            = otx2_ssogws_enq_new_burst;
 217         event_dev->enqueue_forward_burst        = otx2_ssogws_enq_fwd_burst;
 218         if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
 219                 event_dev->dequeue              = ssogws_deq_seg
 220                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 221                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 222                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 223                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 224                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 225                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 226                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 227                 event_dev->dequeue_burst        = ssogws_deq_seg_burst
 228                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 229                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 230                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 231                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 232                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 233                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 234                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 235                 if (dev->is_timeout_deq) {
 236                         event_dev->dequeue      = ssogws_deq_seg_timeout
 237                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 238                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 239                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 240                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 241                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 242                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 243                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 244                         event_dev->dequeue_burst        =
 245                                 ssogws_deq_seg_timeout_burst
 246                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 247                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 248                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 249                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 250                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 251                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 252                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 253                 }
 254         } else {
 255                 event_dev->dequeue                      = ssogws_deq
 256                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 257                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 258                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 259                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 260                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 261                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 262                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 263                 event_dev->dequeue_burst                = ssogws_deq_burst
 264                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 265                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 266                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 267                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 268                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 269                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 270                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 271                 if (dev->is_timeout_deq) {
 272                         event_dev->dequeue              = ssogws_deq_timeout
 273                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 274                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 275                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 276                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 277                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 278                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 279                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 280                         event_dev->dequeue_burst        =
 281                                 ssogws_deq_timeout_burst
 282                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 283                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 284                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 285                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 286                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 287                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 288                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 289                 }
 290         }
 291
 292         if (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {
 293                 /* [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM] */
 294                 event_dev->txa_enqueue = ssogws_tx_adptr_enq_seg
 295                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
 296                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
 297                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]
 298                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]
 299                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
 300                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
 301         } else {
 302                 event_dev->txa_enqueue = ssogws_tx_adptr_enq
 303                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
 304                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
 305                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]
 306                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]
 307                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
 308                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
 309         }
 310
 311         if (dev->dual_ws) {
 312                 event_dev->enqueue              = otx2_ssogws_dual_enq;
 313                 event_dev->enqueue_burst        = otx2_ssogws_dual_enq_burst;
 314                 event_dev->enqueue_new_burst    =
 315                                         otx2_ssogws_dual_enq_new_burst;
 316                 event_dev->enqueue_forward_burst =
 317                                         otx2_ssogws_dual_enq_fwd_burst;
 318
 319                 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
 320                         event_dev->dequeue      = ssogws_dual_deq_seg
 321                                 [!!(dev->rx_offloads &
 322                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 323                                 [!!(dev->rx_offloads &
 324                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 325                                 [!!(dev->rx_offloads &
 326                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 327                                 [!!(dev->rx_offloads &
 328                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 329                                 [!!(dev->rx_offloads &
 330                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 331                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 332                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 333                         event_dev->dequeue_burst = ssogws_dual_deq_seg_burst
 334                                 [!!(dev->rx_offloads &
 335                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 336                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 337                                 [!!(dev->rx_offloads &
 338                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 339                                 [!!(dev->rx_offloads &
 340                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 341                                 [!!(dev->rx_offloads &
 342                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 343                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 344                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 345                         if (dev->is_timeout_deq) {
 346                                 event_dev->dequeue      =
 347                                         ssogws_dual_deq_seg_timeout
 348                                         [!!(dev->rx_offloads &
 349                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 350                                         [!!(dev->rx_offloads &
 351                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 352                                         [!!(dev->rx_offloads &
 353                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 354                                         [!!(dev->rx_offloads &
 355                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 356                                         [!!(dev->rx_offloads &
 357                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 358                                         [!!(dev->rx_offloads &
 359                                                         NIX_RX_OFFLOAD_PTYPE_F)]
 360                                         [!!(dev->rx_offloads &
 361                                                         NIX_RX_OFFLOAD_RSS_F)];
 362                                 event_dev->dequeue_burst =
 363                                         ssogws_dual_deq_seg_timeout_burst
 364                                         [!!(dev->rx_offloads &
 365                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 366                                         [!!(dev->rx_offloads &
 367                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 368                                         [!!(dev->rx_offloads &
 369                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 370                                         [!!(dev->rx_offloads &
 371                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 372                                         [!!(dev->rx_offloads &
 373                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 374                                         [!!(dev->rx_offloads &
 375                                                         NIX_RX_OFFLOAD_PTYPE_F)]
 376                                         [!!(dev->rx_offloads &
 377                                                         NIX_RX_OFFLOAD_RSS_F)];
 378                         }
 379                 } else {
 380                         event_dev->dequeue              = ssogws_dual_deq
 381                                 [!!(dev->rx_offloads &
 382                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 383                                 [!!(dev->rx_offloads &
 384                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 385                                 [!!(dev->rx_offloads &
 386                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 387                                 [!!(dev->rx_offloads &
 388                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 389                                 [!!(dev->rx_offloads &
 390                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 391                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 392                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 393                         event_dev->dequeue_burst        = ssogws_dual_deq_burst
 394                                 [!!(dev->rx_offloads &
 395                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 396                                 [!!(dev->rx_offloads &
 397                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 398                                 [!!(dev->rx_offloads &
 399                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 400                                 [!!(dev->rx_offloads &
 401                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 402                                 [!!(dev->rx_offloads &
 403                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 404                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 405                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 406                         if (dev->is_timeout_deq) {
 407                                 event_dev->dequeue      =
 408                                         ssogws_dual_deq_timeout
 409                                         [!!(dev->rx_offloads &
 410                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 411                                         [!!(dev->rx_offloads &
 412                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 413                                         [!!(dev->rx_offloads &
 414                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 415                                         [!!(dev->rx_offloads &
 416                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 417                                         [!!(dev->rx_offloads &
 418                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 419                                         [!!(dev->rx_offloads &
 420                                                         NIX_RX_OFFLOAD_PTYPE_F)]
 421                                         [!!(dev->rx_offloads &
 422                                                         NIX_RX_OFFLOAD_RSS_F)];
 423                                 event_dev->dequeue_burst =
 424                                         ssogws_dual_deq_timeout_burst
 425                                         [!!(dev->rx_offloads &
 426                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 427                                         [!!(dev->rx_offloads &
 428                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 429                                         [!!(dev->rx_offloads &
 430                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 431                                         [!!(dev->rx_offloads &
 432                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 433                                         [!!(dev->rx_offloads &
 434                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 435                                         [!!(dev->rx_offloads &
 436                                                         NIX_RX_OFFLOAD_PTYPE_F)]
 437                                         [!!(dev->rx_offloads &
 438                                                         NIX_RX_OFFLOAD_RSS_F)];
 439                         }
 440                 }
 441
 442                 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {
 443                 /* [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM] */
 444                         event_dev->txa_enqueue = ssogws_dual_tx_adptr_enq_seg
 445                                 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
 446                                 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
 447                                 [!!(dev->tx_offloads &
 448                                                 NIX_TX_OFFLOAD_MBUF_NOFF_F)]
 449                                 [!!(dev->tx_offloads &
 450                                                 NIX_TX_OFFLOAD_VLAN_QINQ_F)]
 451                                 [!!(dev->tx_offloads &
 452                                                 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
 453                                 [!!(dev->tx_offloads &
 454                                                 NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
 455                 } else {
 456                         event_dev->txa_enqueue = ssogws_dual_tx_adptr_enq
 457                                 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
 458                                 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
 459                                 [!!(dev->tx_offloads &
 460                                                 NIX_TX_OFFLOAD_MBUF_NOFF_F)]
 461                                 [!!(dev->tx_offloads &
 462                                                 NIX_TX_OFFLOAD_VLAN_QINQ_F)]
 463                                 [!!(dev->tx_offloads &
 464                                                 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
 465                                 [!!(dev->tx_offloads &
 466                                                 NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
 467                 }
 468         }
 469
 470         event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
 471         rte_mb();
 472 }
 473
 474 static void
 475 otx2_sso_info_get(struct rte_eventdev *event_dev,
 476                   struct rte_event_dev_info *dev_info)
 477 {
 478         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 479
 480         dev_info->driver_name = RTE_STR(EVENTDEV_NAME_OCTEONTX2_PMD);
 481         dev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns;
 482         dev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns;
 483         dev_info->max_event_queues = dev->max_event_queues;
 484         dev_info->max_event_queue_flows = (1ULL << 20);
 485         dev_info->max_event_queue_priority_levels = 8;
 486         dev_info->max_event_priority_levels = 1;
 487         dev_info->max_event_ports = dev->max_event_ports;
 488         dev_info->max_event_port_dequeue_depth = 1;
 489         dev_info->max_event_port_enqueue_depth = 1;
 490         dev_info->max_num_events =  dev->max_num_events;
 491         dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS |
 492                                         RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
 493                                         RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES |
 494                                         RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
 495                                         RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
 496                                         RTE_EVENT_DEV_CAP_NONSEQ_MODE;
 497 }
 498
 499 static void
 500 sso_port_link_modify(struct otx2_ssogws *ws, uint8_t queue, uint8_t enable)
 501 {
 502         uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
 503         uint64_t val;
 504
 505         val = queue;
 506         val |= 0ULL << 12; /* SET 0 */
 507         val |= 0x8000800080000000; /* Dont modify rest of the masks */
 508         val |= (uint64_t)enable << 14;   /* Enable/Disable Membership. */
 509
 510         otx2_write64(val, base + SSOW_LF_GWS_GRPMSK_CHG);
 511 }
 512
 513 static int
 514 otx2_sso_port_link(struct rte_eventdev *event_dev, void *port,
 515                    const uint8_t queues[], const uint8_t priorities[],
 516                    uint16_t nb_links)
 517 {
 518         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 519         uint8_t port_id = 0;
 520         uint16_t link;
 521
 522         RTE_SET_USED(priorities);
 523         for (link = 0; link < nb_links; link++) {
 524                 if (dev->dual_ws) {
 525                         struct otx2_ssogws_dual *ws = port;
 526
 527                         port_id = ws->port;
 528                         sso_port_link_modify((struct otx2_ssogws *)
 529                                         &ws->ws_state[0], queues[link], true);
 530                         sso_port_link_modify((struct otx2_ssogws *)
 531                                         &ws->ws_state[1], queues[link], true);
 532                 } else {
 533                         struct otx2_ssogws *ws = port;
 534
 535                         port_id = ws->port;
 536                         sso_port_link_modify(ws, queues[link], true);
 537                 }
 538         }
 539         sso_func_trace("Port=%d nb_links=%d", port_id, nb_links);
 540
 541         return (int)nb_links;
 542 }
 543
 544 static int
 545 otx2_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
 546                      uint8_t queues[], uint16_t nb_unlinks)
 547 {
 548         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 549         uint8_t port_id = 0;
 550         uint16_t unlink;
 551
 552         for (unlink = 0; unlink < nb_unlinks; unlink++) {
 553                 if (dev->dual_ws) {
 554                         struct otx2_ssogws_dual *ws = port;
 555
 556                         port_id = ws->port;
 557                         sso_port_link_modify((struct otx2_ssogws *)
 558                                         &ws->ws_state[0], queues[unlink],
 559                                         false);
 560                         sso_port_link_modify((struct otx2_ssogws *)
 561                                         &ws->ws_state[1], queues[unlink],
 562                                         false);
 563                 } else {
 564                         struct otx2_ssogws *ws = port;
 565
 566                         port_id = ws->port;
 567                         sso_port_link_modify(ws, queues[unlink], false);
 568                 }
 569         }
 570         sso_func_trace("Port=%d nb_unlinks=%d", port_id, nb_unlinks);
 571
 572         return (int)nb_unlinks;
 573 }
 574
 575 static int
 576 sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type,
 577               uint16_t nb_lf, uint8_t attach)
 578 {
 579         if (attach) {
 580                 struct rsrc_attach_req *req;
 581
 582                 req = otx2_mbox_alloc_msg_attach_resources(mbox);
 583                 switch (type) {
 584                 case SSO_LF_GGRP:
 585                         req->sso = nb_lf;
 586                         break;
 587                 case SSO_LF_GWS:
 588                         req->ssow = nb_lf;
 589                         break;
 590                 default:
 591                         return -EINVAL;
 592                 }
 593                 req->modify = true;
 594                 if (otx2_mbox_process(mbox) < 0)
 595                         return -EIO;
 596         } else {
 597                 struct rsrc_detach_req *req;
 598
 599                 req = otx2_mbox_alloc_msg_detach_resources(mbox);
 600                 switch (type) {
 601                 case SSO_LF_GGRP:
 602                         req->sso = true;
 603                         break;
 604                 case SSO_LF_GWS:
 605                         req->ssow = true;
 606                         break;
 607                 default:
 608                         return -EINVAL;
 609                 }
 610                 req->partial = true;
 611                 if (otx2_mbox_process(mbox) < 0)
 612                         return -EIO;
 613         }
 614
 615         return 0;
 616 }
 617
 618 static int
 619 sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,
 620            enum otx2_sso_lf_type type, uint16_t nb_lf, uint8_t alloc)
 621 {
 622         void *rsp;
 623         int rc;
 624
 625         if (alloc) {
 626                 switch (type) {
 627                 case SSO_LF_GGRP:
 628                         {
 629                         struct sso_lf_alloc_req *req_ggrp;
 630                         req_ggrp = otx2_mbox_alloc_msg_sso_lf_alloc(mbox);
 631                         req_ggrp->hwgrps = nb_lf;
 632                         }
 633                         break;
 634                 case SSO_LF_GWS:
 635                         {
 636                         struct ssow_lf_alloc_req *req_hws;
 637                         req_hws = otx2_mbox_alloc_msg_ssow_lf_alloc(mbox);
 638                         req_hws->hws = nb_lf;
 639                         }
 640                         break;
 641                 default:
 642                         return -EINVAL;
 643                 }
 644         } else {
 645                 switch (type) {
 646                 case SSO_LF_GGRP:
 647                         {
 648                         struct sso_lf_free_req *req_ggrp;
 649                         req_ggrp = otx2_mbox_alloc_msg_sso_lf_free(mbox);
 650                         req_ggrp->hwgrps = nb_lf;
 651                         }
 652                         break;
 653                 case SSO_LF_GWS:
 654                         {
 655                         struct ssow_lf_free_req *req_hws;
 656                         req_hws = otx2_mbox_alloc_msg_ssow_lf_free(mbox);
 657                         req_hws->hws = nb_lf;
 658                         }
 659                         break;
 660                 default:
 661                         return -EINVAL;
 662                 }
 663         }
 664
 665         rc = otx2_mbox_process_msg_tmo(mbox, (void **)&rsp, ~0);
 666         if (rc < 0)
 667                 return rc;
 668
 669         if (alloc && type == SSO_LF_GGRP) {
 670                 struct sso_lf_alloc_rsp *rsp_ggrp = rsp;
 671
 672                 dev->xaq_buf_size = rsp_ggrp->xaq_buf_size;
 673                 dev->xae_waes = rsp_ggrp->xaq_wq_entries;
 674                 dev->iue = rsp_ggrp->in_unit_entries;
 675         }
 676
 677         return 0;
 678 }
 679
 680 static void
 681 otx2_sso_port_release(void *port)
 682 {
 683         rte_free(port);
 684 }
 685
 686 static void
 687 otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
 688 {
 689         RTE_SET_USED(event_dev);
 690         RTE_SET_USED(queue_id);
 691 }
 692
 693 static void
 694 sso_clr_links(const struct rte_eventdev *event_dev)
 695 {
 696         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 697         int i, j;
 698
 699         for (i = 0; i < dev->nb_event_ports; i++) {
 700                 if (dev->dual_ws) {
 701                         struct otx2_ssogws_dual *ws;
 702
 703                         ws = event_dev->data->ports[i];
 704                         for (j = 0; j < dev->nb_event_queues; j++) {
 705                                 sso_port_link_modify((struct otx2_ssogws *)
 706                                                 &ws->ws_state[0], j, false);
 707                                 sso_port_link_modify((struct otx2_ssogws *)
 708                                                 &ws->ws_state[1], j, false);
 709                         }
 710                 } else {
 711                         struct otx2_ssogws *ws;
 712
 713                         ws = event_dev->data->ports[i];
 714                         for (j = 0; j < dev->nb_event_queues; j++)
 715                                 sso_port_link_modify(ws, j, false);
 716                 }
 717         }
 718 }
 719
 720 static void
 721 sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)
 722 {
 723         ws->tag_op              = base + SSOW_LF_GWS_TAG;
 724         ws->wqp_op              = base + SSOW_LF_GWS_WQP;
 725         ws->getwrk_op           = base + SSOW_LF_GWS_OP_GET_WORK;
 726         ws->swtp_op             = base + SSOW_LF_GWS_SWTP;
 727         ws->swtag_norm_op       = base + SSOW_LF_GWS_OP_SWTAG_NORM;
 728         ws->swtag_desched_op    = base + SSOW_LF_GWS_OP_SWTAG_DESCHED;
 729 }
 730
 731 static int
 732 sso_configure_dual_ports(const struct rte_eventdev *event_dev)
 733 {
 734         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 735         struct otx2_mbox *mbox = dev->mbox;
 736         uint8_t vws = 0;
 737         uint8_t nb_lf;
 738         int i, rc;
 739
 740         otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
 741
 742         nb_lf = dev->nb_event_ports * 2;
 743         /* Ask AF to attach required LFs. */
 744         rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
 745         if (rc < 0) {
 746                 otx2_err("Failed to attach SSO GWS LF");
 747                 return -ENODEV;
 748         }
 749
 750         if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
 751                 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
 752                 otx2_err("Failed to init SSO GWS LF");
 753                 return -ENODEV;
 754         }
 755
 756         for (i = 0; i < dev->nb_event_ports; i++) {
 757                 struct otx2_ssogws_dual *ws;
 758                 uintptr_t base;
 759
 760                 /* Free memory prior to re-allocation if needed */
 761                 if (event_dev->data->ports[i] != NULL) {
 762                         ws = event_dev->data->ports[i];
 763                         rte_free(ws);
 764                         ws = NULL;
 765                 }
 766
 767                 /* Allocate event port memory */
 768                 ws = rte_zmalloc_socket("otx2_sso_ws",
 769                                         sizeof(struct otx2_ssogws_dual),
 770                                         RTE_CACHE_LINE_SIZE,
 771                                         event_dev->data->socket_id);
 772                 if (ws == NULL) {
 773                         otx2_err("Failed to alloc memory for port=%d", i);
 774                         rc = -ENOMEM;
 775                         break;
 776                 }
 777
 778                 ws->port = i;
 779                 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
 780                 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[0], base);
 781                 vws++;
 782
 783                 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
 784                 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[1], base);
 785                 vws++;
 786
 787                 event_dev->data->ports[i] = ws;
 788         }
 789
 790         if (rc < 0) {
 791                 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
 792                 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
 793         }
 794
 795         return rc;
 796 }
 797
 798 static int
 799 sso_configure_ports(const struct rte_eventdev *event_dev)
 800 {
 801         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 802         struct otx2_mbox *mbox = dev->mbox;
 803         uint8_t nb_lf;
 804         int i, rc;
 805
 806         otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
 807
 808         nb_lf = dev->nb_event_ports;
 809         /* Ask AF to attach required LFs. */
 810         rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
 811         if (rc < 0) {
 812                 otx2_err("Failed to attach SSO GWS LF");
 813                 return -ENODEV;
 814         }
 815
 816         if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
 817                 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
 818                 otx2_err("Failed to init SSO GWS LF");
 819                 return -ENODEV;
 820         }
 821
 822         for (i = 0; i < nb_lf; i++) {
 823                 struct otx2_ssogws *ws;
 824                 uintptr_t base;
 825
 826                 /* Free memory prior to re-allocation if needed */
 827                 if (event_dev->data->ports[i] != NULL) {
 828                         ws = event_dev->data->ports[i];
 829                         rte_free(ws);
 830                         ws = NULL;
 831                 }
 832
 833                 /* Allocate event port memory */
 834                 ws = rte_zmalloc_socket("otx2_sso_ws",
 835                                         sizeof(struct otx2_ssogws),
 836                                         RTE_CACHE_LINE_SIZE,
 837                                         event_dev->data->socket_id);
 838                 if (ws == NULL) {
 839                         otx2_err("Failed to alloc memory for port=%d", i);
 840                         rc = -ENOMEM;
 841                         break;
 842                 }
 843
 844                 ws->port = i;
 845                 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);
 846                 sso_set_port_ops(ws, base);
 847
 848                 event_dev->data->ports[i] = ws;
 849         }
 850
 851         if (rc < 0) {
 852                 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
 853                 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
 854         }
 855
 856         return rc;
 857 }
 858
 859 static int
 860 sso_configure_queues(const struct rte_eventdev *event_dev)
 861 {
 862         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 863         struct otx2_mbox *mbox = dev->mbox;
 864         uint8_t nb_lf;
 865         int rc;
 866
 867         otx2_sso_dbg("Configuring event queues %d", dev->nb_event_queues);
 868
 869         nb_lf = dev->nb_event_queues;
 870         /* Ask AF to attach required LFs. */
 871         rc = sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, true);
 872         if (rc < 0) {
 873                 otx2_err("Failed to attach SSO GGRP LF");
 874                 return -ENODEV;
 875         }
 876
 877         if (sso_lf_cfg(dev, mbox, SSO_LF_GGRP, nb_lf, true) < 0) {
 878                 sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, false);
 879                 otx2_err("Failed to init SSO GGRP LF");
 880                 return -ENODEV;
 881         }
 882
 883         return rc;
 884 }
 885
 886 static int
 887 sso_xaq_allocate(struct otx2_sso_evdev *dev)
 888 {
 889         const struct rte_memzone *mz;
 890         struct npa_aura_s *aura;
 891         static int reconfig_cnt;
 892         char pool_name[RTE_MEMZONE_NAMESIZE];
 893         uint32_t xaq_cnt;
 894         int rc;
 895
 896         if (dev->xaq_pool)
 897                 rte_mempool_free(dev->xaq_pool);
 898
 899         /*
 900          * Allocate memory for Add work backpressure.
 901          */
 902         mz = rte_memzone_lookup(OTX2_SSO_FC_NAME);
 903         if (mz == NULL)
 904                 mz = rte_memzone_reserve_aligned(OTX2_SSO_FC_NAME,
 905                                                  OTX2_ALIGN +
 906                                                  sizeof(struct npa_aura_s),
 907                                                  rte_socket_id(),
 908                                                  RTE_MEMZONE_IOVA_CONTIG,
 909                                                  OTX2_ALIGN);
 910         if (mz == NULL) {
 911                 otx2_err("Failed to allocate mem for fcmem");
 912                 return -ENOMEM;
 913         }
 914
 915         dev->fc_iova = mz->iova;
 916         dev->fc_mem = mz->addr;
 917
 918         aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + OTX2_ALIGN);
 919         memset(aura, 0, sizeof(struct npa_aura_s));
 920
 921         aura->fc_ena = 1;
 922         aura->fc_addr = dev->fc_iova;
 923         aura->fc_hyst_bits = 0; /* Store count on all updates */
 924
 925         /* Taken from HRM 14.3.3(4) */
 926         xaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT;
 927         if (dev->xae_cnt)
 928                 xaq_cnt += dev->xae_cnt / dev->xae_waes;
 929         else if (dev->adptr_xae_cnt)
 930                 xaq_cnt += (dev->adptr_xae_cnt / dev->xae_waes) +
 931                         (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
 932         else
 933                 xaq_cnt += (dev->iue / dev->xae_waes) +
 934                         (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
 935
 936         otx2_sso_dbg("Configuring %d xaq buffers", xaq_cnt);
 937         /* Setup XAQ based on number of nb queues. */
 938         snprintf(pool_name, 30, "otx2_xaq_buf_pool_%d", reconfig_cnt);
 939         dev->xaq_pool = (void *)rte_mempool_create_empty(pool_name,
 940                         xaq_cnt, dev->xaq_buf_size, 0, 0,
 941                         rte_socket_id(), 0);
 942
 943         if (dev->xaq_pool == NULL) {
 944                 otx2_err("Unable to create empty mempool.");
 945                 rte_memzone_free(mz);
 946                 return -ENOMEM;
 947         }
 948
 949         rc = rte_mempool_set_ops_byname(dev->xaq_pool,
 950                                         rte_mbuf_platform_mempool_ops(), aura);
 951         if (rc != 0) {
 952                 otx2_err("Unable to set xaqpool ops.");
 953                 goto alloc_fail;
 954         }
 955
 956         rc = rte_mempool_populate_default(dev->xaq_pool);
 957         if (rc < 0) {
 958                 otx2_err("Unable to set populate xaqpool.");
 959                 goto alloc_fail;
 960         }
 961         reconfig_cnt++;
 962         /* When SW does addwork (enqueue) check if there is space in XAQ by
 963          * comparing fc_addr above against the xaq_lmt calculated below.
 964          * There should be a minimum headroom (OTX2_SSO_XAQ_SLACK / 2) for SSO
 965          * to request XAQ to cache them even before enqueue is called.
 966          */
 967         dev->xaq_lmt = xaq_cnt - (OTX2_SSO_XAQ_SLACK / 2 *
 968                                   dev->nb_event_queues);
 969         dev->nb_xaq_cfg = xaq_cnt;
 970
 971         return 0;
 972 alloc_fail:
 973         rte_mempool_free(dev->xaq_pool);
 974         rte_memzone_free(mz);
 975         return rc;
 976 }
 977
 978 static int
 979 sso_ggrp_alloc_xaq(struct otx2_sso_evdev *dev)
 980 {
 981         struct otx2_mbox *mbox = dev->mbox;
 982         struct sso_hw_setconfig *req;
 983
 984         otx2_sso_dbg("Configuring XAQ for GGRPs");
 985         req = otx2_mbox_alloc_msg_sso_hw_setconfig(mbox);
 986         req->npa_pf_func = otx2_npa_pf_func_get();
 987         req->npa_aura_id = npa_lf_aura_handle_to_aura(dev->xaq_pool->pool_id);
 988         req->hwgrps = dev->nb_event_queues;
 989
 990         return otx2_mbox_process(mbox);
 991 }
 992
 993 static void
 994 sso_lf_teardown(struct otx2_sso_evdev *dev,
 995                 enum otx2_sso_lf_type lf_type)
 996 {
 997         uint8_t nb_lf;
 998
 999         switch (lf_type) {
1000         case SSO_LF_GGRP:
1001                 nb_lf = dev->nb_event_queues;
1002                 break;
1003         case SSO_LF_GWS:
1004                 nb_lf = dev->nb_event_ports;
1005                 nb_lf *= dev->dual_ws ? 2 : 1;
1006                 break;
1007         default:
1008                 return;
1009         }
1010
1011         sso_lf_cfg(dev, dev->mbox, lf_type, nb_lf, false);
1012         sso_hw_lf_cfg(dev->mbox, lf_type, nb_lf, false);
1013 }
1014
1015 static int
1016 otx2_sso_configure(const struct rte_eventdev *event_dev)
1017 {
1018         struct rte_event_dev_config *conf = &event_dev->data->dev_conf;
1019         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1020         uint32_t deq_tmo_ns;
1021         int rc;
1022
1023         sso_func_trace();
1024         deq_tmo_ns = conf->dequeue_timeout_ns;
1025
1026         if (deq_tmo_ns == 0)
1027                 deq_tmo_ns = dev->min_dequeue_timeout_ns;
1028
1029         if (deq_tmo_ns < dev->min_dequeue_timeout_ns ||
1030             deq_tmo_ns > dev->max_dequeue_timeout_ns) {
1031                 otx2_err("Unsupported dequeue timeout requested");
1032                 return -EINVAL;
1033         }
1034
1035         if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
1036                 dev->is_timeout_deq = 1;
1037
1038         dev->deq_tmo_ns = deq_tmo_ns;
1039
1040         if (conf->nb_event_ports > dev->max_event_ports ||
1041             conf->nb_event_queues > dev->max_event_queues) {
1042                 otx2_err("Unsupported event queues/ports requested");
1043                 return -EINVAL;
1044         }
1045
1046         if (conf->nb_event_port_dequeue_depth > 1) {
1047                 otx2_err("Unsupported event port deq depth requested");
1048                 return -EINVAL;
1049         }
1050
1051         if (conf->nb_event_port_enqueue_depth > 1) {
1052                 otx2_err("Unsupported event port enq depth requested");
1053                 return -EINVAL;
1054         }
1055
1056         if (dev->configured)
1057                 sso_unregister_irqs(event_dev);
1058
1059         if (dev->nb_event_queues) {
1060                 /* Finit any previous queues. */
1061                 sso_lf_teardown(dev, SSO_LF_GGRP);
1062         }
1063         if (dev->nb_event_ports) {
1064                 /* Finit any previous ports. */
1065                 sso_lf_teardown(dev, SSO_LF_GWS);
1066         }
1067
1068         dev->nb_event_queues = conf->nb_event_queues;
1069         dev->nb_event_ports = conf->nb_event_ports;
1070
1071         if (dev->dual_ws)
1072                 rc = sso_configure_dual_ports(event_dev);
1073         else
1074                 rc = sso_configure_ports(event_dev);
1075
1076         if (rc < 0) {
1077                 otx2_err("Failed to configure event ports");
1078                 return -ENODEV;
1079         }
1080
1081         if (sso_configure_queues(event_dev) < 0) {
1082                 otx2_err("Failed to configure event queues");
1083                 rc = -ENODEV;
1084                 goto teardown_hws;
1085         }
1086
1087         if (sso_xaq_allocate(dev) < 0) {
1088                 rc = -ENOMEM;
1089                 goto teardown_hwggrp;
1090         }
1091
1092         /* Clear any prior port-queue mapping. */
1093         sso_clr_links(event_dev);
1094         rc = sso_ggrp_alloc_xaq(dev);
1095         if (rc < 0) {
1096                 otx2_err("Failed to alloc xaq to ggrp %d", rc);
1097                 goto teardown_hwggrp;
1098         }
1099
1100         rc = sso_get_msix_offsets(event_dev);
1101         if (rc < 0) {
1102                 otx2_err("Failed to get msix offsets %d", rc);
1103                 goto teardown_hwggrp;
1104         }
1105
1106         rc = sso_register_irqs(event_dev);
1107         if (rc < 0) {
1108                 otx2_err("Failed to register irq %d", rc);
1109                 goto teardown_hwggrp;
1110         }
1111
1112         dev->configured = 1;
1113         rte_mb();
1114
1115         return 0;
1116 teardown_hwggrp:
1117         sso_lf_teardown(dev, SSO_LF_GGRP);
1118 teardown_hws:
1119         sso_lf_teardown(dev, SSO_LF_GWS);
1120         dev->nb_event_queues = 0;
1121         dev->nb_event_ports = 0;
1122         dev->configured = 0;
1123         return rc;
1124 }
1125
1126 static void
1127 otx2_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
1128                         struct rte_event_queue_conf *queue_conf)
1129 {
1130         RTE_SET_USED(event_dev);
1131         RTE_SET_USED(queue_id);
1132
1133         queue_conf->nb_atomic_flows = (1ULL << 20);
1134         queue_conf->nb_atomic_order_sequences = (1ULL << 20);
1135         queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
1136         queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
1137 }
1138
1139 static int
1140 otx2_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
1141                      const struct rte_event_queue_conf *queue_conf)
1142 {
1143         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1144         struct otx2_mbox *mbox = dev->mbox;
1145         struct sso_grp_priority *req;
1146         int rc;
1147
1148         sso_func_trace("Queue=%d prio=%d", queue_id, queue_conf->priority);
1149
1150         req = otx2_mbox_alloc_msg_sso_grp_set_priority(dev->mbox);
1151         req->grp = queue_id;
1152         req->weight = 0xFF;
1153         req->affinity = 0xFF;
1154         /* Normalize <0-255> to <0-7> */
1155         req->priority = queue_conf->priority / 32;
1156
1157         rc = otx2_mbox_process(mbox);
1158         if (rc < 0) {
1159                 otx2_err("Failed to set priority queue=%d", queue_id);
1160                 return rc;
1161         }
1162
1163         return 0;
1164 }
1165
1166 static void
1167 otx2_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
1168                        struct rte_event_port_conf *port_conf)
1169 {
1170         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1171
1172         RTE_SET_USED(port_id);
1173         port_conf->new_event_threshold = dev->max_num_events;
1174         port_conf->dequeue_depth = 1;
1175         port_conf->enqueue_depth = 1;
1176 }
1177
1178 static int
1179 otx2_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
1180                     const struct rte_event_port_conf *port_conf)
1181 {
1182         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1183         uintptr_t grps_base[OTX2_SSO_MAX_VHGRP] = {0};
1184         uint64_t val;
1185         uint16_t q;
1186
1187         sso_func_trace("Port=%d", port_id);
1188         RTE_SET_USED(port_conf);
1189
1190         if (event_dev->data->ports[port_id] == NULL) {
1191                 otx2_err("Invalid port Id %d", port_id);
1192                 return -EINVAL;
1193         }
1194
1195         for (q = 0; q < dev->nb_event_queues; q++) {
1196                 grps_base[q] = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | q << 12);
1197                 if (grps_base[q] == 0) {
1198                         otx2_err("Failed to get grp[%d] base addr", q);
1199                         return -EINVAL;
1200                 }
1201         }
1202
1203         /* Set get_work timeout for HWS */
1204         val = NSEC2USEC(dev->deq_tmo_ns) - 1;
1205
1206         if (dev->dual_ws) {
1207                 struct otx2_ssogws_dual *ws = event_dev->data->ports[port_id];
1208
1209                 rte_memcpy(ws->grps_base, grps_base,
1210                            sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
1211                 ws->fc_mem = dev->fc_mem;
1212                 ws->xaq_lmt = dev->xaq_lmt;
1213                 ws->tstamp = dev->tstamp;
1214                 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
1215                              ws->ws_state[0].getwrk_op) + SSOW_LF_GWS_NW_TIM);
1216                 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
1217                              ws->ws_state[1].getwrk_op) + SSOW_LF_GWS_NW_TIM);
1218         } else {
1219                 struct otx2_ssogws *ws = event_dev->data->ports[port_id];
1220                 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
1221
1222                 rte_memcpy(ws->grps_base, grps_base,
1223                            sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
1224                 ws->fc_mem = dev->fc_mem;
1225                 ws->xaq_lmt = dev->xaq_lmt;
1226                 ws->tstamp = dev->tstamp;
1227                 otx2_write64(val, base + SSOW_LF_GWS_NW_TIM);
1228         }
1229
1230         otx2_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]);
1231
1232         return 0;
1233 }
1234
1235 static int
1236 otx2_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,
1237                        uint64_t *tmo_ticks)
1238 {
1239         RTE_SET_USED(event_dev);
1240         *tmo_ticks = NSEC2TICK(ns, rte_get_timer_hz());
1241
1242         return 0;
1243 }
1244
1245 static void
1246 ssogws_dump(struct otx2_ssogws *ws, FILE *f)
1247 {
1248         uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
1249
1250         fprintf(f, "SSOW_LF_GWS Base addr   0x%" PRIx64 "\n", (uint64_t)base);
1251         fprintf(f, "SSOW_LF_GWS_LINKS       0x%" PRIx64 "\n",
1252                 otx2_read64(base + SSOW_LF_GWS_LINKS));
1253         fprintf(f, "SSOW_LF_GWS_PENDWQP     0x%" PRIx64 "\n",
1254                 otx2_read64(base + SSOW_LF_GWS_PENDWQP));
1255         fprintf(f, "SSOW_LF_GWS_PENDSTATE   0x%" PRIx64 "\n",
1256                 otx2_read64(base + SSOW_LF_GWS_PENDSTATE));
1257         fprintf(f, "SSOW_LF_GWS_NW_TIM      0x%" PRIx64 "\n",
1258                 otx2_read64(base + SSOW_LF_GWS_NW_TIM));
1259         fprintf(f, "SSOW_LF_GWS_TAG         0x%" PRIx64 "\n",
1260                 otx2_read64(base + SSOW_LF_GWS_TAG));
1261         fprintf(f, "SSOW_LF_GWS_WQP         0x%" PRIx64 "\n",
1262                 otx2_read64(base + SSOW_LF_GWS_TAG));
1263         fprintf(f, "SSOW_LF_GWS_SWTP        0x%" PRIx64 "\n",
1264                 otx2_read64(base + SSOW_LF_GWS_SWTP));
1265         fprintf(f, "SSOW_LF_GWS_PENDTAG     0x%" PRIx64 "\n",
1266                 otx2_read64(base + SSOW_LF_GWS_PENDTAG));
1267 }
1268
1269 static void
1270 ssoggrp_dump(uintptr_t base, FILE *f)
1271 {
1272         fprintf(f, "SSO_LF_GGRP Base addr   0x%" PRIx64 "\n", (uint64_t)base);
1273         fprintf(f, "SSO_LF_GGRP_QCTL        0x%" PRIx64 "\n",
1274                 otx2_read64(base + SSO_LF_GGRP_QCTL));
1275         fprintf(f, "SSO_LF_GGRP_XAQ_CNT     0x%" PRIx64 "\n",
1276                 otx2_read64(base + SSO_LF_GGRP_XAQ_CNT));
1277         fprintf(f, "SSO_LF_GGRP_INT_THR     0x%" PRIx64 "\n",
1278                 otx2_read64(base + SSO_LF_GGRP_INT_THR));
1279         fprintf(f, "SSO_LF_GGRP_INT_CNT     0x%" PRIX64 "\n",
1280                 otx2_read64(base + SSO_LF_GGRP_INT_CNT));
1281         fprintf(f, "SSO_LF_GGRP_AQ_CNT      0x%" PRIX64 "\n",
1282                 otx2_read64(base + SSO_LF_GGRP_AQ_CNT));
1283         fprintf(f, "SSO_LF_GGRP_AQ_THR      0x%" PRIX64 "\n",
1284                 otx2_read64(base + SSO_LF_GGRP_AQ_THR));
1285         fprintf(f, "SSO_LF_GGRP_MISC_CNT    0x%" PRIx64 "\n",
1286                 otx2_read64(base + SSO_LF_GGRP_MISC_CNT));
1287 }
1288
1289 static void
1290 otx2_sso_dump(struct rte_eventdev *event_dev, FILE *f)
1291 {
1292         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1293         uint8_t queue;
1294         uint8_t port;
1295
1296         fprintf(f, "[%s] SSO running in [%s] mode\n", __func__, dev->dual_ws ?
1297                 "dual_ws" : "single_ws");
1298         /* Dump SSOW registers */
1299         for (port = 0; port < dev->nb_event_ports; port++) {
1300                 if (dev->dual_ws) {
1301                         struct otx2_ssogws_dual *ws =
1302                                 event_dev->data->ports[port];
1303
1304                         fprintf(f, "[%s] SSO dual workslot[%d] vws[%d] dump\n",
1305                                 __func__, port, 0);
1306                         ssogws_dump((struct otx2_ssogws *)&ws->ws_state[0], f);
1307                         fprintf(f, "[%s]SSO dual workslot[%d] vws[%d] dump\n",
1308                                 __func__, port, 1);
1309                         ssogws_dump((struct otx2_ssogws *)&ws->ws_state[1], f);
1310                 } else {
1311                         fprintf(f, "[%s]SSO single workslot[%d] dump\n",
1312                                 __func__, port);
1313                         ssogws_dump(event_dev->data->ports[port], f);
1314                 }
1315         }
1316
1317         /* Dump SSO registers */
1318         for (queue = 0; queue < dev->nb_event_queues; queue++) {
1319                 fprintf(f, "[%s]SSO group[%d] dump\n", __func__, queue);
1320                 if (dev->dual_ws) {
1321                         struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
1322                         ssoggrp_dump(ws->grps_base[queue], f);
1323                 } else {
1324                         struct otx2_ssogws *ws = event_dev->data->ports[0];
1325                         ssoggrp_dump(ws->grps_base[queue], f);
1326                 }
1327         }
1328 }
1329
1330 static void
1331 otx2_handle_event(void *arg, struct rte_event event)
1332 {
1333         struct rte_eventdev *event_dev = arg;
1334
1335         if (event_dev->dev_ops->dev_stop_flush != NULL)
1336                 event_dev->dev_ops->dev_stop_flush(event_dev->data->dev_id,
1337                                 event, event_dev->data->dev_stop_flush_arg);
1338 }
1339
1340 static void
1341 sso_qos_cfg(struct rte_eventdev *event_dev)
1342 {
1343         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1344         struct sso_grp_qos_cfg *req;
1345         uint16_t i;
1346
1347         for (i = 0; i < dev->qos_queue_cnt; i++) {
1348                 uint8_t xaq_prcnt = dev->qos_parse_data[i].xaq_prcnt;
1349                 uint8_t iaq_prcnt = dev->qos_parse_data[i].iaq_prcnt;
1350                 uint8_t taq_prcnt = dev->qos_parse_data[i].taq_prcnt;
1351
1352                 if (dev->qos_parse_data[i].queue >= dev->nb_event_queues)
1353                         continue;
1354
1355                 req = otx2_mbox_alloc_msg_sso_grp_qos_config(dev->mbox);
1356                 req->xaq_limit = (dev->nb_xaq_cfg *
1357                                   (xaq_prcnt ? xaq_prcnt : 100)) / 100;
1358                 req->taq_thr = (SSO_HWGRP_IAQ_MAX_THR_MASK *
1359                                 (iaq_prcnt ? iaq_prcnt : 100)) / 100;
1360                 req->iaq_thr = (SSO_HWGRP_TAQ_MAX_THR_MASK *
1361                                 (taq_prcnt ? taq_prcnt : 100)) / 100;
1362         }
1363
1364         if (dev->qos_queue_cnt)
1365                 otx2_mbox_process(dev->mbox);
1366 }
1367
1368 static void
1369 sso_cleanup(struct rte_eventdev *event_dev, uint8_t enable)
1370 {
1371         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1372         uint16_t i;
1373
1374         for (i = 0; i < dev->nb_event_ports; i++) {
1375                 if (dev->dual_ws) {
1376                         struct otx2_ssogws_dual *ws;
1377
1378                         ws = event_dev->data->ports[i];
1379                         ssogws_reset((struct otx2_ssogws *)&ws->ws_state[0]);
1380                         ssogws_reset((struct otx2_ssogws *)&ws->ws_state[1]);
1381                         ws->swtag_req = 0;
1382                         ws->vws = 0;
1383                         ws->ws_state[0].cur_grp = 0;
1384                         ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
1385                         ws->ws_state[1].cur_grp = 0;
1386                         ws->ws_state[1].cur_tt = SSO_SYNC_EMPTY;
1387                 } else {
1388                         struct otx2_ssogws *ws;
1389
1390                         ws = event_dev->data->ports[i];
1391                         ssogws_reset(ws);
1392                         ws->swtag_req = 0;
1393                         ws->cur_grp = 0;
1394                         ws->cur_tt = SSO_SYNC_EMPTY;
1395                 }
1396         }
1397
1398         rte_mb();
1399         if (dev->dual_ws) {
1400                 struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
1401                 struct otx2_ssogws temp_ws;
1402
1403                 memcpy(&temp_ws, &ws->ws_state[0],
1404                        sizeof(struct otx2_ssogws_state));
1405                 for (i = 0; i < dev->nb_event_queues; i++) {
1406                         /* Consume all the events through HWS0 */
1407                         ssogws_flush_events(&temp_ws, i, ws->grps_base[i],
1408                                             otx2_handle_event, event_dev);
1409                         /* Enable/Disable SSO GGRP */
1410                         otx2_write64(enable, ws->grps_base[i] +
1411                                      SSO_LF_GGRP_QCTL);
1412                 }
1413                 ws->ws_state[0].cur_grp = 0;
1414                 ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
1415         } else {
1416                 struct otx2_ssogws *ws = event_dev->data->ports[0];
1417
1418                 for (i = 0; i < dev->nb_event_queues; i++) {
1419                         /* Consume all the events through HWS0 */
1420                         ssogws_flush_events(ws, i, ws->grps_base[i],
1421                                             otx2_handle_event, event_dev);
1422                         /* Enable/Disable SSO GGRP */
1423                         otx2_write64(enable, ws->grps_base[i] +
1424                                      SSO_LF_GGRP_QCTL);
1425                 }
1426                 ws->cur_grp = 0;
1427                 ws->cur_tt = SSO_SYNC_EMPTY;
1428         }
1429
1430         /* reset SSO GWS cache */
1431         otx2_mbox_alloc_msg_sso_ws_cache_inv(dev->mbox);
1432         otx2_mbox_process(dev->mbox);
1433 }
1434
1435 int
1436 sso_xae_reconfigure(struct rte_eventdev *event_dev)
1437 {
1438         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1439         struct rte_mempool *prev_xaq_pool;
1440         int rc = 0;
1441
1442         if (event_dev->data->dev_started)
1443                 sso_cleanup(event_dev, 0);
1444
1445         prev_xaq_pool = dev->xaq_pool;
1446         dev->xaq_pool = NULL;
1447         rc = sso_xaq_allocate(dev);
1448         if (rc < 0) {
1449                 otx2_err("Failed to alloc xaq pool %d", rc);
1450                 rte_mempool_free(prev_xaq_pool);
1451                 return rc;
1452         }
1453         rc = sso_ggrp_alloc_xaq(dev);
1454         if (rc < 0) {
1455                 otx2_err("Failed to alloc xaq to ggrp %d", rc);
1456                 rte_mempool_free(prev_xaq_pool);
1457                 return rc;
1458         }
1459
1460         rte_mempool_free(prev_xaq_pool);
1461         rte_mb();
1462         if (event_dev->data->dev_started)
1463                 sso_cleanup(event_dev, 1);
1464
1465         return 0;
1466 }
1467
1468 static int
1469 otx2_sso_start(struct rte_eventdev *event_dev)
1470 {
1471         sso_func_trace();
1472         sso_qos_cfg(event_dev);
1473         sso_cleanup(event_dev, 1);
1474         sso_fastpath_fns_set(event_dev);
1475
1476         return 0;
1477 }
1478
1479 static void
1480 otx2_sso_stop(struct rte_eventdev *event_dev)
1481 {
1482         sso_func_trace();
1483         sso_cleanup(event_dev, 0);
1484         rte_mb();
1485 }
1486
1487 static int
1488 otx2_sso_close(struct rte_eventdev *event_dev)
1489 {
1490         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1491         uint8_t all_queues[RTE_EVENT_MAX_QUEUES_PER_DEV];
1492         uint16_t i;
1493
1494         if (!dev->configured)
1495                 return 0;
1496
1497         sso_unregister_irqs(event_dev);
1498
1499         for (i = 0; i < dev->nb_event_queues; i++)
1500                 all_queues[i] = i;
1501
1502         for (i = 0; i < dev->nb_event_ports; i++)
1503                 otx2_sso_port_unlink(event_dev, event_dev->data->ports[i],
1504                                      all_queues, dev->nb_event_queues);
1505
1506         sso_lf_teardown(dev, SSO_LF_GGRP);
1507         sso_lf_teardown(dev, SSO_LF_GWS);
1508         dev->nb_event_ports = 0;
1509         dev->nb_event_queues = 0;
1510         rte_mempool_free(dev->xaq_pool);
1511         rte_memzone_free(rte_memzone_lookup(OTX2_SSO_FC_NAME));
1512
1513         return 0;
1514 }
1515
1516 /* Initialize and register event driver with DPDK Application */
1517 static struct rte_eventdev_ops otx2_sso_ops = {
1518         .dev_infos_get    = otx2_sso_info_get,
1519         .dev_configure    = otx2_sso_configure,
1520         .queue_def_conf   = otx2_sso_queue_def_conf,
1521         .queue_setup      = otx2_sso_queue_setup,
1522         .queue_release    = otx2_sso_queue_release,
1523         .port_def_conf    = otx2_sso_port_def_conf,
1524         .port_setup       = otx2_sso_port_setup,
1525         .port_release     = otx2_sso_port_release,
1526         .port_link        = otx2_sso_port_link,
1527         .port_unlink      = otx2_sso_port_unlink,
1528         .timeout_ticks    = otx2_sso_timeout_ticks,
1529
1530         .eth_rx_adapter_caps_get  = otx2_sso_rx_adapter_caps_get,
1531         .eth_rx_adapter_queue_add = otx2_sso_rx_adapter_queue_add,
1532         .eth_rx_adapter_queue_del = otx2_sso_rx_adapter_queue_del,
1533         .eth_rx_adapter_start = otx2_sso_rx_adapter_start,
1534         .eth_rx_adapter_stop = otx2_sso_rx_adapter_stop,
1535
1536         .eth_tx_adapter_caps_get = otx2_sso_tx_adapter_caps_get,
1537         .eth_tx_adapter_queue_add = otx2_sso_tx_adapter_queue_add,
1538         .eth_tx_adapter_queue_del = otx2_sso_tx_adapter_queue_del,
1539
1540         .timer_adapter_caps_get = otx2_tim_caps_get,
1541
1542         .xstats_get       = otx2_sso_xstats_get,
1543         .xstats_reset     = otx2_sso_xstats_reset,
1544         .xstats_get_names = otx2_sso_xstats_get_names,
1545
1546         .dump             = otx2_sso_dump,
1547         .dev_start        = otx2_sso_start,
1548         .dev_stop         = otx2_sso_stop,
1549         .dev_close        = otx2_sso_close,
1550         .dev_selftest     = otx2_sso_selftest,
1551 };
1552
1553 #define OTX2_SSO_XAE_CNT        "xae_cnt"
1554 #define OTX2_SSO_SINGLE_WS      "single_ws"
1555 #define OTX2_SSO_GGRP_QOS       "qos"
1556 #define OTX2_SSO_SELFTEST       "selftest"
1557
1558 static void
1559 parse_queue_param(char *value, void *opaque)
1560 {
1561         struct otx2_sso_qos queue_qos = {0};
1562         uint8_t *val = (uint8_t *)&queue_qos;
1563         struct otx2_sso_evdev *dev = opaque;
1564         char *tok = strtok(value, "-");
1565         struct otx2_sso_qos *old_ptr;
1566
1567         if (!strlen(value))
1568                 return;
1569
1570         while (tok != NULL) {
1571                 *val = atoi(tok);
1572                 tok = strtok(NULL, "-");
1573                 val++;
1574         }
1575
1576         if (val != (&queue_qos.iaq_prcnt + 1)) {
1577                 otx2_err("Invalid QoS parameter expected [Qx-XAQ-TAQ-IAQ]");
1578                 return;
1579         }
1580
1581         dev->qos_queue_cnt++;
1582         old_ptr = dev->qos_parse_data;
1583         dev->qos_parse_data = rte_realloc(dev->qos_parse_data,
1584                                           sizeof(struct otx2_sso_qos) *
1585                                           dev->qos_queue_cnt, 0);
1586         if (dev->qos_parse_data == NULL) {
1587                 dev->qos_parse_data = old_ptr;
1588                 dev->qos_queue_cnt--;
1589                 return;
1590         }
1591         dev->qos_parse_data[dev->qos_queue_cnt - 1] = queue_qos;
1592 }
1593
1594 static void
1595 parse_qos_list(const char *value, void *opaque)
1596 {
1597         char *s = strdup(value);
1598         char *start = NULL;
1599         char *end = NULL;
1600         char *f = s;
1601
1602         while (*s) {
1603                 if (*s == '[')
1604                         start = s;
1605                 else if (*s == ']')
1606                         end = s;
1607
1608                 if (start && start < end) {
1609                         *end = 0;
1610                         parse_queue_param(start + 1, opaque);
1611                         s = end;
1612                         start = end;
1613                 }
1614                 s++;
1615         }
1616
1617         free(f);
1618 }
1619
1620 static int
1621 parse_sso_kvargs_dict(const char *key, const char *value, void *opaque)
1622 {
1623         RTE_SET_USED(key);
1624
1625         /* Dict format [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] use '-' cause ','
1626          * isn't allowed. Everything is expressed in percentages, 0 represents
1627          * default.
1628          */
1629         parse_qos_list(value, opaque);
1630
1631         return 0;
1632 }
1633
1634 static void
1635 sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)
1636 {
1637         struct rte_kvargs *kvlist;
1638         uint8_t single_ws = 0;
1639
1640         if (devargs == NULL)
1641                 return;
1642         kvlist = rte_kvargs_parse(devargs->args, NULL);
1643         if (kvlist == NULL)
1644                 return;
1645
1646         rte_kvargs_process(kvlist, OTX2_SSO_SELFTEST, &parse_kvargs_flag,
1647                            &dev->selftest);
1648         rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value,
1649                            &dev->xae_cnt);
1650         rte_kvargs_process(kvlist, OTX2_SSO_SINGLE_WS, &parse_kvargs_flag,
1651                            &single_ws);
1652         rte_kvargs_process(kvlist, OTX2_SSO_GGRP_QOS, &parse_sso_kvargs_dict,
1653                            dev);
1654
1655         dev->dual_ws = !single_ws;
1656         rte_kvargs_free(kvlist);
1657 }
1658
1659 static int
1660 otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1661 {
1662         return rte_event_pmd_pci_probe(pci_drv, pci_dev,
1663                                        sizeof(struct otx2_sso_evdev),
1664                                        otx2_sso_init);
1665 }
1666
1667 static int
1668 otx2_sso_remove(struct rte_pci_device *pci_dev)
1669 {
1670         return rte_event_pmd_pci_remove(pci_dev, otx2_sso_fini);
1671 }
1672
1673 static const struct rte_pci_id pci_sso_map[] = {
1674         {
1675                 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
1676                                PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF)
1677         },
1678         {
1679                 .vendor_id = 0,
1680         },
1681 };
1682
1683 static struct rte_pci_driver pci_sso = {
1684         .id_table = pci_sso_map,
1685         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
1686         .probe = otx2_sso_probe,
1687         .remove = otx2_sso_remove,
1688 };
1689
1690 int
1691 otx2_sso_init(struct rte_eventdev *event_dev)
1692 {
1693         struct free_rsrcs_rsp *rsrc_cnt;
1694         struct rte_pci_device *pci_dev;
1695         struct otx2_sso_evdev *dev;
1696         int rc;
1697
1698         event_dev->dev_ops = &otx2_sso_ops;
1699         /* For secondary processes, the primary has done all the work */
1700         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1701                 sso_fastpath_fns_set(event_dev);
1702                 return 0;
1703         }
1704
1705         dev = sso_pmd_priv(event_dev);
1706
1707         pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1708
1709         /* Initialize the base otx2_dev object */
1710         rc = otx2_dev_init(pci_dev, dev);
1711         if (rc < 0) {
1712                 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
1713                 goto error;
1714         }
1715
1716         /* Get SSO and SSOW MSIX rsrc cnt */
1717         otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
1718         rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);
1719         if (rc < 0) {
1720                 otx2_err("Unable to get free rsrc count");
1721                 goto otx2_dev_uninit;
1722         }
1723         otx2_sso_dbg("SSO %d SSOW %d NPA %d provisioned", rsrc_cnt->sso,
1724                      rsrc_cnt->ssow, rsrc_cnt->npa);
1725
1726         dev->max_event_ports = RTE_MIN(rsrc_cnt->ssow, OTX2_SSO_MAX_VHWS);
1727         dev->max_event_queues = RTE_MIN(rsrc_cnt->sso, OTX2_SSO_MAX_VHGRP);
1728         /* Grab the NPA LF if required */
1729         rc = otx2_npa_lf_init(pci_dev, dev);
1730         if (rc < 0) {
1731                 otx2_err("Unable to init NPA lf. It might not be provisioned");
1732                 goto otx2_dev_uninit;
1733         }
1734
1735         dev->drv_inited = true;
1736         dev->is_timeout_deq = 0;
1737         dev->min_dequeue_timeout_ns = USEC2NSEC(1);
1738         dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);
1739         dev->max_num_events = -1;
1740         dev->nb_event_queues = 0;
1741         dev->nb_event_ports = 0;
1742
1743         if (!dev->max_event_ports || !dev->max_event_queues) {
1744                 otx2_err("Not enough eventdev resource queues=%d ports=%d",
1745                          dev->max_event_queues, dev->max_event_ports);
1746                 rc = -ENODEV;
1747                 goto otx2_npa_lf_uninit;
1748         }
1749
1750         dev->dual_ws = 1;
1751         sso_parse_devargs(dev, pci_dev->device.devargs);
1752         if (dev->dual_ws) {
1753                 otx2_sso_dbg("Using dual workslot mode");
1754                 dev->max_event_ports = dev->max_event_ports / 2;
1755         } else {
1756                 otx2_sso_dbg("Using single workslot mode");
1757         }
1758
1759         otx2_sso_pf_func_set(dev->pf_func);
1760         otx2_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
1761                      event_dev->data->name, dev->max_event_queues,
1762                      dev->max_event_ports);
1763         if (dev->selftest) {
1764                 event_dev->dev->driver = &pci_sso.driver;
1765                 event_dev->dev_ops->dev_selftest();
1766         }
1767
1768         otx2_tim_init(pci_dev, (struct otx2_dev *)dev);
1769
1770         return 0;
1771
1772 otx2_npa_lf_uninit:
1773         otx2_npa_lf_fini();
1774 otx2_dev_uninit:
1775         otx2_dev_fini(pci_dev, dev);
1776 error:
1777         return rc;
1778 }
1779
1780 int
1781 otx2_sso_fini(struct rte_eventdev *event_dev)
1782 {
1783         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1784         struct rte_pci_device *pci_dev;
1785
1786         /* For secondary processes, nothing to be done */
1787         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1788                 return 0;
1789
1790         pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1791
1792         if (!dev->drv_inited)
1793                 goto dev_fini;
1794
1795         dev->drv_inited = false;
1796         otx2_npa_lf_fini();
1797
1798 dev_fini:
1799         if (otx2_npa_lf_active(dev)) {
1800                 otx2_info("Common resource in use by other devices");
1801                 return -EAGAIN;
1802         }
1803
1804         otx2_tim_fini();
1805         otx2_dev_fini(pci_dev, dev);
1806
1807         return 0;
1808 }
1809
1810 RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);
1811 RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);
1812 RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, "vfio-pci");
1813 RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "=<int>"
1814                               OTX2_SSO_SINGLE_WS "=1"
1815                               OTX2_SSO_GGRP_QOS "=<string>"
1816                               OTX2_SSO_SELFTEST "=1");