1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef __OTX2_TIM_EVDEV_H__
6 #define __OTX2_TIM_EVDEV_H__
8 #include <rte_event_timer_adapter.h>
9 #include <rte_event_timer_adapter_pmd.h>
13 #define OTX2_TIM_EVDEV_NAME otx2_tim_eventdev
15 #define otx2_tim_func_trace otx2_tim_dbg
17 #define TIM_LF_RING_AURA (0x0)
18 #define TIM_LF_RING_BASE (0x130)
20 #define OTX2_MAX_TIM_RINGS (256)
21 #define OTX2_TIM_MAX_BUCKETS (0xFFFFF)
22 #define OTX2_TIM_RING_DEF_CHUNK_SZ (4096)
23 #define OTX2_TIM_CHUNK_ALIGNMENT (16)
24 #define OTX2_TIM_NB_CHUNK_SLOTS(sz) (((sz) / OTX2_TIM_CHUNK_ALIGNMENT) - 1)
25 #define OTX2_TIM_MIN_CHUNK_SLOTS (0x1)
26 #define OTX2_TIM_MAX_CHUNK_SLOTS (0x1FFE)
27 #define OTX2_TIM_MIN_TMO_TKS (256)
29 enum otx2_tim_clk_src {
30 OTX2_TIM_CLK_SRC_10NS = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,
31 OTX2_TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,
32 OTX2_TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1,
33 OTX2_TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2,
47 int16_t chunk_remainder;
50 uint64_t current_chunk;
52 } __rte_packed __rte_aligned(32);
54 struct otx2_tim_evdev {
55 struct rte_pci_device *pci_dev;
56 struct rte_eventdev *event_dev;
57 struct otx2_mbox *mbox;
66 struct otx2_tim_ring {
68 uint16_t nb_chunk_slots;
70 struct otx2_tim_bkt *bkt;
71 struct rte_mempool *chunk_pool;
83 uint64_t tenns_clk_freq;
84 enum otx2_tim_clk_src clk_src;
85 } __rte_cache_aligned;
87 static inline struct otx2_tim_evdev *
90 const struct rte_memzone *mz;
92 mz = rte_memzone_lookup(RTE_STR(OTX2_TIM_EVDEV_NAME));
99 int otx2_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags,
101 const struct rte_event_timer_adapter_ops **ops);
103 void otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev);
104 void otx2_tim_fini(void);
106 #endif /* __OTX2_TIM_EVDEV_H__ */