4 * Copyright (C) Cavium Inc. 2017. All Right reserved.
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7 * modification, are permitted provided that the following conditions
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11 * notice, this list of conditions and the following disclaimer.
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13 * notice, this list of conditions and the following disclaimer in
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16 * * Neither the name of Cavium networks nor the names of its
17 * contributors may be used to endorse or promote products derived
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20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <rte_atomic.h>
45 #include <rte_errno.h>
46 #include <rte_memory.h>
47 #include <rte_malloc.h>
48 #include <rte_spinlock.h>
50 #include "octeontx_fpavf.h"
53 void *pool_stack_base;
55 uint64_t stack_ln_ptr;
57 uint16_t vf_id; /* gpool_id */
58 uint16_t sz128; /* Block size in cache lines */
62 struct octeontx_fpadev {
64 uint8_t total_gpool_cnt;
65 struct fpavf_res pool[FPA_VF_MAX];
68 static struct octeontx_fpadev fpadev;
71 octeontx_fpavf_setup(void)
74 static bool init_once;
77 rte_spinlock_init(&fpadev.lock);
78 fpadev.total_gpool_cnt = 0;
80 for (i = 0; i < FPA_VF_MAX; i++) {
82 fpadev.pool[i].domain_id = ~0;
83 fpadev.pool[i].stack_ln_ptr = 0;
84 fpadev.pool[i].sz128 = 0;
85 fpadev.pool[i].bar0 = NULL;
86 fpadev.pool[i].pool_stack_base = NULL;
87 fpadev.pool[i].is_inuse = false;
94 octeontx_fpavf_identify(void *bar0)
99 uint64_t stack_ln_ptr;
101 val = fpavf_read64((void *)((uintptr_t)bar0 +
102 FPA_VF_VHAURA_CNT_THRESHOLD(0)));
104 domain_id = (val >> 8) & 0xffff;
105 vf_id = (val >> 24) & 0xffff;
107 stack_ln_ptr = fpavf_read64((void *)((uintptr_t)bar0 +
108 FPA_VF_VHPOOL_THRESHOLD(0)));
109 if (vf_id >= FPA_VF_MAX) {
110 fpavf_log_err("vf_id(%d) greater than max vf (32)\n", vf_id);
114 if (fpadev.pool[vf_id].is_inuse) {
115 fpavf_log_err("vf_id %d is_inuse\n", vf_id);
119 fpadev.pool[vf_id].domain_id = domain_id;
120 fpadev.pool[vf_id].vf_id = vf_id;
121 fpadev.pool[vf_id].bar0 = bar0;
122 fpadev.pool[vf_id].stack_ln_ptr = stack_ln_ptr;
128 /* FPAVF pcie device aka mempool probe */
130 fpavf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
134 struct fpavf_res *fpa;
136 RTE_SET_USED(pci_drv);
139 /* For secondary processes, the primary has done all the work */
140 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
143 if (pci_dev->mem_resource[0].addr == NULL) {
144 fpavf_log_err("Empty bars %p ", pci_dev->mem_resource[0].addr);
147 idreg = pci_dev->mem_resource[0].addr;
149 octeontx_fpavf_setup();
151 res = octeontx_fpavf_identify(idreg);
155 fpa = &fpadev.pool[res];
156 fpadev.total_gpool_cnt++;
159 fpavf_log_dbg("total_fpavfs %d bar0 %p domain %d vf %d stk_ln_ptr 0x%x",
160 fpadev.total_gpool_cnt, fpa->bar0, fpa->domain_id,
161 fpa->vf_id, (unsigned int)fpa->stack_ln_ptr);
166 static const struct rte_pci_id pci_fpavf_map[] = {
168 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
169 PCI_DEVICE_ID_OCTEONTX_FPA_VF)
176 static struct rte_pci_driver pci_fpavf = {
177 .id_table = pci_fpavf_map,
178 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
179 .probe = fpavf_probe,
182 RTE_PMD_REGISTER_PCI(octeontx_fpavf, pci_fpavf);