1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #include "axgbe_ethdev.h"
7 #include "axgbe_common.h"
10 static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev);
11 static int eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev);
12 static void axgbe_dev_interrupt_handler(void *param);
14 /* The set of PCI devices this driver supports */
15 #define AMD_PCI_VENDOR_ID 0x1022
16 #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458
17 #define AMD_PCI_AXGBE_DEVICE_V2B 0x1459
19 int axgbe_logtype_init;
20 int axgbe_logtype_driver;
22 static const struct rte_pci_id pci_id_axgbe_map[] = {
23 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2A)},
24 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2B)},
28 static struct axgbe_version_data axgbe_v2a = {
29 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2,
30 .xpcs_access = AXGBE_XPCS_ACCESS_V2,
32 .tx_max_fifo_size = 229376,
33 .rx_max_fifo_size = 229376,
34 .tx_tstamp_workaround = 1,
39 static struct axgbe_version_data axgbe_v2b = {
40 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2,
41 .xpcs_access = AXGBE_XPCS_ACCESS_V2,
43 .tx_max_fifo_size = 65536,
44 .rx_max_fifo_size = 65536,
45 .tx_tstamp_workaround = 1,
51 * Interrupt handler triggered by NIC for handling
55 * Pointer to interrupt handle.
57 * The address of parameter (struct rte_eth_dev *) regsitered before.
63 axgbe_dev_interrupt_handler(void *param)
65 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
66 struct axgbe_port *pdata = dev->data->dev_private;
68 pdata->phy_if.an_isr(pdata);
70 /* Enable interrupts since disabled after generation*/
71 rte_intr_enable(&pdata->pci_dev->intr_handle);
74 static void axgbe_get_all_hw_features(struct axgbe_port *pdata)
76 unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
77 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
79 mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R);
80 mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R);
81 mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R);
83 memset(hw_feat, 0, sizeof(*hw_feat));
85 hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR);
87 /* Hardware feature register 0 */
88 hw_feat->gmii = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
89 hw_feat->vlhash = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
90 hw_feat->sma = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
91 hw_feat->rwk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
92 hw_feat->mgk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
93 hw_feat->mmc = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
94 hw_feat->aoe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
95 hw_feat->ts = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
96 hw_feat->eee = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
97 hw_feat->tx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
98 hw_feat->rx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
99 hw_feat->addn_mac = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
101 hw_feat->ts_src = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
102 hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
104 /* Hardware feature register 1 */
105 hw_feat->rx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
107 hw_feat->tx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
109 hw_feat->adv_ts_hi = AXGMAC_GET_BITS(mac_hfr1,
110 MAC_HWF1R, ADVTHWORD);
111 hw_feat->dma_width = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
112 hw_feat->dcb = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
113 hw_feat->sph = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
114 hw_feat->tso = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
115 hw_feat->dma_debug = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
116 hw_feat->rss = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
117 hw_feat->tc_cnt = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
118 hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
120 hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
123 /* Hardware feature register 2 */
124 hw_feat->rx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
125 hw_feat->tx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
126 hw_feat->rx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
127 hw_feat->tx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
128 hw_feat->pps_out_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
129 hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R,
132 /* Translate the Hash Table size into actual number */
133 switch (hw_feat->hash_table_size) {
137 hw_feat->hash_table_size = 64;
140 hw_feat->hash_table_size = 128;
143 hw_feat->hash_table_size = 256;
147 /* Translate the address width setting into actual number */
148 switch (hw_feat->dma_width) {
150 hw_feat->dma_width = 32;
153 hw_feat->dma_width = 40;
156 hw_feat->dma_width = 48;
159 hw_feat->dma_width = 32;
162 /* The Queue, Channel and TC counts are zero based so increment them
163 * to get the actual number
167 hw_feat->rx_ch_cnt++;
168 hw_feat->tx_ch_cnt++;
171 /* Translate the fifo sizes into actual numbers */
172 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
173 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
176 static void axgbe_init_all_fptrs(struct axgbe_port *pdata)
178 axgbe_init_function_ptrs_dev(&pdata->hw_if);
179 axgbe_init_function_ptrs_phy(&pdata->phy_if);
180 axgbe_init_function_ptrs_i2c(&pdata->i2c_if);
181 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
184 static void axgbe_set_counts(struct axgbe_port *pdata)
186 /* Set all the function pointers */
187 axgbe_init_all_fptrs(pdata);
189 /* Populate the hardware features */
190 axgbe_get_all_hw_features(pdata);
192 /* Set default max values if not provided */
193 if (!pdata->tx_max_channel_count)
194 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
195 if (!pdata->rx_max_channel_count)
196 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
198 if (!pdata->tx_max_q_count)
199 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
200 if (!pdata->rx_max_q_count)
201 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
203 /* Calculate the number of Tx and Rx rings to be created
204 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
205 * the number of Tx queues to the number of Tx channels
207 * -Rx (DMA) Channels do not map 1-to-1 so use the actual
208 * number of Rx queues or maximum allowed
210 pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt,
211 pdata->tx_max_channel_count);
212 pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count,
213 pdata->tx_max_q_count);
215 pdata->tx_q_count = pdata->tx_ring_count;
217 pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt,
218 pdata->rx_max_channel_count);
220 pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt,
221 pdata->rx_max_q_count);
224 static void axgbe_default_config(struct axgbe_port *pdata)
226 pdata->pblx8 = DMA_PBL_X8_ENABLE;
227 pdata->tx_sf_mode = MTL_TSF_ENABLE;
228 pdata->tx_threshold = MTL_TX_THRESHOLD_64;
229 pdata->tx_pbl = DMA_PBL_32;
230 pdata->tx_osp_mode = DMA_OSP_ENABLE;
231 pdata->rx_sf_mode = MTL_RSF_ENABLE;
232 pdata->rx_threshold = MTL_RX_THRESHOLD_64;
233 pdata->rx_pbl = DMA_PBL_32;
234 pdata->pause_autoneg = 1;
237 pdata->phy_speed = SPEED_UNKNOWN;
238 pdata->power_down = 0;
242 * It returns 0 on success.
245 eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
247 PMD_INIT_FUNC_TRACE();
248 struct axgbe_port *pdata;
249 struct rte_pci_device *pci_dev;
250 uint32_t reg, mac_lo, mac_hi;
254 * For secondary processes, we don't initialise any further as primary
255 * has already done this work.
257 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
260 pdata = (struct axgbe_port *)eth_dev->data->dev_private;
262 axgbe_set_bit(AXGBE_DOWN, &pdata->dev_state);
263 axgbe_set_bit(AXGBE_STOPPED, &pdata->dev_state);
264 pdata->eth_dev = eth_dev;
266 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
267 pdata->pci_dev = pci_dev;
270 (uint64_t)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr;
271 pdata->xprop_regs = pdata->xgmac_regs + AXGBE_MAC_PROP_OFFSET;
272 pdata->xi2c_regs = pdata->xgmac_regs + AXGBE_I2C_CTRL_OFFSET;
273 pdata->xpcs_regs = (uint64_t)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr;
275 /* version specific driver data*/
276 if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A)
277 pdata->vdata = &axgbe_v2a;
279 pdata->vdata = &axgbe_v2b;
281 /* Configure the PCS indirect addressing support */
282 reg = XPCS32_IOREAD(pdata, PCS_V2_WINDOW_DEF);
283 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
284 pdata->xpcs_window <<= 6;
285 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
286 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
287 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
288 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
289 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
291 "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window,
292 pdata->xpcs_window_size, pdata->xpcs_window_mask);
293 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
295 /* Retrieve the MAC address */
296 mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
297 mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
298 pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff;
299 pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff;
300 pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff;
301 pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff;
302 pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff;
303 pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8) & 0xff;
305 eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr",
307 if (!eth_dev->data->mac_addrs) {
309 "Failed to alloc %u bytes needed to store MAC addr tbl",
314 if (!is_valid_assigned_ether_addr(&pdata->mac_addr))
315 eth_random_addr(pdata->mac_addr.addr_bytes);
317 /* Copy the permanent MAC address */
318 ether_addr_copy(&pdata->mac_addr, ð_dev->data->mac_addrs[0]);
321 pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ;
322 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ;
324 /* Set the DMA coherency values */
326 pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN;
327 pdata->arcache = AXGBE_DMA_OS_ARCACHE;
328 pdata->awcache = AXGBE_DMA_OS_AWCACHE;
330 /* Set the maximum channels and queues */
331 reg = XP_IOREAD(pdata, XP_PROP_1);
332 pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA);
333 pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA);
334 pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES);
335 pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES);
337 /* Set the hardware channel and queue counts */
338 axgbe_set_counts(pdata);
340 /* Set the maximum fifo amounts */
341 reg = XP_IOREAD(pdata, XP_PROP_2);
342 pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE);
343 pdata->tx_max_fifo_size *= 16384;
344 pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size,
345 pdata->vdata->tx_max_fifo_size);
346 pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE);
347 pdata->rx_max_fifo_size *= 16384;
348 pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size,
349 pdata->vdata->rx_max_fifo_size);
350 /* Issue software reset to DMA */
351 ret = pdata->hw_if.exit(pdata);
353 PMD_DRV_LOG(ERR, "hw_if->exit EBUSY error\n");
355 /* Set default configuration data */
356 axgbe_default_config(pdata);
358 /* Set default max values if not provided */
359 if (!pdata->tx_max_fifo_size)
360 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
361 if (!pdata->rx_max_fifo_size)
362 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
364 pthread_mutex_init(&pdata->xpcs_mutex, NULL);
365 pthread_mutex_init(&pdata->i2c_mutex, NULL);
366 pthread_mutex_init(&pdata->an_mutex, NULL);
367 pthread_mutex_init(&pdata->phy_mutex, NULL);
369 ret = pdata->phy_if.phy_init(pdata);
371 rte_free(eth_dev->data->mac_addrs);
375 rte_intr_callback_register(&pci_dev->intr_handle,
376 axgbe_dev_interrupt_handler,
378 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
379 eth_dev->data->port_id, pci_dev->id.vendor_id,
380 pci_dev->id.device_id);
386 eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev)
388 struct rte_pci_device *pci_dev;
390 PMD_INIT_FUNC_TRACE();
392 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
395 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
397 rte_free(eth_dev->data->mac_addrs);
398 eth_dev->data->mac_addrs = NULL;
400 /* disable uio intr before callback unregister */
401 rte_intr_disable(&pci_dev->intr_handle);
402 rte_intr_callback_unregister(&pci_dev->intr_handle,
403 axgbe_dev_interrupt_handler,
409 static int eth_axgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
410 struct rte_pci_device *pci_dev)
412 return rte_eth_dev_pci_generic_probe(pci_dev,
413 sizeof(struct axgbe_port), eth_axgbe_dev_init);
416 static int eth_axgbe_pci_remove(struct rte_pci_device *pci_dev)
418 return rte_eth_dev_pci_generic_remove(pci_dev, eth_axgbe_dev_uninit);
421 static struct rte_pci_driver rte_axgbe_pmd = {
422 .id_table = pci_id_axgbe_map,
423 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
424 .probe = eth_axgbe_pci_probe,
425 .remove = eth_axgbe_pci_remove,
428 RTE_PMD_REGISTER_PCI(net_axgbe, rte_axgbe_pmd);
429 RTE_PMD_REGISTER_PCI_TABLE(net_axgbe, pci_id_axgbe_map);
430 RTE_PMD_REGISTER_KMOD_DEP(net_axgbe, "* igb_uio | uio_pci_generic | vfio-pci");
432 RTE_INIT(axgbe_init_log);
436 axgbe_logtype_init = rte_log_register("pmd.net.axgbe.init");
437 if (axgbe_logtype_init >= 0)
438 rte_log_set_level(axgbe_logtype_init, RTE_LOG_NOTICE);
439 axgbe_logtype_driver = rte_log_register("pmd.net.axgbe.driver");
440 if (axgbe_logtype_driver >= 0)
441 rte_log_set_level(axgbe_logtype_driver, RTE_LOG_NOTICE);