drivers/net/axgbe/axgbe_rxtx.c

   1 /*   SPDX-License-Identifier: BSD-3-Clause
   2  *   Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
   3  *   Copyright(c) 2018 Synopsys, Inc. All rights reserved.
   4  */
   5
   6 #include "axgbe_ethdev.h"
   7 #include "axgbe_rxtx.h"
   8 #include "axgbe_phy.h"
   9
  10 #include <rte_time.h>
  11 #include <rte_mempool.h>
  12 #include <rte_mbuf.h>
  13
  14 static void
  15 axgbe_rx_queue_release(struct axgbe_rx_queue *rx_queue)
  16 {
  17         uint16_t i;
  18         struct rte_mbuf **sw_ring;
  19
  20         if (rx_queue) {
  21                 sw_ring = rx_queue->sw_ring;
  22                 if (sw_ring) {
  23                         for (i = 0; i < rx_queue->nb_desc; i++) {
  24                                 if (sw_ring[i])
  25                                         rte_pktmbuf_free(sw_ring[i]);
  26                         }
  27                         rte_free(sw_ring);
  28                 }
  29                 rte_free(rx_queue);
  30         }
  31 }
  32
  33 void axgbe_dev_rx_queue_release(void *rxq)
  34 {
  35         axgbe_rx_queue_release(rxq);
  36 }
  37
  38 int axgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  39                              uint16_t nb_desc, unsigned int socket_id,
  40                              const struct rte_eth_rxconf *rx_conf,
  41                              struct rte_mempool *mp)
  42 {
  43         PMD_INIT_FUNC_TRACE();
  44         uint32_t size;
  45         const struct rte_memzone *dma;
  46         struct axgbe_rx_queue *rxq;
  47         uint32_t rx_desc = nb_desc;
  48         struct axgbe_port *pdata =  dev->data->dev_private;
  49
  50         /*
  51          * validate Rx descriptors count
  52          * should be power of 2 and less than h/w supported
  53          */
  54         if ((!rte_is_power_of_2(rx_desc)) ||
  55             rx_desc > pdata->rx_desc_count)
  56                 return -EINVAL;
  57         /* First allocate the rx queue data structure */
  58         rxq = rte_zmalloc_socket("ethdev RX queue",
  59                                  sizeof(struct axgbe_rx_queue),
  60                                  RTE_CACHE_LINE_SIZE, socket_id);
  61         if (!rxq) {
  62                 PMD_INIT_LOG(ERR, "rte_zmalloc for rxq failed!");
  63                 return -ENOMEM;
  64         }
  65
  66         rxq->cur = 0;
  67         rxq->dirty = 0;
  68         rxq->pdata = pdata;
  69         rxq->mb_pool = mp;
  70         rxq->queue_id = queue_idx;
  71         rxq->port_id = dev->data->port_id;
  72         rxq->nb_desc = rx_desc;
  73         rxq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE +
  74                 (DMA_CH_INC * rxq->queue_id));
  75         rxq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)rxq->dma_regs +
  76                                                   DMA_CH_RDTR_LO);
  77         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
  78                 rxq->crc_len = RTE_ETHER_CRC_LEN;
  79         else
  80                 rxq->crc_len = 0;
  81
  82         /* CRC strip in AXGBE supports per port not per queue */
  83         pdata->crc_strip_enable = (rxq->crc_len == 0) ? 1 : 0;
  84         rxq->free_thresh = rx_conf->rx_free_thresh ?
  85                 rx_conf->rx_free_thresh : AXGBE_RX_FREE_THRESH;
  86         if (rxq->free_thresh >  rxq->nb_desc)
  87                 rxq->free_thresh = rxq->nb_desc >> 3;
  88
  89         /* Allocate RX ring hardware descriptors */
  90         size = rxq->nb_desc * sizeof(union axgbe_rx_desc);
  91         dma = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx, size, 128,
  92                                        socket_id);
  93         if (!dma) {
  94                 PMD_DRV_LOG(ERR, "ring_dma_zone_reserve for rx_ring failed\n");
  95                 axgbe_rx_queue_release(rxq);
  96                 return -ENOMEM;
  97         }
  98         rxq->ring_phys_addr = (uint64_t)dma->phys_addr;
  99         rxq->desc = (volatile union axgbe_rx_desc *)dma->addr;
 100         memset((void *)rxq->desc, 0, size);
 101         /* Allocate software ring */
 102         size = rxq->nb_desc * sizeof(struct rte_mbuf *);
 103         rxq->sw_ring = rte_zmalloc_socket("sw_ring", size,
 104                                           RTE_CACHE_LINE_SIZE,
 105                                           socket_id);
 106         if (!rxq->sw_ring) {
 107                 PMD_DRV_LOG(ERR, "rte_zmalloc for sw_ring failed\n");
 108                 axgbe_rx_queue_release(rxq);
 109                 return -ENOMEM;
 110         }
 111         dev->data->rx_queues[queue_idx] = rxq;
 112         if (!pdata->rx_queues)
 113                 pdata->rx_queues = dev->data->rx_queues;
 114
 115         return 0;
 116 }
 117
 118 static void axgbe_prepare_rx_stop(struct axgbe_port *pdata,
 119                                   unsigned int queue)
 120 {
 121         unsigned int rx_status;
 122         unsigned long rx_timeout;
 123
 124         /* The Rx engine cannot be stopped if it is actively processing
 125          * packets. Wait for the Rx queue to empty the Rx fifo.  Don't
 126          * wait forever though...
 127          */
 128         rx_timeout = rte_get_timer_cycles() + (AXGBE_DMA_STOP_TIMEOUT *
 129                                                rte_get_timer_hz());
 130
 131         while (time_before(rte_get_timer_cycles(), rx_timeout)) {
 132                 rx_status = AXGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR);
 133                 if ((AXGMAC_GET_BITS(rx_status, MTL_Q_RQDR, PRXQ) == 0) &&
 134                     (AXGMAC_GET_BITS(rx_status, MTL_Q_RQDR, RXQSTS) == 0))
 135                         break;
 136
 137                 rte_delay_us(900);
 138         }
 139
 140         if (!time_before(rte_get_timer_cycles(), rx_timeout))
 141                 PMD_DRV_LOG(ERR,
 142                             "timed out waiting for Rx queue %u to empty\n",
 143                             queue);
 144 }
 145
 146 void axgbe_dev_disable_rx(struct rte_eth_dev *dev)
 147 {
 148         struct axgbe_rx_queue *rxq;
 149         struct axgbe_port *pdata = dev->data->dev_private;
 150         unsigned int i;
 151
 152         /* Disable MAC Rx */
 153         AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0);
 154         AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0);
 155         AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0);
 156         AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0);
 157
 158         /* Prepare for Rx DMA channel stop */
 159         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 160                 rxq = dev->data->rx_queues[i];
 161                 axgbe_prepare_rx_stop(pdata, i);
 162         }
 163         /* Disable each Rx queue */
 164         AXGMAC_IOWRITE(pdata, MAC_RQC0R, 0);
 165         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 166                 rxq = dev->data->rx_queues[i];
 167                 /* Disable Rx DMA channel */
 168                 AXGMAC_DMA_IOWRITE_BITS(rxq, DMA_CH_RCR, SR, 0);
 169         }
 170 }
 171
 172 void axgbe_dev_enable_rx(struct rte_eth_dev *dev)
 173 {
 174         struct axgbe_rx_queue *rxq;
 175         struct axgbe_port *pdata = dev->data->dev_private;
 176         unsigned int i;
 177         unsigned int reg_val = 0;
 178
 179         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 180                 rxq = dev->data->rx_queues[i];
 181                 /* Enable Rx DMA channel */
 182                 AXGMAC_DMA_IOWRITE_BITS(rxq, DMA_CH_RCR, SR, 1);
 183         }
 184
 185         reg_val = 0;
 186         for (i = 0; i < pdata->rx_q_count; i++)
 187                 reg_val |= (0x02 << (i << 1));
 188         AXGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
 189
 190         /* Enable MAC Rx */
 191         AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1);
 192         /* Frame is forwarded after stripping CRC to application*/
 193         if (pdata->crc_strip_enable) {
 194                 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1);
 195                 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1);
 196         }
 197         AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1);
 198 }
 199
 200 /* Rx function one to one refresh */
 201 uint16_t
 202 axgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 203                 uint16_t nb_pkts)
 204 {
 205         PMD_INIT_FUNC_TRACE();
 206         uint16_t nb_rx = 0;
 207         struct axgbe_rx_queue *rxq = rx_queue;
 208         volatile union axgbe_rx_desc *desc;
 209         uint64_t old_dirty = rxq->dirty;
 210         struct rte_mbuf *mbuf, *tmbuf;
 211         unsigned int err;
 212         uint32_t error_status;
 213         uint16_t idx, pidx, pkt_len;
 214
 215         idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
 216         while (nb_rx < nb_pkts) {
 217                 if (unlikely(idx == rxq->nb_desc))
 218                         idx = 0;
 219
 220                 desc = &rxq->desc[idx];
 221
 222                 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
 223                         break;
 224                 tmbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
 225                 if (unlikely(!tmbuf)) {
 226                         PMD_DRV_LOG(ERR, "RX mbuf alloc failed port_id = %u"
 227                                     " queue_id = %u\n",
 228                                     (unsigned int)rxq->port_id,
 229                                     (unsigned int)rxq->queue_id);
 230                         rte_eth_devices[
 231                                 rxq->port_id].data->rx_mbuf_alloc_failed++;
 232                         rxq->rx_mbuf_alloc_failed++;
 233                         break;
 234                 }
 235                 pidx = idx + 1;
 236                 if (unlikely(pidx == rxq->nb_desc))
 237                         pidx = 0;
 238
 239                 rte_prefetch0(rxq->sw_ring[pidx]);
 240                 if ((pidx & 0x3) == 0) {
 241                         rte_prefetch0(&rxq->desc[pidx]);
 242                         rte_prefetch0(&rxq->sw_ring[pidx]);
 243                 }
 244
 245                 mbuf = rxq->sw_ring[idx];
 246                 /* Check for any errors and free mbuf*/
 247                 err = AXGMAC_GET_BITS_LE(desc->write.desc3,
 248                                          RX_NORMAL_DESC3, ES);
 249                 error_status = 0;
 250                 if (unlikely(err)) {
 251                         error_status = desc->write.desc3 & AXGBE_ERR_STATUS;
 252                         if ((error_status != AXGBE_L3_CSUM_ERR) &&
 253                             (error_status != AXGBE_L4_CSUM_ERR)) {
 254                                 rxq->errors++;
 255                                 rte_pktmbuf_free(mbuf);
 256                                 goto err_set;
 257                         }
 258                 }
 259                 if (rxq->pdata->rx_csum_enable) {
 260                         mbuf->ol_flags = 0;
 261                         mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
 262                         mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
 263                         if (unlikely(error_status == AXGBE_L3_CSUM_ERR)) {
 264                                 mbuf->ol_flags &= ~PKT_RX_IP_CKSUM_GOOD;
 265                                 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
 266                                 mbuf->ol_flags &= ~PKT_RX_L4_CKSUM_GOOD;
 267                                 mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 268                         } else if (
 269                                 unlikely(error_status == AXGBE_L4_CSUM_ERR)) {
 270                                 mbuf->ol_flags &= ~PKT_RX_L4_CKSUM_GOOD;
 271                                 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
 272                         }
 273                 }
 274                 rte_prefetch1(rte_pktmbuf_mtod(mbuf, void *));
 275                 /* Get the RSS hash */
 276                 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, RSV))
 277                         mbuf->hash.rss = rte_le_to_cpu_32(desc->write.desc1);
 278                 pkt_len = AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3,
 279                                              PL) - rxq->crc_len;
 280                 /* Mbuf populate */
 281                 mbuf->next = NULL;
 282                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 283                 mbuf->nb_segs = 1;
 284                 mbuf->port = rxq->port_id;
 285                 mbuf->pkt_len = pkt_len;
 286                 mbuf->data_len = pkt_len;
 287                 rxq->bytes += pkt_len;
 288                 rx_pkts[nb_rx++] = mbuf;
 289 err_set:
 290                 rxq->cur++;
 291                 rxq->sw_ring[idx++] = tmbuf;
 292                 desc->read.baddr =
 293                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(tmbuf));
 294                 memset((void *)(&desc->read.desc2), 0, 8);
 295                 AXGMAC_SET_BITS_LE(desc->read.desc3, RX_NORMAL_DESC3, OWN, 1);
 296                 rxq->dirty++;
 297         }
 298         rxq->pkts += nb_rx;
 299         if (rxq->dirty != old_dirty) {
 300                 rte_wmb();
 301                 idx = AXGBE_GET_DESC_IDX(rxq, rxq->dirty - 1);
 302                 AXGMAC_DMA_IOWRITE(rxq, DMA_CH_RDTR_LO,
 303                                    low32_value(rxq->ring_phys_addr +
 304                                    (idx * sizeof(union axgbe_rx_desc))));
 305         }
 306
 307         return nb_rx;
 308 }
 309
 310
 311 uint16_t eth_axgbe_recv_scattered_pkts(void *rx_queue,
 312                 struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 313 {
 314         PMD_INIT_FUNC_TRACE();
 315         uint16_t nb_rx = 0;
 316         struct axgbe_rx_queue *rxq = rx_queue;
 317         volatile union axgbe_rx_desc *desc;
 318
 319         uint64_t old_dirty = rxq->dirty;
 320         struct rte_mbuf *first_seg = NULL;
 321         struct rte_mbuf *mbuf, *tmbuf;
 322         unsigned int err;
 323         uint32_t error_status;
 324         uint16_t idx, pidx, data_len = 0, pkt_len = 0;
 325
 326         idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
 327         while (nb_rx < nb_pkts) {
 328                 bool eop = 0;
 329 next_desc:
 330                 if (unlikely(idx == rxq->nb_desc))
 331                         idx = 0;
 332
 333                 desc = &rxq->desc[idx];
 334
 335                 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
 336                         break;
 337
 338                 tmbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
 339                 if (unlikely(!tmbuf)) {
 340                         PMD_DRV_LOG(ERR, "RX mbuf alloc failed port_id = %u"
 341                                     " queue_id = %u\n",
 342                                     (unsigned int)rxq->port_id,
 343                                     (unsigned int)rxq->queue_id);
 344                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
 345                         break;
 346                 }
 347
 348                 pidx = idx + 1;
 349                 if (unlikely(pidx == rxq->nb_desc))
 350                         pidx = 0;
 351
 352                 rte_prefetch0(rxq->sw_ring[pidx]);
 353                 if ((pidx & 0x3) == 0) {
 354                         rte_prefetch0(&rxq->desc[pidx]);
 355                         rte_prefetch0(&rxq->sw_ring[pidx]);
 356                 }
 357
 358                 mbuf = rxq->sw_ring[idx];
 359                 /* Check for any errors and free mbuf*/
 360                 err = AXGMAC_GET_BITS_LE(desc->write.desc3,
 361                                          RX_NORMAL_DESC3, ES);
 362                 error_status = 0;
 363                 if (unlikely(err)) {
 364                         error_status = desc->write.desc3 & AXGBE_ERR_STATUS;
 365                         if ((error_status != AXGBE_L3_CSUM_ERR)
 366                                         && (error_status != AXGBE_L4_CSUM_ERR)) {
 367                                 rxq->errors++;
 368                                 rte_pktmbuf_free(mbuf);
 369                                 goto err_set;
 370                         }
 371                 }
 372                 rte_prefetch1(rte_pktmbuf_mtod(mbuf, void *));
 373
 374                 if (!AXGMAC_GET_BITS_LE(desc->write.desc3,
 375                                         RX_NORMAL_DESC3, LD)) {
 376                         eop = 0;
 377                         pkt_len = rxq->buf_size;
 378                         data_len = pkt_len;
 379                 } else {
 380                         eop = 1;
 381                         pkt_len = AXGMAC_GET_BITS_LE(desc->write.desc3,
 382                                         RX_NORMAL_DESC3, PL);
 383                         data_len = pkt_len - rxq->crc_len;
 384                 }
 385
 386                 if (first_seg != NULL) {
 387                         if (rte_pktmbuf_chain(first_seg, mbuf) != 0)
 388                                 rte_mempool_put(rxq->mb_pool,
 389                                                 first_seg);
 390                 } else {
 391                         first_seg = mbuf;
 392                 }
 393
 394                 /* Get the RSS hash */
 395                 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, RSV))
 396                         mbuf->hash.rss = rte_le_to_cpu_32(desc->write.desc1);
 397
 398                 /* Mbuf populate */
 399                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 400                 mbuf->data_len = data_len;
 401
 402 err_set:
 403                 rxq->cur++;
 404                 rxq->sw_ring[idx++] = tmbuf;
 405                 desc->read.baddr =
 406                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(tmbuf));
 407                 memset((void *)(&desc->read.desc2), 0, 8);
 408                 AXGMAC_SET_BITS_LE(desc->read.desc3, RX_NORMAL_DESC3, OWN, 1);
 409                 rxq->dirty++;
 410
 411                 if (!eop) {
 412                         rte_pktmbuf_free(mbuf);
 413                         goto next_desc;
 414                 }
 415
 416                 first_seg->pkt_len = pkt_len;
 417                 rxq->bytes += pkt_len;
 418                 mbuf->next = NULL;
 419
 420                 first_seg->port = rxq->port_id;
 421                 if (rxq->pdata->rx_csum_enable) {
 422                         mbuf->ol_flags = 0;
 423                         mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
 424                         mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
 425                         if (unlikely(error_status == AXGBE_L3_CSUM_ERR)) {
 426                                 mbuf->ol_flags &= ~PKT_RX_IP_CKSUM_GOOD;
 427                                 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
 428                                 mbuf->ol_flags &= ~PKT_RX_L4_CKSUM_GOOD;
 429                                 mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 430                         } else if (unlikely(error_status
 431                                                 == AXGBE_L4_CSUM_ERR)) {
 432                                 mbuf->ol_flags &= ~PKT_RX_L4_CKSUM_GOOD;
 433                                 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
 434                         }
 435                 }
 436
 437                 rx_pkts[nb_rx++] = first_seg;
 438
 439                  /* Setup receipt context for a new packet.*/
 440                 first_seg = NULL;
 441         }
 442
 443         /* Save receive context.*/
 444         rxq->pkts += nb_rx;
 445
 446         if (rxq->dirty != old_dirty) {
 447                 rte_wmb();
 448                 idx = AXGBE_GET_DESC_IDX(rxq, rxq->dirty - 1);
 449                 AXGMAC_DMA_IOWRITE(rxq, DMA_CH_RDTR_LO,
 450                                    low32_value(rxq->ring_phys_addr +
 451                                    (idx * sizeof(union axgbe_rx_desc))));
 452         }
 453         return nb_rx;
 454 }
 455
 456 /* Tx Apis */
 457 static void axgbe_tx_queue_release(struct axgbe_tx_queue *tx_queue)
 458 {
 459         uint16_t i;
 460         struct rte_mbuf **sw_ring;
 461
 462         if (tx_queue) {
 463                 sw_ring = tx_queue->sw_ring;
 464                 if (sw_ring) {
 465                         for (i = 0; i < tx_queue->nb_desc; i++) {
 466                                 if (sw_ring[i])
 467                                         rte_pktmbuf_free(sw_ring[i]);
 468                         }
 469                         rte_free(sw_ring);
 470                 }
 471                 rte_free(tx_queue);
 472         }
 473 }
 474
 475 void axgbe_dev_tx_queue_release(void *txq)
 476 {
 477         axgbe_tx_queue_release(txq);
 478 }
 479
 480 int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 481                              uint16_t nb_desc, unsigned int socket_id,
 482                              const struct rte_eth_txconf *tx_conf)
 483 {
 484         PMD_INIT_FUNC_TRACE();
 485         uint32_t tx_desc;
 486         struct axgbe_port *pdata;
 487         struct axgbe_tx_queue *txq;
 488         unsigned int tsize;
 489         const struct rte_memzone *tz;
 490
 491         tx_desc = nb_desc;
 492         pdata = dev->data->dev_private;
 493
 494         /*
 495          * validate tx descriptors count
 496          * should be power of 2 and less than h/w supported
 497          */
 498         if ((!rte_is_power_of_2(tx_desc)) ||
 499             tx_desc > pdata->tx_desc_count ||
 500             tx_desc < AXGBE_MIN_RING_DESC)
 501                 return -EINVAL;
 502
 503         /* First allocate the tx queue data structure */
 504         txq = rte_zmalloc("ethdev TX queue", sizeof(struct axgbe_tx_queue),
 505                           RTE_CACHE_LINE_SIZE);
 506         if (!txq)
 507                 return -ENOMEM;
 508         txq->pdata = pdata;
 509
 510         txq->nb_desc = tx_desc;
 511         txq->free_thresh = tx_conf->tx_free_thresh ?
 512                 tx_conf->tx_free_thresh : AXGBE_TX_FREE_THRESH;
 513         if (txq->free_thresh > txq->nb_desc)
 514                 txq->free_thresh = (txq->nb_desc >> 1);
 515         txq->free_batch_cnt = txq->free_thresh;
 516
 517         /* In vector_tx path threshold should be multiple of queue_size*/
 518         if (txq->nb_desc % txq->free_thresh != 0)
 519                 txq->vector_disable = 1;
 520
 521         if (tx_conf->offloads != 0)
 522                 txq->vector_disable = 1;
 523
 524         /* Allocate TX ring hardware descriptors */
 525         tsize = txq->nb_desc * sizeof(struct axgbe_tx_desc);
 526         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 527                                       tsize, AXGBE_DESC_ALIGN, socket_id);
 528         if (!tz) {
 529                 axgbe_tx_queue_release(txq);
 530                 return -ENOMEM;
 531         }
 532         memset(tz->addr, 0, tsize);
 533         txq->ring_phys_addr = (uint64_t)tz->phys_addr;
 534         txq->desc = tz->addr;
 535         txq->queue_id = queue_idx;
 536         txq->port_id = dev->data->port_id;
 537         txq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE +
 538                 (DMA_CH_INC * txq->queue_id));
 539         txq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)txq->dma_regs +
 540                                                   DMA_CH_TDTR_LO);
 541         txq->cur = 0;
 542         txq->dirty = 0;
 543         txq->nb_desc_free = txq->nb_desc;
 544         /* Allocate software ring */
 545         tsize = txq->nb_desc * sizeof(struct rte_mbuf *);
 546         txq->sw_ring = rte_zmalloc("tx_sw_ring", tsize,
 547                                    RTE_CACHE_LINE_SIZE);
 548         if (!txq->sw_ring) {
 549                 axgbe_tx_queue_release(txq);
 550                 return -ENOMEM;
 551         }
 552         dev->data->tx_queues[queue_idx] = txq;
 553         if (!pdata->tx_queues)
 554                 pdata->tx_queues = dev->data->tx_queues;
 555
 556         if (txq->vector_disable)
 557                 dev->tx_pkt_burst = &axgbe_xmit_pkts;
 558         else
 559 #ifdef RTE_ARCH_X86
 560                 dev->tx_pkt_burst = &axgbe_xmit_pkts_vec;
 561 #else
 562                 dev->tx_pkt_burst = &axgbe_xmit_pkts;
 563 #endif
 564
 565         return 0;
 566 }
 567
 568 static void axgbe_txq_prepare_tx_stop(struct axgbe_port *pdata,
 569                                       unsigned int queue)
 570 {
 571         unsigned int tx_status;
 572         unsigned long tx_timeout;
 573
 574         /* The Tx engine cannot be stopped if it is actively processing
 575          * packets. Wait for the Tx queue to empty the Tx fifo.  Don't
 576          * wait forever though...
 577          */
 578         tx_timeout = rte_get_timer_cycles() + (AXGBE_DMA_STOP_TIMEOUT *
 579                                                rte_get_timer_hz());
 580         while (time_before(rte_get_timer_cycles(), tx_timeout)) {
 581                 tx_status = AXGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR);
 582                 if ((AXGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TRCSTS) != 1) &&
 583                     (AXGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TXQSTS) == 0))
 584                         break;
 585
 586                 rte_delay_us(900);
 587         }
 588
 589         if (!time_before(rte_get_timer_cycles(), tx_timeout))
 590                 PMD_DRV_LOG(ERR,
 591                             "timed out waiting for Tx queue %u to empty\n",
 592                             queue);
 593 }
 594
 595 static void axgbe_prepare_tx_stop(struct axgbe_port *pdata,
 596                                   unsigned int queue)
 597 {
 598         unsigned int tx_dsr, tx_pos, tx_qidx;
 599         unsigned int tx_status;
 600         unsigned long tx_timeout;
 601
 602         if (AXGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20)
 603                 return axgbe_txq_prepare_tx_stop(pdata, queue);
 604
 605         /* Calculate the status register to read and the position within */
 606         if (queue < DMA_DSRX_FIRST_QUEUE) {
 607                 tx_dsr = DMA_DSR0;
 608                 tx_pos = (queue * DMA_DSR_Q_WIDTH) + DMA_DSR0_TPS_START;
 609         } else {
 610                 tx_qidx = queue - DMA_DSRX_FIRST_QUEUE;
 611
 612                 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC);
 613                 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) +
 614                         DMA_DSRX_TPS_START;
 615         }
 616
 617         /* The Tx engine cannot be stopped if it is actively processing
 618          * descriptors. Wait for the Tx engine to enter the stopped or
 619          * suspended state.  Don't wait forever though...
 620          */
 621         tx_timeout = rte_get_timer_cycles() + (AXGBE_DMA_STOP_TIMEOUT *
 622                                                rte_get_timer_hz());
 623         while (time_before(rte_get_timer_cycles(), tx_timeout)) {
 624                 tx_status = AXGMAC_IOREAD(pdata, tx_dsr);
 625                 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH);
 626                 if ((tx_status == DMA_TPS_STOPPED) ||
 627                     (tx_status == DMA_TPS_SUSPENDED))
 628                         break;
 629
 630                 rte_delay_us(900);
 631         }
 632
 633         if (!time_before(rte_get_timer_cycles(), tx_timeout))
 634                 PMD_DRV_LOG(ERR,
 635                             "timed out waiting for Tx DMA channel %u to stop\n",
 636                             queue);
 637 }
 638
 639 void axgbe_dev_disable_tx(struct rte_eth_dev *dev)
 640 {
 641         struct axgbe_tx_queue *txq;
 642         struct axgbe_port *pdata = dev->data->dev_private;
 643         unsigned int i;
 644
 645         /* Prepare for stopping DMA channel */
 646         for (i = 0; i < pdata->tx_q_count; i++) {
 647                 txq = dev->data->tx_queues[i];
 648                 axgbe_prepare_tx_stop(pdata, i);
 649         }
 650         /* Disable MAC Tx */
 651         AXGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
 652         /* Disable each Tx queue*/
 653         for (i = 0; i < pdata->tx_q_count; i++)
 654                 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
 655                                         0);
 656         /* Disable each  Tx DMA channel */
 657         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 658                 txq = dev->data->tx_queues[i];
 659                 AXGMAC_DMA_IOWRITE_BITS(txq, DMA_CH_TCR, ST, 0);
 660         }
 661 }
 662
 663 void axgbe_dev_enable_tx(struct rte_eth_dev *dev)
 664 {
 665         struct axgbe_tx_queue *txq;
 666         struct axgbe_port *pdata = dev->data->dev_private;
 667         unsigned int i;
 668
 669         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 670                 txq = dev->data->tx_queues[i];
 671                 /* Enable Tx DMA channel */
 672                 AXGMAC_DMA_IOWRITE_BITS(txq, DMA_CH_TCR, ST, 1);
 673         }
 674         /* Enable Tx queue*/
 675         for (i = 0; i < pdata->tx_q_count; i++)
 676                 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
 677                                         MTL_Q_ENABLED);
 678         /* Enable MAC Tx */
 679         AXGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
 680 }
 681
 682 /* Free Tx conformed mbufs */
 683 static void axgbe_xmit_cleanup(struct axgbe_tx_queue *txq)
 684 {
 685         volatile struct axgbe_tx_desc *desc;
 686         uint16_t idx;
 687
 688         idx = AXGBE_GET_DESC_IDX(txq, txq->dirty);
 689         while (txq->cur != txq->dirty) {
 690                 if (unlikely(idx == txq->nb_desc))
 691                         idx = 0;
 692                 desc = &txq->desc[idx];
 693                 /* Check for ownership */
 694                 if (AXGMAC_GET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN))
 695                         return;
 696                 memset((void *)&desc->desc2, 0, 8);
 697                 /* Free mbuf */
 698                 rte_pktmbuf_free(txq->sw_ring[idx]);
 699                 txq->sw_ring[idx++] = NULL;
 700                 txq->dirty++;
 701         }
 702 }
 703
 704 /* Tx Descriptor formation
 705  * Considering each mbuf requires one desc
 706  * mbuf is linear
 707  */
 708 static int axgbe_xmit_hw(struct axgbe_tx_queue *txq,
 709                          struct rte_mbuf *mbuf)
 710 {
 711         volatile struct axgbe_tx_desc *desc;
 712         uint16_t idx;
 713         uint64_t mask;
 714
 715         idx = AXGBE_GET_DESC_IDX(txq, txq->cur);
 716         desc = &txq->desc[idx];
 717
 718         /* Update buffer address  and length */
 719         desc->baddr = rte_mbuf_data_iova(mbuf);
 720         AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, HL_B1L,
 721                            mbuf->pkt_len);
 722         /* Total msg length to transmit */
 723         AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FL,
 724                            mbuf->pkt_len);
 725         /* Mark it as First and Last Descriptor */
 726         AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FD, 1);
 727         AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, LD, 1);
 728         /* Mark it as a NORMAL descriptor */
 729         AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CTXT, 0);
 730         /* configure h/w Offload */
 731         mask = mbuf->ol_flags & PKT_TX_L4_MASK;
 732         if ((mask == PKT_TX_TCP_CKSUM) || (mask == PKT_TX_UDP_CKSUM))
 733                 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CIC, 0x3);
 734         else if (mbuf->ol_flags & PKT_TX_IP_CKSUM)
 735                 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CIC, 0x1);
 736         rte_wmb();
 737
 738         /* Set OWN bit */
 739         AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN, 1);
 740         rte_wmb();
 741
 742         /* Save mbuf */
 743         txq->sw_ring[idx] = mbuf;
 744         /* Update current index*/
 745         txq->cur++;
 746         /* Update stats */
 747         txq->bytes += mbuf->pkt_len;
 748
 749         return 0;
 750 }
 751
 752 /* Eal supported tx wrapper*/
 753 uint16_t
 754 axgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 755                 uint16_t nb_pkts)
 756 {
 757         PMD_INIT_FUNC_TRACE();
 758
 759         if (unlikely(nb_pkts == 0))
 760                 return nb_pkts;
 761
 762         struct axgbe_tx_queue *txq;
 763         uint16_t nb_desc_free;
 764         uint16_t nb_pkt_sent = 0;
 765         uint16_t idx;
 766         uint32_t tail_addr;
 767         struct rte_mbuf *mbuf;
 768
 769         txq  = (struct axgbe_tx_queue *)tx_queue;
 770         nb_desc_free = txq->nb_desc - (txq->cur - txq->dirty);
 771
 772         if (unlikely(nb_desc_free <= txq->free_thresh)) {
 773                 axgbe_xmit_cleanup(txq);
 774                 nb_desc_free = txq->nb_desc - (txq->cur - txq->dirty);
 775                 if (unlikely(nb_desc_free == 0))
 776                         return 0;
 777         }
 778         nb_pkts = RTE_MIN(nb_desc_free, nb_pkts);
 779         while (nb_pkts--) {
 780                 mbuf = *tx_pkts++;
 781                 if (axgbe_xmit_hw(txq, mbuf))
 782                         goto out;
 783                 nb_pkt_sent++;
 784         }
 785 out:
 786         /* Sync read and write */
 787         rte_mb();
 788         idx = AXGBE_GET_DESC_IDX(txq, txq->cur);
 789         tail_addr = low32_value(txq->ring_phys_addr +
 790                                 idx * sizeof(struct axgbe_tx_desc));
 791         /* Update tail reg with next immediate address to kick Tx DMA channel*/
 792         AXGMAC_DMA_IOWRITE(txq, DMA_CH_TDTR_LO, tail_addr);
 793         txq->pkts += nb_pkt_sent;
 794         return nb_pkt_sent;
 795 }
 796
 797 void axgbe_dev_clear_queues(struct rte_eth_dev *dev)
 798 {
 799         PMD_INIT_FUNC_TRACE();
 800         uint8_t i;
 801         struct axgbe_rx_queue *rxq;
 802         struct axgbe_tx_queue *txq;
 803
 804         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 805                 rxq = dev->data->rx_queues[i];
 806
 807                 if (rxq) {
 808                         axgbe_rx_queue_release(rxq);
 809                         dev->data->rx_queues[i] = NULL;
 810                 }
 811         }
 812
 813         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 814                 txq = dev->data->tx_queues[i];
 815
 816                 if (txq) {
 817                         axgbe_tx_queue_release(txq);
 818                         dev->data->tx_queues[i] = NULL;
 819                 }
 820         }
 821 }