drivers/net/bnx2x/bnx2x.c

   1 /*-
   2  * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.
   3  *
   4  * Eric Davis        <edavis@broadcom.com>
   5  * David Christensen <davidch@broadcom.com>
   6  * Gary Zambrano     <zambrano@broadcom.com>
   7  *
   8  * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
   9  * All rights reserved.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  *
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in the
  19  *    documentation and/or other materials provided with the distribution.
  20  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  21  *    may be used to endorse or promote products derived from this software
  22  *    without specific prior written consent.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  32  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  34  * THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 #define BNX2X_DRIVER_VERSION "1.78.18"
  38
  39 #include "bnx2x.h"
  40 #include "bnx2x_vfpf.h"
  41 #include "ecore_sp.h"
  42 #include "ecore_init.h"
  43 #include "ecore_init_ops.h"
  44
  45 #include "rte_pci_dev_ids.h"
  46
  47 #include <sys/types.h>
  48 #include <sys/stat.h>
  49 #include <fcntl.h>
  50 #include <zlib.h>
  51
  52 static z_stream zlib_stream;
  53
  54 #define EVL_VLID_MASK 0x0FFF
  55
  56 #define BNX2X_DEF_SB_ATT_IDX 0x0001
  57 #define BNX2X_DEF_SB_IDX     0x0002
  58
  59 /*
  60  * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
  61  * function HW initialization.
  62  */
  63 #define FLR_WAIT_USEC     10000 /* 10 msecs */
  64 #define FLR_WAIT_INTERVAL 50    /* usecs */
  65 #define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)   /* 200 */
  66
  67 struct pbf_pN_buf_regs {
  68         int pN;
  69         uint32_t init_crd;
  70         uint32_t crd;
  71         uint32_t crd_freed;
  72 };
  73
  74 struct pbf_pN_cmd_regs {
  75         int pN;
  76         uint32_t lines_occup;
  77         uint32_t lines_freed;
  78 };
  79
  80 /* resources needed for unloading a previously loaded device */
  81
  82 #define BNX2X_PREV_WAIT_NEEDED 1
  83 rte_spinlock_t bnx2x_prev_mtx;
  84 struct bnx2x_prev_list_node {
  85         LIST_ENTRY(bnx2x_prev_list_node) node;
  86         uint8_t bus;
  87         uint8_t slot;
  88         uint8_t path;
  89         uint8_t aer;
  90         uint8_t undi;
  91 };
  92
  93 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
  94         = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
  95
  96 static int load_count[2][3] = { { 0 } };
  97         /* per-path: 0-common, 1-port0, 2-port1 */
  98
  99 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
 100                                 uint8_t cmng_type);
 101 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
 102 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
 103                               uint8_t port);
 104 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
 105 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
 106 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
 107 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
 108 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
 109                                      uint8_t print);
 110 static void bnx2x_int_disable(struct bnx2x_softc *sc);
 111 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
 112 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
 113 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
 114                                  struct bnx2x_fastpath *fp,
 115                                  uint16_t rx_bd_prod, uint16_t rx_cq_prod);
 116 static void bnx2x_link_report(struct bnx2x_softc *sc);
 117 void bnx2x_link_status_update(struct bnx2x_softc *sc);
 118 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
 119 static void bnx2x_free_mem(struct bnx2x_softc *sc);
 120 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
 121 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
 122 static __attribute__ ((noinline))
 123 int bnx2x_nic_load(struct bnx2x_softc *sc);
 124
 125 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
 126 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
 127 static void bnx2x_periodic_stop(struct bnx2x_softc *sc);
 128 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
 129                          uint8_t storm, uint16_t index, uint8_t op,
 130                          uint8_t update);
 131
 132 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
 133 {
 134         int res;
 135
 136         mb();
 137         res = ((*addr) & (1UL << nr)) != 0;
 138         mb();
 139         return res;
 140 }
 141
 142 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
 143 {
 144         __sync_fetch_and_or(addr, (1UL << nr));
 145 }
 146
 147 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
 148 {
 149         __sync_fetch_and_and(addr, ~(1UL << nr));
 150 }
 151
 152 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
 153 {
 154         unsigned long mask = (1UL << nr);
 155         return __sync_fetch_and_and(addr, ~mask) & mask;
 156 }
 157
 158 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
 159 {
 160         return __sync_val_compare_and_swap(addr, old, new);
 161 }
 162
 163 int
 164 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
 165               const char *msg, uint32_t align)
 166 {
 167         char mz_name[RTE_MEMZONE_NAMESIZE];
 168         const struct rte_memzone *z;
 169
 170         dma->sc = sc;
 171         if (IS_PF(sc))
 172                 sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
 173                         rte_get_timer_cycles());
 174         else
 175                 sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
 176                         rte_get_timer_cycles());
 177
 178         /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
 179         z = rte_memzone_reserve_aligned(mz_name, (uint64_t) (size),
 180                                         rte_lcore_to_socket_id(rte_lcore_id()),
 181                                         0, align);
 182         if (z == NULL) {
 183                 PMD_DRV_LOG(ERR, "DMA alloc failed for %s", msg);
 184                 return -ENOMEM;
 185         }
 186         dma->paddr = (uint64_t) z->phys_addr;
 187         dma->vaddr = z->addr;
 188
 189         PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
 190
 191         return 0;
 192 }
 193
 194 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 195 {
 196         uint32_t lock_status;
 197         uint32_t resource_bit = (1 << resource);
 198         int func = SC_FUNC(sc);
 199         uint32_t hw_lock_control_reg;
 200         int cnt;
 201
 202         PMD_INIT_FUNC_TRACE();
 203
 204         /* validate the resource is within range */
 205         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 206                 PMD_DRV_LOG(NOTICE,
 207                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 208                             resource);
 209                 return -1;
 210         }
 211
 212         if (func <= 5) {
 213                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 214         } else {
 215                 hw_lock_control_reg =
 216                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 217         }
 218
 219         /* validate the resource is not already taken */
 220         lock_status = REG_RD(sc, hw_lock_control_reg);
 221         if (lock_status & resource_bit) {
 222                 PMD_DRV_LOG(NOTICE,
 223                             "resource in use (status 0x%x bit 0x%x)",
 224                             lock_status, resource_bit);
 225                 return -1;
 226         }
 227
 228         /* try every 5ms for 5 seconds */
 229         for (cnt = 0; cnt < 1000; cnt++) {
 230                 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
 231                 lock_status = REG_RD(sc, hw_lock_control_reg);
 232                 if (lock_status & resource_bit) {
 233                         return 0;
 234                 }
 235                 DELAY(5000);
 236         }
 237
 238         PMD_DRV_LOG(NOTICE, "Resource lock timeout!");
 239         return -1;
 240 }
 241
 242 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 243 {
 244         uint32_t lock_status;
 245         uint32_t resource_bit = (1 << resource);
 246         int func = SC_FUNC(sc);
 247         uint32_t hw_lock_control_reg;
 248
 249         PMD_INIT_FUNC_TRACE();
 250
 251         /* validate the resource is within range */
 252         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 253                 PMD_DRV_LOG(NOTICE,
 254                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 255                             resource);
 256                 return -1;
 257         }
 258
 259         if (func <= 5) {
 260                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 261         } else {
 262                 hw_lock_control_reg =
 263                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 264         }
 265
 266         /* validate the resource is currently taken */
 267         lock_status = REG_RD(sc, hw_lock_control_reg);
 268         if (!(lock_status & resource_bit)) {
 269                 PMD_DRV_LOG(NOTICE,
 270                             "resource not in use (status 0x%x bit 0x%x)",
 271                             lock_status, resource_bit);
 272                 return -1;
 273         }
 274
 275         REG_WR(sc, hw_lock_control_reg, resource_bit);
 276         return 0;
 277 }
 278
 279 /* copy command into DMAE command memory and set DMAE command Go */
 280 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
 281 {
 282         uint32_t cmd_offset;
 283         uint32_t i;
 284
 285         cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
 286         for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
 287                 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
 288         }
 289
 290         REG_WR(sc, dmae_reg_go_c[idx], 1);
 291 }
 292
 293 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
 294 {
 295         return (opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 296                           DMAE_COMMAND_C_TYPE_ENABLE));
 297 }
 298
 299 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
 300 {
 301         return (opcode & ~DMAE_COMMAND_SRC_RESET);
 302 }
 303
 304 uint32_t
 305 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
 306                 uint8_t with_comp, uint8_t comp_type)
 307 {
 308         uint32_t opcode = 0;
 309
 310         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 311                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 312
 313         opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
 314
 315         opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 316
 317         opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
 318                    (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
 319
 320         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 321
 322 #ifdef __BIG_ENDIAN
 323         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 324 #else
 325         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 326 #endif
 327
 328         if (with_comp) {
 329                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 330         }
 331
 332         return opcode;
 333 }
 334
 335 static void
 336 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
 337                         uint8_t src_type, uint8_t dst_type)
 338 {
 339         memset(dmae, 0, sizeof(struct dmae_command));
 340
 341         /* set the opcode */
 342         dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
 343                                        TRUE, DMAE_COMP_PCI);
 344
 345         /* fill in the completion parameters */
 346         dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
 347         dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
 348         dmae->comp_val = DMAE_COMP_VAL;
 349 }
 350
 351 /* issue a DMAE command over the init channel and wait for completion */
 352 static int
 353 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
 354 {
 355         uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
 356         int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
 357
 358         /* reset completion */
 359         *wb_comp = 0;
 360
 361         /* post the command on the channel used for initializations */
 362         bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
 363
 364         /* wait for completion */
 365         DELAY(500);
 366
 367         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 368                 if (!timeout ||
 369                     (sc->recovery_state != BNX2X_RECOVERY_DONE &&
 370                      sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 371                         PMD_DRV_LOG(INFO, "DMAE timeout!");
 372                         return DMAE_TIMEOUT;
 373                 }
 374
 375                 timeout--;
 376                 DELAY(50);
 377         }
 378
 379         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 380                 PMD_DRV_LOG(INFO, "DMAE PCI error!");
 381                 return DMAE_PCI_ERROR;
 382         }
 383
 384         return 0;
 385 }
 386
 387 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
 388 {
 389         struct dmae_command dmae;
 390         uint32_t *data;
 391         uint32_t i;
 392         int rc;
 393
 394         if (!sc->dmae_ready) {
 395                 data = BNX2X_SP(sc, wb_data[0]);
 396
 397                 for (i = 0; i < len32; i++) {
 398                         data[i] = REG_RD(sc, (src_addr + (i * 4)));
 399                 }
 400
 401                 return;
 402         }
 403
 404         /* set opcode and fixed command fields */
 405         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 406
 407         /* fill in addresses and len */
 408         dmae.src_addr_lo = (src_addr >> 2);     /* GRC addr has dword resolution */
 409         dmae.src_addr_hi = 0;
 410         dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
 411         dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
 412         dmae.len = len32;
 413
 414         /* issue the command and wait for completion */
 415         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 416                 rte_panic("DMAE failed (%d)", rc);
 417         };
 418 }
 419
 420 void
 421 bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr, uint32_t dst_addr,
 422                uint32_t len32)
 423 {
 424         struct dmae_command dmae;
 425         int rc;
 426
 427         if (!sc->dmae_ready) {
 428                 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
 429                 return;
 430         }
 431
 432         /* set opcode and fixed command fields */
 433         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 434
 435         /* fill in addresses and len */
 436         dmae.src_addr_lo = U64_LO(dma_addr);
 437         dmae.src_addr_hi = U64_HI(dma_addr);
 438         dmae.dst_addr_lo = (dst_addr >> 2);     /* GRC addr has dword resolution */
 439         dmae.dst_addr_hi = 0;
 440         dmae.len = len32;
 441
 442         /* issue the command and wait for completion */
 443         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 444                 rte_panic("DMAE failed (%d)", rc);
 445         }
 446 }
 447
 448 static void
 449 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
 450                         uint32_t addr, uint32_t len)
 451 {
 452         uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
 453         uint32_t offset = 0;
 454
 455         while (len > dmae_wr_max) {
 456                 bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 457                                (addr + offset), /* dst GRC address */
 458                                dmae_wr_max);
 459                 offset += (dmae_wr_max * 4);
 460                 len -= dmae_wr_max;
 461         }
 462
 463         bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 464                        (addr + offset), /* dst GRC address */
 465                        len);
 466 }
 467
 468 void
 469 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
 470                        uint32_t cid)
 471 {
 472         /* ustorm cxt validation */
 473         cxt->ustorm_ag_context.cdu_usage =
 474             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 475                                    CDU_REGION_NUMBER_UCM_AG,
 476                                    ETH_CONNECTION_TYPE);
 477         /* xcontext validation */
 478         cxt->xstorm_ag_context.cdu_reserved =
 479             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 480                                    CDU_REGION_NUMBER_XCM_AG,
 481                                    ETH_CONNECTION_TYPE);
 482 }
 483
 484 static void
 485 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 486                             uint8_t sb_index, uint8_t ticks)
 487 {
 488         uint32_t addr =
 489             (BAR_CSTRORM_INTMEM +
 490              CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
 491
 492         REG_WR8(sc, addr, ticks);
 493 }
 494
 495 static void
 496 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
 497                             uint8_t sb_index, uint8_t disable)
 498 {
 499         uint32_t enable_flag =
 500             (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
 501         uint32_t addr =
 502             (BAR_CSTRORM_INTMEM +
 503              CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
 504         uint8_t flags;
 505
 506         /* clear and set */
 507         flags = REG_RD8(sc, addr);
 508         flags &= ~HC_INDEX_DATA_HC_ENABLED;
 509         flags |= enable_flag;
 510         REG_WR8(sc, addr, flags);
 511 }
 512
 513 void
 514 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 515                              uint8_t sb_index, uint8_t disable, uint16_t usec)
 516 {
 517         uint8_t ticks = (usec / 4);
 518
 519         bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
 520
 521         disable = (disable) ? 1 : ((usec) ? 0 : 1);
 522         bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
 523 }
 524
 525 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
 526 {
 527         return REG_RD(sc, reg_addr);
 528 }
 529
 530 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
 531 {
 532         REG_WR(sc, reg_addr, val);
 533 }
 534
 535 void
 536 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
 537                    __rte_unused const elink_log_id_t elink_log_id, ...)
 538 {
 539         PMD_DRV_LOG(DEBUG, "ELINK EVENT LOG (%d)", elink_log_id);
 540 }
 541
 542 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
 543 {
 544         uint32_t spio_reg;
 545
 546         /* Only 2 SPIOs are configurable */
 547         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
 548                 PMD_DRV_LOG(NOTICE, "Invalid SPIO 0x%x", spio);
 549                 return -1;
 550         }
 551
 552         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 553
 554         /* read SPIO and mask except the float bits */
 555         spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
 556
 557         switch (mode) {
 558         case MISC_SPIO_OUTPUT_LOW:
 559                 /* clear FLOAT and set CLR */
 560                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 561                 spio_reg |= (spio << MISC_SPIO_CLR_POS);
 562                 break;
 563
 564         case MISC_SPIO_OUTPUT_HIGH:
 565                 /* clear FLOAT and set SET */
 566                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 567                 spio_reg |= (spio << MISC_SPIO_SET_POS);
 568                 break;
 569
 570         case MISC_SPIO_INPUT_HI_Z:
 571                 /* set FLOAT */
 572                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
 573                 break;
 574
 575         default:
 576                 break;
 577         }
 578
 579         REG_WR(sc, MISC_REG_SPIO, spio_reg);
 580         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 581
 582         return 0;
 583 }
 584
 585 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
 586 {
 587         /* The GPIO should be swapped if swap register is set and active */
 588         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 589                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 590         int gpio_shift = gpio_num;
 591         if (gpio_port)
 592                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 593
 594         uint32_t gpio_mask = (1 << gpio_shift);
 595         uint32_t gpio_reg;
 596
 597         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 598                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 599                 return -1;
 600         }
 601
 602         /* read GPIO value */
 603         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 604
 605         /* get the requested pin value */
 606         return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
 607 }
 608
 609 static int
 610 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
 611 {
 612         /* The GPIO should be swapped if swap register is set and active */
 613         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 614                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 615         int gpio_shift = gpio_num;
 616         if (gpio_port)
 617                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 618
 619         uint32_t gpio_mask = (1 << gpio_shift);
 620         uint32_t gpio_reg;
 621
 622         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 623                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 624                 return -1;
 625         }
 626
 627         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 628
 629         /* read GPIO and mask except the float bits */
 630         gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
 631
 632         switch (mode) {
 633         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 634                 /* clear FLOAT and set CLR */
 635                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 636                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
 637                 break;
 638
 639         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 640                 /* clear FLOAT and set SET */
 641                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 642                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
 643                 break;
 644
 645         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 646                 /* set FLOAT */
 647                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 648                 break;
 649
 650         default:
 651                 break;
 652         }
 653
 654         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 655         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 656
 657         return 0;
 658 }
 659
 660 static int
 661 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
 662 {
 663         uint32_t gpio_reg;
 664
 665         /* any port swapping should be handled by caller */
 666
 667         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 668
 669         /* read GPIO and mask except the float bits */
 670         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 671         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 672         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
 673         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
 674
 675         switch (mode) {
 676         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 677                 /* set CLR */
 678                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
 679                 break;
 680
 681         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 682                 /* set SET */
 683                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
 684                 break;
 685
 686         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 687                 /* set FLOAT */
 688                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 689                 break;
 690
 691         default:
 692                 PMD_DRV_LOG(NOTICE, "Invalid GPIO mode assignment %d", mode);
 693                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 694                 return -1;
 695         }
 696
 697         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 698         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 699
 700         return 0;
 701 }
 702
 703 static int
 704 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
 705                    uint8_t port)
 706 {
 707         /* The GPIO should be swapped if swap register is set and active */
 708         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 709                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 710         int gpio_shift = gpio_num;
 711         if (gpio_port)
 712                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 713
 714         uint32_t gpio_mask = (1 << gpio_shift);
 715         uint32_t gpio_reg;
 716
 717         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 718                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 719                 return -1;
 720         }
 721
 722         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 723
 724         /* read GPIO int */
 725         gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
 726
 727         switch (mode) {
 728         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
 729                 /* clear SET and set CLR */
 730                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 731                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 732                 break;
 733
 734         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
 735                 /* clear CLR and set SET */
 736                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 737                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 738                 break;
 739
 740         default:
 741                 break;
 742         }
 743
 744         REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
 745         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 746
 747         return 0;
 748 }
 749
 750 uint32_t
 751 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
 752 {
 753         return bnx2x_gpio_read(sc, gpio_num, port);
 754 }
 755
 756 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,   /* 0=low 1=high */
 757                             uint8_t port)
 758 {
 759         return bnx2x_gpio_write(sc, gpio_num, mode, port);
 760 }
 761
 762 uint8_t
 763 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
 764                          uint8_t mode /* 0=low 1=high */ )
 765 {
 766         return bnx2x_gpio_mult_write(sc, pins, mode);
 767 }
 768
 769 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,       /* 0=low 1=high */
 770                                 uint8_t port)
 771 {
 772         return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
 773 }
 774
 775 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
 776 {
 777         REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
 778                     (SC_FUNC(sc) * sizeof(uint32_t))), 1);
 779 }
 780
 781 /* send the MCP a request, block until there is a reply */
 782 uint32_t
 783 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 784 {
 785         int mb_idx = SC_FW_MB_IDX(sc);
 786         uint32_t seq;
 787         uint32_t rc = 0;
 788         uint32_t cnt = 1;
 789         uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
 790
 791         seq = ++sc->fw_seq;
 792         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
 793         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
 794
 795         PMD_DRV_LOG(DEBUG,
 796                     "wrote command 0x%08x to FW MB param 0x%08x",
 797                     (command | seq), param);
 798
 799         /* Let the FW do it's magic. GIve it up to 5 seconds... */
 800         do {
 801                 DELAY(delay * 1000);
 802                 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
 803         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
 804
 805         /* is this a reply to our command? */
 806         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
 807                 rc &= FW_MSG_CODE_MASK;
 808         } else {
 809                 /* Ruh-roh! */
 810                 PMD_DRV_LOG(NOTICE, "FW failed to respond!");
 811                 rc = 0;
 812         }
 813
 814         return rc;
 815 }
 816
 817 static uint32_t
 818 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 819 {
 820         return elink_cb_fw_command(sc, command, param);
 821 }
 822
 823 static void
 824 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
 825                            phys_addr_t mapping)
 826 {
 827         REG_WR(sc, addr, U64_LO(mapping));
 828         REG_WR(sc, (addr + 4), U64_HI(mapping));
 829 }
 830
 831 static void
 832 storm_memset_spq_addr(struct bnx2x_softc *sc, phys_addr_t mapping,
 833                       uint16_t abs_fid)
 834 {
 835         uint32_t addr = (XSEM_REG_FAST_MEMORY +
 836                          XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
 837         __storm_memset_dma_mapping(sc, addr, mapping);
 838 }
 839
 840 static void
 841 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
 842 {
 843         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
 844                 pf_id);
 845         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
 846                 pf_id);
 847         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
 848                 pf_id);
 849         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
 850                 pf_id);
 851 }
 852
 853 static void
 854 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
 855 {
 856         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
 857                 enable);
 858         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
 859                 enable);
 860         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
 861                 enable);
 862         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
 863                 enable);
 864 }
 865
 866 static void
 867 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
 868                      uint16_t pfid)
 869 {
 870         uint32_t addr;
 871         size_t size;
 872
 873         addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
 874         size = sizeof(struct event_ring_data);
 875         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
 876 }
 877
 878 static void
 879 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
 880 {
 881         uint32_t addr = (BAR_CSTRORM_INTMEM +
 882                          CSTORM_EVENT_RING_PROD_OFFSET(pfid));
 883         REG_WR16(sc, addr, eq_prod);
 884 }
 885
 886 /*
 887  * Post a slowpath command.
 888  *
 889  * A slowpath command is used to propogate a configuration change through
 890  * the controller in a controlled manner, allowing each STORM processor and
 891  * other H/W blocks to phase in the change.  The commands sent on the
 892  * slowpath are referred to as ramrods.  Depending on the ramrod used the
 893  * completion of the ramrod will occur in different ways.  Here's a
 894  * breakdown of ramrods and how they complete:
 895  *
 896  * RAMROD_CMD_ID_ETH_PORT_SETUP
 897  *   Used to setup the leading connection on a port.  Completes on the
 898  *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
 899  *
 900  * RAMROD_CMD_ID_ETH_CLIENT_SETUP
 901  *   Used to setup an additional connection on a port.  Completes on the
 902  *   RCQ of the multi-queue/RSS connection being initialized.
 903  *
 904  * RAMROD_CMD_ID_ETH_STAT_QUERY
 905  *   Used to force the storm processors to update the statistics database
 906  *   in host memory.  This ramrod is send on the leading connection CID and
 907  *   completes as an index increment of the CSTORM on the default status
 908  *   block.
 909  *
 910  * RAMROD_CMD_ID_ETH_UPDATE
 911  *   Used to update the state of the leading connection, usually to udpate
 912  *   the RSS indirection table.  Completes on the RCQ of the leading
 913  *   connection. (Not currently used under FreeBSD until OS support becomes
 914  *   available.)
 915  *
 916  * RAMROD_CMD_ID_ETH_HALT
 917  *   Used when tearing down a connection prior to driver unload.  Completes
 918  *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
 919  *   use this on the leading connection.
 920  *
 921  * RAMROD_CMD_ID_ETH_SET_MAC
 922  *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
 923  *   the RCQ of the leading connection.
 924  *
 925  * RAMROD_CMD_ID_ETH_CFC_DEL
 926  *   Used when tearing down a conneciton prior to driver unload.  Completes
 927  *   on the RCQ of the leading connection (since the current connection
 928  *   has been completely removed from controller memory).
 929  *
 930  * RAMROD_CMD_ID_ETH_PORT_DEL
 931  *   Used to tear down the leading connection prior to driver unload,
 932  *   typically fp[0].  Completes as an index increment of the CSTORM on the
 933  *   default status block.
 934  *
 935  * RAMROD_CMD_ID_ETH_FORWARD_SETUP
 936  *   Used for connection offload.  Completes on the RCQ of the multi-queue
 937  *   RSS connection that is being offloaded.  (Not currently used under
 938  *   FreeBSD.)
 939  *
 940  * There can only be one command pending per function.
 941  *
 942  * Returns:
 943  *   0 = Success, !0 = Failure.
 944  */
 945
 946 /* must be called under the spq lock */
 947 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
 948 {
 949         struct eth_spe *next_spe = sc->spq_prod_bd;
 950
 951         if (sc->spq_prod_bd == sc->spq_last_bd) {
 952                 /* wrap back to the first eth_spq */
 953                 sc->spq_prod_bd = sc->spq;
 954                 sc->spq_prod_idx = 0;
 955         } else {
 956                 sc->spq_prod_bd++;
 957                 sc->spq_prod_idx++;
 958         }
 959
 960         return next_spe;
 961 }
 962
 963 /* must be called under the spq lock */
 964 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
 965 {
 966         int func = SC_FUNC(sc);
 967
 968         /*
 969          * Make sure that BD data is updated before writing the producer.
 970          * BD data is written to the memory, the producer is read from the
 971          * memory, thus we need a full memory barrier to ensure the ordering.
 972          */
 973         mb();
 974
 975         REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
 976                  sc->spq_prod_idx);
 977
 978         mb();
 979 }
 980
 981 /**
 982  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
 983  *
 984  * @cmd:      command to check
 985  * @cmd_type: command type
 986  */
 987 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
 988 {
 989         if ((cmd_type == NONE_CONNECTION_TYPE) ||
 990             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
 991             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
 992             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
 993             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
 994             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
 995             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
 996                 return TRUE;
 997         } else {
 998                 return FALSE;
 999         }
1000 }
1001
1002 /**
1003  * bnx2x_sp_post - place a single command on an SP ring
1004  *
1005  * @sc:         driver handle
1006  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
1007  * @cid:        SW CID the command is related to
1008  * @data_hi:    command private data address (high 32 bits)
1009  * @data_lo:    command private data address (low 32 bits)
1010  * @cmd_type:   command type (e.g. NONE, ETH)
1011  *
1012  * SP data is handled as if it's always an address pair, thus data fields are
1013  * not swapped to little endian in upper functions. Instead this function swaps
1014  * data as if it's two uint32 fields.
1015  */
1016 int
1017 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1018             uint32_t data_lo, int cmd_type)
1019 {
1020         struct eth_spe *spe;
1021         uint16_t type;
1022         int common;
1023
1024         common = bnx2x_is_contextless_ramrod(command, cmd_type);
1025
1026         if (common) {
1027                 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1028                         PMD_DRV_LOG(INFO, "EQ ring is full!");
1029                         return -1;
1030                 }
1031         } else {
1032                 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1033                         PMD_DRV_LOG(INFO, "SPQ ring is full!");
1034                         return -1;
1035                 }
1036         }
1037
1038         spe = bnx2x_sp_get_next(sc);
1039
1040         /* CID needs port number to be encoded int it */
1041         spe->hdr.conn_and_cmd_data =
1042             htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1043
1044         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1045
1046         /* TBD: Check if it works for VFs */
1047         type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1048                  SPE_HDR_FUNCTION_ID);
1049
1050         spe->hdr.type = htole16(type);
1051
1052         spe->data.update_data_addr.hi = htole32(data_hi);
1053         spe->data.update_data_addr.lo = htole32(data_lo);
1054
1055         /*
1056          * It's ok if the actual decrement is issued towards the memory
1057          * somewhere between the lock and unlock. Thus no more explict
1058          * memory barrier is needed.
1059          */
1060         if (common) {
1061                 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1062         } else {
1063                 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1064         }
1065
1066         PMD_DRV_LOG(DEBUG,
1067                     "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1068                     "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1069                     sc->spq_prod_idx,
1070                     (uint32_t) U64_HI(sc->spq_dma.paddr),
1071                     (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1072                                 (uint8_t *) sc->spq_prod_bd -
1073                                 (uint8_t *) sc->spq), command, common,
1074                     HW_CID(sc, cid), data_hi, data_lo, type,
1075                     atomic_load_acq_long(&sc->cq_spq_left),
1076                     atomic_load_acq_long(&sc->eq_spq_left));
1077
1078         bnx2x_sp_prod_update(sc);
1079
1080         return 0;
1081 }
1082
1083 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1084 {
1085         SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1086                  sc->fw_drv_pulse_wr_seq);
1087 }
1088
1089 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1090 {
1091         uint16_t hw_cons;
1092         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1093
1094         if (unlikely(!txq)) {
1095                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1096                 return 0;
1097         }
1098
1099         mb();                   /* status block fields can change */
1100         hw_cons = le16toh(*fp->tx_cons_sb);
1101         return (hw_cons != txq->tx_pkt_head);
1102 }
1103
1104 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1105 {
1106         /* expand this for multi-cos if ever supported */
1107         return bnx2x_tx_queue_has_work(fp);
1108 }
1109
1110 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1111 {
1112         uint16_t rx_cq_cons_sb;
1113         struct bnx2x_rx_queue *rxq;
1114         rxq = fp->sc->rx_queues[fp->index];
1115         if (unlikely(!rxq)) {
1116                 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1117                 return 0;
1118         }
1119
1120         mb();                   /* status block fields can change */
1121         rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1122         if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1123                      MAX_RCQ_ENTRIES(rxq)))
1124                 rx_cq_cons_sb++;
1125         return (rxq->rx_cq_head != rx_cq_cons_sb);
1126 }
1127
1128 static void
1129 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1130              union eth_rx_cqe *rr_cqe)
1131 {
1132 #ifdef RTE_LIBRTE_BNX2X_DEBUG
1133         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1134 #endif
1135         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1136         enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1137         struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1138
1139         PMD_DRV_LOG(DEBUG,
1140                     "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1141                     fp->index, cid, command, sc->state,
1142                     rr_cqe->ramrod_cqe.ramrod_type);
1143
1144         switch (command) {
1145         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1146                 PMD_DRV_LOG(DEBUG, "got UPDATE ramrod. CID %d", cid);
1147                 drv_cmd = ECORE_Q_CMD_UPDATE;
1148                 break;
1149
1150         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1151                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] setup ramrod", cid);
1152                 drv_cmd = ECORE_Q_CMD_SETUP;
1153                 break;
1154
1155         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1156                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] tx-only setup ramrod", cid);
1157                 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1158                 break;
1159
1160         case (RAMROD_CMD_ID_ETH_HALT):
1161                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] halt ramrod", cid);
1162                 drv_cmd = ECORE_Q_CMD_HALT;
1163                 break;
1164
1165         case (RAMROD_CMD_ID_ETH_TERMINATE):
1166                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] teminate ramrod", cid);
1167                 drv_cmd = ECORE_Q_CMD_TERMINATE;
1168                 break;
1169
1170         case (RAMROD_CMD_ID_ETH_EMPTY):
1171                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] empty ramrod", cid);
1172                 drv_cmd = ECORE_Q_CMD_EMPTY;
1173                 break;
1174
1175         default:
1176                 PMD_DRV_LOG(DEBUG,
1177                             "ERROR: unexpected MC reply (%d)"
1178                             "on fp[%d]", command, fp->index);
1179                 return;
1180         }
1181
1182         if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1183             q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1184                 /*
1185                  * q_obj->complete_cmd() failure means that this was
1186                  * an unexpected completion.
1187                  *
1188                  * In this case we don't want to increase the sc->spq_left
1189                  * because apparently we haven't sent this command the first
1190                  * place.
1191                  */
1192                 // rte_panic("Unexpected SP completion");
1193                 return;
1194         }
1195
1196         atomic_add_acq_long(&sc->cq_spq_left, 1);
1197
1198         PMD_DRV_LOG(DEBUG, "sc->cq_spq_left 0x%lx",
1199                     atomic_load_acq_long(&sc->cq_spq_left));
1200 }
1201
1202 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1203 {
1204         struct bnx2x_rx_queue *rxq;
1205         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1206         uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1207
1208         rxq = sc->rx_queues[fp->index];
1209         if (!rxq) {
1210                 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1211                 return 0;
1212         }
1213
1214         /* CQ "next element" is of the size of the regular element */
1215         hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1216         if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1217                      USABLE_RCQ_ENTRIES_PER_PAGE)) {
1218                 hw_cq_cons++;
1219         }
1220
1221         bd_cons = rxq->rx_bd_head;
1222         bd_prod = rxq->rx_bd_tail;
1223         bd_prod_fw = bd_prod;
1224         sw_cq_cons = rxq->rx_cq_head;
1225         sw_cq_prod = rxq->rx_cq_tail;
1226
1227         /*
1228          * Memory barrier necessary as speculative reads of the rx
1229          * buffer can be ahead of the index in the status block
1230          */
1231         rmb();
1232
1233         while (sw_cq_cons != hw_cq_cons) {
1234                 union eth_rx_cqe *cqe;
1235                 struct eth_fast_path_rx_cqe *cqe_fp;
1236                 uint8_t cqe_fp_flags;
1237                 enum eth_rx_cqe_type cqe_fp_type;
1238
1239                 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1240                 bd_prod = RX_BD(bd_prod, rxq);
1241                 bd_cons = RX_BD(bd_cons, rxq);
1242
1243                 cqe = &rxq->cq_ring[comp_ring_cons];
1244                 cqe_fp = &cqe->fast_path_cqe;
1245                 cqe_fp_flags = cqe_fp->type_error_flags;
1246                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1247
1248                 /* is this a slowpath msg? */
1249                 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1250                         bnx2x_sp_event(sc, fp, cqe);
1251                         goto next_cqe;
1252                 }
1253
1254                 /* is this an error packet? */
1255                 if (unlikely(cqe_fp_flags &
1256                              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1257                         PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1258                                    cqe_fp_flags, sw_cq_cons);
1259                         goto next_rx;
1260                 }
1261
1262                 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1263
1264 next_rx:
1265                 bd_cons = NEXT_RX_BD(bd_cons);
1266                 bd_prod = NEXT_RX_BD(bd_prod);
1267                 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1268
1269 next_cqe:
1270                 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1271                 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1272
1273         }                       /* while work to do */
1274
1275         rxq->rx_bd_head = bd_cons;
1276         rxq->rx_bd_tail = bd_prod_fw;
1277         rxq->rx_cq_head = sw_cq_cons;
1278         rxq->rx_cq_tail = sw_cq_prod;
1279
1280         /* Update producers */
1281         bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1282
1283         return (sw_cq_cons != hw_cq_cons);
1284 }
1285
1286 static uint16_t
1287 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1288                 uint16_t pkt_idx, uint16_t bd_idx)
1289 {
1290         struct eth_tx_start_bd *tx_start_bd =
1291             &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1292         uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1293         struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1294
1295         if (likely(tx_mbuf != NULL)) {
1296                 rte_pktmbuf_free(tx_mbuf);
1297         } else {
1298                 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1299                            fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1300         }
1301
1302         txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1303         txq->nb_tx_avail += nbd;
1304
1305         while (nbd--)
1306                 bd_idx = NEXT_TX_BD(bd_idx);
1307
1308         return bd_idx;
1309 }
1310
1311 /* processes transmit completions */
1312 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1313 {
1314         uint16_t bd_cons, hw_cons, sw_cons;
1315         __rte_unused uint16_t tx_bd_avail;
1316
1317         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1318
1319         if (unlikely(!txq)) {
1320                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1321                 return 0;
1322         }
1323
1324         bd_cons = txq->tx_bd_head;
1325         hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1326         sw_cons = txq->tx_pkt_head;
1327
1328         while (sw_cons != hw_cons) {
1329                 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1330                 sw_cons++;
1331         }
1332
1333         txq->tx_pkt_head = sw_cons;
1334         txq->tx_bd_head = bd_cons;
1335
1336         tx_bd_avail = txq->nb_tx_avail;
1337
1338         PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1339                    "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1340                    fp->index, tx_bd_avail, hw_cons,
1341                    txq->tx_pkt_head, txq->tx_pkt_tail,
1342                    txq->tx_bd_head, txq->tx_bd_tail);
1343         return TRUE;
1344 }
1345
1346 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1347 {
1348         struct bnx2x_fastpath *fp;
1349         int i, count;
1350
1351         /* wait until all TX fastpath tasks have completed */
1352         for (i = 0; i < sc->num_queues; i++) {
1353                 fp = &sc->fp[i];
1354
1355                 count = 1000;
1356
1357                 while (bnx2x_has_tx_work(fp)) {
1358                         bnx2x_txeof(sc, fp);
1359
1360                         if (count == 0) {
1361                                 PMD_TX_LOG(ERR,
1362                                            "Timeout waiting for fp[%d] "
1363                                            "transmits to complete!", i);
1364                                 rte_panic("tx drain failure");
1365                                 return;
1366                         }
1367
1368                         count--;
1369                         DELAY(1000);
1370                         rmb();
1371                 }
1372         }
1373
1374         return;
1375 }
1376
1377 static int
1378 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1379                  int mac_type, uint8_t wait_for_comp)
1380 {
1381         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1382         int rc;
1383
1384         /* wait for completion of requested */
1385         if (wait_for_comp) {
1386                 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1387         }
1388
1389         /* Set the mac type of addresses we want to clear */
1390         bnx2x_set_bit(mac_type, &vlan_mac_flags);
1391
1392         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1393         if (rc < 0)
1394                 PMD_DRV_LOG(ERR, "Failed to delete MACs (%d)", rc);
1395
1396         return rc;
1397 }
1398
1399 int
1400 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1401                       unsigned long *rx_accept_flags,
1402                       unsigned long *tx_accept_flags)
1403 {
1404         /* Clear the flags first */
1405         *rx_accept_flags = 0;
1406         *tx_accept_flags = 0;
1407
1408         switch (rx_mode) {
1409         case BNX2X_RX_MODE_NONE:
1410                 /*
1411                  * 'drop all' supersedes any accept flags that may have been
1412                  * passed to the function.
1413                  */
1414                 break;
1415
1416         case BNX2X_RX_MODE_NORMAL:
1417                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1418                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1419                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1420
1421                 /* internal switching mode */
1422                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1423                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1424                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1425
1426                 break;
1427
1428         case BNX2X_RX_MODE_ALLMULTI:
1429                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1430                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1431                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1432
1433                 /* internal switching mode */
1434                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1435                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1436                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1437
1438                 break;
1439
1440         case BNX2X_RX_MODE_PROMISC:
1441                 /*
1442                  * According to deffinition of SI mode, iface in promisc mode
1443                  * should receive matched and unmatched (in resolution of port)
1444                  * unicast packets.
1445                  */
1446                 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1447                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1448                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1449                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1450
1451                 /* internal switching mode */
1452                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1453                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1454
1455                 if (IS_MF_SI(sc)) {
1456                         bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1457                 } else {
1458                         bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1459                 }
1460
1461                 break;
1462
1463         default:
1464                 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1465                 return -1;
1466         }
1467
1468         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1469         if (rx_mode != BNX2X_RX_MODE_NONE) {
1470                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1471                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1472         }
1473
1474         return 0;
1475 }
1476
1477 static int
1478 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1479                   unsigned long rx_mode_flags,
1480                   unsigned long rx_accept_flags,
1481                   unsigned long tx_accept_flags, unsigned long ramrod_flags)
1482 {
1483         struct ecore_rx_mode_ramrod_params ramrod_param;
1484         int rc;
1485
1486         memset(&ramrod_param, 0, sizeof(ramrod_param));
1487
1488         /* Prepare ramrod parameters */
1489         ramrod_param.cid = 0;
1490         ramrod_param.cl_id = cl_id;
1491         ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1492         ramrod_param.func_id = SC_FUNC(sc);
1493
1494         ramrod_param.pstate = &sc->sp_state;
1495         ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1496
1497         ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1498         ramrod_param.rdata_mapping =
1499             (phys_addr_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1500             bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1501
1502         ramrod_param.ramrod_flags = ramrod_flags;
1503         ramrod_param.rx_mode_flags = rx_mode_flags;
1504
1505         ramrod_param.rx_accept_flags = rx_accept_flags;
1506         ramrod_param.tx_accept_flags = tx_accept_flags;
1507
1508         rc = ecore_config_rx_mode(sc, &ramrod_param);
1509         if (rc < 0) {
1510                 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1511                 return rc;
1512         }
1513
1514         return 0;
1515 }
1516
1517 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1518 {
1519         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1520         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1521         int rc;
1522
1523         rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1524                                    &tx_accept_flags);
1525         if (rc) {
1526                 return rc;
1527         }
1528
1529         bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1530         bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1531         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1532
1533         return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1534                                  rx_accept_flags, tx_accept_flags,
1535                                  ramrod_flags);
1536 }
1537
1538 /* returns the "mcp load_code" according to global load_count array */
1539 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1540 {
1541         int path = SC_PATH(sc);
1542         int port = SC_PORT(sc);
1543
1544         PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1545                     path, load_count[path][0], load_count[path][1],
1546                     load_count[path][2]);
1547
1548         load_count[path][0]++;
1549         load_count[path][1 + port]++;
1550         PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1551                     path, load_count[path][0], load_count[path][1],
1552                     load_count[path][2]);
1553         if (load_count[path][0] == 1)
1554                 return FW_MSG_CODE_DRV_LOAD_COMMON;
1555         else if (load_count[path][1 + port] == 1)
1556                 return FW_MSG_CODE_DRV_LOAD_PORT;
1557         else
1558                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1559 }
1560
1561 /* returns the "mcp load_code" according to global load_count array */
1562 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1563 {
1564         int port = SC_PORT(sc);
1565         int path = SC_PATH(sc);
1566
1567         PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1568                     path, load_count[path][0], load_count[path][1],
1569                     load_count[path][2]);
1570         load_count[path][0]--;
1571         load_count[path][1 + port]--;
1572         PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1573                     path, load_count[path][0], load_count[path][1],
1574                     load_count[path][2]);
1575         if (load_count[path][0] == 0) {
1576                 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1577         } else if (load_count[path][1 + port] == 0) {
1578                 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1579         } else {
1580                 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1581         }
1582 }
1583
1584 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1585 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1586 {
1587         uint32_t reset_code = 0;
1588
1589         /* Select the UNLOAD request mode */
1590         if (unload_mode == UNLOAD_NORMAL) {
1591                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1592         } else {
1593                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1594         }
1595
1596         /* Send the request to the MCP */
1597         if (!BNX2X_NOMCP(sc)) {
1598                 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1599         } else {
1600                 reset_code = bnx2x_nic_unload_no_mcp(sc);
1601         }
1602
1603         return reset_code;
1604 }
1605
1606 /* send UNLOAD_DONE command to the MCP */
1607 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1608 {
1609         uint32_t reset_param =
1610             keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1611
1612         /* Report UNLOAD_DONE to MCP */
1613         if (!BNX2X_NOMCP(sc)) {
1614                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1615         }
1616 }
1617
1618 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1619 {
1620         int tout = 50;
1621
1622         if (!sc->port.pmf) {
1623                 return 0;
1624         }
1625
1626         /*
1627          * (assumption: No Attention from MCP at this stage)
1628          * PMF probably in the middle of TX disable/enable transaction
1629          * 1. Sync IRS for default SB
1630          * 2. Sync SP queue - this guarantees us that attention handling started
1631          * 3. Wait, that TX disable/enable transaction completes
1632          *
1633          * 1+2 guarantee that if DCBX attention was scheduled it already changed
1634          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1635          * received completion for the transaction the state is TX_STOPPED.
1636          * State will return to STARTED after completion of TX_STOPPED-->STARTED
1637          * transaction.
1638          */
1639
1640         while (ecore_func_get_state(sc, &sc->func_obj) !=
1641                ECORE_F_STATE_STARTED && tout--) {
1642                 DELAY(20000);
1643         }
1644
1645         if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1646                 /*
1647                  * Failed to complete the transaction in a "good way"
1648                  * Force both transactions with CLR bit.
1649                  */
1650                 struct ecore_func_state_params func_params = { NULL };
1651
1652                 PMD_DRV_LOG(NOTICE, "Unexpected function state! "
1653                             "Forcing STARTED-->TX_STOPPED-->STARTED");
1654
1655                 func_params.f_obj = &sc->func_obj;
1656                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1657
1658                 /* STARTED-->TX_STOPPED */
1659                 func_params.cmd = ECORE_F_CMD_TX_STOP;
1660                 ecore_func_state_change(sc, &func_params);
1661
1662                 /* TX_STOPPED-->STARTED */
1663                 func_params.cmd = ECORE_F_CMD_TX_START;
1664                 return ecore_func_state_change(sc, &func_params);
1665         }
1666
1667         return 0;
1668 }
1669
1670 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1671 {
1672         struct bnx2x_fastpath *fp = &sc->fp[index];
1673         struct ecore_queue_state_params q_params = { NULL };
1674         int rc;
1675
1676         PMD_DRV_LOG(DEBUG, "stopping queue %d cid %d", index, fp->index);
1677
1678         q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1679         /* We want to wait for completion in this context */
1680         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1681
1682         /* Stop the primary connection: */
1683
1684         /* ...halt the connection */
1685         q_params.cmd = ECORE_Q_CMD_HALT;
1686         rc = ecore_queue_state_change(sc, &q_params);
1687         if (rc) {
1688                 return rc;
1689         }
1690
1691         /* ...terminate the connection */
1692         q_params.cmd = ECORE_Q_CMD_TERMINATE;
1693         memset(&q_params.params.terminate, 0,
1694                sizeof(q_params.params.terminate));
1695         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1696         rc = ecore_queue_state_change(sc, &q_params);
1697         if (rc) {
1698                 return rc;
1699         }
1700
1701         /* ...delete cfc entry */
1702         q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1703         memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1704         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1705         return ecore_queue_state_change(sc, &q_params);
1706 }
1707
1708 /* wait for the outstanding SP commands */
1709 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1710 {
1711         unsigned long tmp;
1712         int tout = 5000;        /* wait for 5 secs tops */
1713
1714         while (tout--) {
1715                 mb();
1716                 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1717                         return TRUE;
1718                 }
1719
1720                 DELAY(1000);
1721         }
1722
1723         mb();
1724
1725         tmp = atomic_load_acq_long(&sc->sp_state);
1726         if (tmp & mask) {
1727                 PMD_DRV_LOG(INFO, "Filtering completion timed out: "
1728                             "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1729                 return FALSE;
1730         }
1731
1732         return FALSE;
1733 }
1734
1735 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1736 {
1737         struct ecore_func_state_params func_params = { NULL };
1738         int rc;
1739
1740         /* prepare parameters for function state transitions */
1741         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1742         func_params.f_obj = &sc->func_obj;
1743         func_params.cmd = ECORE_F_CMD_STOP;
1744
1745         /*
1746          * Try to stop the function the 'good way'. If it fails (in case
1747          * of a parity error during bnx2x_chip_cleanup()) and we are
1748          * not in a debug mode, perform a state transaction in order to
1749          * enable further HW_RESET transaction.
1750          */
1751         rc = ecore_func_state_change(sc, &func_params);
1752         if (rc) {
1753                 PMD_DRV_LOG(NOTICE, "FUNC_STOP ramrod failed. "
1754                             "Running a dry transaction");
1755                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1756                 return ecore_func_state_change(sc, &func_params);
1757         }
1758
1759         return 0;
1760 }
1761
1762 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1763 {
1764         struct ecore_func_state_params func_params = { NULL };
1765
1766         /* Prepare parameters for function state transitions */
1767         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1768
1769         func_params.f_obj = &sc->func_obj;
1770         func_params.cmd = ECORE_F_CMD_HW_RESET;
1771
1772         func_params.params.hw_init.load_phase = load_code;
1773
1774         return ecore_func_state_change(sc, &func_params);
1775 }
1776
1777 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1778 {
1779         if (disable_hw) {
1780                 /* prevent the HW from sending interrupts */
1781                 bnx2x_int_disable(sc);
1782         }
1783 }
1784
1785 static void
1786 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1787 {
1788         int port = SC_PORT(sc);
1789         struct ecore_mcast_ramrod_params rparam = { NULL };
1790         uint32_t reset_code;
1791         int i, rc = 0;
1792
1793         bnx2x_drain_tx_queues(sc);
1794
1795         /* give HW time to discard old tx messages */
1796         DELAY(1000);
1797
1798         /* Clean all ETH MACs */
1799         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1800                               FALSE);
1801         if (rc < 0) {
1802                 PMD_DRV_LOG(NOTICE, "Failed to delete all ETH MACs (%d)", rc);
1803         }
1804
1805         /* Clean up UC list  */
1806         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1807                               TRUE);
1808         if (rc < 0) {
1809                 PMD_DRV_LOG(NOTICE, "Failed to delete UC MACs list (%d)", rc);
1810         }
1811
1812         /* Disable LLH */
1813         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1814
1815         /* Set "drop all" to stop Rx */
1816
1817         /*
1818          * We need to take the if_maddr_lock() here in order to prevent
1819          * a race between the completion code and this code.
1820          */
1821
1822         if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1823                 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1824         } else {
1825                 bnx2x_set_storm_rx_mode(sc);
1826         }
1827
1828         /* Clean up multicast configuration */
1829         rparam.mcast_obj = &sc->mcast_obj;
1830         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1831         if (rc < 0) {
1832                 PMD_DRV_LOG(NOTICE,
1833                             "Failed to send DEL MCAST command (%d)", rc);
1834         }
1835
1836         /*
1837          * Send the UNLOAD_REQUEST to the MCP. This will return if
1838          * this function should perform FUNCTION, PORT, or COMMON HW
1839          * reset.
1840          */
1841         reset_code = bnx2x_send_unload_req(sc, unload_mode);
1842
1843         /*
1844          * (assumption: No Attention from MCP at this stage)
1845          * PMF probably in the middle of TX disable/enable transaction
1846          */
1847         rc = bnx2x_func_wait_started(sc);
1848         if (rc) {
1849                 PMD_DRV_LOG(NOTICE, "bnx2x_func_wait_started failed");
1850         }
1851
1852         /*
1853          * Close multi and leading connections
1854          * Completions for ramrods are collected in a synchronous way
1855          */
1856         for (i = 0; i < sc->num_queues; i++) {
1857                 if (bnx2x_stop_queue(sc, i)) {
1858                         goto unload_error;
1859                 }
1860         }
1861
1862         /*
1863          * If SP settings didn't get completed so far - something
1864          * very wrong has happen.
1865          */
1866         if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1867                 PMD_DRV_LOG(NOTICE, "Common slow path ramrods got stuck!");
1868         }
1869
1870 unload_error:
1871
1872         rc = bnx2x_func_stop(sc);
1873         if (rc) {
1874                 PMD_DRV_LOG(NOTICE, "Function stop failed!");
1875         }
1876
1877         /* disable HW interrupts */
1878         bnx2x_int_disable_sync(sc, TRUE);
1879
1880         /* Reset the chip */
1881         rc = bnx2x_reset_hw(sc, reset_code);
1882         if (rc) {
1883                 PMD_DRV_LOG(NOTICE, "Hardware reset failed");
1884         }
1885
1886         /* Report UNLOAD_DONE to MCP */
1887         bnx2x_send_unload_done(sc, keep_link);
1888 }
1889
1890 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1891 {
1892         uint32_t val;
1893
1894         PMD_DRV_LOG(DEBUG, "Disabling 'close the gates'");
1895
1896         val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1897         val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1898                  MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1899         REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1900 }
1901
1902 /*
1903  * Cleans the object that have internal lists without sending
1904  * ramrods. Should be run when interrutps are disabled.
1905  */
1906 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1907 {
1908         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1909         struct ecore_mcast_ramrod_params rparam = { NULL };
1910         struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1911         int rc;
1912
1913         /* Cleanup MACs' object first... */
1914
1915         /* Wait for completion of requested */
1916         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1917         /* Perform a dry cleanup */
1918         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1919
1920         /* Clean ETH primary MAC */
1921         bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1922         rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1923                                  &ramrod_flags);
1924         if (rc != 0) {
1925                 PMD_DRV_LOG(NOTICE, "Failed to clean ETH MACs (%d)", rc);
1926         }
1927
1928         /* Cleanup UC list */
1929         vlan_mac_flags = 0;
1930         bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1931         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1932         if (rc != 0) {
1933                 PMD_DRV_LOG(NOTICE, "Failed to clean UC list MACs (%d)", rc);
1934         }
1935
1936         /* Now clean mcast object... */
1937
1938         rparam.mcast_obj = &sc->mcast_obj;
1939         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1940
1941         /* Add a DEL command... */
1942         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1943         if (rc < 0) {
1944                 PMD_DRV_LOG(NOTICE,
1945                             "Failed to send DEL MCAST command (%d)", rc);
1946         }
1947
1948         /* now wait until all pending commands are cleared */
1949
1950         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1951         while (rc != 0) {
1952                 if (rc < 0) {
1953                         PMD_DRV_LOG(NOTICE,
1954                                     "Failed to clean MCAST object (%d)", rc);
1955                         return;
1956                 }
1957
1958                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1959         }
1960 }
1961
1962 /* stop the controller */
1963 __attribute__ ((noinline))
1964 int
1965 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1966 {
1967         uint8_t global = FALSE;
1968         uint32_t val;
1969
1970         PMD_DRV_LOG(DEBUG, "Starting NIC unload...");
1971
1972         /* stop the periodic callout */
1973         bnx2x_periodic_stop(sc);
1974
1975         /* mark driver as unloaded in shmem2 */
1976         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
1977                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
1978                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
1979                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
1980         }
1981
1982         if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
1983             (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
1984                 /*
1985                  * We can get here if the driver has been unloaded
1986                  * during parity error recovery and is either waiting for a
1987                  * leader to complete or for other functions to unload and
1988                  * then ifconfig down has been issued. In this case we want to
1989                  * unload and let other functions to complete a recovery
1990                  * process.
1991                  */
1992                 sc->recovery_state = BNX2X_RECOVERY_DONE;
1993                 sc->is_leader = 0;
1994                 bnx2x_release_leader_lock(sc);
1995                 mb();
1996
1997                 PMD_DRV_LOG(NOTICE, "Can't unload in closed or error state");
1998                 return -1;
1999         }
2000
2001         /*
2002          * Nothing to do during unload if previous bnx2x_nic_load()
2003          * did not completed succesfully - all resourses are released.
2004          */
2005         if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2006                 return 0;
2007         }
2008
2009         sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2010         mb();
2011
2012         sc->rx_mode = BNX2X_RX_MODE_NONE;
2013         bnx2x_set_rx_mode(sc);
2014         mb();
2015
2016         if (IS_PF(sc)) {
2017                 /* set ALWAYS_ALIVE bit in shmem */
2018                 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2019
2020                 bnx2x_drv_pulse(sc);
2021
2022                 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2023                 bnx2x_save_statistics(sc);
2024         }
2025
2026         /* wait till consumers catch up with producers in all queues */
2027         bnx2x_drain_tx_queues(sc);
2028
2029         /* if VF indicate to PF this function is going down (PF will delete sp
2030          * elements and clear initializations
2031          */
2032         if (IS_VF(sc)) {
2033                 bnx2x_vf_unload(sc);
2034         } else if (unload_mode != UNLOAD_RECOVERY) {
2035                 /* if this is a normal/close unload need to clean up chip */
2036                 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2037         } else {
2038                 /* Send the UNLOAD_REQUEST to the MCP */
2039                 bnx2x_send_unload_req(sc, unload_mode);
2040
2041                 /*
2042                  * Prevent transactions to host from the functions on the
2043                  * engine that doesn't reset global blocks in case of global
2044                  * attention once gloabl blocks are reset and gates are opened
2045                  * (the engine which leader will perform the recovery
2046                  * last).
2047                  */
2048                 if (!CHIP_IS_E1x(sc)) {
2049                         bnx2x_pf_disable(sc);
2050                 }
2051
2052                 /* disable HW interrupts */
2053                 bnx2x_int_disable_sync(sc, TRUE);
2054
2055                 /* Report UNLOAD_DONE to MCP */
2056                 bnx2x_send_unload_done(sc, FALSE);
2057         }
2058
2059         /*
2060          * At this stage no more interrupts will arrive so we may safely clean
2061          * the queue'able objects here in case they failed to get cleaned so far.
2062          */
2063         if (IS_PF(sc)) {
2064                 bnx2x_squeeze_objects(sc);
2065         }
2066
2067         /* There should be no more pending SP commands at this stage */
2068         sc->sp_state = 0;
2069
2070         sc->port.pmf = 0;
2071
2072         if (IS_PF(sc)) {
2073                 bnx2x_free_mem(sc);
2074         }
2075
2076         bnx2x_free_fw_stats_mem(sc);
2077
2078         sc->state = BNX2X_STATE_CLOSED;
2079
2080         /*
2081          * Check if there are pending parity attentions. If there are - set
2082          * RECOVERY_IN_PROGRESS.
2083          */
2084         if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2085                 bnx2x_set_reset_in_progress(sc);
2086
2087                 /* Set RESET_IS_GLOBAL if needed */
2088                 if (global) {
2089                         bnx2x_set_reset_global(sc);
2090                 }
2091         }
2092
2093         /*
2094          * The last driver must disable a "close the gate" if there is no
2095          * parity attention or "process kill" pending.
2096          */
2097         if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2098             bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2099                 bnx2x_disable_close_the_gate(sc);
2100         }
2101
2102         PMD_DRV_LOG(DEBUG, "Ended NIC unload");
2103
2104         return 0;
2105 }
2106
2107 /*
2108  * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2109  * visible to the controller.
2110  *
2111  * If an mbuf is submitted to this routine and cannot be given to the
2112  * controller (e.g. it has too many fragments) then the function may free
2113  * the mbuf and return to the caller.
2114  *
2115  * Returns:
2116  *   0 = Success, !0 = Failure
2117  *   Note the side effect that an mbuf may be freed if it causes a problem.
2118  */
2119 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf **m_head, int m_pkts)
2120 {
2121         struct rte_mbuf *m0;
2122         struct eth_tx_start_bd *tx_start_bd;
2123         uint16_t bd_prod, pkt_prod;
2124         int m_tx;
2125         struct bnx2x_softc *sc;
2126         uint32_t nbds = 0;
2127         struct bnx2x_fastpath *fp;
2128
2129         sc = txq->sc;
2130         fp = &sc->fp[txq->queue_id];
2131
2132         bd_prod = txq->tx_bd_tail;
2133         pkt_prod = txq->tx_pkt_tail;
2134
2135         for (m_tx = 0; m_tx < m_pkts; m_tx++) {
2136
2137                 m0 = *m_head++;
2138
2139                 if (unlikely(txq->nb_tx_avail < 3)) {
2140                         PMD_TX_LOG(ERR, "no enough bds %d/%d",
2141                                    bd_prod, txq->nb_tx_avail);
2142                         return -ENOMEM;
2143                 }
2144
2145                 txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2146
2147                 tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2148
2149                 tx_start_bd->addr =
2150                     rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR(m0));
2151                 tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2152                 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2153                 tx_start_bd->general_data =
2154                     (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2155
2156                 tx_start_bd->nbd = rte_cpu_to_le_16(2);
2157
2158                 if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2159                         tx_start_bd->vlan_or_ethertype =
2160                             rte_cpu_to_le_16(m0->vlan_tci);
2161                         tx_start_bd->bd_flags.as_bitfield |=
2162                             (X_ETH_OUTBAND_VLAN <<
2163                              ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2164                 } else {
2165                         if (IS_PF(sc))
2166                                 tx_start_bd->vlan_or_ethertype =
2167                                     rte_cpu_to_le_16(pkt_prod);
2168                         else {
2169                                 struct ether_hdr *eh
2170                                     = rte_pktmbuf_mtod(m0, struct ether_hdr *);
2171
2172                                 tx_start_bd->vlan_or_ethertype
2173                                     = rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2174                         }
2175                 }
2176
2177                 bd_prod = NEXT_TX_BD(bd_prod);
2178                 if (IS_VF(sc)) {
2179                         struct eth_tx_parse_bd_e2 *tx_parse_bd;
2180                         uint8_t *data = rte_pktmbuf_mtod(m0, uint8_t *);
2181
2182                         tx_parse_bd =
2183                             &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2184                         tx_parse_bd->parsing_data =
2185                             (1 << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2186
2187                         rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2188                                    &data[0], 2);
2189                         rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2190                                    &data[2], 2);
2191                         rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2192                                    &data[4], 2);
2193                         rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2194                                    &data[6], 2);
2195                         rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2196                                    &data[8], 2);
2197                         rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2198                                    &data[10], 2);
2199
2200                         tx_parse_bd->data.mac_addr.dst_hi =
2201                             rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2202                         tx_parse_bd->data.mac_addr.dst_mid =
2203                             rte_cpu_to_be_16(tx_parse_bd->data.
2204                                              mac_addr.dst_mid);
2205                         tx_parse_bd->data.mac_addr.dst_lo =
2206                             rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2207                         tx_parse_bd->data.mac_addr.src_hi =
2208                             rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2209                         tx_parse_bd->data.mac_addr.src_mid =
2210                             rte_cpu_to_be_16(tx_parse_bd->data.
2211                                              mac_addr.src_mid);
2212                         tx_parse_bd->data.mac_addr.src_lo =
2213                             rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2214
2215                         PMD_TX_LOG(DEBUG,
2216                                    "PBD dst %x %x %x src %x %x %x p_data %x",
2217                                    tx_parse_bd->data.mac_addr.dst_hi,
2218                                    tx_parse_bd->data.mac_addr.dst_mid,
2219                                    tx_parse_bd->data.mac_addr.dst_lo,
2220                                    tx_parse_bd->data.mac_addr.src_hi,
2221                                    tx_parse_bd->data.mac_addr.src_mid,
2222                                    tx_parse_bd->data.mac_addr.src_lo,
2223                                    tx_parse_bd->parsing_data);
2224                 }
2225
2226                 PMD_TX_LOG(DEBUG,
2227                            "start bd: nbytes %d flags %x vlan %x\n",
2228                            tx_start_bd->nbytes,
2229                            tx_start_bd->bd_flags.as_bitfield,
2230                            tx_start_bd->vlan_or_ethertype);
2231
2232                 bd_prod = NEXT_TX_BD(bd_prod);
2233                 pkt_prod++;
2234
2235                 if (TX_IDX(bd_prod) < 2) {
2236                         nbds++;
2237                 }
2238         }
2239
2240         txq->nb_tx_avail -= m_pkts << 1;
2241         txq->tx_bd_tail = bd_prod;
2242         txq->tx_pkt_tail = pkt_prod;
2243
2244         mb();
2245         fp->tx_db.data.prod += (m_pkts << 1) + nbds;
2246         DOORBELL(sc, txq->queue_id, fp->tx_db.raw);
2247         mb();
2248
2249         return 0;
2250 }
2251
2252 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2253 {
2254         return L2_ILT_LINES(sc);
2255 }
2256
2257 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2258 {
2259         struct ilt_client_info *ilt_client;
2260         struct ecore_ilt *ilt = sc->ilt;
2261         uint16_t line = 0;
2262
2263         PMD_INIT_FUNC_TRACE();
2264
2265         ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2266
2267         /* CDU */
2268         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2269         ilt_client->client_num = ILT_CLIENT_CDU;
2270         ilt_client->page_size = CDU_ILT_PAGE_SZ;
2271         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2272         ilt_client->start = line;
2273         line += bnx2x_cid_ilt_lines(sc);
2274
2275         if (CNIC_SUPPORT(sc)) {
2276                 line += CNIC_ILT_LINES;
2277         }
2278
2279         ilt_client->end = (line - 1);
2280
2281         /* QM */
2282         if (QM_INIT(sc->qm_cid_count)) {
2283                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2284                 ilt_client->client_num = ILT_CLIENT_QM;
2285                 ilt_client->page_size = QM_ILT_PAGE_SZ;
2286                 ilt_client->flags = 0;
2287                 ilt_client->start = line;
2288
2289                 /* 4 bytes for each cid */
2290                 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2291                                      QM_ILT_PAGE_SZ);
2292
2293                 ilt_client->end = (line - 1);
2294         }
2295
2296         if (CNIC_SUPPORT(sc)) {
2297                 /* SRC */
2298                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2299                 ilt_client->client_num = ILT_CLIENT_SRC;
2300                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2301                 ilt_client->flags = 0;
2302                 ilt_client->start = line;
2303                 line += SRC_ILT_LINES;
2304                 ilt_client->end = (line - 1);
2305
2306                 /* TM */
2307                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2308                 ilt_client->client_num = ILT_CLIENT_TM;
2309                 ilt_client->page_size = TM_ILT_PAGE_SZ;
2310                 ilt_client->flags = 0;
2311                 ilt_client->start = line;
2312                 line += TM_ILT_LINES;
2313                 ilt_client->end = (line - 1);
2314         }
2315
2316         assert((line <= ILT_MAX_LINES));
2317 }
2318
2319 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2320 {
2321         int i;
2322
2323         for (i = 0; i < sc->num_queues; i++) {
2324                 /* get the Rx buffer size for RX frames */
2325                 sc->fp[i].rx_buf_size =
2326                     (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2327
2328                 /* get the mbuf allocation size for RX frames */
2329                 if (sc->fp[i].rx_buf_size <= MCLBYTES) {
2330                         sc->fp[i].mbuf_alloc_size = MCLBYTES;
2331                 } else if (sc->fp[i].rx_buf_size <= BNX2X_PAGE_SIZE) {
2332                         sc->fp[i].mbuf_alloc_size = PAGE_SIZE;
2333                 } else {
2334                         sc->fp[i].mbuf_alloc_size = MJUM9BYTES;
2335                 }
2336         }
2337 }
2338
2339 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2340 {
2341
2342         sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2343
2344         return sc->ilt == NULL;
2345 }
2346
2347 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2348 {
2349         sc->ilt->lines = rte_calloc("",
2350                                     sizeof(struct ilt_line), ILT_MAX_LINES,
2351                                     RTE_CACHE_LINE_SIZE);
2352         return sc->ilt->lines == NULL;
2353 }
2354
2355 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2356 {
2357         rte_free(sc->ilt);
2358         sc->ilt = NULL;
2359 }
2360
2361 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2362 {
2363         if (sc->ilt->lines != NULL) {
2364                 rte_free(sc->ilt->lines);
2365                 sc->ilt->lines = NULL;
2366         }
2367 }
2368
2369 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2370 {
2371         uint32_t i;
2372
2373         for (i = 0; i < L2_ILT_LINES(sc); i++) {
2374                 sc->context[i].vcxt = NULL;
2375                 sc->context[i].size = 0;
2376         }
2377
2378         ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2379
2380         bnx2x_free_ilt_lines_mem(sc);
2381 }
2382
2383 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2384 {
2385         int context_size;
2386         int allocated;
2387         int i;
2388         char cdu_name[RTE_MEMZONE_NAMESIZE];
2389
2390         /*
2391          * Allocate memory for CDU context:
2392          * This memory is allocated separately and not in the generic ILT
2393          * functions because CDU differs in few aspects:
2394          * 1. There can be multiple entities allocating memory for context -
2395          * regular L2, CNIC, and SRIOV drivers. Each separately controls
2396          * its own ILT lines.
2397          * 2. Since CDU page-size is not a single 4KB page (which is the case
2398          * for the other ILT clients), to be efficient we want to support
2399          * allocation of sub-page-size in the last entry.
2400          * 3. Context pointers are used by the driver to pass to FW / update
2401          * the context (for the other ILT clients the pointers are used just to
2402          * free the memory during unload).
2403          */
2404         context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2405         for (i = 0, allocated = 0; allocated < context_size; i++) {
2406                 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2407                                           (context_size - allocated));
2408
2409                 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2410                 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2411                                   &sc->context[i].vcxt_dma,
2412                                   cdu_name, BNX2X_PAGE_SIZE) != 0) {
2413                         bnx2x_free_mem(sc);
2414                         return -1;
2415                 }
2416
2417                 sc->context[i].vcxt =
2418                     (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2419
2420                 allocated += sc->context[i].size;
2421         }
2422
2423         bnx2x_alloc_ilt_lines_mem(sc);
2424
2425         if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2426                 PMD_DRV_LOG(NOTICE, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2427                 bnx2x_free_mem(sc);
2428                 return -1;
2429         }
2430
2431         return 0;
2432 }
2433
2434 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2435 {
2436         sc->fw_stats_num = 0;
2437
2438         sc->fw_stats_req_size = 0;
2439         sc->fw_stats_req = NULL;
2440         sc->fw_stats_req_mapping = 0;
2441
2442         sc->fw_stats_data_size = 0;
2443         sc->fw_stats_data = NULL;
2444         sc->fw_stats_data_mapping = 0;
2445 }
2446
2447 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2448 {
2449         uint8_t num_queue_stats;
2450         int num_groups, vf_headroom = 0;
2451
2452         /* number of queues for statistics is number of eth queues */
2453         num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2454
2455         /*
2456          * Total number of FW statistics requests =
2457          *   1 for port stats + 1 for PF stats + num of queues
2458          */
2459         sc->fw_stats_num = (2 + num_queue_stats);
2460
2461         /*
2462          * Request is built from stats_query_header and an array of
2463          * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2464          * rules. The real number or requests is configured in the
2465          * stats_query_header.
2466          */
2467         num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2468         if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2469                 num_groups++;
2470
2471         sc->fw_stats_req_size =
2472             (sizeof(struct stats_query_header) +
2473              (num_groups * sizeof(struct stats_query_cmd_group)));
2474
2475         /*
2476          * Data for statistics requests + stats_counter.
2477          * stats_counter holds per-STORM counters that are incremented when
2478          * STORM has finished with the current request. Memory for FCoE
2479          * offloaded statistics are counted anyway, even if they will not be sent.
2480          * VF stats are not accounted for here as the data of VF stats is stored
2481          * in memory allocated by the VF, not here.
2482          */
2483         sc->fw_stats_data_size =
2484             (sizeof(struct stats_counter) +
2485              sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2486              /* sizeof(struct fcoe_statistics_params) + */
2487              (sizeof(struct per_queue_stats) * num_queue_stats));
2488
2489         if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2490                           &sc->fw_stats_dma, "fw_stats",
2491                           RTE_CACHE_LINE_SIZE) != 0) {
2492                 bnx2x_free_fw_stats_mem(sc);
2493                 return -1;
2494         }
2495
2496         /* set up the shortcuts */
2497
2498         sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2499         sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2500
2501         sc->fw_stats_data =
2502             (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2503                                          sc->fw_stats_req_size);
2504         sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2505                                      sc->fw_stats_req_size);
2506
2507         return 0;
2508 }
2509
2510 /*
2511  * Bits map:
2512  * 0-7  - Engine0 load counter.
2513  * 8-15 - Engine1 load counter.
2514  * 16   - Engine0 RESET_IN_PROGRESS bit.
2515  * 17   - Engine1 RESET_IN_PROGRESS bit.
2516  * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
2517  *        function on the engine
2518  * 19   - Engine1 ONE_IS_LOADED.
2519  * 20   - Chip reset flow bit. When set none-leader must wait for both engines
2520  *        leader to complete (check for both RESET_IN_PROGRESS bits and not
2521  *        for just the one belonging to its engine).
2522  */
2523 #define BNX2X_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
2524 #define BNX2X_PATH0_LOAD_CNT_MASK   0x000000ff
2525 #define BNX2X_PATH0_LOAD_CNT_SHIFT  0
2526 #define BNX2X_PATH1_LOAD_CNT_MASK   0x0000ff00
2527 #define BNX2X_PATH1_LOAD_CNT_SHIFT  8
2528 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2529 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2530 #define BNX2X_GLOBAL_RESET_BIT      0x00040000
2531
2532 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2533 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2534 {
2535         uint32_t val;
2536         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2537         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2538         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2539         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2540 }
2541
2542 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2543 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2544 {
2545         uint32_t val;
2546         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2547         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2548         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2549         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2550 }
2551
2552 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2553 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2554 {
2555         return (REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT);
2556 }
2557
2558 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2559 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2560 {
2561         uint32_t val;
2562         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2563             BNX2X_PATH0_RST_IN_PROG_BIT;
2564
2565         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2566
2567         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2568         /* Clear the bit */
2569         val &= ~bit;
2570         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2571
2572         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2573 }
2574
2575 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2576 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2577 {
2578         uint32_t val;
2579         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2580             BNX2X_PATH0_RST_IN_PROG_BIT;
2581
2582         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2583
2584         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2585         /* Set the bit */
2586         val |= bit;
2587         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2588
2589         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2590 }
2591
2592 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2593 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2594 {
2595         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2596         uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2597             BNX2X_PATH0_RST_IN_PROG_BIT;
2598
2599         /* return false if bit is set */
2600         return (val & bit) ? FALSE : TRUE;
2601 }
2602
2603 /* get the load status for an engine, should be run under rtnl lock */
2604 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2605 {
2606         uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2607             BNX2X_PATH0_LOAD_CNT_MASK;
2608         uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2609             BNX2X_PATH0_LOAD_CNT_SHIFT;
2610         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2611
2612         val = ((val & mask) >> shift);
2613
2614         return (val != 0);
2615 }
2616
2617 /* set pf load mark */
2618 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2619 {
2620         uint32_t val;
2621         uint32_t val1;
2622         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2623             BNX2X_PATH0_LOAD_CNT_MASK;
2624         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2625             BNX2X_PATH0_LOAD_CNT_SHIFT;
2626
2627         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2628
2629         PMD_INIT_FUNC_TRACE();
2630
2631         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2632
2633         /* get the current counter value */
2634         val1 = ((val & mask) >> shift);
2635
2636         /* set bit of this PF */
2637         val1 |= (1 << SC_ABS_FUNC(sc));
2638
2639         /* clear the old value */
2640         val &= ~mask;
2641
2642         /* set the new one */
2643         val |= ((val1 << shift) & mask);
2644
2645         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2646
2647         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2648 }
2649
2650 /* clear pf load mark */
2651 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2652 {
2653         uint32_t val1, val;
2654         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2655             BNX2X_PATH0_LOAD_CNT_MASK;
2656         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2657             BNX2X_PATH0_LOAD_CNT_SHIFT;
2658
2659         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2660         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2661
2662         /* get the current counter value */
2663         val1 = (val & mask) >> shift;
2664
2665         /* clear bit of that PF */
2666         val1 &= ~(1 << SC_ABS_FUNC(sc));
2667
2668         /* clear the old value */
2669         val &= ~mask;
2670
2671         /* set the new one */
2672         val |= ((val1 << shift) & mask);
2673
2674         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2675         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2676         return val1 != 0;
2677 }
2678
2679 /* send load requrest to mcp and analyze response */
2680 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2681 {
2682         PMD_INIT_FUNC_TRACE();
2683
2684         /* init fw_seq */
2685         sc->fw_seq =
2686             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2687              DRV_MSG_SEQ_NUMBER_MASK);
2688
2689         PMD_DRV_LOG(DEBUG, "initial fw_seq 0x%04x", sc->fw_seq);
2690
2691 #ifdef BNX2X_PULSE
2692         /* get the current FW pulse sequence */
2693         sc->fw_drv_pulse_wr_seq =
2694             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2695              DRV_PULSE_SEQ_MASK);
2696 #else
2697         /* set ALWAYS_ALIVE bit in shmem */
2698         sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2699         bnx2x_drv_pulse(sc);
2700 #endif
2701
2702         /* load request */
2703         (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2704                                       DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2705
2706         /* if the MCP fails to respond we must abort */
2707         if (!(*load_code)) {
2708                 PMD_DRV_LOG(NOTICE, "MCP response failure!");
2709                 return -1;
2710         }
2711
2712         /* if MCP refused then must abort */
2713         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2714                 PMD_DRV_LOG(NOTICE, "MCP refused load request");
2715                 return -1;
2716         }
2717
2718         return 0;
2719 }
2720
2721 /*
2722  * Check whether another PF has already loaded FW to chip. In virtualized
2723  * environments a pf from anoth VM may have already initialized the device
2724  * including loading FW.
2725  */
2726 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2727 {
2728         uint32_t my_fw, loaded_fw;
2729
2730         /* is another pf loaded on this engine? */
2731         if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2732             (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2733                 /* build my FW version dword */
2734                 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2735                          (BNX2X_5710_FW_MINOR_VERSION << 8) +
2736                          (BNX2X_5710_FW_REVISION_VERSION << 16) +
2737                          (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2738
2739                 /* read loaded FW from chip */
2740                 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2741                 PMD_DRV_LOG(DEBUG, "loaded FW 0x%08x / my FW 0x%08x",
2742                             loaded_fw, my_fw);
2743
2744                 /* abort nic load if version mismatch */
2745                 if (my_fw != loaded_fw) {
2746                         PMD_DRV_LOG(NOTICE,
2747                                     "FW 0x%08x already loaded (mine is 0x%08x)",
2748                                     loaded_fw, my_fw);
2749                         return -1;
2750                 }
2751         }
2752
2753         return 0;
2754 }
2755
2756 /* mark PMF if applicable */
2757 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2758 {
2759         uint32_t ncsi_oem_data_addr;
2760
2761         PMD_INIT_FUNC_TRACE();
2762
2763         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2764             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2765             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2766                 /*
2767                  * Barrier here for ordering between the writing to sc->port.pmf here
2768                  * and reading it from the periodic task.
2769                  */
2770                 sc->port.pmf = 1;
2771                 mb();
2772         } else {
2773                 sc->port.pmf = 0;
2774         }
2775
2776         PMD_DRV_LOG(DEBUG, "pmf %d", sc->port.pmf);
2777
2778         if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2779                 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2780                         ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2781                         if (ncsi_oem_data_addr) {
2782                                 REG_WR(sc,
2783                                        (ncsi_oem_data_addr +
2784                                         offsetof(struct glob_ncsi_oem_data,
2785                                                  driver_version)), 0);
2786                         }
2787                 }
2788         }
2789 }
2790
2791 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2792 {
2793         int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2794         int abs_func;
2795         int vn;
2796
2797         if (BNX2X_NOMCP(sc)) {
2798                 return;         /* what should be the default bvalue in this case */
2799         }
2800
2801         /*
2802          * The formula for computing the absolute function number is...
2803          * For 2 port configuration (4 functions per port):
2804          *   abs_func = 2 * vn + SC_PORT + SC_PATH
2805          * For 4 port configuration (2 functions per port):
2806          *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2807          */
2808         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2809                 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2810                 if (abs_func >= E1H_FUNC_MAX) {
2811                         break;
2812                 }
2813                 sc->devinfo.mf_info.mf_config[vn] =
2814                     MFCFG_RD(sc, func_mf_config[abs_func].config);
2815         }
2816
2817         if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2818             FUNC_MF_CFG_FUNC_DISABLED) {
2819                 PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
2820                 sc->flags |= BNX2X_MF_FUNC_DIS;
2821         } else {
2822                 PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
2823                 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2824         }
2825 }
2826
2827 /* acquire split MCP access lock register */
2828 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2829 {
2830         uint32_t j, val;
2831
2832         for (j = 0; j < 1000; j++) {
2833                 val = (1UL << 31);
2834                 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2835                 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2836                 if (val & (1L << 31))
2837                         break;
2838
2839                 DELAY(5000);
2840         }
2841
2842         if (!(val & (1L << 31))) {
2843                 PMD_DRV_LOG(NOTICE, "Cannot acquire MCP access lock register");
2844                 return -1;
2845         }
2846
2847         return 0;
2848 }
2849
2850 /* release split MCP access lock register */
2851 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2852 {
2853         REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2854 }
2855
2856 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2857 {
2858         int port = SC_PORT(sc);
2859         uint32_t ext_phy_config;
2860
2861         /* mark the failure */
2862         ext_phy_config =
2863             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2864
2865         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2866         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2867         SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2868                  ext_phy_config);
2869
2870         /* log the failure */
2871         PMD_DRV_LOG(INFO,
2872                     "Fan Failure has caused the driver to shutdown "
2873                     "the card to prevent permanent damage. "
2874                     "Please contact OEM Support for assistance");
2875
2876         rte_panic("Schedule task to handle fan failure");
2877 }
2878
2879 /* this function is called upon a link interrupt */
2880 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2881 {
2882         uint32_t pause_enabled = 0;
2883         struct host_port_stats *pstats;
2884         int cmng_fns;
2885
2886         /* Make sure that we are synced with the current statistics */
2887         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2888
2889         elink_link_update(&sc->link_params, &sc->link_vars);
2890
2891         if (sc->link_vars.link_up) {
2892
2893                 /* dropless flow control */
2894                 if (sc->dropless_fc) {
2895                         pause_enabled = 0;
2896
2897                         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2898                                 pause_enabled = 1;
2899                         }
2900
2901                         REG_WR(sc,
2902                                (BAR_USTRORM_INTMEM +
2903                                 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2904                                pause_enabled);
2905                 }
2906
2907                 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2908                         pstats = BNX2X_SP(sc, port_stats);
2909                         /* reset old mac stats */
2910                         memset(&(pstats->mac_stx[0]), 0,
2911                                sizeof(struct mac_stx));
2912                 }
2913
2914                 if (sc->state == BNX2X_STATE_OPEN) {
2915                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2916                 }
2917         }
2918
2919         if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2920                 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2921
2922                 if (cmng_fns != CMNG_FNS_NONE) {
2923                         bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2924                         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2925                 }
2926         }
2927
2928         bnx2x_link_report(sc);
2929
2930         if (IS_MF(sc)) {
2931                 bnx2x_link_sync_notify(sc);
2932         }
2933 }
2934
2935 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2936 {
2937         int port = SC_PORT(sc);
2938         uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2939             MISC_REG_AEU_MASK_ATTN_FUNC_0;
2940         uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2941             NIG_REG_MASK_INTERRUPT_PORT0;
2942         uint32_t aeu_mask;
2943         uint32_t nig_mask = 0;
2944         uint32_t reg_addr;
2945         uint32_t igu_acked;
2946         uint32_t cnt;
2947
2948         if (sc->attn_state & asserted) {
2949                 PMD_DRV_LOG(ERR, "IGU ERROR attn=0x%08x", asserted);
2950         }
2951
2952         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2953
2954         aeu_mask = REG_RD(sc, aeu_addr);
2955
2956         aeu_mask &= ~(asserted & 0x3ff);
2957
2958         REG_WR(sc, aeu_addr, aeu_mask);
2959
2960         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2961
2962         sc->attn_state |= asserted;
2963
2964         if (asserted & ATTN_HARD_WIRED_MASK) {
2965                 if (asserted & ATTN_NIG_FOR_FUNC) {
2966
2967                         /* save nig interrupt mask */
2968                         nig_mask = REG_RD(sc, nig_int_mask_addr);
2969
2970                         /* If nig_mask is not set, no need to call the update function */
2971                         if (nig_mask) {
2972                                 REG_WR(sc, nig_int_mask_addr, 0);
2973
2974                                 bnx2x_link_attn(sc);
2975                         }
2976
2977                         /* handle unicore attn? */
2978                 }
2979
2980                 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2981                         PMD_DRV_LOG(DEBUG, "ATTN_SW_TIMER_4_FUNC!");
2982                 }
2983
2984                 if (asserted & GPIO_2_FUNC) {
2985                         PMD_DRV_LOG(DEBUG, "GPIO_2_FUNC!");
2986                 }
2987
2988                 if (asserted & GPIO_3_FUNC) {
2989                         PMD_DRV_LOG(DEBUG, "GPIO_3_FUNC!");
2990                 }
2991
2992                 if (asserted & GPIO_4_FUNC) {
2993                         PMD_DRV_LOG(DEBUG, "GPIO_4_FUNC!");
2994                 }
2995
2996                 if (port == 0) {
2997                         if (asserted & ATTN_GENERAL_ATTN_1) {
2998                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_1!");
2999                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3000                         }
3001                         if (asserted & ATTN_GENERAL_ATTN_2) {
3002                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_2!");
3003                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3004                         }
3005                         if (asserted & ATTN_GENERAL_ATTN_3) {
3006                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_3!");
3007                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3008                         }
3009                 } else {
3010                         if (asserted & ATTN_GENERAL_ATTN_4) {
3011                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_4!");
3012                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3013                         }
3014                         if (asserted & ATTN_GENERAL_ATTN_5) {
3015                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_5!");
3016                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3017                         }
3018                         if (asserted & ATTN_GENERAL_ATTN_6) {
3019                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_6!");
3020                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3021                         }
3022                 }
3023         }
3024         /* hardwired */
3025         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3026                 reg_addr =
3027                     (HC_REG_COMMAND_REG + port * 32 +
3028                      COMMAND_REG_ATTN_BITS_SET);
3029         } else {
3030                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3031         }
3032
3033         PMD_DRV_LOG(DEBUG, "about to mask 0x%08x at %s addr 0x%08x",
3034                     asserted,
3035                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3036                     reg_addr);
3037         REG_WR(sc, reg_addr, asserted);
3038
3039         /* now set back the mask */
3040         if (asserted & ATTN_NIG_FOR_FUNC) {
3041                 /*
3042                  * Verify that IGU ack through BAR was written before restoring
3043                  * NIG mask. This loop should exit after 2-3 iterations max.
3044                  */
3045                 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3046                         cnt = 0;
3047
3048                         do {
3049                                 igu_acked =
3050                                     REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3051                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3052                                  && (++cnt < MAX_IGU_ATTN_ACK_TO));
3053
3054                         if (!igu_acked) {
3055                                 PMD_DRV_LOG(ERR,
3056                                             "Failed to verify IGU ack on time");
3057                         }
3058
3059                         mb();
3060                 }
3061
3062                 REG_WR(sc, nig_int_mask_addr, nig_mask);
3063
3064         }
3065 }
3066
3067 static void
3068 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3069                      __rte_unused const char *blk)
3070 {
3071         PMD_DRV_LOG(INFO, "%s%s", idx ? ", " : "", blk);
3072 }
3073
3074 static int
3075 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3076                               uint8_t print)
3077 {
3078         uint32_t cur_bit = 0;
3079         int i = 0;
3080
3081         for (i = 0; sig; i++) {
3082                 cur_bit = ((uint32_t) 0x1 << i);
3083                 if (sig & cur_bit) {
3084                         switch (cur_bit) {
3085                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3086                                 if (print)
3087                                         bnx2x_print_next_block(sc, par_num++,
3088                                                              "BRB");
3089                                 break;
3090                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3091                                 if (print)
3092                                         bnx2x_print_next_block(sc, par_num++,
3093                                                              "PARSER");
3094                                 break;
3095                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3096                                 if (print)
3097                                         bnx2x_print_next_block(sc, par_num++,
3098                                                              "TSDM");
3099                                 break;
3100                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3101                                 if (print)
3102                                         bnx2x_print_next_block(sc, par_num++,
3103                                                              "SEARCHER");
3104                                 break;
3105                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3106                                 if (print)
3107                                         bnx2x_print_next_block(sc, par_num++,
3108                                                              "TCM");
3109                                 break;
3110                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3111                                 if (print)
3112                                         bnx2x_print_next_block(sc, par_num++,
3113                                                              "TSEMI");
3114                                 break;
3115                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3116                                 if (print)
3117                                         bnx2x_print_next_block(sc, par_num++,
3118                                                              "XPB");
3119                                 break;
3120                         }
3121
3122                         /* Clear the bit */
3123                         sig &= ~cur_bit;
3124                 }
3125         }
3126
3127         return par_num;
3128 }
3129
3130 static int
3131 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3132                               uint8_t * global, uint8_t print)
3133 {
3134         int i = 0;
3135         uint32_t cur_bit = 0;
3136         for (i = 0; sig; i++) {
3137                 cur_bit = ((uint32_t) 0x1 << i);
3138                 if (sig & cur_bit) {
3139                         switch (cur_bit) {
3140                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3141                                 if (print)
3142                                         bnx2x_print_next_block(sc, par_num++,
3143                                                              "PBF");
3144                                 break;
3145                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3146                                 if (print)
3147                                         bnx2x_print_next_block(sc, par_num++,
3148                                                              "QM");
3149                                 break;
3150                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3151                                 if (print)
3152                                         bnx2x_print_next_block(sc, par_num++,
3153                                                              "TM");
3154                                 break;
3155                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3156                                 if (print)
3157                                         bnx2x_print_next_block(sc, par_num++,
3158                                                              "XSDM");
3159                                 break;
3160                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3161                                 if (print)
3162                                         bnx2x_print_next_block(sc, par_num++,
3163                                                              "XCM");
3164                                 break;
3165                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3166                                 if (print)
3167                                         bnx2x_print_next_block(sc, par_num++,
3168                                                              "XSEMI");
3169                                 break;
3170                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3171                                 if (print)
3172                                         bnx2x_print_next_block(sc, par_num++,
3173                                                              "DOORBELLQ");
3174                                 break;
3175                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3176                                 if (print)
3177                                         bnx2x_print_next_block(sc, par_num++,
3178                                                              "NIG");
3179                                 break;
3180                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3181                                 if (print)
3182                                         bnx2x_print_next_block(sc, par_num++,
3183                                                              "VAUX PCI CORE");
3184                                 *global = TRUE;
3185                                 break;
3186                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3187                                 if (print)
3188                                         bnx2x_print_next_block(sc, par_num++,
3189                                                              "DEBUG");
3190                                 break;
3191                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3192                                 if (print)
3193                                         bnx2x_print_next_block(sc, par_num++,
3194                                                              "USDM");
3195                                 break;
3196                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3197                                 if (print)
3198                                         bnx2x_print_next_block(sc, par_num++,
3199                                                              "UCM");
3200                                 break;
3201                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3202                                 if (print)
3203                                         bnx2x_print_next_block(sc, par_num++,
3204                                                              "USEMI");
3205                                 break;
3206                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3207                                 if (print)
3208                                         bnx2x_print_next_block(sc, par_num++,
3209                                                              "UPB");
3210                                 break;
3211                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3212                                 if (print)
3213                                         bnx2x_print_next_block(sc, par_num++,
3214                                                              "CSDM");
3215                                 break;
3216                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3217                                 if (print)
3218                                         bnx2x_print_next_block(sc, par_num++,
3219                                                              "CCM");
3220                                 break;
3221                         }
3222
3223                         /* Clear the bit */
3224                         sig &= ~cur_bit;
3225                 }
3226         }
3227
3228         return par_num;
3229 }
3230
3231 static int
3232 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3233                               uint8_t print)
3234 {
3235         uint32_t cur_bit = 0;
3236         int i = 0;
3237
3238         for (i = 0; sig; i++) {
3239                 cur_bit = ((uint32_t) 0x1 << i);
3240                 if (sig & cur_bit) {
3241                         switch (cur_bit) {
3242                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3243                                 if (print)
3244                                         bnx2x_print_next_block(sc, par_num++,
3245                                                              "CSEMI");
3246                                 break;
3247                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3248                                 if (print)
3249                                         bnx2x_print_next_block(sc, par_num++,
3250                                                              "PXP");
3251                                 break;
3252                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3253                                 if (print)
3254                                         bnx2x_print_next_block(sc, par_num++,
3255                                                              "PXPPCICLOCKCLIENT");
3256                                 break;
3257                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3258                                 if (print)
3259                                         bnx2x_print_next_block(sc, par_num++,
3260                                                              "CFC");
3261                                 break;
3262                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3263                                 if (print)
3264                                         bnx2x_print_next_block(sc, par_num++,
3265                                                              "CDU");
3266                                 break;
3267                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3268                                 if (print)
3269                                         bnx2x_print_next_block(sc, par_num++,
3270                                                              "DMAE");
3271                                 break;
3272                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3273                                 if (print)
3274                                         bnx2x_print_next_block(sc, par_num++,
3275                                                              "IGU");
3276                                 break;
3277                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3278                                 if (print)
3279                                         bnx2x_print_next_block(sc, par_num++,
3280                                                              "MISC");
3281                                 break;
3282                         }
3283
3284                         /* Clear the bit */
3285                         sig &= ~cur_bit;
3286                 }
3287         }
3288
3289         return par_num;
3290 }
3291
3292 static int
3293 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3294                               uint8_t * global, uint8_t print)
3295 {
3296         uint32_t cur_bit = 0;
3297         int i = 0;
3298
3299         for (i = 0; sig; i++) {
3300                 cur_bit = ((uint32_t) 0x1 << i);
3301                 if (sig & cur_bit) {
3302                         switch (cur_bit) {
3303                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3304                                 if (print)
3305                                         bnx2x_print_next_block(sc, par_num++,
3306                                                              "MCP ROM");
3307                                 *global = TRUE;
3308                                 break;
3309                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3310                                 if (print)
3311                                         bnx2x_print_next_block(sc, par_num++,
3312                                                              "MCP UMP RX");
3313                                 *global = TRUE;
3314                                 break;
3315                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3316                                 if (print)
3317                                         bnx2x_print_next_block(sc, par_num++,
3318                                                              "MCP UMP TX");
3319                                 *global = TRUE;
3320                                 break;
3321                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3322                                 if (print)
3323                                         bnx2x_print_next_block(sc, par_num++,
3324                                                              "MCP SCPAD");
3325                                 *global = TRUE;
3326                                 break;
3327                         }
3328
3329                         /* Clear the bit */
3330                         sig &= ~cur_bit;
3331                 }
3332         }
3333
3334         return par_num;
3335 }
3336
3337 static int
3338 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3339                               uint8_t print)
3340 {
3341         uint32_t cur_bit = 0;
3342         int i = 0;
3343
3344         for (i = 0; sig; i++) {
3345                 cur_bit = ((uint32_t) 0x1 << i);
3346                 if (sig & cur_bit) {
3347                         switch (cur_bit) {
3348                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3349                                 if (print)
3350                                         bnx2x_print_next_block(sc, par_num++,
3351                                                              "PGLUE_B");
3352                                 break;
3353                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3354                                 if (print)
3355                                         bnx2x_print_next_block(sc, par_num++,
3356                                                              "ATC");
3357                                 break;
3358                         }
3359
3360                         /* Clear the bit */
3361                         sig &= ~cur_bit;
3362                 }
3363         }
3364
3365         return par_num;
3366 }
3367
3368 static uint8_t
3369 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3370                 uint32_t * sig)
3371 {
3372         int par_num = 0;
3373
3374         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3375             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3376             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3377             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3378             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3379                 PMD_DRV_LOG(ERR,
3380                             "Parity error: HW block parity attention:"
3381                             "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3382                             (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3383                             (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3384                             (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3385                             (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3386                             (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3387
3388                 if (print)
3389                         PMD_DRV_LOG(INFO, "Parity errors detected in blocks: ");
3390
3391                 par_num =
3392                     bnx2x_check_blocks_with_parity0(sc, sig[0] &
3393                                                   HW_PRTY_ASSERT_SET_0,
3394                                                   par_num, print);
3395                 par_num =
3396                     bnx2x_check_blocks_with_parity1(sc, sig[1] &
3397                                                   HW_PRTY_ASSERT_SET_1,
3398                                                   par_num, global, print);
3399                 par_num =
3400                     bnx2x_check_blocks_with_parity2(sc, sig[2] &
3401                                                   HW_PRTY_ASSERT_SET_2,
3402                                                   par_num, print);
3403                 par_num =
3404                     bnx2x_check_blocks_with_parity3(sc, sig[3] &
3405                                                   HW_PRTY_ASSERT_SET_3,
3406                                                   par_num, global, print);
3407                 par_num =
3408                     bnx2x_check_blocks_with_parity4(sc, sig[4] &
3409                                                   HW_PRTY_ASSERT_SET_4,
3410                                                   par_num, print);
3411
3412                 if (print)
3413                         PMD_DRV_LOG(INFO, "");
3414
3415                 return TRUE;
3416         }
3417
3418         return FALSE;
3419 }
3420
3421 static uint8_t
3422 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3423 {
3424         struct attn_route attn = { {0} };
3425         int port = SC_PORT(sc);
3426
3427         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3428         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3429         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3430         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3431
3432         if (!CHIP_IS_E1x(sc))
3433                 attn.sig[4] =
3434                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3435
3436         return bnx2x_parity_attn(sc, global, print, attn.sig);
3437 }
3438
3439 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3440 {
3441         uint32_t val;
3442
3443         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3444                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3445                 PMD_DRV_LOG(INFO, "ERROR: PGLUE hw attention 0x%08x", val);
3446                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3447                         PMD_DRV_LOG(INFO,
3448                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3449                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3450                         PMD_DRV_LOG(INFO,
3451                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3452                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3453                         PMD_DRV_LOG(INFO,
3454                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3455                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3456                         PMD_DRV_LOG(INFO,
3457                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3458                 if (val &
3459                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3460                         PMD_DRV_LOG(INFO,
3461                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3462                 if (val &
3463                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3464                         PMD_DRV_LOG(INFO,
3465                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3466                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3467                         PMD_DRV_LOG(INFO,
3468                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3469                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3470                         PMD_DRV_LOG(INFO,
3471                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3472                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3473                         PMD_DRV_LOG(INFO,
3474                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3475         }
3476
3477         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3478                 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3479                 PMD_DRV_LOG(INFO, "ERROR: ATC hw attention 0x%08x", val);
3480                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3481                         PMD_DRV_LOG(INFO,
3482                                     "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3483                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3484                         PMD_DRV_LOG(INFO,
3485                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3486                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3487                         PMD_DRV_LOG(INFO,
3488                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3489                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3490                         PMD_DRV_LOG(INFO,
3491                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3492                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3493                         PMD_DRV_LOG(INFO,
3494                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3495                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3496                         PMD_DRV_LOG(INFO,
3497                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3498         }
3499
3500         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3501                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3502                 PMD_DRV_LOG(INFO,
3503                             "ERROR: FATAL parity attention set4 0x%08x",
3504                             (uint32_t) (attn &
3505                                         (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3506                                          |
3507                                          AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3508         }
3509 }
3510
3511 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3512 {
3513         int port = SC_PORT(sc);
3514
3515         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3516 }
3517
3518 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3519 {
3520         int port = SC_PORT(sc);
3521
3522         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3523 }
3524
3525 /*
3526  * called due to MCP event (on pmf):
3527  *   reread new bandwidth configuration
3528  *   configure FW
3529  *   notify others function about the change
3530  */
3531 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3532 {
3533         if (sc->link_vars.link_up) {
3534                 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3535                 bnx2x_link_sync_notify(sc);
3536         }
3537
3538         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3539 }
3540
3541 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3542 {
3543         bnx2x_config_mf_bw(sc);
3544         bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3545 }
3546
3547 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3548 {
3549         bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3550 }
3551
3552 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3553
3554 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3555 {
3556         struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3557
3558         strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3559                 ETH_STAT_INFO_VERSION_LEN);
3560
3561         sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3562                                               DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3563                                               ether_stat->mac_local + MAC_PAD,
3564                                               MAC_PAD, ETH_ALEN);
3565
3566         ether_stat->mtu_size = sc->mtu;
3567
3568         ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3569         ether_stat->promiscuous_mode = 0;       // (flags & PROMISC) ? 1 : 0;
3570
3571         ether_stat->txq_size = sc->tx_ring_size;
3572         ether_stat->rxq_size = sc->rx_ring_size;
3573 }
3574
3575 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3576 {
3577         enum drv_info_opcode op_code;
3578         uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3579
3580         /* if drv_info version supported by MFW doesn't match - send NACK */
3581         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3582                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3583                 return;
3584         }
3585
3586         op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3587                    DRV_INFO_CONTROL_OP_CODE_SHIFT);
3588
3589         memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3590
3591         switch (op_code) {
3592         case ETH_STATS_OPCODE:
3593                 bnx2x_drv_info_ether_stat(sc);
3594                 break;
3595         case FCOE_STATS_OPCODE:
3596         case ISCSI_STATS_OPCODE:
3597         default:
3598                 /* if op code isn't supported - send NACK */
3599                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3600                 return;
3601         }
3602
3603         /*
3604          * If we got drv_info attn from MFW then these fields are defined in
3605          * shmem2 for sure
3606          */
3607         SHMEM2_WR(sc, drv_info_host_addr_lo,
3608                   U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3609         SHMEM2_WR(sc, drv_info_host_addr_hi,
3610                   U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3611
3612         bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3613 }
3614
3615 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3616 {
3617         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3618 /*
3619  * This is the only place besides the function initialization
3620  * where the sc->flags can change so it is done without any
3621  * locks
3622  */
3623                 if (sc->devinfo.
3624                     mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3625                         PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
3626                         sc->flags |= BNX2X_MF_FUNC_DIS;
3627                         bnx2x_e1h_disable(sc);
3628                 } else {
3629                         PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
3630                         sc->flags &= ~BNX2X_MF_FUNC_DIS;
3631                         bnx2x_e1h_enable(sc);
3632                 }
3633                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3634         }
3635
3636         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3637                 bnx2x_config_mf_bw(sc);
3638                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3639         }
3640
3641         /* Report results to MCP */
3642         if (dcc_event)
3643                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3644         else
3645                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3646 }
3647
3648 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3649 {
3650         int port = SC_PORT(sc);
3651         uint32_t val;
3652
3653         sc->port.pmf = 1;
3654
3655         /*
3656          * We need the mb() to ensure the ordering between the writing to
3657          * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3658          */
3659         mb();
3660
3661         /* enable nig attention */
3662         val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3663         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3664                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3665                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3666         } else if (!CHIP_IS_E1x(sc)) {
3667                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3668                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3669         }
3670
3671         bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3672 }
3673
3674 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3675 {
3676         char last_idx;
3677         int i, rc = 0;
3678         __rte_unused uint32_t row0, row1, row2, row3;
3679
3680         /* XSTORM */
3681         last_idx =
3682             REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3683         if (last_idx)
3684                 PMD_DRV_LOG(ERR, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3685
3686         /* print the asserts */
3687         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3688
3689                 row0 =
3690                     REG_RD(sc,
3691                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3692                 row1 =
3693                     REG_RD(sc,
3694                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3695                            4);
3696                 row2 =
3697                     REG_RD(sc,
3698                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3699                            8);
3700                 row3 =
3701                     REG_RD(sc,
3702                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3703                            12);
3704
3705                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3706                         PMD_DRV_LOG(ERR,
3707                                     "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3708                                     i, row3, row2, row1, row0);
3709                         rc++;
3710                 } else {
3711                         break;
3712                 }
3713         }
3714
3715         /* TSTORM */
3716         last_idx =
3717             REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3718         if (last_idx) {
3719                 PMD_DRV_LOG(ERR, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3720         }
3721
3722         /* print the asserts */
3723         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3724
3725                 row0 =
3726                     REG_RD(sc,
3727                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3728                 row1 =
3729                     REG_RD(sc,
3730                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3731                            4);
3732                 row2 =
3733                     REG_RD(sc,
3734                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3735                            8);
3736                 row3 =
3737                     REG_RD(sc,
3738                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3739                            12);
3740
3741                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3742                         PMD_DRV_LOG(ERR,
3743                                     "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3744                                     i, row3, row2, row1, row0);
3745                         rc++;
3746                 } else {
3747                         break;
3748                 }
3749         }
3750
3751         /* CSTORM */
3752         last_idx =
3753             REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3754         if (last_idx) {
3755                 PMD_DRV_LOG(ERR, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3756         }
3757
3758         /* print the asserts */
3759         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3760
3761                 row0 =
3762                     REG_RD(sc,
3763                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3764                 row1 =
3765                     REG_RD(sc,
3766                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3767                            4);
3768                 row2 =
3769                     REG_RD(sc,
3770                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3771                            8);
3772                 row3 =
3773                     REG_RD(sc,
3774                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3775                            12);
3776
3777                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3778                         PMD_DRV_LOG(ERR,
3779                                     "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3780                                     i, row3, row2, row1, row0);
3781                         rc++;
3782                 } else {
3783                         break;
3784                 }
3785         }
3786
3787         /* USTORM */
3788         last_idx =
3789             REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3790         if (last_idx) {
3791                 PMD_DRV_LOG(ERR, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3792         }
3793
3794         /* print the asserts */
3795         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3796
3797                 row0 =
3798                     REG_RD(sc,
3799                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3800                 row1 =
3801                     REG_RD(sc,
3802                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3803                            4);
3804                 row2 =
3805                     REG_RD(sc,
3806                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3807                            8);
3808                 row3 =
3809                     REG_RD(sc,
3810                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3811                            12);
3812
3813                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3814                         PMD_DRV_LOG(ERR,
3815                                     "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3816                                     i, row3, row2, row1, row0);
3817                         rc++;
3818                 } else {
3819                         break;
3820                 }
3821         }
3822
3823         return rc;
3824 }
3825
3826 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3827 {
3828         int func = SC_FUNC(sc);
3829         uint32_t val;
3830
3831         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3832
3833                 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3834
3835                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3836                         bnx2x_read_mf_cfg(sc);
3837                         sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3838                             MFCFG_RD(sc,
3839                                      func_mf_config[SC_ABS_FUNC(sc)].config);
3840                         val =
3841                             SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3842
3843                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3844                                 bnx2x_dcc_event(sc,
3845                                               (val &
3846                                                DRV_STATUS_DCC_EVENT_MASK));
3847
3848                         if (val & DRV_STATUS_SET_MF_BW)
3849                                 bnx2x_set_mf_bw(sc);
3850
3851                         if (val & DRV_STATUS_DRV_INFO_REQ)
3852                                 bnx2x_handle_drv_info_req(sc);
3853
3854                         if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3855                                 bnx2x_pmf_update(sc);
3856
3857                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3858                                 bnx2x_handle_eee_event(sc);
3859
3860                         if (sc->link_vars.periodic_flags &
3861                             ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3862                                 /* sync with link */
3863                                 sc->link_vars.periodic_flags &=
3864                                     ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3865                                 if (IS_MF(sc)) {
3866                                         bnx2x_link_sync_notify(sc);
3867                                 }
3868                                 bnx2x_link_report(sc);
3869                         }
3870
3871                         /*
3872                          * Always call it here: bnx2x_link_report() will
3873                          * prevent the link indication duplication.
3874                          */
3875                         bnx2x_link_status_update(sc);
3876
3877                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3878
3879                         PMD_DRV_LOG(ERR, "MC assert!");
3880                         bnx2x_mc_assert(sc);
3881                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3882                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3883                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3884                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3885                         rte_panic("MC assert!");
3886
3887                 } else if (attn & BNX2X_MCP_ASSERT) {
3888
3889                         PMD_DRV_LOG(ERR, "MCP assert!");
3890                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3891
3892                 } else {
3893                         PMD_DRV_LOG(ERR,
3894                                     "Unknown HW assert! (attn 0x%08x)", attn);
3895                 }
3896         }
3897
3898         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3899                 PMD_DRV_LOG(ERR, "LATCHED attention 0x%08x (masked)", attn);
3900                 if (attn & BNX2X_GRC_TIMEOUT) {
3901                         val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3902                         PMD_DRV_LOG(ERR, "GRC time-out 0x%08x", val);
3903                 }
3904                 if (attn & BNX2X_GRC_RSV) {
3905                         val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3906                         PMD_DRV_LOG(ERR, "GRC reserved 0x%08x", val);
3907                 }
3908                 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3909         }
3910 }
3911
3912 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3913 {
3914         int port = SC_PORT(sc);
3915         int reg_offset;
3916         uint32_t val0, mask0, val1, mask1;
3917         uint32_t val;
3918
3919         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3920                 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3921                 PMD_DRV_LOG(ERR, "CFC hw attention 0x%08x", val);
3922 /* CFC error attention */
3923                 if (val & 0x2) {
3924                         PMD_DRV_LOG(ERR, "FATAL error from CFC");
3925                 }
3926         }
3927
3928         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3929                 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3930                 PMD_DRV_LOG(ERR, "PXP hw attention-0 0x%08x", val);
3931 /* RQ_USDMDP_FIFO_OVERFLOW */
3932                 if (val & 0x18000) {
3933                         PMD_DRV_LOG(ERR, "FATAL error from PXP");
3934                 }
3935
3936                 if (!CHIP_IS_E1x(sc)) {
3937                         val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3938                         PMD_DRV_LOG(ERR, "PXP hw attention-1 0x%08x", val);
3939                 }
3940         }
3941 #define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3942 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3943
3944         if (attn & AEU_PXP2_HW_INT_BIT) {
3945 /*  CQ47854 workaround do not panic on
3946  *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3947  */
3948                 if (!CHIP_IS_E1x(sc)) {
3949                         mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3950                         val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3951                         mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3952                         val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3953                         /*
3954                          * If the olny PXP2_EOP_ERROR_BIT is set in
3955                          * STS0 and STS1 - clear it
3956                          *
3957                          * probably we lose additional attentions between
3958                          * STS0 and STS_CLR0, in this case user will not
3959                          * be notified about them
3960                          */
3961                         if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3962                             !(val1 & mask1))
3963                                 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3964
3965                         /* print the register, since no one can restore it */
3966                         PMD_DRV_LOG(ERR,
3967                                     "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3968
3969                         /*
3970                          * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3971                          * then notify
3972                          */
3973                         if (val0 & PXP2_EOP_ERROR_BIT) {
3974                                 PMD_DRV_LOG(ERR, "PXP2_WR_PGLUE_EOP_ERROR");
3975
3976                                 /*
3977                                  * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3978                                  * set then clear attention from PXP2 block without panic
3979                                  */
3980                                 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3981                                     ((val1 & mask1) == 0))
3982                                         attn &= ~AEU_PXP2_HW_INT_BIT;
3983                         }
3984                 }
3985         }
3986
3987         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3988                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3989                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3990
3991                 val = REG_RD(sc, reg_offset);
3992                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3993                 REG_WR(sc, reg_offset, val);
3994
3995                 PMD_DRV_LOG(ERR,
3996                             "FATAL HW block attention set2 0x%x",
3997                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
3998                 rte_panic("HW block attention set2");
3999         }
4000 }
4001
4002 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
4003 {
4004         int port = SC_PORT(sc);
4005         int reg_offset;
4006         uint32_t val;
4007
4008         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4009                 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
4010                 PMD_DRV_LOG(ERR, "DB hw attention 0x%08x", val);
4011 /* DORQ discard attention */
4012                 if (val & 0x2) {
4013                         PMD_DRV_LOG(ERR, "FATAL error from DORQ");
4014                 }
4015         }
4016
4017         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4018                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4019                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4020
4021                 val = REG_RD(sc, reg_offset);
4022                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4023                 REG_WR(sc, reg_offset, val);
4024
4025                 PMD_DRV_LOG(ERR,
4026                             "FATAL HW block attention set1 0x%08x",
4027                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4028                 rte_panic("HW block attention set1");
4029         }
4030 }
4031
4032 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4033 {
4034         int port = SC_PORT(sc);
4035         int reg_offset;
4036         uint32_t val;
4037
4038         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4039             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4040
4041         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4042                 val = REG_RD(sc, reg_offset);
4043                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4044                 REG_WR(sc, reg_offset, val);
4045
4046                 PMD_DRV_LOG(WARNING, "SPIO5 hw attention");
4047
4048 /* Fan failure attention */
4049                 elink_hw_reset_phy(&sc->link_params);
4050                 bnx2x_fan_failure(sc);
4051         }
4052
4053         if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4054                 elink_handle_module_detect_int(&sc->link_params);
4055         }
4056
4057         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4058                 val = REG_RD(sc, reg_offset);
4059                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4060                 REG_WR(sc, reg_offset, val);
4061
4062                 rte_panic("FATAL HW block attention set0 0x%lx",
4063                           (attn & HW_INTERRUT_ASSERT_SET_0));
4064         }
4065 }
4066
4067 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4068 {
4069         struct attn_route attn;
4070         struct attn_route *group_mask;
4071         int port = SC_PORT(sc);
4072         int index;
4073         uint32_t reg_addr;
4074         uint32_t val;
4075         uint32_t aeu_mask;
4076         uint8_t global = FALSE;
4077
4078         /*
4079          * Need to take HW lock because MCP or other port might also
4080          * try to handle this event.
4081          */
4082         bnx2x_acquire_alr(sc);
4083
4084         if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4085                 sc->recovery_state = BNX2X_RECOVERY_INIT;
4086
4087 /* disable HW interrupts */
4088                 bnx2x_int_disable(sc);
4089                 bnx2x_release_alr(sc);
4090                 return;
4091         }
4092
4093         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4094         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4095         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4096         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4097         if (!CHIP_IS_E1x(sc)) {
4098                 attn.sig[4] =
4099                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4100         } else {
4101                 attn.sig[4] = 0;
4102         }
4103
4104         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4105                 if (deasserted & (1 << index)) {
4106                         group_mask = &sc->attn_group[index];
4107
4108                         bnx2x_attn_int_deasserted4(sc,
4109                                                  attn.
4110                                                  sig[4] & group_mask->sig[4]);
4111                         bnx2x_attn_int_deasserted3(sc,
4112                                                  attn.
4113                                                  sig[3] & group_mask->sig[3]);
4114                         bnx2x_attn_int_deasserted1(sc,
4115                                                  attn.
4116                                                  sig[1] & group_mask->sig[1]);
4117                         bnx2x_attn_int_deasserted2(sc,
4118                                                  attn.
4119                                                  sig[2] & group_mask->sig[2]);
4120                         bnx2x_attn_int_deasserted0(sc,
4121                                                  attn.
4122                                                  sig[0] & group_mask->sig[0]);
4123                 }
4124         }
4125
4126         bnx2x_release_alr(sc);
4127
4128         if (sc->devinfo.int_block == INT_BLOCK_HC) {
4129                 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4130                             COMMAND_REG_ATTN_BITS_CLR);
4131         } else {
4132                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4133         }
4134
4135         val = ~deasserted;
4136         PMD_DRV_LOG(DEBUG,
4137                     "about to mask 0x%08x at %s addr 0x%08x", val,
4138                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4139                     reg_addr);
4140         REG_WR(sc, reg_addr, val);
4141
4142         if (~sc->attn_state & deasserted) {
4143                 PMD_DRV_LOG(ERR, "IGU error");
4144         }
4145
4146         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4147             MISC_REG_AEU_MASK_ATTN_FUNC_0;
4148
4149         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4150
4151         aeu_mask = REG_RD(sc, reg_addr);
4152
4153         aeu_mask |= (deasserted & 0x3ff);
4154
4155         REG_WR(sc, reg_addr, aeu_mask);
4156         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4157
4158         sc->attn_state &= ~deasserted;
4159 }
4160
4161 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4162 {
4163         /* read local copy of bits */
4164         uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4165         uint32_t attn_ack =
4166             le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4167         uint32_t attn_state = sc->attn_state;
4168
4169         /* look for changed bits */
4170         uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4171         uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4172
4173         PMD_DRV_LOG(DEBUG,
4174                     "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4175                     attn_bits, attn_ack, asserted, deasserted);
4176
4177         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4178                 PMD_DRV_LOG(ERR, "BAD attention state");
4179         }
4180
4181         /* handle bits that were raised */
4182         if (asserted) {
4183                 bnx2x_attn_int_asserted(sc, asserted);
4184         }
4185
4186         if (deasserted) {
4187                 bnx2x_attn_int_deasserted(sc, deasserted);
4188         }
4189 }
4190
4191 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4192 {
4193         struct host_sp_status_block *def_sb = sc->def_sb;
4194         uint16_t rc = 0;
4195
4196         mb();                   /* status block is written to by the chip */
4197
4198         if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4199                 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4200                 rc |= BNX2X_DEF_SB_ATT_IDX;
4201         }
4202
4203         if (sc->def_idx != def_sb->sp_sb.running_index) {
4204                 sc->def_idx = def_sb->sp_sb.running_index;
4205                 rc |= BNX2X_DEF_SB_IDX;
4206         }
4207
4208         mb();
4209
4210         return rc;
4211 }
4212
4213 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4214                                                           uint32_t cid)
4215 {
4216         return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4217 }
4218
4219 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4220 {
4221         struct ecore_mcast_ramrod_params rparam;
4222         int rc;
4223
4224         memset(&rparam, 0, sizeof(rparam));
4225
4226         rparam.mcast_obj = &sc->mcast_obj;
4227
4228         /* clear pending state for the last command */
4229         sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4230
4231         /* if there are pending mcast commands - send them */
4232         if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4233                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4234                 if (rc < 0) {
4235                         PMD_DRV_LOG(INFO,
4236                                     "Failed to send pending mcast commands (%d)",
4237                                     rc);
4238                 }
4239         }
4240 }
4241
4242 static void
4243 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4244 {
4245         unsigned long ramrod_flags = 0;
4246         int rc = 0;
4247         uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4248         struct ecore_vlan_mac_obj *vlan_mac_obj;
4249
4250         /* always push next commands out, don't wait here */
4251         bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4252
4253         switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4254         case ECORE_FILTER_MAC_PENDING:
4255                 PMD_DRV_LOG(DEBUG, "Got SETUP_MAC completions");
4256                 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4257                 break;
4258
4259         case ECORE_FILTER_MCAST_PENDING:
4260                 PMD_DRV_LOG(DEBUG, "Got SETUP_MCAST completions");
4261                 bnx2x_handle_mcast_eqe(sc);
4262                 return;
4263
4264         default:
4265                 PMD_DRV_LOG(NOTICE, "Unsupported classification command: %d",
4266                             elem->message.data.eth_event.echo);
4267                 return;
4268         }
4269
4270         rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4271
4272         if (rc < 0) {
4273                 PMD_DRV_LOG(NOTICE, "Failed to schedule new commands (%d)", rc);
4274         } else if (rc > 0) {
4275                 PMD_DRV_LOG(DEBUG, "Scheduled next pending commands...");
4276         }
4277 }
4278
4279 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4280 {
4281         bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4282
4283         /* send rx_mode command again if was requested */
4284         if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4285                 bnx2x_set_storm_rx_mode(sc);
4286         }
4287 }
4288
4289 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4290 {
4291         storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4292         wmb();                  /* keep prod updates ordered */
4293 }
4294
4295 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4296 {
4297         uint16_t hw_cons, sw_cons, sw_prod;
4298         union event_ring_elem *elem;
4299         uint8_t echo;
4300         uint32_t cid;
4301         uint8_t opcode;
4302         int spqe_cnt = 0;
4303         struct ecore_queue_sp_obj *q_obj;
4304         struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4305         struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4306
4307         hw_cons = le16toh(*sc->eq_cons_sb);
4308
4309         /*
4310          * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4311          * when we get to the next-page we need to adjust so the loop
4312          * condition below will be met. The next element is the size of a
4313          * regular element and hence incrementing by 1
4314          */
4315         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4316                 hw_cons++;
4317         }
4318
4319         /*
4320          * This function may never run in parallel with itself for a
4321          * specific sc and no need for a read memory barrier here.
4322          */
4323         sw_cons = sc->eq_cons;
4324         sw_prod = sc->eq_prod;
4325
4326         for (;
4327              sw_cons != hw_cons;
4328              sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4329
4330                 elem = &sc->eq[EQ_DESC(sw_cons)];
4331
4332 /* elem CID originates from FW, actually LE */
4333                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4334                 opcode = elem->message.opcode;
4335
4336 /* handle eq element */
4337                 switch (opcode) {
4338                 case EVENT_RING_OPCODE_STAT_QUERY:
4339                         PMD_DRV_LOG(DEBUG, "got statistics completion event %d",
4340                                     sc->stats_comp++);
4341                         /* nothing to do with stats comp */
4342                         goto next_spqe;
4343
4344                 case EVENT_RING_OPCODE_CFC_DEL:
4345                         /* handle according to cid range */
4346                         /* we may want to verify here that the sc state is HALTING */
4347                         PMD_DRV_LOG(DEBUG, "got delete ramrod for MULTI[%d]",
4348                                     cid);
4349                         q_obj = bnx2x_cid_to_q_obj(sc, cid);
4350                         if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4351                                 break;
4352                         }
4353                         goto next_spqe;
4354
4355                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4356                         PMD_DRV_LOG(DEBUG, "got STOP TRAFFIC");
4357                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4358                                 break;
4359                         }
4360                         goto next_spqe;
4361
4362                 case EVENT_RING_OPCODE_START_TRAFFIC:
4363                         PMD_DRV_LOG(DEBUG, "got START TRAFFIC");
4364                         if (f_obj->complete_cmd
4365                             (sc, f_obj, ECORE_F_CMD_TX_START)) {
4366                                 break;
4367                         }
4368                         goto next_spqe;
4369
4370                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4371                         echo = elem->message.data.function_update_event.echo;
4372                         if (echo == SWITCH_UPDATE) {
4373                                 PMD_DRV_LOG(DEBUG,
4374                                             "got FUNC_SWITCH_UPDATE ramrod");
4375                                 if (f_obj->complete_cmd(sc, f_obj,
4376                                                         ECORE_F_CMD_SWITCH_UPDATE))
4377                                 {
4378                                         break;
4379                                 }
4380                         } else {
4381                                 PMD_DRV_LOG(DEBUG,
4382                                             "AFEX: ramrod completed FUNCTION_UPDATE");
4383                                 f_obj->complete_cmd(sc, f_obj,
4384                                                     ECORE_F_CMD_AFEX_UPDATE);
4385                         }
4386                         goto next_spqe;
4387
4388                 case EVENT_RING_OPCODE_FORWARD_SETUP:
4389                         q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4390                         if (q_obj->complete_cmd(sc, q_obj,
4391                                                 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4392                                 break;
4393                         }
4394                         goto next_spqe;
4395
4396                 case EVENT_RING_OPCODE_FUNCTION_START:
4397                         PMD_DRV_LOG(DEBUG, "got FUNC_START ramrod");
4398                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4399                                 break;
4400                         }
4401                         goto next_spqe;
4402
4403                 case EVENT_RING_OPCODE_FUNCTION_STOP:
4404                         PMD_DRV_LOG(DEBUG, "got FUNC_STOP ramrod");
4405                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4406                                 break;
4407                         }
4408                         goto next_spqe;
4409                 }
4410
4411                 switch (opcode | sc->state) {
4412                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4413                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4414                         cid =
4415                             elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4416                         PMD_DRV_LOG(DEBUG, "got RSS_UPDATE ramrod. CID %d",
4417                                     cid);
4418                         rss_raw->clear_pending(rss_raw);
4419                         break;
4420
4421                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4422                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4423                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4424                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4425                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4426                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4427                         PMD_DRV_LOG(DEBUG,
4428                                     "got (un)set mac ramrod");
4429                         bnx2x_handle_classification_eqe(sc, elem);
4430                         break;
4431
4432                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4433                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4434                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4435                         PMD_DRV_LOG(DEBUG,
4436                                     "got mcast ramrod");
4437                         bnx2x_handle_mcast_eqe(sc);
4438                         break;
4439
4440                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4441                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4442                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4443                         PMD_DRV_LOG(DEBUG,
4444                                     "got rx_mode ramrod");
4445                         bnx2x_handle_rx_mode_eqe(sc);
4446                         break;
4447
4448                 default:
4449                         /* unknown event log error and continue */
4450                         PMD_DRV_LOG(INFO, "Unknown EQ event %d, sc->state 0x%x",
4451                                     elem->message.opcode, sc->state);
4452                 }
4453
4454 next_spqe:
4455                 spqe_cnt++;
4456         }                       /* for */
4457
4458         mb();
4459         atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4460
4461         sc->eq_cons = sw_cons;
4462         sc->eq_prod = sw_prod;
4463
4464         /* make sure that above mem writes were issued towards the memory */
4465         wmb();
4466
4467         /* update producer */
4468         bnx2x_update_eq_prod(sc, sc->eq_prod);
4469 }
4470
4471 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4472 {
4473         uint16_t status;
4474         int rc = 0;
4475
4476         /* what work needs to be performed? */
4477         status = bnx2x_update_dsb_idx(sc);
4478
4479         /* HW attentions */
4480         if (status & BNX2X_DEF_SB_ATT_IDX) {
4481                 PMD_DRV_LOG(DEBUG, "---> ATTN INTR <---");
4482                 bnx2x_attn_int(sc);
4483                 status &= ~BNX2X_DEF_SB_ATT_IDX;
4484                 rc = 1;
4485         }
4486
4487         /* SP events: STAT_QUERY and others */
4488         if (status & BNX2X_DEF_SB_IDX) {
4489 /* handle EQ completions */
4490                 PMD_DRV_LOG(DEBUG, "---> EQ INTR <---");
4491                 bnx2x_eq_int(sc);
4492                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4493                            le16toh(sc->def_idx), IGU_INT_NOP, 1);
4494                 status &= ~BNX2X_DEF_SB_IDX;
4495         }
4496
4497         /* if status is non zero then something went wrong */
4498         if (unlikely(status)) {
4499                 PMD_DRV_LOG(INFO,
4500                             "Got an unknown SP interrupt! (0x%04x)", status);
4501         }
4502
4503         /* ack status block only if something was actually handled */
4504         bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4505                    le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4506
4507         return rc;
4508 }
4509
4510 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4511 {
4512         struct bnx2x_softc *sc = fp->sc;
4513         uint8_t more_rx = FALSE;
4514
4515         /* update the fastpath index */
4516         bnx2x_update_fp_sb_idx(fp);
4517
4518         if (scan_fp) {
4519                 if (bnx2x_has_rx_work(fp)) {
4520                         more_rx = bnx2x_rxeof(sc, fp);
4521                 }
4522
4523                 if (more_rx) {
4524                         /* still more work to do */
4525                         bnx2x_handle_fp_tq(fp, scan_fp);
4526                         return;
4527                 }
4528         }
4529
4530         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4531                    le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4532 }
4533
4534 /*
4535  * Legacy interrupt entry point.
4536  *
4537  * Verifies that the controller generated the interrupt and
4538  * then calls a separate routine to handle the various
4539  * interrupt causes: link, RX, and TX.
4540  */
4541 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4542 {
4543         struct bnx2x_fastpath *fp;
4544         uint32_t status, mask;
4545         int i, rc = 0;
4546
4547         /*
4548          * 0 for ustorm, 1 for cstorm
4549          * the bits returned from ack_int() are 0-15
4550          * bit 0 = attention status block
4551          * bit 1 = fast path status block
4552          * a mask of 0x2 or more = tx/rx event
4553          * a mask of 1 = slow path event
4554          */
4555
4556         status = bnx2x_ack_int(sc);
4557
4558         /* the interrupt is not for us */
4559         if (unlikely(status == 0)) {
4560                 return 0;
4561         }
4562
4563         PMD_DRV_LOG(DEBUG, "Interrupt status 0x%04x", status);
4564         //bnx2x_dump_status_block(sc);
4565
4566         FOR_EACH_ETH_QUEUE(sc, i) {
4567                 fp = &sc->fp[i];
4568                 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4569                 if (status & mask) {
4570                         bnx2x_handle_fp_tq(fp, scan_fp);
4571                         status &= ~mask;
4572                 }
4573         }
4574
4575         if (unlikely(status & 0x1)) {
4576                 rc = bnx2x_handle_sp_tq(sc);
4577                 status &= ~0x1;
4578         }
4579
4580         if (unlikely(status)) {
4581                 PMD_DRV_LOG(WARNING,
4582                             "Unexpected fastpath status (0x%08x)!", status);
4583         }
4584
4585         return rc;
4586 }
4587
4588 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4589 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4590 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4591 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4592 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4593 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4594 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4595 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4596 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4597
4598 static struct
4599 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4600         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4601         .init_hw_cmn = bnx2x_init_hw_common,
4602         .init_hw_port = bnx2x_init_hw_port,
4603         .init_hw_func = bnx2x_init_hw_func,
4604
4605         .reset_hw_cmn = bnx2x_reset_common,
4606         .reset_hw_port = bnx2x_reset_port,
4607         .reset_hw_func = bnx2x_reset_func,
4608
4609         .init_fw = bnx2x_init_firmware,
4610         .release_fw = bnx2x_release_firmware,
4611 };
4612
4613 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4614 {
4615         sc->dmae_ready = 0;
4616
4617         PMD_INIT_FUNC_TRACE();
4618
4619         ecore_init_func_obj(sc,
4620                             &sc->func_obj,
4621                             BNX2X_SP(sc, func_rdata),
4622                             (phys_addr_t)BNX2X_SP_MAPPING(sc, func_rdata),
4623                             BNX2X_SP(sc, func_afex_rdata),
4624                             (phys_addr_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4625                             &bnx2x_func_sp_drv);
4626 }
4627
4628 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4629 {
4630         struct ecore_func_state_params func_params = { NULL };
4631         int rc;
4632
4633         PMD_INIT_FUNC_TRACE();
4634
4635         /* prepare the parameters for function state transitions */
4636         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4637
4638         func_params.f_obj = &sc->func_obj;
4639         func_params.cmd = ECORE_F_CMD_HW_INIT;
4640
4641         func_params.params.hw_init.load_phase = load_code;
4642
4643         /*
4644          * Via a plethora of function pointers, we will eventually reach
4645          * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4646          */
4647         rc = ecore_func_state_change(sc, &func_params);
4648
4649         return rc;
4650 }
4651
4652 static void
4653 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4654 {
4655         uint32_t i;
4656
4657         if (!(len % 4) && !(addr % 4)) {
4658                 for (i = 0; i < len; i += 4) {
4659                         REG_WR(sc, (addr + i), fill);
4660                 }
4661         } else {
4662                 for (i = 0; i < len; i++) {
4663                         REG_WR8(sc, (addr + i), fill);
4664                 }
4665         }
4666 }
4667
4668 /* writes FP SP data to FW - data_size in dwords */
4669 static void
4670 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4671                   uint32_t data_size)
4672 {
4673         uint32_t index;
4674
4675         for (index = 0; index < data_size; index++) {
4676                 REG_WR(sc,
4677                        (BAR_CSTRORM_INTMEM +
4678                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4679                         (sizeof(uint32_t) * index)), *(sb_data_p + index));
4680         }
4681 }
4682
4683 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4684 {
4685         struct hc_status_block_data_e2 sb_data_e2;
4686         struct hc_status_block_data_e1x sb_data_e1x;
4687         uint32_t *sb_data_p;
4688         uint32_t data_size = 0;
4689
4690         if (!CHIP_IS_E1x(sc)) {
4691                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4692                 sb_data_e2.common.state = SB_DISABLED;
4693                 sb_data_e2.common.p_func.vf_valid = FALSE;
4694                 sb_data_p = (uint32_t *) & sb_data_e2;
4695                 data_size = (sizeof(struct hc_status_block_data_e2) /
4696                              sizeof(uint32_t));
4697         } else {
4698                 memset(&sb_data_e1x, 0,
4699                        sizeof(struct hc_status_block_data_e1x));
4700                 sb_data_e1x.common.state = SB_DISABLED;
4701                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4702                 sb_data_p = (uint32_t *) & sb_data_e1x;
4703                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4704                              sizeof(uint32_t));
4705         }
4706
4707         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4708
4709         bnx2x_fill(sc,
4710                  (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4711                  CSTORM_STATUS_BLOCK_SIZE);
4712         bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4713                  0, CSTORM_SYNC_BLOCK_SIZE);
4714 }
4715
4716 static void
4717 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4718                   struct hc_sp_status_block_data *sp_sb_data)
4719 {
4720         uint32_t i;
4721
4722         for (i = 0;
4723              i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4724              i++) {
4725                 REG_WR(sc,
4726                        (BAR_CSTRORM_INTMEM +
4727                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4728                         (i * sizeof(uint32_t))),
4729                        *((uint32_t *) sp_sb_data + i));
4730         }
4731 }
4732
4733 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4734 {
4735         struct hc_sp_status_block_data sp_sb_data;
4736
4737         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4738
4739         sp_sb_data.state = SB_DISABLED;
4740         sp_sb_data.p_func.vf_valid = FALSE;
4741
4742         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4743
4744         bnx2x_fill(sc,
4745                  (BAR_CSTRORM_INTMEM +
4746                   CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4747                  0, CSTORM_SP_STATUS_BLOCK_SIZE);
4748         bnx2x_fill(sc,
4749                  (BAR_CSTRORM_INTMEM +
4750                   CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4751                  0, CSTORM_SP_SYNC_BLOCK_SIZE);
4752 }
4753
4754 static void
4755 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4756                              int igu_seg_id)
4757 {
4758         hc_sm->igu_sb_id = igu_sb_id;
4759         hc_sm->igu_seg_id = igu_seg_id;
4760         hc_sm->timer_value = 0xFF;
4761         hc_sm->time_to_expire = 0xFFFFFFFF;
4762 }
4763
4764 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4765 {
4766         /* zero out state machine indices */
4767
4768         /* rx indices */
4769         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4770
4771         /* tx indices */
4772         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4773         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4774         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4775         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4776
4777         /* map indices */
4778
4779         /* rx indices */
4780         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4781             (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4782
4783         /* tx indices */
4784         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4785             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4786         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4787             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4788         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4789             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4790         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4791             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4792 }
4793
4794 static void
4795 bnx2x_init_sb(struct bnx2x_softc *sc, phys_addr_t busaddr, int vfid,
4796             uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4797 {
4798         struct hc_status_block_data_e2 sb_data_e2;
4799         struct hc_status_block_data_e1x sb_data_e1x;
4800         struct hc_status_block_sm *hc_sm_p;
4801         uint32_t *sb_data_p;
4802         int igu_seg_id;
4803         int data_size;
4804
4805         if (CHIP_INT_MODE_IS_BC(sc)) {
4806                 igu_seg_id = HC_SEG_ACCESS_NORM;
4807         } else {
4808                 igu_seg_id = IGU_SEG_ACCESS_NORM;
4809         }
4810
4811         bnx2x_zero_fp_sb(sc, fw_sb_id);
4812
4813         if (!CHIP_IS_E1x(sc)) {
4814                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4815                 sb_data_e2.common.state = SB_ENABLED;
4816                 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4817                 sb_data_e2.common.p_func.vf_id = vfid;
4818                 sb_data_e2.common.p_func.vf_valid = vf_valid;
4819                 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4820                 sb_data_e2.common.same_igu_sb_1b = TRUE;
4821                 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4822                 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4823                 hc_sm_p = sb_data_e2.common.state_machine;
4824                 sb_data_p = (uint32_t *) & sb_data_e2;
4825                 data_size = (sizeof(struct hc_status_block_data_e2) /
4826                              sizeof(uint32_t));
4827                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4828         } else {
4829                 memset(&sb_data_e1x, 0,
4830                        sizeof(struct hc_status_block_data_e1x));
4831                 sb_data_e1x.common.state = SB_ENABLED;
4832                 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4833                 sb_data_e1x.common.p_func.vf_id = 0xff;
4834                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4835                 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4836                 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4837                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4838                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4839                 hc_sm_p = sb_data_e1x.common.state_machine;
4840                 sb_data_p = (uint32_t *) & sb_data_e1x;
4841                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4842                              sizeof(uint32_t));
4843                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4844         }
4845
4846         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4847         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4848
4849         /* write indices to HW - PCI guarantees endianity of regpairs */
4850         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4851 }
4852
4853 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4854 {
4855         if (CHIP_IS_E1x(fp->sc)) {
4856                 return (fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H);
4857         } else {
4858                 return (fp->cl_id);
4859         }
4860 }
4861
4862 static uint32_t
4863 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4864 {
4865         uint32_t offset = BAR_USTRORM_INTMEM;
4866
4867         if (IS_VF(sc)) {
4868                 return (PXP_VF_ADDR_USDM_QUEUES_START +
4869                         (sc->acquire_resp.resc.hw_qid[fp->index] *
4870                          sizeof(struct ustorm_queue_zone_data)));
4871         } else if (!CHIP_IS_E1x(sc)) {
4872                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4873         } else {
4874                 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4875         }
4876
4877         return offset;
4878 }
4879
4880 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4881 {
4882         struct bnx2x_fastpath *fp = &sc->fp[idx];
4883         uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4884         unsigned long q_type = 0;
4885         int cos;
4886
4887         fp->sc = sc;
4888         fp->index = idx;
4889
4890         fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4891         fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4892
4893         if (CHIP_IS_E1x(sc))
4894                 fp->cl_id = SC_L_ID(sc) + idx;
4895         else
4896 /* want client ID same as IGU SB ID for non-E1 */
4897                 fp->cl_id = fp->igu_sb_id;
4898         fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4899
4900         /* setup sb indices */
4901         if (!CHIP_IS_E1x(sc)) {
4902                 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4903                 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4904         } else {
4905                 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4906                 fp->sb_running_index =
4907                     fp->status_block.e1x_sb->sb.running_index;
4908         }
4909
4910         /* init shortcut */
4911         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4912
4913         fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4914
4915         for (cos = 0; cos < sc->max_cos; cos++) {
4916                 cids[cos] = idx;
4917         }
4918         fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4919
4920         /* nothing more for a VF to do */
4921         if (IS_VF(sc)) {
4922                 return;
4923         }
4924
4925         bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4926                     fp->fw_sb_id, fp->igu_sb_id);
4927
4928         bnx2x_update_fp_sb_idx(fp);
4929
4930         /* Configure Queue State object */
4931         bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4932         bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4933
4934         ecore_init_queue_obj(sc,
4935                              &sc->sp_objs[idx].q_obj,
4936                              fp->cl_id,
4937                              cids,
4938                              sc->max_cos,
4939                              SC_FUNC(sc),
4940                              BNX2X_SP(sc, q_rdata),
4941                              (phys_addr_t)BNX2X_SP_MAPPING(sc, q_rdata),
4942                              q_type);
4943
4944         /* configure classification DBs */
4945         ecore_init_mac_obj(sc,
4946                            &sc->sp_objs[idx].mac_obj,
4947                            fp->cl_id,
4948                            idx,
4949                            SC_FUNC(sc),
4950                            BNX2X_SP(sc, mac_rdata),
4951                            (phys_addr_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4952                            ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4953                            ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4954 }
4955
4956 static void
4957 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4958                    uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4959 {
4960         union ustorm_eth_rx_producers rx_prods;
4961         uint32_t i;
4962
4963         /* update producers */
4964         rx_prods.prod.bd_prod = rx_bd_prod;
4965         rx_prods.prod.cqe_prod = rx_cq_prod;
4966         rx_prods.prod.reserved = 0;
4967
4968         /*
4969          * Make sure that the BD and SGE data is updated before updating the
4970          * producers since FW might read the BD/SGE right after the producer
4971          * is updated.
4972          * This is only applicable for weak-ordered memory model archs such
4973          * as IA-64. The following barrier is also mandatory since FW will
4974          * assumes BDs must have buffers.
4975          */
4976         wmb();
4977
4978         for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
4979                 REG_WR(sc,
4980                        (fp->ustorm_rx_prods_offset + (i * 4)),
4981                        rx_prods.raw_data[i]);
4982         }
4983
4984         wmb();                  /* keep prod updates ordered */
4985 }
4986
4987 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
4988 {
4989         struct bnx2x_fastpath *fp;
4990         int i;
4991         struct bnx2x_rx_queue *rxq;
4992
4993         for (i = 0; i < sc->num_queues; i++) {
4994                 fp = &sc->fp[i];
4995                 rxq = sc->rx_queues[fp->index];
4996                 if (!rxq) {
4997                         PMD_RX_LOG(ERR, "RX queue is NULL");
4998                         return;
4999                 }
5000
5001 /*
5002  * Activate the BD ring...
5003  * Warning, this will generate an interrupt (to the TSTORM)
5004  * so this can only be done after the chip is initialized
5005  */
5006                 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5007
5008                 if (i != 0) {
5009                         continue;
5010                 }
5011         }
5012 }
5013
5014 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5015 {
5016         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5017
5018         fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5019         fp->tx_db.data.zero_fill1 = 0;
5020         fp->tx_db.data.prod = 0;
5021
5022         if (!txq) {
5023                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5024                 return;
5025         }
5026
5027         txq->tx_pkt_tail = 0;
5028         txq->tx_pkt_head = 0;
5029         txq->tx_bd_tail = 0;
5030         txq->tx_bd_head = 0;
5031 }
5032
5033 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5034 {
5035         int i;
5036
5037         for (i = 0; i < sc->num_queues; i++) {
5038                 bnx2x_init_tx_ring_one(&sc->fp[i]);
5039         }
5040 }
5041
5042 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5043 {
5044         struct host_sp_status_block *def_sb = sc->def_sb;
5045         phys_addr_t mapping = sc->def_sb_dma.paddr;
5046         int igu_sp_sb_index;
5047         int igu_seg_id;
5048         int port = SC_PORT(sc);
5049         int func = SC_FUNC(sc);
5050         int reg_offset, reg_offset_en5;
5051         uint64_t section;
5052         int index, sindex;
5053         struct hc_sp_status_block_data sp_sb_data;
5054
5055         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5056
5057         if (CHIP_INT_MODE_IS_BC(sc)) {
5058                 igu_sp_sb_index = DEF_SB_IGU_ID;
5059                 igu_seg_id = HC_SEG_ACCESS_DEF;
5060         } else {
5061                 igu_sp_sb_index = sc->igu_dsb_id;
5062                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5063         }
5064
5065         /* attentions */
5066         section = ((uint64_t) mapping +
5067                    offsetof(struct host_sp_status_block, atten_status_block));
5068         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5069         sc->attn_state = 0;
5070
5071         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5072             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5073
5074         reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5075             MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5076
5077         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5078 /* take care of sig[0]..sig[4] */
5079                 for (sindex = 0; sindex < 4; sindex++) {
5080                         sc->attn_group[index].sig[sindex] =
5081                             REG_RD(sc,
5082                                    (reg_offset + (sindex * 0x4) +
5083                                     (0x10 * index)));
5084                 }
5085
5086                 if (!CHIP_IS_E1x(sc)) {
5087                         /*
5088                          * enable5 is separate from the rest of the registers,
5089                          * and the address skip is 4 and not 16 between the
5090                          * different groups
5091                          */
5092                         sc->attn_group[index].sig[4] =
5093                             REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5094                 } else {
5095                         sc->attn_group[index].sig[4] = 0;
5096                 }
5097         }
5098
5099         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5100                 reg_offset =
5101                     port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5102                 REG_WR(sc, reg_offset, U64_LO(section));
5103                 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5104         } else if (!CHIP_IS_E1x(sc)) {
5105                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5106                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5107         }
5108
5109         section = ((uint64_t) mapping +
5110                    offsetof(struct host_sp_status_block, sp_sb));
5111
5112         bnx2x_zero_sp_sb(sc);
5113
5114         /* PCI guarantees endianity of regpair */
5115         sp_sb_data.state = SB_ENABLED;
5116         sp_sb_data.host_sb_addr.lo = U64_LO(section);
5117         sp_sb_data.host_sb_addr.hi = U64_HI(section);
5118         sp_sb_data.igu_sb_id = igu_sp_sb_index;
5119         sp_sb_data.igu_seg_id = igu_seg_id;
5120         sp_sb_data.p_func.pf_id = func;
5121         sp_sb_data.p_func.vnic_id = SC_VN(sc);
5122         sp_sb_data.p_func.vf_id = 0xff;
5123
5124         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5125
5126         bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5127 }
5128
5129 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5130 {
5131         atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5132         sc->spq_prod_idx = 0;
5133         sc->dsb_sp_prod =
5134             &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5135         sc->spq_prod_bd = sc->spq;
5136         sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5137 }
5138
5139 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5140 {
5141         union event_ring_elem *elem;
5142         int i;
5143
5144         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5145                 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5146
5147                 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5148                                                          BNX2X_PAGE_SIZE *
5149                                                          (i % NUM_EQ_PAGES)));
5150                 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5151                                                          BNX2X_PAGE_SIZE *
5152                                                          (i % NUM_EQ_PAGES)));
5153         }
5154
5155         sc->eq_cons = 0;
5156         sc->eq_prod = NUM_EQ_DESC;
5157         sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5158
5159         atomic_store_rel_long(&sc->eq_spq_left,
5160                               (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5161                                    NUM_EQ_DESC) - 1));
5162 }
5163
5164 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5165 {
5166         int i;
5167
5168         if (IS_MF_SI(sc)) {
5169 /*
5170  * In switch independent mode, the TSTORM needs to accept
5171  * packets that failed classification, since approximate match
5172  * mac addresses aren't written to NIG LLH.
5173  */
5174                 REG_WR8(sc,
5175                         (BAR_TSTRORM_INTMEM +
5176                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5177         } else
5178                 REG_WR8(sc,
5179                         (BAR_TSTRORM_INTMEM +
5180                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5181
5182         /*
5183          * Zero this manually as its initialization is currently missing
5184          * in the initTool.
5185          */
5186         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5187                 REG_WR(sc,
5188                        (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5189                        0);
5190         }
5191
5192         if (!CHIP_IS_E1x(sc)) {
5193                 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5194                         CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5195                         HC_IGU_NBC_MODE);
5196         }
5197 }
5198
5199 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5200 {
5201         switch (load_code) {
5202         case FW_MSG_CODE_DRV_LOAD_COMMON:
5203         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5204                 bnx2x_init_internal_common(sc);
5205                 /* no break */
5206
5207         case FW_MSG_CODE_DRV_LOAD_PORT:
5208                 /* nothing to do */
5209                 /* no break */
5210
5211         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5212                 /* internal memory per function is initialized inside bnx2x_pf_init */
5213                 break;
5214
5215         default:
5216                 PMD_DRV_LOG(NOTICE, "Unknown load_code (0x%x) from MCP",
5217                             load_code);
5218                 break;
5219         }
5220 }
5221
5222 static void
5223 storm_memset_func_cfg(struct bnx2x_softc *sc,
5224                       struct tstorm_eth_function_common_config *tcfg,
5225                       uint16_t abs_fid)
5226 {
5227         uint32_t addr;
5228         size_t size;
5229
5230         addr = (BAR_TSTRORM_INTMEM +
5231                 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5232         size = sizeof(struct tstorm_eth_function_common_config);
5233         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5234 }
5235
5236 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5237 {
5238         struct tstorm_eth_function_common_config tcfg = { 0 };
5239
5240         if (CHIP_IS_E1x(sc)) {
5241                 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5242         }
5243
5244         /* Enable the function in the FW */
5245         storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5246         storm_memset_func_en(sc, p->func_id, 1);
5247
5248         /* spq */
5249         if (p->func_flgs & FUNC_FLG_SPQ) {
5250                 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5251                 REG_WR(sc,
5252                        (XSEM_REG_FAST_MEMORY +
5253                         XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5254         }
5255 }
5256
5257 /*
5258  * Calculates the sum of vn_min_rates.
5259  * It's needed for further normalizing of the min_rates.
5260  * Returns:
5261  *   sum of vn_min_rates.
5262  *     or
5263  *   0 - if all the min_rates are 0.
5264  * In the later case fainess algorithm should be deactivated.
5265  * If all min rates are not zero then those that are zeroes will be set to 1.
5266  */
5267 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5268 {
5269         uint32_t vn_cfg;
5270         uint32_t vn_min_rate;
5271         int all_zero = 1;
5272         int vn;
5273
5274         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5275                 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5276                 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5277                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5278
5279                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5280                         /* skip hidden VNs */
5281                         vn_min_rate = 0;
5282                 } else if (!vn_min_rate) {
5283                         /* If min rate is zero - set it to 100 */
5284                         vn_min_rate = DEF_MIN_RATE;
5285                 } else {
5286                         all_zero = 0;
5287                 }
5288
5289                 input->vnic_min_rate[vn] = vn_min_rate;
5290         }
5291
5292         /* if ETS or all min rates are zeros - disable fairness */
5293         if (all_zero) {
5294                 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5295         } else {
5296                 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5297         }
5298 }
5299
5300 static uint16_t
5301 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5302 {
5303         uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5304                             FUNC_MF_CFG_MAX_BW_SHIFT);
5305
5306         if (!max_cfg) {
5307                 PMD_DRV_LOG(DEBUG,
5308                             "Max BW configured to 0 - using 100 instead");
5309                 max_cfg = 100;
5310         }
5311
5312         return max_cfg;
5313 }
5314
5315 static void
5316 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5317 {
5318         uint16_t vn_max_rate;
5319         uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5320         uint32_t max_cfg;
5321
5322         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5323                 vn_max_rate = 0;
5324         } else {
5325                 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5326
5327                 if (IS_MF_SI(sc)) {
5328                         /* max_cfg in percents of linkspeed */
5329                         vn_max_rate =
5330                             ((sc->link_vars.line_speed * max_cfg) / 100);
5331                 } else {        /* SD modes */
5332                         /* max_cfg is absolute in 100Mb units */
5333                         vn_max_rate = (max_cfg * 100);
5334                 }
5335         }
5336
5337         input->vnic_max_rate[vn] = vn_max_rate;
5338 }
5339
5340 static void
5341 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5342 {
5343         struct cmng_init_input input;
5344         int vn;
5345
5346         memset(&input, 0, sizeof(struct cmng_init_input));
5347
5348         input.port_rate = sc->link_vars.line_speed;
5349
5350         if (cmng_type == CMNG_FNS_MINMAX) {
5351 /* read mf conf from shmem */
5352                 if (read_cfg) {
5353                         bnx2x_read_mf_cfg(sc);
5354                 }
5355
5356 /* get VN min rate and enable fairness if not 0 */
5357                 bnx2x_calc_vn_min(sc, &input);
5358
5359 /* get VN max rate */
5360                 if (sc->port.pmf) {
5361                         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5362                                 bnx2x_calc_vn_max(sc, vn, &input);
5363                         }
5364                 }
5365
5366 /* always enable rate shaping and fairness */
5367                 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5368
5369                 ecore_init_cmng(&input, &sc->cmng);
5370                 return;
5371         }
5372 }
5373
5374 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5375 {
5376         if (CHIP_REV_IS_SLOW(sc)) {
5377                 return CMNG_FNS_NONE;
5378         }
5379
5380         if (IS_MF(sc)) {
5381                 return CMNG_FNS_MINMAX;
5382         }
5383
5384         return CMNG_FNS_NONE;
5385 }
5386
5387 static void
5388 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5389 {
5390         int vn;
5391         int func;
5392         uint32_t addr;
5393         size_t size;
5394
5395         addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5396         size = sizeof(struct cmng_struct_per_port);
5397         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5398
5399         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5400                 func = func_by_vn(sc, vn);
5401
5402                 addr = (BAR_XSTRORM_INTMEM +
5403                         XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5404                 size = sizeof(struct rate_shaping_vars_per_vn);
5405                 ecore_storm_memset_struct(sc, addr, size,
5406                                           (uint32_t *) & cmng->
5407                                           vnic.vnic_max_rate[vn]);
5408
5409                 addr = (BAR_XSTRORM_INTMEM +
5410                         XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5411                 size = sizeof(struct fairness_vars_per_vn);
5412                 ecore_storm_memset_struct(sc, addr, size,
5413                                           (uint32_t *) & cmng->
5414                                           vnic.vnic_min_rate[vn]);
5415         }
5416 }
5417
5418 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5419 {
5420         struct bnx2x_func_init_params func_init;
5421         struct event_ring_data eq_data;
5422         uint16_t flags;
5423
5424         memset(&eq_data, 0, sizeof(struct event_ring_data));
5425         memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5426
5427         if (!CHIP_IS_E1x(sc)) {
5428 /* reset IGU PF statistics: MSIX + ATTN */
5429 /* PF */
5430                 REG_WR(sc,
5431                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5432                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5433                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5434                          4)), 0);
5435 /* ATTN */
5436                 REG_WR(sc,
5437                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5438                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5439                         (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5440                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5441                          4)), 0);
5442         }
5443
5444         /* function setup flags */
5445         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5446
5447         func_init.func_flgs = flags;
5448         func_init.pf_id = SC_FUNC(sc);
5449         func_init.func_id = SC_FUNC(sc);
5450         func_init.spq_map = sc->spq_dma.paddr;
5451         func_init.spq_prod = sc->spq_prod_idx;
5452
5453         bnx2x_func_init(sc, &func_init);
5454
5455         memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5456
5457         /*
5458          * Congestion management values depend on the link rate.
5459          * There is no active link so initial link rate is set to 10Gbps.
5460          * When the link comes up the congestion management values are
5461          * re-calculated according to the actual link rate.
5462          */
5463         sc->link_vars.line_speed = SPEED_10000;
5464         bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5465
5466         /* Only the PMF sets the HW */
5467         if (sc->port.pmf) {
5468                 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5469         }
5470
5471         /* init Event Queue - PCI bus guarantees correct endainity */
5472         eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5473         eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5474         eq_data.producer = sc->eq_prod;
5475         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5476         eq_data.sb_id = DEF_SB_ID;
5477         storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5478 }
5479
5480 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5481 {
5482         int port = SC_PORT(sc);
5483         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5484         uint32_t val = REG_RD(sc, addr);
5485         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5486             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5487         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5488         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5489
5490         if (msix) {
5491                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5492                          HC_CONFIG_0_REG_INT_LINE_EN_0);
5493                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5494                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5495                 if (single_msix) {
5496                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5497                 }
5498         } else if (msi) {
5499                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5500                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5501                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5502                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5503         } else {
5504                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5505                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5506                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
5507                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5508
5509                 REG_WR(sc, addr, val);
5510
5511                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5512         }
5513
5514         REG_WR(sc, addr, val);
5515
5516         /* ensure that HC_CONFIG is written before leading/trailing edge config */
5517         mb();
5518
5519         /* init leading/trailing edge */
5520         if (IS_MF(sc)) {
5521                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5522                 if (sc->port.pmf) {
5523                         /* enable nig and gpio3 attention */
5524                         val |= 0x1100;
5525                 }
5526         } else {
5527                 val = 0xffff;
5528         }
5529
5530         REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5531         REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5532
5533         /* make sure that interrupts are indeed enabled from here on */
5534         mb();
5535 }
5536
5537 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5538 {
5539         uint32_t val;
5540         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5541             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5542         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5543         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5544
5545         val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5546
5547         if (msix) {
5548                 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5549                 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5550                 if (single_msix) {
5551                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
5552                 }
5553         } else if (msi) {
5554                 val &= ~IGU_PF_CONF_INT_LINE_EN;
5555                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5556                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5557         } else {
5558                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5559                 val |= (IGU_PF_CONF_INT_LINE_EN |
5560                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5561         }
5562
5563         /* clean previous status - need to configure igu prior to ack */
5564         if ((!msix) || single_msix) {
5565                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5566                 bnx2x_ack_int(sc);
5567         }
5568
5569         val |= IGU_PF_CONF_FUNC_EN;
5570
5571         PMD_DRV_LOG(DEBUG, "write 0x%x to IGU mode %s",
5572                     val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5573
5574         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5575
5576         mb();
5577
5578         /* init leading/trailing edge */
5579         if (IS_MF(sc)) {
5580                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5581                 if (sc->port.pmf) {
5582                         /* enable nig and gpio3 attention */
5583                         val |= 0x1100;
5584                 }
5585         } else {
5586                 val = 0xffff;
5587         }
5588
5589         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5590         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5591
5592         /* make sure that interrupts are indeed enabled from here on */
5593         mb();
5594 }
5595
5596 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5597 {
5598         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5599                 bnx2x_hc_int_enable(sc);
5600         } else {
5601                 bnx2x_igu_int_enable(sc);
5602         }
5603 }
5604
5605 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5606 {
5607         int port = SC_PORT(sc);
5608         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5609         uint32_t val = REG_RD(sc, addr);
5610
5611         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5612                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5613                  HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5614         /* flush all outstanding writes */
5615         mb();
5616
5617         REG_WR(sc, addr, val);
5618         if (REG_RD(sc, addr) != val) {
5619                 PMD_DRV_LOG(ERR, "proper val not read from HC IGU!");
5620         }
5621 }
5622
5623 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5624 {
5625         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5626
5627         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5628                  IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5629
5630         PMD_DRV_LOG(DEBUG, "write %x to IGU", val);
5631
5632         /* flush all outstanding writes */
5633         mb();
5634
5635         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5636         if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5637                 PMD_DRV_LOG(ERR, "proper val not read from IGU!");
5638         }
5639 }
5640
5641 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5642 {
5643         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5644                 bnx2x_hc_int_disable(sc);
5645         } else {
5646                 bnx2x_igu_int_disable(sc);
5647         }
5648 }
5649
5650 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5651 {
5652         int i;
5653
5654         PMD_INIT_FUNC_TRACE();
5655
5656         for (i = 0; i < sc->num_queues; i++) {
5657                 bnx2x_init_eth_fp(sc, i);
5658         }
5659
5660         rmb();                  /* ensure status block indices were read */
5661
5662         bnx2x_init_rx_rings(sc);
5663         bnx2x_init_tx_rings(sc);
5664
5665         if (IS_VF(sc)) {
5666                 bnx2x_memset_stats(sc);
5667                 return;
5668         }
5669
5670         /* initialize MOD_ABS interrupts */
5671         elink_init_mod_abs_int(sc, &sc->link_vars,
5672                                sc->devinfo.chip_id,
5673                                sc->devinfo.shmem_base,
5674                                sc->devinfo.shmem2_base, SC_PORT(sc));
5675
5676         bnx2x_init_def_sb(sc);
5677         bnx2x_update_dsb_idx(sc);
5678         bnx2x_init_sp_ring(sc);
5679         bnx2x_init_eq_ring(sc);
5680         bnx2x_init_internal(sc, load_code);
5681         bnx2x_pf_init(sc);
5682         bnx2x_stats_init(sc);
5683
5684         /* flush all before enabling interrupts */
5685         mb();
5686
5687         bnx2x_int_enable(sc);
5688
5689         /* check for SPIO5 */
5690         bnx2x_attn_int_deasserted0(sc,
5691                                  REG_RD(sc,
5692                                         (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5693                                          SC_PORT(sc) * 4)) &
5694                                  AEU_INPUTS_ATTN_BITS_SPIO5);
5695 }
5696
5697 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5698 {
5699         /* mcast rules must be added to tx if tx switching is enabled */
5700         ecore_obj_type o_type;
5701         if (sc->flags & BNX2X_TX_SWITCHING)
5702                 o_type = ECORE_OBJ_TYPE_RX_TX;
5703         else
5704                 o_type = ECORE_OBJ_TYPE_RX;
5705
5706         /* RX_MODE controlling object */
5707         ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5708
5709         /* multicast configuration controlling object */
5710         ecore_init_mcast_obj(sc,
5711                              &sc->mcast_obj,
5712                              sc->fp[0].cl_id,
5713                              sc->fp[0].index,
5714                              SC_FUNC(sc),
5715                              SC_FUNC(sc),
5716                              BNX2X_SP(sc, mcast_rdata),
5717                              (phys_addr_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5718                              ECORE_FILTER_MCAST_PENDING,
5719                              &sc->sp_state, o_type);
5720
5721         /* Setup CAM credit pools */
5722         ecore_init_mac_credit_pool(sc,
5723                                    &sc->macs_pool,
5724                                    SC_FUNC(sc),
5725                                    CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5726                                    VNICS_PER_PATH(sc));
5727
5728         ecore_init_vlan_credit_pool(sc,
5729                                     &sc->vlans_pool,
5730                                     SC_ABS_FUNC(sc) >> 1,
5731                                     CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5732                                     VNICS_PER_PATH(sc));
5733
5734         /* RSS configuration object */
5735         ecore_init_rss_config_obj(&sc->rss_conf_obj,
5736                                   sc->fp[0].cl_id,
5737                                   sc->fp[0].index,
5738                                   SC_FUNC(sc),
5739                                   SC_FUNC(sc),
5740                                   BNX2X_SP(sc, rss_rdata),
5741                                   (phys_addr_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5742                                   ECORE_FILTER_RSS_CONF_PENDING,
5743                                   &sc->sp_state, ECORE_OBJ_TYPE_RX);
5744 }
5745
5746 /*
5747  * Initialize the function. This must be called before sending CLIENT_SETUP
5748  * for the first client.
5749  */
5750 static int bnx2x_func_start(struct bnx2x_softc *sc)
5751 {
5752         struct ecore_func_state_params func_params = { NULL };
5753         struct ecore_func_start_params *start_params =
5754             &func_params.params.start;
5755
5756         /* Prepare parameters for function state transitions */
5757         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5758
5759         func_params.f_obj = &sc->func_obj;
5760         func_params.cmd = ECORE_F_CMD_START;
5761
5762         /* Function parameters */
5763         start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5764         start_params->sd_vlan_tag = OVLAN(sc);
5765
5766         if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5767                 start_params->network_cos_mode = STATIC_COS;
5768         } else {                /* CHIP_IS_E1X */
5769                 start_params->network_cos_mode = FW_WRR;
5770         }
5771
5772         start_params->gre_tunnel_mode = 0;
5773         start_params->gre_tunnel_rss = 0;
5774
5775         return ecore_func_state_change(sc, &func_params);
5776 }
5777
5778 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5779 {
5780         uint16_t pmcsr;
5781
5782         /* If there is no power capability, silently succeed */
5783         if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5784                 PMD_DRV_LOG(WARNING, "No power capability");
5785                 return 0;
5786         }
5787
5788         pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5789                  2);
5790
5791         switch (state) {
5792         case PCI_PM_D0:
5793                 pci_write_word(sc,
5794                                (sc->devinfo.pcie_pm_cap_reg +
5795                                 PCIR_POWER_STATUS),
5796                                ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5797
5798                 if (pmcsr & PCIM_PSTAT_DMASK) {
5799                         /* delay required during transition out of D3hot */
5800                         DELAY(20000);
5801                 }
5802
5803                 break;
5804
5805         case PCI_PM_D3hot:
5806                 /* don't shut down the power for emulation and FPGA */
5807                 if (CHIP_REV_IS_SLOW(sc)) {
5808                         return 0;
5809                 }
5810
5811                 pmcsr &= ~PCIM_PSTAT_DMASK;
5812                 pmcsr |= PCIM_PSTAT_D3;
5813
5814                 if (sc->wol) {
5815                         pmcsr |= PCIM_PSTAT_PMEENABLE;
5816                 }
5817
5818                 pci_write_long(sc,
5819                                (sc->devinfo.pcie_pm_cap_reg +
5820                                 PCIR_POWER_STATUS), pmcsr);
5821
5822                 /*
5823                  * No more memory access after this point until device is brought back
5824                  * to D0 state.
5825                  */
5826                 break;
5827
5828         default:
5829                 PMD_DRV_LOG(NOTICE, "Can't support PCI power state = %d",
5830                             state);
5831                 return -1;
5832         }
5833
5834         return 0;
5835 }
5836
5837 /* return true if succeeded to acquire the lock */
5838 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5839 {
5840         uint32_t lock_status;
5841         uint32_t resource_bit = (1 << resource);
5842         int func = SC_FUNC(sc);
5843         uint32_t hw_lock_control_reg;
5844
5845         /* Validating that the resource is within range */
5846         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5847                 PMD_DRV_LOG(INFO,
5848                             "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5849                             resource, HW_LOCK_MAX_RESOURCE_VALUE);
5850                 return FALSE;
5851         }
5852
5853         if (func <= 5) {
5854                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5855         } else {
5856                 hw_lock_control_reg =
5857                     (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5858         }
5859
5860         /* try to acquire the lock */
5861         REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5862         lock_status = REG_RD(sc, hw_lock_control_reg);
5863         if (lock_status & resource_bit) {
5864                 return TRUE;
5865         }
5866
5867         PMD_DRV_LOG(NOTICE, "Failed to get a resource lock 0x%x", resource);
5868
5869         return FALSE;
5870 }
5871
5872 /*
5873  * Get the recovery leader resource id according to the engine this function
5874  * belongs to. Currently only only 2 engines is supported.
5875  */
5876 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5877 {
5878         if (SC_PATH(sc)) {
5879                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5880         } else {
5881                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5882         }
5883 }
5884
5885 /* try to acquire a leader lock for current engine */
5886 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5887 {
5888         return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5889 }
5890
5891 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5892 {
5893         return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5894 }
5895
5896 /* close gates #2, #3 and #4 */
5897 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5898 {
5899         uint32_t val;
5900
5901         /* gates #2 and #4a are closed/opened */
5902         /* #4 */
5903         REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5904         /* #2 */
5905         REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5906
5907         /* #3 */
5908         if (CHIP_IS_E1x(sc)) {
5909 /* prevent interrupts from HC on both ports */
5910                 val = REG_RD(sc, HC_REG_CONFIG_1);
5911                 if (close)
5912                         REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5913                                                      HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5914                 else
5915                         REG_WR(sc, HC_REG_CONFIG_1,
5916                                (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5917
5918                 val = REG_RD(sc, HC_REG_CONFIG_0);
5919                 if (close)
5920                         REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5921                                                      HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5922                 else
5923                         REG_WR(sc, HC_REG_CONFIG_0,
5924                                (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5925
5926         } else {
5927 /* Prevent incomming interrupts in IGU */
5928                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5929
5930                 if (close)
5931                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5932                                (val & ~(uint32_t)
5933                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5934                 else
5935                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5936                                (val |
5937                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5938         }
5939
5940         wmb();
5941 }
5942
5943 /* poll for pending writes bit, it should get cleared in no more than 1s */
5944 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5945 {
5946         uint32_t cnt = 1000;
5947         uint32_t pend_bits = 0;
5948
5949         do {
5950                 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5951
5952                 if (pend_bits == 0) {
5953                         break;
5954                 }
5955
5956                 DELAY(1000);
5957         } while (cnt-- > 0);
5958
5959         if (cnt <= 0) {
5960                 PMD_DRV_LOG(NOTICE, "Still pending IGU requests bits=0x%08x!",
5961                             pend_bits);
5962                 return -1;
5963         }
5964
5965         return 0;
5966 }
5967
5968 #define SHARED_MF_CLP_MAGIC  0x80000000 /* 'magic' bit */
5969
5970 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5971 {
5972         /* Do some magic... */
5973         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5974         *magic_val = val & SHARED_MF_CLP_MAGIC;
5975         MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
5976 }
5977
5978 /* restore the value of the 'magic' bit */
5979 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
5980 {
5981         /* Restore the 'magic' bit value... */
5982         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5983         MFCFG_WR(sc, shared_mf_config.clp_mb,
5984                  (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
5985 }
5986
5987 /* prepare for MCP reset, takes care of CLP configurations */
5988 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5989 {
5990         uint32_t shmem;
5991         uint32_t validity_offset;
5992
5993         /* set `magic' bit in order to save MF config */
5994         bnx2x_clp_reset_prep(sc, magic_val);
5995
5996         /* get shmem offset */
5997         shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
5998         validity_offset =
5999             offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
6000
6001         /* Clear validity map flags */
6002         if (shmem > 0) {
6003                 REG_WR(sc, shmem + validity_offset, 0);
6004         }
6005 }
6006
6007 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
6008 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
6009
6010 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6011 {
6012         /* special handling for emulation and FPGA (10 times longer) */
6013         if (CHIP_REV_IS_SLOW(sc)) {
6014                 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6015         } else {
6016                 DELAY((MCP_ONE_TIMEOUT) * 1000);
6017         }
6018 }
6019
6020 /* initialize shmem_base and waits for validity signature to appear */
6021 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6022 {
6023         int cnt = 0;
6024         uint32_t val = 0;
6025
6026         do {
6027                 sc->devinfo.shmem_base =
6028                     sc->link_params.shmem_base =
6029                     REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6030
6031                 if (sc->devinfo.shmem_base) {
6032                         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6033                         if (val & SHR_MEM_VALIDITY_MB)
6034                                 return 0;
6035                 }
6036
6037                 bnx2x_mcp_wait_one(sc);
6038
6039         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6040
6041         PMD_DRV_LOG(NOTICE, "BAD MCP validity signature");
6042
6043         return -1;
6044 }
6045
6046 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6047 {
6048         int rc = bnx2x_init_shmem(sc);
6049
6050         /* Restore the `magic' bit value */
6051         bnx2x_clp_reset_done(sc, magic_val);
6052
6053         return rc;
6054 }
6055
6056 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6057 {
6058         REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6059         REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6060         wmb();
6061 }
6062
6063 /*
6064  * Reset the whole chip except for:
6065  *      - PCIE core
6066  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6067  *      - IGU
6068  *      - MISC (including AEU)
6069  *      - GRC
6070  *      - RBCN, RBCP
6071  */
6072 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6073 {
6074         uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6075         uint32_t global_bits2, stay_reset2;
6076
6077         /*
6078          * Bits that have to be set in reset_mask2 if we want to reset 'global'
6079          * (per chip) blocks.
6080          */
6081         global_bits2 =
6082             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6083             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6084
6085         /*
6086          * Don't reset the following blocks.
6087          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6088          *            reset, as in 4 port device they might still be owned
6089          *            by the MCP (there is only one leader per path).
6090          */
6091         not_reset_mask1 =
6092             MISC_REGISTERS_RESET_REG_1_RST_HC |
6093             MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6094             MISC_REGISTERS_RESET_REG_1_RST_PXP;
6095
6096         not_reset_mask2 =
6097             MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6098             MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6099             MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6100             MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6101             MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6102             MISC_REGISTERS_RESET_REG_2_RST_GRC |
6103             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6104             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6105             MISC_REGISTERS_RESET_REG_2_RST_ATC |
6106             MISC_REGISTERS_RESET_REG_2_PGLC |
6107             MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6108             MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6109             MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6110             MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6111             MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6112
6113         /*
6114          * Keep the following blocks in reset:
6115          *  - all xxMACs are handled by the elink code.
6116          */
6117         stay_reset2 =
6118             MISC_REGISTERS_RESET_REG_2_XMAC |
6119             MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6120
6121         /* Full reset masks according to the chip */
6122         reset_mask1 = 0xffffffff;
6123
6124         if (CHIP_IS_E1H(sc))
6125                 reset_mask2 = 0x1ffff;
6126         else if (CHIP_IS_E2(sc))
6127                 reset_mask2 = 0xfffff;
6128         else                    /* CHIP_IS_E3 */
6129                 reset_mask2 = 0x3ffffff;
6130
6131         /* Don't reset global blocks unless we need to */
6132         if (!global)
6133                 reset_mask2 &= ~global_bits2;
6134
6135         /*
6136          * In case of attention in the QM, we need to reset PXP
6137          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6138          * because otherwise QM reset would release 'close the gates' shortly
6139          * before resetting the PXP, then the PSWRQ would send a write
6140          * request to PGLUE. Then when PXP is reset, PGLUE would try to
6141          * read the payload data from PSWWR, but PSWWR would not
6142          * respond. The write queue in PGLUE would stuck, dmae commands
6143          * would not return. Therefore it's important to reset the second
6144          * reset register (containing the
6145          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6146          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6147          * bit).
6148          */
6149         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6150                reset_mask2 & (~not_reset_mask2));
6151
6152         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6153                reset_mask1 & (~not_reset_mask1));
6154
6155         mb();
6156         wmb();
6157
6158         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6159                reset_mask2 & (~stay_reset2));
6160
6161         mb();
6162         wmb();
6163
6164         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6165         wmb();
6166 }
6167
6168 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6169 {
6170         int cnt = 1000;
6171         uint32_t val = 0;
6172         uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6173         uint32_t tags_63_32 = 0;
6174
6175         /* Empty the Tetris buffer, wait for 1s */
6176         do {
6177                 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6178                 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6179                 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6180                 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6181                 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6182                 if (CHIP_IS_E3(sc)) {
6183                         tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6184                 }
6185
6186                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6187                     ((port_is_idle_0 & 0x1) == 0x1) &&
6188                     ((port_is_idle_1 & 0x1) == 0x1) &&
6189                     (pgl_exp_rom2 == 0xffffffff) &&
6190                     (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6191                         break;
6192                 DELAY(1000);
6193         } while (cnt-- > 0);
6194
6195         if (cnt <= 0) {
6196                 PMD_DRV_LOG(NOTICE,
6197                             "ERROR: Tetris buffer didn't get empty or there "
6198                             "are still outstanding read requests after 1s! "
6199                             "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6200                             "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6201                             sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6202                             pgl_exp_rom2);
6203                 return -1;
6204         }
6205
6206         mb();
6207
6208         /* Close gates #2, #3 and #4 */
6209         bnx2x_set_234_gates(sc, TRUE);
6210
6211         /* Poll for IGU VQs for 57712 and newer chips */
6212         if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6213                 return -1;
6214         }
6215
6216         /* clear "unprepared" bit */
6217         REG_WR(sc, MISC_REG_UNPREPARED, 0);
6218         mb();
6219
6220         /* Make sure all is written to the chip before the reset */
6221         wmb();
6222
6223         /*
6224          * Wait for 1ms to empty GLUE and PCI-E core queues,
6225          * PSWHST, GRC and PSWRD Tetris buffer.
6226          */
6227         DELAY(1000);
6228
6229         /* Prepare to chip reset: */
6230         /* MCP */
6231         if (global) {
6232                 bnx2x_reset_mcp_prep(sc, &val);
6233         }
6234
6235         /* PXP */
6236         bnx2x_pxp_prep(sc);
6237         mb();
6238
6239         /* reset the chip */
6240         bnx2x_process_kill_chip_reset(sc, global);
6241         mb();
6242
6243         /* Recover after reset: */
6244         /* MCP */
6245         if (global && bnx2x_reset_mcp_comp(sc, val)) {
6246                 return -1;
6247         }
6248
6249         /* Open the gates #2, #3 and #4 */
6250         bnx2x_set_234_gates(sc, FALSE);
6251
6252         return 0;
6253 }
6254
6255 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6256 {
6257         int rc = 0;
6258         uint8_t global = bnx2x_reset_is_global(sc);
6259         uint32_t load_code;
6260
6261         /*
6262          * If not going to reset MCP, load "fake" driver to reset HW while
6263          * driver is owner of the HW.
6264          */
6265         if (!global && !BNX2X_NOMCP(sc)) {
6266                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6267                                            DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6268                 if (!load_code) {
6269                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6270                         rc = -1;
6271                         goto exit_leader_reset;
6272                 }
6273
6274                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6275                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6276                         PMD_DRV_LOG(NOTICE,
6277                                     "MCP unexpected response, aborting");
6278                         rc = -1;
6279                         goto exit_leader_reset2;
6280                 }
6281
6282                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6283                 if (!load_code) {
6284                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6285                         rc = -1;
6286                         goto exit_leader_reset2;
6287                 }
6288         }
6289
6290         /* try to recover after the failure */
6291         if (bnx2x_process_kill(sc, global)) {
6292                 PMD_DRV_LOG(NOTICE, "Something bad occurred on engine %d!",
6293                             SC_PATH(sc));
6294                 rc = -1;
6295                 goto exit_leader_reset2;
6296         }
6297
6298         /*
6299          * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6300          * state.
6301          */
6302         bnx2x_set_reset_done(sc);
6303         if (global) {
6304                 bnx2x_clear_reset_global(sc);
6305         }
6306
6307 exit_leader_reset2:
6308
6309         /* unload "fake driver" if it was loaded */
6310         if (!global &&!BNX2X_NOMCP(sc)) {
6311                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6312                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6313         }
6314
6315 exit_leader_reset:
6316
6317         sc->is_leader = 0;
6318         bnx2x_release_leader_lock(sc);
6319
6320         mb();
6321         return rc;
6322 }
6323
6324 /*
6325  * prepare INIT transition, parameters configured:
6326  *   - HC configuration
6327  *   - Queue's CDU context
6328  */
6329 static void
6330 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6331                    struct ecore_queue_init_params *init_params)
6332 {
6333         uint8_t cos;
6334         int cxt_index, cxt_offset;
6335
6336         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6337         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6338
6339         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6340         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6341
6342         /* HC rate */
6343         init_params->rx.hc_rate =
6344             sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6345         init_params->tx.hc_rate =
6346             sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6347
6348         /* FW SB ID */
6349         init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6350
6351         /* CQ index among the SB indices */
6352         init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6353         init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6354
6355         /* set maximum number of COSs supported by this queue */
6356         init_params->max_cos = sc->max_cos;
6357
6358         /* set the context pointers queue object */
6359         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6360                 cxt_index = fp->index / ILT_PAGE_CIDS;
6361                 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6362                 init_params->cxts[cos] =
6363                     &sc->context[cxt_index].vcxt[cxt_offset].eth;
6364         }
6365 }
6366
6367 /* set flags that are common for the Tx-only and not normal connections */
6368 static unsigned long
6369 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6370 {
6371         unsigned long flags = 0;
6372
6373         /* PF driver will always initialize the Queue to an ACTIVE state */
6374         bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6375
6376         /*
6377          * tx only connections collect statistics (on the same index as the
6378          * parent connection). The statistics are zeroed when the parent
6379          * connection is initialized.
6380          */
6381
6382         bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6383         if (zero_stats) {
6384                 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6385         }
6386
6387         /*
6388          * tx only connections can support tx-switching, though their
6389          * CoS-ness doesn't survive the loopback
6390          */
6391         if (sc->flags & BNX2X_TX_SWITCHING) {
6392                 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6393         }
6394
6395         bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6396
6397         return flags;
6398 }
6399
6400 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6401 {
6402         unsigned long flags = 0;
6403
6404         if (IS_MF_SD(sc)) {
6405                 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6406         }
6407
6408         if (leading) {
6409                 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6410                 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6411         }
6412
6413         bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6414
6415         /* merge with common flags */
6416         return flags | bnx2x_get_common_flags(sc, TRUE);
6417 }
6418
6419 static void
6420 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6421                       struct ecore_general_setup_params *gen_init, uint8_t cos)
6422 {
6423         gen_init->stat_id = bnx2x_stats_id(fp);
6424         gen_init->spcl_id = fp->cl_id;
6425         gen_init->mtu = sc->mtu;
6426         gen_init->cos = cos;
6427 }
6428
6429 static void
6430 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6431                  struct rxq_pause_params *pause,
6432                  struct ecore_rxq_setup_params *rxq_init)
6433 {
6434         struct bnx2x_rx_queue *rxq;
6435
6436         rxq = sc->rx_queues[fp->index];
6437         if (!rxq) {
6438                 PMD_RX_LOG(ERR, "RX queue is NULL");
6439                 return;
6440         }
6441         /* pause */
6442         pause->bd_th_lo = BD_TH_LO(sc);
6443         pause->bd_th_hi = BD_TH_HI(sc);
6444
6445         pause->rcq_th_lo = RCQ_TH_LO(sc);
6446         pause->rcq_th_hi = RCQ_TH_HI(sc);
6447
6448         /* validate rings have enough entries to cross high thresholds */
6449         if (sc->dropless_fc &&
6450             pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6451                 PMD_DRV_LOG(WARNING, "rx bd ring threshold limit");
6452         }
6453
6454         if (sc->dropless_fc &&
6455             pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6456                 PMD_DRV_LOG(WARNING, "rcq ring threshold limit");
6457         }
6458
6459         pause->pri_map = 1;
6460
6461         /* rxq setup */
6462         rxq_init->dscr_map = (phys_addr_t)rxq->rx_ring_phys_addr;
6463         rxq_init->rcq_map = (phys_addr_t)rxq->cq_ring_phys_addr;
6464         rxq_init->rcq_np_map = (phys_addr_t)(rxq->cq_ring_phys_addr +
6465                                               BNX2X_PAGE_SIZE);
6466
6467         /*
6468          * This should be a maximum number of data bytes that may be
6469          * placed on the BD (not including paddings).
6470          */
6471         rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6472
6473         rxq_init->cl_qzone_id = fp->cl_qzone_id;
6474         rxq_init->rss_engine_id = SC_FUNC(sc);
6475         rxq_init->mcast_engine_id = SC_FUNC(sc);
6476
6477         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6478         rxq_init->fw_sb_id = fp->fw_sb_id;
6479
6480         rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6481
6482         /*
6483          * configure silent vlan removal
6484          * if multi function mode is afex, then mask default vlan
6485          */
6486         if (IS_MF_AFEX(sc)) {
6487                 rxq_init->silent_removal_value =
6488                     sc->devinfo.mf_info.afex_def_vlan_tag;
6489                 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6490         }
6491 }
6492
6493 static void
6494 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6495                  struct ecore_txq_setup_params *txq_init, uint8_t cos)
6496 {
6497         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6498
6499         if (!txq) {
6500                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6501                 return;
6502         }
6503         txq_init->dscr_map = (phys_addr_t)txq->tx_ring_phys_addr;
6504         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6505         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6506         txq_init->fw_sb_id = fp->fw_sb_id;
6507
6508         /*
6509          * set the TSS leading client id for TX classfication to the
6510          * leading RSS client id
6511          */
6512         txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6513 }
6514
6515 /*
6516  * This function performs 2 steps in a queue state machine:
6517  *   1) RESET->INIT
6518  *   2) INIT->SETUP
6519  */
6520 static int
6521 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6522 {
6523         struct ecore_queue_state_params q_params = { NULL };
6524         struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6525         int rc;
6526
6527         PMD_DRV_LOG(DEBUG, "setting up queue %d", fp->index);
6528
6529         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6530
6531         q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6532
6533         /* we want to wait for completion in this context */
6534         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6535
6536         /* prepare the INIT parameters */
6537         bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6538
6539         /* Set the command */
6540         q_params.cmd = ECORE_Q_CMD_INIT;
6541
6542         /* Change the state to INIT */
6543         rc = ecore_queue_state_change(sc, &q_params);
6544         if (rc) {
6545                 PMD_DRV_LOG(NOTICE, "Queue(%d) INIT failed", fp->index);
6546                 return rc;
6547         }
6548
6549         PMD_DRV_LOG(DEBUG, "init complete");
6550
6551         /* now move the Queue to the SETUP state */
6552         memset(setup_params, 0, sizeof(*setup_params));
6553
6554         /* set Queue flags */
6555         setup_params->flags = bnx2x_get_q_flags(sc, leading);
6556
6557         /* set general SETUP parameters */
6558         bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6559                               FIRST_TX_COS_INDEX);
6560
6561         bnx2x_pf_rx_q_prep(sc, fp,
6562                          &setup_params->pause_params,
6563                          &setup_params->rxq_params);
6564
6565         bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6566
6567         /* Set the command */
6568         q_params.cmd = ECORE_Q_CMD_SETUP;
6569
6570         /* change the state to SETUP */
6571         rc = ecore_queue_state_change(sc, &q_params);
6572         if (rc) {
6573                 PMD_DRV_LOG(NOTICE, "Queue(%d) SETUP failed", fp->index);
6574                 return rc;
6575         }
6576
6577         return rc;
6578 }
6579
6580 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6581 {
6582         if (IS_PF(sc))
6583                 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6584         else                    /* VF */
6585                 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6586 }
6587
6588 static int
6589 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6590                   uint8_t config_hash)
6591 {
6592         struct ecore_config_rss_params params = { NULL };
6593         uint32_t i;
6594
6595         /*
6596          * Although RSS is meaningless when there is a single HW queue we
6597          * still need it enabled in order to have HW Rx hash generated.
6598          */
6599
6600         params.rss_obj = rss_obj;
6601
6602         bnx2x_set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
6603
6604         bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, &params.rss_flags);
6605
6606         /* RSS configuration */
6607         bnx2x_set_bit(ECORE_RSS_IPV4, &params.rss_flags);
6608         bnx2x_set_bit(ECORE_RSS_IPV4_TCP, &params.rss_flags);
6609         bnx2x_set_bit(ECORE_RSS_IPV6, &params.rss_flags);
6610         bnx2x_set_bit(ECORE_RSS_IPV6_TCP, &params.rss_flags);
6611         if (rss_obj->udp_rss_v4) {
6612                 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, &params.rss_flags);
6613         }
6614         if (rss_obj->udp_rss_v6) {
6615                 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, &params.rss_flags);
6616         }
6617
6618         /* Hash bits */
6619         params.rss_result_mask = MULTI_MASK;
6620
6621         (void)rte_memcpy(params.ind_table, rss_obj->ind_table,
6622                          sizeof(params.ind_table));
6623
6624         if (config_hash) {
6625 /* RSS keys */
6626                 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6627                         params.rss_key[i] = (uint32_t) rte_rand();
6628                 }
6629
6630                 bnx2x_set_bit(ECORE_RSS_SET_SRCH, &params.rss_flags);
6631         }
6632
6633         if (IS_PF(sc))
6634                 return ecore_config_rss(sc, &params);
6635         else
6636                 return bnx2x_vf_config_rss(sc, &params);
6637 }
6638
6639 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6640 {
6641         return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6642 }
6643
6644 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6645 {
6646         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6647         uint32_t i;
6648
6649         /*
6650          * Prepare the initial contents of the indirection table if
6651          * RSS is enabled
6652          */
6653         for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6654                 sc->rss_conf_obj.ind_table[i] =
6655                     (sc->fp->cl_id + (i % num_eth_queues));
6656         }
6657
6658         if (sc->udp_rss) {
6659                 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6660         }
6661
6662         /*
6663          * For 57711 SEARCHER configuration (rss_keys) is
6664          * per-port, so if explicit configuration is needed, do it only
6665          * for a PMF.
6666          *
6667          * For 57712 and newer it's a per-function configuration.
6668          */
6669         return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6670 }
6671
6672 static int
6673 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6674                 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6675                 unsigned long *ramrod_flags)
6676 {
6677         struct ecore_vlan_mac_ramrod_params ramrod_param;
6678         int rc;
6679
6680         memset(&ramrod_param, 0, sizeof(ramrod_param));
6681
6682         /* fill in general parameters */
6683         ramrod_param.vlan_mac_obj = obj;
6684         ramrod_param.ramrod_flags = *ramrod_flags;
6685
6686         /* fill a user request section if needed */
6687         if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6688                 (void)rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6689                                  ETH_ALEN);
6690
6691                 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6692
6693 /* Set the command: ADD or DEL */
6694                 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6695                     ECORE_VLAN_MAC_DEL;
6696         }
6697
6698         rc = ecore_config_vlan_mac(sc, &ramrod_param);
6699
6700         if (rc == ECORE_EXISTS) {
6701                 PMD_DRV_LOG(INFO, "Failed to schedule ADD operations (EEXIST)");
6702 /* do not treat adding same MAC as error */
6703                 rc = 0;
6704         } else if (rc < 0) {
6705                 PMD_DRV_LOG(ERR,
6706                             "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6707         }
6708
6709         return rc;
6710 }
6711
6712 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6713 {
6714         unsigned long ramrod_flags = 0;
6715
6716         PMD_DRV_LOG(DEBUG, "Adding Ethernet MAC");
6717
6718         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6719
6720         /* Eth MAC is set on RSS leading client (fp[0]) */
6721         return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6722                                &sc->sp_objs->mac_obj,
6723                                set, ECORE_ETH_MAC, &ramrod_flags);
6724 }
6725
6726 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6727 {
6728         uint32_t sel_phy_idx = 0;
6729
6730         if (sc->link_params.num_phys <= 1) {
6731                 return ELINK_INT_PHY;
6732         }
6733
6734         if (sc->link_vars.link_up) {
6735                 sel_phy_idx = ELINK_EXT_PHY1;
6736 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6737                 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6738                     (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6739                      ELINK_SUPPORTED_FIBRE))
6740                         sel_phy_idx = ELINK_EXT_PHY2;
6741         } else {
6742                 switch (elink_phy_selection(&sc->link_params)) {
6743                 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6744                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6745                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6746                         sel_phy_idx = ELINK_EXT_PHY1;
6747                         break;
6748                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6749                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6750                         sel_phy_idx = ELINK_EXT_PHY2;
6751                         break;
6752                 }
6753         }
6754
6755         return sel_phy_idx;
6756 }
6757
6758 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6759 {
6760         uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6761
6762         /*
6763          * The selected activated PHY is always after swapping (in case PHY
6764          * swapping is enabled). So when swapping is enabled, we need to reverse
6765          * the configuration
6766          */
6767
6768         if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6769                 if (sel_phy_idx == ELINK_EXT_PHY1)
6770                         sel_phy_idx = ELINK_EXT_PHY2;
6771                 else if (sel_phy_idx == ELINK_EXT_PHY2)
6772                         sel_phy_idx = ELINK_EXT_PHY1;
6773         }
6774
6775         return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6776 }
6777
6778 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6779 {
6780         /*
6781          * Initialize link parameters structure variables
6782          * It is recommended to turn off RX FC for jumbo frames
6783          * for better performance
6784          */
6785         if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6786                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6787         } else {
6788                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6789         }
6790 }
6791
6792 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6793 {
6794         uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6795         switch (sc->link_vars.ieee_fc &
6796                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6797         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6798         default:
6799                 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6800                                                    ADVERTISED_Pause);
6801                 break;
6802
6803         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6804                 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6805                                                   ADVERTISED_Pause);
6806                 break;
6807
6808         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6809                 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6810                 break;
6811         }
6812 }
6813
6814 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6815 {
6816         uint16_t line_speed = sc->link_vars.line_speed;
6817         if (IS_MF(sc)) {
6818                 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6819                                                       sc->devinfo.
6820                                                       mf_info.mf_config[SC_VN
6821                                                                         (sc)]);
6822
6823 /* calculate the current MAX line speed limit for the MF devices */
6824                 if (IS_MF_SI(sc)) {
6825                         line_speed = (line_speed * maxCfg) / 100;
6826                 } else {        /* SD mode */
6827                         uint16_t vn_max_rate = maxCfg * 100;
6828
6829                         if (vn_max_rate < line_speed) {
6830                                 line_speed = vn_max_rate;
6831                         }
6832                 }
6833         }
6834
6835         return line_speed;
6836 }
6837
6838 static void
6839 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6840 {
6841         uint16_t line_speed = bnx2x_get_mf_speed(sc);
6842
6843         memset(data, 0, sizeof(*data));
6844
6845         /* fill the report data with the effective line speed */
6846         data->line_speed = line_speed;
6847
6848         /* Link is down */
6849         if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6850                 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6851                             &data->link_report_flags);
6852         }
6853
6854         /* Full DUPLEX */
6855         if (sc->link_vars.duplex == DUPLEX_FULL) {
6856                 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6857                             &data->link_report_flags);
6858         }
6859
6860         /* Rx Flow Control is ON */
6861         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6862                 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6863         }
6864
6865         /* Tx Flow Control is ON */
6866         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6867                 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6868         }
6869 }
6870
6871 /* report link status to OS, should be called under phy_lock */
6872 static void bnx2x_link_report(struct bnx2x_softc *sc)
6873 {
6874         struct bnx2x_link_report_data cur_data;
6875
6876         /* reread mf_cfg */
6877         if (IS_PF(sc)) {
6878                 bnx2x_read_mf_cfg(sc);
6879         }
6880
6881         /* Read the current link report info */
6882         bnx2x_fill_report_data(sc, &cur_data);
6883
6884         /* Don't report link down or exactly the same link status twice */
6885         if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6886             (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6887                           &sc->last_reported_link.link_report_flags) &&
6888              bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6889                           &cur_data.link_report_flags))) {
6890                 return;
6891         }
6892
6893         sc->link_cnt++;
6894
6895         /* report new link params and remember the state for the next time */
6896         (void)rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6897
6898         if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6899                          &cur_data.link_report_flags)) {
6900                 PMD_DRV_LOG(INFO, "NIC Link is Down");
6901         } else {
6902                 __rte_unused const char *duplex;
6903                 __rte_unused const char *flow;
6904
6905                 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6906                                            &cur_data.link_report_flags)) {
6907                         duplex = "full";
6908                 } else {
6909                         duplex = "half";
6910                 }
6911
6912 /*
6913  * Handle the FC at the end so that only these flags would be
6914  * possibly set. This way we may easily check if there is no FC
6915  * enabled.
6916  */
6917                 if (cur_data.link_report_flags) {
6918                         if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6919                                          &cur_data.link_report_flags) &&
6920                             bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6921                                          &cur_data.link_report_flags)) {
6922                                 flow = "ON - receive & transmit";
6923                         } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6924                                                 &cur_data.link_report_flags) &&
6925                                    !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6926                                                  &cur_data.link_report_flags)) {
6927                                 flow = "ON - receive";
6928                         } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6929                                                  &cur_data.link_report_flags) &&
6930                                    bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6931                                                 &cur_data.link_report_flags)) {
6932                                 flow = "ON - transmit";
6933                         } else {
6934                                 flow = "none";  /* possible? */
6935                         }
6936                 } else {
6937                         flow = "none";
6938                 }
6939
6940                 PMD_DRV_LOG(INFO,
6941                             "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6942                             cur_data.line_speed, duplex, flow);
6943         }
6944 }
6945
6946 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6947 {
6948         if (sc->state != BNX2X_STATE_OPEN) {
6949                 return;
6950         }
6951
6952         if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
6953                 elink_link_status_update(&sc->link_params, &sc->link_vars);
6954         } else {
6955                 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
6956                                           ELINK_SUPPORTED_10baseT_Full |
6957                                           ELINK_SUPPORTED_100baseT_Half |
6958                                           ELINK_SUPPORTED_100baseT_Full |
6959                                           ELINK_SUPPORTED_1000baseT_Full |
6960                                           ELINK_SUPPORTED_2500baseX_Full |
6961                                           ELINK_SUPPORTED_10000baseT_Full |
6962                                           ELINK_SUPPORTED_TP |
6963                                           ELINK_SUPPORTED_FIBRE |
6964                                           ELINK_SUPPORTED_Autoneg |
6965                                           ELINK_SUPPORTED_Pause |
6966                                           ELINK_SUPPORTED_Asym_Pause);
6967                 sc->port.advertising[0] = sc->port.supported[0];
6968
6969                 sc->link_params.sc = sc;
6970                 sc->link_params.port = SC_PORT(sc);
6971                 sc->link_params.req_duplex[0] = DUPLEX_FULL;
6972                 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
6973                 sc->link_params.req_line_speed[0] = SPEED_10000;
6974                 sc->link_params.speed_cap_mask[0] = 0x7f0000;
6975                 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
6976
6977                 if (CHIP_REV_IS_FPGA(sc)) {
6978                         sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
6979                         sc->link_vars.line_speed = ELINK_SPEED_1000;
6980                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6981                                                      LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
6982                 } else {
6983                         sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
6984                         sc->link_vars.line_speed = ELINK_SPEED_10000;
6985                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6986                                                      LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
6987                 }
6988
6989                 sc->link_vars.link_up = 1;
6990
6991                 sc->link_vars.duplex = DUPLEX_FULL;
6992                 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
6993
6994                 if (IS_PF(sc)) {
6995                         REG_WR(sc,
6996                                NIG_REG_EGRESS_DRAIN0_MODE +
6997                                sc->link_params.port * 4, 0);
6998                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6999                         bnx2x_link_report(sc);
7000                 }
7001         }
7002
7003         if (IS_PF(sc)) {
7004                 if (sc->link_vars.link_up) {
7005                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7006                 } else {
7007                         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7008                 }
7009                 bnx2x_link_report(sc);
7010         } else {
7011                 bnx2x_link_report(sc);
7012                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7013         }
7014 }
7015
7016 static void bnx2x_periodic_start(struct bnx2x_softc *sc)
7017 {
7018         atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
7019 }
7020
7021 static void bnx2x_periodic_stop(struct bnx2x_softc *sc)
7022 {
7023         atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
7024 }
7025
7026 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7027 {
7028         int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7029         uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7030         struct elink_params *lp = &sc->link_params;
7031
7032         bnx2x_set_requested_fc(sc);
7033
7034         if (CHIP_REV_IS_SLOW(sc)) {
7035                 uint32_t bond = CHIP_BOND_ID(sc);
7036                 uint32_t feat = 0;
7037
7038                 if (CHIP_IS_E2(sc) && CHIP_IS_MODE_4_PORT(sc)) {
7039                         feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
7040                 } else if (bond & 0x4) {
7041                         if (CHIP_IS_E3(sc)) {
7042                                 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC;
7043                         } else {
7044                                 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
7045                         }
7046                 } else if (bond & 0x8) {
7047                         if (CHIP_IS_E3(sc)) {
7048                                 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC;
7049                         } else {
7050                                 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
7051                         }
7052                 }
7053
7054 /* disable EMAC for E3 and above */
7055                 if (bond & 0x2) {
7056                         feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
7057                 }
7058
7059                 sc->link_params.feature_config_flags |= feat;
7060         }
7061
7062         if (load_mode == LOAD_DIAG) {
7063                 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7064 /* Prefer doing PHY loopback at 10G speed, if possible */
7065                 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7066                         if (lp->speed_cap_mask[cfg_idx] &
7067                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7068                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7069                         } else {
7070                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7071                         }
7072                 }
7073         }
7074
7075         if (load_mode == LOAD_LOOPBACK_EXT) {
7076                 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7077         }
7078
7079         rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7080
7081         bnx2x_calc_fc_adv(sc);
7082
7083         if (sc->link_vars.link_up) {
7084                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7085                 bnx2x_link_report(sc);
7086         }
7087
7088         if (!CHIP_REV_IS_SLOW(sc)) {
7089                 bnx2x_periodic_start(sc);
7090         }
7091
7092         sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7093         return rc;
7094 }
7095
7096 /* update flags in shmem */
7097 static void
7098 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7099 {
7100         uint32_t drv_flags;
7101
7102         if (SHMEM2_HAS(sc, drv_flags)) {
7103                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7104                 drv_flags = SHMEM2_RD(sc, drv_flags);
7105
7106                 if (set) {
7107                         drv_flags |= flags;
7108                 } else {
7109                         drv_flags &= ~flags;
7110                 }
7111
7112                 SHMEM2_WR(sc, drv_flags, drv_flags);
7113
7114                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7115         }
7116 }
7117
7118 /* periodic timer callout routine, only runs when the interface is up */
7119 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7120 {
7121         if ((sc->state != BNX2X_STATE_OPEN) ||
7122             (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7123                 PMD_DRV_LOG(WARNING, "periodic callout exit (state=0x%x)",
7124                             sc->state);
7125                 return;
7126         }
7127         if (!CHIP_REV_IS_SLOW(sc)) {
7128 /*
7129  * This barrier is needed to ensure the ordering between the writing
7130  * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7131  * the reading here.
7132  */
7133                 mb();
7134                 if (sc->port.pmf) {
7135                         elink_period_func(&sc->link_params, &sc->link_vars);
7136                 }
7137         }
7138 #ifdef BNX2X_PULSE
7139         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7140                 int mb_idx = SC_FW_MB_IDX(sc);
7141                 uint32_t drv_pulse;
7142                 uint32_t mcp_pulse;
7143
7144                 ++sc->fw_drv_pulse_wr_seq;
7145                 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7146
7147                 drv_pulse = sc->fw_drv_pulse_wr_seq;
7148                 bnx2x_drv_pulse(sc);
7149
7150                 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7151                              MCP_PULSE_SEQ_MASK);
7152
7153 /*
7154  * The delta between driver pulse and mcp response should
7155  * be 1 (before mcp response) or 0 (after mcp response).
7156  */
7157                 if ((drv_pulse != mcp_pulse) &&
7158                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7159                         /* someone lost a heartbeat... */
7160                         PMD_DRV_LOG(ERR,
7161                                     "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7162                                     drv_pulse, mcp_pulse);
7163                 }
7164         }
7165 #endif
7166 }
7167
7168 /* start the controller */
7169 static __attribute__ ((noinline))
7170 int bnx2x_nic_load(struct bnx2x_softc *sc)
7171 {
7172         uint32_t val;
7173         uint32_t load_code = 0;
7174         int i, rc = 0;
7175
7176         PMD_INIT_FUNC_TRACE();
7177
7178         sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7179
7180         if (IS_PF(sc)) {
7181 /* must be called before memory allocation and HW init */
7182                 bnx2x_ilt_set_info(sc);
7183         }
7184
7185         bnx2x_set_fp_rx_buf_size(sc);
7186
7187         if (IS_PF(sc)) {
7188                 if (bnx2x_alloc_mem(sc) != 0) {
7189                         sc->state = BNX2X_STATE_CLOSED;
7190                         rc = -ENOMEM;
7191                         goto bnx2x_nic_load_error0;
7192                 }
7193         }
7194
7195         if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7196                 sc->state = BNX2X_STATE_CLOSED;
7197                 rc = -ENOMEM;
7198                 goto bnx2x_nic_load_error0;
7199         }
7200
7201         if (IS_VF(sc)) {
7202                 rc = bnx2x_vf_init(sc);
7203                 if (rc) {
7204                         sc->state = BNX2X_STATE_ERROR;
7205                         goto bnx2x_nic_load_error0;
7206                 }
7207         }
7208
7209         if (IS_PF(sc)) {
7210 /* set pf load just before approaching the MCP */
7211                 bnx2x_set_pf_load(sc);
7212
7213 /* if MCP exists send load request and analyze response */
7214                 if (!BNX2X_NOMCP(sc)) {
7215                         /* attempt to load pf */
7216                         if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7217                                 sc->state = BNX2X_STATE_CLOSED;
7218                                 rc = -ENXIO;
7219                                 goto bnx2x_nic_load_error1;
7220                         }
7221
7222                         /* what did the MCP say? */
7223                         if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7224                                 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7225                                 sc->state = BNX2X_STATE_CLOSED;
7226                                 rc = -ENXIO;
7227                                 goto bnx2x_nic_load_error2;
7228                         }
7229                 } else {
7230                         PMD_DRV_LOG(INFO, "Device has no MCP!");
7231                         load_code = bnx2x_nic_load_no_mcp(sc);
7232                 }
7233
7234 /* mark PMF if applicable */
7235                 bnx2x_nic_load_pmf(sc, load_code);
7236
7237 /* Init Function state controlling object */
7238                 bnx2x_init_func_obj(sc);
7239
7240 /* Initialize HW */
7241                 if (bnx2x_init_hw(sc, load_code) != 0) {
7242                         PMD_DRV_LOG(NOTICE, "HW init failed");
7243                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7244                         sc->state = BNX2X_STATE_CLOSED;
7245                         rc = -ENXIO;
7246                         goto bnx2x_nic_load_error2;
7247                 }
7248         }
7249
7250         bnx2x_nic_init(sc, load_code);
7251
7252         /* Init per-function objects */
7253         if (IS_PF(sc)) {
7254                 bnx2x_init_objs(sc);
7255
7256 /* set AFEX default VLAN tag to an invalid value */
7257                 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7258
7259                 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7260                 rc = bnx2x_func_start(sc);
7261                 if (rc) {
7262                         PMD_DRV_LOG(NOTICE, "Function start failed!");
7263                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7264                         sc->state = BNX2X_STATE_ERROR;
7265                         goto bnx2x_nic_load_error3;
7266                 }
7267
7268 /* send LOAD_DONE command to MCP */
7269                 if (!BNX2X_NOMCP(sc)) {
7270                         load_code =
7271                             bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7272                         if (!load_code) {
7273                                 PMD_DRV_LOG(NOTICE,
7274                                             "MCP response failure, aborting");
7275                                 sc->state = BNX2X_STATE_ERROR;
7276                                 rc = -ENXIO;
7277                                 goto bnx2x_nic_load_error3;
7278                         }
7279                 }
7280         }
7281
7282         rc = bnx2x_setup_leading(sc);
7283         if (rc) {
7284                 PMD_DRV_LOG(NOTICE, "Setup leading failed!");
7285                 sc->state = BNX2X_STATE_ERROR;
7286                 goto bnx2x_nic_load_error3;
7287         }
7288
7289         FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7290                 if (IS_PF(sc))
7291                         rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7292                 else            /* IS_VF(sc) */
7293                         rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7294
7295                 if (rc) {
7296                         PMD_DRV_LOG(NOTICE, "Queue(%d) setup failed", i);
7297                         sc->state = BNX2X_STATE_ERROR;
7298                         goto bnx2x_nic_load_error3;
7299                 }
7300         }
7301
7302         rc = bnx2x_init_rss_pf(sc);
7303         if (rc) {
7304                 PMD_DRV_LOG(NOTICE, "PF RSS init failed");
7305                 sc->state = BNX2X_STATE_ERROR;
7306                 goto bnx2x_nic_load_error3;
7307         }
7308
7309         /* now when Clients are configured we are ready to work */
7310         sc->state = BNX2X_STATE_OPEN;
7311
7312         /* Configure a ucast MAC */
7313         if (IS_PF(sc)) {
7314                 rc = bnx2x_set_eth_mac(sc, TRUE);
7315         } else {                /* IS_VF(sc) */
7316                 rc = bnx2x_vf_set_mac(sc, TRUE);
7317         }
7318
7319         if (rc) {
7320                 PMD_DRV_LOG(NOTICE, "Setting Ethernet MAC failed");
7321                 sc->state = BNX2X_STATE_ERROR;
7322                 goto bnx2x_nic_load_error3;
7323         }
7324
7325         if (sc->port.pmf) {
7326                 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7327                 if (rc) {
7328                         sc->state = BNX2X_STATE_ERROR;
7329                         goto bnx2x_nic_load_error3;
7330                 }
7331         }
7332
7333         sc->link_params.feature_config_flags &=
7334             ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7335
7336         /* start the Tx */
7337         switch (LOAD_OPEN) {
7338         case LOAD_NORMAL:
7339         case LOAD_OPEN:
7340                 break;
7341
7342         case LOAD_DIAG:
7343         case LOAD_LOOPBACK_EXT:
7344                 sc->state = BNX2X_STATE_DIAG;
7345                 break;
7346
7347         default:
7348                 break;
7349         }
7350
7351         if (sc->port.pmf) {
7352                 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7353         } else {
7354                 bnx2x_link_status_update(sc);
7355         }
7356
7357         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7358 /* mark driver is loaded in shmem2 */
7359                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7360                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7361                           (val |
7362                            DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7363                            DRV_FLAGS_CAPABILITIES_LOADED_L2));
7364         }
7365
7366         /* start fast path */
7367         /* Initialize Rx filter */
7368         bnx2x_set_rx_mode(sc);
7369
7370         /* wait for all pending SP commands to complete */
7371         if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7372                 PMD_DRV_LOG(NOTICE, "Timeout waiting for all SPs to complete!");
7373                 bnx2x_periodic_stop(sc);
7374                 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7375                 return -ENXIO;
7376         }
7377
7378         PMD_DRV_LOG(DEBUG, "NIC successfully loaded");
7379
7380         return 0;
7381
7382 bnx2x_nic_load_error3:
7383
7384         if (IS_PF(sc)) {
7385                 bnx2x_int_disable_sync(sc, 1);
7386
7387 /* clean out queued objects */
7388                 bnx2x_squeeze_objects(sc);
7389         }
7390
7391 bnx2x_nic_load_error2:
7392
7393         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7394                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7395                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7396         }
7397
7398         sc->port.pmf = 0;
7399
7400 bnx2x_nic_load_error1:
7401
7402         /* clear pf_load status, as it was already set */
7403         if (IS_PF(sc)) {
7404                 bnx2x_clear_pf_load(sc);
7405         }
7406
7407 bnx2x_nic_load_error0:
7408
7409         bnx2x_free_fw_stats_mem(sc);
7410         bnx2x_free_mem(sc);
7411
7412         return rc;
7413 }
7414
7415 /*
7416 * Handles controller initialization.
7417 */
7418 int bnx2x_init(struct bnx2x_softc *sc)
7419 {
7420         int other_engine = SC_PATH(sc) ? 0 : 1;
7421         uint8_t other_load_status, load_status;
7422         uint8_t global = FALSE;
7423         int rc;
7424
7425         /* Check if the driver is still running and bail out if it is. */
7426         if (sc->link_vars.link_up) {
7427                 PMD_DRV_LOG(DEBUG, "Init called while driver is running!");
7428                 rc = 0;
7429                 goto bnx2x_init_done;
7430         }
7431
7432         bnx2x_set_power_state(sc, PCI_PM_D0);
7433
7434         /*
7435          * If parity occurred during the unload, then attentions and/or
7436          * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7437          * loaded on the current engine to complete the recovery. Parity recovery
7438          * is only relevant for PF driver.
7439          */
7440         if (IS_PF(sc)) {
7441                 other_load_status = bnx2x_get_load_status(sc, other_engine);
7442                 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7443
7444                 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7445                     bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7446                         do {
7447                                 /*
7448                                  * If there are attentions and they are in global blocks, set
7449                                  * the GLOBAL_RESET bit regardless whether it will be this
7450                                  * function that will complete the recovery or not.
7451                                  */
7452                                 if (global) {
7453                                         bnx2x_set_reset_global(sc);
7454                                 }
7455
7456                                 /*
7457                                  * Only the first function on the current engine should try
7458                                  * to recover in open. In case of attentions in global blocks
7459                                  * only the first in the chip should try to recover.
7460                                  */
7461                                 if ((!load_status
7462                                      && (!global ||!other_load_status))
7463                                     && bnx2x_trylock_leader_lock(sc)
7464                                     && !bnx2x_leader_reset(sc)) {
7465                                         PMD_DRV_LOG(INFO,
7466                                                     "Recovered during init");
7467                                         break;
7468                                 }
7469
7470                                 /* recovery has failed... */
7471                                 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7472
7473                                 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7474
7475                                 PMD_DRV_LOG(NOTICE,
7476                                             "Recovery flow hasn't properly "
7477                                             "completed yet, try again later. "
7478                                             "If you still see this message after a "
7479                                             "few retries then power cycle is required.");
7480
7481                                 rc = -ENXIO;
7482                                 goto bnx2x_init_done;
7483                         } while (0);
7484                 }
7485         }
7486
7487         sc->recovery_state = BNX2X_RECOVERY_DONE;
7488
7489         rc = bnx2x_nic_load(sc);
7490
7491 bnx2x_init_done:
7492
7493         if (rc) {
7494                 PMD_DRV_LOG(NOTICE, "Initialization failed, "
7495                             "stack notified driver is NOT running!");
7496         }
7497
7498         return rc;
7499 }
7500
7501 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7502 {
7503         uint32_t val = 0;
7504
7505         /*
7506          * Read the ME register to get the function number. The ME register
7507          * holds the relative-function number and absolute-function number. The
7508          * absolute-function number appears only in E2 and above. Before that
7509          * these bits always contained zero, therefore we cannot blindly use them.
7510          */
7511
7512         val = REG_RD(sc, BAR_ME_REGISTER);
7513
7514         sc->pfunc_rel =
7515             (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7516         sc->path_id =
7517             (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7518             1;
7519
7520         if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7521                 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7522         } else {
7523                 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7524         }
7525
7526         PMD_DRV_LOG(DEBUG,
7527                     "Relative function %d, Absolute function %d, Path %d",
7528                     sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7529 }
7530
7531 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7532 {
7533         uint32_t shmem2_size;
7534         uint32_t offset;
7535         uint32_t mf_cfg_offset_value;
7536
7537         /* Non 57712 */
7538         offset = (SHMEM_ADDR(sc, func_mb) +
7539                   (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7540
7541         /* 57712 plus */
7542         if (sc->devinfo.shmem2_base != 0) {
7543                 shmem2_size = SHMEM2_RD(sc, size);
7544                 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7545                         mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7546                         if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7547                                 offset = mf_cfg_offset_value;
7548                         }
7549                 }
7550         }
7551
7552         return offset;
7553 }
7554
7555 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7556 {
7557         uint32_t ret;
7558         struct bnx2x_pci_cap *caps;
7559
7560         /* ensure PCIe capability is enabled */
7561         caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7562         if (NULL != caps) {
7563                 PMD_DRV_LOG(DEBUG, "Found PCIe capability: "
7564                             "id=0x%04X type=0x%04X addr=0x%08X",
7565                             caps->id, caps->type, caps->addr);
7566                 pci_read(sc, (caps->addr + reg), &ret, 2);
7567                 return ret;
7568         }
7569
7570         PMD_DRV_LOG(WARNING, "PCIe capability NOT FOUND!!!");
7571
7572         return 0;
7573 }
7574
7575 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7576 {
7577         return (bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7578                 PCIM_EXP_STA_TRANSACTION_PND);
7579 }
7580
7581 /*
7582 * Walk the PCI capabiites list for the device to find what features are
7583 * supported. These capabilites may be enabled/disabled by firmware so it's
7584 * best to walk the list rather than make assumptions.
7585 */
7586 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7587 {
7588         PMD_INIT_FUNC_TRACE();
7589
7590         struct bnx2x_pci_cap *caps;
7591         uint16_t link_status;
7592 #ifdef RTE_LIBRTE_BNX2X_DEBUG
7593         int reg = 0;
7594 #endif
7595
7596         /* check if PCI Power Management is enabled */
7597         caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7598         if (NULL != caps) {
7599                 PMD_DRV_LOG(DEBUG, "Found PM capability: "
7600                             "id=0x%04X type=0x%04X addr=0x%08X",
7601                             caps->id, caps->type, caps->addr);
7602
7603                 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7604                 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7605         }
7606
7607         link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7608
7609         sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7610         sc->devinfo.pcie_link_width =
7611             ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7612
7613         PMD_DRV_LOG(DEBUG, "PCIe link speed=%d width=%d",
7614                     sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7615
7616         sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7617
7618         /* check if MSI capability is enabled */
7619         caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7620         if (NULL != caps) {
7621                 PMD_DRV_LOG(DEBUG, "Found MSI capability at 0x%04x", reg);
7622
7623                 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7624                 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7625         }
7626
7627         /* check if MSI-X capability is enabled */
7628         caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7629         if (NULL != caps) {
7630                 PMD_DRV_LOG(DEBUG, "Found MSI-X capability at 0x%04x", reg);
7631
7632                 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7633                 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7634         }
7635 }
7636
7637 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7638 {
7639         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7640         uint32_t val;
7641
7642         /* get the outer vlan if we're in switch-dependent mode */
7643
7644         val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7645         mf_info->ext_id = (uint16_t) val;
7646
7647         mf_info->multi_vnics_mode = 1;
7648
7649         if (!VALID_OVLAN(mf_info->ext_id)) {
7650                 PMD_DRV_LOG(NOTICE, "Invalid VLAN (%d)", mf_info->ext_id);
7651                 return 1;
7652         }
7653
7654         /* get the capabilities */
7655         if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7656             FUNC_MF_CFG_PROTOCOL_ISCSI) {
7657                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7658         } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7659                    == FUNC_MF_CFG_PROTOCOL_FCOE) {
7660                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7661         } else {
7662                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7663         }
7664
7665         mf_info->vnics_per_port =
7666             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7667
7668         return 0;
7669 }
7670
7671 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7672 {
7673         uint32_t retval = 0;
7674         uint32_t val;
7675
7676         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7677
7678         if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7679                 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7680                         retval |= MF_PROTO_SUPPORT_ETHERNET;
7681                 }
7682                 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7683                         retval |= MF_PROTO_SUPPORT_ISCSI;
7684                 }
7685                 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7686                         retval |= MF_PROTO_SUPPORT_FCOE;
7687                 }
7688         }
7689
7690         return retval;
7691 }
7692
7693 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7694 {
7695         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7696         uint32_t val;
7697
7698         /*
7699          * There is no outer vlan if we're in switch-independent mode.
7700          * If the mac is valid then assume multi-function.
7701          */
7702
7703         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7704
7705         mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7706
7707         mf_info->mf_protos_supported =
7708             bnx2x_get_shmem_ext_proto_support_flags(sc);
7709
7710         mf_info->vnics_per_port =
7711             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7712
7713         return 0;
7714 }
7715
7716 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7717 {
7718         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7719         uint32_t e1hov_tag;
7720         uint32_t func_config;
7721         uint32_t niv_config;
7722
7723         mf_info->multi_vnics_mode = 1;
7724
7725         e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7726         func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7727         niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7728
7729         mf_info->ext_id =
7730             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7731                         FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7732
7733         mf_info->default_vlan =
7734             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7735                         FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7736
7737         mf_info->niv_allowed_priorities =
7738             (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7739                        FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7740
7741         mf_info->niv_default_cos =
7742             (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7743                        FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7744
7745         mf_info->afex_vlan_mode =
7746             ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7747              FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7748
7749         mf_info->niv_mba_enabled =
7750             ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7751              FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7752
7753         mf_info->mf_protos_supported =
7754             bnx2x_get_shmem_ext_proto_support_flags(sc);
7755
7756         mf_info->vnics_per_port =
7757             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7758
7759         return 0;
7760 }
7761
7762 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7763 {
7764         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7765         uint32_t mf_cfg1;
7766         uint32_t mf_cfg2;
7767         uint32_t ovlan1;
7768         uint32_t ovlan2;
7769         uint8_t i, j;
7770
7771         /* various MF mode sanity checks... */
7772
7773         if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7774                 PMD_DRV_LOG(NOTICE,
7775                             "Enumerated function %d is marked as hidden",
7776                             SC_PORT(sc));
7777                 return 1;
7778         }
7779
7780         if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7781                 PMD_DRV_LOG(NOTICE, "vnics_per_port=%d multi_vnics_mode=%d",
7782                             mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7783                 return 1;
7784         }
7785
7786         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7787 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7788                 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7789                         PMD_DRV_LOG(NOTICE, "mf_mode=SD vnic_id=%d ovlan=%d",
7790                                     SC_VN(sc), OVLAN(sc));
7791                         return 1;
7792                 }
7793
7794                 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7795                         PMD_DRV_LOG(NOTICE,
7796                                     "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7797                                     mf_info->multi_vnics_mode, OVLAN(sc));
7798                         return 1;
7799                 }
7800
7801 /*
7802  * Verify all functions are either MF or SF mode. If MF, make sure
7803  * sure that all non-hidden functions have a valid ovlan. If SF,
7804  * make sure that all non-hidden functions have an invalid ovlan.
7805  */
7806                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7807                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7808                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7809                         if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7810                             (((mf_info->multi_vnics_mode)
7811                               && !VALID_OVLAN(ovlan1))
7812                              || ((!mf_info->multi_vnics_mode)
7813                                  && VALID_OVLAN(ovlan1)))) {
7814                                 PMD_DRV_LOG(NOTICE,
7815                                             "mf_mode=SD function %d MF config "
7816                                             "mismatch, multi_vnics_mode=%d ovlan=%d",
7817                                             i, mf_info->multi_vnics_mode,
7818                                             ovlan1);
7819                                 return 1;
7820                         }
7821                 }
7822
7823 /* Verify all funcs on the same port each have a different ovlan. */
7824                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7825                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7826                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7827                         /* iterate from the next function on the port to the max func */
7828                         for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7829                                 mf_cfg2 =
7830                                     MFCFG_RD(sc, func_mf_config[j].config);
7831                                 ovlan2 =
7832                                     MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7833                                 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7834                                     && VALID_OVLAN(ovlan1)
7835                                     && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7836                                     && VALID_OVLAN(ovlan2)
7837                                     && (ovlan1 == ovlan2)) {
7838                                         PMD_DRV_LOG(NOTICE,
7839                                                     "mf_mode=SD functions %d and %d "
7840                                                     "have the same ovlan (%d)",
7841                                                     i, j, ovlan1);
7842                                         return 1;
7843                                 }
7844                         }
7845                 }
7846         }
7847         /* MULTI_FUNCTION_SD */
7848         return 0;
7849 }
7850
7851 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7852 {
7853         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7854         uint32_t val, mac_upper;
7855         uint8_t i, vnic;
7856
7857         /* initialize mf_info defaults */
7858         mf_info->vnics_per_port = 1;
7859         mf_info->multi_vnics_mode = FALSE;
7860         mf_info->path_has_ovlan = FALSE;
7861         mf_info->mf_mode = SINGLE_FUNCTION;
7862
7863         if (!CHIP_IS_MF_CAP(sc)) {
7864                 return 0;
7865         }
7866
7867         if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7868                 PMD_DRV_LOG(NOTICE, "Invalid mf_cfg_base!");
7869                 return 1;
7870         }
7871
7872         /* get the MF mode (switch dependent / independent / single-function) */
7873
7874         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7875
7876         switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7877         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7878
7879                 mac_upper =
7880                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7881
7882                 /* check for legal upper mac bytes */
7883                 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7884                         mf_info->mf_mode = MULTI_FUNCTION_SI;
7885                 } else {
7886                         PMD_DRV_LOG(NOTICE,
7887                                     "Invalid config for Switch Independent mode");
7888                 }
7889
7890                 break;
7891
7892         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7893         case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7894
7895                 /* get outer vlan configuration */
7896                 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7897
7898                 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7899                     FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7900                         mf_info->mf_mode = MULTI_FUNCTION_SD;
7901                 } else {
7902                         PMD_DRV_LOG(NOTICE,
7903                                     "Invalid config for Switch Dependent mode");
7904                 }
7905
7906                 break;
7907
7908         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7909
7910                 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7911                 return 0;
7912
7913         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7914
7915                 /*
7916                  * Mark MF mode as NIV if MCP version includes NPAR-SD support
7917                  * and the MAC address is valid.
7918                  */
7919                 mac_upper =
7920                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7921
7922                 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7923                     (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7924                         mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7925                 } else {
7926                         PMD_DRV_LOG(NOTICE, "Invalid config for AFEX mode");
7927                 }
7928
7929                 break;
7930
7931         default:
7932
7933                 PMD_DRV_LOG(NOTICE, "Unknown MF mode (0x%08x)",
7934                             (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7935
7936                 return 1;
7937         }
7938
7939         /* set path mf_mode (which could be different than function mf_mode) */
7940         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7941                 mf_info->path_has_ovlan = TRUE;
7942         } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7943 /*
7944  * Decide on path multi vnics mode. If we're not in MF mode and in
7945  * 4-port mode, this is good enough to check vnic-0 of the other port
7946  * on the same path
7947  */
7948                 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7949                         uint8_t other_port = !(PORT_ID(sc) & 1);
7950                         uint8_t abs_func_other_port =
7951                             (SC_PATH(sc) + (2 * other_port));
7952
7953                         val =
7954                             MFCFG_RD(sc,
7955                                      func_mf_config
7956                                      [abs_func_other_port].e1hov_tag);
7957
7958                         mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7959                 }
7960         }
7961
7962         if (mf_info->mf_mode == SINGLE_FUNCTION) {
7963 /* invalid MF config */
7964                 if (SC_VN(sc) >= 1) {
7965                         PMD_DRV_LOG(NOTICE, "VNIC ID >= 1 in SF mode");
7966                         return 1;
7967                 }
7968
7969                 return 0;
7970         }
7971
7972         /* get the MF configuration */
7973         mf_info->mf_config[SC_VN(sc)] =
7974             MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7975
7976         switch (mf_info->mf_mode) {
7977         case MULTI_FUNCTION_SD:
7978
7979                 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7980                 break;
7981
7982         case MULTI_FUNCTION_SI:
7983
7984                 bnx2x_get_shmem_mf_cfg_info_si(sc);
7985                 break;
7986
7987         case MULTI_FUNCTION_AFEX:
7988
7989                 bnx2x_get_shmem_mf_cfg_info_niv(sc);
7990                 break;
7991
7992         default:
7993
7994                 PMD_DRV_LOG(NOTICE, "Get MF config failed (mf_mode=0x%08x)",
7995                             mf_info->mf_mode);
7996                 return 1;
7997         }
7998
7999         /* get the congestion management parameters */
8000
8001         vnic = 0;
8002         FOREACH_ABS_FUNC_IN_PORT(sc, i) {
8003 /* get min/max bw */
8004                 val = MFCFG_RD(sc, func_mf_config[i].config);
8005                 mf_info->min_bw[vnic] =
8006                     ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
8007                      FUNC_MF_CFG_MIN_BW_SHIFT);
8008                 mf_info->max_bw[vnic] =
8009                     ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
8010                      FUNC_MF_CFG_MAX_BW_SHIFT);
8011                 vnic++;
8012         }
8013
8014         return bnx2x_check_valid_mf_cfg(sc);
8015 }
8016
8017 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8018 {
8019         int port;
8020         uint32_t mac_hi, mac_lo, val;
8021
8022         PMD_INIT_FUNC_TRACE();
8023
8024         port = SC_PORT(sc);
8025         mac_hi = mac_lo = 0;
8026
8027         sc->link_params.sc = sc;
8028         sc->link_params.port = port;
8029
8030         /* get the hardware config info */
8031         sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8032         sc->devinfo.hw_config2 =
8033             SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8034
8035         sc->link_params.hw_led_mode =
8036             ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8037              SHARED_HW_CFG_LED_MODE_SHIFT);
8038
8039         /* get the port feature config */
8040         sc->port.config =
8041             SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8042
8043         /* get the link params */
8044         sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8045             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8046             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8047         sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8048             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8049             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8050
8051         /* get the lane config */
8052         sc->link_params.lane_config =
8053             SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8054
8055         /* get the link config */
8056         val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8057         sc->port.link_config[ELINK_INT_PHY] = val;
8058         sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8059         sc->port.link_config[ELINK_EXT_PHY1] =
8060             SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8061
8062         /* get the override preemphasis flag and enable it or turn it off */
8063         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8064         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8065                 sc->link_params.feature_config_flags |=
8066                     ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8067         } else {
8068                 sc->link_params.feature_config_flags &=
8069                     ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8070         }
8071
8072         /* get the initial value of the link params */
8073         sc->link_params.multi_phy_config =
8074             SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8075
8076         /* get external phy info */
8077         sc->port.ext_phy_config =
8078             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8079
8080         /* get the multifunction configuration */
8081         bnx2x_get_mf_cfg_info(sc);
8082
8083         /* get the mac address */
8084         if (IS_MF(sc)) {
8085                 mac_hi =
8086                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8087                 mac_lo =
8088                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8089         } else {
8090                 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8091                 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8092         }
8093
8094         if ((mac_lo == 0) && (mac_hi == 0)) {
8095                 *sc->mac_addr_str = 0;
8096                 PMD_DRV_LOG(NOTICE, "No Ethernet address programmed!");
8097         } else {
8098                 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8099                 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8100                 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8101                 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8102                 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8103                 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8104                 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8105                          "%02x:%02x:%02x:%02x:%02x:%02x",
8106                          sc->link_params.mac_addr[0],
8107                          sc->link_params.mac_addr[1],
8108                          sc->link_params.mac_addr[2],
8109                          sc->link_params.mac_addr[3],
8110                          sc->link_params.mac_addr[4],
8111                          sc->link_params.mac_addr[5]);
8112                 PMD_DRV_LOG(DEBUG, "Ethernet address: %s", sc->mac_addr_str);
8113         }
8114
8115         return 0;
8116 }
8117
8118 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8119 {
8120         uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8121         switch (sc->link_params.phy[phy_idx].media_type) {
8122         case ELINK_ETH_PHY_SFPP_10G_FIBER:
8123         case ELINK_ETH_PHY_SFP_1G_FIBER:
8124         case ELINK_ETH_PHY_XFP_FIBER:
8125         case ELINK_ETH_PHY_KR:
8126         case ELINK_ETH_PHY_CX4:
8127                 PMD_DRV_LOG(INFO, "Found 10GBase-CX4 media.");
8128                 sc->media = IFM_10G_CX4;
8129                 break;
8130         case ELINK_ETH_PHY_DA_TWINAX:
8131                 PMD_DRV_LOG(INFO, "Found 10Gb Twinax media.");
8132                 sc->media = IFM_10G_TWINAX;
8133                 break;
8134         case ELINK_ETH_PHY_BASE_T:
8135                 PMD_DRV_LOG(INFO, "Found 10GBase-T media.");
8136                 sc->media = IFM_10G_T;
8137                 break;
8138         case ELINK_ETH_PHY_NOT_PRESENT:
8139                 PMD_DRV_LOG(INFO, "Media not present.");
8140                 sc->media = 0;
8141                 break;
8142         case ELINK_ETH_PHY_UNSPECIFIED:
8143         default:
8144                 PMD_DRV_LOG(INFO, "Unknown media!");
8145                 sc->media = 0;
8146                 break;
8147         }
8148 }
8149
8150 #define GET_FIELD(value, fname)                     \
8151 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8152 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8153 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8154
8155 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8156 {
8157         int pfid = SC_FUNC(sc);
8158         int igu_sb_id;
8159         uint32_t val;
8160         uint8_t fid, igu_sb_cnt = 0;
8161
8162         sc->igu_base_sb = 0xff;
8163
8164         if (CHIP_INT_MODE_IS_BC(sc)) {
8165                 int vn = SC_VN(sc);
8166                 igu_sb_cnt = sc->igu_sb_cnt;
8167                 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8168                                    FP_SB_MAX_E1x);
8169                 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8170                                   (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8171                 return 0;
8172         }
8173
8174         /* IGU in normal mode - read CAM */
8175         for (igu_sb_id = 0;
8176              igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8177                 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8178                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8179                         continue;
8180                 }
8181                 fid = IGU_FID(val);
8182                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8183                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8184                                 continue;
8185                         }
8186                         if (IGU_VEC(val) == 0) {
8187                                 /* default status block */
8188                                 sc->igu_dsb_id = igu_sb_id;
8189                         } else {
8190                                 if (sc->igu_base_sb == 0xff) {
8191                                         sc->igu_base_sb = igu_sb_id;
8192                                 }
8193                                 igu_sb_cnt++;
8194                         }
8195                 }
8196         }
8197
8198         /*
8199          * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8200          * that number of CAM entries will not be equal to the value advertised in
8201          * PCI. Driver should use the minimal value of both as the actual status
8202          * block count
8203          */
8204         sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8205
8206         if (igu_sb_cnt == 0) {
8207                 PMD_DRV_LOG(ERR, "CAM configuration error");
8208                 return -1;
8209         }
8210
8211         return 0;
8212 }
8213
8214 /*
8215 * Gather various information from the device config space, the device itself,
8216 * shmem, and the user input.
8217 */
8218 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8219 {
8220         uint32_t val;
8221         int rc;
8222
8223         /* get the chip revision (chip metal comes from pci config space) */
8224         sc->devinfo.chip_id = sc->link_params.chip_id =
8225             (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8226              ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8227              (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8228              ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8229
8230         /* force 57811 according to MISC register */
8231         if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8232                 if (CHIP_IS_57810(sc)) {
8233                         sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8234                                                (sc->
8235                                                 devinfo.chip_id & 0x0000ffff));
8236                 } else if (CHIP_IS_57810_MF(sc)) {
8237                         sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8238                                                (sc->
8239                                                 devinfo.chip_id & 0x0000ffff));
8240                 }
8241                 sc->devinfo.chip_id |= 0x1;
8242         }
8243
8244         PMD_DRV_LOG(DEBUG,
8245                     "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8246                     sc->devinfo.chip_id,
8247                     ((sc->devinfo.chip_id >> 16) & 0xffff),
8248                     ((sc->devinfo.chip_id >> 12) & 0xf),
8249                     ((sc->devinfo.chip_id >> 4) & 0xff),
8250                     ((sc->devinfo.chip_id >> 0) & 0xf));
8251
8252         val = (REG_RD(sc, 0x2874) & 0x55);
8253         if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8254                 sc->flags |= BNX2X_ONE_PORT_FLAG;
8255                 PMD_DRV_LOG(DEBUG, "single port device");
8256         }
8257
8258         /* set the doorbell size */
8259         sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8260
8261         /* determine whether the device is in 2 port or 4 port mode */
8262         sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE;       /* E1h */
8263         if (CHIP_IS_E2E3(sc)) {
8264 /*
8265  * Read port4mode_en_ovwr[0]:
8266  *   If 1, four port mode is in port4mode_en_ovwr[1].
8267  *   If 0, four port mode is in port4mode_en[0].
8268  */
8269                 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8270                 if (val & 1) {
8271                         val = ((val >> 1) & 1);
8272                 } else {
8273                         val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8274                 }
8275
8276                 sc->devinfo.chip_port_mode =
8277                     (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8278
8279                 PMD_DRV_LOG(DEBUG, "Port mode = %s", (val) ? "4" : "2");
8280         }
8281
8282         /* get the function and path info for the device */
8283         bnx2x_get_function_num(sc);
8284
8285         /* get the shared memory base address */
8286         sc->devinfo.shmem_base =
8287             sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8288         sc->devinfo.shmem2_base =
8289             REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8290                         MISC_REG_GENERIC_CR_0));
8291
8292         if (!sc->devinfo.shmem_base) {
8293 /* this should ONLY prevent upcoming shmem reads */
8294                 PMD_DRV_LOG(INFO, "MCP not active");
8295                 sc->flags |= BNX2X_NO_MCP_FLAG;
8296                 return 0;
8297         }
8298
8299         /* make sure the shared memory contents are valid */
8300         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8301         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8302             (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8303                 PMD_DRV_LOG(NOTICE, "Invalid SHMEM validity signature: 0x%08x",
8304                             val);
8305                 return 0;
8306         }
8307
8308         /* get the bootcode version */
8309         sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8310         snprintf(sc->devinfo.bc_ver_str,
8311                  sizeof(sc->devinfo.bc_ver_str),
8312                  "%d.%d.%d",
8313                  ((sc->devinfo.bc_ver >> 24) & 0xff),
8314                  ((sc->devinfo.bc_ver >> 16) & 0xff),
8315                  ((sc->devinfo.bc_ver >> 8) & 0xff));
8316         PMD_DRV_LOG(INFO, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8317
8318         /* get the bootcode shmem address */
8319         sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8320
8321         /* clean indirect addresses as they're not used */
8322         pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8323         if (IS_PF(sc)) {
8324                 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8325                 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8326                 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8327                 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8328                 if (CHIP_IS_E1x(sc)) {
8329                         REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8330                         REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8331                         REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8332                         REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8333                 }
8334
8335 /*
8336  * Enable internal target-read (in case we are probed after PF
8337  * FLR). Must be done prior to any BAR read access. Only for
8338  * 57712 and up
8339  */
8340                 if (!CHIP_IS_E1x(sc)) {
8341                         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
8342                                1);
8343                 }
8344         }
8345
8346         /* get the nvram size */
8347         val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8348         sc->devinfo.flash_size =
8349             (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8350
8351         bnx2x_set_power_state(sc, PCI_PM_D0);
8352         /* get various configuration parameters from shmem */
8353         bnx2x_get_shmem_info(sc);
8354
8355         /* initialize IGU parameters */
8356         if (CHIP_IS_E1x(sc)) {
8357                 sc->devinfo.int_block = INT_BLOCK_HC;
8358                 sc->igu_dsb_id = DEF_SB_IGU_ID;
8359                 sc->igu_base_sb = 0;
8360         } else {
8361                 sc->devinfo.int_block = INT_BLOCK_IGU;
8362
8363 /* do not allow device reset during IGU info preocessing */
8364                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8365
8366                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8367
8368                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8369                         int tout = 5000;
8370
8371                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8372                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8373                         REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8374
8375                         while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8376                                 tout--;
8377                                 DELAY(1000);
8378                         }
8379
8380                         if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8381                                 PMD_DRV_LOG(NOTICE,
8382                                             "FORCING IGU Normal Mode failed!!!");
8383                                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8384                                 return -1;
8385                         }
8386                 }
8387
8388                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8389                         PMD_DRV_LOG(DEBUG, "IGU Backward Compatible Mode");
8390                         sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8391                 } else {
8392                         PMD_DRV_LOG(DEBUG, "IGU Normal Mode");
8393                 }
8394
8395                 rc = bnx2x_get_igu_cam_info(sc);
8396
8397                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8398
8399                 if (rc) {
8400                         return rc;
8401                 }
8402         }
8403
8404         /*
8405          * Get base FW non-default (fast path) status block ID. This value is
8406          * used to initialize the fw_sb_id saved on the fp/queue structure to
8407          * determine the id used by the FW.
8408          */
8409         if (CHIP_IS_E1x(sc)) {
8410                 sc->base_fw_ndsb =
8411                     ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8412         } else {
8413 /*
8414  * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8415  * the same queue are indicated on the same IGU SB). So we prefer
8416  * FW and IGU SBs to be the same value.
8417  */
8418                 sc->base_fw_ndsb = sc->igu_base_sb;
8419         }
8420
8421         elink_phy_probe(&sc->link_params);
8422
8423         return 0;
8424 }
8425
8426 static void
8427 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8428 {
8429         uint32_t cfg_size = 0;
8430         uint32_t idx;
8431         uint8_t port = SC_PORT(sc);
8432
8433         /* aggregation of supported attributes of all external phys */
8434         sc->port.supported[0] = 0;
8435         sc->port.supported[1] = 0;
8436
8437         switch (sc->link_params.num_phys) {
8438         case 1:
8439                 sc->port.supported[0] =
8440                     sc->link_params.phy[ELINK_INT_PHY].supported;
8441                 cfg_size = 1;
8442                 break;
8443         case 2:
8444                 sc->port.supported[0] =
8445                     sc->link_params.phy[ELINK_EXT_PHY1].supported;
8446                 cfg_size = 1;
8447                 break;
8448         case 3:
8449                 if (sc->link_params.multi_phy_config &
8450                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8451                         sc->port.supported[1] =
8452                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8453                         sc->port.supported[0] =
8454                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8455                 } else {
8456                         sc->port.supported[0] =
8457                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8458                         sc->port.supported[1] =
8459                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8460                 }
8461                 cfg_size = 2;
8462                 break;
8463         }
8464
8465         if (!(sc->port.supported[0] || sc->port.supported[1])) {
8466                 PMD_DRV_LOG(ERR,
8467                             "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8468                             SHMEM_RD(sc,
8469                                      dev_info.port_hw_config
8470                                      [port].external_phy_config),
8471                             SHMEM_RD(sc,
8472                                      dev_info.port_hw_config
8473                                      [port].external_phy_config2));
8474                 return;
8475         }
8476
8477         if (CHIP_IS_E3(sc))
8478                 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8479         else {
8480                 switch (switch_cfg) {
8481                 case ELINK_SWITCH_CFG_1G:
8482                         sc->port.phy_addr =
8483                             REG_RD(sc,
8484                                    NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8485                         break;
8486                 case ELINK_SWITCH_CFG_10G:
8487                         sc->port.phy_addr =
8488                             REG_RD(sc,
8489                                    NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8490                         break;
8491                 default:
8492                         PMD_DRV_LOG(ERR,
8493                                     "Invalid switch config in"
8494                                     "link_config=0x%08x",
8495                                     sc->port.link_config[0]);
8496                         return;
8497                 }
8498         }
8499
8500         PMD_DRV_LOG(INFO, "PHY addr 0x%08x", sc->port.phy_addr);
8501
8502         /* mask what we support according to speed_cap_mask per configuration */
8503         for (idx = 0; idx < cfg_size; idx++) {
8504                 if (!(sc->link_params.speed_cap_mask[idx] &
8505                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8506                         sc->port.supported[idx] &=
8507                             ~ELINK_SUPPORTED_10baseT_Half;
8508                 }
8509
8510                 if (!(sc->link_params.speed_cap_mask[idx] &
8511                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8512                         sc->port.supported[idx] &=
8513                             ~ELINK_SUPPORTED_10baseT_Full;
8514                 }
8515
8516                 if (!(sc->link_params.speed_cap_mask[idx] &
8517                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8518                         sc->port.supported[idx] &=
8519                             ~ELINK_SUPPORTED_100baseT_Half;
8520                 }
8521
8522                 if (!(sc->link_params.speed_cap_mask[idx] &
8523                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8524                         sc->port.supported[idx] &=
8525                             ~ELINK_SUPPORTED_100baseT_Full;
8526                 }
8527
8528                 if (!(sc->link_params.speed_cap_mask[idx] &
8529                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8530                         sc->port.supported[idx] &=
8531                             ~ELINK_SUPPORTED_1000baseT_Full;
8532                 }
8533
8534                 if (!(sc->link_params.speed_cap_mask[idx] &
8535                       PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8536                         sc->port.supported[idx] &=
8537                             ~ELINK_SUPPORTED_2500baseX_Full;
8538                 }
8539
8540                 if (!(sc->link_params.speed_cap_mask[idx] &
8541                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8542                         sc->port.supported[idx] &=
8543                             ~ELINK_SUPPORTED_10000baseT_Full;
8544                 }
8545
8546                 if (!(sc->link_params.speed_cap_mask[idx] &
8547                       PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8548                         sc->port.supported[idx] &=
8549                             ~ELINK_SUPPORTED_20000baseKR2_Full;
8550                 }
8551         }
8552
8553         PMD_DRV_LOG(INFO, "PHY supported 0=0x%08x 1=0x%08x",
8554                     sc->port.supported[0], sc->port.supported[1]);
8555 }
8556
8557 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8558 {
8559         uint32_t link_config;
8560         uint32_t idx;
8561         uint32_t cfg_size = 0;
8562
8563         sc->port.advertising[0] = 0;
8564         sc->port.advertising[1] = 0;
8565
8566         switch (sc->link_params.num_phys) {
8567         case 1:
8568         case 2:
8569                 cfg_size = 1;
8570                 break;
8571         case 3:
8572                 cfg_size = 2;
8573                 break;
8574         }
8575
8576         for (idx = 0; idx < cfg_size; idx++) {
8577                 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8578                 link_config = sc->port.link_config[idx];
8579
8580                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8581                 case PORT_FEATURE_LINK_SPEED_AUTO:
8582                         if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8583                                 sc->link_params.req_line_speed[idx] =
8584                                     ELINK_SPEED_AUTO_NEG;
8585                                 sc->port.advertising[idx] |=
8586                                     sc->port.supported[idx];
8587                                 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8588                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8589                                         sc->port.advertising[idx] |=
8590                                             (ELINK_SUPPORTED_100baseT_Half |
8591                                              ELINK_SUPPORTED_100baseT_Full);
8592                         } else {
8593                                 /* force 10G, no AN */
8594                                 sc->link_params.req_line_speed[idx] =
8595                                     ELINK_SPEED_10000;
8596                                 sc->port.advertising[idx] |=
8597                                     (ADVERTISED_10000baseT_Full |
8598                                      ADVERTISED_FIBRE);
8599                                 continue;
8600                         }
8601                         break;
8602
8603                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8604                         if (sc->
8605                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8606                         {
8607                                 sc->link_params.req_line_speed[idx] =
8608                                     ELINK_SPEED_10;
8609                                 sc->port.advertising[idx] |=
8610                                     (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8611                         } else {
8612                                 PMD_DRV_LOG(ERR,
8613                                             "Invalid NVRAM config link_config=0x%08x "
8614                                             "speed_cap_mask=0x%08x",
8615                                             link_config,
8616                                             sc->
8617                                             link_params.speed_cap_mask[idx]);
8618                                 return;
8619                         }
8620                         break;
8621
8622                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8623                         if (sc->
8624                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8625                         {
8626                                 sc->link_params.req_line_speed[idx] =
8627                                     ELINK_SPEED_10;
8628                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8629                                 sc->port.advertising[idx] |=
8630                                     (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8631                         } else {
8632                                 PMD_DRV_LOG(ERR,
8633                                             "Invalid NVRAM config link_config=0x%08x "
8634                                             "speed_cap_mask=0x%08x",
8635                                             link_config,
8636                                             sc->
8637                                             link_params.speed_cap_mask[idx]);
8638                                 return;
8639                         }
8640                         break;
8641
8642                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8643                         if (sc->
8644                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8645                         {
8646                                 sc->link_params.req_line_speed[idx] =
8647                                     ELINK_SPEED_100;
8648                                 sc->port.advertising[idx] |=
8649                                     (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8650                         } else {
8651                                 PMD_DRV_LOG(ERR,
8652                                             "Invalid NVRAM config link_config=0x%08x "
8653                                             "speed_cap_mask=0x%08x",
8654                                             link_config,
8655                                             sc->
8656                                             link_params.speed_cap_mask[idx]);
8657                                 return;
8658                         }
8659                         break;
8660
8661                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8662                         if (sc->
8663                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8664                         {
8665                                 sc->link_params.req_line_speed[idx] =
8666                                     ELINK_SPEED_100;
8667                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8668                                 sc->port.advertising[idx] |=
8669                                     (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8670                         } else {
8671                                 PMD_DRV_LOG(ERR,
8672                                             "Invalid NVRAM config link_config=0x%08x "
8673                                             "speed_cap_mask=0x%08x",
8674                                             link_config,
8675                                             sc->
8676                                             link_params.speed_cap_mask[idx]);
8677                                 return;
8678                         }
8679                         break;
8680
8681                 case PORT_FEATURE_LINK_SPEED_1G:
8682                         if (sc->port.supported[idx] &
8683                             ELINK_SUPPORTED_1000baseT_Full) {
8684                                 sc->link_params.req_line_speed[idx] =
8685                                     ELINK_SPEED_1000;
8686                                 sc->port.advertising[idx] |=
8687                                     (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8688                         } else {
8689                                 PMD_DRV_LOG(ERR,
8690                                             "Invalid NVRAM config link_config=0x%08x "
8691                                             "speed_cap_mask=0x%08x",
8692                                             link_config,
8693                                             sc->
8694                                             link_params.speed_cap_mask[idx]);
8695                                 return;
8696                         }
8697                         break;
8698
8699                 case PORT_FEATURE_LINK_SPEED_2_5G:
8700                         if (sc->port.supported[idx] &
8701                             ELINK_SUPPORTED_2500baseX_Full) {
8702                                 sc->link_params.req_line_speed[idx] =
8703                                     ELINK_SPEED_2500;
8704                                 sc->port.advertising[idx] |=
8705                                     (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8706                         } else {
8707                                 PMD_DRV_LOG(ERR,
8708                                             "Invalid NVRAM config link_config=0x%08x "
8709                                             "speed_cap_mask=0x%08x",
8710                                             link_config,
8711                                             sc->
8712                                             link_params.speed_cap_mask[idx]);
8713                                 return;
8714                         }
8715                         break;
8716
8717                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8718                         if (sc->port.supported[idx] &
8719                             ELINK_SUPPORTED_10000baseT_Full) {
8720                                 sc->link_params.req_line_speed[idx] =
8721                                     ELINK_SPEED_10000;
8722                                 sc->port.advertising[idx] |=
8723                                     (ADVERTISED_10000baseT_Full |
8724                                      ADVERTISED_FIBRE);
8725                         } else {
8726                                 PMD_DRV_LOG(ERR,
8727                                             "Invalid NVRAM config link_config=0x%08x "
8728                                             "speed_cap_mask=0x%08x",
8729                                             link_config,
8730                                             sc->
8731                                             link_params.speed_cap_mask[idx]);
8732                                 return;
8733                         }
8734                         break;
8735
8736                 case PORT_FEATURE_LINK_SPEED_20G:
8737                         sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8738                         break;
8739
8740                 default:
8741                         PMD_DRV_LOG(ERR,
8742                                     "Invalid NVRAM config link_config=0x%08x "
8743                                     "speed_cap_mask=0x%08x", link_config,
8744                                     sc->link_params.speed_cap_mask[idx]);
8745                         sc->link_params.req_line_speed[idx] =
8746                             ELINK_SPEED_AUTO_NEG;
8747                         sc->port.advertising[idx] = sc->port.supported[idx];
8748                         break;
8749                 }
8750
8751                 sc->link_params.req_flow_ctrl[idx] =
8752                     (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8753
8754                 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8755                         if (!
8756                             (sc->
8757                              port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8758                                 sc->link_params.req_flow_ctrl[idx] =
8759                                     ELINK_FLOW_CTRL_NONE;
8760                         } else {
8761                                 bnx2x_set_requested_fc(sc);
8762                         }
8763                 }
8764         }
8765 }
8766
8767 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8768 {
8769         uint8_t port = SC_PORT(sc);
8770         uint32_t eee_mode;
8771
8772         PMD_INIT_FUNC_TRACE();
8773
8774         /* shmem data already read in bnx2x_get_shmem_info() */
8775
8776         bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8777         bnx2x_link_settings_requested(sc);
8778
8779         /* configure link feature according to nvram value */
8780         eee_mode =
8781             (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8782               & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8783              PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8784         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8785                 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8786                                             ELINK_EEE_MODE_ENABLE_LPI |
8787                                             ELINK_EEE_MODE_OUTPUT_TIME);
8788         } else {
8789                 sc->link_params.eee_mode = 0;
8790         }
8791
8792         /* get the media type */
8793         bnx2x_media_detect(sc);
8794 }
8795
8796 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8797 {
8798         uint32_t flags = MODE_ASIC | MODE_PORT2;
8799
8800         if (CHIP_IS_E2(sc)) {
8801                 flags |= MODE_E2;
8802         } else if (CHIP_IS_E3(sc)) {
8803                 flags |= MODE_E3;
8804                 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8805                         flags |= MODE_E3_A0;
8806                 } else {        /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8807
8808                         flags |= MODE_E3_B0 | MODE_COS3;
8809                 }
8810         }
8811
8812         if (IS_MF(sc)) {
8813                 flags |= MODE_MF;
8814                 switch (sc->devinfo.mf_info.mf_mode) {
8815                 case MULTI_FUNCTION_SD:
8816                         flags |= MODE_MF_SD;
8817                         break;
8818                 case MULTI_FUNCTION_SI:
8819                         flags |= MODE_MF_SI;
8820                         break;
8821                 case MULTI_FUNCTION_AFEX:
8822                         flags |= MODE_MF_AFEX;
8823                         break;
8824                 }
8825         } else {
8826                 flags |= MODE_SF;
8827         }
8828
8829 #if defined(__LITTLE_ENDIAN)
8830         flags |= MODE_LITTLE_ENDIAN;
8831 #else /* __BIG_ENDIAN */
8832         flags |= MODE_BIG_ENDIAN;
8833 #endif
8834
8835         INIT_MODE_FLAGS(sc) = flags;
8836 }
8837
8838 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8839 {
8840         struct bnx2x_fastpath *fp;
8841         char buf[32];
8842         uint32_t i;
8843
8844         if (IS_PF(sc)) {
8845 /************************/
8846 /* DEFAULT STATUS BLOCK */
8847 /************************/
8848
8849                 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8850                                   &sc->def_sb_dma, "def_sb",
8851                                   RTE_CACHE_LINE_SIZE) != 0) {
8852                         return -1;
8853                 }
8854
8855                 sc->def_sb =
8856                     (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8857 /***************/
8858 /* EVENT QUEUE */
8859 /***************/
8860
8861                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8862                                   &sc->eq_dma, "ev_queue",
8863                                   RTE_CACHE_LINE_SIZE) != 0) {
8864                         sc->def_sb = NULL;
8865                         return -1;
8866                 }
8867
8868                 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8869
8870 /*************/
8871 /* SLOW PATH */
8872 /*************/
8873
8874                 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8875                                   &sc->sp_dma, "sp",
8876                                   RTE_CACHE_LINE_SIZE) != 0) {
8877                         sc->eq = NULL;
8878                         sc->def_sb = NULL;
8879                         return -1;
8880                 }
8881
8882                 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8883
8884 /*******************/
8885 /* SLOW PATH QUEUE */
8886 /*******************/
8887
8888                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8889                                   &sc->spq_dma, "sp_queue",
8890                                   RTE_CACHE_LINE_SIZE) != 0) {
8891                         sc->sp = NULL;
8892                         sc->eq = NULL;
8893                         sc->def_sb = NULL;
8894                         return -1;
8895                 }
8896
8897                 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8898
8899 /***************************/
8900 /* FW DECOMPRESSION BUFFER */
8901 /***************************/
8902
8903                 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8904                                   "fw_dec_buf", RTE_CACHE_LINE_SIZE) != 0) {
8905                         sc->spq = NULL;
8906                         sc->sp = NULL;
8907                         sc->eq = NULL;
8908                         sc->def_sb = NULL;
8909                         return -1;
8910                 }
8911
8912                 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8913         }
8914
8915         /*************/
8916         /* FASTPATHS */
8917         /*************/
8918
8919         /* allocate DMA memory for each fastpath structure */
8920         for (i = 0; i < sc->num_queues; i++) {
8921                 fp = &sc->fp[i];
8922                 fp->sc = sc;
8923                 fp->index = i;
8924
8925 /*******************/
8926 /* FP STATUS BLOCK */
8927 /*******************/
8928
8929                 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8930                 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8931                                   &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8932                         PMD_DRV_LOG(NOTICE, "Failed to alloc %s", buf);
8933                         return -1;
8934                 } else {
8935                         if (CHIP_IS_E2E3(sc)) {
8936                                 fp->status_block.e2_sb =
8937                                     (struct host_hc_status_block_e2 *)
8938                                     fp->sb_dma.vaddr;
8939                         } else {
8940                                 fp->status_block.e1x_sb =
8941                                     (struct host_hc_status_block_e1x *)
8942                                     fp->sb_dma.vaddr;
8943                         }
8944                 }
8945         }
8946
8947         return 0;
8948 }
8949
8950 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8951 {
8952         struct bnx2x_fastpath *fp;
8953         int i;
8954
8955         for (i = 0; i < sc->num_queues; i++) {
8956                 fp = &sc->fp[i];
8957
8958 /*******************/
8959 /* FP STATUS BLOCK */
8960 /*******************/
8961
8962                 memset(&fp->status_block, 0, sizeof(fp->status_block));
8963         }
8964
8965         /***************************/
8966         /* FW DECOMPRESSION BUFFER */
8967         /***************************/
8968
8969         sc->gz_buf = NULL;
8970
8971         /*******************/
8972         /* SLOW PATH QUEUE */
8973         /*******************/
8974
8975         sc->spq = NULL;
8976
8977         /*************/
8978         /* SLOW PATH */
8979         /*************/
8980
8981         sc->sp = NULL;
8982
8983         /***************/
8984         /* EVENT QUEUE */
8985         /***************/
8986
8987         sc->eq = NULL;
8988
8989         /************************/
8990         /* DEFAULT STATUS BLOCK */
8991         /************************/
8992
8993         sc->def_sb = NULL;
8994
8995 }
8996
8997 /*
8998 * Previous driver DMAE transaction may have occurred when pre-boot stage
8999 * ended and boot began. This would invalidate the addresses of the
9000 * transaction, resulting in was-error bit set in the PCI causing all
9001 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
9002 * the interrupt which detected this from the pglueb and the was-done bit
9003 */
9004 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
9005 {
9006         uint32_t val;
9007
9008         if (!CHIP_IS_E1x(sc)) {
9009                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
9010                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9011                         REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9012                                1 << SC_FUNC(sc));
9013                 }
9014         }
9015 }
9016
9017 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9018 {
9019         uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9020                                      DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9021         if (!rc) {
9022                 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9023                 return -1;
9024         }
9025
9026         return 0;
9027 }
9028
9029 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9030 {
9031         struct bnx2x_prev_list_node *tmp;
9032
9033         LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9034                 if ((sc->pcie_bus == tmp->bus) &&
9035                     (sc->pcie_device == tmp->slot) &&
9036                     (SC_PATH(sc) == tmp->path)) {
9037                         return tmp;
9038                 }
9039         }
9040
9041         return NULL;
9042 }
9043
9044 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9045 {
9046         struct bnx2x_prev_list_node *tmp;
9047         int rc = FALSE;
9048
9049         rte_spinlock_lock(&bnx2x_prev_mtx);
9050
9051         tmp = bnx2x_prev_path_get_entry(sc);
9052         if (tmp) {
9053                 if (tmp->aer) {
9054                         PMD_DRV_LOG(DEBUG,
9055                                     "Path %d/%d/%d was marked by AER",
9056                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9057                 } else {
9058                         rc = TRUE;
9059                         PMD_DRV_LOG(DEBUG,
9060                                     "Path %d/%d/%d was already cleaned from previous drivers",
9061                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9062                 }
9063         }
9064
9065         rte_spinlock_unlock(&bnx2x_prev_mtx);
9066
9067         return rc;
9068 }
9069
9070 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9071 {
9072         struct bnx2x_prev_list_node *tmp;
9073
9074         rte_spinlock_lock(&bnx2x_prev_mtx);
9075
9076         /* Check whether the entry for this path already exists */
9077         tmp = bnx2x_prev_path_get_entry(sc);
9078         if (tmp) {
9079                 if (!tmp->aer) {
9080                         PMD_DRV_LOG(DEBUG,
9081                                     "Re-marking AER in path %d/%d/%d",
9082                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9083                 } else {
9084                         PMD_DRV_LOG(DEBUG,
9085                                     "Removing AER indication from path %d/%d/%d",
9086                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9087                         tmp->aer = 0;
9088                 }
9089
9090                 rte_spinlock_unlock(&bnx2x_prev_mtx);
9091                 return 0;
9092         }
9093
9094         rte_spinlock_unlock(&bnx2x_prev_mtx);
9095
9096         /* Create an entry for this path and add it */
9097         tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9098                          RTE_CACHE_LINE_SIZE);
9099         if (!tmp) {
9100                 PMD_DRV_LOG(NOTICE, "Failed to allocate 'bnx2x_prev_list_node'");
9101                 return -1;
9102         }
9103
9104         tmp->bus = sc->pcie_bus;
9105         tmp->slot = sc->pcie_device;
9106         tmp->path = SC_PATH(sc);
9107         tmp->aer = 0;
9108         tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9109
9110         rte_spinlock_lock(&bnx2x_prev_mtx);
9111
9112         LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9113
9114         rte_spinlock_unlock(&bnx2x_prev_mtx);
9115
9116         return 0;
9117 }
9118
9119 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9120 {
9121         int i;
9122
9123         /* only E2 and onwards support FLR */
9124         if (CHIP_IS_E1x(sc)) {
9125                 PMD_DRV_LOG(WARNING, "FLR not supported in E1H");
9126                 return -1;
9127         }
9128
9129         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9130         if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9131                 PMD_DRV_LOG(WARNING,
9132                             "FLR not supported by BC_VER: 0x%08x",
9133                             sc->devinfo.bc_ver);
9134                 return -1;
9135         }
9136
9137         /* Wait for Transaction Pending bit clean */
9138         for (i = 0; i < 4; i++) {
9139                 if (i) {
9140                         DELAY(((1 << (i - 1)) * 100) * 1000);
9141                 }
9142
9143                 if (!bnx2x_is_pcie_pending(sc)) {
9144                         goto clear;
9145                 }
9146         }
9147
9148         PMD_DRV_LOG(NOTICE, "PCIE transaction is not cleared, "
9149                     "proceeding with reset anyway");
9150
9151 clear:
9152         bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9153
9154         return 0;
9155 }
9156
9157 struct bnx2x_mac_vals {
9158         uint32_t xmac_addr;
9159         uint32_t xmac_val;
9160         uint32_t emac_addr;
9161         uint32_t emac_val;
9162         uint32_t umac_addr;
9163         uint32_t umac_val;
9164         uint32_t bmac_addr;
9165         uint32_t bmac_val[2];
9166 };
9167
9168 static void
9169 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9170 {
9171         uint32_t val, base_addr, offset, mask, reset_reg;
9172         uint8_t mac_stopped = FALSE;
9173         uint8_t port = SC_PORT(sc);
9174         uint32_t wb_data[2];
9175
9176         /* reset addresses as they also mark which values were changed */
9177         vals->bmac_addr = 0;
9178         vals->umac_addr = 0;
9179         vals->xmac_addr = 0;
9180         vals->emac_addr = 0;
9181
9182         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9183
9184         if (!CHIP_IS_E3(sc)) {
9185                 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9186                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9187                 if ((mask & reset_reg) && val) {
9188                         base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9189                             : NIG_REG_INGRESS_BMAC0_MEM;
9190                         offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9191                             : BIGMAC_REGISTER_BMAC_CONTROL;
9192
9193                         /*
9194                          * use rd/wr since we cannot use dmae. This is safe
9195                          * since MCP won't access the bus due to the request
9196                          * to unload, and no function on the path can be
9197                          * loaded at this time.
9198                          */
9199                         wb_data[0] = REG_RD(sc, base_addr + offset);
9200                         wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9201                         vals->bmac_addr = base_addr + offset;
9202                         vals->bmac_val[0] = wb_data[0];
9203                         vals->bmac_val[1] = wb_data[1];
9204                         wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9205                         REG_WR(sc, vals->bmac_addr, wb_data[0]);
9206                         REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9207                 }
9208
9209                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9210                 vals->emac_val = REG_RD(sc, vals->emac_addr);
9211                 REG_WR(sc, vals->emac_addr, 0);
9212                 mac_stopped = TRUE;
9213         } else {
9214                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9215                         base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9216                         val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9217                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9218                                val & ~(1 << 1));
9219                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9220                                val | (1 << 1));
9221                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9222                         vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9223                         REG_WR(sc, vals->xmac_addr, 0);
9224                         mac_stopped = TRUE;
9225                 }
9226
9227                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9228                 if (mask & reset_reg) {
9229                         base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9230                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9231                         vals->umac_val = REG_RD(sc, vals->umac_addr);
9232                         REG_WR(sc, vals->umac_addr, 0);
9233                         mac_stopped = TRUE;
9234                 }
9235         }
9236
9237         if (mac_stopped) {
9238                 DELAY(20000);
9239         }
9240 }
9241
9242 #define BNX2X_PREV_UNDI_PROD_ADDR(p)  (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9243 #define BNX2X_PREV_UNDI_RCQ(val)      ((val) & 0xffff)
9244 #define BNX2X_PREV_UNDI_BD(val)       ((val) >> 16 & 0xffff)
9245 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9246
9247 static void
9248 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9249 {
9250         uint16_t rcq, bd;
9251         uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9252
9253         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9254         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9255
9256         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9257         REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9258 }
9259
9260 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9261 {
9262         uint32_t reset_reg, tmp_reg = 0, rc;
9263         uint8_t prev_undi = FALSE;
9264         struct bnx2x_mac_vals mac_vals;
9265         uint32_t timer_count = 1000;
9266         uint32_t prev_brb;
9267
9268         /*
9269          * It is possible a previous function received 'common' answer,
9270          * but hasn't loaded yet, therefore creating a scenario of
9271          * multiple functions receiving 'common' on the same path.
9272          */
9273         memset(&mac_vals, 0, sizeof(mac_vals));
9274
9275         if (bnx2x_prev_is_path_marked(sc)) {
9276                 return bnx2x_prev_mcp_done(sc);
9277         }
9278
9279         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9280
9281         /* Reset should be performed after BRB is emptied */
9282         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9283                 /* Close the MAC Rx to prevent BRB from filling up */
9284                 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9285
9286                 /* close LLH filters towards the BRB */
9287                 elink_set_rx_filter(&sc->link_params, 0);
9288
9289                 /*
9290                  * Check if the UNDI driver was previously loaded.
9291                  * UNDI driver initializes CID offset for normal bell to 0x7
9292                  */
9293                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9294                         tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9295                         if (tmp_reg == 0x7) {
9296                                 PMD_DRV_LOG(DEBUG, "UNDI previously loaded");
9297                                 prev_undi = TRUE;
9298                                 /* clear the UNDI indication */
9299                                 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9300                                 /* clear possible idle check errors */
9301                                 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9302                         }
9303                 }
9304
9305                 /* wait until BRB is empty */
9306                 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9307                 while (timer_count) {
9308                         prev_brb = tmp_reg;
9309
9310                         tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9311                         if (!tmp_reg) {
9312                                 break;
9313                         }
9314
9315                         PMD_DRV_LOG(DEBUG, "BRB still has 0x%08x", tmp_reg);
9316
9317                         /* reset timer as long as BRB actually gets emptied */
9318                         if (prev_brb > tmp_reg) {
9319                                 timer_count = 1000;
9320                         } else {
9321                                 timer_count--;
9322                         }
9323
9324                         /* If UNDI resides in memory, manually increment it */
9325                         if (prev_undi) {
9326                                 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9327                         }
9328
9329                         DELAY(10);
9330                 }
9331
9332                 if (!timer_count) {
9333                         PMD_DRV_LOG(NOTICE, "Failed to empty BRB");
9334                 }
9335         }
9336
9337         /* No packets are in the pipeline, path is ready for reset */
9338         bnx2x_reset_common(sc);
9339
9340         if (mac_vals.xmac_addr) {
9341                 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9342         }
9343         if (mac_vals.umac_addr) {
9344                 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9345         }
9346         if (mac_vals.emac_addr) {
9347                 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9348         }
9349         if (mac_vals.bmac_addr) {
9350                 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9351                 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9352         }
9353
9354         rc = bnx2x_prev_mark_path(sc, prev_undi);
9355         if (rc) {
9356                 bnx2x_prev_mcp_done(sc);
9357                 return rc;
9358         }
9359
9360         return bnx2x_prev_mcp_done(sc);
9361 }
9362
9363 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9364 {
9365         int rc;
9366
9367         /* Test if previous unload process was already finished for this path */
9368         if (bnx2x_prev_is_path_marked(sc)) {
9369                 return bnx2x_prev_mcp_done(sc);
9370         }
9371
9372         /*
9373          * If function has FLR capabilities, and existing FW version matches
9374          * the one required, then FLR will be sufficient to clean any residue
9375          * left by previous driver
9376          */
9377         rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9378         if (!rc) {
9379                 /* fw version is good */
9380                 rc = bnx2x_do_flr(sc);
9381         }
9382
9383         if (!rc) {
9384                 /* FLR was performed */
9385                 return 0;
9386         }
9387
9388         PMD_DRV_LOG(INFO, "Could not FLR");
9389
9390         /* Close the MCP request, return failure */
9391         rc = bnx2x_prev_mcp_done(sc);
9392         if (!rc) {
9393                 rc = BNX2X_PREV_WAIT_NEEDED;
9394         }
9395
9396         return rc;
9397 }
9398
9399 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9400 {
9401         int time_counter = 10;
9402         uint32_t fw, hw_lock_reg, hw_lock_val;
9403         uint32_t rc = 0;
9404
9405         /*
9406          * Clear HW from errors which may have resulted from an interrupted
9407          * DMAE transaction.
9408          */
9409         bnx2x_prev_interrupted_dmae(sc);
9410
9411         /* Release previously held locks */
9412         if (SC_FUNC(sc) <= 5)
9413                 hw_lock_reg = (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8);
9414         else
9415                 hw_lock_reg =
9416                     (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9417
9418         hw_lock_val = (REG_RD(sc, hw_lock_reg));
9419         if (hw_lock_val) {
9420                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9421                         REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9422                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9423                 }
9424                 REG_WR(sc, hw_lock_reg, 0xffffffff);
9425         }
9426
9427         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9428                 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9429         }
9430
9431         do {
9432                 /* Lock MCP using an unload request */
9433                 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9434                 if (!fw) {
9435                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9436                         rc = -1;
9437                         break;
9438                 }
9439
9440                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9441                         rc = bnx2x_prev_unload_common(sc);
9442                         break;
9443                 }
9444
9445                 /* non-common reply from MCP might require looping */
9446                 rc = bnx2x_prev_unload_uncommon(sc);
9447                 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9448                         break;
9449                 }
9450
9451                 DELAY(20000);
9452         } while (--time_counter);
9453
9454         if (!time_counter || rc) {
9455                 PMD_DRV_LOG(NOTICE, "Failed to unload previous driver!");
9456                 rc = -1;
9457         }
9458
9459         return rc;
9460 }
9461
9462 static void
9463 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9464 {
9465         if (!CHIP_IS_E1x(sc)) {
9466                 sc->dcb_state = dcb_on;
9467                 sc->dcbx_enabled = dcbx_enabled;
9468         } else {
9469                 sc->dcb_state = FALSE;
9470                 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9471         }
9472         PMD_DRV_LOG(DEBUG,
9473                     "DCB state [%s:%s]",
9474                     dcb_on ? "ON" : "OFF",
9475                     (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9476                     (dcbx_enabled ==
9477                      BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9478                     : (dcbx_enabled ==
9479                        BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9480                     "on-chip with negotiation" : "invalid");
9481 }
9482
9483 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9484 {
9485         int cid_count = BNX2X_L2_MAX_CID(sc);
9486
9487         if (CNIC_SUPPORT(sc)) {
9488                 cid_count += CNIC_CID_MAX;
9489         }
9490
9491         return roundup(cid_count, QM_CID_ROUND);
9492 }
9493
9494 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9495 {
9496         int pri, cos;
9497
9498         uint32_t pri_map = 0;
9499
9500         for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9501                 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9502                 if (cos < sc->max_cos) {
9503                         sc->prio_to_cos[pri] = cos;
9504                 } else {
9505                         PMD_DRV_LOG(WARNING,
9506                                     "Invalid COS %d for priority %d "
9507                                     "(max COS is %d), setting to 0", cos, pri,
9508                                     (sc->max_cos - 1));
9509                         sc->prio_to_cos[pri] = 0;
9510                 }
9511         }
9512 }
9513
9514 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9515 {
9516         struct {
9517                 uint8_t id;
9518                 uint8_t next;
9519         } pci_cap;
9520         uint16_t status;
9521         struct bnx2x_pci_cap *cap;
9522
9523         cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9524                                          RTE_CACHE_LINE_SIZE);
9525         if (!cap) {
9526                 PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9527                 return -ENOMEM;
9528         }
9529
9530         pci_read(sc, PCI_STATUS, &status, 2);
9531         if (!(status & PCI_STATUS_CAP_LIST)) {
9532                 PMD_DRV_LOG(NOTICE, "PCIe capability reading failed");
9533                 return -1;
9534         }
9535
9536         pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9537         while (pci_cap.next) {
9538                 cap->addr = pci_cap.next & ~3;
9539                 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9540                 if (pci_cap.id == 0xff)
9541                         break;
9542                 cap->id = pci_cap.id;
9543                 cap->type = BNX2X_PCI_CAP;
9544                 cap->next = rte_zmalloc("pci_cap",
9545                                         sizeof(struct bnx2x_pci_cap),
9546                                         RTE_CACHE_LINE_SIZE);
9547                 if (!cap->next) {
9548                         PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9549                         return -ENOMEM;
9550                 }
9551                 cap = cap->next;
9552         }
9553
9554         return 0;
9555 }
9556
9557 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9558 {
9559         sc->max_tx_queues = 128;
9560         sc->max_rx_queues = 128;
9561 }
9562
9563 #define FW_HEADER_LEN 104
9564 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9565 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9566
9567 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9568 {
9569         const char *fwname;
9570         int f;
9571         struct stat st;
9572
9573         fwname = sc->devinfo.device_id == BNX2X_DEV_ID_57711
9574                 ? FW_NAME_57711 : FW_NAME_57810;
9575         f = open(fwname, O_RDONLY);
9576         if (f < 0) {
9577                 PMD_DRV_LOG(NOTICE, "Can't open firmware file");
9578                 return;
9579         }
9580
9581         if (fstat(f, &st) < 0) {
9582                 PMD_DRV_LOG(NOTICE, "Can't stat firmware file");
9583                 close(f);
9584                 return;
9585         }
9586
9587         sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9588         if (!sc->firmware) {
9589                 PMD_DRV_LOG(NOTICE, "Can't allocate memory for firmware");
9590                 close(f);
9591                 return;
9592         }
9593
9594         if (read(f, sc->firmware, st.st_size) != st.st_size) {
9595                 PMD_DRV_LOG(NOTICE, "Can't read firmware data");
9596                 close(f);
9597                 return;
9598         }
9599         close(f);
9600
9601         sc->fw_len = st.st_size;
9602         if (sc->fw_len < FW_HEADER_LEN) {
9603                 PMD_DRV_LOG(NOTICE, "Invalid fw size: %" PRIu64, sc->fw_len);
9604                 return;
9605         }
9606         PMD_DRV_LOG(DEBUG, "fw_len = %" PRIu64, sc->fw_len);
9607 }
9608
9609 static void
9610 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9611 {
9612         uint32_t *src = (uint32_t *) data;
9613         uint32_t i, j, tmp;
9614
9615         for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9616                 tmp = rte_be_to_cpu_32(src[j]);
9617                 dst[i].op = (tmp >> 24) & 0xFF;
9618                 dst[i].offset = tmp & 0xFFFFFF;
9619                 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9620         }
9621 }
9622
9623 static void
9624 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9625 {
9626         uint16_t *src = (uint16_t *) data;
9627         uint32_t i;
9628
9629         for (i = 0; i < len / 2; ++i)
9630                 dst[i] = rte_be_to_cpu_16(src[i]);
9631 }
9632
9633 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9634 {
9635         uint32_t *src = (uint32_t *) data;
9636         uint32_t i;
9637
9638         for (i = 0; i < len / 4; ++i)
9639                 dst[i] = rte_be_to_cpu_32(src[i]);
9640 }
9641
9642 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9643 {
9644         uint32_t *src = (uint32_t *) data;
9645         uint32_t i, j, tmp;
9646
9647         for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9648                 dst[i].base = rte_be_to_cpu_32(src[j++]);
9649                 tmp = rte_be_to_cpu_32(src[j]);
9650                 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9651                 dst[i].m2 = tmp & 0xFFFF;
9652                 ++j;
9653                 tmp = rte_be_to_cpu_32(src[j]);
9654                 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9655                 dst[i].size = tmp & 0xFFFF;
9656         }
9657 }
9658
9659 /*
9660 * Device attach function.
9661 *
9662 * Allocates device resources, performs secondary chip identification, and
9663 * initializes driver instance variables. This function is called from driver
9664 * load after a successful probe.
9665 *
9666 * Returns:
9667 *   0 = Success, >0 = Failure
9668 */
9669 int bnx2x_attach(struct bnx2x_softc *sc)
9670 {
9671         int rc;
9672
9673         PMD_DRV_LOG(DEBUG, "Starting attach...");
9674
9675         rc = bnx2x_pci_get_caps(sc);
9676         if (rc) {
9677                 PMD_DRV_LOG(NOTICE, "PCIe caps reading was failed");
9678                 return rc;
9679         }
9680
9681         sc->state = BNX2X_STATE_CLOSED;
9682
9683         /* Init RTE stuff */
9684         bnx2x_init_rte(sc);
9685
9686         pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9687
9688         sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9689
9690         /* get PCI capabilites */
9691         bnx2x_probe_pci_caps(sc);
9692
9693         if (sc->devinfo.pcie_msix_cap_reg != 0) {
9694                 uint32_t val;
9695                 pci_read(sc,
9696                          (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9697                          2);
9698                 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE);
9699         } else {
9700                 sc->igu_sb_cnt = 1;
9701         }
9702
9703         if (IS_PF(sc)) {
9704 /* get device info and set params */
9705                 if (bnx2x_get_device_info(sc) != 0) {
9706                         PMD_DRV_LOG(NOTICE, "getting device info");
9707                         return -ENXIO;
9708                 }
9709
9710 /* get phy settings from shmem and 'and' against admin settings */
9711                 bnx2x_get_phy_info(sc);
9712         } else {
9713 /* Left mac of VF unfilled, PF should set it for VF */
9714                 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9715         }
9716
9717         sc->wol = 0;
9718
9719         /* set the default MTU (changed via ifconfig) */
9720         sc->mtu = ETHER_MTU;
9721
9722         bnx2x_set_modes_bitmap(sc);
9723
9724         /* need to reset chip if UNDI was active */
9725         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9726 /* init fw_seq */
9727                 sc->fw_seq =
9728                     (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9729                      DRV_MSG_SEQ_NUMBER_MASK);
9730                 bnx2x_prev_unload(sc);
9731         }
9732
9733         bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9734
9735         /* calculate qm_cid_count */
9736         sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9737
9738         sc->max_cos = 1;
9739         bnx2x_init_multi_cos(sc);
9740
9741         return 0;
9742 }
9743
9744 static void
9745 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9746                uint16_t index, uint8_t op, uint8_t update)
9747 {
9748         uint32_t igu_addr = sc->igu_base_addr;
9749         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9750         bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9751 }
9752
9753 static void
9754 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9755            uint16_t index, uint8_t op, uint8_t update)
9756 {
9757         if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9758                 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9759         else {
9760                 uint8_t segment;
9761                 if (CHIP_INT_MODE_IS_BC(sc)) {
9762                         segment = storm;
9763                 } else if (igu_sb_id != sc->igu_dsb_id) {
9764                         segment = IGU_SEG_ACCESS_DEF;
9765                 } else if (storm == ATTENTION_ID) {
9766                         segment = IGU_SEG_ACCESS_ATTN;
9767                 } else {
9768                         segment = IGU_SEG_ACCESS_DEF;
9769                 }
9770                 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9771         }
9772 }
9773
9774 static void
9775 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9776                      uint8_t is_pf)
9777 {
9778         uint32_t data, ctl, cnt = 100;
9779         uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9780         uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9781         uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9782             (idu_sb_id / 32) * 4;
9783         uint32_t sb_bit = 1 << (idu_sb_id % 32);
9784         uint32_t func_encode = func |
9785             (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9786         uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9787
9788         /* Not supported in BC mode */
9789         if (CHIP_INT_MODE_IS_BC(sc)) {
9790                 return;
9791         }
9792
9793         data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9794                  IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9795                 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9796
9797         ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9798                (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9799                (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9800
9801         REG_WR(sc, igu_addr_data, data);
9802
9803         mb();
9804
9805         PMD_DRV_LOG(DEBUG, "write 0x%08x to IGU(via GRC) addr 0x%x",
9806                     ctl, igu_addr_ctl);
9807         REG_WR(sc, igu_addr_ctl, ctl);
9808
9809         mb();
9810
9811         /* wait for clean up to finish */
9812         while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9813                 DELAY(20000);
9814         }
9815
9816         if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9817                 PMD_DRV_LOG(DEBUG,
9818                             "Unable to finish IGU cleanup: "
9819                             "idu_sb_id %d offset %d bit %d (cnt %d)",
9820                             idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9821         }
9822 }
9823
9824 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9825 {
9826         bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9827 }
9828
9829 /*******************/
9830 /* ECORE CALLBACKS */
9831 /*******************/
9832
9833 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9834 {
9835         uint32_t val = 0x1400;
9836
9837         PMD_INIT_FUNC_TRACE();
9838
9839         /* reset_common */
9840         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9841                0xd3ffff7f);
9842
9843         if (CHIP_IS_E3(sc)) {
9844                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9845                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9846         }
9847
9848         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9849 }
9850
9851 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9852 {
9853         uint32_t shmem_base[2];
9854         uint32_t shmem2_base[2];
9855
9856         /* Avoid common init in case MFW supports LFA */
9857         if (SHMEM2_RD(sc, size) >
9858             (uint32_t) offsetof(struct shmem2_region,
9859                                 lfa_host_addr[SC_PORT(sc)])) {
9860                 return;
9861         }
9862
9863         shmem_base[0] = sc->devinfo.shmem_base;
9864         shmem2_base[0] = sc->devinfo.shmem2_base;
9865
9866         if (!CHIP_IS_E1x(sc)) {
9867                 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9868                 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9869         }
9870
9871         elink_common_init_phy(sc, shmem_base, shmem2_base,
9872                               sc->devinfo.chip_id, 0);
9873 }
9874
9875 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9876 {
9877         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9878
9879         val &= ~IGU_PF_CONF_FUNC_EN;
9880
9881         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9882         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9883         REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9884 }
9885
9886 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9887 {
9888         uint16_t devctl;
9889         int r_order, w_order;
9890
9891         devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9892
9893         w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9894         r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9895
9896         ecore_init_pxp_arb(sc, r_order, w_order);
9897 }
9898
9899 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9900 {
9901         uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9902         uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9903         return (base + (SC_ABS_FUNC(sc)) * stride);
9904 }
9905
9906 /*
9907  * Called only on E1H or E2.
9908  * When pretending to be PF, the pretend value is the function number 0..7.
9909  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9910  * combination.
9911  */
9912 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9913 {
9914         uint32_t pretend_reg;
9915
9916         if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9917                 return -1;
9918
9919         /* get my own pretend register */
9920         pretend_reg = bnx2x_get_pretend_reg(sc);
9921         REG_WR(sc, pretend_reg, pretend_func_val);
9922         REG_RD(sc, pretend_reg);
9923         return 0;
9924 }
9925
9926 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9927 {
9928         int is_required;
9929         uint32_t val;
9930         int port;
9931
9932         is_required = 0;
9933         val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9934                SHARED_HW_CFG_FAN_FAILURE_MASK);
9935
9936         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9937                 is_required = 1;
9938         }
9939         /*
9940          * The fan failure mechanism is usually related to the PHY type since
9941          * the power consumption of the board is affected by the PHY. Currently,
9942          * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9943          */
9944         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9945                 for (port = PORT_0; port < PORT_MAX; port++) {
9946                         is_required |= elink_fan_failure_det_req(sc,
9947                                                                  sc->
9948                                                                  devinfo.shmem_base,
9949                                                                  sc->
9950                                                                  devinfo.shmem2_base,
9951                                                                  port);
9952                 }
9953         }
9954
9955         if (is_required == 0) {
9956                 return;
9957         }
9958
9959         /* Fan failure is indicated by SPIO 5 */
9960         bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9961
9962         /* set to active low mode */
9963         val = REG_RD(sc, MISC_REG_SPIO_INT);
9964         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
9965         REG_WR(sc, MISC_REG_SPIO_INT, val);
9966
9967         /* enable interrupt to signal the IGU */
9968         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
9969         val |= MISC_SPIO_SPIO5;
9970         REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
9971 }
9972
9973 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
9974 {
9975         uint32_t val;
9976
9977         REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
9978         if (!CHIP_IS_E1x(sc)) {
9979                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
9980         } else {
9981                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
9982         }
9983         REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
9984         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
9985         /*
9986          * mask read length error interrupts in brb for parser
9987          * (parsing unit and 'checksum and crc' unit)
9988          * these errors are legal (PU reads fixed length and CAC can cause
9989          * read length error on truncated packets)
9990          */
9991         REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
9992         REG_WR(sc, QM_REG_QM_INT_MASK, 0);
9993         REG_WR(sc, TM_REG_TM_INT_MASK, 0);
9994         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
9995         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
9996         REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
9997         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
9998         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
9999         REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
10000         REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10001         REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10002         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10003         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10004         REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10005         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10006         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10007         REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10008         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10009         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10010
10011         val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10012                PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10013                PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10014         if (!CHIP_IS_E1x(sc)) {
10015                 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10016                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10017         }
10018         REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10019
10020         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10021         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10022         REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10023         /*      REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10024
10025         if (!CHIP_IS_E1x(sc)) {
10026 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10027                 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10028         }
10029
10030         REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10031         REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10032         /*      REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10033         REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10034 }
10035
10036 /**
10037  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10038  *
10039  * @sc:     driver handle
10040  */
10041 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10042 {
10043         uint8_t abs_func_id;
10044         uint32_t val;
10045
10046         PMD_DRV_LOG(DEBUG, "starting common init for func %d", SC_ABS_FUNC(sc));
10047
10048         /*
10049          * take the RESET lock to protect undi_unload flow from accessing
10050          * registers while we are resetting the chip
10051          */
10052         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10053
10054         bnx2x_reset_common(sc);
10055
10056         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10057
10058         val = 0xfffc;
10059         if (CHIP_IS_E3(sc)) {
10060                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10061                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10062         }
10063
10064         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10065
10066         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10067
10068         ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10069
10070         if (!CHIP_IS_E1x(sc)) {
10071 /*
10072  * 4-port mode or 2-port mode we need to turn off master-enable for
10073  * everyone. After that we turn it back on for self. So, we disregard
10074  * multi-function, and always disable all functions on the given path,
10075  * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10076  */
10077                 for (abs_func_id = SC_PATH(sc);
10078                      abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10079                         if (abs_func_id == SC_ABS_FUNC(sc)) {
10080                                 REG_WR(sc,
10081                                        PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10082                                        1);
10083                                 continue;
10084                         }
10085
10086                         bnx2x_pretend_func(sc, abs_func_id);
10087
10088                         /* clear pf enable */
10089                         bnx2x_pf_disable(sc);
10090
10091                         bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10092                 }
10093         }
10094
10095         ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10096
10097         ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10098         bnx2x_init_pxp(sc);
10099
10100 #ifdef __BIG_ENDIAN
10101         REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10102         REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10103         REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10104         REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10105         REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10106         /* make sure this value is 0 */
10107         REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10108
10109         //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10110         REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10111         REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10112         REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10113         REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10114 #endif
10115
10116         ecore_ilt_init_page_size(sc, INITOP_SET);
10117
10118         if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10119                 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10120         }
10121
10122         /* let the HW do it's magic... */
10123         DELAY(100000);
10124
10125         /* finish PXP init */
10126
10127         val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10128         if (val != 1) {
10129                 PMD_DRV_LOG(NOTICE, "PXP2 CFG failed");
10130                 return -1;
10131         }
10132         val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10133         if (val != 1) {
10134                 PMD_DRV_LOG(NOTICE, "PXP2 RD_INIT failed");
10135                 return -1;
10136         }
10137
10138         /*
10139          * Timer bug workaround for E2 only. We need to set the entire ILT to have
10140          * entries with value "0" and valid bit on. This needs to be done by the
10141          * first PF that is loaded in a path (i.e. common phase)
10142          */
10143         if (!CHIP_IS_E1x(sc)) {
10144 /*
10145  * In E2 there is a bug in the timers block that can cause function 6 / 7
10146  * (i.e. vnic3) to start even if it is marked as "scan-off".
10147  * This occurs when a different function (func2,3) is being marked
10148  * as "scan-off". Real-life scenario for example: if a driver is being
10149  * load-unloaded while func6,7 are down. This will cause the timer to access
10150  * the ilt, translate to a logical address and send a request to read/write.
10151  * Since the ilt for the function that is down is not valid, this will cause
10152  * a translation error which is unrecoverable.
10153  * The Workaround is intended to make sure that when this happens nothing
10154  * fatal will occur. The workaround:
10155  *  1.  First PF driver which loads on a path will:
10156  *      a.  After taking the chip out of reset, by using pretend,
10157  *          it will write "0" to the following registers of
10158  *          the other vnics.
10159  *          REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10160  *          REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10161  *          REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10162  *          And for itself it will write '1' to
10163  *          PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10164  *          dmae-operations (writing to pram for example.)
10165  *          note: can be done for only function 6,7 but cleaner this
10166  *            way.
10167  *      b.  Write zero+valid to the entire ILT.
10168  *      c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
10169  *          VNIC3 (of that port). The range allocated will be the
10170  *          entire ILT. This is needed to prevent  ILT range error.
10171  *  2.  Any PF driver load flow:
10172  *      a.  ILT update with the physical addresses of the allocated
10173  *          logical pages.
10174  *      b.  Wait 20msec. - note that this timeout is needed to make
10175  *          sure there are no requests in one of the PXP internal
10176  *          queues with "old" ILT addresses.
10177  *      c.  PF enable in the PGLC.
10178  *      d.  Clear the was_error of the PF in the PGLC. (could have
10179  *          occurred while driver was down)
10180  *      e.  PF enable in the CFC (WEAK + STRONG)
10181  *      f.  Timers scan enable
10182  *  3.  PF driver unload flow:
10183  *      a.  Clear the Timers scan_en.
10184  *      b.  Polling for scan_on=0 for that PF.
10185  *      c.  Clear the PF enable bit in the PXP.
10186  *      d.  Clear the PF enable in the CFC (WEAK + STRONG)
10187  *      e.  Write zero+valid to all ILT entries (The valid bit must
10188  *          stay set)
10189  *      f.  If this is VNIC 3 of a port then also init
10190  *          first_timers_ilt_entry to zero and last_timers_ilt_entry
10191  *          to the last enrty in the ILT.
10192  *
10193  *      Notes:
10194  *      Currently the PF error in the PGLC is non recoverable.
10195  *      In the future the there will be a recovery routine for this error.
10196  *      Currently attention is masked.
10197  *      Having an MCP lock on the load/unload process does not guarantee that
10198  *      there is no Timer disable during Func6/7 enable. This is because the
10199  *      Timers scan is currently being cleared by the MCP on FLR.
10200  *      Step 2.d can be done only for PF6/7 and the driver can also check if
10201  *      there is error before clearing it. But the flow above is simpler and
10202  *      more general.
10203  *      All ILT entries are written by zero+valid and not just PF6/7
10204  *      ILT entries since in the future the ILT entries allocation for
10205  *      PF-s might be dynamic.
10206  */
10207                 struct ilt_client_info ilt_cli;
10208                 struct ecore_ilt ilt;
10209
10210                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10211                 memset(&ilt, 0, sizeof(struct ecore_ilt));
10212
10213 /* initialize dummy TM client */
10214                 ilt_cli.start = 0;
10215                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10216                 ilt_cli.client_num = ILT_CLIENT_TM;
10217
10218 /*
10219  * Step 1: set zeroes to all ilt page entries with valid bit on
10220  * Step 2: set the timers first/last ilt entry to point
10221  * to the entire range to prevent ILT range error for 3rd/4th
10222  * vnic (this code assumes existence of the vnic)
10223  *
10224  * both steps performed by call to ecore_ilt_client_init_op()
10225  * with dummy TM client
10226  *
10227  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10228  * and his brother are split registers
10229  */
10230
10231                 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10232                 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10233                 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10234
10235                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10236                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10237                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10238         }
10239
10240         REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10241         REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10242
10243         if (!CHIP_IS_E1x(sc)) {
10244                 int factor = 0;
10245
10246                 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10247                 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10248
10249 /* let the HW do it's magic... */
10250                 do {
10251                         DELAY(200000);
10252                         val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10253                 } while (factor-- && (val != 1));
10254
10255                 if (val != 1) {
10256                         PMD_DRV_LOG(NOTICE, "ATC_INIT failed");
10257                         return -1;
10258                 }
10259         }
10260
10261         ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10262
10263         /* clean the DMAE memory */
10264         sc->dmae_ready = 1;
10265         ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10266
10267         ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10268
10269         ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10270
10271         ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10272
10273         ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10274
10275         bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10276         bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10277         bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10278         bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10279
10280         ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10281
10282         /* QM queues pointers table */
10283         ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10284
10285         /* soft reset pulse */
10286         REG_WR(sc, QM_REG_SOFT_RESET, 1);
10287         REG_WR(sc, QM_REG_SOFT_RESET, 0);
10288
10289         if (CNIC_SUPPORT(sc))
10290                 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10291
10292         ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10293         REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10294
10295         if (!CHIP_REV_IS_SLOW(sc)) {
10296 /* enable hw interrupt from doorbell Q */
10297                 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10298         }
10299
10300         ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10301
10302         ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10303         REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10304         REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10305
10306         if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10307                 if (IS_MF_AFEX(sc)) {
10308                         /*
10309                          * configure that AFEX and VLAN headers must be
10310                          * received in AFEX mode
10311                          */
10312                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10313                         REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10314                         REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10315                         REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10316                         REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10317                 } else {
10318                         /*
10319                          * Bit-map indicating which L2 hdrs may appear
10320                          * after the basic Ethernet header
10321                          */
10322                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10323                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10324                 }
10325         }
10326
10327         ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10328         ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10329         ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10330         ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10331
10332         if (!CHIP_IS_E1x(sc)) {
10333 /* reset VFC memories */
10334                 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10335                        VFC_MEMORIES_RST_REG_CAM_RST |
10336                        VFC_MEMORIES_RST_REG_RAM_RST);
10337                 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10338                        VFC_MEMORIES_RST_REG_CAM_RST |
10339                        VFC_MEMORIES_RST_REG_RAM_RST);
10340
10341                 DELAY(20000);
10342         }
10343
10344         ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10345         ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10346         ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10347         ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10348
10349         /* sync semi rtc */
10350         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10351         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10352
10353         ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10354         ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10355         ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10356
10357         if (!CHIP_IS_E1x(sc)) {
10358                 if (IS_MF_AFEX(sc)) {
10359                         /*
10360                          * configure that AFEX and VLAN headers must be
10361                          * sent in AFEX mode
10362                          */
10363                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10364                         REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10365                         REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10366                         REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10367                         REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10368                 } else {
10369                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10370                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10371                 }
10372         }
10373
10374         REG_WR(sc, SRC_REG_SOFT_RST, 1);
10375
10376         ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10377
10378         if (CNIC_SUPPORT(sc)) {
10379                 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10380                 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10381                 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10382                 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10383                 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10384                 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10385                 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10386                 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10387                 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10388                 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10389         }
10390         REG_WR(sc, SRC_REG_SOFT_RST, 0);
10391
10392         if (sizeof(union cdu_context) != 1024) {
10393 /* we currently assume that a context is 1024 bytes */
10394                 PMD_DRV_LOG(NOTICE,
10395                             "please adjust the size of cdu_context(%ld)",
10396                             (long)sizeof(union cdu_context));
10397         }
10398
10399         ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10400         val = (4 << 24) + (0 << 12) + 1024;
10401         REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10402
10403         ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10404
10405         REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10406         /* enable context validation interrupt from CFC */
10407         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10408
10409         /* set the thresholds to prevent CFC/CDU race */
10410         REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10411         ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10412
10413         if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10414                 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10415         }
10416
10417         ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10418         ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10419
10420         /* Reset PCIE errors for debug */
10421         REG_WR(sc, 0x2814, 0xffffffff);
10422         REG_WR(sc, 0x3820, 0xffffffff);
10423
10424         if (!CHIP_IS_E1x(sc)) {
10425                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10426                        (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10427                         PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10428                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10429                        (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10430                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10431                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10432                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10433                        (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10434                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10435                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10436         }
10437
10438         ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10439
10440         /* in E3 this done in per-port section */
10441         if (!CHIP_IS_E3(sc))
10442                 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10443
10444         if (CHIP_IS_E1H(sc)) {
10445 /* not applicable for E2 (and above ...) */
10446                 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10447         }
10448
10449         if (CHIP_REV_IS_SLOW(sc)) {
10450                 DELAY(200000);
10451         }
10452
10453         /* finish CFC init */
10454         val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10455         if (val != 1) {
10456                 PMD_DRV_LOG(NOTICE, "CFC LL_INIT failed");
10457                 return -1;
10458         }
10459         val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10460         if (val != 1) {
10461                 PMD_DRV_LOG(NOTICE, "CFC AC_INIT failed");
10462                 return -1;
10463         }
10464         val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10465         if (val != 1) {
10466                 PMD_DRV_LOG(NOTICE, "CFC CAM_INIT failed");
10467                 return -1;
10468         }
10469         REG_WR(sc, CFC_REG_DEBUG0, 0);
10470
10471         bnx2x_setup_fan_failure_detection(sc);
10472
10473         /* clear PXP2 attentions */
10474         REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10475
10476         bnx2x_enable_blocks_attention(sc);
10477
10478         if (!CHIP_REV_IS_SLOW(sc)) {
10479                 ecore_enable_blocks_parity(sc);
10480         }
10481
10482         if (!BNX2X_NOMCP(sc)) {
10483                 if (CHIP_IS_E1x(sc)) {
10484                         bnx2x_common_init_phy(sc);
10485                 }
10486         }
10487
10488         return 0;
10489 }
10490
10491 /**
10492  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10493  *
10494  * @sc:     driver handle
10495  */
10496 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10497 {
10498         int rc = bnx2x_init_hw_common(sc);
10499
10500         if (rc) {
10501                 return rc;
10502         }
10503
10504         /* In E2 2-PORT mode, same ext phy is used for the two paths */
10505         if (!BNX2X_NOMCP(sc)) {
10506                 bnx2x_common_init_phy(sc);
10507         }
10508
10509         return 0;
10510 }
10511
10512 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10513 {
10514         int port = SC_PORT(sc);
10515         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10516         uint32_t low, high;
10517         uint32_t val;
10518
10519         PMD_DRV_LOG(DEBUG, "starting port init for port %d", port);
10520
10521         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10522
10523         ecore_init_block(sc, BLOCK_MISC, init_phase);
10524         ecore_init_block(sc, BLOCK_PXP, init_phase);
10525         ecore_init_block(sc, BLOCK_PXP2, init_phase);
10526
10527         /*
10528          * Timers bug workaround: disables the pf_master bit in pglue at
10529          * common phase, we need to enable it here before any dmae access are
10530          * attempted. Therefore we manually added the enable-master to the
10531          * port phase (it also happens in the function phase)
10532          */
10533         if (!CHIP_IS_E1x(sc)) {
10534                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10535         }
10536
10537         ecore_init_block(sc, BLOCK_ATC, init_phase);
10538         ecore_init_block(sc, BLOCK_DMAE, init_phase);
10539         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10540         ecore_init_block(sc, BLOCK_QM, init_phase);
10541
10542         ecore_init_block(sc, BLOCK_TCM, init_phase);
10543         ecore_init_block(sc, BLOCK_UCM, init_phase);
10544         ecore_init_block(sc, BLOCK_CCM, init_phase);
10545         ecore_init_block(sc, BLOCK_XCM, init_phase);
10546
10547         /* QM cid (connection) count */
10548         ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10549
10550         if (CNIC_SUPPORT(sc)) {
10551                 ecore_init_block(sc, BLOCK_TM, init_phase);
10552                 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10553                 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10554         }
10555
10556         ecore_init_block(sc, BLOCK_DORQ, init_phase);
10557
10558         ecore_init_block(sc, BLOCK_BRB1, init_phase);
10559
10560         if (CHIP_IS_E1H(sc)) {
10561                 if (IS_MF(sc)) {
10562                         low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10563                 } else if (sc->mtu > 4096) {
10564                         if (BNX2X_ONE_PORT(sc)) {
10565                                 low = 160;
10566                         } else {
10567                                 val = sc->mtu;
10568                                 /* (24*1024 + val*4)/256 */
10569                                 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10570                         }
10571                 } else {
10572                         low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10573                 }
10574                 high = (low + 56);      /* 14*1024/256 */
10575                 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10576                 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10577         }
10578
10579         if (CHIP_IS_MODE_4_PORT(sc)) {
10580                 REG_WR(sc, SC_PORT(sc) ?
10581                        BRB1_REG_MAC_GUARANTIED_1 :
10582                        BRB1_REG_MAC_GUARANTIED_0, 40);
10583         }
10584
10585         ecore_init_block(sc, BLOCK_PRS, init_phase);
10586         if (CHIP_IS_E3B0(sc)) {
10587                 if (IS_MF_AFEX(sc)) {
10588                         /* configure headers for AFEX mode */
10589                         if (SC_PORT(sc)) {
10590                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10591                                        0xE);
10592                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10593                                        0x6);
10594                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10595                         } else {
10596                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10597                                        0xE);
10598                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10599                                        0x6);
10600                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10601                         }
10602                 } else {
10603                         /* Ovlan exists only if we are in multi-function +
10604                          * switch-dependent mode, in switch-independent there
10605                          * is no ovlan headers
10606                          */
10607                         REG_WR(sc, SC_PORT(sc) ?
10608                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10609                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10610                                (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10611                 }
10612         }
10613
10614         ecore_init_block(sc, BLOCK_TSDM, init_phase);
10615         ecore_init_block(sc, BLOCK_CSDM, init_phase);
10616         ecore_init_block(sc, BLOCK_USDM, init_phase);
10617         ecore_init_block(sc, BLOCK_XSDM, init_phase);
10618
10619         ecore_init_block(sc, BLOCK_TSEM, init_phase);
10620         ecore_init_block(sc, BLOCK_USEM, init_phase);
10621         ecore_init_block(sc, BLOCK_CSEM, init_phase);
10622         ecore_init_block(sc, BLOCK_XSEM, init_phase);
10623
10624         ecore_init_block(sc, BLOCK_UPB, init_phase);
10625         ecore_init_block(sc, BLOCK_XPB, init_phase);
10626
10627         ecore_init_block(sc, BLOCK_PBF, init_phase);
10628
10629         if (CHIP_IS_E1x(sc)) {
10630 /* configure PBF to work without PAUSE mtu 9000 */
10631                 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10632
10633 /* update threshold */
10634                 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10635 /* update init credit */
10636                 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10637                        (9040 / 16) + 553 - 22);
10638
10639 /* probe changes */
10640                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10641                 DELAY(50);
10642                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10643         }
10644
10645         if (CNIC_SUPPORT(sc)) {
10646                 ecore_init_block(sc, BLOCK_SRC, init_phase);
10647         }
10648
10649         ecore_init_block(sc, BLOCK_CDU, init_phase);
10650         ecore_init_block(sc, BLOCK_CFC, init_phase);
10651         ecore_init_block(sc, BLOCK_HC, init_phase);
10652         ecore_init_block(sc, BLOCK_IGU, init_phase);
10653         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10654         /* init aeu_mask_attn_func_0/1:
10655          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10656          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10657          *             bits 4-7 are used for "per vn group attention" */
10658         val = IS_MF(sc) ? 0xF7 : 0x7;
10659         val |= 0x10;
10660         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10661
10662         ecore_init_block(sc, BLOCK_NIG, init_phase);
10663
10664         if (!CHIP_IS_E1x(sc)) {
10665 /* Bit-map indicating which L2 hdrs may appear after the
10666  * basic Ethernet header
10667  */
10668                 if (IS_MF_AFEX(sc)) {
10669                         REG_WR(sc, SC_PORT(sc) ?
10670                                NIG_REG_P1_HDRS_AFTER_BASIC :
10671                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10672                 } else {
10673                         REG_WR(sc, SC_PORT(sc) ?
10674                                NIG_REG_P1_HDRS_AFTER_BASIC :
10675                                NIG_REG_P0_HDRS_AFTER_BASIC,
10676                                IS_MF_SD(sc) ? 7 : 6);
10677                 }
10678
10679                 if (CHIP_IS_E3(sc)) {
10680                         REG_WR(sc, SC_PORT(sc) ?
10681                                NIG_REG_LLH1_MF_MODE :
10682                                NIG_REG_LLH_MF_MODE, IS_MF(sc));
10683                 }
10684         }
10685         if (!CHIP_IS_E3(sc)) {
10686                 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10687         }
10688
10689         /* 0x2 disable mf_ov, 0x1 enable */
10690         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10691                (IS_MF_SD(sc) ? 0x1 : 0x2));
10692
10693         if (!CHIP_IS_E1x(sc)) {
10694                 val = 0;
10695                 switch (sc->devinfo.mf_info.mf_mode) {
10696                 case MULTI_FUNCTION_SD:
10697                         val = 1;
10698                         break;
10699                 case MULTI_FUNCTION_SI:
10700                 case MULTI_FUNCTION_AFEX:
10701                         val = 2;
10702                         break;
10703                 }
10704
10705                 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10706                             NIG_REG_LLH0_CLS_TYPE), val);
10707         }
10708         REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10709         REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10710         REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10711
10712         /* If SPIO5 is set to generate interrupts, enable it for this port */
10713         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10714         if (val & MISC_SPIO_SPIO5) {
10715                 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10716                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10717                 val = REG_RD(sc, reg_addr);
10718                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10719                 REG_WR(sc, reg_addr, val);
10720         }
10721
10722         return 0;
10723 }
10724
10725 static uint32_t
10726 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10727                        uint32_t expected, uint32_t poll_count)
10728 {
10729         uint32_t cur_cnt = poll_count;
10730         uint32_t val;
10731
10732         while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10733                 DELAY(FLR_WAIT_INTERVAL);
10734         }
10735
10736         return val;
10737 }
10738
10739 static int
10740 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10741                               __rte_unused const char *msg, uint32_t poll_cnt)
10742 {
10743         uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10744
10745         if (val != 0) {
10746                 PMD_DRV_LOG(NOTICE, "%s usage count=%d", msg, val);
10747                 return -1;
10748         }
10749
10750         return 0;
10751 }
10752
10753 /* Common routines with VF FLR cleanup */
10754 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10755 {
10756         /* adjust polling timeout */
10757         if (CHIP_REV_IS_EMUL(sc)) {
10758                 return (FLR_POLL_CNT * 2000);
10759         }
10760
10761         if (CHIP_REV_IS_FPGA(sc)) {
10762                 return (FLR_POLL_CNT * 120);
10763         }
10764
10765         return FLR_POLL_CNT;
10766 }
10767
10768 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10769 {
10770         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10771         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10772                                           CFC_REG_NUM_LCIDS_INSIDE_PF,
10773                                           "CFC PF usage counter timed out",
10774                                           poll_cnt)) {
10775                 return -1;
10776         }
10777
10778         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10779         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10780                                           DORQ_REG_PF_USAGE_CNT,
10781                                           "DQ PF usage counter timed out",
10782                                           poll_cnt)) {
10783                 return -1;
10784         }
10785
10786         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10787         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10788                                           QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10789                                           "QM PF usage counter timed out",
10790                                           poll_cnt)) {
10791                 return -1;
10792         }
10793
10794         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10795         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10796                                           TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10797                                           "Timers VNIC usage counter timed out",
10798                                           poll_cnt)) {
10799                 return -1;
10800         }
10801
10802         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10803                                           TM_REG_LIN0_NUM_SCANS +
10804                                           4 * SC_PORT(sc),
10805                                           "Timers NUM_SCANS usage counter timed out",
10806                                           poll_cnt)) {
10807                 return -1;
10808         }
10809
10810         /* Wait DMAE PF usage counter to zero */
10811         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10812                                           dmae_reg_go_c[INIT_DMAE_C(sc)],
10813                                           "DMAE dommand register timed out",
10814                                           poll_cnt)) {
10815                 return -1;
10816         }
10817
10818         return 0;
10819 }
10820
10821 #define OP_GEN_PARAM(param)                                            \
10822         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10823 #define OP_GEN_TYPE(type)                                           \
10824         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10825 #define OP_GEN_AGG_VECT(index)                                             \
10826         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10827
10828 static int
10829 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10830                      uint32_t poll_cnt)
10831 {
10832         uint32_t op_gen_command = 0;
10833         uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10834                               CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10835         int ret = 0;
10836
10837         if (REG_RD(sc, comp_addr)) {
10838                 PMD_DRV_LOG(NOTICE,
10839                             "Cleanup complete was not 0 before sending");
10840                 return -1;
10841         }
10842
10843         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10844         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10845         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10846         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10847
10848         REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10849
10850         if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10851                 PMD_DRV_LOG(NOTICE, "FW final cleanup did not succeed");
10852                 PMD_DRV_LOG(DEBUG, "At timeout completion address contained %x",
10853                             (REG_RD(sc, comp_addr)));
10854                 rte_panic("FLR cleanup failed");
10855                 return -1;
10856         }
10857
10858         /* Zero completion for nxt FLR */
10859         REG_WR(sc, comp_addr, 0);
10860
10861         return ret;
10862 }
10863
10864 static void
10865 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10866                        uint32_t poll_count)
10867 {
10868         uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10869         uint32_t cur_cnt = poll_count;
10870
10871         crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10872         crd = crd_start = REG_RD(sc, regs->crd);
10873         init_crd = REG_RD(sc, regs->init_crd);
10874
10875         while ((crd != init_crd) &&
10876                ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10877                 (init_crd - crd_start))) {
10878                 if (cur_cnt--) {
10879                         DELAY(FLR_WAIT_INTERVAL);
10880                         crd = REG_RD(sc, regs->crd);
10881                         crd_freed = REG_RD(sc, regs->crd_freed);
10882                 } else {
10883                         break;
10884                 }
10885         }
10886 }
10887
10888 static void
10889 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10890                        uint32_t poll_count)
10891 {
10892         uint32_t occup, to_free, freed, freed_start;
10893         uint32_t cur_cnt = poll_count;
10894
10895         occup = to_free = REG_RD(sc, regs->lines_occup);
10896         freed = freed_start = REG_RD(sc, regs->lines_freed);
10897
10898         while (occup &&
10899                ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10900                 to_free)) {
10901                 if (cur_cnt--) {
10902                         DELAY(FLR_WAIT_INTERVAL);
10903                         occup = REG_RD(sc, regs->lines_occup);
10904                         freed = REG_RD(sc, regs->lines_freed);
10905                 } else {
10906                         break;
10907                 }
10908         }
10909 }
10910
10911 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10912 {
10913         struct pbf_pN_cmd_regs cmd_regs[] = {
10914                 {0, (CHIP_IS_E3B0(sc)) ?
10915                  PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10916                  (CHIP_IS_E3B0(sc)) ?
10917                  PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10918                 {1, (CHIP_IS_E3B0(sc)) ?
10919                  PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10920                  (CHIP_IS_E3B0(sc)) ?
10921                  PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10922                 {4, (CHIP_IS_E3B0(sc)) ?
10923                  PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10924                  (CHIP_IS_E3B0(sc)) ?
10925                  PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10926                  PBF_REG_P4_TQ_LINES_FREED_CNT}
10927         };
10928
10929         struct pbf_pN_buf_regs buf_regs[] = {
10930                 {0, (CHIP_IS_E3B0(sc)) ?
10931                  PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10932                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10933                  (CHIP_IS_E3B0(sc)) ?
10934                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10935                  PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10936                 {1, (CHIP_IS_E3B0(sc)) ?
10937                  PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10938                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10939                  (CHIP_IS_E3B0(sc)) ?
10940                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10941                  PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10942                 {4, (CHIP_IS_E3B0(sc)) ?
10943                  PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10944                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10945                  (CHIP_IS_E3B0(sc)) ?
10946                  PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10947                  PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10948         };
10949
10950         uint32_t i;
10951
10952         /* Verify the command queues are flushed P0, P1, P4 */
10953         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10954                 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10955         }
10956
10957         /* Verify the transmission buffers are flushed P0, P1, P4 */
10958         for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10959                 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
10960         }
10961 }
10962
10963 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
10964 {
10965         __rte_unused uint32_t val;
10966
10967         val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
10968         PMD_DRV_LOG(DEBUG, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
10969
10970         val = REG_RD(sc, PBF_REG_DISABLE_PF);
10971         PMD_DRV_LOG(DEBUG, "PBF_REG_DISABLE_PF is 0x%x", val);
10972
10973         val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
10974         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
10975
10976         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
10977         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
10978
10979         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
10980         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
10981
10982         val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
10983         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
10984
10985         val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
10986         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
10987
10988         val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
10989         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
10990                     val);
10991 }
10992
10993 /**
10994  *      bnx2x_pf_flr_clnup
10995  *      a. re-enable target read on the PF
10996  *      b. poll cfc per function usgae counter
10997  *      c. poll the qm perfunction usage counter
10998  *      d. poll the tm per function usage counter
10999  *      e. poll the tm per function scan-done indication
11000  *      f. clear the dmae channel associated wit hthe PF
11001  *      g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11002  *      h. call the common flr cleanup code with -1 (pf indication)
11003  */
11004 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11005 {
11006         uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11007
11008         /* Re-enable PF target read access */
11009         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11010
11011         /* Poll HW usage counters */
11012         if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11013                 return -1;
11014         }
11015
11016         /* Zero the igu 'trailing edge' and 'leading edge' */
11017
11018         /* Send the FW cleanup command */
11019         if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11020                 return -1;
11021         }
11022
11023         /* ATC cleanup */
11024
11025         /* Verify TX hw is flushed */
11026         bnx2x_tx_hw_flushed(sc, poll_cnt);
11027
11028         /* Wait 100ms (not adjusted according to platform) */
11029         DELAY(100000);
11030
11031         /* Verify no pending pci transactions */
11032         if (bnx2x_is_pcie_pending(sc)) {
11033                 PMD_DRV_LOG(NOTICE, "PCIE Transactions still pending");
11034         }
11035
11036         /* Debug */
11037         bnx2x_hw_enable_status(sc);
11038
11039         /*
11040          * Master enable - Due to WB DMAE writes performed before this
11041          * register is re-initialized as part of the regular function init
11042          */
11043         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11044
11045         return 0;
11046 }
11047
11048 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11049 {
11050         int port = SC_PORT(sc);
11051         int func = SC_FUNC(sc);
11052         int init_phase = PHASE_PF0 + func;
11053         struct ecore_ilt *ilt = sc->ilt;
11054         uint16_t cdu_ilt_start;
11055         uint32_t addr, val;
11056         uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11057         int main_mem_width, rc;
11058         uint32_t i;
11059
11060         PMD_DRV_LOG(DEBUG, "starting func init for func %d", func);
11061
11062         /* FLR cleanup */
11063         if (!CHIP_IS_E1x(sc)) {
11064                 rc = bnx2x_pf_flr_clnup(sc);
11065                 if (rc) {
11066                         PMD_DRV_LOG(NOTICE, "FLR cleanup failed!");
11067                         return rc;
11068                 }
11069         }
11070
11071         /* set MSI reconfigure capability */
11072         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11073                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11074                 val = REG_RD(sc, addr);
11075                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11076                 REG_WR(sc, addr, val);
11077         }
11078
11079         ecore_init_block(sc, BLOCK_PXP, init_phase);
11080         ecore_init_block(sc, BLOCK_PXP2, init_phase);
11081
11082         ilt = sc->ilt;
11083         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11084
11085         for (i = 0; i < L2_ILT_LINES(sc); i++) {
11086                 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11087                 ilt->lines[cdu_ilt_start + i].page_mapping =
11088                     (phys_addr_t)sc->context[i].vcxt_dma.paddr;
11089                 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11090         }
11091         ecore_ilt_init_op(sc, INITOP_SET);
11092
11093         REG_WR(sc, PRS_REG_NIC_MODE, 1);
11094
11095         if (!CHIP_IS_E1x(sc)) {
11096                 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11097
11098 /* Turn on a single ISR mode in IGU if driver is going to use
11099  * INT#x or MSI
11100  */
11101                 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11102                     || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11103                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11104                 }
11105
11106 /*
11107  * Timers workaround bug: function init part.
11108  * Need to wait 20msec after initializing ILT,
11109  * needed to make sure there are no requests in
11110  * one of the PXP internal queues with "old" ILT addresses
11111  */
11112                 DELAY(20000);
11113
11114 /*
11115  * Master enable - Due to WB DMAE writes performed before this
11116  * register is re-initialized as part of the regular function
11117  * init
11118  */
11119                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11120 /* Enable the function in IGU */
11121                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11122         }
11123
11124         sc->dmae_ready = 1;
11125
11126         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11127
11128         if (!CHIP_IS_E1x(sc))
11129                 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11130
11131         ecore_init_block(sc, BLOCK_ATC, init_phase);
11132         ecore_init_block(sc, BLOCK_DMAE, init_phase);
11133         ecore_init_block(sc, BLOCK_NIG, init_phase);
11134         ecore_init_block(sc, BLOCK_SRC, init_phase);
11135         ecore_init_block(sc, BLOCK_MISC, init_phase);
11136         ecore_init_block(sc, BLOCK_TCM, init_phase);
11137         ecore_init_block(sc, BLOCK_UCM, init_phase);
11138         ecore_init_block(sc, BLOCK_CCM, init_phase);
11139         ecore_init_block(sc, BLOCK_XCM, init_phase);
11140         ecore_init_block(sc, BLOCK_TSEM, init_phase);
11141         ecore_init_block(sc, BLOCK_USEM, init_phase);
11142         ecore_init_block(sc, BLOCK_CSEM, init_phase);
11143         ecore_init_block(sc, BLOCK_XSEM, init_phase);
11144
11145         if (!CHIP_IS_E1x(sc))
11146                 REG_WR(sc, QM_REG_PF_EN, 1);
11147
11148         if (!CHIP_IS_E1x(sc)) {
11149                 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11150                 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11151                 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11152                 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11153         }
11154         ecore_init_block(sc, BLOCK_QM, init_phase);
11155
11156         ecore_init_block(sc, BLOCK_TM, init_phase);
11157         ecore_init_block(sc, BLOCK_DORQ, init_phase);
11158
11159         ecore_init_block(sc, BLOCK_BRB1, init_phase);
11160         ecore_init_block(sc, BLOCK_PRS, init_phase);
11161         ecore_init_block(sc, BLOCK_TSDM, init_phase);
11162         ecore_init_block(sc, BLOCK_CSDM, init_phase);
11163         ecore_init_block(sc, BLOCK_USDM, init_phase);
11164         ecore_init_block(sc, BLOCK_XSDM, init_phase);
11165         ecore_init_block(sc, BLOCK_UPB, init_phase);
11166         ecore_init_block(sc, BLOCK_XPB, init_phase);
11167         ecore_init_block(sc, BLOCK_PBF, init_phase);
11168         if (!CHIP_IS_E1x(sc))
11169                 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11170
11171         ecore_init_block(sc, BLOCK_CDU, init_phase);
11172
11173         ecore_init_block(sc, BLOCK_CFC, init_phase);
11174
11175         if (!CHIP_IS_E1x(sc))
11176                 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11177
11178         if (IS_MF(sc)) {
11179                 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11180                 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11181         }
11182
11183         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11184
11185         /* HC init per function */
11186         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11187                 if (CHIP_IS_E1H(sc)) {
11188                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11189
11190                         REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11191                         REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11192                 }
11193                 ecore_init_block(sc, BLOCK_HC, init_phase);
11194
11195         } else {
11196                 uint32_t num_segs, sb_idx, prod_offset;
11197
11198                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11199
11200                 if (!CHIP_IS_E1x(sc)) {
11201                         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11202                         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11203                 }
11204
11205                 ecore_init_block(sc, BLOCK_IGU, init_phase);
11206
11207                 if (!CHIP_IS_E1x(sc)) {
11208                         int dsb_idx = 0;
11209         /**
11210          * Producer memory:
11211          * E2 mode: address 0-135 match to the mapping memory;
11212          * 136 - PF0 default prod; 137 - PF1 default prod;
11213          * 138 - PF2 default prod; 139 - PF3 default prod;
11214          * 140 - PF0 attn prod;    141 - PF1 attn prod;
11215          * 142 - PF2 attn prod;    143 - PF3 attn prod;
11216          * 144-147 reserved.
11217          *
11218          * E1.5 mode - In backward compatible mode;
11219          * for non default SB; each even line in the memory
11220          * holds the U producer and each odd line hold
11221          * the C producer. The first 128 producers are for
11222          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11223          * producers are for the DSB for each PF.
11224          * Each PF has five segments: (the order inside each
11225          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11226          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11227          * 144-147 attn prods;
11228          */
11229                         /* non-default-status-blocks */
11230                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11231                             IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11232                         for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11233                                 prod_offset = (sc->igu_base_sb + sb_idx) *
11234                                     num_segs;
11235
11236                                 for (i = 0; i < num_segs; i++) {
11237                                         addr = IGU_REG_PROD_CONS_MEMORY +
11238                                             (prod_offset + i) * 4;
11239                                         REG_WR(sc, addr, 0);
11240                                 }
11241                                 /* send consumer update with value 0 */
11242                                 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11243                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11244                                 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11245                         }
11246
11247                         /* default-status-blocks */
11248                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11249                             IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11250
11251                         if (CHIP_IS_MODE_4_PORT(sc))
11252                                 dsb_idx = SC_FUNC(sc);
11253                         else
11254                                 dsb_idx = SC_VN(sc);
11255
11256                         prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11257                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
11258                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
11259
11260                         /*
11261                          * igu prods come in chunks of E1HVN_MAX (4) -
11262                          * does not matters what is the current chip mode
11263                          */
11264                         for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11265                                 addr = IGU_REG_PROD_CONS_MEMORY +
11266                                     (prod_offset + i) * 4;
11267                                 REG_WR(sc, addr, 0);
11268                         }
11269                         /* send consumer update with 0 */
11270                         if (CHIP_INT_MODE_IS_BC(sc)) {
11271                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11272                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11273                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11274                                            CSTORM_ID, 0, IGU_INT_NOP, 1);
11275                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11276                                            XSTORM_ID, 0, IGU_INT_NOP, 1);
11277                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11278                                            TSTORM_ID, 0, IGU_INT_NOP, 1);
11279                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11280                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11281                         } else {
11282                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11283                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11284                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11285                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11286                         }
11287                         bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11288
11289                         /* !!! these should become driver const once
11290                            rf-tool supports split-68 const */
11291                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11292                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11293                         REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11294                         REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11295                         REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11296                         REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11297                 }
11298         }
11299
11300         /* Reset PCIE errors for debug */
11301         REG_WR(sc, 0x2114, 0xffffffff);
11302         REG_WR(sc, 0x2120, 0xffffffff);
11303
11304         if (CHIP_IS_E1x(sc)) {
11305                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2;    /*dwords */
11306                 main_mem_base = HC_REG_MAIN_MEMORY +
11307                     SC_PORT(sc) * (main_mem_size * 4);
11308                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11309                 main_mem_width = 8;
11310
11311                 val = REG_RD(sc, main_mem_prty_clr);
11312                 if (val) {
11313                         PMD_DRV_LOG(DEBUG,
11314                                     "Parity errors in HC block during function init (0x%x)!",
11315                                     val);
11316                 }
11317
11318 /* Clear "false" parity errors in MSI-X table */
11319                 for (i = main_mem_base;
11320                      i < main_mem_base + main_mem_size * 4;
11321                      i += main_mem_width) {
11322                         bnx2x_read_dmae(sc, i, main_mem_width / 4);
11323                         bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11324                                        i, main_mem_width / 4);
11325                 }
11326 /* Clear HC parity attention */
11327                 REG_RD(sc, main_mem_prty_clr);
11328         }
11329
11330         /* Enable STORMs SP logging */
11331         REG_WR8(sc, BAR_USTRORM_INTMEM +
11332                 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11333         REG_WR8(sc, BAR_TSTRORM_INTMEM +
11334                 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11335         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11336                 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11337         REG_WR8(sc, BAR_XSTRORM_INTMEM +
11338                 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11339
11340         elink_phy_probe(&sc->link_params);
11341
11342         return 0;
11343 }
11344
11345 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11346 {
11347         if (!BNX2X_NOMCP(sc)) {
11348                 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11349         } else {
11350                 if (!CHIP_REV_IS_SLOW(sc)) {
11351                         PMD_DRV_LOG(WARNING,
11352                                     "Bootcode is missing - cannot reset link");
11353                 }
11354         }
11355 }
11356
11357 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11358 {
11359         int port = SC_PORT(sc);
11360         uint32_t val;
11361
11362         /* reset physical Link */
11363         bnx2x_link_reset(sc);
11364
11365         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11366
11367         /* Do not rcv packets to BRB */
11368         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11369         /* Do not direct rcv packets that are not for MCP to the BRB */
11370         REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11371                     NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11372
11373         /* Configure AEU */
11374         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11375
11376         DELAY(100000);
11377
11378         /* Check for BRB port occupancy */
11379         val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11380         if (val) {
11381                 PMD_DRV_LOG(DEBUG,
11382                             "BRB1 is not empty, %d blocks are occupied", val);
11383         }
11384 }
11385
11386 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, phys_addr_t addr)
11387 {
11388         int reg;
11389         uint32_t wb_write[2];
11390
11391         reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11392
11393         wb_write[0] = ONCHIP_ADDR1(addr);
11394         wb_write[1] = ONCHIP_ADDR2(addr);
11395         REG_WR_DMAE(sc, reg, wb_write, 2);
11396 }
11397
11398 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11399 {
11400         uint32_t i, base = FUNC_ILT_BASE(func);
11401         for (i = base; i < base + ILT_PER_FUNC; i++) {
11402                 bnx2x_ilt_wr(sc, i, 0);
11403         }
11404 }
11405
11406 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11407 {
11408         struct bnx2x_fastpath *fp;
11409         int port = SC_PORT(sc);
11410         int func = SC_FUNC(sc);
11411         int i;
11412
11413         /* Disable the function in the FW */
11414         REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11415         REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11416         REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11417         REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11418
11419         /* FP SBs */
11420         FOR_EACH_ETH_QUEUE(sc, i) {
11421                 fp = &sc->fp[i];
11422                 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11423                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11424                         SB_DISABLED);
11425         }
11426
11427         /* SP SB */
11428         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11429                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11430
11431         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11432                 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11433                        0);
11434         }
11435
11436         /* Configure IGU */
11437         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11438                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11439                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11440         } else {
11441                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11442                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11443         }
11444
11445         if (CNIC_LOADED(sc)) {
11446 /* Disable Timer scan */
11447                 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11448 /*
11449  * Wait for at least 10ms and up to 2 second for the timers
11450  * scan to complete
11451  */
11452                 for (i = 0; i < 200; i++) {
11453                         DELAY(10000);
11454                         if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11455                                 break;
11456                 }
11457         }
11458
11459         /* Clear ILT */
11460         bnx2x_clear_func_ilt(sc, func);
11461
11462         /*
11463          * Timers workaround bug for E2: if this is vnic-3,
11464          * we need to set the entire ilt range for this timers.
11465          */
11466         if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11467                 struct ilt_client_info ilt_cli;
11468 /* use dummy TM client */
11469                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11470                 ilt_cli.start = 0;
11471                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11472                 ilt_cli.client_num = ILT_CLIENT_TM;
11473
11474                 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11475         }
11476
11477         /* this assumes that reset_port() called before reset_func() */
11478         if (!CHIP_IS_E1x(sc)) {
11479                 bnx2x_pf_disable(sc);
11480         }
11481
11482         sc->dmae_ready = 0;
11483 }
11484
11485 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11486 {
11487         rte_free(sc->init_ops);
11488         rte_free(sc->init_ops_offsets);
11489         rte_free(sc->init_data);
11490         rte_free(sc->iro_array);
11491 }
11492
11493 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11494 {
11495         uint32_t len, i;
11496         uint8_t *p = sc->firmware;
11497         uint32_t off[24];
11498
11499         for (i = 0; i < 24; ++i)
11500                 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11501
11502         len = off[0];
11503         sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11504         if (!sc->init_ops)
11505                 goto alloc_failed;
11506         bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11507
11508         len = off[2];
11509         sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11510         if (!sc->init_ops_offsets)
11511                 goto alloc_failed;
11512         bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11513
11514         len = off[4];
11515         sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11516         if (!sc->init_data)
11517                 goto alloc_failed;
11518         bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11519
11520         sc->tsem_int_table_data = p + off[7];
11521         sc->tsem_pram_data = p + off[9];
11522         sc->usem_int_table_data = p + off[11];
11523         sc->usem_pram_data = p + off[13];
11524         sc->csem_int_table_data = p + off[15];
11525         sc->csem_pram_data = p + off[17];
11526         sc->xsem_int_table_data = p + off[19];
11527         sc->xsem_pram_data = p + off[21];
11528
11529         len = off[22];
11530         sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11531         if (!sc->iro_array)
11532                 goto alloc_failed;
11533         bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11534
11535         return 0;
11536
11537 alloc_failed:
11538         bnx2x_release_firmware(sc);
11539         return -1;
11540 }
11541
11542 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11543 {
11544 #define MIN_PREFIX_SIZE (10)
11545
11546         int n = MIN_PREFIX_SIZE;
11547         uint16_t xlen;
11548
11549         if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11550             len <= MIN_PREFIX_SIZE) {
11551                 return -1;
11552         }
11553
11554         /* optional extra fields are present */
11555         if (zbuf[3] & 0x4) {
11556                 xlen = zbuf[13];
11557                 xlen <<= 8;
11558                 xlen += zbuf[12];
11559
11560                 n += xlen;
11561         }
11562         /* file name is present */
11563         if (zbuf[3] & 0x8) {
11564                 while ((zbuf[n++] != 0) && (n < len)) ;
11565         }
11566
11567         return n;
11568 }
11569
11570 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11571 {
11572         int ret;
11573         int data_begin = cut_gzip_prefix(zbuf, len);
11574
11575         PMD_DRV_LOG(DEBUG, "ecore_gunzip %d", len);
11576
11577         if (data_begin <= 0) {
11578                 PMD_DRV_LOG(NOTICE, "bad gzip prefix");
11579                 return -1;
11580         }
11581
11582         memset(&zlib_stream, 0, sizeof(zlib_stream));
11583         zlib_stream.next_in = zbuf + data_begin;
11584         zlib_stream.avail_in = len - data_begin;
11585         zlib_stream.next_out = sc->gz_buf;
11586         zlib_stream.avail_out = FW_BUF_SIZE;
11587
11588         ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11589         if (ret != Z_OK) {
11590                 PMD_DRV_LOG(NOTICE, "zlib inflateInit2 error");
11591                 return ret;
11592         }
11593
11594         ret = inflate(&zlib_stream, Z_FINISH);
11595         if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11596                 PMD_DRV_LOG(NOTICE, "zlib inflate error: %d %s", ret,
11597                             zlib_stream.msg);
11598         }
11599
11600         sc->gz_outlen = zlib_stream.total_out;
11601         if (sc->gz_outlen & 0x3) {
11602                 PMD_DRV_LOG(NOTICE, "firmware is not aligned. gz_outlen == %d",
11603                             sc->gz_outlen);
11604         }
11605         sc->gz_outlen >>= 2;
11606
11607         inflateEnd(&zlib_stream);
11608
11609         if (ret == Z_STREAM_END)
11610                 return 0;
11611
11612         return ret;
11613 }
11614
11615 static void
11616 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
11617                           uint32_t addr, uint32_t len)
11618 {
11619         bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11620 }
11621
11622 void
11623 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11624                           uint32_t * data)
11625 {
11626         uint8_t i;
11627         for (i = 0; i < size / 4; i++) {
11628                 REG_WR(sc, addr + (i * 4), data[i]);
11629         }
11630 }
11631
11632 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11633 {
11634         uint32_t phy_type_idx = ext_phy_type >> 8;
11635         static const char *types[] =
11636             { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11637                 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11638                 "BNX2X-8727",
11639                 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11640         };
11641
11642         if (phy_type_idx < 12)
11643                 return types[phy_type_idx];
11644         else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11645                 return types[12];
11646         else
11647                 return types[13];
11648 }
11649
11650 static const char *get_state(uint32_t state)
11651 {
11652         uint32_t state_idx = state >> 12;
11653         static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11654                 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11655                 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11656                 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11657                 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11658         };
11659
11660         if (state_idx <= 0xF)
11661                 return states[state_idx];
11662         else
11663                 return states[0x10];
11664 }
11665
11666 static const char *get_recovery_state(uint32_t state)
11667 {
11668         static const char *states[] = { "NONE", "DONE", "INIT",
11669                 "WAIT", "FAILED", "NIC_LOADING"
11670         };
11671         return states[state];
11672 }
11673
11674 static const char *get_rx_mode(uint32_t mode)
11675 {
11676         static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11677                 "PROMISC", "MAX_MULTICAST", "ERROR"
11678         };
11679
11680         if (mode < 0x4)
11681                 return modes[mode];
11682         else if (BNX2X_MAX_MULTICAST == mode)
11683                 return modes[4];
11684         else
11685                 return modes[5];
11686 }
11687
11688 #define BNX2X_INFO_STR_MAX 256
11689 static const char *get_bnx2x_flags(uint32_t flags)
11690 {
11691         int i;
11692         static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11693                 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11694                 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11695                 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11696         };
11697         static char flag_str[BNX2X_INFO_STR_MAX];
11698         memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11699
11700         for (i = 0; i < 5; i++)
11701                 if (flags & (1 << i)) {
11702                         strcat(flag_str, flag[i]);
11703                         flags ^= (1 << i);
11704                 }
11705         if (flags) {
11706                 static char unknown[BNX2X_INFO_STR_MAX];
11707                 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11708                 strcat(flag_str, unknown);
11709         }
11710         return flag_str;
11711 }
11712
11713 /*
11714  * Prints useful adapter info.
11715  */
11716 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11717 {
11718         int i = 0;
11719         __rte_unused uint32_t ext_phy_type;
11720
11721         PMD_INIT_FUNC_TRACE();
11722         if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11723                 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
11724                                                               sc->
11725                                                               devinfo.shmem_base
11726                                                               + offsetof(struct
11727                                                                          shmem_region,
11728                                                                          dev_info.port_hw_config
11729                                                                          [0].external_phy_config)));
11730         else
11731                 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
11732                                                                 sc->
11733                                                                 devinfo.shmem_base
11734                                                                 +
11735                                                                 offsetof(struct
11736                                                                          shmem_region,
11737                                                                          dev_info.port_hw_config
11738                                                                          [0].external_phy_config)));
11739
11740         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11741         /* Hardware chip info. */
11742         PMD_INIT_LOG(DEBUG, "%10s : %#08x\n", "ASIC", sc->devinfo.chip_id);
11743         PMD_INIT_LOG(DEBUG, "%10s : %c%d\n", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11744                      (CHIP_METAL(sc) >> 4));
11745
11746         /* Bus info. */
11747         PMD_INIT_LOG(DEBUG, "%10s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
11748         switch (sc->devinfo.pcie_link_speed) {
11749         case 1:
11750                 PMD_INIT_LOG(DEBUG, "2.5 Gbps\n");
11751                 break;
11752         case 2:
11753                 PMD_INIT_LOG(DEBUG, "5 Gbps\n");
11754                 break;
11755         case 4:
11756                 PMD_INIT_LOG(DEBUG, "8 Gbps\n");
11757                 break;
11758         default:
11759                 PMD_INIT_LOG(DEBUG, "Unknown link speed\n");
11760         }
11761
11762         /* Device features. */
11763         PMD_INIT_LOG(DEBUG, "%10s : ", "Flags");
11764
11765         /* Miscellaneous flags. */
11766         if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11767                 PMD_INIT_LOG(DEBUG, "MSI");
11768                 i++;
11769         }
11770
11771         if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11772                 if (i > 0)
11773                         PMD_INIT_LOG(DEBUG, "|");
11774                 PMD_INIT_LOG(DEBUG, "MSI-X");
11775                 i++;
11776         }
11777
11778         PMD_INIT_LOG(DEBUG, "\n");
11779
11780         if (IS_PF(sc)) {
11781                 PMD_INIT_LOG(DEBUG, "\n%10s : ", "Queues");
11782                 switch (sc->sp->rss_rdata.rss_mode) {
11783                 case ETH_RSS_MODE_DISABLED:
11784                         PMD_INIT_LOG(DEBUG, "None\n");
11785                         break;
11786                 case ETH_RSS_MODE_REGULAR:
11787                         PMD_INIT_LOG(DEBUG, "RSS : %d\n", sc->num_queues);
11788                         break;
11789                 default:
11790                         PMD_INIT_LOG(DEBUG, "Unknown\n");
11791                         break;
11792                 }
11793         }
11794
11795         /* Firmware versions and device features. */
11796         PMD_INIT_LOG(DEBUG, "%10s : %d.%d.%d\n%10s : %s\n",
11797                      "Firmware",
11798                      BNX2X_5710_FW_MAJOR_VERSION,
11799                      BNX2X_5710_FW_MINOR_VERSION,
11800                      BNX2X_5710_FW_REVISION_VERSION,
11801                      "Bootcode", sc->devinfo.bc_ver_str);
11802
11803         PMD_INIT_LOG(DEBUG, "===================================\n");
11804         PMD_INIT_LOG(DEBUG, "%10s : %u\n", "Bnx2x Func", sc->pcie_func);
11805         PMD_INIT_LOG(DEBUG, "%10s : %s\n", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11806         PMD_INIT_LOG(DEBUG, "%10s : %s\n", "DMAE Is",
11807                      (sc->dmae_ready ? "Ready" : "Not Ready"));
11808         PMD_INIT_LOG(DEBUG, "%10s : %s\n", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11809         PMD_INIT_LOG(DEBUG, "%10s : %s\n", "MF", (IS_MF(sc) ? "YES" : "NO"));
11810         PMD_INIT_LOG(DEBUG, "%10s : %u\n", "MTU", sc->mtu);
11811         PMD_INIT_LOG(DEBUG, "%10s : %s\n", "PHY Type", get_ext_phy_type(ext_phy_type));
11812         PMD_INIT_LOG(DEBUG, "%10s : ", "MAC Addr");
11813         for (i = 0; i < 6; i++)
11814                 PMD_INIT_LOG(DEBUG, "%x%s", sc->link_params.mac_addr[i],
11815                              i < 5 ? ":" : "\n");
11816         PMD_INIT_LOG(DEBUG, "%10s : %s\n", "RX Mode", get_rx_mode(sc->rx_mode));
11817         PMD_INIT_LOG(DEBUG, "%10s : %s\n", "State", get_state(sc->state));
11818         if (sc->recovery_state)
11819                 PMD_INIT_LOG(DEBUG, "%10s : %s\n", "Recovery",
11820                              get_recovery_state(sc->recovery_state));
11821         PMD_INIT_LOG(DEBUG, "%10s : CQ = %lx,  EQ = %lx\n", "SPQ Left",
11822                      sc->cq_spq_left, sc->eq_spq_left);
11823         PMD_INIT_LOG(DEBUG, "%10s : %x\n", "Switch", sc->link_params.switch_cfg);
11824         PMD_INIT_LOG(DEBUG, "===================================\n\n");
11825 }