drivers/net/bnx2x/bnx2x.c

   1 /*-
   2  * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.
   3  *
   4  * Eric Davis        <edavis@broadcom.com>
   5  * David Christensen <davidch@broadcom.com>
   6  * Gary Zambrano     <zambrano@broadcom.com>
   7  *
   8  * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
   9  * All rights reserved.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  *
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in the
  19  *    documentation and/or other materials provided with the distribution.
  20  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  21  *    may be used to endorse or promote products derived from this software
  22  *    without specific prior written consent.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  32  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  34  * THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 #define BNX2X_DRIVER_VERSION "1.78.18"
  38
  39 #include "bnx2x.h"
  40 #include "bnx2x_vfpf.h"
  41 #include "ecore_sp.h"
  42 #include "ecore_init.h"
  43 #include "ecore_init_ops.h"
  44
  45 #include "rte_pci_dev_ids.h"
  46
  47 #include <sys/types.h>
  48 #include <sys/stat.h>
  49 #include <fcntl.h>
  50 #include <zlib.h>
  51
  52 static z_stream zlib_stream;
  53
  54 #define EVL_VLID_MASK 0x0FFF
  55
  56 #define BNX2X_DEF_SB_ATT_IDX 0x0001
  57 #define BNX2X_DEF_SB_IDX     0x0002
  58
  59 /*
  60  * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
  61  * function HW initialization.
  62  */
  63 #define FLR_WAIT_USEC     10000 /* 10 msecs */
  64 #define FLR_WAIT_INTERVAL 50    /* usecs */
  65 #define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)   /* 200 */
  66
  67 struct pbf_pN_buf_regs {
  68         int pN;
  69         uint32_t init_crd;
  70         uint32_t crd;
  71         uint32_t crd_freed;
  72 };
  73
  74 struct pbf_pN_cmd_regs {
  75         int pN;
  76         uint32_t lines_occup;
  77         uint32_t lines_freed;
  78 };
  79
  80 /* resources needed for unloading a previously loaded device */
  81
  82 #define BNX2X_PREV_WAIT_NEEDED 1
  83 rte_spinlock_t bnx2x_prev_mtx;
  84 struct bnx2x_prev_list_node {
  85         LIST_ENTRY(bnx2x_prev_list_node) node;
  86         uint8_t bus;
  87         uint8_t slot;
  88         uint8_t path;
  89         uint8_t aer;
  90         uint8_t undi;
  91 };
  92
  93 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
  94         = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
  95
  96 static int load_count[2][3] = { { 0 } };
  97         /* per-path: 0-common, 1-port0, 2-port1 */
  98
  99 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
 100                                 uint8_t cmng_type);
 101 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
 102 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
 103                               uint8_t port);
 104 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
 105 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
 106 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
 107 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
 108 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
 109                                      uint8_t print);
 110 static void bnx2x_int_disable(struct bnx2x_softc *sc);
 111 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
 112 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
 113 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
 114                                  struct bnx2x_fastpath *fp,
 115                                  uint16_t rx_bd_prod, uint16_t rx_cq_prod);
 116 static void bnx2x_link_report(struct bnx2x_softc *sc);
 117 void bnx2x_link_status_update(struct bnx2x_softc *sc);
 118 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
 119 static void bnx2x_free_mem(struct bnx2x_softc *sc);
 120 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
 121 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
 122 static __attribute__ ((noinline))
 123 int bnx2x_nic_load(struct bnx2x_softc *sc);
 124
 125 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
 126 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
 127 static void bnx2x_periodic_stop(struct bnx2x_softc *sc);
 128 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
 129                          uint8_t storm, uint16_t index, uint8_t op,
 130                          uint8_t update);
 131
 132 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
 133 {
 134         int res;
 135
 136         mb();
 137         res = ((*addr) & (1UL << nr)) != 0;
 138         mb();
 139         return res;
 140 }
 141
 142 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
 143 {
 144         __sync_fetch_and_or(addr, (1UL << nr));
 145 }
 146
 147 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
 148 {
 149         __sync_fetch_and_and(addr, ~(1UL << nr));
 150 }
 151
 152 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
 153 {
 154         unsigned long mask = (1UL << nr);
 155         return __sync_fetch_and_and(addr, ~mask) & mask;
 156 }
 157
 158 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
 159 {
 160         return __sync_val_compare_and_swap(addr, old, new);
 161 }
 162
 163 int
 164 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
 165               const char *msg, uint32_t align)
 166 {
 167         char mz_name[RTE_MEMZONE_NAMESIZE];
 168         const struct rte_memzone *z;
 169
 170         dma->sc = sc;
 171         if (IS_PF(sc))
 172                 sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
 173                         rte_get_timer_cycles());
 174         else
 175                 sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
 176                         rte_get_timer_cycles());
 177
 178         /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
 179         z = rte_memzone_reserve_aligned(mz_name, (uint64_t) (size),
 180                                         rte_lcore_to_socket_id(rte_lcore_id()),
 181                                         0, align);
 182         if (z == NULL) {
 183                 PMD_DRV_LOG(ERR, "DMA alloc failed for %s", msg);
 184                 return -ENOMEM;
 185         }
 186         dma->paddr = (uint64_t) z->phys_addr;
 187         dma->vaddr = z->addr;
 188
 189         PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
 190
 191         return 0;
 192 }
 193
 194 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 195 {
 196         uint32_t lock_status;
 197         uint32_t resource_bit = (1 << resource);
 198         int func = SC_FUNC(sc);
 199         uint32_t hw_lock_control_reg;
 200         int cnt;
 201
 202         PMD_INIT_FUNC_TRACE();
 203
 204         /* validate the resource is within range */
 205         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 206                 PMD_DRV_LOG(NOTICE,
 207                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 208                             resource);
 209                 return -1;
 210         }
 211
 212         if (func <= 5) {
 213                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 214         } else {
 215                 hw_lock_control_reg =
 216                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 217         }
 218
 219         /* validate the resource is not already taken */
 220         lock_status = REG_RD(sc, hw_lock_control_reg);
 221         if (lock_status & resource_bit) {
 222                 PMD_DRV_LOG(NOTICE,
 223                             "resource in use (status 0x%x bit 0x%x)",
 224                             lock_status, resource_bit);
 225                 return -1;
 226         }
 227
 228         /* try every 5ms for 5 seconds */
 229         for (cnt = 0; cnt < 1000; cnt++) {
 230                 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
 231                 lock_status = REG_RD(sc, hw_lock_control_reg);
 232                 if (lock_status & resource_bit) {
 233                         return 0;
 234                 }
 235                 DELAY(5000);
 236         }
 237
 238         PMD_DRV_LOG(NOTICE, "Resource lock timeout!");
 239         return -1;
 240 }
 241
 242 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 243 {
 244         uint32_t lock_status;
 245         uint32_t resource_bit = (1 << resource);
 246         int func = SC_FUNC(sc);
 247         uint32_t hw_lock_control_reg;
 248
 249         PMD_INIT_FUNC_TRACE();
 250
 251         /* validate the resource is within range */
 252         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 253                 PMD_DRV_LOG(NOTICE,
 254                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 255                             resource);
 256                 return -1;
 257         }
 258
 259         if (func <= 5) {
 260                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 261         } else {
 262                 hw_lock_control_reg =
 263                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 264         }
 265
 266         /* validate the resource is currently taken */
 267         lock_status = REG_RD(sc, hw_lock_control_reg);
 268         if (!(lock_status & resource_bit)) {
 269                 PMD_DRV_LOG(NOTICE,
 270                             "resource not in use (status 0x%x bit 0x%x)",
 271                             lock_status, resource_bit);
 272                 return -1;
 273         }
 274
 275         REG_WR(sc, hw_lock_control_reg, resource_bit);
 276         return 0;
 277 }
 278
 279 /* copy command into DMAE command memory and set DMAE command Go */
 280 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
 281 {
 282         uint32_t cmd_offset;
 283         uint32_t i;
 284
 285         cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
 286         for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
 287                 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
 288         }
 289
 290         REG_WR(sc, dmae_reg_go_c[idx], 1);
 291 }
 292
 293 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
 294 {
 295         return (opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 296                           DMAE_COMMAND_C_TYPE_ENABLE));
 297 }
 298
 299 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
 300 {
 301         return (opcode & ~DMAE_COMMAND_SRC_RESET);
 302 }
 303
 304 uint32_t
 305 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
 306                 uint8_t with_comp, uint8_t comp_type)
 307 {
 308         uint32_t opcode = 0;
 309
 310         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 311                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 312
 313         opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
 314
 315         opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 316
 317         opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
 318                    (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
 319
 320         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 321
 322 #ifdef __BIG_ENDIAN
 323         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 324 #else
 325         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 326 #endif
 327
 328         if (with_comp) {
 329                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 330         }
 331
 332         return opcode;
 333 }
 334
 335 static void
 336 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
 337                         uint8_t src_type, uint8_t dst_type)
 338 {
 339         memset(dmae, 0, sizeof(struct dmae_command));
 340
 341         /* set the opcode */
 342         dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
 343                                        TRUE, DMAE_COMP_PCI);
 344
 345         /* fill in the completion parameters */
 346         dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
 347         dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
 348         dmae->comp_val = DMAE_COMP_VAL;
 349 }
 350
 351 /* issue a DMAE command over the init channel and wait for completion */
 352 static int
 353 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
 354 {
 355         uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
 356         int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
 357
 358         /* reset completion */
 359         *wb_comp = 0;
 360
 361         /* post the command on the channel used for initializations */
 362         bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
 363
 364         /* wait for completion */
 365         DELAY(500);
 366
 367         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 368                 if (!timeout ||
 369                     (sc->recovery_state != BNX2X_RECOVERY_DONE &&
 370                      sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 371                         PMD_DRV_LOG(INFO, "DMAE timeout!");
 372                         return DMAE_TIMEOUT;
 373                 }
 374
 375                 timeout--;
 376                 DELAY(50);
 377         }
 378
 379         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 380                 PMD_DRV_LOG(INFO, "DMAE PCI error!");
 381                 return DMAE_PCI_ERROR;
 382         }
 383
 384         return 0;
 385 }
 386
 387 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
 388 {
 389         struct dmae_command dmae;
 390         uint32_t *data;
 391         uint32_t i;
 392         int rc;
 393
 394         if (!sc->dmae_ready) {
 395                 data = BNX2X_SP(sc, wb_data[0]);
 396
 397                 for (i = 0; i < len32; i++) {
 398                         data[i] = REG_RD(sc, (src_addr + (i * 4)));
 399                 }
 400
 401                 return;
 402         }
 403
 404         /* set opcode and fixed command fields */
 405         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 406
 407         /* fill in addresses and len */
 408         dmae.src_addr_lo = (src_addr >> 2);     /* GRC addr has dword resolution */
 409         dmae.src_addr_hi = 0;
 410         dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
 411         dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
 412         dmae.len = len32;
 413
 414         /* issue the command and wait for completion */
 415         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 416                 rte_panic("DMAE failed (%d)", rc);
 417         };
 418 }
 419
 420 void
 421 bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr, uint32_t dst_addr,
 422                uint32_t len32)
 423 {
 424         struct dmae_command dmae;
 425         int rc;
 426
 427         if (!sc->dmae_ready) {
 428                 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
 429                 return;
 430         }
 431
 432         /* set opcode and fixed command fields */
 433         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 434
 435         /* fill in addresses and len */
 436         dmae.src_addr_lo = U64_LO(dma_addr);
 437         dmae.src_addr_hi = U64_HI(dma_addr);
 438         dmae.dst_addr_lo = (dst_addr >> 2);     /* GRC addr has dword resolution */
 439         dmae.dst_addr_hi = 0;
 440         dmae.len = len32;
 441
 442         /* issue the command and wait for completion */
 443         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 444                 rte_panic("DMAE failed (%d)", rc);
 445         }
 446 }
 447
 448 static void
 449 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
 450                         uint32_t addr, uint32_t len)
 451 {
 452         uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
 453         uint32_t offset = 0;
 454
 455         while (len > dmae_wr_max) {
 456                 bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 457                                (addr + offset), /* dst GRC address */
 458                                dmae_wr_max);
 459                 offset += (dmae_wr_max * 4);
 460                 len -= dmae_wr_max;
 461         }
 462
 463         bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 464                        (addr + offset), /* dst GRC address */
 465                        len);
 466 }
 467
 468 void
 469 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
 470                        uint32_t cid)
 471 {
 472         /* ustorm cxt validation */
 473         cxt->ustorm_ag_context.cdu_usage =
 474             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 475                                    CDU_REGION_NUMBER_UCM_AG,
 476                                    ETH_CONNECTION_TYPE);
 477         /* xcontext validation */
 478         cxt->xstorm_ag_context.cdu_reserved =
 479             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 480                                    CDU_REGION_NUMBER_XCM_AG,
 481                                    ETH_CONNECTION_TYPE);
 482 }
 483
 484 static void
 485 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 486                             uint8_t sb_index, uint8_t ticks)
 487 {
 488         uint32_t addr =
 489             (BAR_CSTRORM_INTMEM +
 490              CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
 491
 492         REG_WR8(sc, addr, ticks);
 493 }
 494
 495 static void
 496 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
 497                             uint8_t sb_index, uint8_t disable)
 498 {
 499         uint32_t enable_flag =
 500             (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
 501         uint32_t addr =
 502             (BAR_CSTRORM_INTMEM +
 503              CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
 504         uint8_t flags;
 505
 506         /* clear and set */
 507         flags = REG_RD8(sc, addr);
 508         flags &= ~HC_INDEX_DATA_HC_ENABLED;
 509         flags |= enable_flag;
 510         REG_WR8(sc, addr, flags);
 511 }
 512
 513 void
 514 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 515                              uint8_t sb_index, uint8_t disable, uint16_t usec)
 516 {
 517         uint8_t ticks = (usec / 4);
 518
 519         bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
 520
 521         disable = (disable) ? 1 : ((usec) ? 0 : 1);
 522         bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
 523 }
 524
 525 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
 526 {
 527         return REG_RD(sc, reg_addr);
 528 }
 529
 530 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
 531 {
 532         REG_WR(sc, reg_addr, val);
 533 }
 534
 535 void
 536 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
 537                    __rte_unused const elink_log_id_t elink_log_id, ...)
 538 {
 539         PMD_DRV_LOG(DEBUG, "ELINK EVENT LOG (%d)", elink_log_id);
 540 }
 541
 542 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
 543 {
 544         uint32_t spio_reg;
 545
 546         /* Only 2 SPIOs are configurable */
 547         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
 548                 PMD_DRV_LOG(NOTICE, "Invalid SPIO 0x%x", spio);
 549                 return -1;
 550         }
 551
 552         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 553
 554         /* read SPIO and mask except the float bits */
 555         spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
 556
 557         switch (mode) {
 558         case MISC_SPIO_OUTPUT_LOW:
 559                 /* clear FLOAT and set CLR */
 560                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 561                 spio_reg |= (spio << MISC_SPIO_CLR_POS);
 562                 break;
 563
 564         case MISC_SPIO_OUTPUT_HIGH:
 565                 /* clear FLOAT and set SET */
 566                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 567                 spio_reg |= (spio << MISC_SPIO_SET_POS);
 568                 break;
 569
 570         case MISC_SPIO_INPUT_HI_Z:
 571                 /* set FLOAT */
 572                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
 573                 break;
 574
 575         default:
 576                 break;
 577         }
 578
 579         REG_WR(sc, MISC_REG_SPIO, spio_reg);
 580         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 581
 582         return 0;
 583 }
 584
 585 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
 586 {
 587         /* The GPIO should be swapped if swap register is set and active */
 588         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 589                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 590         int gpio_shift = gpio_num;
 591         if (gpio_port)
 592                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 593
 594         uint32_t gpio_mask = (1 << gpio_shift);
 595         uint32_t gpio_reg;
 596
 597         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 598                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 599                 return -1;
 600         }
 601
 602         /* read GPIO value */
 603         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 604
 605         /* get the requested pin value */
 606         return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
 607 }
 608
 609 static int
 610 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
 611 {
 612         /* The GPIO should be swapped if swap register is set and active */
 613         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 614                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 615         int gpio_shift = gpio_num;
 616         if (gpio_port)
 617                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 618
 619         uint32_t gpio_mask = (1 << gpio_shift);
 620         uint32_t gpio_reg;
 621
 622         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 623                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 624                 return -1;
 625         }
 626
 627         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 628
 629         /* read GPIO and mask except the float bits */
 630         gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
 631
 632         switch (mode) {
 633         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 634                 /* clear FLOAT and set CLR */
 635                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 636                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
 637                 break;
 638
 639         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 640                 /* clear FLOAT and set SET */
 641                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 642                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
 643                 break;
 644
 645         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 646                 /* set FLOAT */
 647                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 648                 break;
 649
 650         default:
 651                 break;
 652         }
 653
 654         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 655         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 656
 657         return 0;
 658 }
 659
 660 static int
 661 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
 662 {
 663         uint32_t gpio_reg;
 664
 665         /* any port swapping should be handled by caller */
 666
 667         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 668
 669         /* read GPIO and mask except the float bits */
 670         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 671         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 672         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
 673         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
 674
 675         switch (mode) {
 676         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 677                 /* set CLR */
 678                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
 679                 break;
 680
 681         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 682                 /* set SET */
 683                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
 684                 break;
 685
 686         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 687                 /* set FLOAT */
 688                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 689                 break;
 690
 691         default:
 692                 PMD_DRV_LOG(NOTICE, "Invalid GPIO mode assignment %d", mode);
 693                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 694                 return -1;
 695         }
 696
 697         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 698         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 699
 700         return 0;
 701 }
 702
 703 static int
 704 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
 705                    uint8_t port)
 706 {
 707         /* The GPIO should be swapped if swap register is set and active */
 708         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 709                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 710         int gpio_shift = gpio_num;
 711         if (gpio_port)
 712                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 713
 714         uint32_t gpio_mask = (1 << gpio_shift);
 715         uint32_t gpio_reg;
 716
 717         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 718                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 719                 return -1;
 720         }
 721
 722         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 723
 724         /* read GPIO int */
 725         gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
 726
 727         switch (mode) {
 728         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
 729                 /* clear SET and set CLR */
 730                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 731                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 732                 break;
 733
 734         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
 735                 /* clear CLR and set SET */
 736                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 737                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 738                 break;
 739
 740         default:
 741                 break;
 742         }
 743
 744         REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
 745         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 746
 747         return 0;
 748 }
 749
 750 uint32_t
 751 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
 752 {
 753         return bnx2x_gpio_read(sc, gpio_num, port);
 754 }
 755
 756 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,   /* 0=low 1=high */
 757                             uint8_t port)
 758 {
 759         return bnx2x_gpio_write(sc, gpio_num, mode, port);
 760 }
 761
 762 uint8_t
 763 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
 764                          uint8_t mode /* 0=low 1=high */ )
 765 {
 766         return bnx2x_gpio_mult_write(sc, pins, mode);
 767 }
 768
 769 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,       /* 0=low 1=high */
 770                                 uint8_t port)
 771 {
 772         return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
 773 }
 774
 775 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
 776 {
 777         REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
 778                     (SC_FUNC(sc) * sizeof(uint32_t))), 1);
 779 }
 780
 781 /* send the MCP a request, block until there is a reply */
 782 uint32_t
 783 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 784 {
 785         int mb_idx = SC_FW_MB_IDX(sc);
 786         uint32_t seq;
 787         uint32_t rc = 0;
 788         uint32_t cnt = 1;
 789         uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
 790
 791         seq = ++sc->fw_seq;
 792         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
 793         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
 794
 795         PMD_DRV_LOG(DEBUG,
 796                     "wrote command 0x%08x to FW MB param 0x%08x",
 797                     (command | seq), param);
 798
 799         /* Let the FW do it's magic. GIve it up to 5 seconds... */
 800         do {
 801                 DELAY(delay * 1000);
 802                 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
 803         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
 804
 805         /* is this a reply to our command? */
 806         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
 807                 rc &= FW_MSG_CODE_MASK;
 808         } else {
 809                 /* Ruh-roh! */
 810                 PMD_DRV_LOG(NOTICE, "FW failed to respond!");
 811                 rc = 0;
 812         }
 813
 814         return rc;
 815 }
 816
 817 static uint32_t
 818 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 819 {
 820         return elink_cb_fw_command(sc, command, param);
 821 }
 822
 823 static void
 824 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
 825                            phys_addr_t mapping)
 826 {
 827         REG_WR(sc, addr, U64_LO(mapping));
 828         REG_WR(sc, (addr + 4), U64_HI(mapping));
 829 }
 830
 831 static void
 832 storm_memset_spq_addr(struct bnx2x_softc *sc, phys_addr_t mapping,
 833                       uint16_t abs_fid)
 834 {
 835         uint32_t addr = (XSEM_REG_FAST_MEMORY +
 836                          XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
 837         __storm_memset_dma_mapping(sc, addr, mapping);
 838 }
 839
 840 static void
 841 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
 842 {
 843         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
 844                 pf_id);
 845         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
 846                 pf_id);
 847         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
 848                 pf_id);
 849         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
 850                 pf_id);
 851 }
 852
 853 static void
 854 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
 855 {
 856         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
 857                 enable);
 858         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
 859                 enable);
 860         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
 861                 enable);
 862         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
 863                 enable);
 864 }
 865
 866 static void
 867 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
 868                      uint16_t pfid)
 869 {
 870         uint32_t addr;
 871         size_t size;
 872
 873         addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
 874         size = sizeof(struct event_ring_data);
 875         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
 876 }
 877
 878 static void
 879 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
 880 {
 881         uint32_t addr = (BAR_CSTRORM_INTMEM +
 882                          CSTORM_EVENT_RING_PROD_OFFSET(pfid));
 883         REG_WR16(sc, addr, eq_prod);
 884 }
 885
 886 /*
 887  * Post a slowpath command.
 888  *
 889  * A slowpath command is used to propogate a configuration change through
 890  * the controller in a controlled manner, allowing each STORM processor and
 891  * other H/W blocks to phase in the change.  The commands sent on the
 892  * slowpath are referred to as ramrods.  Depending on the ramrod used the
 893  * completion of the ramrod will occur in different ways.  Here's a
 894  * breakdown of ramrods and how they complete:
 895  *
 896  * RAMROD_CMD_ID_ETH_PORT_SETUP
 897  *   Used to setup the leading connection on a port.  Completes on the
 898  *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
 899  *
 900  * RAMROD_CMD_ID_ETH_CLIENT_SETUP
 901  *   Used to setup an additional connection on a port.  Completes on the
 902  *   RCQ of the multi-queue/RSS connection being initialized.
 903  *
 904  * RAMROD_CMD_ID_ETH_STAT_QUERY
 905  *   Used to force the storm processors to update the statistics database
 906  *   in host memory.  This ramrod is send on the leading connection CID and
 907  *   completes as an index increment of the CSTORM on the default status
 908  *   block.
 909  *
 910  * RAMROD_CMD_ID_ETH_UPDATE
 911  *   Used to update the state of the leading connection, usually to udpate
 912  *   the RSS indirection table.  Completes on the RCQ of the leading
 913  *   connection. (Not currently used under FreeBSD until OS support becomes
 914  *   available.)
 915  *
 916  * RAMROD_CMD_ID_ETH_HALT
 917  *   Used when tearing down a connection prior to driver unload.  Completes
 918  *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
 919  *   use this on the leading connection.
 920  *
 921  * RAMROD_CMD_ID_ETH_SET_MAC
 922  *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
 923  *   the RCQ of the leading connection.
 924  *
 925  * RAMROD_CMD_ID_ETH_CFC_DEL
 926  *   Used when tearing down a conneciton prior to driver unload.  Completes
 927  *   on the RCQ of the leading connection (since the current connection
 928  *   has been completely removed from controller memory).
 929  *
 930  * RAMROD_CMD_ID_ETH_PORT_DEL
 931  *   Used to tear down the leading connection prior to driver unload,
 932  *   typically fp[0].  Completes as an index increment of the CSTORM on the
 933  *   default status block.
 934  *
 935  * RAMROD_CMD_ID_ETH_FORWARD_SETUP
 936  *   Used for connection offload.  Completes on the RCQ of the multi-queue
 937  *   RSS connection that is being offloaded.  (Not currently used under
 938  *   FreeBSD.)
 939  *
 940  * There can only be one command pending per function.
 941  *
 942  * Returns:
 943  *   0 = Success, !0 = Failure.
 944  */
 945
 946 /* must be called under the spq lock */
 947 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
 948 {
 949         struct eth_spe *next_spe = sc->spq_prod_bd;
 950
 951         if (sc->spq_prod_bd == sc->spq_last_bd) {
 952                 /* wrap back to the first eth_spq */
 953                 sc->spq_prod_bd = sc->spq;
 954                 sc->spq_prod_idx = 0;
 955         } else {
 956                 sc->spq_prod_bd++;
 957                 sc->spq_prod_idx++;
 958         }
 959
 960         return next_spe;
 961 }
 962
 963 /* must be called under the spq lock */
 964 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
 965 {
 966         int func = SC_FUNC(sc);
 967
 968         /*
 969          * Make sure that BD data is updated before writing the producer.
 970          * BD data is written to the memory, the producer is read from the
 971          * memory, thus we need a full memory barrier to ensure the ordering.
 972          */
 973         mb();
 974
 975         REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
 976                  sc->spq_prod_idx);
 977
 978         mb();
 979 }
 980
 981 /**
 982  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
 983  *
 984  * @cmd:      command to check
 985  * @cmd_type: command type
 986  */
 987 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
 988 {
 989         if ((cmd_type == NONE_CONNECTION_TYPE) ||
 990             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
 991             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
 992             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
 993             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
 994             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
 995             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
 996                 return TRUE;
 997         } else {
 998                 return FALSE;
 999         }
1000 }
1001
1002 /**
1003  * bnx2x_sp_post - place a single command on an SP ring
1004  *
1005  * @sc:         driver handle
1006  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
1007  * @cid:        SW CID the command is related to
1008  * @data_hi:    command private data address (high 32 bits)
1009  * @data_lo:    command private data address (low 32 bits)
1010  * @cmd_type:   command type (e.g. NONE, ETH)
1011  *
1012  * SP data is handled as if it's always an address pair, thus data fields are
1013  * not swapped to little endian in upper functions. Instead this function swaps
1014  * data as if it's two uint32 fields.
1015  */
1016 int
1017 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1018             uint32_t data_lo, int cmd_type)
1019 {
1020         struct eth_spe *spe;
1021         uint16_t type;
1022         int common;
1023
1024         common = bnx2x_is_contextless_ramrod(command, cmd_type);
1025
1026         if (common) {
1027                 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1028                         PMD_DRV_LOG(INFO, "EQ ring is full!");
1029                         return -1;
1030                 }
1031         } else {
1032                 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1033                         PMD_DRV_LOG(INFO, "SPQ ring is full!");
1034                         return -1;
1035                 }
1036         }
1037
1038         spe = bnx2x_sp_get_next(sc);
1039
1040         /* CID needs port number to be encoded int it */
1041         spe->hdr.conn_and_cmd_data =
1042             htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1043
1044         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1045
1046         /* TBD: Check if it works for VFs */
1047         type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1048                  SPE_HDR_FUNCTION_ID);
1049
1050         spe->hdr.type = htole16(type);
1051
1052         spe->data.update_data_addr.hi = htole32(data_hi);
1053         spe->data.update_data_addr.lo = htole32(data_lo);
1054
1055         /*
1056          * It's ok if the actual decrement is issued towards the memory
1057          * somewhere between the lock and unlock. Thus no more explict
1058          * memory barrier is needed.
1059          */
1060         if (common) {
1061                 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1062         } else {
1063                 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1064         }
1065
1066         PMD_DRV_LOG(DEBUG,
1067                     "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1068                     "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1069                     sc->spq_prod_idx,
1070                     (uint32_t) U64_HI(sc->spq_dma.paddr),
1071                     (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1072                                 (uint8_t *) sc->spq_prod_bd -
1073                                 (uint8_t *) sc->spq), command, common,
1074                     HW_CID(sc, cid), data_hi, data_lo, type,
1075                     atomic_load_acq_long(&sc->cq_spq_left),
1076                     atomic_load_acq_long(&sc->eq_spq_left));
1077
1078         bnx2x_sp_prod_update(sc);
1079
1080         return 0;
1081 }
1082
1083 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1084 {
1085         SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1086                  sc->fw_drv_pulse_wr_seq);
1087 }
1088
1089 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1090 {
1091         uint16_t hw_cons;
1092         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1093
1094         if (unlikely(!txq)) {
1095                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1096                 return 0;
1097         }
1098
1099         mb();                   /* status block fields can change */
1100         hw_cons = le16toh(*fp->tx_cons_sb);
1101         return (hw_cons != txq->tx_pkt_head);
1102 }
1103
1104 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1105 {
1106         /* expand this for multi-cos if ever supported */
1107         return bnx2x_tx_queue_has_work(fp);
1108 }
1109
1110 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1111 {
1112         uint16_t rx_cq_cons_sb;
1113         struct bnx2x_rx_queue *rxq;
1114         rxq = fp->sc->rx_queues[fp->index];
1115         if (unlikely(!rxq)) {
1116                 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1117                 return 0;
1118         }
1119
1120         mb();                   /* status block fields can change */
1121         rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1122         if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1123                      MAX_RCQ_ENTRIES(rxq)))
1124                 rx_cq_cons_sb++;
1125         return (rxq->rx_cq_head != rx_cq_cons_sb);
1126 }
1127
1128 static void
1129 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1130              union eth_rx_cqe *rr_cqe)
1131 {
1132 #ifdef RTE_LIBRTE_BNX2X_DEBUG
1133         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1134 #endif
1135         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1136         enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1137         struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1138
1139         PMD_DRV_LOG(DEBUG,
1140                     "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1141                     fp->index, cid, command, sc->state,
1142                     rr_cqe->ramrod_cqe.ramrod_type);
1143
1144         switch (command) {
1145         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1146                 PMD_DRV_LOG(DEBUG, "got UPDATE ramrod. CID %d", cid);
1147                 drv_cmd = ECORE_Q_CMD_UPDATE;
1148                 break;
1149
1150         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1151                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] setup ramrod", cid);
1152                 drv_cmd = ECORE_Q_CMD_SETUP;
1153                 break;
1154
1155         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1156                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] tx-only setup ramrod", cid);
1157                 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1158                 break;
1159
1160         case (RAMROD_CMD_ID_ETH_HALT):
1161                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] halt ramrod", cid);
1162                 drv_cmd = ECORE_Q_CMD_HALT;
1163                 break;
1164
1165         case (RAMROD_CMD_ID_ETH_TERMINATE):
1166                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] teminate ramrod", cid);
1167                 drv_cmd = ECORE_Q_CMD_TERMINATE;
1168                 break;
1169
1170         case (RAMROD_CMD_ID_ETH_EMPTY):
1171                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] empty ramrod", cid);
1172                 drv_cmd = ECORE_Q_CMD_EMPTY;
1173                 break;
1174
1175         default:
1176                 PMD_DRV_LOG(DEBUG,
1177                             "ERROR: unexpected MC reply (%d)"
1178                             "on fp[%d]", command, fp->index);
1179                 return;
1180         }
1181
1182         if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1183             q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1184                 /*
1185                  * q_obj->complete_cmd() failure means that this was
1186                  * an unexpected completion.
1187                  *
1188                  * In this case we don't want to increase the sc->spq_left
1189                  * because apparently we haven't sent this command the first
1190                  * place.
1191                  */
1192                 // rte_panic("Unexpected SP completion");
1193                 return;
1194         }
1195
1196         atomic_add_acq_long(&sc->cq_spq_left, 1);
1197
1198         PMD_DRV_LOG(DEBUG, "sc->cq_spq_left 0x%lx",
1199                     atomic_load_acq_long(&sc->cq_spq_left));
1200 }
1201
1202 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1203 {
1204         struct bnx2x_rx_queue *rxq;
1205         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1206         uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1207
1208         rxq = sc->rx_queues[fp->index];
1209         if (!rxq) {
1210                 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1211                 return 0;
1212         }
1213
1214         /* CQ "next element" is of the size of the regular element */
1215         hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1216         if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1217                      USABLE_RCQ_ENTRIES_PER_PAGE)) {
1218                 hw_cq_cons++;
1219         }
1220
1221         bd_cons = rxq->rx_bd_head;
1222         bd_prod = rxq->rx_bd_tail;
1223         bd_prod_fw = bd_prod;
1224         sw_cq_cons = rxq->rx_cq_head;
1225         sw_cq_prod = rxq->rx_cq_tail;
1226
1227         /*
1228          * Memory barrier necessary as speculative reads of the rx
1229          * buffer can be ahead of the index in the status block
1230          */
1231         rmb();
1232
1233         while (sw_cq_cons != hw_cq_cons) {
1234                 union eth_rx_cqe *cqe;
1235                 struct eth_fast_path_rx_cqe *cqe_fp;
1236                 uint8_t cqe_fp_flags;
1237                 enum eth_rx_cqe_type cqe_fp_type;
1238
1239                 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1240                 bd_prod = RX_BD(bd_prod, rxq);
1241                 bd_cons = RX_BD(bd_cons, rxq);
1242
1243                 cqe = &rxq->cq_ring[comp_ring_cons];
1244                 cqe_fp = &cqe->fast_path_cqe;
1245                 cqe_fp_flags = cqe_fp->type_error_flags;
1246                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1247
1248                 /* is this a slowpath msg? */
1249                 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1250                         bnx2x_sp_event(sc, fp, cqe);
1251                         goto next_cqe;
1252                 }
1253
1254                 /* is this an error packet? */
1255                 if (unlikely(cqe_fp_flags &
1256                              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1257                         PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1258                                    cqe_fp_flags, sw_cq_cons);
1259                         goto next_rx;
1260                 }
1261
1262                 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1263
1264 next_rx:
1265                 bd_cons = NEXT_RX_BD(bd_cons);
1266                 bd_prod = NEXT_RX_BD(bd_prod);
1267                 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1268
1269 next_cqe:
1270                 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1271                 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1272
1273         }                       /* while work to do */
1274
1275         rxq->rx_bd_head = bd_cons;
1276         rxq->rx_bd_tail = bd_prod_fw;
1277         rxq->rx_cq_head = sw_cq_cons;
1278         rxq->rx_cq_tail = sw_cq_prod;
1279
1280         /* Update producers */
1281         bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1282
1283         return (sw_cq_cons != hw_cq_cons);
1284 }
1285
1286 static uint16_t
1287 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1288                 uint16_t pkt_idx, uint16_t bd_idx)
1289 {
1290         struct eth_tx_start_bd *tx_start_bd =
1291             &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1292         uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1293         struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1294
1295         if (likely(tx_mbuf != NULL)) {
1296                 rte_pktmbuf_free(tx_mbuf);
1297         } else {
1298                 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1299                            fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1300         }
1301
1302         txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1303         txq->nb_tx_avail += nbd;
1304
1305         while (nbd--)
1306                 bd_idx = NEXT_TX_BD(bd_idx);
1307
1308         return bd_idx;
1309 }
1310
1311 /* processes transmit completions */
1312 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1313 {
1314         uint16_t bd_cons, hw_cons, sw_cons;
1315         __rte_unused uint16_t tx_bd_avail;
1316
1317         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1318
1319         if (unlikely(!txq)) {
1320                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1321                 return 0;
1322         }
1323
1324         bd_cons = txq->tx_bd_head;
1325         hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1326         sw_cons = txq->tx_pkt_head;
1327
1328         while (sw_cons != hw_cons) {
1329                 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1330                 sw_cons++;
1331         }
1332
1333         txq->tx_pkt_head = sw_cons;
1334         txq->tx_bd_head = bd_cons;
1335
1336         tx_bd_avail = txq->nb_tx_avail;
1337
1338         PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1339                    "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1340                    fp->index, tx_bd_avail, hw_cons,
1341                    txq->tx_pkt_head, txq->tx_pkt_tail,
1342                    txq->tx_bd_head, txq->tx_bd_tail);
1343         return TRUE;
1344 }
1345
1346 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1347 {
1348         struct bnx2x_fastpath *fp;
1349         int i, count;
1350
1351         /* wait until all TX fastpath tasks have completed */
1352         for (i = 0; i < sc->num_queues; i++) {
1353                 fp = &sc->fp[i];
1354
1355                 count = 1000;
1356
1357                 while (bnx2x_has_tx_work(fp)) {
1358                         bnx2x_txeof(sc, fp);
1359
1360                         if (count == 0) {
1361                                 PMD_TX_LOG(ERR,
1362                                            "Timeout waiting for fp[%d] "
1363                                            "transmits to complete!", i);
1364                                 rte_panic("tx drain failure");
1365                                 return;
1366                         }
1367
1368                         count--;
1369                         DELAY(1000);
1370                         rmb();
1371                 }
1372         }
1373
1374         return;
1375 }
1376
1377 static int
1378 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1379                  int mac_type, uint8_t wait_for_comp)
1380 {
1381         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1382         int rc;
1383
1384         /* wait for completion of requested */
1385         if (wait_for_comp) {
1386                 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1387         }
1388
1389         /* Set the mac type of addresses we want to clear */
1390         bnx2x_set_bit(mac_type, &vlan_mac_flags);
1391
1392         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1393         if (rc < 0)
1394                 PMD_DRV_LOG(ERR, "Failed to delete MACs (%d)", rc);
1395
1396         return rc;
1397 }
1398
1399 int
1400 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1401                       unsigned long *rx_accept_flags,
1402                       unsigned long *tx_accept_flags)
1403 {
1404         /* Clear the flags first */
1405         *rx_accept_flags = 0;
1406         *tx_accept_flags = 0;
1407
1408         switch (rx_mode) {
1409         case BNX2X_RX_MODE_NONE:
1410                 /*
1411                  * 'drop all' supersedes any accept flags that may have been
1412                  * passed to the function.
1413                  */
1414                 break;
1415
1416         case BNX2X_RX_MODE_NORMAL:
1417                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1418                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1419                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1420
1421                 /* internal switching mode */
1422                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1423                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1424                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1425
1426                 break;
1427
1428         case BNX2X_RX_MODE_ALLMULTI:
1429                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1430                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1431                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1432
1433                 /* internal switching mode */
1434                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1435                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1436                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1437
1438                 break;
1439
1440         case BNX2X_RX_MODE_PROMISC:
1441                 /*
1442                  * According to deffinition of SI mode, iface in promisc mode
1443                  * should receive matched and unmatched (in resolution of port)
1444                  * unicast packets.
1445                  */
1446                 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1447                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1448                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1449                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1450
1451                 /* internal switching mode */
1452                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1453                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1454
1455                 if (IS_MF_SI(sc)) {
1456                         bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1457                 } else {
1458                         bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1459                 }
1460
1461                 break;
1462
1463         default:
1464                 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1465                 return -1;
1466         }
1467
1468         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1469         if (rx_mode != BNX2X_RX_MODE_NONE) {
1470                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1471                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1472         }
1473
1474         return 0;
1475 }
1476
1477 static int
1478 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1479                   unsigned long rx_mode_flags,
1480                   unsigned long rx_accept_flags,
1481                   unsigned long tx_accept_flags, unsigned long ramrod_flags)
1482 {
1483         struct ecore_rx_mode_ramrod_params ramrod_param;
1484         int rc;
1485
1486         memset(&ramrod_param, 0, sizeof(ramrod_param));
1487
1488         /* Prepare ramrod parameters */
1489         ramrod_param.cid = 0;
1490         ramrod_param.cl_id = cl_id;
1491         ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1492         ramrod_param.func_id = SC_FUNC(sc);
1493
1494         ramrod_param.pstate = &sc->sp_state;
1495         ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1496
1497         ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1498         ramrod_param.rdata_mapping =
1499             (phys_addr_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1500             bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1501
1502         ramrod_param.ramrod_flags = ramrod_flags;
1503         ramrod_param.rx_mode_flags = rx_mode_flags;
1504
1505         ramrod_param.rx_accept_flags = rx_accept_flags;
1506         ramrod_param.tx_accept_flags = tx_accept_flags;
1507
1508         rc = ecore_config_rx_mode(sc, &ramrod_param);
1509         if (rc < 0) {
1510                 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1511                 return rc;
1512         }
1513
1514         return 0;
1515 }
1516
1517 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1518 {
1519         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1520         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1521         int rc;
1522
1523         rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1524                                    &tx_accept_flags);
1525         if (rc) {
1526                 return rc;
1527         }
1528
1529         bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1530         bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1531         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1532
1533         return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1534                                  rx_accept_flags, tx_accept_flags,
1535                                  ramrod_flags);
1536 }
1537
1538 /* returns the "mcp load_code" according to global load_count array */
1539 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1540 {
1541         int path = SC_PATH(sc);
1542         int port = SC_PORT(sc);
1543
1544         PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1545                     path, load_count[path][0], load_count[path][1],
1546                     load_count[path][2]);
1547
1548         load_count[path][0]++;
1549         load_count[path][1 + port]++;
1550         PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1551                     path, load_count[path][0], load_count[path][1],
1552                     load_count[path][2]);
1553         if (load_count[path][0] == 1)
1554                 return FW_MSG_CODE_DRV_LOAD_COMMON;
1555         else if (load_count[path][1 + port] == 1)
1556                 return FW_MSG_CODE_DRV_LOAD_PORT;
1557         else
1558                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1559 }
1560
1561 /* returns the "mcp load_code" according to global load_count array */
1562 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1563 {
1564         int port = SC_PORT(sc);
1565         int path = SC_PATH(sc);
1566
1567         PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1568                     path, load_count[path][0], load_count[path][1],
1569                     load_count[path][2]);
1570         load_count[path][0]--;
1571         load_count[path][1 + port]--;
1572         PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1573                     path, load_count[path][0], load_count[path][1],
1574                     load_count[path][2]);
1575         if (load_count[path][0] == 0) {
1576                 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1577         } else if (load_count[path][1 + port] == 0) {
1578                 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1579         } else {
1580                 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1581         }
1582 }
1583
1584 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1585 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1586 {
1587         uint32_t reset_code = 0;
1588
1589         /* Select the UNLOAD request mode */
1590         if (unload_mode == UNLOAD_NORMAL) {
1591                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1592         } else {
1593                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1594         }
1595
1596         /* Send the request to the MCP */
1597         if (!BNX2X_NOMCP(sc)) {
1598                 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1599         } else {
1600                 reset_code = bnx2x_nic_unload_no_mcp(sc);
1601         }
1602
1603         return reset_code;
1604 }
1605
1606 /* send UNLOAD_DONE command to the MCP */
1607 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1608 {
1609         uint32_t reset_param =
1610             keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1611
1612         /* Report UNLOAD_DONE to MCP */
1613         if (!BNX2X_NOMCP(sc)) {
1614                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1615         }
1616 }
1617
1618 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1619 {
1620         int tout = 50;
1621
1622         if (!sc->port.pmf) {
1623                 return 0;
1624         }
1625
1626         /*
1627          * (assumption: No Attention from MCP at this stage)
1628          * PMF probably in the middle of TX disable/enable transaction
1629          * 1. Sync IRS for default SB
1630          * 2. Sync SP queue - this guarantees us that attention handling started
1631          * 3. Wait, that TX disable/enable transaction completes
1632          *
1633          * 1+2 guarantee that if DCBX attention was scheduled it already changed
1634          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1635          * received completion for the transaction the state is TX_STOPPED.
1636          * State will return to STARTED after completion of TX_STOPPED-->STARTED
1637          * transaction.
1638          */
1639
1640         while (ecore_func_get_state(sc, &sc->func_obj) !=
1641                ECORE_F_STATE_STARTED && tout--) {
1642                 DELAY(20000);
1643         }
1644
1645         if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1646                 /*
1647                  * Failed to complete the transaction in a "good way"
1648                  * Force both transactions with CLR bit.
1649                  */
1650                 struct ecore_func_state_params func_params = { NULL };
1651
1652                 PMD_DRV_LOG(NOTICE, "Unexpected function state! "
1653                             "Forcing STARTED-->TX_STOPPED-->STARTED");
1654
1655                 func_params.f_obj = &sc->func_obj;
1656                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1657
1658                 /* STARTED-->TX_STOPPED */
1659                 func_params.cmd = ECORE_F_CMD_TX_STOP;
1660                 ecore_func_state_change(sc, &func_params);
1661
1662                 /* TX_STOPPED-->STARTED */
1663                 func_params.cmd = ECORE_F_CMD_TX_START;
1664                 return ecore_func_state_change(sc, &func_params);
1665         }
1666
1667         return 0;
1668 }
1669
1670 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1671 {
1672         struct bnx2x_fastpath *fp = &sc->fp[index];
1673         struct ecore_queue_state_params q_params = { NULL };
1674         int rc;
1675
1676         PMD_DRV_LOG(DEBUG, "stopping queue %d cid %d", index, fp->index);
1677
1678         q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1679         /* We want to wait for completion in this context */
1680         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1681
1682         /* Stop the primary connection: */
1683
1684         /* ...halt the connection */
1685         q_params.cmd = ECORE_Q_CMD_HALT;
1686         rc = ecore_queue_state_change(sc, &q_params);
1687         if (rc) {
1688                 return rc;
1689         }
1690
1691         /* ...terminate the connection */
1692         q_params.cmd = ECORE_Q_CMD_TERMINATE;
1693         memset(&q_params.params.terminate, 0,
1694                sizeof(q_params.params.terminate));
1695         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1696         rc = ecore_queue_state_change(sc, &q_params);
1697         if (rc) {
1698                 return rc;
1699         }
1700
1701         /* ...delete cfc entry */
1702         q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1703         memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1704         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1705         return ecore_queue_state_change(sc, &q_params);
1706 }
1707
1708 /* wait for the outstanding SP commands */
1709 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1710 {
1711         unsigned long tmp;
1712         int tout = 5000;        /* wait for 5 secs tops */
1713
1714         while (tout--) {
1715                 mb();
1716                 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1717                         return TRUE;
1718                 }
1719
1720                 DELAY(1000);
1721         }
1722
1723         mb();
1724
1725         tmp = atomic_load_acq_long(&sc->sp_state);
1726         if (tmp & mask) {
1727                 PMD_DRV_LOG(INFO, "Filtering completion timed out: "
1728                             "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1729                 return FALSE;
1730         }
1731
1732         return FALSE;
1733 }
1734
1735 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1736 {
1737         struct ecore_func_state_params func_params = { NULL };
1738         int rc;
1739
1740         /* prepare parameters for function state transitions */
1741         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1742         func_params.f_obj = &sc->func_obj;
1743         func_params.cmd = ECORE_F_CMD_STOP;
1744
1745         /*
1746          * Try to stop the function the 'good way'. If it fails (in case
1747          * of a parity error during bnx2x_chip_cleanup()) and we are
1748          * not in a debug mode, perform a state transaction in order to
1749          * enable further HW_RESET transaction.
1750          */
1751         rc = ecore_func_state_change(sc, &func_params);
1752         if (rc) {
1753                 PMD_DRV_LOG(NOTICE, "FUNC_STOP ramrod failed. "
1754                             "Running a dry transaction");
1755                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1756                 return ecore_func_state_change(sc, &func_params);
1757         }
1758
1759         return 0;
1760 }
1761
1762 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1763 {
1764         struct ecore_func_state_params func_params = { NULL };
1765
1766         /* Prepare parameters for function state transitions */
1767         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1768
1769         func_params.f_obj = &sc->func_obj;
1770         func_params.cmd = ECORE_F_CMD_HW_RESET;
1771
1772         func_params.params.hw_init.load_phase = load_code;
1773
1774         return ecore_func_state_change(sc, &func_params);
1775 }
1776
1777 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1778 {
1779         if (disable_hw) {
1780                 /* prevent the HW from sending interrupts */
1781                 bnx2x_int_disable(sc);
1782         }
1783 }
1784
1785 static void
1786 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1787 {
1788         int port = SC_PORT(sc);
1789         struct ecore_mcast_ramrod_params rparam = { NULL };
1790         uint32_t reset_code;
1791         int i, rc = 0;
1792
1793         bnx2x_drain_tx_queues(sc);
1794
1795         /* give HW time to discard old tx messages */
1796         DELAY(1000);
1797
1798         /* Clean all ETH MACs */
1799         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1800                               FALSE);
1801         if (rc < 0) {
1802                 PMD_DRV_LOG(NOTICE, "Failed to delete all ETH MACs (%d)", rc);
1803         }
1804
1805         /* Clean up UC list  */
1806         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1807                               TRUE);
1808         if (rc < 0) {
1809                 PMD_DRV_LOG(NOTICE, "Failed to delete UC MACs list (%d)", rc);
1810         }
1811
1812         /* Disable LLH */
1813         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1814
1815         /* Set "drop all" to stop Rx */
1816
1817         /*
1818          * We need to take the if_maddr_lock() here in order to prevent
1819          * a race between the completion code and this code.
1820          */
1821
1822         if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1823                 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1824         } else {
1825                 bnx2x_set_storm_rx_mode(sc);
1826         }
1827
1828         /* Clean up multicast configuration */
1829         rparam.mcast_obj = &sc->mcast_obj;
1830         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1831         if (rc < 0) {
1832                 PMD_DRV_LOG(NOTICE,
1833                             "Failed to send DEL MCAST command (%d)", rc);
1834         }
1835
1836         /*
1837          * Send the UNLOAD_REQUEST to the MCP. This will return if
1838          * this function should perform FUNCTION, PORT, or COMMON HW
1839          * reset.
1840          */
1841         reset_code = bnx2x_send_unload_req(sc, unload_mode);
1842
1843         /*
1844          * (assumption: No Attention from MCP at this stage)
1845          * PMF probably in the middle of TX disable/enable transaction
1846          */
1847         rc = bnx2x_func_wait_started(sc);
1848         if (rc) {
1849                 PMD_DRV_LOG(NOTICE, "bnx2x_func_wait_started failed");
1850         }
1851
1852         /*
1853          * Close multi and leading connections
1854          * Completions for ramrods are collected in a synchronous way
1855          */
1856         for (i = 0; i < sc->num_queues; i++) {
1857                 if (bnx2x_stop_queue(sc, i)) {
1858                         goto unload_error;
1859                 }
1860         }
1861
1862         /*
1863          * If SP settings didn't get completed so far - something
1864          * very wrong has happen.
1865          */
1866         if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1867                 PMD_DRV_LOG(NOTICE, "Common slow path ramrods got stuck!");
1868         }
1869
1870 unload_error:
1871
1872         rc = bnx2x_func_stop(sc);
1873         if (rc) {
1874                 PMD_DRV_LOG(NOTICE, "Function stop failed!");
1875         }
1876
1877         /* disable HW interrupts */
1878         bnx2x_int_disable_sync(sc, TRUE);
1879
1880         /* Reset the chip */
1881         rc = bnx2x_reset_hw(sc, reset_code);
1882         if (rc) {
1883                 PMD_DRV_LOG(NOTICE, "Hardware reset failed");
1884         }
1885
1886         /* Report UNLOAD_DONE to MCP */
1887         bnx2x_send_unload_done(sc, keep_link);
1888 }
1889
1890 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1891 {
1892         uint32_t val;
1893
1894         PMD_DRV_LOG(DEBUG, "Disabling 'close the gates'");
1895
1896         val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1897         val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1898                  MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1899         REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1900 }
1901
1902 /*
1903  * Cleans the object that have internal lists without sending
1904  * ramrods. Should be run when interrutps are disabled.
1905  */
1906 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1907 {
1908         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1909         struct ecore_mcast_ramrod_params rparam = { NULL };
1910         struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1911         int rc;
1912
1913         /* Cleanup MACs' object first... */
1914
1915         /* Wait for completion of requested */
1916         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1917         /* Perform a dry cleanup */
1918         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1919
1920         /* Clean ETH primary MAC */
1921         bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1922         rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1923                                  &ramrod_flags);
1924         if (rc != 0) {
1925                 PMD_DRV_LOG(NOTICE, "Failed to clean ETH MACs (%d)", rc);
1926         }
1927
1928         /* Cleanup UC list */
1929         vlan_mac_flags = 0;
1930         bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1931         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1932         if (rc != 0) {
1933                 PMD_DRV_LOG(NOTICE, "Failed to clean UC list MACs (%d)", rc);
1934         }
1935
1936         /* Now clean mcast object... */
1937
1938         rparam.mcast_obj = &sc->mcast_obj;
1939         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1940
1941         /* Add a DEL command... */
1942         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1943         if (rc < 0) {
1944                 PMD_DRV_LOG(NOTICE,
1945                             "Failed to send DEL MCAST command (%d)", rc);
1946         }
1947
1948         /* now wait until all pending commands are cleared */
1949
1950         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1951         while (rc != 0) {
1952                 if (rc < 0) {
1953                         PMD_DRV_LOG(NOTICE,
1954                                     "Failed to clean MCAST object (%d)", rc);
1955                         return;
1956                 }
1957
1958                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1959         }
1960 }
1961
1962 /* stop the controller */
1963 __attribute__ ((noinline))
1964 int
1965 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1966 {
1967         uint8_t global = FALSE;
1968         uint32_t val;
1969
1970         PMD_DRV_LOG(DEBUG, "Starting NIC unload...");
1971
1972         /* stop the periodic callout */
1973         bnx2x_periodic_stop(sc);
1974
1975         /* mark driver as unloaded in shmem2 */
1976         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
1977                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
1978                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
1979                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
1980         }
1981
1982         if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
1983             (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
1984                 /*
1985                  * We can get here if the driver has been unloaded
1986                  * during parity error recovery and is either waiting for a
1987                  * leader to complete or for other functions to unload and
1988                  * then ifconfig down has been issued. In this case we want to
1989                  * unload and let other functions to complete a recovery
1990                  * process.
1991                  */
1992                 sc->recovery_state = BNX2X_RECOVERY_DONE;
1993                 sc->is_leader = 0;
1994                 bnx2x_release_leader_lock(sc);
1995                 mb();
1996
1997                 PMD_DRV_LOG(NOTICE, "Can't unload in closed or error state");
1998                 return -1;
1999         }
2000
2001         /*
2002          * Nothing to do during unload if previous bnx2x_nic_load()
2003          * did not completed succesfully - all resourses are released.
2004          */
2005         if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2006                 return 0;
2007         }
2008
2009         sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2010         mb();
2011
2012         sc->rx_mode = BNX2X_RX_MODE_NONE;
2013         bnx2x_set_rx_mode(sc);
2014         mb();
2015
2016         if (IS_PF(sc)) {
2017                 /* set ALWAYS_ALIVE bit in shmem */
2018                 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2019
2020                 bnx2x_drv_pulse(sc);
2021
2022                 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2023                 bnx2x_save_statistics(sc);
2024         }
2025
2026         /* wait till consumers catch up with producers in all queues */
2027         bnx2x_drain_tx_queues(sc);
2028
2029         /* if VF indicate to PF this function is going down (PF will delete sp
2030          * elements and clear initializations
2031          */
2032         if (IS_VF(sc)) {
2033                 bnx2x_vf_unload(sc);
2034         } else if (unload_mode != UNLOAD_RECOVERY) {
2035                 /* if this is a normal/close unload need to clean up chip */
2036                 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2037         } else {
2038                 /* Send the UNLOAD_REQUEST to the MCP */
2039                 bnx2x_send_unload_req(sc, unload_mode);
2040
2041                 /*
2042                  * Prevent transactions to host from the functions on the
2043                  * engine that doesn't reset global blocks in case of global
2044                  * attention once gloabl blocks are reset and gates are opened
2045                  * (the engine which leader will perform the recovery
2046                  * last).
2047                  */
2048                 if (!CHIP_IS_E1x(sc)) {
2049                         bnx2x_pf_disable(sc);
2050                 }
2051
2052                 /* disable HW interrupts */
2053                 bnx2x_int_disable_sync(sc, TRUE);
2054
2055                 /* Report UNLOAD_DONE to MCP */
2056                 bnx2x_send_unload_done(sc, FALSE);
2057         }
2058
2059         /*
2060          * At this stage no more interrupts will arrive so we may safely clean
2061          * the queue'able objects here in case they failed to get cleaned so far.
2062          */
2063         if (IS_PF(sc)) {
2064                 bnx2x_squeeze_objects(sc);
2065         }
2066
2067         /* There should be no more pending SP commands at this stage */
2068         sc->sp_state = 0;
2069
2070         sc->port.pmf = 0;
2071
2072         if (IS_PF(sc)) {
2073                 bnx2x_free_mem(sc);
2074         }
2075
2076         bnx2x_free_fw_stats_mem(sc);
2077
2078         sc->state = BNX2X_STATE_CLOSED;
2079
2080         /*
2081          * Check if there are pending parity attentions. If there are - set
2082          * RECOVERY_IN_PROGRESS.
2083          */
2084         if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2085                 bnx2x_set_reset_in_progress(sc);
2086
2087                 /* Set RESET_IS_GLOBAL if needed */
2088                 if (global) {
2089                         bnx2x_set_reset_global(sc);
2090                 }
2091         }
2092
2093         /*
2094          * The last driver must disable a "close the gate" if there is no
2095          * parity attention or "process kill" pending.
2096          */
2097         if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2098             bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2099                 bnx2x_disable_close_the_gate(sc);
2100         }
2101
2102         PMD_DRV_LOG(DEBUG, "Ended NIC unload");
2103
2104         return 0;
2105 }
2106
2107 /*
2108  * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2109  * visible to the controller.
2110  *
2111  * If an mbuf is submitted to this routine and cannot be given to the
2112  * controller (e.g. it has too many fragments) then the function may free
2113  * the mbuf and return to the caller.
2114  *
2115  * Returns:
2116  *   0 = Success, !0 = Failure
2117  *   Note the side effect that an mbuf may be freed if it causes a problem.
2118  */
2119 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf **m_head, int m_pkts)
2120 {
2121         struct rte_mbuf *m0;
2122         struct eth_tx_start_bd *tx_start_bd;
2123         uint16_t bd_prod, pkt_prod;
2124         int m_tx;
2125         struct bnx2x_softc *sc;
2126         uint32_t nbds = 0;
2127         struct bnx2x_fastpath *fp;
2128
2129         sc = txq->sc;
2130         fp = &sc->fp[txq->queue_id];
2131
2132         bd_prod = txq->tx_bd_tail;
2133         pkt_prod = txq->tx_pkt_tail;
2134
2135         for (m_tx = 0; m_tx < m_pkts; m_tx++) {
2136
2137                 m0 = *m_head++;
2138
2139                 if (unlikely(txq->nb_tx_avail < 3)) {
2140                         PMD_TX_LOG(ERR, "no enough bds %d/%d",
2141                                    bd_prod, txq->nb_tx_avail);
2142                         return -ENOMEM;
2143                 }
2144
2145                 txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2146
2147                 tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2148
2149                 tx_start_bd->addr =
2150                     rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR(m0));
2151                 tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2152                 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2153                 tx_start_bd->general_data =
2154                     (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2155
2156                 tx_start_bd->nbd = rte_cpu_to_le_16(2);
2157
2158                 if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2159                         tx_start_bd->vlan_or_ethertype =
2160                             rte_cpu_to_le_16(m0->vlan_tci);
2161                         tx_start_bd->bd_flags.as_bitfield |=
2162                             (X_ETH_OUTBAND_VLAN <<
2163                              ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2164                 } else {
2165                         if (IS_PF(sc))
2166                                 tx_start_bd->vlan_or_ethertype =
2167                                     rte_cpu_to_le_16(pkt_prod);
2168                         else {
2169                                 struct ether_hdr *eh
2170                                     = rte_pktmbuf_mtod(m0, struct ether_hdr *);
2171
2172                                 tx_start_bd->vlan_or_ethertype = eh->ether_type;
2173                         }
2174                 }
2175
2176                 bd_prod = NEXT_TX_BD(bd_prod);
2177                 if (IS_VF(sc)) {
2178                         struct eth_tx_parse_bd_e2 *tx_parse_bd;
2179                         uint8_t *data = rte_pktmbuf_mtod(m0, uint8_t *);
2180
2181                         tx_parse_bd =
2182                             &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2183                         tx_parse_bd->parsing_data =
2184                             (1 << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2185
2186                         rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2187                                    &data[0], 2);
2188                         rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2189                                    &data[2], 2);
2190                         rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2191                                    &data[4], 2);
2192                         rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2193                                    &data[6], 2);
2194                         rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2195                                    &data[8], 2);
2196                         rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2197                                    &data[10], 2);
2198
2199                         tx_parse_bd->data.mac_addr.dst_hi =
2200                             rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2201                         tx_parse_bd->data.mac_addr.dst_mid =
2202                             rte_cpu_to_be_16(tx_parse_bd->data.
2203                                              mac_addr.dst_mid);
2204                         tx_parse_bd->data.mac_addr.dst_lo =
2205                             rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2206                         tx_parse_bd->data.mac_addr.src_hi =
2207                             rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2208                         tx_parse_bd->data.mac_addr.src_mid =
2209                             rte_cpu_to_be_16(tx_parse_bd->data.
2210                                              mac_addr.src_mid);
2211                         tx_parse_bd->data.mac_addr.src_lo =
2212                             rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2213
2214                         PMD_TX_LOG(DEBUG,
2215                                    "PBD dst %x %x %x src %x %x %x p_data %x",
2216                                    tx_parse_bd->data.mac_addr.dst_hi,
2217                                    tx_parse_bd->data.mac_addr.dst_mid,
2218                                    tx_parse_bd->data.mac_addr.dst_lo,
2219                                    tx_parse_bd->data.mac_addr.src_hi,
2220                                    tx_parse_bd->data.mac_addr.src_mid,
2221                                    tx_parse_bd->data.mac_addr.src_lo,
2222                                    tx_parse_bd->parsing_data);
2223                 }
2224
2225                 PMD_TX_LOG(DEBUG,
2226                            "start bd: nbytes %d flags %x vlan %x\n",
2227                            tx_start_bd->nbytes,
2228                            tx_start_bd->bd_flags.as_bitfield,
2229                            tx_start_bd->vlan_or_ethertype);
2230
2231                 bd_prod = NEXT_TX_BD(bd_prod);
2232                 pkt_prod++;
2233
2234                 if (TX_IDX(bd_prod) < 2) {
2235                         nbds++;
2236                 }
2237         }
2238
2239         txq->nb_tx_avail -= m_pkts << 1;
2240         txq->tx_bd_tail = bd_prod;
2241         txq->tx_pkt_tail = pkt_prod;
2242
2243         mb();
2244         fp->tx_db.data.prod += (m_pkts << 1) + nbds;
2245         DOORBELL(sc, txq->queue_id, fp->tx_db.raw);
2246         mb();
2247
2248         return 0;
2249 }
2250
2251 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2252 {
2253         return L2_ILT_LINES(sc);
2254 }
2255
2256 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2257 {
2258         struct ilt_client_info *ilt_client;
2259         struct ecore_ilt *ilt = sc->ilt;
2260         uint16_t line = 0;
2261
2262         PMD_INIT_FUNC_TRACE();
2263
2264         ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2265
2266         /* CDU */
2267         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2268         ilt_client->client_num = ILT_CLIENT_CDU;
2269         ilt_client->page_size = CDU_ILT_PAGE_SZ;
2270         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2271         ilt_client->start = line;
2272         line += bnx2x_cid_ilt_lines(sc);
2273
2274         if (CNIC_SUPPORT(sc)) {
2275                 line += CNIC_ILT_LINES;
2276         }
2277
2278         ilt_client->end = (line - 1);
2279
2280         /* QM */
2281         if (QM_INIT(sc->qm_cid_count)) {
2282                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2283                 ilt_client->client_num = ILT_CLIENT_QM;
2284                 ilt_client->page_size = QM_ILT_PAGE_SZ;
2285                 ilt_client->flags = 0;
2286                 ilt_client->start = line;
2287
2288                 /* 4 bytes for each cid */
2289                 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2290                                      QM_ILT_PAGE_SZ);
2291
2292                 ilt_client->end = (line - 1);
2293         }
2294
2295         if (CNIC_SUPPORT(sc)) {
2296                 /* SRC */
2297                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2298                 ilt_client->client_num = ILT_CLIENT_SRC;
2299                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2300                 ilt_client->flags = 0;
2301                 ilt_client->start = line;
2302                 line += SRC_ILT_LINES;
2303                 ilt_client->end = (line - 1);
2304
2305                 /* TM */
2306                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2307                 ilt_client->client_num = ILT_CLIENT_TM;
2308                 ilt_client->page_size = TM_ILT_PAGE_SZ;
2309                 ilt_client->flags = 0;
2310                 ilt_client->start = line;
2311                 line += TM_ILT_LINES;
2312                 ilt_client->end = (line - 1);
2313         }
2314
2315         assert((line <= ILT_MAX_LINES));
2316 }
2317
2318 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2319 {
2320         int i;
2321
2322         for (i = 0; i < sc->num_queues; i++) {
2323                 /* get the Rx buffer size for RX frames */
2324                 sc->fp[i].rx_buf_size =
2325                     (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2326
2327                 /* get the mbuf allocation size for RX frames */
2328                 if (sc->fp[i].rx_buf_size <= MCLBYTES) {
2329                         sc->fp[i].mbuf_alloc_size = MCLBYTES;
2330                 } else if (sc->fp[i].rx_buf_size <= BNX2X_PAGE_SIZE) {
2331                         sc->fp[i].mbuf_alloc_size = PAGE_SIZE;
2332                 } else {
2333                         sc->fp[i].mbuf_alloc_size = MJUM9BYTES;
2334                 }
2335         }
2336 }
2337
2338 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2339 {
2340
2341         sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2342
2343         return sc->ilt == NULL;
2344 }
2345
2346 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2347 {
2348         sc->ilt->lines = rte_calloc("",
2349                                     sizeof(struct ilt_line), ILT_MAX_LINES,
2350                                     RTE_CACHE_LINE_SIZE);
2351         return sc->ilt->lines == NULL;
2352 }
2353
2354 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2355 {
2356         rte_free(sc->ilt);
2357         sc->ilt = NULL;
2358 }
2359
2360 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2361 {
2362         if (sc->ilt->lines != NULL) {
2363                 rte_free(sc->ilt->lines);
2364                 sc->ilt->lines = NULL;
2365         }
2366 }
2367
2368 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2369 {
2370         uint32_t i;
2371
2372         for (i = 0; i < L2_ILT_LINES(sc); i++) {
2373                 sc->context[i].vcxt = NULL;
2374                 sc->context[i].size = 0;
2375         }
2376
2377         ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2378
2379         bnx2x_free_ilt_lines_mem(sc);
2380 }
2381
2382 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2383 {
2384         int context_size;
2385         int allocated;
2386         int i;
2387         char cdu_name[RTE_MEMZONE_NAMESIZE];
2388
2389         /*
2390          * Allocate memory for CDU context:
2391          * This memory is allocated separately and not in the generic ILT
2392          * functions because CDU differs in few aspects:
2393          * 1. There can be multiple entities allocating memory for context -
2394          * regular L2, CNIC, and SRIOV drivers. Each separately controls
2395          * its own ILT lines.
2396          * 2. Since CDU page-size is not a single 4KB page (which is the case
2397          * for the other ILT clients), to be efficient we want to support
2398          * allocation of sub-page-size in the last entry.
2399          * 3. Context pointers are used by the driver to pass to FW / update
2400          * the context (for the other ILT clients the pointers are used just to
2401          * free the memory during unload).
2402          */
2403         context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2404         for (i = 0, allocated = 0; allocated < context_size; i++) {
2405                 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2406                                           (context_size - allocated));
2407
2408                 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2409                 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2410                                   &sc->context[i].vcxt_dma,
2411                                   cdu_name, BNX2X_PAGE_SIZE) != 0) {
2412                         bnx2x_free_mem(sc);
2413                         return -1;
2414                 }
2415
2416                 sc->context[i].vcxt =
2417                     (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2418
2419                 allocated += sc->context[i].size;
2420         }
2421
2422         bnx2x_alloc_ilt_lines_mem(sc);
2423
2424         if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2425                 PMD_DRV_LOG(NOTICE, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2426                 bnx2x_free_mem(sc);
2427                 return -1;
2428         }
2429
2430         return 0;
2431 }
2432
2433 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2434 {
2435         sc->fw_stats_num = 0;
2436
2437         sc->fw_stats_req_size = 0;
2438         sc->fw_stats_req = NULL;
2439         sc->fw_stats_req_mapping = 0;
2440
2441         sc->fw_stats_data_size = 0;
2442         sc->fw_stats_data = NULL;
2443         sc->fw_stats_data_mapping = 0;
2444 }
2445
2446 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2447 {
2448         uint8_t num_queue_stats;
2449         int num_groups, vf_headroom = 0;
2450
2451         /* number of queues for statistics is number of eth queues */
2452         num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2453
2454         /*
2455          * Total number of FW statistics requests =
2456          *   1 for port stats + 1 for PF stats + num of queues
2457          */
2458         sc->fw_stats_num = (2 + num_queue_stats);
2459
2460         /*
2461          * Request is built from stats_query_header and an array of
2462          * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2463          * rules. The real number or requests is configured in the
2464          * stats_query_header.
2465          */
2466         num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2467         if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2468                 num_groups++;
2469
2470         sc->fw_stats_req_size =
2471             (sizeof(struct stats_query_header) +
2472              (num_groups * sizeof(struct stats_query_cmd_group)));
2473
2474         /*
2475          * Data for statistics requests + stats_counter.
2476          * stats_counter holds per-STORM counters that are incremented when
2477          * STORM has finished with the current request. Memory for FCoE
2478          * offloaded statistics are counted anyway, even if they will not be sent.
2479          * VF stats are not accounted for here as the data of VF stats is stored
2480          * in memory allocated by the VF, not here.
2481          */
2482         sc->fw_stats_data_size =
2483             (sizeof(struct stats_counter) +
2484              sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2485              /* sizeof(struct fcoe_statistics_params) + */
2486              (sizeof(struct per_queue_stats) * num_queue_stats));
2487
2488         if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2489                           &sc->fw_stats_dma, "fw_stats",
2490                           RTE_CACHE_LINE_SIZE) != 0) {
2491                 bnx2x_free_fw_stats_mem(sc);
2492                 return -1;
2493         }
2494
2495         /* set up the shortcuts */
2496
2497         sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2498         sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2499
2500         sc->fw_stats_data =
2501             (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2502                                          sc->fw_stats_req_size);
2503         sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2504                                      sc->fw_stats_req_size);
2505
2506         return 0;
2507 }
2508
2509 /*
2510  * Bits map:
2511  * 0-7  - Engine0 load counter.
2512  * 8-15 - Engine1 load counter.
2513  * 16   - Engine0 RESET_IN_PROGRESS bit.
2514  * 17   - Engine1 RESET_IN_PROGRESS bit.
2515  * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
2516  *        function on the engine
2517  * 19   - Engine1 ONE_IS_LOADED.
2518  * 20   - Chip reset flow bit. When set none-leader must wait for both engines
2519  *        leader to complete (check for both RESET_IN_PROGRESS bits and not
2520  *        for just the one belonging to its engine).
2521  */
2522 #define BNX2X_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
2523 #define BNX2X_PATH0_LOAD_CNT_MASK   0x000000ff
2524 #define BNX2X_PATH0_LOAD_CNT_SHIFT  0
2525 #define BNX2X_PATH1_LOAD_CNT_MASK   0x0000ff00
2526 #define BNX2X_PATH1_LOAD_CNT_SHIFT  8
2527 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2528 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2529 #define BNX2X_GLOBAL_RESET_BIT      0x00040000
2530
2531 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2532 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2533 {
2534         uint32_t val;
2535         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2536         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2537         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2538         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2539 }
2540
2541 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2542 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2543 {
2544         uint32_t val;
2545         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2546         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2547         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2548         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2549 }
2550
2551 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2552 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2553 {
2554         return (REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT);
2555 }
2556
2557 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2558 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2559 {
2560         uint32_t val;
2561         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2562             BNX2X_PATH0_RST_IN_PROG_BIT;
2563
2564         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2565
2566         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2567         /* Clear the bit */
2568         val &= ~bit;
2569         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2570
2571         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2572 }
2573
2574 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2575 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2576 {
2577         uint32_t val;
2578         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2579             BNX2X_PATH0_RST_IN_PROG_BIT;
2580
2581         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2582
2583         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2584         /* Set the bit */
2585         val |= bit;
2586         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2587
2588         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2589 }
2590
2591 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2592 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2593 {
2594         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2595         uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2596             BNX2X_PATH0_RST_IN_PROG_BIT;
2597
2598         /* return false if bit is set */
2599         return (val & bit) ? FALSE : TRUE;
2600 }
2601
2602 /* get the load status for an engine, should be run under rtnl lock */
2603 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2604 {
2605         uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2606             BNX2X_PATH0_LOAD_CNT_MASK;
2607         uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2608             BNX2X_PATH0_LOAD_CNT_SHIFT;
2609         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2610
2611         val = ((val & mask) >> shift);
2612
2613         return (val != 0);
2614 }
2615
2616 /* set pf load mark */
2617 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2618 {
2619         uint32_t val;
2620         uint32_t val1;
2621         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2622             BNX2X_PATH0_LOAD_CNT_MASK;
2623         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2624             BNX2X_PATH0_LOAD_CNT_SHIFT;
2625
2626         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2627
2628         PMD_INIT_FUNC_TRACE();
2629
2630         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2631
2632         /* get the current counter value */
2633         val1 = ((val & mask) >> shift);
2634
2635         /* set bit of this PF */
2636         val1 |= (1 << SC_ABS_FUNC(sc));
2637
2638         /* clear the old value */
2639         val &= ~mask;
2640
2641         /* set the new one */
2642         val |= ((val1 << shift) & mask);
2643
2644         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2645
2646         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2647 }
2648
2649 /* clear pf load mark */
2650 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2651 {
2652         uint32_t val1, val;
2653         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2654             BNX2X_PATH0_LOAD_CNT_MASK;
2655         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2656             BNX2X_PATH0_LOAD_CNT_SHIFT;
2657
2658         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2659         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2660
2661         /* get the current counter value */
2662         val1 = (val & mask) >> shift;
2663
2664         /* clear bit of that PF */
2665         val1 &= ~(1 << SC_ABS_FUNC(sc));
2666
2667         /* clear the old value */
2668         val &= ~mask;
2669
2670         /* set the new one */
2671         val |= ((val1 << shift) & mask);
2672
2673         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2674         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2675         return val1 != 0;
2676 }
2677
2678 /* send load requrest to mcp and analyze response */
2679 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2680 {
2681         PMD_INIT_FUNC_TRACE();
2682
2683         /* init fw_seq */
2684         sc->fw_seq =
2685             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2686              DRV_MSG_SEQ_NUMBER_MASK);
2687
2688         PMD_DRV_LOG(DEBUG, "initial fw_seq 0x%04x", sc->fw_seq);
2689
2690 #ifdef BNX2X_PULSE
2691         /* get the current FW pulse sequence */
2692         sc->fw_drv_pulse_wr_seq =
2693             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2694              DRV_PULSE_SEQ_MASK);
2695 #else
2696         /* set ALWAYS_ALIVE bit in shmem */
2697         sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2698         bnx2x_drv_pulse(sc);
2699 #endif
2700
2701         /* load request */
2702         (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2703                                       DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2704
2705         /* if the MCP fails to respond we must abort */
2706         if (!(*load_code)) {
2707                 PMD_DRV_LOG(NOTICE, "MCP response failure!");
2708                 return -1;
2709         }
2710
2711         /* if MCP refused then must abort */
2712         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2713                 PMD_DRV_LOG(NOTICE, "MCP refused load request");
2714                 return -1;
2715         }
2716
2717         return 0;
2718 }
2719
2720 /*
2721  * Check whether another PF has already loaded FW to chip. In virtualized
2722  * environments a pf from anoth VM may have already initialized the device
2723  * including loading FW.
2724  */
2725 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2726 {
2727         uint32_t my_fw, loaded_fw;
2728
2729         /* is another pf loaded on this engine? */
2730         if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2731             (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2732                 /* build my FW version dword */
2733                 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2734                          (BNX2X_5710_FW_MINOR_VERSION << 8) +
2735                          (BNX2X_5710_FW_REVISION_VERSION << 16) +
2736                          (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2737
2738                 /* read loaded FW from chip */
2739                 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2740                 PMD_DRV_LOG(DEBUG, "loaded FW 0x%08x / my FW 0x%08x",
2741                             loaded_fw, my_fw);
2742
2743                 /* abort nic load if version mismatch */
2744                 if (my_fw != loaded_fw) {
2745                         PMD_DRV_LOG(NOTICE,
2746                                     "FW 0x%08x already loaded (mine is 0x%08x)",
2747                                     loaded_fw, my_fw);
2748                         return -1;
2749                 }
2750         }
2751
2752         return 0;
2753 }
2754
2755 /* mark PMF if applicable */
2756 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2757 {
2758         uint32_t ncsi_oem_data_addr;
2759
2760         PMD_INIT_FUNC_TRACE();
2761
2762         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2763             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2764             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2765                 /*
2766                  * Barrier here for ordering between the writing to sc->port.pmf here
2767                  * and reading it from the periodic task.
2768                  */
2769                 sc->port.pmf = 1;
2770                 mb();
2771         } else {
2772                 sc->port.pmf = 0;
2773         }
2774
2775         PMD_DRV_LOG(DEBUG, "pmf %d", sc->port.pmf);
2776
2777         if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2778                 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2779                         ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2780                         if (ncsi_oem_data_addr) {
2781                                 REG_WR(sc,
2782                                        (ncsi_oem_data_addr +
2783                                         offsetof(struct glob_ncsi_oem_data,
2784                                                  driver_version)), 0);
2785                         }
2786                 }
2787         }
2788 }
2789
2790 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2791 {
2792         int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2793         int abs_func;
2794         int vn;
2795
2796         if (BNX2X_NOMCP(sc)) {
2797                 return;         /* what should be the default bvalue in this case */
2798         }
2799
2800         /*
2801          * The formula for computing the absolute function number is...
2802          * For 2 port configuration (4 functions per port):
2803          *   abs_func = 2 * vn + SC_PORT + SC_PATH
2804          * For 4 port configuration (2 functions per port):
2805          *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2806          */
2807         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2808                 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2809                 if (abs_func >= E1H_FUNC_MAX) {
2810                         break;
2811                 }
2812                 sc->devinfo.mf_info.mf_config[vn] =
2813                     MFCFG_RD(sc, func_mf_config[abs_func].config);
2814         }
2815
2816         if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2817             FUNC_MF_CFG_FUNC_DISABLED) {
2818                 PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
2819                 sc->flags |= BNX2X_MF_FUNC_DIS;
2820         } else {
2821                 PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
2822                 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2823         }
2824 }
2825
2826 /* acquire split MCP access lock register */
2827 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2828 {
2829         uint32_t j, val;
2830
2831         for (j = 0; j < 1000; j++) {
2832                 val = (1UL << 31);
2833                 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2834                 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2835                 if (val & (1L << 31))
2836                         break;
2837
2838                 DELAY(5000);
2839         }
2840
2841         if (!(val & (1L << 31))) {
2842                 PMD_DRV_LOG(NOTICE, "Cannot acquire MCP access lock register");
2843                 return -1;
2844         }
2845
2846         return 0;
2847 }
2848
2849 /* release split MCP access lock register */
2850 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2851 {
2852         REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2853 }
2854
2855 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2856 {
2857         int port = SC_PORT(sc);
2858         uint32_t ext_phy_config;
2859
2860         /* mark the failure */
2861         ext_phy_config =
2862             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2863
2864         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2865         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2866         SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2867                  ext_phy_config);
2868
2869         /* log the failure */
2870         PMD_DRV_LOG(INFO,
2871                     "Fan Failure has caused the driver to shutdown "
2872                     "the card to prevent permanent damage. "
2873                     "Please contact OEM Support for assistance");
2874
2875         rte_panic("Schedule task to handle fan failure");
2876 }
2877
2878 /* this function is called upon a link interrupt */
2879 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2880 {
2881         uint32_t pause_enabled = 0;
2882         struct host_port_stats *pstats;
2883         int cmng_fns;
2884
2885         /* Make sure that we are synced with the current statistics */
2886         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2887
2888         elink_link_update(&sc->link_params, &sc->link_vars);
2889
2890         if (sc->link_vars.link_up) {
2891
2892                 /* dropless flow control */
2893                 if (sc->dropless_fc) {
2894                         pause_enabled = 0;
2895
2896                         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2897                                 pause_enabled = 1;
2898                         }
2899
2900                         REG_WR(sc,
2901                                (BAR_USTRORM_INTMEM +
2902                                 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2903                                pause_enabled);
2904                 }
2905
2906                 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2907                         pstats = BNX2X_SP(sc, port_stats);
2908                         /* reset old mac stats */
2909                         memset(&(pstats->mac_stx[0]), 0,
2910                                sizeof(struct mac_stx));
2911                 }
2912
2913                 if (sc->state == BNX2X_STATE_OPEN) {
2914                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2915                 }
2916         }
2917
2918         if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2919                 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2920
2921                 if (cmng_fns != CMNG_FNS_NONE) {
2922                         bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2923                         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2924                 }
2925         }
2926
2927         bnx2x_link_report(sc);
2928
2929         if (IS_MF(sc)) {
2930                 bnx2x_link_sync_notify(sc);
2931         }
2932 }
2933
2934 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2935 {
2936         int port = SC_PORT(sc);
2937         uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2938             MISC_REG_AEU_MASK_ATTN_FUNC_0;
2939         uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2940             NIG_REG_MASK_INTERRUPT_PORT0;
2941         uint32_t aeu_mask;
2942         uint32_t nig_mask = 0;
2943         uint32_t reg_addr;
2944         uint32_t igu_acked;
2945         uint32_t cnt;
2946
2947         if (sc->attn_state & asserted) {
2948                 PMD_DRV_LOG(ERR, "IGU ERROR attn=0x%08x", asserted);
2949         }
2950
2951         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2952
2953         aeu_mask = REG_RD(sc, aeu_addr);
2954
2955         aeu_mask &= ~(asserted & 0x3ff);
2956
2957         REG_WR(sc, aeu_addr, aeu_mask);
2958
2959         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2960
2961         sc->attn_state |= asserted;
2962
2963         if (asserted & ATTN_HARD_WIRED_MASK) {
2964                 if (asserted & ATTN_NIG_FOR_FUNC) {
2965
2966                         /* save nig interrupt mask */
2967                         nig_mask = REG_RD(sc, nig_int_mask_addr);
2968
2969                         /* If nig_mask is not set, no need to call the update function */
2970                         if (nig_mask) {
2971                                 REG_WR(sc, nig_int_mask_addr, 0);
2972
2973                                 bnx2x_link_attn(sc);
2974                         }
2975
2976                         /* handle unicore attn? */
2977                 }
2978
2979                 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2980                         PMD_DRV_LOG(DEBUG, "ATTN_SW_TIMER_4_FUNC!");
2981                 }
2982
2983                 if (asserted & GPIO_2_FUNC) {
2984                         PMD_DRV_LOG(DEBUG, "GPIO_2_FUNC!");
2985                 }
2986
2987                 if (asserted & GPIO_3_FUNC) {
2988                         PMD_DRV_LOG(DEBUG, "GPIO_3_FUNC!");
2989                 }
2990
2991                 if (asserted & GPIO_4_FUNC) {
2992                         PMD_DRV_LOG(DEBUG, "GPIO_4_FUNC!");
2993                 }
2994
2995                 if (port == 0) {
2996                         if (asserted & ATTN_GENERAL_ATTN_1) {
2997                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_1!");
2998                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2999                         }
3000                         if (asserted & ATTN_GENERAL_ATTN_2) {
3001                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_2!");
3002                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3003                         }
3004                         if (asserted & ATTN_GENERAL_ATTN_3) {
3005                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_3!");
3006                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3007                         }
3008                 } else {
3009                         if (asserted & ATTN_GENERAL_ATTN_4) {
3010                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_4!");
3011                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3012                         }
3013                         if (asserted & ATTN_GENERAL_ATTN_5) {
3014                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_5!");
3015                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3016                         }
3017                         if (asserted & ATTN_GENERAL_ATTN_6) {
3018                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_6!");
3019                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3020                         }
3021                 }
3022         }
3023         /* hardwired */
3024         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3025                 reg_addr =
3026                     (HC_REG_COMMAND_REG + port * 32 +
3027                      COMMAND_REG_ATTN_BITS_SET);
3028         } else {
3029                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3030         }
3031
3032         PMD_DRV_LOG(DEBUG, "about to mask 0x%08x at %s addr 0x%08x",
3033                     asserted,
3034                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3035                     reg_addr);
3036         REG_WR(sc, reg_addr, asserted);
3037
3038         /* now set back the mask */
3039         if (asserted & ATTN_NIG_FOR_FUNC) {
3040                 /*
3041                  * Verify that IGU ack through BAR was written before restoring
3042                  * NIG mask. This loop should exit after 2-3 iterations max.
3043                  */
3044                 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3045                         cnt = 0;
3046
3047                         do {
3048                                 igu_acked =
3049                                     REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3050                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3051                                  && (++cnt < MAX_IGU_ATTN_ACK_TO));
3052
3053                         if (!igu_acked) {
3054                                 PMD_DRV_LOG(ERR,
3055                                             "Failed to verify IGU ack on time");
3056                         }
3057
3058                         mb();
3059                 }
3060
3061                 REG_WR(sc, nig_int_mask_addr, nig_mask);
3062
3063         }
3064 }
3065
3066 static void
3067 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3068                      __rte_unused const char *blk)
3069 {
3070         PMD_DRV_LOG(INFO, "%s%s", idx ? ", " : "", blk);
3071 }
3072
3073 static int
3074 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3075                               uint8_t print)
3076 {
3077         uint32_t cur_bit = 0;
3078         int i = 0;
3079
3080         for (i = 0; sig; i++) {
3081                 cur_bit = ((uint32_t) 0x1 << i);
3082                 if (sig & cur_bit) {
3083                         switch (cur_bit) {
3084                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3085                                 if (print)
3086                                         bnx2x_print_next_block(sc, par_num++,
3087                                                              "BRB");
3088                                 break;
3089                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3090                                 if (print)
3091                                         bnx2x_print_next_block(sc, par_num++,
3092                                                              "PARSER");
3093                                 break;
3094                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3095                                 if (print)
3096                                         bnx2x_print_next_block(sc, par_num++,
3097                                                              "TSDM");
3098                                 break;
3099                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3100                                 if (print)
3101                                         bnx2x_print_next_block(sc, par_num++,
3102                                                              "SEARCHER");
3103                                 break;
3104                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3105                                 if (print)
3106                                         bnx2x_print_next_block(sc, par_num++,
3107                                                              "TCM");
3108                                 break;
3109                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3110                                 if (print)
3111                                         bnx2x_print_next_block(sc, par_num++,
3112                                                              "TSEMI");
3113                                 break;
3114                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3115                                 if (print)
3116                                         bnx2x_print_next_block(sc, par_num++,
3117                                                              "XPB");
3118                                 break;
3119                         }
3120
3121                         /* Clear the bit */
3122                         sig &= ~cur_bit;
3123                 }
3124         }
3125
3126         return par_num;
3127 }
3128
3129 static int
3130 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3131                               uint8_t * global, uint8_t print)
3132 {
3133         int i = 0;
3134         uint32_t cur_bit = 0;
3135         for (i = 0; sig; i++) {
3136                 cur_bit = ((uint32_t) 0x1 << i);
3137                 if (sig & cur_bit) {
3138                         switch (cur_bit) {
3139                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3140                                 if (print)
3141                                         bnx2x_print_next_block(sc, par_num++,
3142                                                              "PBF");
3143                                 break;
3144                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3145                                 if (print)
3146                                         bnx2x_print_next_block(sc, par_num++,
3147                                                              "QM");
3148                                 break;
3149                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3150                                 if (print)
3151                                         bnx2x_print_next_block(sc, par_num++,
3152                                                              "TM");
3153                                 break;
3154                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3155                                 if (print)
3156                                         bnx2x_print_next_block(sc, par_num++,
3157                                                              "XSDM");
3158                                 break;
3159                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3160                                 if (print)
3161                                         bnx2x_print_next_block(sc, par_num++,
3162                                                              "XCM");
3163                                 break;
3164                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3165                                 if (print)
3166                                         bnx2x_print_next_block(sc, par_num++,
3167                                                              "XSEMI");
3168                                 break;
3169                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3170                                 if (print)
3171                                         bnx2x_print_next_block(sc, par_num++,
3172                                                              "DOORBELLQ");
3173                                 break;
3174                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3175                                 if (print)
3176                                         bnx2x_print_next_block(sc, par_num++,
3177                                                              "NIG");
3178                                 break;
3179                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3180                                 if (print)
3181                                         bnx2x_print_next_block(sc, par_num++,
3182                                                              "VAUX PCI CORE");
3183                                 *global = TRUE;
3184                                 break;
3185                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3186                                 if (print)
3187                                         bnx2x_print_next_block(sc, par_num++,
3188                                                              "DEBUG");
3189                                 break;
3190                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3191                                 if (print)
3192                                         bnx2x_print_next_block(sc, par_num++,
3193                                                              "USDM");
3194                                 break;
3195                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3196                                 if (print)
3197                                         bnx2x_print_next_block(sc, par_num++,
3198                                                              "UCM");
3199                                 break;
3200                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3201                                 if (print)
3202                                         bnx2x_print_next_block(sc, par_num++,
3203                                                              "USEMI");
3204                                 break;
3205                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3206                                 if (print)
3207                                         bnx2x_print_next_block(sc, par_num++,
3208                                                              "UPB");
3209                                 break;
3210                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3211                                 if (print)
3212                                         bnx2x_print_next_block(sc, par_num++,
3213                                                              "CSDM");
3214                                 break;
3215                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3216                                 if (print)
3217                                         bnx2x_print_next_block(sc, par_num++,
3218                                                              "CCM");
3219                                 break;
3220                         }
3221
3222                         /* Clear the bit */
3223                         sig &= ~cur_bit;
3224                 }
3225         }
3226
3227         return par_num;
3228 }
3229
3230 static int
3231 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3232                               uint8_t print)
3233 {
3234         uint32_t cur_bit = 0;
3235         int i = 0;
3236
3237         for (i = 0; sig; i++) {
3238                 cur_bit = ((uint32_t) 0x1 << i);
3239                 if (sig & cur_bit) {
3240                         switch (cur_bit) {
3241                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3242                                 if (print)
3243                                         bnx2x_print_next_block(sc, par_num++,
3244                                                              "CSEMI");
3245                                 break;
3246                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3247                                 if (print)
3248                                         bnx2x_print_next_block(sc, par_num++,
3249                                                              "PXP");
3250                                 break;
3251                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3252                                 if (print)
3253                                         bnx2x_print_next_block(sc, par_num++,
3254                                                              "PXPPCICLOCKCLIENT");
3255                                 break;
3256                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3257                                 if (print)
3258                                         bnx2x_print_next_block(sc, par_num++,
3259                                                              "CFC");
3260                                 break;
3261                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3262                                 if (print)
3263                                         bnx2x_print_next_block(sc, par_num++,
3264                                                              "CDU");
3265                                 break;
3266                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3267                                 if (print)
3268                                         bnx2x_print_next_block(sc, par_num++,
3269                                                              "DMAE");
3270                                 break;
3271                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3272                                 if (print)
3273                                         bnx2x_print_next_block(sc, par_num++,
3274                                                              "IGU");
3275                                 break;
3276                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3277                                 if (print)
3278                                         bnx2x_print_next_block(sc, par_num++,
3279                                                              "MISC");
3280                                 break;
3281                         }
3282
3283                         /* Clear the bit */
3284                         sig &= ~cur_bit;
3285                 }
3286         }
3287
3288         return par_num;
3289 }
3290
3291 static int
3292 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3293                               uint8_t * global, uint8_t print)
3294 {
3295         uint32_t cur_bit = 0;
3296         int i = 0;
3297
3298         for (i = 0; sig; i++) {
3299                 cur_bit = ((uint32_t) 0x1 << i);
3300                 if (sig & cur_bit) {
3301                         switch (cur_bit) {
3302                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3303                                 if (print)
3304                                         bnx2x_print_next_block(sc, par_num++,
3305                                                              "MCP ROM");
3306                                 *global = TRUE;
3307                                 break;
3308                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3309                                 if (print)
3310                                         bnx2x_print_next_block(sc, par_num++,
3311                                                              "MCP UMP RX");
3312                                 *global = TRUE;
3313                                 break;
3314                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3315                                 if (print)
3316                                         bnx2x_print_next_block(sc, par_num++,
3317                                                              "MCP UMP TX");
3318                                 *global = TRUE;
3319                                 break;
3320                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3321                                 if (print)
3322                                         bnx2x_print_next_block(sc, par_num++,
3323                                                              "MCP SCPAD");
3324                                 *global = TRUE;
3325                                 break;
3326                         }
3327
3328                         /* Clear the bit */
3329                         sig &= ~cur_bit;
3330                 }
3331         }
3332
3333         return par_num;
3334 }
3335
3336 static int
3337 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3338                               uint8_t print)
3339 {
3340         uint32_t cur_bit = 0;
3341         int i = 0;
3342
3343         for (i = 0; sig; i++) {
3344                 cur_bit = ((uint32_t) 0x1 << i);
3345                 if (sig & cur_bit) {
3346                         switch (cur_bit) {
3347                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3348                                 if (print)
3349                                         bnx2x_print_next_block(sc, par_num++,
3350                                                              "PGLUE_B");
3351                                 break;
3352                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3353                                 if (print)
3354                                         bnx2x_print_next_block(sc, par_num++,
3355                                                              "ATC");
3356                                 break;
3357                         }
3358
3359                         /* Clear the bit */
3360                         sig &= ~cur_bit;
3361                 }
3362         }
3363
3364         return par_num;
3365 }
3366
3367 static uint8_t
3368 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3369                 uint32_t * sig)
3370 {
3371         int par_num = 0;
3372
3373         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3374             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3375             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3376             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3377             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3378                 PMD_DRV_LOG(ERR,
3379                             "Parity error: HW block parity attention:"
3380                             "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3381                             (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3382                             (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3383                             (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3384                             (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3385                             (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3386
3387                 if (print)
3388                         PMD_DRV_LOG(INFO, "Parity errors detected in blocks: ");
3389
3390                 par_num =
3391                     bnx2x_check_blocks_with_parity0(sc, sig[0] &
3392                                                   HW_PRTY_ASSERT_SET_0,
3393                                                   par_num, print);
3394                 par_num =
3395                     bnx2x_check_blocks_with_parity1(sc, sig[1] &
3396                                                   HW_PRTY_ASSERT_SET_1,
3397                                                   par_num, global, print);
3398                 par_num =
3399                     bnx2x_check_blocks_with_parity2(sc, sig[2] &
3400                                                   HW_PRTY_ASSERT_SET_2,
3401                                                   par_num, print);
3402                 par_num =
3403                     bnx2x_check_blocks_with_parity3(sc, sig[3] &
3404                                                   HW_PRTY_ASSERT_SET_3,
3405                                                   par_num, global, print);
3406                 par_num =
3407                     bnx2x_check_blocks_with_parity4(sc, sig[4] &
3408                                                   HW_PRTY_ASSERT_SET_4,
3409                                                   par_num, print);
3410
3411                 if (print)
3412                         PMD_DRV_LOG(INFO, "");
3413
3414                 return TRUE;
3415         }
3416
3417         return FALSE;
3418 }
3419
3420 static uint8_t
3421 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3422 {
3423         struct attn_route attn = { {0} };
3424         int port = SC_PORT(sc);
3425
3426         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3427         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3428         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3429         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3430
3431         if (!CHIP_IS_E1x(sc))
3432                 attn.sig[4] =
3433                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3434
3435         return bnx2x_parity_attn(sc, global, print, attn.sig);
3436 }
3437
3438 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3439 {
3440         uint32_t val;
3441
3442         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3443                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3444                 PMD_DRV_LOG(INFO, "ERROR: PGLUE hw attention 0x%08x", val);
3445                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3446                         PMD_DRV_LOG(INFO,
3447                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3448                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3449                         PMD_DRV_LOG(INFO,
3450                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3451                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3452                         PMD_DRV_LOG(INFO,
3453                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3454                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3455                         PMD_DRV_LOG(INFO,
3456                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3457                 if (val &
3458                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3459                         PMD_DRV_LOG(INFO,
3460                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3461                 if (val &
3462                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3463                         PMD_DRV_LOG(INFO,
3464                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3465                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3466                         PMD_DRV_LOG(INFO,
3467                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3468                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3469                         PMD_DRV_LOG(INFO,
3470                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3471                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3472                         PMD_DRV_LOG(INFO,
3473                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3474         }
3475
3476         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3477                 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3478                 PMD_DRV_LOG(INFO, "ERROR: ATC hw attention 0x%08x", val);
3479                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3480                         PMD_DRV_LOG(INFO,
3481                                     "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3482                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3483                         PMD_DRV_LOG(INFO,
3484                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3485                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3486                         PMD_DRV_LOG(INFO,
3487                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3488                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3489                         PMD_DRV_LOG(INFO,
3490                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3491                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3492                         PMD_DRV_LOG(INFO,
3493                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3494                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3495                         PMD_DRV_LOG(INFO,
3496                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3497         }
3498
3499         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3500                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3501                 PMD_DRV_LOG(INFO,
3502                             "ERROR: FATAL parity attention set4 0x%08x",
3503                             (uint32_t) (attn &
3504                                         (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3505                                          |
3506                                          AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3507         }
3508 }
3509
3510 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3511 {
3512         int port = SC_PORT(sc);
3513
3514         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3515 }
3516
3517 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3518 {
3519         int port = SC_PORT(sc);
3520
3521         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3522 }
3523
3524 /*
3525  * called due to MCP event (on pmf):
3526  *   reread new bandwidth configuration
3527  *   configure FW
3528  *   notify others function about the change
3529  */
3530 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3531 {
3532         if (sc->link_vars.link_up) {
3533                 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3534                 bnx2x_link_sync_notify(sc);
3535         }
3536
3537         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3538 }
3539
3540 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3541 {
3542         bnx2x_config_mf_bw(sc);
3543         bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3544 }
3545
3546 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3547 {
3548         bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3549 }
3550
3551 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3552
3553 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3554 {
3555         struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3556
3557         strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3558                 ETH_STAT_INFO_VERSION_LEN);
3559
3560         sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3561                                               DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3562                                               ether_stat->mac_local + MAC_PAD,
3563                                               MAC_PAD, ETH_ALEN);
3564
3565         ether_stat->mtu_size = sc->mtu;
3566
3567         ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3568         ether_stat->promiscuous_mode = 0;       // (flags & PROMISC) ? 1 : 0;
3569
3570         ether_stat->txq_size = sc->tx_ring_size;
3571         ether_stat->rxq_size = sc->rx_ring_size;
3572 }
3573
3574 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3575 {
3576         enum drv_info_opcode op_code;
3577         uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3578
3579         /* if drv_info version supported by MFW doesn't match - send NACK */
3580         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3581                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3582                 return;
3583         }
3584
3585         op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3586                    DRV_INFO_CONTROL_OP_CODE_SHIFT);
3587
3588         memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3589
3590         switch (op_code) {
3591         case ETH_STATS_OPCODE:
3592                 bnx2x_drv_info_ether_stat(sc);
3593                 break;
3594         case FCOE_STATS_OPCODE:
3595         case ISCSI_STATS_OPCODE:
3596         default:
3597                 /* if op code isn't supported - send NACK */
3598                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3599                 return;
3600         }
3601
3602         /*
3603          * If we got drv_info attn from MFW then these fields are defined in
3604          * shmem2 for sure
3605          */
3606         SHMEM2_WR(sc, drv_info_host_addr_lo,
3607                   U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3608         SHMEM2_WR(sc, drv_info_host_addr_hi,
3609                   U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3610
3611         bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3612 }
3613
3614 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3615 {
3616         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3617 /*
3618  * This is the only place besides the function initialization
3619  * where the sc->flags can change so it is done without any
3620  * locks
3621  */
3622                 if (sc->devinfo.
3623                     mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3624                         PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
3625                         sc->flags |= BNX2X_MF_FUNC_DIS;
3626                         bnx2x_e1h_disable(sc);
3627                 } else {
3628                         PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
3629                         sc->flags &= ~BNX2X_MF_FUNC_DIS;
3630                         bnx2x_e1h_enable(sc);
3631                 }
3632                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3633         }
3634
3635         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3636                 bnx2x_config_mf_bw(sc);
3637                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3638         }
3639
3640         /* Report results to MCP */
3641         if (dcc_event)
3642                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3643         else
3644                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3645 }
3646
3647 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3648 {
3649         int port = SC_PORT(sc);
3650         uint32_t val;
3651
3652         sc->port.pmf = 1;
3653
3654         /*
3655          * We need the mb() to ensure the ordering between the writing to
3656          * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3657          */
3658         mb();
3659
3660         /* enable nig attention */
3661         val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3662         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3663                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3664                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3665         } else if (!CHIP_IS_E1x(sc)) {
3666                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3667                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3668         }
3669
3670         bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3671 }
3672
3673 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3674 {
3675         char last_idx;
3676         int i, rc = 0;
3677         __rte_unused uint32_t row0, row1, row2, row3;
3678
3679         /* XSTORM */
3680         last_idx =
3681             REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3682         if (last_idx)
3683                 PMD_DRV_LOG(ERR, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3684
3685         /* print the asserts */
3686         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3687
3688                 row0 =
3689                     REG_RD(sc,
3690                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3691                 row1 =
3692                     REG_RD(sc,
3693                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3694                            4);
3695                 row2 =
3696                     REG_RD(sc,
3697                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3698                            8);
3699                 row3 =
3700                     REG_RD(sc,
3701                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3702                            12);
3703
3704                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3705                         PMD_DRV_LOG(ERR,
3706                                     "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3707                                     i, row3, row2, row1, row0);
3708                         rc++;
3709                 } else {
3710                         break;
3711                 }
3712         }
3713
3714         /* TSTORM */
3715         last_idx =
3716             REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3717         if (last_idx) {
3718                 PMD_DRV_LOG(ERR, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3719         }
3720
3721         /* print the asserts */
3722         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3723
3724                 row0 =
3725                     REG_RD(sc,
3726                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3727                 row1 =
3728                     REG_RD(sc,
3729                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3730                            4);
3731                 row2 =
3732                     REG_RD(sc,
3733                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3734                            8);
3735                 row3 =
3736                     REG_RD(sc,
3737                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3738                            12);
3739
3740                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3741                         PMD_DRV_LOG(ERR,
3742                                     "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3743                                     i, row3, row2, row1, row0);
3744                         rc++;
3745                 } else {
3746                         break;
3747                 }
3748         }
3749
3750         /* CSTORM */
3751         last_idx =
3752             REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3753         if (last_idx) {
3754                 PMD_DRV_LOG(ERR, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3755         }
3756
3757         /* print the asserts */
3758         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3759
3760                 row0 =
3761                     REG_RD(sc,
3762                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3763                 row1 =
3764                     REG_RD(sc,
3765                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3766                            4);
3767                 row2 =
3768                     REG_RD(sc,
3769                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3770                            8);
3771                 row3 =
3772                     REG_RD(sc,
3773                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3774                            12);
3775
3776                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3777                         PMD_DRV_LOG(ERR,
3778                                     "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3779                                     i, row3, row2, row1, row0);
3780                         rc++;
3781                 } else {
3782                         break;
3783                 }
3784         }
3785
3786         /* USTORM */
3787         last_idx =
3788             REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3789         if (last_idx) {
3790                 PMD_DRV_LOG(ERR, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3791         }
3792
3793         /* print the asserts */
3794         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3795
3796                 row0 =
3797                     REG_RD(sc,
3798                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3799                 row1 =
3800                     REG_RD(sc,
3801                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3802                            4);
3803                 row2 =
3804                     REG_RD(sc,
3805                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3806                            8);
3807                 row3 =
3808                     REG_RD(sc,
3809                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3810                            12);
3811
3812                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3813                         PMD_DRV_LOG(ERR,
3814                                     "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3815                                     i, row3, row2, row1, row0);
3816                         rc++;
3817                 } else {
3818                         break;
3819                 }
3820         }
3821
3822         return rc;
3823 }
3824
3825 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3826 {
3827         int func = SC_FUNC(sc);
3828         uint32_t val;
3829
3830         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3831
3832                 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3833
3834                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3835                         bnx2x_read_mf_cfg(sc);
3836                         sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3837                             MFCFG_RD(sc,
3838                                      func_mf_config[SC_ABS_FUNC(sc)].config);
3839                         val =
3840                             SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3841
3842                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3843                                 bnx2x_dcc_event(sc,
3844                                               (val &
3845                                                DRV_STATUS_DCC_EVENT_MASK));
3846
3847                         if (val & DRV_STATUS_SET_MF_BW)
3848                                 bnx2x_set_mf_bw(sc);
3849
3850                         if (val & DRV_STATUS_DRV_INFO_REQ)
3851                                 bnx2x_handle_drv_info_req(sc);
3852
3853                         if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3854                                 bnx2x_pmf_update(sc);
3855
3856                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3857                                 bnx2x_handle_eee_event(sc);
3858
3859                         if (sc->link_vars.periodic_flags &
3860                             ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3861                                 /* sync with link */
3862                                 sc->link_vars.periodic_flags &=
3863                                     ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3864                                 if (IS_MF(sc)) {
3865                                         bnx2x_link_sync_notify(sc);
3866                                 }
3867                                 bnx2x_link_report(sc);
3868                         }
3869
3870                         /*
3871                          * Always call it here: bnx2x_link_report() will
3872                          * prevent the link indication duplication.
3873                          */
3874                         bnx2x_link_status_update(sc);
3875
3876                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3877
3878                         PMD_DRV_LOG(ERR, "MC assert!");
3879                         bnx2x_mc_assert(sc);
3880                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3881                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3882                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3883                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3884                         rte_panic("MC assert!");
3885
3886                 } else if (attn & BNX2X_MCP_ASSERT) {
3887
3888                         PMD_DRV_LOG(ERR, "MCP assert!");
3889                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3890
3891                 } else {
3892                         PMD_DRV_LOG(ERR,
3893                                     "Unknown HW assert! (attn 0x%08x)", attn);
3894                 }
3895         }
3896
3897         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3898                 PMD_DRV_LOG(ERR, "LATCHED attention 0x%08x (masked)", attn);
3899                 if (attn & BNX2X_GRC_TIMEOUT) {
3900                         val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3901                         PMD_DRV_LOG(ERR, "GRC time-out 0x%08x", val);
3902                 }
3903                 if (attn & BNX2X_GRC_RSV) {
3904                         val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3905                         PMD_DRV_LOG(ERR, "GRC reserved 0x%08x", val);
3906                 }
3907                 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3908         }
3909 }
3910
3911 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3912 {
3913         int port = SC_PORT(sc);
3914         int reg_offset;
3915         uint32_t val0, mask0, val1, mask1;
3916         uint32_t val;
3917
3918         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3919                 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3920                 PMD_DRV_LOG(ERR, "CFC hw attention 0x%08x", val);
3921 /* CFC error attention */
3922                 if (val & 0x2) {
3923                         PMD_DRV_LOG(ERR, "FATAL error from CFC");
3924                 }
3925         }
3926
3927         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3928                 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3929                 PMD_DRV_LOG(ERR, "PXP hw attention-0 0x%08x", val);
3930 /* RQ_USDMDP_FIFO_OVERFLOW */
3931                 if (val & 0x18000) {
3932                         PMD_DRV_LOG(ERR, "FATAL error from PXP");
3933                 }
3934
3935                 if (!CHIP_IS_E1x(sc)) {
3936                         val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3937                         PMD_DRV_LOG(ERR, "PXP hw attention-1 0x%08x", val);
3938                 }
3939         }
3940 #define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3941 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3942
3943         if (attn & AEU_PXP2_HW_INT_BIT) {
3944 /*  CQ47854 workaround do not panic on
3945  *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3946  */
3947                 if (!CHIP_IS_E1x(sc)) {
3948                         mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3949                         val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3950                         mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3951                         val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3952                         /*
3953                          * If the olny PXP2_EOP_ERROR_BIT is set in
3954                          * STS0 and STS1 - clear it
3955                          *
3956                          * probably we lose additional attentions between
3957                          * STS0 and STS_CLR0, in this case user will not
3958                          * be notified about them
3959                          */
3960                         if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3961                             !(val1 & mask1))
3962                                 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3963
3964                         /* print the register, since no one can restore it */
3965                         PMD_DRV_LOG(ERR,
3966                                     "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3967
3968                         /*
3969                          * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3970                          * then notify
3971                          */
3972                         if (val0 & PXP2_EOP_ERROR_BIT) {
3973                                 PMD_DRV_LOG(ERR, "PXP2_WR_PGLUE_EOP_ERROR");
3974
3975                                 /*
3976                                  * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3977                                  * set then clear attention from PXP2 block without panic
3978                                  */
3979                                 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3980                                     ((val1 & mask1) == 0))
3981                                         attn &= ~AEU_PXP2_HW_INT_BIT;
3982                         }
3983                 }
3984         }
3985
3986         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3987                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3988                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3989
3990                 val = REG_RD(sc, reg_offset);
3991                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3992                 REG_WR(sc, reg_offset, val);
3993
3994                 PMD_DRV_LOG(ERR,
3995                             "FATAL HW block attention set2 0x%x",
3996                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
3997                 rte_panic("HW block attention set2");
3998         }
3999 }
4000
4001 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
4002 {
4003         int port = SC_PORT(sc);
4004         int reg_offset;
4005         uint32_t val;
4006
4007         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4008                 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
4009                 PMD_DRV_LOG(ERR, "DB hw attention 0x%08x", val);
4010 /* DORQ discard attention */
4011                 if (val & 0x2) {
4012                         PMD_DRV_LOG(ERR, "FATAL error from DORQ");
4013                 }
4014         }
4015
4016         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4017                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4018                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4019
4020                 val = REG_RD(sc, reg_offset);
4021                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4022                 REG_WR(sc, reg_offset, val);
4023
4024                 PMD_DRV_LOG(ERR,
4025                             "FATAL HW block attention set1 0x%08x",
4026                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4027                 rte_panic("HW block attention set1");
4028         }
4029 }
4030
4031 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4032 {
4033         int port = SC_PORT(sc);
4034         int reg_offset;
4035         uint32_t val;
4036
4037         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4038             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4039
4040         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4041                 val = REG_RD(sc, reg_offset);
4042                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4043                 REG_WR(sc, reg_offset, val);
4044
4045                 PMD_DRV_LOG(WARNING, "SPIO5 hw attention");
4046
4047 /* Fan failure attention */
4048                 elink_hw_reset_phy(&sc->link_params);
4049                 bnx2x_fan_failure(sc);
4050         }
4051
4052         if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4053                 elink_handle_module_detect_int(&sc->link_params);
4054         }
4055
4056         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4057                 val = REG_RD(sc, reg_offset);
4058                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4059                 REG_WR(sc, reg_offset, val);
4060
4061                 rte_panic("FATAL HW block attention set0 0x%lx",
4062                           (attn & HW_INTERRUT_ASSERT_SET_0));
4063         }
4064 }
4065
4066 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4067 {
4068         struct attn_route attn;
4069         struct attn_route *group_mask;
4070         int port = SC_PORT(sc);
4071         int index;
4072         uint32_t reg_addr;
4073         uint32_t val;
4074         uint32_t aeu_mask;
4075         uint8_t global = FALSE;
4076
4077         /*
4078          * Need to take HW lock because MCP or other port might also
4079          * try to handle this event.
4080          */
4081         bnx2x_acquire_alr(sc);
4082
4083         if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4084                 sc->recovery_state = BNX2X_RECOVERY_INIT;
4085
4086 /* disable HW interrupts */
4087                 bnx2x_int_disable(sc);
4088                 bnx2x_release_alr(sc);
4089                 return;
4090         }
4091
4092         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4093         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4094         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4095         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4096         if (!CHIP_IS_E1x(sc)) {
4097                 attn.sig[4] =
4098                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4099         } else {
4100                 attn.sig[4] = 0;
4101         }
4102
4103         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4104                 if (deasserted & (1 << index)) {
4105                         group_mask = &sc->attn_group[index];
4106
4107                         bnx2x_attn_int_deasserted4(sc,
4108                                                  attn.
4109                                                  sig[4] & group_mask->sig[4]);
4110                         bnx2x_attn_int_deasserted3(sc,
4111                                                  attn.
4112                                                  sig[3] & group_mask->sig[3]);
4113                         bnx2x_attn_int_deasserted1(sc,
4114                                                  attn.
4115                                                  sig[1] & group_mask->sig[1]);
4116                         bnx2x_attn_int_deasserted2(sc,
4117                                                  attn.
4118                                                  sig[2] & group_mask->sig[2]);
4119                         bnx2x_attn_int_deasserted0(sc,
4120                                                  attn.
4121                                                  sig[0] & group_mask->sig[0]);
4122                 }
4123         }
4124
4125         bnx2x_release_alr(sc);
4126
4127         if (sc->devinfo.int_block == INT_BLOCK_HC) {
4128                 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4129                             COMMAND_REG_ATTN_BITS_CLR);
4130         } else {
4131                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4132         }
4133
4134         val = ~deasserted;
4135         PMD_DRV_LOG(DEBUG,
4136                     "about to mask 0x%08x at %s addr 0x%08x", val,
4137                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4138                     reg_addr);
4139         REG_WR(sc, reg_addr, val);
4140
4141         if (~sc->attn_state & deasserted) {
4142                 PMD_DRV_LOG(ERR, "IGU error");
4143         }
4144
4145         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4146             MISC_REG_AEU_MASK_ATTN_FUNC_0;
4147
4148         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4149
4150         aeu_mask = REG_RD(sc, reg_addr);
4151
4152         aeu_mask |= (deasserted & 0x3ff);
4153
4154         REG_WR(sc, reg_addr, aeu_mask);
4155         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4156
4157         sc->attn_state &= ~deasserted;
4158 }
4159
4160 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4161 {
4162         /* read local copy of bits */
4163         uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4164         uint32_t attn_ack =
4165             le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4166         uint32_t attn_state = sc->attn_state;
4167
4168         /* look for changed bits */
4169         uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4170         uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4171
4172         PMD_DRV_LOG(DEBUG,
4173                     "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4174                     attn_bits, attn_ack, asserted, deasserted);
4175
4176         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4177                 PMD_DRV_LOG(ERR, "BAD attention state");
4178         }
4179
4180         /* handle bits that were raised */
4181         if (asserted) {
4182                 bnx2x_attn_int_asserted(sc, asserted);
4183         }
4184
4185         if (deasserted) {
4186                 bnx2x_attn_int_deasserted(sc, deasserted);
4187         }
4188 }
4189
4190 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4191 {
4192         struct host_sp_status_block *def_sb = sc->def_sb;
4193         uint16_t rc = 0;
4194
4195         mb();                   /* status block is written to by the chip */
4196
4197         if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4198                 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4199                 rc |= BNX2X_DEF_SB_ATT_IDX;
4200         }
4201
4202         if (sc->def_idx != def_sb->sp_sb.running_index) {
4203                 sc->def_idx = def_sb->sp_sb.running_index;
4204                 rc |= BNX2X_DEF_SB_IDX;
4205         }
4206
4207         mb();
4208
4209         return rc;
4210 }
4211
4212 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4213                                                           uint32_t cid)
4214 {
4215         return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4216 }
4217
4218 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4219 {
4220         struct ecore_mcast_ramrod_params rparam;
4221         int rc;
4222
4223         memset(&rparam, 0, sizeof(rparam));
4224
4225         rparam.mcast_obj = &sc->mcast_obj;
4226
4227         /* clear pending state for the last command */
4228         sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4229
4230         /* if there are pending mcast commands - send them */
4231         if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4232                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4233                 if (rc < 0) {
4234                         PMD_DRV_LOG(INFO,
4235                                     "Failed to send pending mcast commands (%d)",
4236                                     rc);
4237                 }
4238         }
4239 }
4240
4241 static void
4242 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4243 {
4244         unsigned long ramrod_flags = 0;
4245         int rc = 0;
4246         uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4247         struct ecore_vlan_mac_obj *vlan_mac_obj;
4248
4249         /* always push next commands out, don't wait here */
4250         bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4251
4252         switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4253         case ECORE_FILTER_MAC_PENDING:
4254                 PMD_DRV_LOG(DEBUG, "Got SETUP_MAC completions");
4255                 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4256                 break;
4257
4258         case ECORE_FILTER_MCAST_PENDING:
4259                 PMD_DRV_LOG(DEBUG, "Got SETUP_MCAST completions");
4260                 bnx2x_handle_mcast_eqe(sc);
4261                 return;
4262
4263         default:
4264                 PMD_DRV_LOG(NOTICE, "Unsupported classification command: %d",
4265                             elem->message.data.eth_event.echo);
4266                 return;
4267         }
4268
4269         rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4270
4271         if (rc < 0) {
4272                 PMD_DRV_LOG(NOTICE, "Failed to schedule new commands (%d)", rc);
4273         } else if (rc > 0) {
4274                 PMD_DRV_LOG(DEBUG, "Scheduled next pending commands...");
4275         }
4276 }
4277
4278 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4279 {
4280         bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4281
4282         /* send rx_mode command again if was requested */
4283         if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4284                 bnx2x_set_storm_rx_mode(sc);
4285         }
4286 }
4287
4288 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4289 {
4290         storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4291         wmb();                  /* keep prod updates ordered */
4292 }
4293
4294 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4295 {
4296         uint16_t hw_cons, sw_cons, sw_prod;
4297         union event_ring_elem *elem;
4298         uint8_t echo;
4299         uint32_t cid;
4300         uint8_t opcode;
4301         int spqe_cnt = 0;
4302         struct ecore_queue_sp_obj *q_obj;
4303         struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4304         struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4305
4306         hw_cons = le16toh(*sc->eq_cons_sb);
4307
4308         /*
4309          * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4310          * when we get to the next-page we need to adjust so the loop
4311          * condition below will be met. The next element is the size of a
4312          * regular element and hence incrementing by 1
4313          */
4314         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4315                 hw_cons++;
4316         }
4317
4318         /*
4319          * This function may never run in parallel with itself for a
4320          * specific sc and no need for a read memory barrier here.
4321          */
4322         sw_cons = sc->eq_cons;
4323         sw_prod = sc->eq_prod;
4324
4325         for (;
4326              sw_cons != hw_cons;
4327              sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4328
4329                 elem = &sc->eq[EQ_DESC(sw_cons)];
4330
4331 /* elem CID originates from FW, actually LE */
4332                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4333                 opcode = elem->message.opcode;
4334
4335 /* handle eq element */
4336                 switch (opcode) {
4337                 case EVENT_RING_OPCODE_STAT_QUERY:
4338                         PMD_DRV_LOG(DEBUG, "got statistics completion event %d",
4339                                     sc->stats_comp++);
4340                         /* nothing to do with stats comp */
4341                         goto next_spqe;
4342
4343                 case EVENT_RING_OPCODE_CFC_DEL:
4344                         /* handle according to cid range */
4345                         /* we may want to verify here that the sc state is HALTING */
4346                         PMD_DRV_LOG(DEBUG, "got delete ramrod for MULTI[%d]",
4347                                     cid);
4348                         q_obj = bnx2x_cid_to_q_obj(sc, cid);
4349                         if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4350                                 break;
4351                         }
4352                         goto next_spqe;
4353
4354                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4355                         PMD_DRV_LOG(DEBUG, "got STOP TRAFFIC");
4356                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4357                                 break;
4358                         }
4359                         goto next_spqe;
4360
4361                 case EVENT_RING_OPCODE_START_TRAFFIC:
4362                         PMD_DRV_LOG(DEBUG, "got START TRAFFIC");
4363                         if (f_obj->complete_cmd
4364                             (sc, f_obj, ECORE_F_CMD_TX_START)) {
4365                                 break;
4366                         }
4367                         goto next_spqe;
4368
4369                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4370                         echo = elem->message.data.function_update_event.echo;
4371                         if (echo == SWITCH_UPDATE) {
4372                                 PMD_DRV_LOG(DEBUG,
4373                                             "got FUNC_SWITCH_UPDATE ramrod");
4374                                 if (f_obj->complete_cmd(sc, f_obj,
4375                                                         ECORE_F_CMD_SWITCH_UPDATE))
4376                                 {
4377                                         break;
4378                                 }
4379                         } else {
4380                                 PMD_DRV_LOG(DEBUG,
4381                                             "AFEX: ramrod completed FUNCTION_UPDATE");
4382                                 f_obj->complete_cmd(sc, f_obj,
4383                                                     ECORE_F_CMD_AFEX_UPDATE);
4384                         }
4385                         goto next_spqe;
4386
4387                 case EVENT_RING_OPCODE_FORWARD_SETUP:
4388                         q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4389                         if (q_obj->complete_cmd(sc, q_obj,
4390                                                 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4391                                 break;
4392                         }
4393                         goto next_spqe;
4394
4395                 case EVENT_RING_OPCODE_FUNCTION_START:
4396                         PMD_DRV_LOG(DEBUG, "got FUNC_START ramrod");
4397                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4398                                 break;
4399                         }
4400                         goto next_spqe;
4401
4402                 case EVENT_RING_OPCODE_FUNCTION_STOP:
4403                         PMD_DRV_LOG(DEBUG, "got FUNC_STOP ramrod");
4404                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4405                                 break;
4406                         }
4407                         goto next_spqe;
4408                 }
4409
4410                 switch (opcode | sc->state) {
4411                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4412                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4413                         cid =
4414                             elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4415                         PMD_DRV_LOG(DEBUG, "got RSS_UPDATE ramrod. CID %d",
4416                                     cid);
4417                         rss_raw->clear_pending(rss_raw);
4418                         break;
4419
4420                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4421                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4422                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4423                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4424                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4425                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4426                         PMD_DRV_LOG(DEBUG,
4427                                     "got (un)set mac ramrod");
4428                         bnx2x_handle_classification_eqe(sc, elem);
4429                         break;
4430
4431                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4432                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4433                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4434                         PMD_DRV_LOG(DEBUG,
4435                                     "got mcast ramrod");
4436                         bnx2x_handle_mcast_eqe(sc);
4437                         break;
4438
4439                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4440                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4441                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4442                         PMD_DRV_LOG(DEBUG,
4443                                     "got rx_mode ramrod");
4444                         bnx2x_handle_rx_mode_eqe(sc);
4445                         break;
4446
4447                 default:
4448                         /* unknown event log error and continue */
4449                         PMD_DRV_LOG(INFO, "Unknown EQ event %d, sc->state 0x%x",
4450                                     elem->message.opcode, sc->state);
4451                 }
4452
4453 next_spqe:
4454                 spqe_cnt++;
4455         }                       /* for */
4456
4457         mb();
4458         atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4459
4460         sc->eq_cons = sw_cons;
4461         sc->eq_prod = sw_prod;
4462
4463         /* make sure that above mem writes were issued towards the memory */
4464         wmb();
4465
4466         /* update producer */
4467         bnx2x_update_eq_prod(sc, sc->eq_prod);
4468 }
4469
4470 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4471 {
4472         uint16_t status;
4473         int rc = 0;
4474
4475         /* what work needs to be performed? */
4476         status = bnx2x_update_dsb_idx(sc);
4477
4478         /* HW attentions */
4479         if (status & BNX2X_DEF_SB_ATT_IDX) {
4480                 PMD_DRV_LOG(DEBUG, "---> ATTN INTR <---");
4481                 bnx2x_attn_int(sc);
4482                 status &= ~BNX2X_DEF_SB_ATT_IDX;
4483                 rc = 1;
4484         }
4485
4486         /* SP events: STAT_QUERY and others */
4487         if (status & BNX2X_DEF_SB_IDX) {
4488 /* handle EQ completions */
4489                 PMD_DRV_LOG(DEBUG, "---> EQ INTR <---");
4490                 bnx2x_eq_int(sc);
4491                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4492                            le16toh(sc->def_idx), IGU_INT_NOP, 1);
4493                 status &= ~BNX2X_DEF_SB_IDX;
4494         }
4495
4496         /* if status is non zero then something went wrong */
4497         if (unlikely(status)) {
4498                 PMD_DRV_LOG(INFO,
4499                             "Got an unknown SP interrupt! (0x%04x)", status);
4500         }
4501
4502         /* ack status block only if something was actually handled */
4503         bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4504                    le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4505
4506         return rc;
4507 }
4508
4509 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4510 {
4511         struct bnx2x_softc *sc = fp->sc;
4512         uint8_t more_rx = FALSE;
4513
4514         /* update the fastpath index */
4515         bnx2x_update_fp_sb_idx(fp);
4516
4517         if (scan_fp) {
4518                 if (bnx2x_has_rx_work(fp)) {
4519                         more_rx = bnx2x_rxeof(sc, fp);
4520                 }
4521
4522                 if (more_rx) {
4523                         /* still more work to do */
4524                         bnx2x_handle_fp_tq(fp, scan_fp);
4525                         return;
4526                 }
4527         }
4528
4529         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4530                    le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4531 }
4532
4533 /*
4534  * Legacy interrupt entry point.
4535  *
4536  * Verifies that the controller generated the interrupt and
4537  * then calls a separate routine to handle the various
4538  * interrupt causes: link, RX, and TX.
4539  */
4540 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4541 {
4542         struct bnx2x_fastpath *fp;
4543         uint32_t status, mask;
4544         int i, rc = 0;
4545
4546         /*
4547          * 0 for ustorm, 1 for cstorm
4548          * the bits returned from ack_int() are 0-15
4549          * bit 0 = attention status block
4550          * bit 1 = fast path status block
4551          * a mask of 0x2 or more = tx/rx event
4552          * a mask of 1 = slow path event
4553          */
4554
4555         status = bnx2x_ack_int(sc);
4556
4557         /* the interrupt is not for us */
4558         if (unlikely(status == 0)) {
4559                 return 0;
4560         }
4561
4562         PMD_DRV_LOG(DEBUG, "Interrupt status 0x%04x", status);
4563         //bnx2x_dump_status_block(sc);
4564
4565         FOR_EACH_ETH_QUEUE(sc, i) {
4566                 fp = &sc->fp[i];
4567                 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4568                 if (status & mask) {
4569                         bnx2x_handle_fp_tq(fp, scan_fp);
4570                         status &= ~mask;
4571                 }
4572         }
4573
4574         if (unlikely(status & 0x1)) {
4575                 rc = bnx2x_handle_sp_tq(sc);
4576                 status &= ~0x1;
4577         }
4578
4579         if (unlikely(status)) {
4580                 PMD_DRV_LOG(WARNING,
4581                             "Unexpected fastpath status (0x%08x)!", status);
4582         }
4583
4584         return rc;
4585 }
4586
4587 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4588 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4589 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4590 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4591 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4592 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4593 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4594 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4595 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4596
4597 static struct
4598 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4599         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4600         .init_hw_cmn = bnx2x_init_hw_common,
4601         .init_hw_port = bnx2x_init_hw_port,
4602         .init_hw_func = bnx2x_init_hw_func,
4603
4604         .reset_hw_cmn = bnx2x_reset_common,
4605         .reset_hw_port = bnx2x_reset_port,
4606         .reset_hw_func = bnx2x_reset_func,
4607
4608         .init_fw = bnx2x_init_firmware,
4609         .release_fw = bnx2x_release_firmware,
4610 };
4611
4612 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4613 {
4614         sc->dmae_ready = 0;
4615
4616         PMD_INIT_FUNC_TRACE();
4617
4618         ecore_init_func_obj(sc,
4619                             &sc->func_obj,
4620                             BNX2X_SP(sc, func_rdata),
4621                             (phys_addr_t)BNX2X_SP_MAPPING(sc, func_rdata),
4622                             BNX2X_SP(sc, func_afex_rdata),
4623                             (phys_addr_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4624                             &bnx2x_func_sp_drv);
4625 }
4626
4627 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4628 {
4629         struct ecore_func_state_params func_params = { NULL };
4630         int rc;
4631
4632         PMD_INIT_FUNC_TRACE();
4633
4634         /* prepare the parameters for function state transitions */
4635         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4636
4637         func_params.f_obj = &sc->func_obj;
4638         func_params.cmd = ECORE_F_CMD_HW_INIT;
4639
4640         func_params.params.hw_init.load_phase = load_code;
4641
4642         /*
4643          * Via a plethora of function pointers, we will eventually reach
4644          * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4645          */
4646         rc = ecore_func_state_change(sc, &func_params);
4647
4648         return rc;
4649 }
4650
4651 static void
4652 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4653 {
4654         uint32_t i;
4655
4656         if (!(len % 4) && !(addr % 4)) {
4657                 for (i = 0; i < len; i += 4) {
4658                         REG_WR(sc, (addr + i), fill);
4659                 }
4660         } else {
4661                 for (i = 0; i < len; i++) {
4662                         REG_WR8(sc, (addr + i), fill);
4663                 }
4664         }
4665 }
4666
4667 /* writes FP SP data to FW - data_size in dwords */
4668 static void
4669 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4670                   uint32_t data_size)
4671 {
4672         uint32_t index;
4673
4674         for (index = 0; index < data_size; index++) {
4675                 REG_WR(sc,
4676                        (BAR_CSTRORM_INTMEM +
4677                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4678                         (sizeof(uint32_t) * index)), *(sb_data_p + index));
4679         }
4680 }
4681
4682 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4683 {
4684         struct hc_status_block_data_e2 sb_data_e2;
4685         struct hc_status_block_data_e1x sb_data_e1x;
4686         uint32_t *sb_data_p;
4687         uint32_t data_size = 0;
4688
4689         if (!CHIP_IS_E1x(sc)) {
4690                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4691                 sb_data_e2.common.state = SB_DISABLED;
4692                 sb_data_e2.common.p_func.vf_valid = FALSE;
4693                 sb_data_p = (uint32_t *) & sb_data_e2;
4694                 data_size = (sizeof(struct hc_status_block_data_e2) /
4695                              sizeof(uint32_t));
4696         } else {
4697                 memset(&sb_data_e1x, 0,
4698                        sizeof(struct hc_status_block_data_e1x));
4699                 sb_data_e1x.common.state = SB_DISABLED;
4700                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4701                 sb_data_p = (uint32_t *) & sb_data_e1x;
4702                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4703                              sizeof(uint32_t));
4704         }
4705
4706         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4707
4708         bnx2x_fill(sc,
4709                  (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4710                  CSTORM_STATUS_BLOCK_SIZE);
4711         bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4712                  0, CSTORM_SYNC_BLOCK_SIZE);
4713 }
4714
4715 static void
4716 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4717                   struct hc_sp_status_block_data *sp_sb_data)
4718 {
4719         uint32_t i;
4720
4721         for (i = 0;
4722              i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4723              i++) {
4724                 REG_WR(sc,
4725                        (BAR_CSTRORM_INTMEM +
4726                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4727                         (i * sizeof(uint32_t))),
4728                        *((uint32_t *) sp_sb_data + i));
4729         }
4730 }
4731
4732 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4733 {
4734         struct hc_sp_status_block_data sp_sb_data;
4735
4736         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4737
4738         sp_sb_data.state = SB_DISABLED;
4739         sp_sb_data.p_func.vf_valid = FALSE;
4740
4741         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4742
4743         bnx2x_fill(sc,
4744                  (BAR_CSTRORM_INTMEM +
4745                   CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4746                  0, CSTORM_SP_STATUS_BLOCK_SIZE);
4747         bnx2x_fill(sc,
4748                  (BAR_CSTRORM_INTMEM +
4749                   CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4750                  0, CSTORM_SP_SYNC_BLOCK_SIZE);
4751 }
4752
4753 static void
4754 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4755                              int igu_seg_id)
4756 {
4757         hc_sm->igu_sb_id = igu_sb_id;
4758         hc_sm->igu_seg_id = igu_seg_id;
4759         hc_sm->timer_value = 0xFF;
4760         hc_sm->time_to_expire = 0xFFFFFFFF;
4761 }
4762
4763 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4764 {
4765         /* zero out state machine indices */
4766
4767         /* rx indices */
4768         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4769
4770         /* tx indices */
4771         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4772         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4773         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4774         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4775
4776         /* map indices */
4777
4778         /* rx indices */
4779         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4780             (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4781
4782         /* tx indices */
4783         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4784             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4785         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4786             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4787         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4788             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4789         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4790             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4791 }
4792
4793 static void
4794 bnx2x_init_sb(struct bnx2x_softc *sc, phys_addr_t busaddr, int vfid,
4795             uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4796 {
4797         struct hc_status_block_data_e2 sb_data_e2;
4798         struct hc_status_block_data_e1x sb_data_e1x;
4799         struct hc_status_block_sm *hc_sm_p;
4800         uint32_t *sb_data_p;
4801         int igu_seg_id;
4802         int data_size;
4803
4804         if (CHIP_INT_MODE_IS_BC(sc)) {
4805                 igu_seg_id = HC_SEG_ACCESS_NORM;
4806         } else {
4807                 igu_seg_id = IGU_SEG_ACCESS_NORM;
4808         }
4809
4810         bnx2x_zero_fp_sb(sc, fw_sb_id);
4811
4812         if (!CHIP_IS_E1x(sc)) {
4813                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4814                 sb_data_e2.common.state = SB_ENABLED;
4815                 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4816                 sb_data_e2.common.p_func.vf_id = vfid;
4817                 sb_data_e2.common.p_func.vf_valid = vf_valid;
4818                 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4819                 sb_data_e2.common.same_igu_sb_1b = TRUE;
4820                 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4821                 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4822                 hc_sm_p = sb_data_e2.common.state_machine;
4823                 sb_data_p = (uint32_t *) & sb_data_e2;
4824                 data_size = (sizeof(struct hc_status_block_data_e2) /
4825                              sizeof(uint32_t));
4826                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4827         } else {
4828                 memset(&sb_data_e1x, 0,
4829                        sizeof(struct hc_status_block_data_e1x));
4830                 sb_data_e1x.common.state = SB_ENABLED;
4831                 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4832                 sb_data_e1x.common.p_func.vf_id = 0xff;
4833                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4834                 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4835                 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4836                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4837                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4838                 hc_sm_p = sb_data_e1x.common.state_machine;
4839                 sb_data_p = (uint32_t *) & sb_data_e1x;
4840                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4841                              sizeof(uint32_t));
4842                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4843         }
4844
4845         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4846         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4847
4848         /* write indices to HW - PCI guarantees endianity of regpairs */
4849         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4850 }
4851
4852 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4853 {
4854         if (CHIP_IS_E1x(fp->sc)) {
4855                 return (fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H);
4856         } else {
4857                 return (fp->cl_id);
4858         }
4859 }
4860
4861 static uint32_t
4862 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4863 {
4864         uint32_t offset = BAR_USTRORM_INTMEM;
4865
4866         if (IS_VF(sc)) {
4867                 return (PXP_VF_ADDR_USDM_QUEUES_START +
4868                         (sc->acquire_resp.resc.hw_qid[fp->index] *
4869                          sizeof(struct ustorm_queue_zone_data)));
4870         } else if (!CHIP_IS_E1x(sc)) {
4871                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4872         } else {
4873                 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4874         }
4875
4876         return offset;
4877 }
4878
4879 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4880 {
4881         struct bnx2x_fastpath *fp = &sc->fp[idx];
4882         uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4883         unsigned long q_type = 0;
4884         int cos;
4885
4886         fp->sc = sc;
4887         fp->index = idx;
4888
4889         fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4890         fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4891
4892         if (CHIP_IS_E1x(sc))
4893                 fp->cl_id = SC_L_ID(sc) + idx;
4894         else
4895 /* want client ID same as IGU SB ID for non-E1 */
4896                 fp->cl_id = fp->igu_sb_id;
4897         fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4898
4899         /* setup sb indices */
4900         if (!CHIP_IS_E1x(sc)) {
4901                 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4902                 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4903         } else {
4904                 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4905                 fp->sb_running_index =
4906                     fp->status_block.e1x_sb->sb.running_index;
4907         }
4908
4909         /* init shortcut */
4910         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4911
4912         fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4913
4914         for (cos = 0; cos < sc->max_cos; cos++) {
4915                 cids[cos] = idx;
4916         }
4917         fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4918
4919         /* nothing more for a VF to do */
4920         if (IS_VF(sc)) {
4921                 return;
4922         }
4923
4924         bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4925                     fp->fw_sb_id, fp->igu_sb_id);
4926
4927         bnx2x_update_fp_sb_idx(fp);
4928
4929         /* Configure Queue State object */
4930         bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4931         bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4932
4933         ecore_init_queue_obj(sc,
4934                              &sc->sp_objs[idx].q_obj,
4935                              fp->cl_id,
4936                              cids,
4937                              sc->max_cos,
4938                              SC_FUNC(sc),
4939                              BNX2X_SP(sc, q_rdata),
4940                              (phys_addr_t)BNX2X_SP_MAPPING(sc, q_rdata),
4941                              q_type);
4942
4943         /* configure classification DBs */
4944         ecore_init_mac_obj(sc,
4945                            &sc->sp_objs[idx].mac_obj,
4946                            fp->cl_id,
4947                            idx,
4948                            SC_FUNC(sc),
4949                            BNX2X_SP(sc, mac_rdata),
4950                            (phys_addr_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4951                            ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4952                            ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4953 }
4954
4955 static void
4956 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4957                    uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4958 {
4959         union ustorm_eth_rx_producers rx_prods;
4960         uint32_t i;
4961
4962         /* update producers */
4963         rx_prods.prod.bd_prod = rx_bd_prod;
4964         rx_prods.prod.cqe_prod = rx_cq_prod;
4965         rx_prods.prod.reserved = 0;
4966
4967         /*
4968          * Make sure that the BD and SGE data is updated before updating the
4969          * producers since FW might read the BD/SGE right after the producer
4970          * is updated.
4971          * This is only applicable for weak-ordered memory model archs such
4972          * as IA-64. The following barrier is also mandatory since FW will
4973          * assumes BDs must have buffers.
4974          */
4975         wmb();
4976
4977         for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
4978                 REG_WR(sc,
4979                        (fp->ustorm_rx_prods_offset + (i * 4)),
4980                        rx_prods.raw_data[i]);
4981         }
4982
4983         wmb();                  /* keep prod updates ordered */
4984 }
4985
4986 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
4987 {
4988         struct bnx2x_fastpath *fp;
4989         int i;
4990         struct bnx2x_rx_queue *rxq;
4991
4992         for (i = 0; i < sc->num_queues; i++) {
4993                 fp = &sc->fp[i];
4994                 rxq = sc->rx_queues[fp->index];
4995                 if (!rxq) {
4996                         PMD_RX_LOG(ERR, "RX queue is NULL");
4997                         return;
4998                 }
4999
5000 /*
5001  * Activate the BD ring...
5002  * Warning, this will generate an interrupt (to the TSTORM)
5003  * so this can only be done after the chip is initialized
5004  */
5005                 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5006
5007                 if (i != 0) {
5008                         continue;
5009                 }
5010         }
5011 }
5012
5013 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5014 {
5015         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5016
5017         fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5018         fp->tx_db.data.zero_fill1 = 0;
5019         fp->tx_db.data.prod = 0;
5020
5021         if (!txq) {
5022                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5023                 return;
5024         }
5025
5026         txq->tx_pkt_tail = 0;
5027         txq->tx_pkt_head = 0;
5028         txq->tx_bd_tail = 0;
5029         txq->tx_bd_head = 0;
5030 }
5031
5032 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5033 {
5034         int i;
5035
5036         for (i = 0; i < sc->num_queues; i++) {
5037                 bnx2x_init_tx_ring_one(&sc->fp[i]);
5038         }
5039 }
5040
5041 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5042 {
5043         struct host_sp_status_block *def_sb = sc->def_sb;
5044         phys_addr_t mapping = sc->def_sb_dma.paddr;
5045         int igu_sp_sb_index;
5046         int igu_seg_id;
5047         int port = SC_PORT(sc);
5048         int func = SC_FUNC(sc);
5049         int reg_offset, reg_offset_en5;
5050         uint64_t section;
5051         int index, sindex;
5052         struct hc_sp_status_block_data sp_sb_data;
5053
5054         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5055
5056         if (CHIP_INT_MODE_IS_BC(sc)) {
5057                 igu_sp_sb_index = DEF_SB_IGU_ID;
5058                 igu_seg_id = HC_SEG_ACCESS_DEF;
5059         } else {
5060                 igu_sp_sb_index = sc->igu_dsb_id;
5061                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5062         }
5063
5064         /* attentions */
5065         section = ((uint64_t) mapping +
5066                    offsetof(struct host_sp_status_block, atten_status_block));
5067         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5068         sc->attn_state = 0;
5069
5070         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5071             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5072
5073         reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5074             MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5075
5076         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5077 /* take care of sig[0]..sig[4] */
5078                 for (sindex = 0; sindex < 4; sindex++) {
5079                         sc->attn_group[index].sig[sindex] =
5080                             REG_RD(sc,
5081                                    (reg_offset + (sindex * 0x4) +
5082                                     (0x10 * index)));
5083                 }
5084
5085                 if (!CHIP_IS_E1x(sc)) {
5086                         /*
5087                          * enable5 is separate from the rest of the registers,
5088                          * and the address skip is 4 and not 16 between the
5089                          * different groups
5090                          */
5091                         sc->attn_group[index].sig[4] =
5092                             REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5093                 } else {
5094                         sc->attn_group[index].sig[4] = 0;
5095                 }
5096         }
5097
5098         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5099                 reg_offset =
5100                     port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5101                 REG_WR(sc, reg_offset, U64_LO(section));
5102                 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5103         } else if (!CHIP_IS_E1x(sc)) {
5104                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5105                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5106         }
5107
5108         section = ((uint64_t) mapping +
5109                    offsetof(struct host_sp_status_block, sp_sb));
5110
5111         bnx2x_zero_sp_sb(sc);
5112
5113         /* PCI guarantees endianity of regpair */
5114         sp_sb_data.state = SB_ENABLED;
5115         sp_sb_data.host_sb_addr.lo = U64_LO(section);
5116         sp_sb_data.host_sb_addr.hi = U64_HI(section);
5117         sp_sb_data.igu_sb_id = igu_sp_sb_index;
5118         sp_sb_data.igu_seg_id = igu_seg_id;
5119         sp_sb_data.p_func.pf_id = func;
5120         sp_sb_data.p_func.vnic_id = SC_VN(sc);
5121         sp_sb_data.p_func.vf_id = 0xff;
5122
5123         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5124
5125         bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5126 }
5127
5128 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5129 {
5130         atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5131         sc->spq_prod_idx = 0;
5132         sc->dsb_sp_prod =
5133             &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5134         sc->spq_prod_bd = sc->spq;
5135         sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5136 }
5137
5138 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5139 {
5140         union event_ring_elem *elem;
5141         int i;
5142
5143         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5144                 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5145
5146                 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5147                                                          BNX2X_PAGE_SIZE *
5148                                                          (i % NUM_EQ_PAGES)));
5149                 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5150                                                          BNX2X_PAGE_SIZE *
5151                                                          (i % NUM_EQ_PAGES)));
5152         }
5153
5154         sc->eq_cons = 0;
5155         sc->eq_prod = NUM_EQ_DESC;
5156         sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5157
5158         atomic_store_rel_long(&sc->eq_spq_left,
5159                               (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5160                                    NUM_EQ_DESC) - 1));
5161 }
5162
5163 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5164 {
5165         int i;
5166
5167         if (IS_MF_SI(sc)) {
5168 /*
5169  * In switch independent mode, the TSTORM needs to accept
5170  * packets that failed classification, since approximate match
5171  * mac addresses aren't written to NIG LLH.
5172  */
5173                 REG_WR8(sc,
5174                         (BAR_TSTRORM_INTMEM +
5175                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5176         } else
5177                 REG_WR8(sc,
5178                         (BAR_TSTRORM_INTMEM +
5179                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5180
5181         /*
5182          * Zero this manually as its initialization is currently missing
5183          * in the initTool.
5184          */
5185         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5186                 REG_WR(sc,
5187                        (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5188                        0);
5189         }
5190
5191         if (!CHIP_IS_E1x(sc)) {
5192                 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5193                         CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5194                         HC_IGU_NBC_MODE);
5195         }
5196 }
5197
5198 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5199 {
5200         switch (load_code) {
5201         case FW_MSG_CODE_DRV_LOAD_COMMON:
5202         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5203                 bnx2x_init_internal_common(sc);
5204                 /* no break */
5205
5206         case FW_MSG_CODE_DRV_LOAD_PORT:
5207                 /* nothing to do */
5208                 /* no break */
5209
5210         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5211                 /* internal memory per function is initialized inside bnx2x_pf_init */
5212                 break;
5213
5214         default:
5215                 PMD_DRV_LOG(NOTICE, "Unknown load_code (0x%x) from MCP",
5216                             load_code);
5217                 break;
5218         }
5219 }
5220
5221 static void
5222 storm_memset_func_cfg(struct bnx2x_softc *sc,
5223                       struct tstorm_eth_function_common_config *tcfg,
5224                       uint16_t abs_fid)
5225 {
5226         uint32_t addr;
5227         size_t size;
5228
5229         addr = (BAR_TSTRORM_INTMEM +
5230                 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5231         size = sizeof(struct tstorm_eth_function_common_config);
5232         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5233 }
5234
5235 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5236 {
5237         struct tstorm_eth_function_common_config tcfg = { 0 };
5238
5239         if (CHIP_IS_E1x(sc)) {
5240                 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5241         }
5242
5243         /* Enable the function in the FW */
5244         storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5245         storm_memset_func_en(sc, p->func_id, 1);
5246
5247         /* spq */
5248         if (p->func_flgs & FUNC_FLG_SPQ) {
5249                 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5250                 REG_WR(sc,
5251                        (XSEM_REG_FAST_MEMORY +
5252                         XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5253         }
5254 }
5255
5256 /*
5257  * Calculates the sum of vn_min_rates.
5258  * It's needed for further normalizing of the min_rates.
5259  * Returns:
5260  *   sum of vn_min_rates.
5261  *     or
5262  *   0 - if all the min_rates are 0.
5263  * In the later case fainess algorithm should be deactivated.
5264  * If all min rates are not zero then those that are zeroes will be set to 1.
5265  */
5266 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5267 {
5268         uint32_t vn_cfg;
5269         uint32_t vn_min_rate;
5270         int all_zero = 1;
5271         int vn;
5272
5273         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5274                 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5275                 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5276                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5277
5278                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5279                         /* skip hidden VNs */
5280                         vn_min_rate = 0;
5281                 } else if (!vn_min_rate) {
5282                         /* If min rate is zero - set it to 100 */
5283                         vn_min_rate = DEF_MIN_RATE;
5284                 } else {
5285                         all_zero = 0;
5286                 }
5287
5288                 input->vnic_min_rate[vn] = vn_min_rate;
5289         }
5290
5291         /* if ETS or all min rates are zeros - disable fairness */
5292         if (all_zero) {
5293                 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5294         } else {
5295                 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5296         }
5297 }
5298
5299 static uint16_t
5300 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5301 {
5302         uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5303                             FUNC_MF_CFG_MAX_BW_SHIFT);
5304
5305         if (!max_cfg) {
5306                 PMD_DRV_LOG(DEBUG,
5307                             "Max BW configured to 0 - using 100 instead");
5308                 max_cfg = 100;
5309         }
5310
5311         return max_cfg;
5312 }
5313
5314 static void
5315 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5316 {
5317         uint16_t vn_max_rate;
5318         uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5319         uint32_t max_cfg;
5320
5321         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5322                 vn_max_rate = 0;
5323         } else {
5324                 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5325
5326                 if (IS_MF_SI(sc)) {
5327                         /* max_cfg in percents of linkspeed */
5328                         vn_max_rate =
5329                             ((sc->link_vars.line_speed * max_cfg) / 100);
5330                 } else {        /* SD modes */
5331                         /* max_cfg is absolute in 100Mb units */
5332                         vn_max_rate = (max_cfg * 100);
5333                 }
5334         }
5335
5336         input->vnic_max_rate[vn] = vn_max_rate;
5337 }
5338
5339 static void
5340 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5341 {
5342         struct cmng_init_input input;
5343         int vn;
5344
5345         memset(&input, 0, sizeof(struct cmng_init_input));
5346
5347         input.port_rate = sc->link_vars.line_speed;
5348
5349         if (cmng_type == CMNG_FNS_MINMAX) {
5350 /* read mf conf from shmem */
5351                 if (read_cfg) {
5352                         bnx2x_read_mf_cfg(sc);
5353                 }
5354
5355 /* get VN min rate and enable fairness if not 0 */
5356                 bnx2x_calc_vn_min(sc, &input);
5357
5358 /* get VN max rate */
5359                 if (sc->port.pmf) {
5360                         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5361                                 bnx2x_calc_vn_max(sc, vn, &input);
5362                         }
5363                 }
5364
5365 /* always enable rate shaping and fairness */
5366                 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5367
5368                 ecore_init_cmng(&input, &sc->cmng);
5369                 return;
5370         }
5371 }
5372
5373 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5374 {
5375         if (CHIP_REV_IS_SLOW(sc)) {
5376                 return CMNG_FNS_NONE;
5377         }
5378
5379         if (IS_MF(sc)) {
5380                 return CMNG_FNS_MINMAX;
5381         }
5382
5383         return CMNG_FNS_NONE;
5384 }
5385
5386 static void
5387 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5388 {
5389         int vn;
5390         int func;
5391         uint32_t addr;
5392         size_t size;
5393
5394         addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5395         size = sizeof(struct cmng_struct_per_port);
5396         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5397
5398         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5399                 func = func_by_vn(sc, vn);
5400
5401                 addr = (BAR_XSTRORM_INTMEM +
5402                         XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5403                 size = sizeof(struct rate_shaping_vars_per_vn);
5404                 ecore_storm_memset_struct(sc, addr, size,
5405                                           (uint32_t *) & cmng->
5406                                           vnic.vnic_max_rate[vn]);
5407
5408                 addr = (BAR_XSTRORM_INTMEM +
5409                         XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5410                 size = sizeof(struct fairness_vars_per_vn);
5411                 ecore_storm_memset_struct(sc, addr, size,
5412                                           (uint32_t *) & cmng->
5413                                           vnic.vnic_min_rate[vn]);
5414         }
5415 }
5416
5417 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5418 {
5419         struct bnx2x_func_init_params func_init;
5420         struct event_ring_data eq_data;
5421         uint16_t flags;
5422
5423         memset(&eq_data, 0, sizeof(struct event_ring_data));
5424         memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5425
5426         if (!CHIP_IS_E1x(sc)) {
5427 /* reset IGU PF statistics: MSIX + ATTN */
5428 /* PF */
5429                 REG_WR(sc,
5430                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5431                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5432                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5433                          4)), 0);
5434 /* ATTN */
5435                 REG_WR(sc,
5436                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5437                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5438                         (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5439                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5440                          4)), 0);
5441         }
5442
5443         /* function setup flags */
5444         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5445
5446         func_init.func_flgs = flags;
5447         func_init.pf_id = SC_FUNC(sc);
5448         func_init.func_id = SC_FUNC(sc);
5449         func_init.spq_map = sc->spq_dma.paddr;
5450         func_init.spq_prod = sc->spq_prod_idx;
5451
5452         bnx2x_func_init(sc, &func_init);
5453
5454         memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5455
5456         /*
5457          * Congestion management values depend on the link rate.
5458          * There is no active link so initial link rate is set to 10Gbps.
5459          * When the link comes up the congestion management values are
5460          * re-calculated according to the actual link rate.
5461          */
5462         sc->link_vars.line_speed = SPEED_10000;
5463         bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5464
5465         /* Only the PMF sets the HW */
5466         if (sc->port.pmf) {
5467                 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5468         }
5469
5470         /* init Event Queue - PCI bus guarantees correct endainity */
5471         eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5472         eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5473         eq_data.producer = sc->eq_prod;
5474         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5475         eq_data.sb_id = DEF_SB_ID;
5476         storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5477 }
5478
5479 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5480 {
5481         int port = SC_PORT(sc);
5482         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5483         uint32_t val = REG_RD(sc, addr);
5484         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5485             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5486         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5487         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5488
5489         if (msix) {
5490                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5491                          HC_CONFIG_0_REG_INT_LINE_EN_0);
5492                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5493                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5494                 if (single_msix) {
5495                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5496                 }
5497         } else if (msi) {
5498                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5499                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5500                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5501                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5502         } else {
5503                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5504                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5505                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
5506                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5507
5508                 REG_WR(sc, addr, val);
5509
5510                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5511         }
5512
5513         REG_WR(sc, addr, val);
5514
5515         /* ensure that HC_CONFIG is written before leading/trailing edge config */
5516         mb();
5517
5518         /* init leading/trailing edge */
5519         if (IS_MF(sc)) {
5520                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5521                 if (sc->port.pmf) {
5522                         /* enable nig and gpio3 attention */
5523                         val |= 0x1100;
5524                 }
5525         } else {
5526                 val = 0xffff;
5527         }
5528
5529         REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5530         REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5531
5532         /* make sure that interrupts are indeed enabled from here on */
5533         mb();
5534 }
5535
5536 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5537 {
5538         uint32_t val;
5539         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5540             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5541         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5542         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5543
5544         val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5545
5546         if (msix) {
5547                 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5548                 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5549                 if (single_msix) {
5550                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
5551                 }
5552         } else if (msi) {
5553                 val &= ~IGU_PF_CONF_INT_LINE_EN;
5554                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5555                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5556         } else {
5557                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5558                 val |= (IGU_PF_CONF_INT_LINE_EN |
5559                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5560         }
5561
5562         /* clean previous status - need to configure igu prior to ack */
5563         if ((!msix) || single_msix) {
5564                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5565                 bnx2x_ack_int(sc);
5566         }
5567
5568         val |= IGU_PF_CONF_FUNC_EN;
5569
5570         PMD_DRV_LOG(DEBUG, "write 0x%x to IGU mode %s",
5571                     val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5572
5573         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5574
5575         mb();
5576
5577         /* init leading/trailing edge */
5578         if (IS_MF(sc)) {
5579                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5580                 if (sc->port.pmf) {
5581                         /* enable nig and gpio3 attention */
5582                         val |= 0x1100;
5583                 }
5584         } else {
5585                 val = 0xffff;
5586         }
5587
5588         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5589         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5590
5591         /* make sure that interrupts are indeed enabled from here on */
5592         mb();
5593 }
5594
5595 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5596 {
5597         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5598                 bnx2x_hc_int_enable(sc);
5599         } else {
5600                 bnx2x_igu_int_enable(sc);
5601         }
5602 }
5603
5604 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5605 {
5606         int port = SC_PORT(sc);
5607         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5608         uint32_t val = REG_RD(sc, addr);
5609
5610         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5611                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5612                  HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5613         /* flush all outstanding writes */
5614         mb();
5615
5616         REG_WR(sc, addr, val);
5617         if (REG_RD(sc, addr) != val) {
5618                 PMD_DRV_LOG(ERR, "proper val not read from HC IGU!");
5619         }
5620 }
5621
5622 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5623 {
5624         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5625
5626         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5627                  IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5628
5629         PMD_DRV_LOG(DEBUG, "write %x to IGU", val);
5630
5631         /* flush all outstanding writes */
5632         mb();
5633
5634         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5635         if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5636                 PMD_DRV_LOG(ERR, "proper val not read from IGU!");
5637         }
5638 }
5639
5640 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5641 {
5642         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5643                 bnx2x_hc_int_disable(sc);
5644         } else {
5645                 bnx2x_igu_int_disable(sc);
5646         }
5647 }
5648
5649 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5650 {
5651         int i;
5652
5653         PMD_INIT_FUNC_TRACE();
5654
5655         for (i = 0; i < sc->num_queues; i++) {
5656                 bnx2x_init_eth_fp(sc, i);
5657         }
5658
5659         rmb();                  /* ensure status block indices were read */
5660
5661         bnx2x_init_rx_rings(sc);
5662         bnx2x_init_tx_rings(sc);
5663
5664         if (IS_VF(sc)) {
5665                 bnx2x_memset_stats(sc);
5666                 return;
5667         }
5668
5669         /* initialize MOD_ABS interrupts */
5670         elink_init_mod_abs_int(sc, &sc->link_vars,
5671                                sc->devinfo.chip_id,
5672                                sc->devinfo.shmem_base,
5673                                sc->devinfo.shmem2_base, SC_PORT(sc));
5674
5675         bnx2x_init_def_sb(sc);
5676         bnx2x_update_dsb_idx(sc);
5677         bnx2x_init_sp_ring(sc);
5678         bnx2x_init_eq_ring(sc);
5679         bnx2x_init_internal(sc, load_code);
5680         bnx2x_pf_init(sc);
5681         bnx2x_stats_init(sc);
5682
5683         /* flush all before enabling interrupts */
5684         mb();
5685
5686         bnx2x_int_enable(sc);
5687
5688         /* check for SPIO5 */
5689         bnx2x_attn_int_deasserted0(sc,
5690                                  REG_RD(sc,
5691                                         (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5692                                          SC_PORT(sc) * 4)) &
5693                                  AEU_INPUTS_ATTN_BITS_SPIO5);
5694 }
5695
5696 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5697 {
5698         /* mcast rules must be added to tx if tx switching is enabled */
5699         ecore_obj_type o_type;
5700         if (sc->flags & BNX2X_TX_SWITCHING)
5701                 o_type = ECORE_OBJ_TYPE_RX_TX;
5702         else
5703                 o_type = ECORE_OBJ_TYPE_RX;
5704
5705         /* RX_MODE controlling object */
5706         ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5707
5708         /* multicast configuration controlling object */
5709         ecore_init_mcast_obj(sc,
5710                              &sc->mcast_obj,
5711                              sc->fp[0].cl_id,
5712                              sc->fp[0].index,
5713                              SC_FUNC(sc),
5714                              SC_FUNC(sc),
5715                              BNX2X_SP(sc, mcast_rdata),
5716                              (phys_addr_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5717                              ECORE_FILTER_MCAST_PENDING,
5718                              &sc->sp_state, o_type);
5719
5720         /* Setup CAM credit pools */
5721         ecore_init_mac_credit_pool(sc,
5722                                    &sc->macs_pool,
5723                                    SC_FUNC(sc),
5724                                    CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5725                                    VNICS_PER_PATH(sc));
5726
5727         ecore_init_vlan_credit_pool(sc,
5728                                     &sc->vlans_pool,
5729                                     SC_ABS_FUNC(sc) >> 1,
5730                                     CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5731                                     VNICS_PER_PATH(sc));
5732
5733         /* RSS configuration object */
5734         ecore_init_rss_config_obj(&sc->rss_conf_obj,
5735                                   sc->fp[0].cl_id,
5736                                   sc->fp[0].index,
5737                                   SC_FUNC(sc),
5738                                   SC_FUNC(sc),
5739                                   BNX2X_SP(sc, rss_rdata),
5740                                   (phys_addr_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5741                                   ECORE_FILTER_RSS_CONF_PENDING,
5742                                   &sc->sp_state, ECORE_OBJ_TYPE_RX);
5743 }
5744
5745 /*
5746  * Initialize the function. This must be called before sending CLIENT_SETUP
5747  * for the first client.
5748  */
5749 static int bnx2x_func_start(struct bnx2x_softc *sc)
5750 {
5751         struct ecore_func_state_params func_params = { NULL };
5752         struct ecore_func_start_params *start_params =
5753             &func_params.params.start;
5754
5755         /* Prepare parameters for function state transitions */
5756         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5757
5758         func_params.f_obj = &sc->func_obj;
5759         func_params.cmd = ECORE_F_CMD_START;
5760
5761         /* Function parameters */
5762         start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5763         start_params->sd_vlan_tag = OVLAN(sc);
5764
5765         if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5766                 start_params->network_cos_mode = STATIC_COS;
5767         } else {                /* CHIP_IS_E1X */
5768                 start_params->network_cos_mode = FW_WRR;
5769         }
5770
5771         start_params->gre_tunnel_mode = 0;
5772         start_params->gre_tunnel_rss = 0;
5773
5774         return ecore_func_state_change(sc, &func_params);
5775 }
5776
5777 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5778 {
5779         uint16_t pmcsr;
5780
5781         /* If there is no power capability, silently succeed */
5782         if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5783                 PMD_DRV_LOG(WARNING, "No power capability");
5784                 return 0;
5785         }
5786
5787         pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5788                  2);
5789
5790         switch (state) {
5791         case PCI_PM_D0:
5792                 pci_write_word(sc,
5793                                (sc->devinfo.pcie_pm_cap_reg +
5794                                 PCIR_POWER_STATUS),
5795                                ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5796
5797                 if (pmcsr & PCIM_PSTAT_DMASK) {
5798                         /* delay required during transition out of D3hot */
5799                         DELAY(20000);
5800                 }
5801
5802                 break;
5803
5804         case PCI_PM_D3hot:
5805                 /* don't shut down the power for emulation and FPGA */
5806                 if (CHIP_REV_IS_SLOW(sc)) {
5807                         return 0;
5808                 }
5809
5810                 pmcsr &= ~PCIM_PSTAT_DMASK;
5811                 pmcsr |= PCIM_PSTAT_D3;
5812
5813                 if (sc->wol) {
5814                         pmcsr |= PCIM_PSTAT_PMEENABLE;
5815                 }
5816
5817                 pci_write_long(sc,
5818                                (sc->devinfo.pcie_pm_cap_reg +
5819                                 PCIR_POWER_STATUS), pmcsr);
5820
5821                 /*
5822                  * No more memory access after this point until device is brought back
5823                  * to D0 state.
5824                  */
5825                 break;
5826
5827         default:
5828                 PMD_DRV_LOG(NOTICE, "Can't support PCI power state = %d",
5829                             state);
5830                 return -1;
5831         }
5832
5833         return 0;
5834 }
5835
5836 /* return true if succeeded to acquire the lock */
5837 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5838 {
5839         uint32_t lock_status;
5840         uint32_t resource_bit = (1 << resource);
5841         int func = SC_FUNC(sc);
5842         uint32_t hw_lock_control_reg;
5843
5844         /* Validating that the resource is within range */
5845         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5846                 PMD_DRV_LOG(INFO,
5847                             "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5848                             resource, HW_LOCK_MAX_RESOURCE_VALUE);
5849                 return FALSE;
5850         }
5851
5852         if (func <= 5) {
5853                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5854         } else {
5855                 hw_lock_control_reg =
5856                     (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5857         }
5858
5859         /* try to acquire the lock */
5860         REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5861         lock_status = REG_RD(sc, hw_lock_control_reg);
5862         if (lock_status & resource_bit) {
5863                 return TRUE;
5864         }
5865
5866         PMD_DRV_LOG(NOTICE, "Failed to get a resource lock 0x%x", resource);
5867
5868         return FALSE;
5869 }
5870
5871 /*
5872  * Get the recovery leader resource id according to the engine this function
5873  * belongs to. Currently only only 2 engines is supported.
5874  */
5875 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5876 {
5877         if (SC_PATH(sc)) {
5878                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5879         } else {
5880                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5881         }
5882 }
5883
5884 /* try to acquire a leader lock for current engine */
5885 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5886 {
5887         return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5888 }
5889
5890 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5891 {
5892         return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5893 }
5894
5895 /* close gates #2, #3 and #4 */
5896 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5897 {
5898         uint32_t val;
5899
5900         /* gates #2 and #4a are closed/opened */
5901         /* #4 */
5902         REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5903         /* #2 */
5904         REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5905
5906         /* #3 */
5907         if (CHIP_IS_E1x(sc)) {
5908 /* prevent interrupts from HC on both ports */
5909                 val = REG_RD(sc, HC_REG_CONFIG_1);
5910                 if (close)
5911                         REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5912                                                      HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5913                 else
5914                         REG_WR(sc, HC_REG_CONFIG_1,
5915                                (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5916
5917                 val = REG_RD(sc, HC_REG_CONFIG_0);
5918                 if (close)
5919                         REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5920                                                      HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5921                 else
5922                         REG_WR(sc, HC_REG_CONFIG_0,
5923                                (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5924
5925         } else {
5926 /* Prevent incomming interrupts in IGU */
5927                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5928
5929                 if (close)
5930                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5931                                (val & ~(uint32_t)
5932                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5933                 else
5934                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5935                                (val |
5936                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5937         }
5938
5939         wmb();
5940 }
5941
5942 /* poll for pending writes bit, it should get cleared in no more than 1s */
5943 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5944 {
5945         uint32_t cnt = 1000;
5946         uint32_t pend_bits = 0;
5947
5948         do {
5949                 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5950
5951                 if (pend_bits == 0) {
5952                         break;
5953                 }
5954
5955                 DELAY(1000);
5956         } while (cnt-- > 0);
5957
5958         if (cnt <= 0) {
5959                 PMD_DRV_LOG(NOTICE, "Still pending IGU requests bits=0x%08x!",
5960                             pend_bits);
5961                 return -1;
5962         }
5963
5964         return 0;
5965 }
5966
5967 #define SHARED_MF_CLP_MAGIC  0x80000000 /* 'magic' bit */
5968
5969 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5970 {
5971         /* Do some magic... */
5972         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5973         *magic_val = val & SHARED_MF_CLP_MAGIC;
5974         MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
5975 }
5976
5977 /* restore the value of the 'magic' bit */
5978 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
5979 {
5980         /* Restore the 'magic' bit value... */
5981         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5982         MFCFG_WR(sc, shared_mf_config.clp_mb,
5983                  (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
5984 }
5985
5986 /* prepare for MCP reset, takes care of CLP configurations */
5987 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5988 {
5989         uint32_t shmem;
5990         uint32_t validity_offset;
5991
5992         /* set `magic' bit in order to save MF config */
5993         bnx2x_clp_reset_prep(sc, magic_val);
5994
5995         /* get shmem offset */
5996         shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
5997         validity_offset =
5998             offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
5999
6000         /* Clear validity map flags */
6001         if (shmem > 0) {
6002                 REG_WR(sc, shmem + validity_offset, 0);
6003         }
6004 }
6005
6006 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
6007 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
6008
6009 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6010 {
6011         /* special handling for emulation and FPGA (10 times longer) */
6012         if (CHIP_REV_IS_SLOW(sc)) {
6013                 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6014         } else {
6015                 DELAY((MCP_ONE_TIMEOUT) * 1000);
6016         }
6017 }
6018
6019 /* initialize shmem_base and waits for validity signature to appear */
6020 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6021 {
6022         int cnt = 0;
6023         uint32_t val = 0;
6024
6025         do {
6026                 sc->devinfo.shmem_base =
6027                     sc->link_params.shmem_base =
6028                     REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6029
6030                 if (sc->devinfo.shmem_base) {
6031                         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6032                         if (val & SHR_MEM_VALIDITY_MB)
6033                                 return 0;
6034                 }
6035
6036                 bnx2x_mcp_wait_one(sc);
6037
6038         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6039
6040         PMD_DRV_LOG(NOTICE, "BAD MCP validity signature");
6041
6042         return -1;
6043 }
6044
6045 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6046 {
6047         int rc = bnx2x_init_shmem(sc);
6048
6049         /* Restore the `magic' bit value */
6050         bnx2x_clp_reset_done(sc, magic_val);
6051
6052         return rc;
6053 }
6054
6055 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6056 {
6057         REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6058         REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6059         wmb();
6060 }
6061
6062 /*
6063  * Reset the whole chip except for:
6064  *      - PCIE core
6065  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6066  *      - IGU
6067  *      - MISC (including AEU)
6068  *      - GRC
6069  *      - RBCN, RBCP
6070  */
6071 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6072 {
6073         uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6074         uint32_t global_bits2, stay_reset2;
6075
6076         /*
6077          * Bits that have to be set in reset_mask2 if we want to reset 'global'
6078          * (per chip) blocks.
6079          */
6080         global_bits2 =
6081             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6082             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6083
6084         /*
6085          * Don't reset the following blocks.
6086          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6087          *            reset, as in 4 port device they might still be owned
6088          *            by the MCP (there is only one leader per path).
6089          */
6090         not_reset_mask1 =
6091             MISC_REGISTERS_RESET_REG_1_RST_HC |
6092             MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6093             MISC_REGISTERS_RESET_REG_1_RST_PXP;
6094
6095         not_reset_mask2 =
6096             MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6097             MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6098             MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6099             MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6100             MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6101             MISC_REGISTERS_RESET_REG_2_RST_GRC |
6102             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6103             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6104             MISC_REGISTERS_RESET_REG_2_RST_ATC |
6105             MISC_REGISTERS_RESET_REG_2_PGLC |
6106             MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6107             MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6108             MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6109             MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6110             MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6111
6112         /*
6113          * Keep the following blocks in reset:
6114          *  - all xxMACs are handled by the elink code.
6115          */
6116         stay_reset2 =
6117             MISC_REGISTERS_RESET_REG_2_XMAC |
6118             MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6119
6120         /* Full reset masks according to the chip */
6121         reset_mask1 = 0xffffffff;
6122
6123         if (CHIP_IS_E1H(sc))
6124                 reset_mask2 = 0x1ffff;
6125         else if (CHIP_IS_E2(sc))
6126                 reset_mask2 = 0xfffff;
6127         else                    /* CHIP_IS_E3 */
6128                 reset_mask2 = 0x3ffffff;
6129
6130         /* Don't reset global blocks unless we need to */
6131         if (!global)
6132                 reset_mask2 &= ~global_bits2;
6133
6134         /*
6135          * In case of attention in the QM, we need to reset PXP
6136          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6137          * because otherwise QM reset would release 'close the gates' shortly
6138          * before resetting the PXP, then the PSWRQ would send a write
6139          * request to PGLUE. Then when PXP is reset, PGLUE would try to
6140          * read the payload data from PSWWR, but PSWWR would not
6141          * respond. The write queue in PGLUE would stuck, dmae commands
6142          * would not return. Therefore it's important to reset the second
6143          * reset register (containing the
6144          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6145          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6146          * bit).
6147          */
6148         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6149                reset_mask2 & (~not_reset_mask2));
6150
6151         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6152                reset_mask1 & (~not_reset_mask1));
6153
6154         mb();
6155         wmb();
6156
6157         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6158                reset_mask2 & (~stay_reset2));
6159
6160         mb();
6161         wmb();
6162
6163         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6164         wmb();
6165 }
6166
6167 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6168 {
6169         int cnt = 1000;
6170         uint32_t val = 0;
6171         uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6172         uint32_t tags_63_32 = 0;
6173
6174         /* Empty the Tetris buffer, wait for 1s */
6175         do {
6176                 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6177                 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6178                 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6179                 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6180                 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6181                 if (CHIP_IS_E3(sc)) {
6182                         tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6183                 }
6184
6185                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6186                     ((port_is_idle_0 & 0x1) == 0x1) &&
6187                     ((port_is_idle_1 & 0x1) == 0x1) &&
6188                     (pgl_exp_rom2 == 0xffffffff) &&
6189                     (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6190                         break;
6191                 DELAY(1000);
6192         } while (cnt-- > 0);
6193
6194         if (cnt <= 0) {
6195                 PMD_DRV_LOG(NOTICE,
6196                             "ERROR: Tetris buffer didn't get empty or there "
6197                             "are still outstanding read requests after 1s! "
6198                             "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6199                             "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6200                             sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6201                             pgl_exp_rom2);
6202                 return -1;
6203         }
6204
6205         mb();
6206
6207         /* Close gates #2, #3 and #4 */
6208         bnx2x_set_234_gates(sc, TRUE);
6209
6210         /* Poll for IGU VQs for 57712 and newer chips */
6211         if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6212                 return -1;
6213         }
6214
6215         /* clear "unprepared" bit */
6216         REG_WR(sc, MISC_REG_UNPREPARED, 0);
6217         mb();
6218
6219         /* Make sure all is written to the chip before the reset */
6220         wmb();
6221
6222         /*
6223          * Wait for 1ms to empty GLUE and PCI-E core queues,
6224          * PSWHST, GRC and PSWRD Tetris buffer.
6225          */
6226         DELAY(1000);
6227
6228         /* Prepare to chip reset: */
6229         /* MCP */
6230         if (global) {
6231                 bnx2x_reset_mcp_prep(sc, &val);
6232         }
6233
6234         /* PXP */
6235         bnx2x_pxp_prep(sc);
6236         mb();
6237
6238         /* reset the chip */
6239         bnx2x_process_kill_chip_reset(sc, global);
6240         mb();
6241
6242         /* Recover after reset: */
6243         /* MCP */
6244         if (global && bnx2x_reset_mcp_comp(sc, val)) {
6245                 return -1;
6246         }
6247
6248         /* Open the gates #2, #3 and #4 */
6249         bnx2x_set_234_gates(sc, FALSE);
6250
6251         return 0;
6252 }
6253
6254 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6255 {
6256         int rc = 0;
6257         uint8_t global = bnx2x_reset_is_global(sc);
6258         uint32_t load_code;
6259
6260         /*
6261          * If not going to reset MCP, load "fake" driver to reset HW while
6262          * driver is owner of the HW.
6263          */
6264         if (!global && !BNX2X_NOMCP(sc)) {
6265                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6266                                            DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6267                 if (!load_code) {
6268                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6269                         rc = -1;
6270                         goto exit_leader_reset;
6271                 }
6272
6273                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6274                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6275                         PMD_DRV_LOG(NOTICE,
6276                                     "MCP unexpected response, aborting");
6277                         rc = -1;
6278                         goto exit_leader_reset2;
6279                 }
6280
6281                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6282                 if (!load_code) {
6283                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6284                         rc = -1;
6285                         goto exit_leader_reset2;
6286                 }
6287         }
6288
6289         /* try to recover after the failure */
6290         if (bnx2x_process_kill(sc, global)) {
6291                 PMD_DRV_LOG(NOTICE, "Something bad occurred on engine %d!",
6292                             SC_PATH(sc));
6293                 rc = -1;
6294                 goto exit_leader_reset2;
6295         }
6296
6297         /*
6298          * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6299          * state.
6300          */
6301         bnx2x_set_reset_done(sc);
6302         if (global) {
6303                 bnx2x_clear_reset_global(sc);
6304         }
6305
6306 exit_leader_reset2:
6307
6308         /* unload "fake driver" if it was loaded */
6309         if (!global &&!BNX2X_NOMCP(sc)) {
6310                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6311                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6312         }
6313
6314 exit_leader_reset:
6315
6316         sc->is_leader = 0;
6317         bnx2x_release_leader_lock(sc);
6318
6319         mb();
6320         return rc;
6321 }
6322
6323 /*
6324  * prepare INIT transition, parameters configured:
6325  *   - HC configuration
6326  *   - Queue's CDU context
6327  */
6328 static void
6329 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6330                    struct ecore_queue_init_params *init_params)
6331 {
6332         uint8_t cos;
6333         int cxt_index, cxt_offset;
6334
6335         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6336         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6337
6338         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6339         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6340
6341         /* HC rate */
6342         init_params->rx.hc_rate =
6343             sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6344         init_params->tx.hc_rate =
6345             sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6346
6347         /* FW SB ID */
6348         init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6349
6350         /* CQ index among the SB indices */
6351         init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6352         init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6353
6354         /* set maximum number of COSs supported by this queue */
6355         init_params->max_cos = sc->max_cos;
6356
6357         /* set the context pointers queue object */
6358         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6359                 cxt_index = fp->index / ILT_PAGE_CIDS;
6360                 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6361                 init_params->cxts[cos] =
6362                     &sc->context[cxt_index].vcxt[cxt_offset].eth;
6363         }
6364 }
6365
6366 /* set flags that are common for the Tx-only and not normal connections */
6367 static unsigned long
6368 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6369 {
6370         unsigned long flags = 0;
6371
6372         /* PF driver will always initialize the Queue to an ACTIVE state */
6373         bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6374
6375         /*
6376          * tx only connections collect statistics (on the same index as the
6377          * parent connection). The statistics are zeroed when the parent
6378          * connection is initialized.
6379          */
6380
6381         bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6382         if (zero_stats) {
6383                 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6384         }
6385
6386         /*
6387          * tx only connections can support tx-switching, though their
6388          * CoS-ness doesn't survive the loopback
6389          */
6390         if (sc->flags & BNX2X_TX_SWITCHING) {
6391                 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6392         }
6393
6394         bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6395
6396         return flags;
6397 }
6398
6399 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6400 {
6401         unsigned long flags = 0;
6402
6403         if (IS_MF_SD(sc)) {
6404                 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6405         }
6406
6407         if (leading) {
6408                 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6409                 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6410         }
6411
6412         bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6413
6414         /* merge with common flags */
6415         return flags | bnx2x_get_common_flags(sc, TRUE);
6416 }
6417
6418 static void
6419 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6420                       struct ecore_general_setup_params *gen_init, uint8_t cos)
6421 {
6422         gen_init->stat_id = bnx2x_stats_id(fp);
6423         gen_init->spcl_id = fp->cl_id;
6424         gen_init->mtu = sc->mtu;
6425         gen_init->cos = cos;
6426 }
6427
6428 static void
6429 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6430                  struct rxq_pause_params *pause,
6431                  struct ecore_rxq_setup_params *rxq_init)
6432 {
6433         struct bnx2x_rx_queue *rxq;
6434
6435         rxq = sc->rx_queues[fp->index];
6436         if (!rxq) {
6437                 PMD_RX_LOG(ERR, "RX queue is NULL");
6438                 return;
6439         }
6440         /* pause */
6441         pause->bd_th_lo = BD_TH_LO(sc);
6442         pause->bd_th_hi = BD_TH_HI(sc);
6443
6444         pause->rcq_th_lo = RCQ_TH_LO(sc);
6445         pause->rcq_th_hi = RCQ_TH_HI(sc);
6446
6447         /* validate rings have enough entries to cross high thresholds */
6448         if (sc->dropless_fc &&
6449             pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6450                 PMD_DRV_LOG(WARNING, "rx bd ring threshold limit");
6451         }
6452
6453         if (sc->dropless_fc &&
6454             pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6455                 PMD_DRV_LOG(WARNING, "rcq ring threshold limit");
6456         }
6457
6458         pause->pri_map = 1;
6459
6460         /* rxq setup */
6461         rxq_init->dscr_map = (phys_addr_t)rxq->rx_ring_phys_addr;
6462         rxq_init->rcq_map = (phys_addr_t)rxq->cq_ring_phys_addr;
6463         rxq_init->rcq_np_map = (phys_addr_t)(rxq->cq_ring_phys_addr +
6464                                               BNX2X_PAGE_SIZE);
6465
6466         /*
6467          * This should be a maximum number of data bytes that may be
6468          * placed on the BD (not including paddings).
6469          */
6470         rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6471
6472         rxq_init->cl_qzone_id = fp->cl_qzone_id;
6473         rxq_init->rss_engine_id = SC_FUNC(sc);
6474         rxq_init->mcast_engine_id = SC_FUNC(sc);
6475
6476         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6477         rxq_init->fw_sb_id = fp->fw_sb_id;
6478
6479         rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6480
6481         /*
6482          * configure silent vlan removal
6483          * if multi function mode is afex, then mask default vlan
6484          */
6485         if (IS_MF_AFEX(sc)) {
6486                 rxq_init->silent_removal_value =
6487                     sc->devinfo.mf_info.afex_def_vlan_tag;
6488                 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6489         }
6490 }
6491
6492 static void
6493 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6494                  struct ecore_txq_setup_params *txq_init, uint8_t cos)
6495 {
6496         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6497
6498         if (!txq) {
6499                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6500                 return;
6501         }
6502         txq_init->dscr_map = (phys_addr_t)txq->tx_ring_phys_addr;
6503         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6504         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6505         txq_init->fw_sb_id = fp->fw_sb_id;
6506
6507         /*
6508          * set the TSS leading client id for TX classfication to the
6509          * leading RSS client id
6510          */
6511         txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6512 }
6513
6514 /*
6515  * This function performs 2 steps in a queue state machine:
6516  *   1) RESET->INIT
6517  *   2) INIT->SETUP
6518  */
6519 static int
6520 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6521 {
6522         struct ecore_queue_state_params q_params = { NULL };
6523         struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6524         int rc;
6525
6526         PMD_DRV_LOG(DEBUG, "setting up queue %d", fp->index);
6527
6528         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6529
6530         q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6531
6532         /* we want to wait for completion in this context */
6533         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6534
6535         /* prepare the INIT parameters */
6536         bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6537
6538         /* Set the command */
6539         q_params.cmd = ECORE_Q_CMD_INIT;
6540
6541         /* Change the state to INIT */
6542         rc = ecore_queue_state_change(sc, &q_params);
6543         if (rc) {
6544                 PMD_DRV_LOG(NOTICE, "Queue(%d) INIT failed", fp->index);
6545                 return rc;
6546         }
6547
6548         PMD_DRV_LOG(DEBUG, "init complete");
6549
6550         /* now move the Queue to the SETUP state */
6551         memset(setup_params, 0, sizeof(*setup_params));
6552
6553         /* set Queue flags */
6554         setup_params->flags = bnx2x_get_q_flags(sc, leading);
6555
6556         /* set general SETUP parameters */
6557         bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6558                               FIRST_TX_COS_INDEX);
6559
6560         bnx2x_pf_rx_q_prep(sc, fp,
6561                          &setup_params->pause_params,
6562                          &setup_params->rxq_params);
6563
6564         bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6565
6566         /* Set the command */
6567         q_params.cmd = ECORE_Q_CMD_SETUP;
6568
6569         /* change the state to SETUP */
6570         rc = ecore_queue_state_change(sc, &q_params);
6571         if (rc) {
6572                 PMD_DRV_LOG(NOTICE, "Queue(%d) SETUP failed", fp->index);
6573                 return rc;
6574         }
6575
6576         return rc;
6577 }
6578
6579 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6580 {
6581         if (IS_PF(sc))
6582                 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6583         else                    /* VF */
6584                 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6585 }
6586
6587 static int
6588 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6589                   uint8_t config_hash)
6590 {
6591         struct ecore_config_rss_params params = { NULL };
6592         uint32_t i;
6593
6594         /*
6595          * Although RSS is meaningless when there is a single HW queue we
6596          * still need it enabled in order to have HW Rx hash generated.
6597          */
6598
6599         params.rss_obj = rss_obj;
6600
6601         bnx2x_set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
6602
6603         bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, &params.rss_flags);
6604
6605         /* RSS configuration */
6606         bnx2x_set_bit(ECORE_RSS_IPV4, &params.rss_flags);
6607         bnx2x_set_bit(ECORE_RSS_IPV4_TCP, &params.rss_flags);
6608         bnx2x_set_bit(ECORE_RSS_IPV6, &params.rss_flags);
6609         bnx2x_set_bit(ECORE_RSS_IPV6_TCP, &params.rss_flags);
6610         if (rss_obj->udp_rss_v4) {
6611                 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, &params.rss_flags);
6612         }
6613         if (rss_obj->udp_rss_v6) {
6614                 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, &params.rss_flags);
6615         }
6616
6617         /* Hash bits */
6618         params.rss_result_mask = MULTI_MASK;
6619
6620         (void)rte_memcpy(params.ind_table, rss_obj->ind_table,
6621                          sizeof(params.ind_table));
6622
6623         if (config_hash) {
6624 /* RSS keys */
6625                 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6626                         params.rss_key[i] = (uint32_t) rte_rand();
6627                 }
6628
6629                 bnx2x_set_bit(ECORE_RSS_SET_SRCH, &params.rss_flags);
6630         }
6631
6632         if (IS_PF(sc))
6633                 return ecore_config_rss(sc, &params);
6634         else
6635                 return bnx2x_vf_config_rss(sc, &params);
6636 }
6637
6638 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6639 {
6640         return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6641 }
6642
6643 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6644 {
6645         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6646         uint32_t i;
6647
6648         /*
6649          * Prepare the initial contents of the indirection table if
6650          * RSS is enabled
6651          */
6652         for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6653                 sc->rss_conf_obj.ind_table[i] =
6654                     (sc->fp->cl_id + (i % num_eth_queues));
6655         }
6656
6657         if (sc->udp_rss) {
6658                 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6659         }
6660
6661         /*
6662          * For 57711 SEARCHER configuration (rss_keys) is
6663          * per-port, so if explicit configuration is needed, do it only
6664          * for a PMF.
6665          *
6666          * For 57712 and newer it's a per-function configuration.
6667          */
6668         return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6669 }
6670
6671 static int
6672 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6673                 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6674                 unsigned long *ramrod_flags)
6675 {
6676         struct ecore_vlan_mac_ramrod_params ramrod_param;
6677         int rc;
6678
6679         memset(&ramrod_param, 0, sizeof(ramrod_param));
6680
6681         /* fill in general parameters */
6682         ramrod_param.vlan_mac_obj = obj;
6683         ramrod_param.ramrod_flags = *ramrod_flags;
6684
6685         /* fill a user request section if needed */
6686         if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6687                 (void)rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6688                                  ETH_ALEN);
6689
6690                 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6691
6692 /* Set the command: ADD or DEL */
6693                 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6694                     ECORE_VLAN_MAC_DEL;
6695         }
6696
6697         rc = ecore_config_vlan_mac(sc, &ramrod_param);
6698
6699         if (rc == ECORE_EXISTS) {
6700                 PMD_DRV_LOG(INFO, "Failed to schedule ADD operations (EEXIST)");
6701 /* do not treat adding same MAC as error */
6702                 rc = 0;
6703         } else if (rc < 0) {
6704                 PMD_DRV_LOG(ERR,
6705                             "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6706         }
6707
6708         return rc;
6709 }
6710
6711 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6712 {
6713         unsigned long ramrod_flags = 0;
6714
6715         PMD_DRV_LOG(DEBUG, "Adding Ethernet MAC");
6716
6717         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6718
6719         /* Eth MAC is set on RSS leading client (fp[0]) */
6720         return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6721                                &sc->sp_objs->mac_obj,
6722                                set, ECORE_ETH_MAC, &ramrod_flags);
6723 }
6724
6725 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6726 {
6727         uint32_t sel_phy_idx = 0;
6728
6729         if (sc->link_params.num_phys <= 1) {
6730                 return ELINK_INT_PHY;
6731         }
6732
6733         if (sc->link_vars.link_up) {
6734                 sel_phy_idx = ELINK_EXT_PHY1;
6735 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6736                 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6737                     (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6738                      ELINK_SUPPORTED_FIBRE))
6739                         sel_phy_idx = ELINK_EXT_PHY2;
6740         } else {
6741                 switch (elink_phy_selection(&sc->link_params)) {
6742                 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6743                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6744                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6745                         sel_phy_idx = ELINK_EXT_PHY1;
6746                         break;
6747                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6748                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6749                         sel_phy_idx = ELINK_EXT_PHY2;
6750                         break;
6751                 }
6752         }
6753
6754         return sel_phy_idx;
6755 }
6756
6757 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6758 {
6759         uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6760
6761         /*
6762          * The selected activated PHY is always after swapping (in case PHY
6763          * swapping is enabled). So when swapping is enabled, we need to reverse
6764          * the configuration
6765          */
6766
6767         if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6768                 if (sel_phy_idx == ELINK_EXT_PHY1)
6769                         sel_phy_idx = ELINK_EXT_PHY2;
6770                 else if (sel_phy_idx == ELINK_EXT_PHY2)
6771                         sel_phy_idx = ELINK_EXT_PHY1;
6772         }
6773
6774         return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6775 }
6776
6777 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6778 {
6779         /*
6780          * Initialize link parameters structure variables
6781          * It is recommended to turn off RX FC for jumbo frames
6782          * for better performance
6783          */
6784         if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6785                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6786         } else {
6787                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6788         }
6789 }
6790
6791 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6792 {
6793         uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6794         switch (sc->link_vars.ieee_fc &
6795                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6796         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6797         default:
6798                 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6799                                                    ADVERTISED_Pause);
6800                 break;
6801
6802         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6803                 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6804                                                   ADVERTISED_Pause);
6805                 break;
6806
6807         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6808                 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6809                 break;
6810         }
6811 }
6812
6813 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6814 {
6815         uint16_t line_speed = sc->link_vars.line_speed;
6816         if (IS_MF(sc)) {
6817                 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6818                                                       sc->devinfo.
6819                                                       mf_info.mf_config[SC_VN
6820                                                                         (sc)]);
6821
6822 /* calculate the current MAX line speed limit for the MF devices */
6823                 if (IS_MF_SI(sc)) {
6824                         line_speed = (line_speed * maxCfg) / 100;
6825                 } else {        /* SD mode */
6826                         uint16_t vn_max_rate = maxCfg * 100;
6827
6828                         if (vn_max_rate < line_speed) {
6829                                 line_speed = vn_max_rate;
6830                         }
6831                 }
6832         }
6833
6834         return line_speed;
6835 }
6836
6837 static void
6838 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6839 {
6840         uint16_t line_speed = bnx2x_get_mf_speed(sc);
6841
6842         memset(data, 0, sizeof(*data));
6843
6844         /* fill the report data with the effective line speed */
6845         data->line_speed = line_speed;
6846
6847         /* Link is down */
6848         if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6849                 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6850                             &data->link_report_flags);
6851         }
6852
6853         /* Full DUPLEX */
6854         if (sc->link_vars.duplex == DUPLEX_FULL) {
6855                 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6856                             &data->link_report_flags);
6857         }
6858
6859         /* Rx Flow Control is ON */
6860         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6861                 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6862         }
6863
6864         /* Tx Flow Control is ON */
6865         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6866                 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6867         }
6868 }
6869
6870 /* report link status to OS, should be called under phy_lock */
6871 static void bnx2x_link_report(struct bnx2x_softc *sc)
6872 {
6873         struct bnx2x_link_report_data cur_data;
6874
6875         /* reread mf_cfg */
6876         if (IS_PF(sc)) {
6877                 bnx2x_read_mf_cfg(sc);
6878         }
6879
6880         /* Read the current link report info */
6881         bnx2x_fill_report_data(sc, &cur_data);
6882
6883         /* Don't report link down or exactly the same link status twice */
6884         if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6885             (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6886                           &sc->last_reported_link.link_report_flags) &&
6887              bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6888                           &cur_data.link_report_flags))) {
6889                 return;
6890         }
6891
6892         sc->link_cnt++;
6893
6894         /* report new link params and remember the state for the next time */
6895         (void)rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6896
6897         if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6898                          &cur_data.link_report_flags)) {
6899                 PMD_DRV_LOG(INFO, "NIC Link is Down");
6900         } else {
6901                 __rte_unused const char *duplex;
6902                 __rte_unused const char *flow;
6903
6904                 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6905                                            &cur_data.link_report_flags)) {
6906                         duplex = "full";
6907                 } else {
6908                         duplex = "half";
6909                 }
6910
6911 /*
6912  * Handle the FC at the end so that only these flags would be
6913  * possibly set. This way we may easily check if there is no FC
6914  * enabled.
6915  */
6916                 if (cur_data.link_report_flags) {
6917                         if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6918                                          &cur_data.link_report_flags) &&
6919                             bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6920                                          &cur_data.link_report_flags)) {
6921                                 flow = "ON - receive & transmit";
6922                         } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6923                                                 &cur_data.link_report_flags) &&
6924                                    !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6925                                                  &cur_data.link_report_flags)) {
6926                                 flow = "ON - receive";
6927                         } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6928                                                  &cur_data.link_report_flags) &&
6929                                    bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6930                                                 &cur_data.link_report_flags)) {
6931                                 flow = "ON - transmit";
6932                         } else {
6933                                 flow = "none";  /* possible? */
6934                         }
6935                 } else {
6936                         flow = "none";
6937                 }
6938
6939                 PMD_DRV_LOG(INFO,
6940                             "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6941                             cur_data.line_speed, duplex, flow);
6942         }
6943 }
6944
6945 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6946 {
6947         if (sc->state != BNX2X_STATE_OPEN) {
6948                 return;
6949         }
6950
6951         if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
6952                 elink_link_status_update(&sc->link_params, &sc->link_vars);
6953         } else {
6954                 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
6955                                           ELINK_SUPPORTED_10baseT_Full |
6956                                           ELINK_SUPPORTED_100baseT_Half |
6957                                           ELINK_SUPPORTED_100baseT_Full |
6958                                           ELINK_SUPPORTED_1000baseT_Full |
6959                                           ELINK_SUPPORTED_2500baseX_Full |
6960                                           ELINK_SUPPORTED_10000baseT_Full |
6961                                           ELINK_SUPPORTED_TP |
6962                                           ELINK_SUPPORTED_FIBRE |
6963                                           ELINK_SUPPORTED_Autoneg |
6964                                           ELINK_SUPPORTED_Pause |
6965                                           ELINK_SUPPORTED_Asym_Pause);
6966                 sc->port.advertising[0] = sc->port.supported[0];
6967
6968                 sc->link_params.sc = sc;
6969                 sc->link_params.port = SC_PORT(sc);
6970                 sc->link_params.req_duplex[0] = DUPLEX_FULL;
6971                 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
6972                 sc->link_params.req_line_speed[0] = SPEED_10000;
6973                 sc->link_params.speed_cap_mask[0] = 0x7f0000;
6974                 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
6975
6976                 if (CHIP_REV_IS_FPGA(sc)) {
6977                         sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
6978                         sc->link_vars.line_speed = ELINK_SPEED_1000;
6979                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6980                                                      LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
6981                 } else {
6982                         sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
6983                         sc->link_vars.line_speed = ELINK_SPEED_10000;
6984                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6985                                                      LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
6986                 }
6987
6988                 sc->link_vars.link_up = 1;
6989
6990                 sc->link_vars.duplex = DUPLEX_FULL;
6991                 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
6992
6993                 if (IS_PF(sc)) {
6994                         REG_WR(sc,
6995                                NIG_REG_EGRESS_DRAIN0_MODE +
6996                                sc->link_params.port * 4, 0);
6997                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6998                         bnx2x_link_report(sc);
6999                 }
7000         }
7001
7002         if (IS_PF(sc)) {
7003                 if (sc->link_vars.link_up) {
7004                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7005                 } else {
7006                         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7007                 }
7008                 bnx2x_link_report(sc);
7009         } else {
7010                 bnx2x_link_report(sc);
7011                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7012         }
7013 }
7014
7015 static void bnx2x_periodic_start(struct bnx2x_softc *sc)
7016 {
7017         atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
7018 }
7019
7020 static void bnx2x_periodic_stop(struct bnx2x_softc *sc)
7021 {
7022         atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
7023 }
7024
7025 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7026 {
7027         int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7028         uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7029         struct elink_params *lp = &sc->link_params;
7030
7031         bnx2x_set_requested_fc(sc);
7032
7033         if (CHIP_REV_IS_SLOW(sc)) {
7034                 uint32_t bond = CHIP_BOND_ID(sc);
7035                 uint32_t feat = 0;
7036
7037                 if (CHIP_IS_E2(sc) && CHIP_IS_MODE_4_PORT(sc)) {
7038                         feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
7039                 } else if (bond & 0x4) {
7040                         if (CHIP_IS_E3(sc)) {
7041                                 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC;
7042                         } else {
7043                                 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
7044                         }
7045                 } else if (bond & 0x8) {
7046                         if (CHIP_IS_E3(sc)) {
7047                                 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC;
7048                         } else {
7049                                 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
7050                         }
7051                 }
7052
7053 /* disable EMAC for E3 and above */
7054                 if (bond & 0x2) {
7055                         feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
7056                 }
7057
7058                 sc->link_params.feature_config_flags |= feat;
7059         }
7060
7061         if (load_mode == LOAD_DIAG) {
7062                 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7063 /* Prefer doing PHY loopback at 10G speed, if possible */
7064                 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7065                         if (lp->speed_cap_mask[cfg_idx] &
7066                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7067                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7068                         } else {
7069                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7070                         }
7071                 }
7072         }
7073
7074         if (load_mode == LOAD_LOOPBACK_EXT) {
7075                 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7076         }
7077
7078         rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7079
7080         bnx2x_calc_fc_adv(sc);
7081
7082         if (sc->link_vars.link_up) {
7083                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7084                 bnx2x_link_report(sc);
7085         }
7086
7087         if (!CHIP_REV_IS_SLOW(sc)) {
7088                 bnx2x_periodic_start(sc);
7089         }
7090
7091         sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7092         return rc;
7093 }
7094
7095 /* update flags in shmem */
7096 static void
7097 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7098 {
7099         uint32_t drv_flags;
7100
7101         if (SHMEM2_HAS(sc, drv_flags)) {
7102                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7103                 drv_flags = SHMEM2_RD(sc, drv_flags);
7104
7105                 if (set) {
7106                         drv_flags |= flags;
7107                 } else {
7108                         drv_flags &= ~flags;
7109                 }
7110
7111                 SHMEM2_WR(sc, drv_flags, drv_flags);
7112
7113                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7114         }
7115 }
7116
7117 /* periodic timer callout routine, only runs when the interface is up */
7118 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7119 {
7120         if ((sc->state != BNX2X_STATE_OPEN) ||
7121             (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7122                 PMD_DRV_LOG(WARNING, "periodic callout exit (state=0x%x)",
7123                             sc->state);
7124                 return;
7125         }
7126         if (!CHIP_REV_IS_SLOW(sc)) {
7127 /*
7128  * This barrier is needed to ensure the ordering between the writing
7129  * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7130  * the reading here.
7131  */
7132                 mb();
7133                 if (sc->port.pmf) {
7134                         elink_period_func(&sc->link_params, &sc->link_vars);
7135                 }
7136         }
7137 #ifdef BNX2X_PULSE
7138         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7139                 int mb_idx = SC_FW_MB_IDX(sc);
7140                 uint32_t drv_pulse;
7141                 uint32_t mcp_pulse;
7142
7143                 ++sc->fw_drv_pulse_wr_seq;
7144                 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7145
7146                 drv_pulse = sc->fw_drv_pulse_wr_seq;
7147                 bnx2x_drv_pulse(sc);
7148
7149                 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7150                              MCP_PULSE_SEQ_MASK);
7151
7152 /*
7153  * The delta between driver pulse and mcp response should
7154  * be 1 (before mcp response) or 0 (after mcp response).
7155  */
7156                 if ((drv_pulse != mcp_pulse) &&
7157                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7158                         /* someone lost a heartbeat... */
7159                         PMD_DRV_LOG(ERR,
7160                                     "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7161                                     drv_pulse, mcp_pulse);
7162                 }
7163         }
7164 #endif
7165 }
7166
7167 /* start the controller */
7168 static __attribute__ ((noinline))
7169 int bnx2x_nic_load(struct bnx2x_softc *sc)
7170 {
7171         uint32_t val;
7172         uint32_t load_code = 0;
7173         int i, rc = 0;
7174
7175         PMD_INIT_FUNC_TRACE();
7176
7177         sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7178
7179         if (IS_PF(sc)) {
7180 /* must be called before memory allocation and HW init */
7181                 bnx2x_ilt_set_info(sc);
7182         }
7183
7184         bnx2x_set_fp_rx_buf_size(sc);
7185
7186         if (IS_PF(sc)) {
7187                 if (bnx2x_alloc_mem(sc) != 0) {
7188                         sc->state = BNX2X_STATE_CLOSED;
7189                         rc = -ENOMEM;
7190                         goto bnx2x_nic_load_error0;
7191                 }
7192         }
7193
7194         if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7195                 sc->state = BNX2X_STATE_CLOSED;
7196                 rc = -ENOMEM;
7197                 goto bnx2x_nic_load_error0;
7198         }
7199
7200         if (IS_VF(sc)) {
7201                 rc = bnx2x_vf_init(sc);
7202                 if (rc) {
7203                         sc->state = BNX2X_STATE_ERROR;
7204                         goto bnx2x_nic_load_error0;
7205                 }
7206         }
7207
7208         if (IS_PF(sc)) {
7209 /* set pf load just before approaching the MCP */
7210                 bnx2x_set_pf_load(sc);
7211
7212 /* if MCP exists send load request and analyze response */
7213                 if (!BNX2X_NOMCP(sc)) {
7214                         /* attempt to load pf */
7215                         if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7216                                 sc->state = BNX2X_STATE_CLOSED;
7217                                 rc = -ENXIO;
7218                                 goto bnx2x_nic_load_error1;
7219                         }
7220
7221                         /* what did the MCP say? */
7222                         if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7223                                 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7224                                 sc->state = BNX2X_STATE_CLOSED;
7225                                 rc = -ENXIO;
7226                                 goto bnx2x_nic_load_error2;
7227                         }
7228                 } else {
7229                         PMD_DRV_LOG(INFO, "Device has no MCP!");
7230                         load_code = bnx2x_nic_load_no_mcp(sc);
7231                 }
7232
7233 /* mark PMF if applicable */
7234                 bnx2x_nic_load_pmf(sc, load_code);
7235
7236 /* Init Function state controlling object */
7237                 bnx2x_init_func_obj(sc);
7238
7239 /* Initialize HW */
7240                 if (bnx2x_init_hw(sc, load_code) != 0) {
7241                         PMD_DRV_LOG(NOTICE, "HW init failed");
7242                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7243                         sc->state = BNX2X_STATE_CLOSED;
7244                         rc = -ENXIO;
7245                         goto bnx2x_nic_load_error2;
7246                 }
7247         }
7248
7249         bnx2x_nic_init(sc, load_code);
7250
7251         /* Init per-function objects */
7252         if (IS_PF(sc)) {
7253                 bnx2x_init_objs(sc);
7254
7255 /* set AFEX default VLAN tag to an invalid value */
7256                 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7257
7258                 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7259                 rc = bnx2x_func_start(sc);
7260                 if (rc) {
7261                         PMD_DRV_LOG(NOTICE, "Function start failed!");
7262                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7263                         sc->state = BNX2X_STATE_ERROR;
7264                         goto bnx2x_nic_load_error3;
7265                 }
7266
7267 /* send LOAD_DONE command to MCP */
7268                 if (!BNX2X_NOMCP(sc)) {
7269                         load_code =
7270                             bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7271                         if (!load_code) {
7272                                 PMD_DRV_LOG(NOTICE,
7273                                             "MCP response failure, aborting");
7274                                 sc->state = BNX2X_STATE_ERROR;
7275                                 rc = -ENXIO;
7276                                 goto bnx2x_nic_load_error3;
7277                         }
7278                 }
7279         }
7280
7281         rc = bnx2x_setup_leading(sc);
7282         if (rc) {
7283                 PMD_DRV_LOG(NOTICE, "Setup leading failed!");
7284                 sc->state = BNX2X_STATE_ERROR;
7285                 goto bnx2x_nic_load_error3;
7286         }
7287
7288         FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7289                 if (IS_PF(sc))
7290                         rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7291                 else            /* IS_VF(sc) */
7292                         rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7293
7294                 if (rc) {
7295                         PMD_DRV_LOG(NOTICE, "Queue(%d) setup failed", i);
7296                         sc->state = BNX2X_STATE_ERROR;
7297                         goto bnx2x_nic_load_error3;
7298                 }
7299         }
7300
7301         rc = bnx2x_init_rss_pf(sc);
7302         if (rc) {
7303                 PMD_DRV_LOG(NOTICE, "PF RSS init failed");
7304                 sc->state = BNX2X_STATE_ERROR;
7305                 goto bnx2x_nic_load_error3;
7306         }
7307
7308         /* now when Clients are configured we are ready to work */
7309         sc->state = BNX2X_STATE_OPEN;
7310
7311         /* Configure a ucast MAC */
7312         if (IS_PF(sc)) {
7313                 rc = bnx2x_set_eth_mac(sc, TRUE);
7314         } else {                /* IS_VF(sc) */
7315                 rc = bnx2x_vf_set_mac(sc, TRUE);
7316         }
7317
7318         if (rc) {
7319                 PMD_DRV_LOG(NOTICE, "Setting Ethernet MAC failed");
7320                 sc->state = BNX2X_STATE_ERROR;
7321                 goto bnx2x_nic_load_error3;
7322         }
7323
7324         if (sc->port.pmf) {
7325                 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7326                 if (rc) {
7327                         sc->state = BNX2X_STATE_ERROR;
7328                         goto bnx2x_nic_load_error3;
7329                 }
7330         }
7331
7332         sc->link_params.feature_config_flags &=
7333             ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7334
7335         /* start the Tx */
7336         switch (LOAD_OPEN) {
7337         case LOAD_NORMAL:
7338         case LOAD_OPEN:
7339                 break;
7340
7341         case LOAD_DIAG:
7342         case LOAD_LOOPBACK_EXT:
7343                 sc->state = BNX2X_STATE_DIAG;
7344                 break;
7345
7346         default:
7347                 break;
7348         }
7349
7350         if (sc->port.pmf) {
7351                 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7352         } else {
7353                 bnx2x_link_status_update(sc);
7354         }
7355
7356         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7357 /* mark driver is loaded in shmem2 */
7358                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7359                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7360                           (val |
7361                            DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7362                            DRV_FLAGS_CAPABILITIES_LOADED_L2));
7363         }
7364
7365         /* start fast path */
7366         /* Initialize Rx filter */
7367         bnx2x_set_rx_mode(sc);
7368
7369         /* wait for all pending SP commands to complete */
7370         if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7371                 PMD_DRV_LOG(NOTICE, "Timeout waiting for all SPs to complete!");
7372                 bnx2x_periodic_stop(sc);
7373                 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7374                 return -ENXIO;
7375         }
7376
7377         PMD_DRV_LOG(DEBUG, "NIC successfully loaded");
7378
7379         return 0;
7380
7381 bnx2x_nic_load_error3:
7382
7383         if (IS_PF(sc)) {
7384                 bnx2x_int_disable_sync(sc, 1);
7385
7386 /* clean out queued objects */
7387                 bnx2x_squeeze_objects(sc);
7388         }
7389
7390 bnx2x_nic_load_error2:
7391
7392         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7393                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7394                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7395         }
7396
7397         sc->port.pmf = 0;
7398
7399 bnx2x_nic_load_error1:
7400
7401         /* clear pf_load status, as it was already set */
7402         if (IS_PF(sc)) {
7403                 bnx2x_clear_pf_load(sc);
7404         }
7405
7406 bnx2x_nic_load_error0:
7407
7408         bnx2x_free_fw_stats_mem(sc);
7409         bnx2x_free_mem(sc);
7410
7411         return rc;
7412 }
7413
7414 /*
7415 * Handles controller initialization.
7416 */
7417 int bnx2x_init(struct bnx2x_softc *sc)
7418 {
7419         int other_engine = SC_PATH(sc) ? 0 : 1;
7420         uint8_t other_load_status, load_status;
7421         uint8_t global = FALSE;
7422         int rc;
7423
7424         /* Check if the driver is still running and bail out if it is. */
7425         if (sc->link_vars.link_up) {
7426                 PMD_DRV_LOG(DEBUG, "Init called while driver is running!");
7427                 rc = 0;
7428                 goto bnx2x_init_done;
7429         }
7430
7431         bnx2x_set_power_state(sc, PCI_PM_D0);
7432
7433         /*
7434          * If parity occurred during the unload, then attentions and/or
7435          * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7436          * loaded on the current engine to complete the recovery. Parity recovery
7437          * is only relevant for PF driver.
7438          */
7439         if (IS_PF(sc)) {
7440                 other_load_status = bnx2x_get_load_status(sc, other_engine);
7441                 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7442
7443                 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7444                     bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7445                         do {
7446                                 /*
7447                                  * If there are attentions and they are in global blocks, set
7448                                  * the GLOBAL_RESET bit regardless whether it will be this
7449                                  * function that will complete the recovery or not.
7450                                  */
7451                                 if (global) {
7452                                         bnx2x_set_reset_global(sc);
7453                                 }
7454
7455                                 /*
7456                                  * Only the first function on the current engine should try
7457                                  * to recover in open. In case of attentions in global blocks
7458                                  * only the first in the chip should try to recover.
7459                                  */
7460                                 if ((!load_status
7461                                      && (!global ||!other_load_status))
7462                                     && bnx2x_trylock_leader_lock(sc)
7463                                     && !bnx2x_leader_reset(sc)) {
7464                                         PMD_DRV_LOG(INFO,
7465                                                     "Recovered during init");
7466                                         break;
7467                                 }
7468
7469                                 /* recovery has failed... */
7470                                 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7471
7472                                 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7473
7474                                 PMD_DRV_LOG(NOTICE,
7475                                             "Recovery flow hasn't properly "
7476                                             "completed yet, try again later. "
7477                                             "If you still see this message after a "
7478                                             "few retries then power cycle is required.");
7479
7480                                 rc = -ENXIO;
7481                                 goto bnx2x_init_done;
7482                         } while (0);
7483                 }
7484         }
7485
7486         sc->recovery_state = BNX2X_RECOVERY_DONE;
7487
7488         rc = bnx2x_nic_load(sc);
7489
7490 bnx2x_init_done:
7491
7492         if (rc) {
7493                 PMD_DRV_LOG(NOTICE, "Initialization failed, "
7494                             "stack notified driver is NOT running!");
7495         }
7496
7497         return rc;
7498 }
7499
7500 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7501 {
7502         uint32_t val = 0;
7503
7504         /*
7505          * Read the ME register to get the function number. The ME register
7506          * holds the relative-function number and absolute-function number. The
7507          * absolute-function number appears only in E2 and above. Before that
7508          * these bits always contained zero, therefore we cannot blindly use them.
7509          */
7510
7511         val = REG_RD(sc, BAR_ME_REGISTER);
7512
7513         sc->pfunc_rel =
7514             (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7515         sc->path_id =
7516             (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7517             1;
7518
7519         if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7520                 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7521         } else {
7522                 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7523         }
7524
7525         PMD_DRV_LOG(DEBUG,
7526                     "Relative function %d, Absolute function %d, Path %d",
7527                     sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7528 }
7529
7530 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7531 {
7532         uint32_t shmem2_size;
7533         uint32_t offset;
7534         uint32_t mf_cfg_offset_value;
7535
7536         /* Non 57712 */
7537         offset = (SHMEM_ADDR(sc, func_mb) +
7538                   (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7539
7540         /* 57712 plus */
7541         if (sc->devinfo.shmem2_base != 0) {
7542                 shmem2_size = SHMEM2_RD(sc, size);
7543                 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7544                         mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7545                         if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7546                                 offset = mf_cfg_offset_value;
7547                         }
7548                 }
7549         }
7550
7551         return offset;
7552 }
7553
7554 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7555 {
7556         uint32_t ret;
7557         struct bnx2x_pci_cap *caps;
7558
7559         /* ensure PCIe capability is enabled */
7560         caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7561         if (NULL != caps) {
7562                 PMD_DRV_LOG(DEBUG, "Found PCIe capability: "
7563                             "id=0x%04X type=0x%04X addr=0x%08X",
7564                             caps->id, caps->type, caps->addr);
7565                 pci_read(sc, (caps->addr + reg), &ret, 2);
7566                 return ret;
7567         }
7568
7569         PMD_DRV_LOG(WARNING, "PCIe capability NOT FOUND!!!");
7570
7571         return 0;
7572 }
7573
7574 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7575 {
7576         return (bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7577                 PCIM_EXP_STA_TRANSACTION_PND);
7578 }
7579
7580 /*
7581 * Walk the PCI capabiites list for the device to find what features are
7582 * supported. These capabilites may be enabled/disabled by firmware so it's
7583 * best to walk the list rather than make assumptions.
7584 */
7585 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7586 {
7587         PMD_INIT_FUNC_TRACE();
7588
7589         struct bnx2x_pci_cap *caps;
7590         uint16_t link_status;
7591 #ifdef RTE_LIBRTE_BNX2X_DEBUG
7592         int reg = 0;
7593 #endif
7594
7595         /* check if PCI Power Management is enabled */
7596         caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7597         if (NULL != caps) {
7598                 PMD_DRV_LOG(DEBUG, "Found PM capability: "
7599                             "id=0x%04X type=0x%04X addr=0x%08X",
7600                             caps->id, caps->type, caps->addr);
7601
7602                 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7603                 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7604         }
7605
7606         link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7607
7608         sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7609         sc->devinfo.pcie_link_width =
7610             ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7611
7612         PMD_DRV_LOG(DEBUG, "PCIe link speed=%d width=%d",
7613                     sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7614
7615         sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7616
7617         /* check if MSI capability is enabled */
7618         caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7619         if (NULL != caps) {
7620                 PMD_DRV_LOG(DEBUG, "Found MSI capability at 0x%04x", reg);
7621
7622                 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7623                 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7624         }
7625
7626         /* check if MSI-X capability is enabled */
7627         caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7628         if (NULL != caps) {
7629                 PMD_DRV_LOG(DEBUG, "Found MSI-X capability at 0x%04x", reg);
7630
7631                 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7632                 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7633         }
7634 }
7635
7636 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7637 {
7638         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7639         uint32_t val;
7640
7641         /* get the outer vlan if we're in switch-dependent mode */
7642
7643         val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7644         mf_info->ext_id = (uint16_t) val;
7645
7646         mf_info->multi_vnics_mode = 1;
7647
7648         if (!VALID_OVLAN(mf_info->ext_id)) {
7649                 PMD_DRV_LOG(NOTICE, "Invalid VLAN (%d)", mf_info->ext_id);
7650                 return 1;
7651         }
7652
7653         /* get the capabilities */
7654         if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7655             FUNC_MF_CFG_PROTOCOL_ISCSI) {
7656                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7657         } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7658                    == FUNC_MF_CFG_PROTOCOL_FCOE) {
7659                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7660         } else {
7661                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7662         }
7663
7664         mf_info->vnics_per_port =
7665             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7666
7667         return 0;
7668 }
7669
7670 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7671 {
7672         uint32_t retval = 0;
7673         uint32_t val;
7674
7675         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7676
7677         if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7678                 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7679                         retval |= MF_PROTO_SUPPORT_ETHERNET;
7680                 }
7681                 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7682                         retval |= MF_PROTO_SUPPORT_ISCSI;
7683                 }
7684                 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7685                         retval |= MF_PROTO_SUPPORT_FCOE;
7686                 }
7687         }
7688
7689         return retval;
7690 }
7691
7692 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7693 {
7694         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7695         uint32_t val;
7696
7697         /*
7698          * There is no outer vlan if we're in switch-independent mode.
7699          * If the mac is valid then assume multi-function.
7700          */
7701
7702         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7703
7704         mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7705
7706         mf_info->mf_protos_supported =
7707             bnx2x_get_shmem_ext_proto_support_flags(sc);
7708
7709         mf_info->vnics_per_port =
7710             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7711
7712         return 0;
7713 }
7714
7715 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7716 {
7717         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7718         uint32_t e1hov_tag;
7719         uint32_t func_config;
7720         uint32_t niv_config;
7721
7722         mf_info->multi_vnics_mode = 1;
7723
7724         e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7725         func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7726         niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7727
7728         mf_info->ext_id =
7729             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7730                         FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7731
7732         mf_info->default_vlan =
7733             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7734                         FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7735
7736         mf_info->niv_allowed_priorities =
7737             (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7738                        FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7739
7740         mf_info->niv_default_cos =
7741             (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7742                        FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7743
7744         mf_info->afex_vlan_mode =
7745             ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7746              FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7747
7748         mf_info->niv_mba_enabled =
7749             ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7750              FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7751
7752         mf_info->mf_protos_supported =
7753             bnx2x_get_shmem_ext_proto_support_flags(sc);
7754
7755         mf_info->vnics_per_port =
7756             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7757
7758         return 0;
7759 }
7760
7761 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7762 {
7763         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7764         uint32_t mf_cfg1;
7765         uint32_t mf_cfg2;
7766         uint32_t ovlan1;
7767         uint32_t ovlan2;
7768         uint8_t i, j;
7769
7770         /* various MF mode sanity checks... */
7771
7772         if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7773                 PMD_DRV_LOG(NOTICE,
7774                             "Enumerated function %d is marked as hidden",
7775                             SC_PORT(sc));
7776                 return 1;
7777         }
7778
7779         if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7780                 PMD_DRV_LOG(NOTICE, "vnics_per_port=%d multi_vnics_mode=%d",
7781                             mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7782                 return 1;
7783         }
7784
7785         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7786 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7787                 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7788                         PMD_DRV_LOG(NOTICE, "mf_mode=SD vnic_id=%d ovlan=%d",
7789                                     SC_VN(sc), OVLAN(sc));
7790                         return 1;
7791                 }
7792
7793                 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7794                         PMD_DRV_LOG(NOTICE,
7795                                     "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7796                                     mf_info->multi_vnics_mode, OVLAN(sc));
7797                         return 1;
7798                 }
7799
7800 /*
7801  * Verify all functions are either MF or SF mode. If MF, make sure
7802  * sure that all non-hidden functions have a valid ovlan. If SF,
7803  * make sure that all non-hidden functions have an invalid ovlan.
7804  */
7805                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7806                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7807                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7808                         if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7809                             (((mf_info->multi_vnics_mode)
7810                               && !VALID_OVLAN(ovlan1))
7811                              || ((!mf_info->multi_vnics_mode)
7812                                  && VALID_OVLAN(ovlan1)))) {
7813                                 PMD_DRV_LOG(NOTICE,
7814                                             "mf_mode=SD function %d MF config "
7815                                             "mismatch, multi_vnics_mode=%d ovlan=%d",
7816                                             i, mf_info->multi_vnics_mode,
7817                                             ovlan1);
7818                                 return 1;
7819                         }
7820                 }
7821
7822 /* Verify all funcs on the same port each have a different ovlan. */
7823                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7824                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7825                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7826                         /* iterate from the next function on the port to the max func */
7827                         for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7828                                 mf_cfg2 =
7829                                     MFCFG_RD(sc, func_mf_config[j].config);
7830                                 ovlan2 =
7831                                     MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7832                                 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7833                                     && VALID_OVLAN(ovlan1)
7834                                     && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7835                                     && VALID_OVLAN(ovlan2)
7836                                     && (ovlan1 == ovlan2)) {
7837                                         PMD_DRV_LOG(NOTICE,
7838                                                     "mf_mode=SD functions %d and %d "
7839                                                     "have the same ovlan (%d)",
7840                                                     i, j, ovlan1);
7841                                         return 1;
7842                                 }
7843                         }
7844                 }
7845         }
7846         /* MULTI_FUNCTION_SD */
7847         return 0;
7848 }
7849
7850 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7851 {
7852         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7853         uint32_t val, mac_upper;
7854         uint8_t i, vnic;
7855
7856         /* initialize mf_info defaults */
7857         mf_info->vnics_per_port = 1;
7858         mf_info->multi_vnics_mode = FALSE;
7859         mf_info->path_has_ovlan = FALSE;
7860         mf_info->mf_mode = SINGLE_FUNCTION;
7861
7862         if (!CHIP_IS_MF_CAP(sc)) {
7863                 return 0;
7864         }
7865
7866         if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7867                 PMD_DRV_LOG(NOTICE, "Invalid mf_cfg_base!");
7868                 return 1;
7869         }
7870
7871         /* get the MF mode (switch dependent / independent / single-function) */
7872
7873         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7874
7875         switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7876         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7877
7878                 mac_upper =
7879                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7880
7881                 /* check for legal upper mac bytes */
7882                 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7883                         mf_info->mf_mode = MULTI_FUNCTION_SI;
7884                 } else {
7885                         PMD_DRV_LOG(NOTICE,
7886                                     "Invalid config for Switch Independent mode");
7887                 }
7888
7889                 break;
7890
7891         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7892         case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7893
7894                 /* get outer vlan configuration */
7895                 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7896
7897                 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7898                     FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7899                         mf_info->mf_mode = MULTI_FUNCTION_SD;
7900                 } else {
7901                         PMD_DRV_LOG(NOTICE,
7902                                     "Invalid config for Switch Dependent mode");
7903                 }
7904
7905                 break;
7906
7907         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7908
7909                 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7910                 return 0;
7911
7912         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7913
7914                 /*
7915                  * Mark MF mode as NIV if MCP version includes NPAR-SD support
7916                  * and the MAC address is valid.
7917                  */
7918                 mac_upper =
7919                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7920
7921                 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7922                     (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7923                         mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7924                 } else {
7925                         PMD_DRV_LOG(NOTICE, "Invalid config for AFEX mode");
7926                 }
7927
7928                 break;
7929
7930         default:
7931
7932                 PMD_DRV_LOG(NOTICE, "Unknown MF mode (0x%08x)",
7933                             (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7934
7935                 return 1;
7936         }
7937
7938         /* set path mf_mode (which could be different than function mf_mode) */
7939         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7940                 mf_info->path_has_ovlan = TRUE;
7941         } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7942 /*
7943  * Decide on path multi vnics mode. If we're not in MF mode and in
7944  * 4-port mode, this is good enough to check vnic-0 of the other port
7945  * on the same path
7946  */
7947                 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7948                         uint8_t other_port = !(PORT_ID(sc) & 1);
7949                         uint8_t abs_func_other_port =
7950                             (SC_PATH(sc) + (2 * other_port));
7951
7952                         val =
7953                             MFCFG_RD(sc,
7954                                      func_mf_config
7955                                      [abs_func_other_port].e1hov_tag);
7956
7957                         mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7958                 }
7959         }
7960
7961         if (mf_info->mf_mode == SINGLE_FUNCTION) {
7962 /* invalid MF config */
7963                 if (SC_VN(sc) >= 1) {
7964                         PMD_DRV_LOG(NOTICE, "VNIC ID >= 1 in SF mode");
7965                         return 1;
7966                 }
7967
7968                 return 0;
7969         }
7970
7971         /* get the MF configuration */
7972         mf_info->mf_config[SC_VN(sc)] =
7973             MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7974
7975         switch (mf_info->mf_mode) {
7976         case MULTI_FUNCTION_SD:
7977
7978                 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7979                 break;
7980
7981         case MULTI_FUNCTION_SI:
7982
7983                 bnx2x_get_shmem_mf_cfg_info_si(sc);
7984                 break;
7985
7986         case MULTI_FUNCTION_AFEX:
7987
7988                 bnx2x_get_shmem_mf_cfg_info_niv(sc);
7989                 break;
7990
7991         default:
7992
7993                 PMD_DRV_LOG(NOTICE, "Get MF config failed (mf_mode=0x%08x)",
7994                             mf_info->mf_mode);
7995                 return 1;
7996         }
7997
7998         /* get the congestion management parameters */
7999
8000         vnic = 0;
8001         FOREACH_ABS_FUNC_IN_PORT(sc, i) {
8002 /* get min/max bw */
8003                 val = MFCFG_RD(sc, func_mf_config[i].config);
8004                 mf_info->min_bw[vnic] =
8005                     ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
8006                      FUNC_MF_CFG_MIN_BW_SHIFT);
8007                 mf_info->max_bw[vnic] =
8008                     ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
8009                      FUNC_MF_CFG_MAX_BW_SHIFT);
8010                 vnic++;
8011         }
8012
8013         return bnx2x_check_valid_mf_cfg(sc);
8014 }
8015
8016 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8017 {
8018         int port;
8019         uint32_t mac_hi, mac_lo, val;
8020
8021         PMD_INIT_FUNC_TRACE();
8022
8023         port = SC_PORT(sc);
8024         mac_hi = mac_lo = 0;
8025
8026         sc->link_params.sc = sc;
8027         sc->link_params.port = port;
8028
8029         /* get the hardware config info */
8030         sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8031         sc->devinfo.hw_config2 =
8032             SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8033
8034         sc->link_params.hw_led_mode =
8035             ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8036              SHARED_HW_CFG_LED_MODE_SHIFT);
8037
8038         /* get the port feature config */
8039         sc->port.config =
8040             SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8041
8042         /* get the link params */
8043         sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8044             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8045             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8046         sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8047             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8048             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8049
8050         /* get the lane config */
8051         sc->link_params.lane_config =
8052             SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8053
8054         /* get the link config */
8055         val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8056         sc->port.link_config[ELINK_INT_PHY] = val;
8057         sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8058         sc->port.link_config[ELINK_EXT_PHY1] =
8059             SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8060
8061         /* get the override preemphasis flag and enable it or turn it off */
8062         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8063         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8064                 sc->link_params.feature_config_flags |=
8065                     ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8066         } else {
8067                 sc->link_params.feature_config_flags &=
8068                     ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8069         }
8070
8071         /* get the initial value of the link params */
8072         sc->link_params.multi_phy_config =
8073             SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8074
8075         /* get external phy info */
8076         sc->port.ext_phy_config =
8077             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8078
8079         /* get the multifunction configuration */
8080         bnx2x_get_mf_cfg_info(sc);
8081
8082         /* get the mac address */
8083         if (IS_MF(sc)) {
8084                 mac_hi =
8085                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8086                 mac_lo =
8087                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8088         } else {
8089                 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8090                 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8091         }
8092
8093         if ((mac_lo == 0) && (mac_hi == 0)) {
8094                 *sc->mac_addr_str = 0;
8095                 PMD_DRV_LOG(NOTICE, "No Ethernet address programmed!");
8096         } else {
8097                 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8098                 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8099                 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8100                 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8101                 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8102                 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8103                 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8104                          "%02x:%02x:%02x:%02x:%02x:%02x",
8105                          sc->link_params.mac_addr[0],
8106                          sc->link_params.mac_addr[1],
8107                          sc->link_params.mac_addr[2],
8108                          sc->link_params.mac_addr[3],
8109                          sc->link_params.mac_addr[4],
8110                          sc->link_params.mac_addr[5]);
8111                 PMD_DRV_LOG(DEBUG, "Ethernet address: %s", sc->mac_addr_str);
8112         }
8113
8114         return 0;
8115 }
8116
8117 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8118 {
8119         uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8120         switch (sc->link_params.phy[phy_idx].media_type) {
8121         case ELINK_ETH_PHY_SFPP_10G_FIBER:
8122         case ELINK_ETH_PHY_SFP_1G_FIBER:
8123         case ELINK_ETH_PHY_XFP_FIBER:
8124         case ELINK_ETH_PHY_KR:
8125         case ELINK_ETH_PHY_CX4:
8126                 PMD_DRV_LOG(INFO, "Found 10GBase-CX4 media.");
8127                 sc->media = IFM_10G_CX4;
8128                 break;
8129         case ELINK_ETH_PHY_DA_TWINAX:
8130                 PMD_DRV_LOG(INFO, "Found 10Gb Twinax media.");
8131                 sc->media = IFM_10G_TWINAX;
8132                 break;
8133         case ELINK_ETH_PHY_BASE_T:
8134                 PMD_DRV_LOG(INFO, "Found 10GBase-T media.");
8135                 sc->media = IFM_10G_T;
8136                 break;
8137         case ELINK_ETH_PHY_NOT_PRESENT:
8138                 PMD_DRV_LOG(INFO, "Media not present.");
8139                 sc->media = 0;
8140                 break;
8141         case ELINK_ETH_PHY_UNSPECIFIED:
8142         default:
8143                 PMD_DRV_LOG(INFO, "Unknown media!");
8144                 sc->media = 0;
8145                 break;
8146         }
8147 }
8148
8149 #define GET_FIELD(value, fname)                     \
8150 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8151 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8152 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8153
8154 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8155 {
8156         int pfid = SC_FUNC(sc);
8157         int igu_sb_id;
8158         uint32_t val;
8159         uint8_t fid, igu_sb_cnt = 0;
8160
8161         sc->igu_base_sb = 0xff;
8162
8163         if (CHIP_INT_MODE_IS_BC(sc)) {
8164                 int vn = SC_VN(sc);
8165                 igu_sb_cnt = sc->igu_sb_cnt;
8166                 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8167                                    FP_SB_MAX_E1x);
8168                 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8169                                   (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8170                 return 0;
8171         }
8172
8173         /* IGU in normal mode - read CAM */
8174         for (igu_sb_id = 0;
8175              igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8176                 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8177                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8178                         continue;
8179                 }
8180                 fid = IGU_FID(val);
8181                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8182                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8183                                 continue;
8184                         }
8185                         if (IGU_VEC(val) == 0) {
8186                                 /* default status block */
8187                                 sc->igu_dsb_id = igu_sb_id;
8188                         } else {
8189                                 if (sc->igu_base_sb == 0xff) {
8190                                         sc->igu_base_sb = igu_sb_id;
8191                                 }
8192                                 igu_sb_cnt++;
8193                         }
8194                 }
8195         }
8196
8197         /*
8198          * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8199          * that number of CAM entries will not be equal to the value advertised in
8200          * PCI. Driver should use the minimal value of both as the actual status
8201          * block count
8202          */
8203         sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8204
8205         if (igu_sb_cnt == 0) {
8206                 PMD_DRV_LOG(ERR, "CAM configuration error");
8207                 return -1;
8208         }
8209
8210         return 0;
8211 }
8212
8213 /*
8214 * Gather various information from the device config space, the device itself,
8215 * shmem, and the user input.
8216 */
8217 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8218 {
8219         uint32_t val;
8220         int rc;
8221
8222         /* get the chip revision (chip metal comes from pci config space) */
8223         sc->devinfo.chip_id = sc->link_params.chip_id =
8224             (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8225              ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8226              (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8227              ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8228
8229         /* force 57811 according to MISC register */
8230         if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8231                 if (CHIP_IS_57810(sc)) {
8232                         sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8233                                                (sc->
8234                                                 devinfo.chip_id & 0x0000ffff));
8235                 } else if (CHIP_IS_57810_MF(sc)) {
8236                         sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8237                                                (sc->
8238                                                 devinfo.chip_id & 0x0000ffff));
8239                 }
8240                 sc->devinfo.chip_id |= 0x1;
8241         }
8242
8243         PMD_DRV_LOG(DEBUG,
8244                     "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8245                     sc->devinfo.chip_id,
8246                     ((sc->devinfo.chip_id >> 16) & 0xffff),
8247                     ((sc->devinfo.chip_id >> 12) & 0xf),
8248                     ((sc->devinfo.chip_id >> 4) & 0xff),
8249                     ((sc->devinfo.chip_id >> 0) & 0xf));
8250
8251         val = (REG_RD(sc, 0x2874) & 0x55);
8252         if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8253                 sc->flags |= BNX2X_ONE_PORT_FLAG;
8254                 PMD_DRV_LOG(DEBUG, "single port device");
8255         }
8256
8257         /* set the doorbell size */
8258         sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8259
8260         /* determine whether the device is in 2 port or 4 port mode */
8261         sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE;       /* E1h */
8262         if (CHIP_IS_E2E3(sc)) {
8263 /*
8264  * Read port4mode_en_ovwr[0]:
8265  *   If 1, four port mode is in port4mode_en_ovwr[1].
8266  *   If 0, four port mode is in port4mode_en[0].
8267  */
8268                 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8269                 if (val & 1) {
8270                         val = ((val >> 1) & 1);
8271                 } else {
8272                         val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8273                 }
8274
8275                 sc->devinfo.chip_port_mode =
8276                     (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8277
8278                 PMD_DRV_LOG(DEBUG, "Port mode = %s", (val) ? "4" : "2");
8279         }
8280
8281         /* get the function and path info for the device */
8282         bnx2x_get_function_num(sc);
8283
8284         /* get the shared memory base address */
8285         sc->devinfo.shmem_base =
8286             sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8287         sc->devinfo.shmem2_base =
8288             REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8289                         MISC_REG_GENERIC_CR_0));
8290
8291         if (!sc->devinfo.shmem_base) {
8292 /* this should ONLY prevent upcoming shmem reads */
8293                 PMD_DRV_LOG(INFO, "MCP not active");
8294                 sc->flags |= BNX2X_NO_MCP_FLAG;
8295                 return 0;
8296         }
8297
8298         /* make sure the shared memory contents are valid */
8299         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8300         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8301             (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8302                 PMD_DRV_LOG(NOTICE, "Invalid SHMEM validity signature: 0x%08x",
8303                             val);
8304                 return 0;
8305         }
8306
8307         /* get the bootcode version */
8308         sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8309         snprintf(sc->devinfo.bc_ver_str,
8310                  sizeof(sc->devinfo.bc_ver_str),
8311                  "%d.%d.%d",
8312                  ((sc->devinfo.bc_ver >> 24) & 0xff),
8313                  ((sc->devinfo.bc_ver >> 16) & 0xff),
8314                  ((sc->devinfo.bc_ver >> 8) & 0xff));
8315         PMD_DRV_LOG(INFO, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8316
8317         /* get the bootcode shmem address */
8318         sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8319
8320         /* clean indirect addresses as they're not used */
8321         pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8322         if (IS_PF(sc)) {
8323                 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8324                 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8325                 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8326                 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8327                 if (CHIP_IS_E1x(sc)) {
8328                         REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8329                         REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8330                         REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8331                         REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8332                 }
8333
8334 /*
8335  * Enable internal target-read (in case we are probed after PF
8336  * FLR). Must be done prior to any BAR read access. Only for
8337  * 57712 and up
8338  */
8339                 if (!CHIP_IS_E1x(sc)) {
8340                         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
8341                                1);
8342                 }
8343         }
8344
8345         /* get the nvram size */
8346         val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8347         sc->devinfo.flash_size =
8348             (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8349
8350         bnx2x_set_power_state(sc, PCI_PM_D0);
8351         /* get various configuration parameters from shmem */
8352         bnx2x_get_shmem_info(sc);
8353
8354         /* initialize IGU parameters */
8355         if (CHIP_IS_E1x(sc)) {
8356                 sc->devinfo.int_block = INT_BLOCK_HC;
8357                 sc->igu_dsb_id = DEF_SB_IGU_ID;
8358                 sc->igu_base_sb = 0;
8359         } else {
8360                 sc->devinfo.int_block = INT_BLOCK_IGU;
8361
8362 /* do not allow device reset during IGU info preocessing */
8363                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8364
8365                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8366
8367                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8368                         int tout = 5000;
8369
8370                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8371                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8372                         REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8373
8374                         while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8375                                 tout--;
8376                                 DELAY(1000);
8377                         }
8378
8379                         if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8380                                 PMD_DRV_LOG(NOTICE,
8381                                             "FORCING IGU Normal Mode failed!!!");
8382                                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8383                                 return -1;
8384                         }
8385                 }
8386
8387                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8388                         PMD_DRV_LOG(DEBUG, "IGU Backward Compatible Mode");
8389                         sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8390                 } else {
8391                         PMD_DRV_LOG(DEBUG, "IGU Normal Mode");
8392                 }
8393
8394                 rc = bnx2x_get_igu_cam_info(sc);
8395
8396                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8397
8398                 if (rc) {
8399                         return rc;
8400                 }
8401         }
8402
8403         /*
8404          * Get base FW non-default (fast path) status block ID. This value is
8405          * used to initialize the fw_sb_id saved on the fp/queue structure to
8406          * determine the id used by the FW.
8407          */
8408         if (CHIP_IS_E1x(sc)) {
8409                 sc->base_fw_ndsb =
8410                     ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8411         } else {
8412 /*
8413  * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8414  * the same queue are indicated on the same IGU SB). So we prefer
8415  * FW and IGU SBs to be the same value.
8416  */
8417                 sc->base_fw_ndsb = sc->igu_base_sb;
8418         }
8419
8420         elink_phy_probe(&sc->link_params);
8421
8422         return 0;
8423 }
8424
8425 static void
8426 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8427 {
8428         uint32_t cfg_size = 0;
8429         uint32_t idx;
8430         uint8_t port = SC_PORT(sc);
8431
8432         /* aggregation of supported attributes of all external phys */
8433         sc->port.supported[0] = 0;
8434         sc->port.supported[1] = 0;
8435
8436         switch (sc->link_params.num_phys) {
8437         case 1:
8438                 sc->port.supported[0] =
8439                     sc->link_params.phy[ELINK_INT_PHY].supported;
8440                 cfg_size = 1;
8441                 break;
8442         case 2:
8443                 sc->port.supported[0] =
8444                     sc->link_params.phy[ELINK_EXT_PHY1].supported;
8445                 cfg_size = 1;
8446                 break;
8447         case 3:
8448                 if (sc->link_params.multi_phy_config &
8449                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8450                         sc->port.supported[1] =
8451                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8452                         sc->port.supported[0] =
8453                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8454                 } else {
8455                         sc->port.supported[0] =
8456                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8457                         sc->port.supported[1] =
8458                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8459                 }
8460                 cfg_size = 2;
8461                 break;
8462         }
8463
8464         if (!(sc->port.supported[0] || sc->port.supported[1])) {
8465                 PMD_DRV_LOG(ERR,
8466                             "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8467                             SHMEM_RD(sc,
8468                                      dev_info.port_hw_config
8469                                      [port].external_phy_config),
8470                             SHMEM_RD(sc,
8471                                      dev_info.port_hw_config
8472                                      [port].external_phy_config2));
8473                 return;
8474         }
8475
8476         if (CHIP_IS_E3(sc))
8477                 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8478         else {
8479                 switch (switch_cfg) {
8480                 case ELINK_SWITCH_CFG_1G:
8481                         sc->port.phy_addr =
8482                             REG_RD(sc,
8483                                    NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8484                         break;
8485                 case ELINK_SWITCH_CFG_10G:
8486                         sc->port.phy_addr =
8487                             REG_RD(sc,
8488                                    NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8489                         break;
8490                 default:
8491                         PMD_DRV_LOG(ERR,
8492                                     "Invalid switch config in"
8493                                     "link_config=0x%08x",
8494                                     sc->port.link_config[0]);
8495                         return;
8496                 }
8497         }
8498
8499         PMD_DRV_LOG(INFO, "PHY addr 0x%08x", sc->port.phy_addr);
8500
8501         /* mask what we support according to speed_cap_mask per configuration */
8502         for (idx = 0; idx < cfg_size; idx++) {
8503                 if (!(sc->link_params.speed_cap_mask[idx] &
8504                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8505                         sc->port.supported[idx] &=
8506                             ~ELINK_SUPPORTED_10baseT_Half;
8507                 }
8508
8509                 if (!(sc->link_params.speed_cap_mask[idx] &
8510                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8511                         sc->port.supported[idx] &=
8512                             ~ELINK_SUPPORTED_10baseT_Full;
8513                 }
8514
8515                 if (!(sc->link_params.speed_cap_mask[idx] &
8516                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8517                         sc->port.supported[idx] &=
8518                             ~ELINK_SUPPORTED_100baseT_Half;
8519                 }
8520
8521                 if (!(sc->link_params.speed_cap_mask[idx] &
8522                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8523                         sc->port.supported[idx] &=
8524                             ~ELINK_SUPPORTED_100baseT_Full;
8525                 }
8526
8527                 if (!(sc->link_params.speed_cap_mask[idx] &
8528                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8529                         sc->port.supported[idx] &=
8530                             ~ELINK_SUPPORTED_1000baseT_Full;
8531                 }
8532
8533                 if (!(sc->link_params.speed_cap_mask[idx] &
8534                       PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8535                         sc->port.supported[idx] &=
8536                             ~ELINK_SUPPORTED_2500baseX_Full;
8537                 }
8538
8539                 if (!(sc->link_params.speed_cap_mask[idx] &
8540                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8541                         sc->port.supported[idx] &=
8542                             ~ELINK_SUPPORTED_10000baseT_Full;
8543                 }
8544
8545                 if (!(sc->link_params.speed_cap_mask[idx] &
8546                       PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8547                         sc->port.supported[idx] &=
8548                             ~ELINK_SUPPORTED_20000baseKR2_Full;
8549                 }
8550         }
8551
8552         PMD_DRV_LOG(INFO, "PHY supported 0=0x%08x 1=0x%08x",
8553                     sc->port.supported[0], sc->port.supported[1]);
8554 }
8555
8556 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8557 {
8558         uint32_t link_config;
8559         uint32_t idx;
8560         uint32_t cfg_size = 0;
8561
8562         sc->port.advertising[0] = 0;
8563         sc->port.advertising[1] = 0;
8564
8565         switch (sc->link_params.num_phys) {
8566         case 1:
8567         case 2:
8568                 cfg_size = 1;
8569                 break;
8570         case 3:
8571                 cfg_size = 2;
8572                 break;
8573         }
8574
8575         for (idx = 0; idx < cfg_size; idx++) {
8576                 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8577                 link_config = sc->port.link_config[idx];
8578
8579                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8580                 case PORT_FEATURE_LINK_SPEED_AUTO:
8581                         if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8582                                 sc->link_params.req_line_speed[idx] =
8583                                     ELINK_SPEED_AUTO_NEG;
8584                                 sc->port.advertising[idx] |=
8585                                     sc->port.supported[idx];
8586                                 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8587                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8588                                         sc->port.advertising[idx] |=
8589                                             (ELINK_SUPPORTED_100baseT_Half |
8590                                              ELINK_SUPPORTED_100baseT_Full);
8591                         } else {
8592                                 /* force 10G, no AN */
8593                                 sc->link_params.req_line_speed[idx] =
8594                                     ELINK_SPEED_10000;
8595                                 sc->port.advertising[idx] |=
8596                                     (ADVERTISED_10000baseT_Full |
8597                                      ADVERTISED_FIBRE);
8598                                 continue;
8599                         }
8600                         break;
8601
8602                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8603                         if (sc->
8604                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8605                         {
8606                                 sc->link_params.req_line_speed[idx] =
8607                                     ELINK_SPEED_10;
8608                                 sc->port.advertising[idx] |=
8609                                     (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8610                         } else {
8611                                 PMD_DRV_LOG(ERR,
8612                                             "Invalid NVRAM config link_config=0x%08x "
8613                                             "speed_cap_mask=0x%08x",
8614                                             link_config,
8615                                             sc->
8616                                             link_params.speed_cap_mask[idx]);
8617                                 return;
8618                         }
8619                         break;
8620
8621                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8622                         if (sc->
8623                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8624                         {
8625                                 sc->link_params.req_line_speed[idx] =
8626                                     ELINK_SPEED_10;
8627                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8628                                 sc->port.advertising[idx] |=
8629                                     (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8630                         } else {
8631                                 PMD_DRV_LOG(ERR,
8632                                             "Invalid NVRAM config link_config=0x%08x "
8633                                             "speed_cap_mask=0x%08x",
8634                                             link_config,
8635                                             sc->
8636                                             link_params.speed_cap_mask[idx]);
8637                                 return;
8638                         }
8639                         break;
8640
8641                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8642                         if (sc->
8643                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8644                         {
8645                                 sc->link_params.req_line_speed[idx] =
8646                                     ELINK_SPEED_100;
8647                                 sc->port.advertising[idx] |=
8648                                     (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8649                         } else {
8650                                 PMD_DRV_LOG(ERR,
8651                                             "Invalid NVRAM config link_config=0x%08x "
8652                                             "speed_cap_mask=0x%08x",
8653                                             link_config,
8654                                             sc->
8655                                             link_params.speed_cap_mask[idx]);
8656                                 return;
8657                         }
8658                         break;
8659
8660                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8661                         if (sc->
8662                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8663                         {
8664                                 sc->link_params.req_line_speed[idx] =
8665                                     ELINK_SPEED_100;
8666                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8667                                 sc->port.advertising[idx] |=
8668                                     (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8669                         } else {
8670                                 PMD_DRV_LOG(ERR,
8671                                             "Invalid NVRAM config link_config=0x%08x "
8672                                             "speed_cap_mask=0x%08x",
8673                                             link_config,
8674                                             sc->
8675                                             link_params.speed_cap_mask[idx]);
8676                                 return;
8677                         }
8678                         break;
8679
8680                 case PORT_FEATURE_LINK_SPEED_1G:
8681                         if (sc->port.supported[idx] &
8682                             ELINK_SUPPORTED_1000baseT_Full) {
8683                                 sc->link_params.req_line_speed[idx] =
8684                                     ELINK_SPEED_1000;
8685                                 sc->port.advertising[idx] |=
8686                                     (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8687                         } else {
8688                                 PMD_DRV_LOG(ERR,
8689                                             "Invalid NVRAM config link_config=0x%08x "
8690                                             "speed_cap_mask=0x%08x",
8691                                             link_config,
8692                                             sc->
8693                                             link_params.speed_cap_mask[idx]);
8694                                 return;
8695                         }
8696                         break;
8697
8698                 case PORT_FEATURE_LINK_SPEED_2_5G:
8699                         if (sc->port.supported[idx] &
8700                             ELINK_SUPPORTED_2500baseX_Full) {
8701                                 sc->link_params.req_line_speed[idx] =
8702                                     ELINK_SPEED_2500;
8703                                 sc->port.advertising[idx] |=
8704                                     (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8705                         } else {
8706                                 PMD_DRV_LOG(ERR,
8707                                             "Invalid NVRAM config link_config=0x%08x "
8708                                             "speed_cap_mask=0x%08x",
8709                                             link_config,
8710                                             sc->
8711                                             link_params.speed_cap_mask[idx]);
8712                                 return;
8713                         }
8714                         break;
8715
8716                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8717                         if (sc->port.supported[idx] &
8718                             ELINK_SUPPORTED_10000baseT_Full) {
8719                                 sc->link_params.req_line_speed[idx] =
8720                                     ELINK_SPEED_10000;
8721                                 sc->port.advertising[idx] |=
8722                                     (ADVERTISED_10000baseT_Full |
8723                                      ADVERTISED_FIBRE);
8724                         } else {
8725                                 PMD_DRV_LOG(ERR,
8726                                             "Invalid NVRAM config link_config=0x%08x "
8727                                             "speed_cap_mask=0x%08x",
8728                                             link_config,
8729                                             sc->
8730                                             link_params.speed_cap_mask[idx]);
8731                                 return;
8732                         }
8733                         break;
8734
8735                 case PORT_FEATURE_LINK_SPEED_20G:
8736                         sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8737                         break;
8738
8739                 default:
8740                         PMD_DRV_LOG(ERR,
8741                                     "Invalid NVRAM config link_config=0x%08x "
8742                                     "speed_cap_mask=0x%08x", link_config,
8743                                     sc->link_params.speed_cap_mask[idx]);
8744                         sc->link_params.req_line_speed[idx] =
8745                             ELINK_SPEED_AUTO_NEG;
8746                         sc->port.advertising[idx] = sc->port.supported[idx];
8747                         break;
8748                 }
8749
8750                 sc->link_params.req_flow_ctrl[idx] =
8751                     (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8752
8753                 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8754                         if (!
8755                             (sc->
8756                              port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8757                                 sc->link_params.req_flow_ctrl[idx] =
8758                                     ELINK_FLOW_CTRL_NONE;
8759                         } else {
8760                                 bnx2x_set_requested_fc(sc);
8761                         }
8762                 }
8763         }
8764 }
8765
8766 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8767 {
8768         uint8_t port = SC_PORT(sc);
8769         uint32_t eee_mode;
8770
8771         PMD_INIT_FUNC_TRACE();
8772
8773         /* shmem data already read in bnx2x_get_shmem_info() */
8774
8775         bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8776         bnx2x_link_settings_requested(sc);
8777
8778         /* configure link feature according to nvram value */
8779         eee_mode =
8780             (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8781               & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8782              PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8783         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8784                 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8785                                             ELINK_EEE_MODE_ENABLE_LPI |
8786                                             ELINK_EEE_MODE_OUTPUT_TIME);
8787         } else {
8788                 sc->link_params.eee_mode = 0;
8789         }
8790
8791         /* get the media type */
8792         bnx2x_media_detect(sc);
8793 }
8794
8795 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8796 {
8797         uint32_t flags = MODE_ASIC | MODE_PORT2;
8798
8799         if (CHIP_IS_E2(sc)) {
8800                 flags |= MODE_E2;
8801         } else if (CHIP_IS_E3(sc)) {
8802                 flags |= MODE_E3;
8803                 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8804                         flags |= MODE_E3_A0;
8805                 } else {        /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8806
8807                         flags |= MODE_E3_B0 | MODE_COS3;
8808                 }
8809         }
8810
8811         if (IS_MF(sc)) {
8812                 flags |= MODE_MF;
8813                 switch (sc->devinfo.mf_info.mf_mode) {
8814                 case MULTI_FUNCTION_SD:
8815                         flags |= MODE_MF_SD;
8816                         break;
8817                 case MULTI_FUNCTION_SI:
8818                         flags |= MODE_MF_SI;
8819                         break;
8820                 case MULTI_FUNCTION_AFEX:
8821                         flags |= MODE_MF_AFEX;
8822                         break;
8823                 }
8824         } else {
8825                 flags |= MODE_SF;
8826         }
8827
8828 #if defined(__LITTLE_ENDIAN)
8829         flags |= MODE_LITTLE_ENDIAN;
8830 #else /* __BIG_ENDIAN */
8831         flags |= MODE_BIG_ENDIAN;
8832 #endif
8833
8834         INIT_MODE_FLAGS(sc) = flags;
8835 }
8836
8837 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8838 {
8839         struct bnx2x_fastpath *fp;
8840         char buf[32];
8841         uint32_t i;
8842
8843         if (IS_PF(sc)) {
8844 /************************/
8845 /* DEFAULT STATUS BLOCK */
8846 /************************/
8847
8848                 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8849                                   &sc->def_sb_dma, "def_sb",
8850                                   RTE_CACHE_LINE_SIZE) != 0) {
8851                         return -1;
8852                 }
8853
8854                 sc->def_sb =
8855                     (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8856 /***************/
8857 /* EVENT QUEUE */
8858 /***************/
8859
8860                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8861                                   &sc->eq_dma, "ev_queue",
8862                                   RTE_CACHE_LINE_SIZE) != 0) {
8863                         sc->def_sb = NULL;
8864                         return -1;
8865                 }
8866
8867                 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8868
8869 /*************/
8870 /* SLOW PATH */
8871 /*************/
8872
8873                 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8874                                   &sc->sp_dma, "sp",
8875                                   RTE_CACHE_LINE_SIZE) != 0) {
8876                         sc->eq = NULL;
8877                         sc->def_sb = NULL;
8878                         return -1;
8879                 }
8880
8881                 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8882
8883 /*******************/
8884 /* SLOW PATH QUEUE */
8885 /*******************/
8886
8887                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8888                                   &sc->spq_dma, "sp_queue",
8889                                   RTE_CACHE_LINE_SIZE) != 0) {
8890                         sc->sp = NULL;
8891                         sc->eq = NULL;
8892                         sc->def_sb = NULL;
8893                         return -1;
8894                 }
8895
8896                 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8897
8898 /***************************/
8899 /* FW DECOMPRESSION BUFFER */
8900 /***************************/
8901
8902                 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8903                                   "fw_dec_buf", RTE_CACHE_LINE_SIZE) != 0) {
8904                         sc->spq = NULL;
8905                         sc->sp = NULL;
8906                         sc->eq = NULL;
8907                         sc->def_sb = NULL;
8908                         return -1;
8909                 }
8910
8911                 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8912         }
8913
8914         /*************/
8915         /* FASTPATHS */
8916         /*************/
8917
8918         /* allocate DMA memory for each fastpath structure */
8919         for (i = 0; i < sc->num_queues; i++) {
8920                 fp = &sc->fp[i];
8921                 fp->sc = sc;
8922                 fp->index = i;
8923
8924 /*******************/
8925 /* FP STATUS BLOCK */
8926 /*******************/
8927
8928                 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8929                 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8930                                   &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8931                         PMD_DRV_LOG(NOTICE, "Failed to alloc %s", buf);
8932                         return -1;
8933                 } else {
8934                         if (CHIP_IS_E2E3(sc)) {
8935                                 fp->status_block.e2_sb =
8936                                     (struct host_hc_status_block_e2 *)
8937                                     fp->sb_dma.vaddr;
8938                         } else {
8939                                 fp->status_block.e1x_sb =
8940                                     (struct host_hc_status_block_e1x *)
8941                                     fp->sb_dma.vaddr;
8942                         }
8943                 }
8944         }
8945
8946         return 0;
8947 }
8948
8949 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8950 {
8951         struct bnx2x_fastpath *fp;
8952         int i;
8953
8954         for (i = 0; i < sc->num_queues; i++) {
8955                 fp = &sc->fp[i];
8956
8957 /*******************/
8958 /* FP STATUS BLOCK */
8959 /*******************/
8960
8961                 memset(&fp->status_block, 0, sizeof(fp->status_block));
8962         }
8963
8964         /***************************/
8965         /* FW DECOMPRESSION BUFFER */
8966         /***************************/
8967
8968         sc->gz_buf = NULL;
8969
8970         /*******************/
8971         /* SLOW PATH QUEUE */
8972         /*******************/
8973
8974         sc->spq = NULL;
8975
8976         /*************/
8977         /* SLOW PATH */
8978         /*************/
8979
8980         sc->sp = NULL;
8981
8982         /***************/
8983         /* EVENT QUEUE */
8984         /***************/
8985
8986         sc->eq = NULL;
8987
8988         /************************/
8989         /* DEFAULT STATUS BLOCK */
8990         /************************/
8991
8992         sc->def_sb = NULL;
8993
8994 }
8995
8996 /*
8997 * Previous driver DMAE transaction may have occurred when pre-boot stage
8998 * ended and boot began. This would invalidate the addresses of the
8999 * transaction, resulting in was-error bit set in the PCI causing all
9000 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
9001 * the interrupt which detected this from the pglueb and the was-done bit
9002 */
9003 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
9004 {
9005         uint32_t val;
9006
9007         if (!CHIP_IS_E1x(sc)) {
9008                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
9009                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9010                         REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9011                                1 << SC_FUNC(sc));
9012                 }
9013         }
9014 }
9015
9016 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9017 {
9018         uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9019                                      DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9020         if (!rc) {
9021                 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9022                 return -1;
9023         }
9024
9025         return 0;
9026 }
9027
9028 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9029 {
9030         struct bnx2x_prev_list_node *tmp;
9031
9032         LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9033                 if ((sc->pcie_bus == tmp->bus) &&
9034                     (sc->pcie_device == tmp->slot) &&
9035                     (SC_PATH(sc) == tmp->path)) {
9036                         return tmp;
9037                 }
9038         }
9039
9040         return NULL;
9041 }
9042
9043 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9044 {
9045         struct bnx2x_prev_list_node *tmp;
9046         int rc = FALSE;
9047
9048         rte_spinlock_lock(&bnx2x_prev_mtx);
9049
9050         tmp = bnx2x_prev_path_get_entry(sc);
9051         if (tmp) {
9052                 if (tmp->aer) {
9053                         PMD_DRV_LOG(DEBUG,
9054                                     "Path %d/%d/%d was marked by AER",
9055                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9056                 } else {
9057                         rc = TRUE;
9058                         PMD_DRV_LOG(DEBUG,
9059                                     "Path %d/%d/%d was already cleaned from previous drivers",
9060                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9061                 }
9062         }
9063
9064         rte_spinlock_unlock(&bnx2x_prev_mtx);
9065
9066         return rc;
9067 }
9068
9069 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9070 {
9071         struct bnx2x_prev_list_node *tmp;
9072
9073         rte_spinlock_lock(&bnx2x_prev_mtx);
9074
9075         /* Check whether the entry for this path already exists */
9076         tmp = bnx2x_prev_path_get_entry(sc);
9077         if (tmp) {
9078                 if (!tmp->aer) {
9079                         PMD_DRV_LOG(DEBUG,
9080                                     "Re-marking AER in path %d/%d/%d",
9081                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9082                 } else {
9083                         PMD_DRV_LOG(DEBUG,
9084                                     "Removing AER indication from path %d/%d/%d",
9085                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9086                         tmp->aer = 0;
9087                 }
9088
9089                 rte_spinlock_unlock(&bnx2x_prev_mtx);
9090                 return 0;
9091         }
9092
9093         rte_spinlock_unlock(&bnx2x_prev_mtx);
9094
9095         /* Create an entry for this path and add it */
9096         tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9097                          RTE_CACHE_LINE_SIZE);
9098         if (!tmp) {
9099                 PMD_DRV_LOG(NOTICE, "Failed to allocate 'bnx2x_prev_list_node'");
9100                 return -1;
9101         }
9102
9103         tmp->bus = sc->pcie_bus;
9104         tmp->slot = sc->pcie_device;
9105         tmp->path = SC_PATH(sc);
9106         tmp->aer = 0;
9107         tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9108
9109         rte_spinlock_lock(&bnx2x_prev_mtx);
9110
9111         LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9112
9113         rte_spinlock_unlock(&bnx2x_prev_mtx);
9114
9115         return 0;
9116 }
9117
9118 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9119 {
9120         int i;
9121
9122         /* only E2 and onwards support FLR */
9123         if (CHIP_IS_E1x(sc)) {
9124                 PMD_DRV_LOG(WARNING, "FLR not supported in E1H");
9125                 return -1;
9126         }
9127
9128         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9129         if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9130                 PMD_DRV_LOG(WARNING,
9131                             "FLR not supported by BC_VER: 0x%08x",
9132                             sc->devinfo.bc_ver);
9133                 return -1;
9134         }
9135
9136         /* Wait for Transaction Pending bit clean */
9137         for (i = 0; i < 4; i++) {
9138                 if (i) {
9139                         DELAY(((1 << (i - 1)) * 100) * 1000);
9140                 }
9141
9142                 if (!bnx2x_is_pcie_pending(sc)) {
9143                         goto clear;
9144                 }
9145         }
9146
9147         PMD_DRV_LOG(NOTICE, "PCIE transaction is not cleared, "
9148                     "proceeding with reset anyway");
9149
9150 clear:
9151         bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9152
9153         return 0;
9154 }
9155
9156 struct bnx2x_mac_vals {
9157         uint32_t xmac_addr;
9158         uint32_t xmac_val;
9159         uint32_t emac_addr;
9160         uint32_t emac_val;
9161         uint32_t umac_addr;
9162         uint32_t umac_val;
9163         uint32_t bmac_addr;
9164         uint32_t bmac_val[2];
9165 };
9166
9167 static void
9168 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9169 {
9170         uint32_t val, base_addr, offset, mask, reset_reg;
9171         uint8_t mac_stopped = FALSE;
9172         uint8_t port = SC_PORT(sc);
9173         uint32_t wb_data[2];
9174
9175         /* reset addresses as they also mark which values were changed */
9176         vals->bmac_addr = 0;
9177         vals->umac_addr = 0;
9178         vals->xmac_addr = 0;
9179         vals->emac_addr = 0;
9180
9181         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9182
9183         if (!CHIP_IS_E3(sc)) {
9184                 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9185                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9186                 if ((mask & reset_reg) && val) {
9187                         base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9188                             : NIG_REG_INGRESS_BMAC0_MEM;
9189                         offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9190                             : BIGMAC_REGISTER_BMAC_CONTROL;
9191
9192                         /*
9193                          * use rd/wr since we cannot use dmae. This is safe
9194                          * since MCP won't access the bus due to the request
9195                          * to unload, and no function on the path can be
9196                          * loaded at this time.
9197                          */
9198                         wb_data[0] = REG_RD(sc, base_addr + offset);
9199                         wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9200                         vals->bmac_addr = base_addr + offset;
9201                         vals->bmac_val[0] = wb_data[0];
9202                         vals->bmac_val[1] = wb_data[1];
9203                         wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9204                         REG_WR(sc, vals->bmac_addr, wb_data[0]);
9205                         REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9206                 }
9207
9208                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9209                 vals->emac_val = REG_RD(sc, vals->emac_addr);
9210                 REG_WR(sc, vals->emac_addr, 0);
9211                 mac_stopped = TRUE;
9212         } else {
9213                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9214                         base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9215                         val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9216                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9217                                val & ~(1 << 1));
9218                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9219                                val | (1 << 1));
9220                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9221                         vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9222                         REG_WR(sc, vals->xmac_addr, 0);
9223                         mac_stopped = TRUE;
9224                 }
9225
9226                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9227                 if (mask & reset_reg) {
9228                         base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9229                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9230                         vals->umac_val = REG_RD(sc, vals->umac_addr);
9231                         REG_WR(sc, vals->umac_addr, 0);
9232                         mac_stopped = TRUE;
9233                 }
9234         }
9235
9236         if (mac_stopped) {
9237                 DELAY(20000);
9238         }
9239 }
9240
9241 #define BNX2X_PREV_UNDI_PROD_ADDR(p)  (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9242 #define BNX2X_PREV_UNDI_RCQ(val)      ((val) & 0xffff)
9243 #define BNX2X_PREV_UNDI_BD(val)       ((val) >> 16 & 0xffff)
9244 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9245
9246 static void
9247 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9248 {
9249         uint16_t rcq, bd;
9250         uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9251
9252         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9253         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9254
9255         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9256         REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9257 }
9258
9259 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9260 {
9261         uint32_t reset_reg, tmp_reg = 0, rc;
9262         uint8_t prev_undi = FALSE;
9263         struct bnx2x_mac_vals mac_vals;
9264         uint32_t timer_count = 1000;
9265         uint32_t prev_brb;
9266
9267         /*
9268          * It is possible a previous function received 'common' answer,
9269          * but hasn't loaded yet, therefore creating a scenario of
9270          * multiple functions receiving 'common' on the same path.
9271          */
9272         memset(&mac_vals, 0, sizeof(mac_vals));
9273
9274         if (bnx2x_prev_is_path_marked(sc)) {
9275                 return bnx2x_prev_mcp_done(sc);
9276         }
9277
9278         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9279
9280         /* Reset should be performed after BRB is emptied */
9281         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9282                 /* Close the MAC Rx to prevent BRB from filling up */
9283                 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9284
9285                 /* close LLH filters towards the BRB */
9286                 elink_set_rx_filter(&sc->link_params, 0);
9287
9288                 /*
9289                  * Check if the UNDI driver was previously loaded.
9290                  * UNDI driver initializes CID offset for normal bell to 0x7
9291                  */
9292                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9293                         tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9294                         if (tmp_reg == 0x7) {
9295                                 PMD_DRV_LOG(DEBUG, "UNDI previously loaded");
9296                                 prev_undi = TRUE;
9297                                 /* clear the UNDI indication */
9298                                 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9299                                 /* clear possible idle check errors */
9300                                 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9301                         }
9302                 }
9303
9304                 /* wait until BRB is empty */
9305                 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9306                 while (timer_count) {
9307                         prev_brb = tmp_reg;
9308
9309                         tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9310                         if (!tmp_reg) {
9311                                 break;
9312                         }
9313
9314                         PMD_DRV_LOG(DEBUG, "BRB still has 0x%08x", tmp_reg);
9315
9316                         /* reset timer as long as BRB actually gets emptied */
9317                         if (prev_brb > tmp_reg) {
9318                                 timer_count = 1000;
9319                         } else {
9320                                 timer_count--;
9321                         }
9322
9323                         /* If UNDI resides in memory, manually increment it */
9324                         if (prev_undi) {
9325                                 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9326                         }
9327
9328                         DELAY(10);
9329                 }
9330
9331                 if (!timer_count) {
9332                         PMD_DRV_LOG(NOTICE, "Failed to empty BRB");
9333                 }
9334         }
9335
9336         /* No packets are in the pipeline, path is ready for reset */
9337         bnx2x_reset_common(sc);
9338
9339         if (mac_vals.xmac_addr) {
9340                 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9341         }
9342         if (mac_vals.umac_addr) {
9343                 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9344         }
9345         if (mac_vals.emac_addr) {
9346                 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9347         }
9348         if (mac_vals.bmac_addr) {
9349                 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9350                 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9351         }
9352
9353         rc = bnx2x_prev_mark_path(sc, prev_undi);
9354         if (rc) {
9355                 bnx2x_prev_mcp_done(sc);
9356                 return rc;
9357         }
9358
9359         return bnx2x_prev_mcp_done(sc);
9360 }
9361
9362 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9363 {
9364         int rc;
9365
9366         /* Test if previous unload process was already finished for this path */
9367         if (bnx2x_prev_is_path_marked(sc)) {
9368                 return bnx2x_prev_mcp_done(sc);
9369         }
9370
9371         /*
9372          * If function has FLR capabilities, and existing FW version matches
9373          * the one required, then FLR will be sufficient to clean any residue
9374          * left by previous driver
9375          */
9376         rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9377         if (!rc) {
9378                 /* fw version is good */
9379                 rc = bnx2x_do_flr(sc);
9380         }
9381
9382         if (!rc) {
9383                 /* FLR was performed */
9384                 return 0;
9385         }
9386
9387         PMD_DRV_LOG(INFO, "Could not FLR");
9388
9389         /* Close the MCP request, return failure */
9390         rc = bnx2x_prev_mcp_done(sc);
9391         if (!rc) {
9392                 rc = BNX2X_PREV_WAIT_NEEDED;
9393         }
9394
9395         return rc;
9396 }
9397
9398 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9399 {
9400         int time_counter = 10;
9401         uint32_t fw, hw_lock_reg, hw_lock_val;
9402         uint32_t rc = 0;
9403
9404         /*
9405          * Clear HW from errors which may have resulted from an interrupted
9406          * DMAE transaction.
9407          */
9408         bnx2x_prev_interrupted_dmae(sc);
9409
9410         /* Release previously held locks */
9411         if (SC_FUNC(sc) <= 5)
9412                 hw_lock_reg = (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8);
9413         else
9414                 hw_lock_reg =
9415                     (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9416
9417         hw_lock_val = (REG_RD(sc, hw_lock_reg));
9418         if (hw_lock_val) {
9419                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9420                         REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9421                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9422                 }
9423                 REG_WR(sc, hw_lock_reg, 0xffffffff);
9424         }
9425
9426         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9427                 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9428         }
9429
9430         do {
9431                 /* Lock MCP using an unload request */
9432                 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9433                 if (!fw) {
9434                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9435                         rc = -1;
9436                         break;
9437                 }
9438
9439                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9440                         rc = bnx2x_prev_unload_common(sc);
9441                         break;
9442                 }
9443
9444                 /* non-common reply from MCP might require looping */
9445                 rc = bnx2x_prev_unload_uncommon(sc);
9446                 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9447                         break;
9448                 }
9449
9450                 DELAY(20000);
9451         } while (--time_counter);
9452
9453         if (!time_counter || rc) {
9454                 PMD_DRV_LOG(NOTICE, "Failed to unload previous driver!");
9455                 rc = -1;
9456         }
9457
9458         return rc;
9459 }
9460
9461 static void
9462 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9463 {
9464         if (!CHIP_IS_E1x(sc)) {
9465                 sc->dcb_state = dcb_on;
9466                 sc->dcbx_enabled = dcbx_enabled;
9467         } else {
9468                 sc->dcb_state = FALSE;
9469                 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9470         }
9471         PMD_DRV_LOG(DEBUG,
9472                     "DCB state [%s:%s]",
9473                     dcb_on ? "ON" : "OFF",
9474                     (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9475                     (dcbx_enabled ==
9476                      BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9477                     : (dcbx_enabled ==
9478                        BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9479                     "on-chip with negotiation" : "invalid");
9480 }
9481
9482 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9483 {
9484         int cid_count = BNX2X_L2_MAX_CID(sc);
9485
9486         if (CNIC_SUPPORT(sc)) {
9487                 cid_count += CNIC_CID_MAX;
9488         }
9489
9490         return roundup(cid_count, QM_CID_ROUND);
9491 }
9492
9493 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9494 {
9495         int pri, cos;
9496
9497         uint32_t pri_map = 0;
9498
9499         for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9500                 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9501                 if (cos < sc->max_cos) {
9502                         sc->prio_to_cos[pri] = cos;
9503                 } else {
9504                         PMD_DRV_LOG(WARNING,
9505                                     "Invalid COS %d for priority %d "
9506                                     "(max COS is %d), setting to 0", cos, pri,
9507                                     (sc->max_cos - 1));
9508                         sc->prio_to_cos[pri] = 0;
9509                 }
9510         }
9511 }
9512
9513 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9514 {
9515         struct {
9516                 uint8_t id;
9517                 uint8_t next;
9518         } pci_cap;
9519         uint16_t status;
9520         struct bnx2x_pci_cap *cap;
9521
9522         cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9523                                          RTE_CACHE_LINE_SIZE);
9524         if (!cap) {
9525                 PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9526                 return -ENOMEM;
9527         }
9528
9529         pci_read(sc, PCI_STATUS, &status, 2);
9530         if (!(status & PCI_STATUS_CAP_LIST)) {
9531                 PMD_DRV_LOG(NOTICE, "PCIe capability reading failed");
9532                 return -1;
9533         }
9534
9535         pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9536         while (pci_cap.next) {
9537                 cap->addr = pci_cap.next & ~3;
9538                 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9539                 if (pci_cap.id == 0xff)
9540                         break;
9541                 cap->id = pci_cap.id;
9542                 cap->type = BNX2X_PCI_CAP;
9543                 cap->next = rte_zmalloc("pci_cap",
9544                                         sizeof(struct bnx2x_pci_cap),
9545                                         RTE_CACHE_LINE_SIZE);
9546                 if (!cap->next) {
9547                         PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9548                         return -ENOMEM;
9549                 }
9550                 cap = cap->next;
9551         }
9552
9553         return 0;
9554 }
9555
9556 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9557 {
9558         sc->max_tx_queues = 128;
9559         sc->max_rx_queues = 128;
9560 }
9561
9562 #define FW_HEADER_LEN 104
9563 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9564 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9565
9566 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9567 {
9568         const char *fwname;
9569         int f;
9570         struct stat st;
9571
9572         fwname = sc->devinfo.device_id == BNX2X_DEV_ID_57711
9573                 ? FW_NAME_57711 : FW_NAME_57810;
9574         f = open(fwname, O_RDONLY);
9575         if (f < 0) {
9576                 PMD_DRV_LOG(NOTICE, "Can't open firmware file");
9577                 return;
9578         }
9579
9580         if (fstat(f, &st) < 0) {
9581                 PMD_DRV_LOG(NOTICE, "Can't stat firmware file");
9582                 close(f);
9583                 return;
9584         }
9585
9586         sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9587         if (!sc->firmware) {
9588                 PMD_DRV_LOG(NOTICE, "Can't allocate memory for firmware");
9589                 close(f);
9590                 return;
9591         }
9592
9593         if (read(f, sc->firmware, st.st_size) != st.st_size) {
9594                 PMD_DRV_LOG(NOTICE, "Can't read firmware data");
9595                 close(f);
9596                 return;
9597         }
9598         close(f);
9599
9600         sc->fw_len = st.st_size;
9601         if (sc->fw_len < FW_HEADER_LEN) {
9602                 PMD_DRV_LOG(NOTICE, "Invalid fw size: %" PRIu64, sc->fw_len);
9603                 return;
9604         }
9605         PMD_DRV_LOG(DEBUG, "fw_len = %" PRIu64, sc->fw_len);
9606 }
9607
9608 static void
9609 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9610 {
9611         uint32_t *src = (uint32_t *) data;
9612         uint32_t i, j, tmp;
9613
9614         for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9615                 tmp = rte_be_to_cpu_32(src[j]);
9616                 dst[i].op = (tmp >> 24) & 0xFF;
9617                 dst[i].offset = tmp & 0xFFFFFF;
9618                 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9619         }
9620 }
9621
9622 static void
9623 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9624 {
9625         uint16_t *src = (uint16_t *) data;
9626         uint32_t i;
9627
9628         for (i = 0; i < len / 2; ++i)
9629                 dst[i] = rte_be_to_cpu_16(src[i]);
9630 }
9631
9632 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9633 {
9634         uint32_t *src = (uint32_t *) data;
9635         uint32_t i;
9636
9637         for (i = 0; i < len / 4; ++i)
9638                 dst[i] = rte_be_to_cpu_32(src[i]);
9639 }
9640
9641 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9642 {
9643         uint32_t *src = (uint32_t *) data;
9644         uint32_t i, j, tmp;
9645
9646         for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9647                 dst[i].base = rte_be_to_cpu_32(src[j++]);
9648                 tmp = rte_be_to_cpu_32(src[j]);
9649                 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9650                 dst[i].m2 = tmp & 0xFFFF;
9651                 ++j;
9652                 tmp = rte_be_to_cpu_32(src[j]);
9653                 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9654                 dst[i].size = tmp & 0xFFFF;
9655         }
9656 }
9657
9658 /*
9659 * Device attach function.
9660 *
9661 * Allocates device resources, performs secondary chip identification, and
9662 * initializes driver instance variables. This function is called from driver
9663 * load after a successful probe.
9664 *
9665 * Returns:
9666 *   0 = Success, >0 = Failure
9667 */
9668 int bnx2x_attach(struct bnx2x_softc *sc)
9669 {
9670         int rc;
9671
9672         PMD_DRV_LOG(DEBUG, "Starting attach...");
9673
9674         rc = bnx2x_pci_get_caps(sc);
9675         if (rc) {
9676                 PMD_DRV_LOG(NOTICE, "PCIe caps reading was failed");
9677                 return rc;
9678         }
9679
9680         sc->state = BNX2X_STATE_CLOSED;
9681
9682         /* Init RTE stuff */
9683         bnx2x_init_rte(sc);
9684
9685         pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9686
9687         sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9688
9689         /* get PCI capabilites */
9690         bnx2x_probe_pci_caps(sc);
9691
9692         if (sc->devinfo.pcie_msix_cap_reg != 0) {
9693                 uint32_t val;
9694                 pci_read(sc,
9695                          (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9696                          2);
9697                 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE);
9698         } else {
9699                 sc->igu_sb_cnt = 1;
9700         }
9701
9702         if (IS_PF(sc)) {
9703 /* get device info and set params */
9704                 if (bnx2x_get_device_info(sc) != 0) {
9705                         PMD_DRV_LOG(NOTICE, "getting device info");
9706                         return -ENXIO;
9707                 }
9708
9709 /* get phy settings from shmem and 'and' against admin settings */
9710                 bnx2x_get_phy_info(sc);
9711         } else {
9712 /* Left mac of VF unfilled, PF should set it for VF */
9713                 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9714         }
9715
9716         sc->wol = 0;
9717
9718         /* set the default MTU (changed via ifconfig) */
9719         sc->mtu = ETHER_MTU;
9720
9721         bnx2x_set_modes_bitmap(sc);
9722
9723         /* need to reset chip if UNDI was active */
9724         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9725 /* init fw_seq */
9726                 sc->fw_seq =
9727                     (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9728                      DRV_MSG_SEQ_NUMBER_MASK);
9729                 bnx2x_prev_unload(sc);
9730         }
9731
9732         bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9733
9734         /* calculate qm_cid_count */
9735         sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9736
9737         sc->max_cos = 1;
9738         bnx2x_init_multi_cos(sc);
9739
9740         return 0;
9741 }
9742
9743 static void
9744 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9745                uint16_t index, uint8_t op, uint8_t update)
9746 {
9747         uint32_t igu_addr = sc->igu_base_addr;
9748         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9749         bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9750 }
9751
9752 static void
9753 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9754            uint16_t index, uint8_t op, uint8_t update)
9755 {
9756         if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9757                 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9758         else {
9759                 uint8_t segment;
9760                 if (CHIP_INT_MODE_IS_BC(sc)) {
9761                         segment = storm;
9762                 } else if (igu_sb_id != sc->igu_dsb_id) {
9763                         segment = IGU_SEG_ACCESS_DEF;
9764                 } else if (storm == ATTENTION_ID) {
9765                         segment = IGU_SEG_ACCESS_ATTN;
9766                 } else {
9767                         segment = IGU_SEG_ACCESS_DEF;
9768                 }
9769                 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9770         }
9771 }
9772
9773 static void
9774 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9775                      uint8_t is_pf)
9776 {
9777         uint32_t data, ctl, cnt = 100;
9778         uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9779         uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9780         uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9781             (idu_sb_id / 32) * 4;
9782         uint32_t sb_bit = 1 << (idu_sb_id % 32);
9783         uint32_t func_encode = func |
9784             (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9785         uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9786
9787         /* Not supported in BC mode */
9788         if (CHIP_INT_MODE_IS_BC(sc)) {
9789                 return;
9790         }
9791
9792         data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9793                  IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9794                 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9795
9796         ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9797                (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9798                (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9799
9800         REG_WR(sc, igu_addr_data, data);
9801
9802         mb();
9803
9804         PMD_DRV_LOG(DEBUG, "write 0x%08x to IGU(via GRC) addr 0x%x",
9805                     ctl, igu_addr_ctl);
9806         REG_WR(sc, igu_addr_ctl, ctl);
9807
9808         mb();
9809
9810         /* wait for clean up to finish */
9811         while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9812                 DELAY(20000);
9813         }
9814
9815         if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9816                 PMD_DRV_LOG(DEBUG,
9817                             "Unable to finish IGU cleanup: "
9818                             "idu_sb_id %d offset %d bit %d (cnt %d)",
9819                             idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9820         }
9821 }
9822
9823 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9824 {
9825         bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9826 }
9827
9828 /*******************/
9829 /* ECORE CALLBACKS */
9830 /*******************/
9831
9832 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9833 {
9834         uint32_t val = 0x1400;
9835
9836         PMD_INIT_FUNC_TRACE();
9837
9838         /* reset_common */
9839         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9840                0xd3ffff7f);
9841
9842         if (CHIP_IS_E3(sc)) {
9843                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9844                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9845         }
9846
9847         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9848 }
9849
9850 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9851 {
9852         uint32_t shmem_base[2];
9853         uint32_t shmem2_base[2];
9854
9855         /* Avoid common init in case MFW supports LFA */
9856         if (SHMEM2_RD(sc, size) >
9857             (uint32_t) offsetof(struct shmem2_region,
9858                                 lfa_host_addr[SC_PORT(sc)])) {
9859                 return;
9860         }
9861
9862         shmem_base[0] = sc->devinfo.shmem_base;
9863         shmem2_base[0] = sc->devinfo.shmem2_base;
9864
9865         if (!CHIP_IS_E1x(sc)) {
9866                 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9867                 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9868         }
9869
9870         elink_common_init_phy(sc, shmem_base, shmem2_base,
9871                               sc->devinfo.chip_id, 0);
9872 }
9873
9874 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9875 {
9876         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9877
9878         val &= ~IGU_PF_CONF_FUNC_EN;
9879
9880         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9881         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9882         REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9883 }
9884
9885 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9886 {
9887         uint16_t devctl;
9888         int r_order, w_order;
9889
9890         devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9891
9892         w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9893         r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9894
9895         ecore_init_pxp_arb(sc, r_order, w_order);
9896 }
9897
9898 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9899 {
9900         uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9901         uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9902         return (base + (SC_ABS_FUNC(sc)) * stride);
9903 }
9904
9905 /*
9906  * Called only on E1H or E2.
9907  * When pretending to be PF, the pretend value is the function number 0..7.
9908  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9909  * combination.
9910  */
9911 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9912 {
9913         uint32_t pretend_reg;
9914
9915         if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9916                 return -1;
9917
9918         /* get my own pretend register */
9919         pretend_reg = bnx2x_get_pretend_reg(sc);
9920         REG_WR(sc, pretend_reg, pretend_func_val);
9921         REG_RD(sc, pretend_reg);
9922         return 0;
9923 }
9924
9925 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9926 {
9927         int is_required;
9928         uint32_t val;
9929         int port;
9930
9931         is_required = 0;
9932         val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9933                SHARED_HW_CFG_FAN_FAILURE_MASK);
9934
9935         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9936                 is_required = 1;
9937         }
9938         /*
9939          * The fan failure mechanism is usually related to the PHY type since
9940          * the power consumption of the board is affected by the PHY. Currently,
9941          * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9942          */
9943         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9944                 for (port = PORT_0; port < PORT_MAX; port++) {
9945                         is_required |= elink_fan_failure_det_req(sc,
9946                                                                  sc->
9947                                                                  devinfo.shmem_base,
9948                                                                  sc->
9949                                                                  devinfo.shmem2_base,
9950                                                                  port);
9951                 }
9952         }
9953
9954         if (is_required == 0) {
9955                 return;
9956         }
9957
9958         /* Fan failure is indicated by SPIO 5 */
9959         bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9960
9961         /* set to active low mode */
9962         val = REG_RD(sc, MISC_REG_SPIO_INT);
9963         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
9964         REG_WR(sc, MISC_REG_SPIO_INT, val);
9965
9966         /* enable interrupt to signal the IGU */
9967         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
9968         val |= MISC_SPIO_SPIO5;
9969         REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
9970 }
9971
9972 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
9973 {
9974         uint32_t val;
9975
9976         REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
9977         if (!CHIP_IS_E1x(sc)) {
9978                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
9979         } else {
9980                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
9981         }
9982         REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
9983         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
9984         /*
9985          * mask read length error interrupts in brb for parser
9986          * (parsing unit and 'checksum and crc' unit)
9987          * these errors are legal (PU reads fixed length and CAC can cause
9988          * read length error on truncated packets)
9989          */
9990         REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
9991         REG_WR(sc, QM_REG_QM_INT_MASK, 0);
9992         REG_WR(sc, TM_REG_TM_INT_MASK, 0);
9993         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
9994         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
9995         REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
9996         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
9997         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
9998         REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
9999         REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10000         REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10001         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10002         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10003         REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10004         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10005         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10006         REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10007         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10008         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10009
10010         val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10011                PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10012                PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10013         if (!CHIP_IS_E1x(sc)) {
10014                 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10015                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10016         }
10017         REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10018
10019         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10020         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10021         REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10022         /*      REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10023
10024         if (!CHIP_IS_E1x(sc)) {
10025 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10026                 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10027         }
10028
10029         REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10030         REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10031         /*      REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10032         REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10033 }
10034
10035 /**
10036  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10037  *
10038  * @sc:     driver handle
10039  */
10040 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10041 {
10042         uint8_t abs_func_id;
10043         uint32_t val;
10044
10045         PMD_DRV_LOG(DEBUG, "starting common init for func %d", SC_ABS_FUNC(sc));
10046
10047         /*
10048          * take the RESET lock to protect undi_unload flow from accessing
10049          * registers while we are resetting the chip
10050          */
10051         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10052
10053         bnx2x_reset_common(sc);
10054
10055         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10056
10057         val = 0xfffc;
10058         if (CHIP_IS_E3(sc)) {
10059                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10060                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10061         }
10062
10063         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10064
10065         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10066
10067         ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10068
10069         if (!CHIP_IS_E1x(sc)) {
10070 /*
10071  * 4-port mode or 2-port mode we need to turn off master-enable for
10072  * everyone. After that we turn it back on for self. So, we disregard
10073  * multi-function, and always disable all functions on the given path,
10074  * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10075  */
10076                 for (abs_func_id = SC_PATH(sc);
10077                      abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10078                         if (abs_func_id == SC_ABS_FUNC(sc)) {
10079                                 REG_WR(sc,
10080                                        PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10081                                        1);
10082                                 continue;
10083                         }
10084
10085                         bnx2x_pretend_func(sc, abs_func_id);
10086
10087                         /* clear pf enable */
10088                         bnx2x_pf_disable(sc);
10089
10090                         bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10091                 }
10092         }
10093
10094         ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10095
10096         ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10097         bnx2x_init_pxp(sc);
10098
10099 #ifdef __BIG_ENDIAN
10100         REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10101         REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10102         REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10103         REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10104         REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10105         /* make sure this value is 0 */
10106         REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10107
10108         //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10109         REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10110         REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10111         REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10112         REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10113 #endif
10114
10115         ecore_ilt_init_page_size(sc, INITOP_SET);
10116
10117         if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10118                 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10119         }
10120
10121         /* let the HW do it's magic... */
10122         DELAY(100000);
10123
10124         /* finish PXP init */
10125
10126         val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10127         if (val != 1) {
10128                 PMD_DRV_LOG(NOTICE, "PXP2 CFG failed");
10129                 return -1;
10130         }
10131         val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10132         if (val != 1) {
10133                 PMD_DRV_LOG(NOTICE, "PXP2 RD_INIT failed");
10134                 return -1;
10135         }
10136
10137         /*
10138          * Timer bug workaround for E2 only. We need to set the entire ILT to have
10139          * entries with value "0" and valid bit on. This needs to be done by the
10140          * first PF that is loaded in a path (i.e. common phase)
10141          */
10142         if (!CHIP_IS_E1x(sc)) {
10143 /*
10144  * In E2 there is a bug in the timers block that can cause function 6 / 7
10145  * (i.e. vnic3) to start even if it is marked as "scan-off".
10146  * This occurs when a different function (func2,3) is being marked
10147  * as "scan-off". Real-life scenario for example: if a driver is being
10148  * load-unloaded while func6,7 are down. This will cause the timer to access
10149  * the ilt, translate to a logical address and send a request to read/write.
10150  * Since the ilt for the function that is down is not valid, this will cause
10151  * a translation error which is unrecoverable.
10152  * The Workaround is intended to make sure that when this happens nothing
10153  * fatal will occur. The workaround:
10154  *  1.  First PF driver which loads on a path will:
10155  *      a.  After taking the chip out of reset, by using pretend,
10156  *          it will write "0" to the following registers of
10157  *          the other vnics.
10158  *          REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10159  *          REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10160  *          REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10161  *          And for itself it will write '1' to
10162  *          PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10163  *          dmae-operations (writing to pram for example.)
10164  *          note: can be done for only function 6,7 but cleaner this
10165  *            way.
10166  *      b.  Write zero+valid to the entire ILT.
10167  *      c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
10168  *          VNIC3 (of that port). The range allocated will be the
10169  *          entire ILT. This is needed to prevent  ILT range error.
10170  *  2.  Any PF driver load flow:
10171  *      a.  ILT update with the physical addresses of the allocated
10172  *          logical pages.
10173  *      b.  Wait 20msec. - note that this timeout is needed to make
10174  *          sure there are no requests in one of the PXP internal
10175  *          queues with "old" ILT addresses.
10176  *      c.  PF enable in the PGLC.
10177  *      d.  Clear the was_error of the PF in the PGLC. (could have
10178  *          occurred while driver was down)
10179  *      e.  PF enable in the CFC (WEAK + STRONG)
10180  *      f.  Timers scan enable
10181  *  3.  PF driver unload flow:
10182  *      a.  Clear the Timers scan_en.
10183  *      b.  Polling for scan_on=0 for that PF.
10184  *      c.  Clear the PF enable bit in the PXP.
10185  *      d.  Clear the PF enable in the CFC (WEAK + STRONG)
10186  *      e.  Write zero+valid to all ILT entries (The valid bit must
10187  *          stay set)
10188  *      f.  If this is VNIC 3 of a port then also init
10189  *          first_timers_ilt_entry to zero and last_timers_ilt_entry
10190  *          to the last enrty in the ILT.
10191  *
10192  *      Notes:
10193  *      Currently the PF error in the PGLC is non recoverable.
10194  *      In the future the there will be a recovery routine for this error.
10195  *      Currently attention is masked.
10196  *      Having an MCP lock on the load/unload process does not guarantee that
10197  *      there is no Timer disable during Func6/7 enable. This is because the
10198  *      Timers scan is currently being cleared by the MCP on FLR.
10199  *      Step 2.d can be done only for PF6/7 and the driver can also check if
10200  *      there is error before clearing it. But the flow above is simpler and
10201  *      more general.
10202  *      All ILT entries are written by zero+valid and not just PF6/7
10203  *      ILT entries since in the future the ILT entries allocation for
10204  *      PF-s might be dynamic.
10205  */
10206                 struct ilt_client_info ilt_cli;
10207                 struct ecore_ilt ilt;
10208
10209                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10210                 memset(&ilt, 0, sizeof(struct ecore_ilt));
10211
10212 /* initialize dummy TM client */
10213                 ilt_cli.start = 0;
10214                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10215                 ilt_cli.client_num = ILT_CLIENT_TM;
10216
10217 /*
10218  * Step 1: set zeroes to all ilt page entries with valid bit on
10219  * Step 2: set the timers first/last ilt entry to point
10220  * to the entire range to prevent ILT range error for 3rd/4th
10221  * vnic (this code assumes existence of the vnic)
10222  *
10223  * both steps performed by call to ecore_ilt_client_init_op()
10224  * with dummy TM client
10225  *
10226  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10227  * and his brother are split registers
10228  */
10229
10230                 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10231                 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10232                 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10233
10234                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10235                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10236                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10237         }
10238
10239         REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10240         REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10241
10242         if (!CHIP_IS_E1x(sc)) {
10243                 int factor = 0;
10244
10245                 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10246                 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10247
10248 /* let the HW do it's magic... */
10249                 do {
10250                         DELAY(200000);
10251                         val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10252                 } while (factor-- && (val != 1));
10253
10254                 if (val != 1) {
10255                         PMD_DRV_LOG(NOTICE, "ATC_INIT failed");
10256                         return -1;
10257                 }
10258         }
10259
10260         ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10261
10262         /* clean the DMAE memory */
10263         sc->dmae_ready = 1;
10264         ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10265
10266         ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10267
10268         ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10269
10270         ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10271
10272         ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10273
10274         bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10275         bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10276         bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10277         bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10278
10279         ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10280
10281         /* QM queues pointers table */
10282         ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10283
10284         /* soft reset pulse */
10285         REG_WR(sc, QM_REG_SOFT_RESET, 1);
10286         REG_WR(sc, QM_REG_SOFT_RESET, 0);
10287
10288         if (CNIC_SUPPORT(sc))
10289                 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10290
10291         ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10292         REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10293
10294         if (!CHIP_REV_IS_SLOW(sc)) {
10295 /* enable hw interrupt from doorbell Q */
10296                 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10297         }
10298
10299         ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10300
10301         ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10302         REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10303         REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10304
10305         if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10306                 if (IS_MF_AFEX(sc)) {
10307                         /*
10308                          * configure that AFEX and VLAN headers must be
10309                          * received in AFEX mode
10310                          */
10311                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10312                         REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10313                         REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10314                         REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10315                         REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10316                 } else {
10317                         /*
10318                          * Bit-map indicating which L2 hdrs may appear
10319                          * after the basic Ethernet header
10320                          */
10321                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10322                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10323                 }
10324         }
10325
10326         ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10327         ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10328         ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10329         ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10330
10331         if (!CHIP_IS_E1x(sc)) {
10332 /* reset VFC memories */
10333                 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10334                        VFC_MEMORIES_RST_REG_CAM_RST |
10335                        VFC_MEMORIES_RST_REG_RAM_RST);
10336                 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10337                        VFC_MEMORIES_RST_REG_CAM_RST |
10338                        VFC_MEMORIES_RST_REG_RAM_RST);
10339
10340                 DELAY(20000);
10341         }
10342
10343         ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10344         ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10345         ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10346         ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10347
10348         /* sync semi rtc */
10349         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10350         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10351
10352         ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10353         ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10354         ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10355
10356         if (!CHIP_IS_E1x(sc)) {
10357                 if (IS_MF_AFEX(sc)) {
10358                         /*
10359                          * configure that AFEX and VLAN headers must be
10360                          * sent in AFEX mode
10361                          */
10362                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10363                         REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10364                         REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10365                         REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10366                         REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10367                 } else {
10368                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10369                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10370                 }
10371         }
10372
10373         REG_WR(sc, SRC_REG_SOFT_RST, 1);
10374
10375         ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10376
10377         if (CNIC_SUPPORT(sc)) {
10378                 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10379                 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10380                 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10381                 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10382                 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10383                 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10384                 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10385                 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10386                 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10387                 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10388         }
10389         REG_WR(sc, SRC_REG_SOFT_RST, 0);
10390
10391         if (sizeof(union cdu_context) != 1024) {
10392 /* we currently assume that a context is 1024 bytes */
10393                 PMD_DRV_LOG(NOTICE,
10394                             "please adjust the size of cdu_context(%ld)",
10395                             (long)sizeof(union cdu_context));
10396         }
10397
10398         ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10399         val = (4 << 24) + (0 << 12) + 1024;
10400         REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10401
10402         ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10403
10404         REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10405         /* enable context validation interrupt from CFC */
10406         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10407
10408         /* set the thresholds to prevent CFC/CDU race */
10409         REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10410         ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10411
10412         if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10413                 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10414         }
10415
10416         ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10417         ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10418
10419         /* Reset PCIE errors for debug */
10420         REG_WR(sc, 0x2814, 0xffffffff);
10421         REG_WR(sc, 0x3820, 0xffffffff);
10422
10423         if (!CHIP_IS_E1x(sc)) {
10424                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10425                        (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10426                         PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10427                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10428                        (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10429                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10430                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10431                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10432                        (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10433                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10434                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10435         }
10436
10437         ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10438
10439         /* in E3 this done in per-port section */
10440         if (!CHIP_IS_E3(sc))
10441                 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10442
10443         if (CHIP_IS_E1H(sc)) {
10444 /* not applicable for E2 (and above ...) */
10445                 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10446         }
10447
10448         if (CHIP_REV_IS_SLOW(sc)) {
10449                 DELAY(200000);
10450         }
10451
10452         /* finish CFC init */
10453         val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10454         if (val != 1) {
10455                 PMD_DRV_LOG(NOTICE, "CFC LL_INIT failed");
10456                 return -1;
10457         }
10458         val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10459         if (val != 1) {
10460                 PMD_DRV_LOG(NOTICE, "CFC AC_INIT failed");
10461                 return -1;
10462         }
10463         val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10464         if (val != 1) {
10465                 PMD_DRV_LOG(NOTICE, "CFC CAM_INIT failed");
10466                 return -1;
10467         }
10468         REG_WR(sc, CFC_REG_DEBUG0, 0);
10469
10470         bnx2x_setup_fan_failure_detection(sc);
10471
10472         /* clear PXP2 attentions */
10473         REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10474
10475         bnx2x_enable_blocks_attention(sc);
10476
10477         if (!CHIP_REV_IS_SLOW(sc)) {
10478                 ecore_enable_blocks_parity(sc);
10479         }
10480
10481         if (!BNX2X_NOMCP(sc)) {
10482                 if (CHIP_IS_E1x(sc)) {
10483                         bnx2x_common_init_phy(sc);
10484                 }
10485         }
10486
10487         return 0;
10488 }
10489
10490 /**
10491  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10492  *
10493  * @sc:     driver handle
10494  */
10495 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10496 {
10497         int rc = bnx2x_init_hw_common(sc);
10498
10499         if (rc) {
10500                 return rc;
10501         }
10502
10503         /* In E2 2-PORT mode, same ext phy is used for the two paths */
10504         if (!BNX2X_NOMCP(sc)) {
10505                 bnx2x_common_init_phy(sc);
10506         }
10507
10508         return 0;
10509 }
10510
10511 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10512 {
10513         int port = SC_PORT(sc);
10514         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10515         uint32_t low, high;
10516         uint32_t val;
10517
10518         PMD_DRV_LOG(DEBUG, "starting port init for port %d", port);
10519
10520         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10521
10522         ecore_init_block(sc, BLOCK_MISC, init_phase);
10523         ecore_init_block(sc, BLOCK_PXP, init_phase);
10524         ecore_init_block(sc, BLOCK_PXP2, init_phase);
10525
10526         /*
10527          * Timers bug workaround: disables the pf_master bit in pglue at
10528          * common phase, we need to enable it here before any dmae access are
10529          * attempted. Therefore we manually added the enable-master to the
10530          * port phase (it also happens in the function phase)
10531          */
10532         if (!CHIP_IS_E1x(sc)) {
10533                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10534         }
10535
10536         ecore_init_block(sc, BLOCK_ATC, init_phase);
10537         ecore_init_block(sc, BLOCK_DMAE, init_phase);
10538         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10539         ecore_init_block(sc, BLOCK_QM, init_phase);
10540
10541         ecore_init_block(sc, BLOCK_TCM, init_phase);
10542         ecore_init_block(sc, BLOCK_UCM, init_phase);
10543         ecore_init_block(sc, BLOCK_CCM, init_phase);
10544         ecore_init_block(sc, BLOCK_XCM, init_phase);
10545
10546         /* QM cid (connection) count */
10547         ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10548
10549         if (CNIC_SUPPORT(sc)) {
10550                 ecore_init_block(sc, BLOCK_TM, init_phase);
10551                 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10552                 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10553         }
10554
10555         ecore_init_block(sc, BLOCK_DORQ, init_phase);
10556
10557         ecore_init_block(sc, BLOCK_BRB1, init_phase);
10558
10559         if (CHIP_IS_E1H(sc)) {
10560                 if (IS_MF(sc)) {
10561                         low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10562                 } else if (sc->mtu > 4096) {
10563                         if (BNX2X_ONE_PORT(sc)) {
10564                                 low = 160;
10565                         } else {
10566                                 val = sc->mtu;
10567                                 /* (24*1024 + val*4)/256 */
10568                                 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10569                         }
10570                 } else {
10571                         low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10572                 }
10573                 high = (low + 56);      /* 14*1024/256 */
10574                 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10575                 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10576         }
10577
10578         if (CHIP_IS_MODE_4_PORT(sc)) {
10579                 REG_WR(sc, SC_PORT(sc) ?
10580                        BRB1_REG_MAC_GUARANTIED_1 :
10581                        BRB1_REG_MAC_GUARANTIED_0, 40);
10582         }
10583
10584         ecore_init_block(sc, BLOCK_PRS, init_phase);
10585         if (CHIP_IS_E3B0(sc)) {
10586                 if (IS_MF_AFEX(sc)) {
10587                         /* configure headers for AFEX mode */
10588                         if (SC_PORT(sc)) {
10589                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10590                                        0xE);
10591                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10592                                        0x6);
10593                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10594                         } else {
10595                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10596                                        0xE);
10597                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10598                                        0x6);
10599                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10600                         }
10601                 } else {
10602                         /* Ovlan exists only if we are in multi-function +
10603                          * switch-dependent mode, in switch-independent there
10604                          * is no ovlan headers
10605                          */
10606                         REG_WR(sc, SC_PORT(sc) ?
10607                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10608                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10609                                (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10610                 }
10611         }
10612
10613         ecore_init_block(sc, BLOCK_TSDM, init_phase);
10614         ecore_init_block(sc, BLOCK_CSDM, init_phase);
10615         ecore_init_block(sc, BLOCK_USDM, init_phase);
10616         ecore_init_block(sc, BLOCK_XSDM, init_phase);
10617
10618         ecore_init_block(sc, BLOCK_TSEM, init_phase);
10619         ecore_init_block(sc, BLOCK_USEM, init_phase);
10620         ecore_init_block(sc, BLOCK_CSEM, init_phase);
10621         ecore_init_block(sc, BLOCK_XSEM, init_phase);
10622
10623         ecore_init_block(sc, BLOCK_UPB, init_phase);
10624         ecore_init_block(sc, BLOCK_XPB, init_phase);
10625
10626         ecore_init_block(sc, BLOCK_PBF, init_phase);
10627
10628         if (CHIP_IS_E1x(sc)) {
10629 /* configure PBF to work without PAUSE mtu 9000 */
10630                 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10631
10632 /* update threshold */
10633                 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10634 /* update init credit */
10635                 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10636                        (9040 / 16) + 553 - 22);
10637
10638 /* probe changes */
10639                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10640                 DELAY(50);
10641                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10642         }
10643
10644         if (CNIC_SUPPORT(sc)) {
10645                 ecore_init_block(sc, BLOCK_SRC, init_phase);
10646         }
10647
10648         ecore_init_block(sc, BLOCK_CDU, init_phase);
10649         ecore_init_block(sc, BLOCK_CFC, init_phase);
10650         ecore_init_block(sc, BLOCK_HC, init_phase);
10651         ecore_init_block(sc, BLOCK_IGU, init_phase);
10652         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10653         /* init aeu_mask_attn_func_0/1:
10654          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10655          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10656          *             bits 4-7 are used for "per vn group attention" */
10657         val = IS_MF(sc) ? 0xF7 : 0x7;
10658         val |= 0x10;
10659         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10660
10661         ecore_init_block(sc, BLOCK_NIG, init_phase);
10662
10663         if (!CHIP_IS_E1x(sc)) {
10664 /* Bit-map indicating which L2 hdrs may appear after the
10665  * basic Ethernet header
10666  */
10667                 if (IS_MF_AFEX(sc)) {
10668                         REG_WR(sc, SC_PORT(sc) ?
10669                                NIG_REG_P1_HDRS_AFTER_BASIC :
10670                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10671                 } else {
10672                         REG_WR(sc, SC_PORT(sc) ?
10673                                NIG_REG_P1_HDRS_AFTER_BASIC :
10674                                NIG_REG_P0_HDRS_AFTER_BASIC,
10675                                IS_MF_SD(sc) ? 7 : 6);
10676                 }
10677
10678                 if (CHIP_IS_E3(sc)) {
10679                         REG_WR(sc, SC_PORT(sc) ?
10680                                NIG_REG_LLH1_MF_MODE :
10681                                NIG_REG_LLH_MF_MODE, IS_MF(sc));
10682                 }
10683         }
10684         if (!CHIP_IS_E3(sc)) {
10685                 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10686         }
10687
10688         /* 0x2 disable mf_ov, 0x1 enable */
10689         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10690                (IS_MF_SD(sc) ? 0x1 : 0x2));
10691
10692         if (!CHIP_IS_E1x(sc)) {
10693                 val = 0;
10694                 switch (sc->devinfo.mf_info.mf_mode) {
10695                 case MULTI_FUNCTION_SD:
10696                         val = 1;
10697                         break;
10698                 case MULTI_FUNCTION_SI:
10699                 case MULTI_FUNCTION_AFEX:
10700                         val = 2;
10701                         break;
10702                 }
10703
10704                 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10705                             NIG_REG_LLH0_CLS_TYPE), val);
10706         }
10707         REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10708         REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10709         REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10710
10711         /* If SPIO5 is set to generate interrupts, enable it for this port */
10712         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10713         if (val & MISC_SPIO_SPIO5) {
10714                 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10715                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10716                 val = REG_RD(sc, reg_addr);
10717                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10718                 REG_WR(sc, reg_addr, val);
10719         }
10720
10721         return 0;
10722 }
10723
10724 static uint32_t
10725 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10726                        uint32_t expected, uint32_t poll_count)
10727 {
10728         uint32_t cur_cnt = poll_count;
10729         uint32_t val;
10730
10731         while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10732                 DELAY(FLR_WAIT_INTERVAL);
10733         }
10734
10735         return val;
10736 }
10737
10738 static int
10739 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10740                               __rte_unused const char *msg, uint32_t poll_cnt)
10741 {
10742         uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10743
10744         if (val != 0) {
10745                 PMD_DRV_LOG(NOTICE, "%s usage count=%d", msg, val);
10746                 return -1;
10747         }
10748
10749         return 0;
10750 }
10751
10752 /* Common routines with VF FLR cleanup */
10753 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10754 {
10755         /* adjust polling timeout */
10756         if (CHIP_REV_IS_EMUL(sc)) {
10757                 return (FLR_POLL_CNT * 2000);
10758         }
10759
10760         if (CHIP_REV_IS_FPGA(sc)) {
10761                 return (FLR_POLL_CNT * 120);
10762         }
10763
10764         return FLR_POLL_CNT;
10765 }
10766
10767 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10768 {
10769         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10770         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10771                                           CFC_REG_NUM_LCIDS_INSIDE_PF,
10772                                           "CFC PF usage counter timed out",
10773                                           poll_cnt)) {
10774                 return -1;
10775         }
10776
10777         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10778         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10779                                           DORQ_REG_PF_USAGE_CNT,
10780                                           "DQ PF usage counter timed out",
10781                                           poll_cnt)) {
10782                 return -1;
10783         }
10784
10785         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10786         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10787                                           QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10788                                           "QM PF usage counter timed out",
10789                                           poll_cnt)) {
10790                 return -1;
10791         }
10792
10793         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10794         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10795                                           TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10796                                           "Timers VNIC usage counter timed out",
10797                                           poll_cnt)) {
10798                 return -1;
10799         }
10800
10801         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10802                                           TM_REG_LIN0_NUM_SCANS +
10803                                           4 * SC_PORT(sc),
10804                                           "Timers NUM_SCANS usage counter timed out",
10805                                           poll_cnt)) {
10806                 return -1;
10807         }
10808
10809         /* Wait DMAE PF usage counter to zero */
10810         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10811                                           dmae_reg_go_c[INIT_DMAE_C(sc)],
10812                                           "DMAE dommand register timed out",
10813                                           poll_cnt)) {
10814                 return -1;
10815         }
10816
10817         return 0;
10818 }
10819
10820 #define OP_GEN_PARAM(param)                                            \
10821         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10822 #define OP_GEN_TYPE(type)                                           \
10823         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10824 #define OP_GEN_AGG_VECT(index)                                             \
10825         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10826
10827 static int
10828 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10829                      uint32_t poll_cnt)
10830 {
10831         uint32_t op_gen_command = 0;
10832         uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10833                               CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10834         int ret = 0;
10835
10836         if (REG_RD(sc, comp_addr)) {
10837                 PMD_DRV_LOG(NOTICE,
10838                             "Cleanup complete was not 0 before sending");
10839                 return -1;
10840         }
10841
10842         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10843         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10844         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10845         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10846
10847         REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10848
10849         if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10850                 PMD_DRV_LOG(NOTICE, "FW final cleanup did not succeed");
10851                 PMD_DRV_LOG(DEBUG, "At timeout completion address contained %x",
10852                             (REG_RD(sc, comp_addr)));
10853                 rte_panic("FLR cleanup failed");
10854                 return -1;
10855         }
10856
10857         /* Zero completion for nxt FLR */
10858         REG_WR(sc, comp_addr, 0);
10859
10860         return ret;
10861 }
10862
10863 static void
10864 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10865                        uint32_t poll_count)
10866 {
10867         uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10868         uint32_t cur_cnt = poll_count;
10869
10870         crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10871         crd = crd_start = REG_RD(sc, regs->crd);
10872         init_crd = REG_RD(sc, regs->init_crd);
10873
10874         while ((crd != init_crd) &&
10875                ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10876                 (init_crd - crd_start))) {
10877                 if (cur_cnt--) {
10878                         DELAY(FLR_WAIT_INTERVAL);
10879                         crd = REG_RD(sc, regs->crd);
10880                         crd_freed = REG_RD(sc, regs->crd_freed);
10881                 } else {
10882                         break;
10883                 }
10884         }
10885 }
10886
10887 static void
10888 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10889                        uint32_t poll_count)
10890 {
10891         uint32_t occup, to_free, freed, freed_start;
10892         uint32_t cur_cnt = poll_count;
10893
10894         occup = to_free = REG_RD(sc, regs->lines_occup);
10895         freed = freed_start = REG_RD(sc, regs->lines_freed);
10896
10897         while (occup &&
10898                ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10899                 to_free)) {
10900                 if (cur_cnt--) {
10901                         DELAY(FLR_WAIT_INTERVAL);
10902                         occup = REG_RD(sc, regs->lines_occup);
10903                         freed = REG_RD(sc, regs->lines_freed);
10904                 } else {
10905                         break;
10906                 }
10907         }
10908 }
10909
10910 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10911 {
10912         struct pbf_pN_cmd_regs cmd_regs[] = {
10913                 {0, (CHIP_IS_E3B0(sc)) ?
10914                  PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10915                  (CHIP_IS_E3B0(sc)) ?
10916                  PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10917                 {1, (CHIP_IS_E3B0(sc)) ?
10918                  PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10919                  (CHIP_IS_E3B0(sc)) ?
10920                  PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10921                 {4, (CHIP_IS_E3B0(sc)) ?
10922                  PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10923                  (CHIP_IS_E3B0(sc)) ?
10924                  PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10925                  PBF_REG_P4_TQ_LINES_FREED_CNT}
10926         };
10927
10928         struct pbf_pN_buf_regs buf_regs[] = {
10929                 {0, (CHIP_IS_E3B0(sc)) ?
10930                  PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10931                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10932                  (CHIP_IS_E3B0(sc)) ?
10933                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10934                  PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10935                 {1, (CHIP_IS_E3B0(sc)) ?
10936                  PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10937                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10938                  (CHIP_IS_E3B0(sc)) ?
10939                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10940                  PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10941                 {4, (CHIP_IS_E3B0(sc)) ?
10942                  PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10943                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10944                  (CHIP_IS_E3B0(sc)) ?
10945                  PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10946                  PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10947         };
10948
10949         uint32_t i;
10950
10951         /* Verify the command queues are flushed P0, P1, P4 */
10952         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10953                 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10954         }
10955
10956         /* Verify the transmission buffers are flushed P0, P1, P4 */
10957         for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10958                 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
10959         }
10960 }
10961
10962 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
10963 {
10964         __rte_unused uint32_t val;
10965
10966         val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
10967         PMD_DRV_LOG(DEBUG, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
10968
10969         val = REG_RD(sc, PBF_REG_DISABLE_PF);
10970         PMD_DRV_LOG(DEBUG, "PBF_REG_DISABLE_PF is 0x%x", val);
10971
10972         val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
10973         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
10974
10975         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
10976         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
10977
10978         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
10979         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
10980
10981         val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
10982         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
10983
10984         val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
10985         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
10986
10987         val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
10988         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
10989                     val);
10990 }
10991
10992 /**
10993  *      bnx2x_pf_flr_clnup
10994  *      a. re-enable target read on the PF
10995  *      b. poll cfc per function usgae counter
10996  *      c. poll the qm perfunction usage counter
10997  *      d. poll the tm per function usage counter
10998  *      e. poll the tm per function scan-done indication
10999  *      f. clear the dmae channel associated wit hthe PF
11000  *      g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11001  *      h. call the common flr cleanup code with -1 (pf indication)
11002  */
11003 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11004 {
11005         uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11006
11007         /* Re-enable PF target read access */
11008         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11009
11010         /* Poll HW usage counters */
11011         if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11012                 return -1;
11013         }
11014
11015         /* Zero the igu 'trailing edge' and 'leading edge' */
11016
11017         /* Send the FW cleanup command */
11018         if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11019                 return -1;
11020         }
11021
11022         /* ATC cleanup */
11023
11024         /* Verify TX hw is flushed */
11025         bnx2x_tx_hw_flushed(sc, poll_cnt);
11026
11027         /* Wait 100ms (not adjusted according to platform) */
11028         DELAY(100000);
11029
11030         /* Verify no pending pci transactions */
11031         if (bnx2x_is_pcie_pending(sc)) {
11032                 PMD_DRV_LOG(NOTICE, "PCIE Transactions still pending");
11033         }
11034
11035         /* Debug */
11036         bnx2x_hw_enable_status(sc);
11037
11038         /*
11039          * Master enable - Due to WB DMAE writes performed before this
11040          * register is re-initialized as part of the regular function init
11041          */
11042         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11043
11044         return 0;
11045 }
11046
11047 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11048 {
11049         int port = SC_PORT(sc);
11050         int func = SC_FUNC(sc);
11051         int init_phase = PHASE_PF0 + func;
11052         struct ecore_ilt *ilt = sc->ilt;
11053         uint16_t cdu_ilt_start;
11054         uint32_t addr, val;
11055         uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11056         int main_mem_width, rc;
11057         uint32_t i;
11058
11059         PMD_DRV_LOG(DEBUG, "starting func init for func %d", func);
11060
11061         /* FLR cleanup */
11062         if (!CHIP_IS_E1x(sc)) {
11063                 rc = bnx2x_pf_flr_clnup(sc);
11064                 if (rc) {
11065                         PMD_DRV_LOG(NOTICE, "FLR cleanup failed!");
11066                         return rc;
11067                 }
11068         }
11069
11070         /* set MSI reconfigure capability */
11071         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11072                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11073                 val = REG_RD(sc, addr);
11074                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11075                 REG_WR(sc, addr, val);
11076         }
11077
11078         ecore_init_block(sc, BLOCK_PXP, init_phase);
11079         ecore_init_block(sc, BLOCK_PXP2, init_phase);
11080
11081         ilt = sc->ilt;
11082         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11083
11084         for (i = 0; i < L2_ILT_LINES(sc); i++) {
11085                 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11086                 ilt->lines[cdu_ilt_start + i].page_mapping =
11087                     (phys_addr_t)sc->context[i].vcxt_dma.paddr;
11088                 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11089         }
11090         ecore_ilt_init_op(sc, INITOP_SET);
11091
11092         REG_WR(sc, PRS_REG_NIC_MODE, 1);
11093
11094         if (!CHIP_IS_E1x(sc)) {
11095                 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11096
11097 /* Turn on a single ISR mode in IGU if driver is going to use
11098  * INT#x or MSI
11099  */
11100                 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11101                     || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11102                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11103                 }
11104
11105 /*
11106  * Timers workaround bug: function init part.
11107  * Need to wait 20msec after initializing ILT,
11108  * needed to make sure there are no requests in
11109  * one of the PXP internal queues with "old" ILT addresses
11110  */
11111                 DELAY(20000);
11112
11113 /*
11114  * Master enable - Due to WB DMAE writes performed before this
11115  * register is re-initialized as part of the regular function
11116  * init
11117  */
11118                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11119 /* Enable the function in IGU */
11120                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11121         }
11122
11123         sc->dmae_ready = 1;
11124
11125         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11126
11127         if (!CHIP_IS_E1x(sc))
11128                 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11129
11130         ecore_init_block(sc, BLOCK_ATC, init_phase);
11131         ecore_init_block(sc, BLOCK_DMAE, init_phase);
11132         ecore_init_block(sc, BLOCK_NIG, init_phase);
11133         ecore_init_block(sc, BLOCK_SRC, init_phase);
11134         ecore_init_block(sc, BLOCK_MISC, init_phase);
11135         ecore_init_block(sc, BLOCK_TCM, init_phase);
11136         ecore_init_block(sc, BLOCK_UCM, init_phase);
11137         ecore_init_block(sc, BLOCK_CCM, init_phase);
11138         ecore_init_block(sc, BLOCK_XCM, init_phase);
11139         ecore_init_block(sc, BLOCK_TSEM, init_phase);
11140         ecore_init_block(sc, BLOCK_USEM, init_phase);
11141         ecore_init_block(sc, BLOCK_CSEM, init_phase);
11142         ecore_init_block(sc, BLOCK_XSEM, init_phase);
11143
11144         if (!CHIP_IS_E1x(sc))
11145                 REG_WR(sc, QM_REG_PF_EN, 1);
11146
11147         if (!CHIP_IS_E1x(sc)) {
11148                 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11149                 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11150                 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11151                 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11152         }
11153         ecore_init_block(sc, BLOCK_QM, init_phase);
11154
11155         ecore_init_block(sc, BLOCK_TM, init_phase);
11156         ecore_init_block(sc, BLOCK_DORQ, init_phase);
11157
11158         ecore_init_block(sc, BLOCK_BRB1, init_phase);
11159         ecore_init_block(sc, BLOCK_PRS, init_phase);
11160         ecore_init_block(sc, BLOCK_TSDM, init_phase);
11161         ecore_init_block(sc, BLOCK_CSDM, init_phase);
11162         ecore_init_block(sc, BLOCK_USDM, init_phase);
11163         ecore_init_block(sc, BLOCK_XSDM, init_phase);
11164         ecore_init_block(sc, BLOCK_UPB, init_phase);
11165         ecore_init_block(sc, BLOCK_XPB, init_phase);
11166         ecore_init_block(sc, BLOCK_PBF, init_phase);
11167         if (!CHIP_IS_E1x(sc))
11168                 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11169
11170         ecore_init_block(sc, BLOCK_CDU, init_phase);
11171
11172         ecore_init_block(sc, BLOCK_CFC, init_phase);
11173
11174         if (!CHIP_IS_E1x(sc))
11175                 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11176
11177         if (IS_MF(sc)) {
11178                 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11179                 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11180         }
11181
11182         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11183
11184         /* HC init per function */
11185         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11186                 if (CHIP_IS_E1H(sc)) {
11187                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11188
11189                         REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11190                         REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11191                 }
11192                 ecore_init_block(sc, BLOCK_HC, init_phase);
11193
11194         } else {
11195                 uint32_t num_segs, sb_idx, prod_offset;
11196
11197                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11198
11199                 if (!CHIP_IS_E1x(sc)) {
11200                         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11201                         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11202                 }
11203
11204                 ecore_init_block(sc, BLOCK_IGU, init_phase);
11205
11206                 if (!CHIP_IS_E1x(sc)) {
11207                         int dsb_idx = 0;
11208         /**
11209          * Producer memory:
11210          * E2 mode: address 0-135 match to the mapping memory;
11211          * 136 - PF0 default prod; 137 - PF1 default prod;
11212          * 138 - PF2 default prod; 139 - PF3 default prod;
11213          * 140 - PF0 attn prod;    141 - PF1 attn prod;
11214          * 142 - PF2 attn prod;    143 - PF3 attn prod;
11215          * 144-147 reserved.
11216          *
11217          * E1.5 mode - In backward compatible mode;
11218          * for non default SB; each even line in the memory
11219          * holds the U producer and each odd line hold
11220          * the C producer. The first 128 producers are for
11221          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11222          * producers are for the DSB for each PF.
11223          * Each PF has five segments: (the order inside each
11224          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11225          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11226          * 144-147 attn prods;
11227          */
11228                         /* non-default-status-blocks */
11229                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11230                             IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11231                         for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11232                                 prod_offset = (sc->igu_base_sb + sb_idx) *
11233                                     num_segs;
11234
11235                                 for (i = 0; i < num_segs; i++) {
11236                                         addr = IGU_REG_PROD_CONS_MEMORY +
11237                                             (prod_offset + i) * 4;
11238                                         REG_WR(sc, addr, 0);
11239                                 }
11240                                 /* send consumer update with value 0 */
11241                                 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11242                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11243                                 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11244                         }
11245
11246                         /* default-status-blocks */
11247                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11248                             IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11249
11250                         if (CHIP_IS_MODE_4_PORT(sc))
11251                                 dsb_idx = SC_FUNC(sc);
11252                         else
11253                                 dsb_idx = SC_VN(sc);
11254
11255                         prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11256                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
11257                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
11258
11259                         /*
11260                          * igu prods come in chunks of E1HVN_MAX (4) -
11261                          * does not matters what is the current chip mode
11262                          */
11263                         for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11264                                 addr = IGU_REG_PROD_CONS_MEMORY +
11265                                     (prod_offset + i) * 4;
11266                                 REG_WR(sc, addr, 0);
11267                         }
11268                         /* send consumer update with 0 */
11269                         if (CHIP_INT_MODE_IS_BC(sc)) {
11270                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11271                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11272                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11273                                            CSTORM_ID, 0, IGU_INT_NOP, 1);
11274                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11275                                            XSTORM_ID, 0, IGU_INT_NOP, 1);
11276                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11277                                            TSTORM_ID, 0, IGU_INT_NOP, 1);
11278                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11279                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11280                         } else {
11281                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11282                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11283                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11284                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11285                         }
11286                         bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11287
11288                         /* !!! these should become driver const once
11289                            rf-tool supports split-68 const */
11290                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11291                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11292                         REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11293                         REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11294                         REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11295                         REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11296                 }
11297         }
11298
11299         /* Reset PCIE errors for debug */
11300         REG_WR(sc, 0x2114, 0xffffffff);
11301         REG_WR(sc, 0x2120, 0xffffffff);
11302
11303         if (CHIP_IS_E1x(sc)) {
11304                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2;    /*dwords */
11305                 main_mem_base = HC_REG_MAIN_MEMORY +
11306                     SC_PORT(sc) * (main_mem_size * 4);
11307                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11308                 main_mem_width = 8;
11309
11310                 val = REG_RD(sc, main_mem_prty_clr);
11311                 if (val) {
11312                         PMD_DRV_LOG(DEBUG,
11313                                     "Parity errors in HC block during function init (0x%x)!",
11314                                     val);
11315                 }
11316
11317 /* Clear "false" parity errors in MSI-X table */
11318                 for (i = main_mem_base;
11319                      i < main_mem_base + main_mem_size * 4;
11320                      i += main_mem_width) {
11321                         bnx2x_read_dmae(sc, i, main_mem_width / 4);
11322                         bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11323                                        i, main_mem_width / 4);
11324                 }
11325 /* Clear HC parity attention */
11326                 REG_RD(sc, main_mem_prty_clr);
11327         }
11328
11329         /* Enable STORMs SP logging */
11330         REG_WR8(sc, BAR_USTRORM_INTMEM +
11331                 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11332         REG_WR8(sc, BAR_TSTRORM_INTMEM +
11333                 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11334         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11335                 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11336         REG_WR8(sc, BAR_XSTRORM_INTMEM +
11337                 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11338
11339         elink_phy_probe(&sc->link_params);
11340
11341         return 0;
11342 }
11343
11344 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11345 {
11346         if (!BNX2X_NOMCP(sc)) {
11347                 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11348         } else {
11349                 if (!CHIP_REV_IS_SLOW(sc)) {
11350                         PMD_DRV_LOG(WARNING,
11351                                     "Bootcode is missing - cannot reset link");
11352                 }
11353         }
11354 }
11355
11356 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11357 {
11358         int port = SC_PORT(sc);
11359         uint32_t val;
11360
11361         /* reset physical Link */
11362         bnx2x_link_reset(sc);
11363
11364         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11365
11366         /* Do not rcv packets to BRB */
11367         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11368         /* Do not direct rcv packets that are not for MCP to the BRB */
11369         REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11370                     NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11371
11372         /* Configure AEU */
11373         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11374
11375         DELAY(100000);
11376
11377         /* Check for BRB port occupancy */
11378         val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11379         if (val) {
11380                 PMD_DRV_LOG(DEBUG,
11381                             "BRB1 is not empty, %d blocks are occupied", val);
11382         }
11383 }
11384
11385 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, phys_addr_t addr)
11386 {
11387         int reg;
11388         uint32_t wb_write[2];
11389
11390         reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11391
11392         wb_write[0] = ONCHIP_ADDR1(addr);
11393         wb_write[1] = ONCHIP_ADDR2(addr);
11394         REG_WR_DMAE(sc, reg, wb_write, 2);
11395 }
11396
11397 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11398 {
11399         uint32_t i, base = FUNC_ILT_BASE(func);
11400         for (i = base; i < base + ILT_PER_FUNC; i++) {
11401                 bnx2x_ilt_wr(sc, i, 0);
11402         }
11403 }
11404
11405 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11406 {
11407         struct bnx2x_fastpath *fp;
11408         int port = SC_PORT(sc);
11409         int func = SC_FUNC(sc);
11410         int i;
11411
11412         /* Disable the function in the FW */
11413         REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11414         REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11415         REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11416         REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11417
11418         /* FP SBs */
11419         FOR_EACH_ETH_QUEUE(sc, i) {
11420                 fp = &sc->fp[i];
11421                 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11422                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11423                         SB_DISABLED);
11424         }
11425
11426         /* SP SB */
11427         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11428                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11429
11430         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11431                 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11432                        0);
11433         }
11434
11435         /* Configure IGU */
11436         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11437                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11438                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11439         } else {
11440                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11441                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11442         }
11443
11444         if (CNIC_LOADED(sc)) {
11445 /* Disable Timer scan */
11446                 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11447 /*
11448  * Wait for at least 10ms and up to 2 second for the timers
11449  * scan to complete
11450  */
11451                 for (i = 0; i < 200; i++) {
11452                         DELAY(10000);
11453                         if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11454                                 break;
11455                 }
11456         }
11457
11458         /* Clear ILT */
11459         bnx2x_clear_func_ilt(sc, func);
11460
11461         /*
11462          * Timers workaround bug for E2: if this is vnic-3,
11463          * we need to set the entire ilt range for this timers.
11464          */
11465         if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11466                 struct ilt_client_info ilt_cli;
11467 /* use dummy TM client */
11468                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11469                 ilt_cli.start = 0;
11470                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11471                 ilt_cli.client_num = ILT_CLIENT_TM;
11472
11473                 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11474         }
11475
11476         /* this assumes that reset_port() called before reset_func() */
11477         if (!CHIP_IS_E1x(sc)) {
11478                 bnx2x_pf_disable(sc);
11479         }
11480
11481         sc->dmae_ready = 0;
11482 }
11483
11484 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11485 {
11486         rte_free(sc->init_ops);
11487         rte_free(sc->init_ops_offsets);
11488         rte_free(sc->init_data);
11489         rte_free(sc->iro_array);
11490 }
11491
11492 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11493 {
11494         uint32_t len, i;
11495         uint8_t *p = sc->firmware;
11496         uint32_t off[24];
11497
11498         for (i = 0; i < 24; ++i)
11499                 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11500
11501         len = off[0];
11502         sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11503         if (!sc->init_ops)
11504                 goto alloc_failed;
11505         bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11506
11507         len = off[2];
11508         sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11509         if (!sc->init_ops_offsets)
11510                 goto alloc_failed;
11511         bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11512
11513         len = off[4];
11514         sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11515         if (!sc->init_data)
11516                 goto alloc_failed;
11517         bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11518
11519         sc->tsem_int_table_data = p + off[7];
11520         sc->tsem_pram_data = p + off[9];
11521         sc->usem_int_table_data = p + off[11];
11522         sc->usem_pram_data = p + off[13];
11523         sc->csem_int_table_data = p + off[15];
11524         sc->csem_pram_data = p + off[17];
11525         sc->xsem_int_table_data = p + off[19];
11526         sc->xsem_pram_data = p + off[21];
11527
11528         len = off[22];
11529         sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11530         if (!sc->iro_array)
11531                 goto alloc_failed;
11532         bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11533
11534         return 0;
11535
11536 alloc_failed:
11537         bnx2x_release_firmware(sc);
11538         return -1;
11539 }
11540
11541 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11542 {
11543 #define MIN_PREFIX_SIZE (10)
11544
11545         int n = MIN_PREFIX_SIZE;
11546         uint16_t xlen;
11547
11548         if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11549             len <= MIN_PREFIX_SIZE) {
11550                 return -1;
11551         }
11552
11553         /* optional extra fields are present */
11554         if (zbuf[3] & 0x4) {
11555                 xlen = zbuf[13];
11556                 xlen <<= 8;
11557                 xlen += zbuf[12];
11558
11559                 n += xlen;
11560         }
11561         /* file name is present */
11562         if (zbuf[3] & 0x8) {
11563                 while ((zbuf[n++] != 0) && (n < len)) ;
11564         }
11565
11566         return n;
11567 }
11568
11569 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11570 {
11571         int ret;
11572         int data_begin = cut_gzip_prefix(zbuf, len);
11573
11574         PMD_DRV_LOG(DEBUG, "ecore_gunzip %d", len);
11575
11576         if (data_begin <= 0) {
11577                 PMD_DRV_LOG(NOTICE, "bad gzip prefix");
11578                 return -1;
11579         }
11580
11581         memset(&zlib_stream, 0, sizeof(zlib_stream));
11582         zlib_stream.next_in = zbuf + data_begin;
11583         zlib_stream.avail_in = len - data_begin;
11584         zlib_stream.next_out = sc->gz_buf;
11585         zlib_stream.avail_out = FW_BUF_SIZE;
11586
11587         ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11588         if (ret != Z_OK) {
11589                 PMD_DRV_LOG(NOTICE, "zlib inflateInit2 error");
11590                 return ret;
11591         }
11592
11593         ret = inflate(&zlib_stream, Z_FINISH);
11594         if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11595                 PMD_DRV_LOG(NOTICE, "zlib inflate error: %d %s", ret,
11596                             zlib_stream.msg);
11597         }
11598
11599         sc->gz_outlen = zlib_stream.total_out;
11600         if (sc->gz_outlen & 0x3) {
11601                 PMD_DRV_LOG(NOTICE, "firmware is not aligned. gz_outlen == %d",
11602                             sc->gz_outlen);
11603         }
11604         sc->gz_outlen >>= 2;
11605
11606         inflateEnd(&zlib_stream);
11607
11608         if (ret == Z_STREAM_END)
11609                 return 0;
11610
11611         return ret;
11612 }
11613
11614 static void
11615 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
11616                           uint32_t addr, uint32_t len)
11617 {
11618         bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11619 }
11620
11621 void
11622 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11623                           uint32_t * data)
11624 {
11625         uint8_t i;
11626         for (i = 0; i < size / 4; i++) {
11627                 REG_WR(sc, addr + (i * 4), data[i]);
11628         }
11629 }
11630
11631 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11632 {
11633         uint32_t phy_type_idx = ext_phy_type >> 8;
11634         static const char *types[] =
11635             { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11636                 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11637                 "BNX2X-8727",
11638                 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11639         };
11640
11641         if (phy_type_idx < 12)
11642                 return types[phy_type_idx];
11643         else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11644                 return types[12];
11645         else
11646                 return types[13];
11647 }
11648
11649 static const char *get_state(uint32_t state)
11650 {
11651         uint32_t state_idx = state >> 12;
11652         static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11653                 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11654                 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11655                 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11656                 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11657         };
11658
11659         if (state_idx <= 0xF)
11660                 return states[state_idx];
11661         else
11662                 return states[0x10];
11663 }
11664
11665 static const char *get_recovery_state(uint32_t state)
11666 {
11667         static const char *states[] = { "NONE", "DONE", "INIT",
11668                 "WAIT", "FAILED", "NIC_LOADING"
11669         };
11670         return states[state];
11671 }
11672
11673 static const char *get_rx_mode(uint32_t mode)
11674 {
11675         static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11676                 "PROMISC", "MAX_MULTICAST", "ERROR"
11677         };
11678
11679         if (mode < 0x4)
11680                 return modes[mode];
11681         else if (BNX2X_MAX_MULTICAST == mode)
11682                 return modes[4];
11683         else
11684                 return modes[5];
11685 }
11686
11687 #define BNX2X_INFO_STR_MAX 256
11688 static const char *get_bnx2x_flags(uint32_t flags)
11689 {
11690         int i;
11691         static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11692                 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11693                 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11694                 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11695         };
11696         static char flag_str[BNX2X_INFO_STR_MAX];
11697         memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11698
11699         for (i = 0; i < 5; i++)
11700                 if (flags & (1 << i)) {
11701                         strcat(flag_str, flag[i]);
11702                         flags ^= (1 << i);
11703                 }
11704         if (flags) {
11705                 static char unknown[BNX2X_INFO_STR_MAX];
11706                 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11707                 strcat(flag_str, unknown);
11708         }
11709         return flag_str;
11710 }
11711
11712 /*
11713  * Prints useful adapter info.
11714  */
11715 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11716 {
11717         int i = 0;
11718         __rte_unused uint32_t ext_phy_type;
11719
11720         PMD_INIT_FUNC_TRACE();
11721         if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11722                 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
11723                                                               sc->
11724                                                               devinfo.shmem_base
11725                                                               + offsetof(struct
11726                                                                          shmem_region,
11727                                                                          dev_info.port_hw_config
11728                                                                          [0].external_phy_config)));
11729         else
11730                 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
11731                                                                 sc->
11732                                                                 devinfo.shmem_base
11733                                                                 +
11734                                                                 offsetof(struct
11735                                                                          shmem_region,
11736                                                                          dev_info.port_hw_config
11737                                                                          [0].external_phy_config)));
11738
11739         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11740         /* Hardware chip info. */
11741         PMD_INIT_LOG(DEBUG, "%10s : %#08x\n", "ASIC", sc->devinfo.chip_id);
11742         PMD_INIT_LOG(DEBUG, "%10s : %c%d\n", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11743                      (CHIP_METAL(sc) >> 4));
11744
11745         /* Bus info. */
11746         PMD_INIT_LOG(DEBUG, "%10s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
11747         switch (sc->devinfo.pcie_link_speed) {
11748         case 1:
11749                 PMD_INIT_LOG(DEBUG, "2.5 Gbps\n");
11750                 break;
11751         case 2:
11752                 PMD_INIT_LOG(DEBUG, "5 Gbps\n");
11753                 break;
11754         case 4:
11755                 PMD_INIT_LOG(DEBUG, "8 Gbps\n");
11756                 break;
11757         default:
11758                 PMD_INIT_LOG(DEBUG, "Unknown link speed\n");
11759         }
11760
11761         /* Device features. */
11762         PMD_INIT_LOG(DEBUG, "%10s : ", "Flags");
11763
11764         /* Miscellaneous flags. */
11765         if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11766                 PMD_INIT_LOG(DEBUG, "MSI");
11767                 i++;
11768         }
11769
11770         if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11771                 if (i > 0)
11772                         PMD_INIT_LOG(DEBUG, "|");
11773                 PMD_INIT_LOG(DEBUG, "MSI-X");
11774                 i++;
11775         }
11776
11777         PMD_INIT_LOG(DEBUG, "\n");
11778
11779         if (IS_PF(sc)) {
11780                 PMD_INIT_LOG(DEBUG, "\n%10s : ", "Queues");
11781                 switch (sc->sp->rss_rdata.rss_mode) {
11782                 case ETH_RSS_MODE_DISABLED:
11783                         PMD_INIT_LOG(DEBUG, "None\n");
11784                         break;
11785                 case ETH_RSS_MODE_REGULAR:
11786                         PMD_INIT_LOG(DEBUG, "RSS : %d\n", sc->num_queues);
11787                         break;
11788                 default:
11789                         PMD_INIT_LOG(DEBUG, "Unknown\n");
11790                         break;
11791                 }
11792         }
11793
11794         /* Firmware versions and device features. */
11795         PMD_INIT_LOG(DEBUG, "%10s : %d.%d.%d\n%10s : %s\n",
11796                      "Firmware",
11797                      BNX2X_5710_FW_MAJOR_VERSION,
11798                      BNX2X_5710_FW_MINOR_VERSION,
11799                      BNX2X_5710_FW_REVISION_VERSION,
11800                      "Bootcode", sc->devinfo.bc_ver_str);
11801
11802         PMD_INIT_LOG(DEBUG, "===================================\n");
11803         PMD_INIT_LOG(DEBUG, "%10s : %u\n", "Bnx2x Func", sc->pcie_func);
11804         PMD_INIT_LOG(DEBUG, "%10s : %s\n", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11805         PMD_INIT_LOG(DEBUG, "%10s : %s\n", "DMAE Is",
11806                      (sc->dmae_ready ? "Ready" : "Not Ready"));
11807         PMD_INIT_LOG(DEBUG, "%10s : %s\n", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11808         PMD_INIT_LOG(DEBUG, "%10s : %s\n", "MF", (IS_MF(sc) ? "YES" : "NO"));
11809         PMD_INIT_LOG(DEBUG, "%10s : %u\n", "MTU", sc->mtu);
11810         PMD_INIT_LOG(DEBUG, "%10s : %s\n", "PHY Type", get_ext_phy_type(ext_phy_type));
11811         PMD_INIT_LOG(DEBUG, "%10s : ", "MAC Addr");
11812         for (i = 0; i < 6; i++)
11813                 PMD_INIT_LOG(DEBUG, "%x%s", sc->link_params.mac_addr[i],
11814                              i < 5 ? ":" : "\n");
11815         PMD_INIT_LOG(DEBUG, "%10s : %s\n", "RX Mode", get_rx_mode(sc->rx_mode));
11816         PMD_INIT_LOG(DEBUG, "%10s : %s\n", "State", get_state(sc->state));
11817         if (sc->recovery_state)
11818                 PMD_INIT_LOG(DEBUG, "%10s : %s\n", "Recovery",
11819                              get_recovery_state(sc->recovery_state));
11820         PMD_INIT_LOG(DEBUG, "%10s : CQ = %lx,  EQ = %lx\n", "SPQ Left",
11821                      sc->cq_spq_left, sc->eq_spq_left);
11822         PMD_INIT_LOG(DEBUG, "%10s : %x\n", "Switch", sc->link_params.switch_cfg);
11823         PMD_INIT_LOG(DEBUG, "===================================\n\n");
11824 }