drivers/net/bnx2x/bnx2x.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2007-2013 Broadcom Corporation.
   3  *
   4  * Eric Davis        <edavis@broadcom.com>
   5  * David Christensen <davidch@broadcom.com>
   6  * Gary Zambrano     <zambrano@broadcom.com>
   7  *
   8  * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
   9  * Copyright (c) 2015-2018 Cavium Inc.
  10  * All rights reserved.
  11  * www.cavium.com
  12  */
  13
  14 #define BNX2X_DRIVER_VERSION "1.78.18"
  15
  16 #include "bnx2x.h"
  17 #include "bnx2x_vfpf.h"
  18 #include "ecore_sp.h"
  19 #include "ecore_init.h"
  20 #include "ecore_init_ops.h"
  21
  22 #include "rte_version.h"
  23
  24 #include <sys/types.h>
  25 #include <sys/stat.h>
  26 #include <fcntl.h>
  27 #include <zlib.h>
  28
  29 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
  30 #define BNX2X_PMD_VERSION_MAJOR 1
  31 #define BNX2X_PMD_VERSION_MINOR 0
  32 #define BNX2X_PMD_VERSION_REVISION 6
  33 #define BNX2X_PMD_VERSION_PATCH 1
  34
  35 static inline const char *
  36 bnx2x_pmd_version(void)
  37 {
  38         static char version[32];
  39
  40         snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
  41                         BNX2X_PMD_VER_PREFIX,
  42                         BNX2X_DRIVER_VERSION,
  43                         BNX2X_PMD_VERSION_MAJOR,
  44                         BNX2X_PMD_VERSION_MINOR,
  45                         BNX2X_PMD_VERSION_REVISION,
  46                         BNX2X_PMD_VERSION_PATCH);
  47
  48         return version;
  49 }
  50
  51 static z_stream zlib_stream;
  52
  53 #define EVL_VLID_MASK 0x0FFF
  54
  55 #define BNX2X_DEF_SB_ATT_IDX 0x0001
  56 #define BNX2X_DEF_SB_IDX     0x0002
  57
  58 /*
  59  * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
  60  * function HW initialization.
  61  */
  62 #define FLR_WAIT_USEC     10000 /* 10 msecs */
  63 #define FLR_WAIT_INTERVAL 50    /* usecs */
  64 #define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)   /* 200 */
  65
  66 struct pbf_pN_buf_regs {
  67         int pN;
  68         uint32_t init_crd;
  69         uint32_t crd;
  70         uint32_t crd_freed;
  71 };
  72
  73 struct pbf_pN_cmd_regs {
  74         int pN;
  75         uint32_t lines_occup;
  76         uint32_t lines_freed;
  77 };
  78
  79 /* resources needed for unloading a previously loaded device */
  80
  81 #define BNX2X_PREV_WAIT_NEEDED 1
  82 rte_spinlock_t bnx2x_prev_mtx;
  83 struct bnx2x_prev_list_node {
  84         LIST_ENTRY(bnx2x_prev_list_node) node;
  85         uint8_t bus;
  86         uint8_t slot;
  87         uint8_t path;
  88         uint8_t aer;
  89         uint8_t undi;
  90 };
  91
  92 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
  93         = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
  94
  95 static int load_count[2][3] = { { 0 } };
  96         /* per-path: 0-common, 1-port0, 2-port1 */
  97
  98 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
  99                                 uint8_t cmng_type);
 100 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
 101 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
 102                               uint8_t port);
 103 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
 104 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
 105 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
 106 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
 107 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
 108                                      uint8_t print);
 109 static void bnx2x_int_disable(struct bnx2x_softc *sc);
 110 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
 111 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
 112 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
 113                                  struct bnx2x_fastpath *fp,
 114                                  uint16_t rx_bd_prod, uint16_t rx_cq_prod);
 115 static void bnx2x_link_report(struct bnx2x_softc *sc);
 116 void bnx2x_link_status_update(struct bnx2x_softc *sc);
 117 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
 118 static void bnx2x_free_mem(struct bnx2x_softc *sc);
 119 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
 120 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
 121 static __rte_noinline
 122 int bnx2x_nic_load(struct bnx2x_softc *sc);
 123
 124 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
 125 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
 126 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
 127                          uint8_t storm, uint16_t index, uint8_t op,
 128                          uint8_t update);
 129
 130 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
 131 {
 132         int res;
 133
 134         mb();
 135         res = ((*addr) & (1UL << nr)) != 0;
 136         mb();
 137         return res;
 138 }
 139
 140 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
 141 {
 142         __sync_fetch_and_or(addr, (1UL << nr));
 143 }
 144
 145 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
 146 {
 147         __sync_fetch_and_and(addr, ~(1UL << nr));
 148 }
 149
 150 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
 151 {
 152         unsigned long mask = (1UL << nr);
 153         return __sync_fetch_and_and(addr, ~mask) & mask;
 154 }
 155
 156 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
 157 {
 158         return __sync_val_compare_and_swap(addr, old, new);
 159 }
 160
 161 int
 162 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
 163               const char *msg, uint32_t align)
 164 {
 165         char mz_name[RTE_MEMZONE_NAMESIZE];
 166         const struct rte_memzone *z;
 167
 168         dma->sc = sc;
 169         if (IS_PF(sc))
 170                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
 171                         rte_get_timer_cycles());
 172         else
 173                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
 174                         rte_get_timer_cycles());
 175
 176         /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
 177         z = rte_memzone_reserve_aligned(mz_name, (uint64_t)size,
 178                                         SOCKET_ID_ANY,
 179                                         RTE_MEMZONE_IOVA_CONTIG, align);
 180         if (z == NULL) {
 181                 PMD_DRV_LOG(ERR, sc, "DMA alloc failed for %s", msg);
 182                 return -ENOMEM;
 183         }
 184         dma->paddr = (uint64_t) z->iova;
 185         dma->vaddr = z->addr;
 186
 187         PMD_DRV_LOG(DEBUG, sc,
 188                     "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
 189
 190         return 0;
 191 }
 192
 193 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 194 {
 195         uint32_t lock_status;
 196         uint32_t resource_bit = (1 << resource);
 197         int func = SC_FUNC(sc);
 198         uint32_t hw_lock_control_reg;
 199         int cnt;
 200
 201         PMD_INIT_FUNC_TRACE(sc);
 202
 203         /* validate the resource is within range */
 204         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 205                 PMD_DRV_LOG(NOTICE, sc,
 206                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 207                             resource);
 208                 return -1;
 209         }
 210
 211         if (func <= 5) {
 212                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 213         } else {
 214                 hw_lock_control_reg =
 215                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 216         }
 217
 218         /* validate the resource is not already taken */
 219         lock_status = REG_RD(sc, hw_lock_control_reg);
 220         if (lock_status & resource_bit) {
 221                 PMD_DRV_LOG(NOTICE, sc,
 222                             "resource in use (status 0x%x bit 0x%x)",
 223                             lock_status, resource_bit);
 224                 return -1;
 225         }
 226
 227         /* try every 5ms for 5 seconds */
 228         for (cnt = 0; cnt < 1000; cnt++) {
 229                 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
 230                 lock_status = REG_RD(sc, hw_lock_control_reg);
 231                 if (lock_status & resource_bit) {
 232                         return 0;
 233                 }
 234                 DELAY(5000);
 235         }
 236
 237         PMD_DRV_LOG(NOTICE, sc, "Resource lock timeout!");
 238         return -1;
 239 }
 240
 241 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 242 {
 243         uint32_t lock_status;
 244         uint32_t resource_bit = (1 << resource);
 245         int func = SC_FUNC(sc);
 246         uint32_t hw_lock_control_reg;
 247
 248         PMD_INIT_FUNC_TRACE(sc);
 249
 250         /* validate the resource is within range */
 251         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 252                 PMD_DRV_LOG(NOTICE, sc,
 253                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 254                             resource);
 255                 return -1;
 256         }
 257
 258         if (func <= 5) {
 259                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 260         } else {
 261                 hw_lock_control_reg =
 262                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 263         }
 264
 265         /* validate the resource is currently taken */
 266         lock_status = REG_RD(sc, hw_lock_control_reg);
 267         if (!(lock_status & resource_bit)) {
 268                 PMD_DRV_LOG(NOTICE, sc,
 269                             "resource not in use (status 0x%x bit 0x%x)",
 270                             lock_status, resource_bit);
 271                 return -1;
 272         }
 273
 274         REG_WR(sc, hw_lock_control_reg, resource_bit);
 275         return 0;
 276 }
 277
 278 /* copy command into DMAE command memory and set DMAE command Go */
 279 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
 280 {
 281         uint32_t cmd_offset;
 282         uint32_t i;
 283
 284         cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
 285         for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
 286                 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
 287         }
 288
 289         REG_WR(sc, dmae_reg_go_c[idx], 1);
 290 }
 291
 292 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
 293 {
 294         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 295                           DMAE_COMMAND_C_TYPE_ENABLE);
 296 }
 297
 298 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
 299 {
 300         return opcode & ~DMAE_COMMAND_SRC_RESET;
 301 }
 302
 303 uint32_t
 304 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
 305                 uint8_t with_comp, uint8_t comp_type)
 306 {
 307         uint32_t opcode = 0;
 308
 309         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 310                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 311
 312         opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
 313
 314         opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 315
 316         opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
 317                    (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
 318
 319         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 320
 321 #ifdef __BIG_ENDIAN
 322         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 323 #else
 324         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 325 #endif
 326
 327         if (with_comp) {
 328                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 329         }
 330
 331         return opcode;
 332 }
 333
 334 static void
 335 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
 336                         uint8_t src_type, uint8_t dst_type)
 337 {
 338         memset(dmae, 0, sizeof(struct dmae_command));
 339
 340         /* set the opcode */
 341         dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
 342                                        TRUE, DMAE_COMP_PCI);
 343
 344         /* fill in the completion parameters */
 345         dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
 346         dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
 347         dmae->comp_val = DMAE_COMP_VAL;
 348 }
 349
 350 /* issue a DMAE command over the init channel and wait for completion */
 351 static int
 352 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
 353 {
 354         uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
 355         int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
 356
 357         /* reset completion */
 358         *wb_comp = 0;
 359
 360         /* post the command on the channel used for initializations */
 361         bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
 362
 363         /* wait for completion */
 364         DELAY(500);
 365
 366         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 367                 if (!timeout ||
 368                     (sc->recovery_state != BNX2X_RECOVERY_DONE &&
 369                      sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 370                         PMD_DRV_LOG(INFO, sc, "DMAE timeout!");
 371                         return DMAE_TIMEOUT;
 372                 }
 373
 374                 timeout--;
 375                 DELAY(50);
 376         }
 377
 378         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 379                 PMD_DRV_LOG(INFO, sc, "DMAE PCI error!");
 380                 return DMAE_PCI_ERROR;
 381         }
 382
 383         return 0;
 384 }
 385
 386 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
 387 {
 388         struct dmae_command dmae;
 389         uint32_t *data;
 390         uint32_t i;
 391         int rc;
 392
 393         if (!sc->dmae_ready) {
 394                 data = BNX2X_SP(sc, wb_data[0]);
 395
 396                 for (i = 0; i < len32; i++) {
 397                         data[i] = REG_RD(sc, (src_addr + (i * 4)));
 398                 }
 399
 400                 return;
 401         }
 402
 403         /* set opcode and fixed command fields */
 404         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 405
 406         /* fill in addresses and len */
 407         dmae.src_addr_lo = (src_addr >> 2);     /* GRC addr has dword resolution */
 408         dmae.src_addr_hi = 0;
 409         dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
 410         dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
 411         dmae.len = len32;
 412
 413         /* issue the command and wait for completion */
 414         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 415                 rte_panic("DMAE failed (%d)", rc);
 416         };
 417 }
 418
 419 void
 420 bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr,
 421                uint32_t len32)
 422 {
 423         struct dmae_command dmae;
 424         int rc;
 425
 426         if (!sc->dmae_ready) {
 427                 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
 428                 return;
 429         }
 430
 431         /* set opcode and fixed command fields */
 432         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 433
 434         /* fill in addresses and len */
 435         dmae.src_addr_lo = U64_LO(dma_addr);
 436         dmae.src_addr_hi = U64_HI(dma_addr);
 437         dmae.dst_addr_lo = (dst_addr >> 2);     /* GRC addr has dword resolution */
 438         dmae.dst_addr_hi = 0;
 439         dmae.len = len32;
 440
 441         /* issue the command and wait for completion */
 442         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 443                 rte_panic("DMAE failed (%d)", rc);
 444         }
 445 }
 446
 447 static void
 448 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
 449                         uint32_t addr, uint32_t len)
 450 {
 451         uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
 452         uint32_t offset = 0;
 453
 454         while (len > dmae_wr_max) {
 455                 bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 456                                (addr + offset), /* dst GRC address */
 457                                dmae_wr_max);
 458                 offset += (dmae_wr_max * 4);
 459                 len -= dmae_wr_max;
 460         }
 461
 462         bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 463                        (addr + offset), /* dst GRC address */
 464                        len);
 465 }
 466
 467 void
 468 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
 469                        uint32_t cid)
 470 {
 471         /* ustorm cxt validation */
 472         cxt->ustorm_ag_context.cdu_usage =
 473             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 474                                    CDU_REGION_NUMBER_UCM_AG,
 475                                    ETH_CONNECTION_TYPE);
 476         /* xcontext validation */
 477         cxt->xstorm_ag_context.cdu_reserved =
 478             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 479                                    CDU_REGION_NUMBER_XCM_AG,
 480                                    ETH_CONNECTION_TYPE);
 481 }
 482
 483 static void
 484 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 485                             uint8_t sb_index, uint8_t ticks)
 486 {
 487         uint32_t addr =
 488             (BAR_CSTRORM_INTMEM +
 489              CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
 490
 491         REG_WR8(sc, addr, ticks);
 492 }
 493
 494 static void
 495 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
 496                             uint8_t sb_index, uint8_t disable)
 497 {
 498         uint32_t enable_flag =
 499             (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
 500         uint32_t addr =
 501             (BAR_CSTRORM_INTMEM +
 502              CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
 503         uint8_t flags;
 504
 505         /* clear and set */
 506         flags = REG_RD8(sc, addr);
 507         flags &= ~HC_INDEX_DATA_HC_ENABLED;
 508         flags |= enable_flag;
 509         REG_WR8(sc, addr, flags);
 510 }
 511
 512 void
 513 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 514                              uint8_t sb_index, uint8_t disable, uint16_t usec)
 515 {
 516         uint8_t ticks = (usec / 4);
 517
 518         bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
 519
 520         disable = (disable) ? 1 : ((usec) ? 0 : 1);
 521         bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
 522 }
 523
 524 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
 525 {
 526         return REG_RD(sc, reg_addr);
 527 }
 528
 529 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
 530 {
 531         REG_WR(sc, reg_addr, val);
 532 }
 533
 534 void
 535 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
 536                    __rte_unused const elink_log_id_t elink_log_id, ...)
 537 {
 538         PMD_DRV_LOG(DEBUG, sc, "ELINK EVENT LOG (%d)", elink_log_id);
 539 }
 540
 541 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
 542 {
 543         uint32_t spio_reg;
 544
 545         /* Only 2 SPIOs are configurable */
 546         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
 547                 PMD_DRV_LOG(NOTICE, sc, "Invalid SPIO 0x%x", spio);
 548                 return -1;
 549         }
 550
 551         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 552
 553         /* read SPIO and mask except the float bits */
 554         spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
 555
 556         switch (mode) {
 557         case MISC_SPIO_OUTPUT_LOW:
 558                 /* clear FLOAT and set CLR */
 559                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 560                 spio_reg |= (spio << MISC_SPIO_CLR_POS);
 561                 break;
 562
 563         case MISC_SPIO_OUTPUT_HIGH:
 564                 /* clear FLOAT and set SET */
 565                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 566                 spio_reg |= (spio << MISC_SPIO_SET_POS);
 567                 break;
 568
 569         case MISC_SPIO_INPUT_HI_Z:
 570                 /* set FLOAT */
 571                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
 572                 break;
 573
 574         default:
 575                 break;
 576         }
 577
 578         REG_WR(sc, MISC_REG_SPIO, spio_reg);
 579         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 580
 581         return 0;
 582 }
 583
 584 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
 585 {
 586         /* The GPIO should be swapped if swap register is set and active */
 587         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 588                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 589         int gpio_shift = gpio_num;
 590         if (gpio_port)
 591                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 592
 593         uint32_t gpio_mask = (1 << gpio_shift);
 594         uint32_t gpio_reg;
 595
 596         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 597                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 598                 return -1;
 599         }
 600
 601         /* read GPIO value */
 602         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 603
 604         /* get the requested pin value */
 605         return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
 606 }
 607
 608 static int
 609 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
 610 {
 611         /* The GPIO should be swapped if swap register is set and active */
 612         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 613                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 614         int gpio_shift = gpio_num;
 615         if (gpio_port)
 616                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 617
 618         uint32_t gpio_mask = (1 << gpio_shift);
 619         uint32_t gpio_reg;
 620
 621         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 622                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 623                 return -1;
 624         }
 625
 626         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 627
 628         /* read GPIO and mask except the float bits */
 629         gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
 630
 631         switch (mode) {
 632         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 633                 /* clear FLOAT and set CLR */
 634                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 635                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
 636                 break;
 637
 638         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 639                 /* clear FLOAT and set SET */
 640                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 641                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
 642                 break;
 643
 644         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 645                 /* set FLOAT */
 646                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 647                 break;
 648
 649         default:
 650                 break;
 651         }
 652
 653         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 654         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 655
 656         return 0;
 657 }
 658
 659 static int
 660 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
 661 {
 662         uint32_t gpio_reg;
 663
 664         /* any port swapping should be handled by caller */
 665
 666         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 667
 668         /* read GPIO and mask except the float bits */
 669         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 670         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 671         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
 672         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
 673
 674         switch (mode) {
 675         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 676                 /* set CLR */
 677                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
 678                 break;
 679
 680         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 681                 /* set SET */
 682                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
 683                 break;
 684
 685         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 686                 /* set FLOAT */
 687                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 688                 break;
 689
 690         default:
 691                 PMD_DRV_LOG(NOTICE, sc,
 692                             "Invalid GPIO mode assignment %d", mode);
 693                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 694                 return -1;
 695         }
 696
 697         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 698         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 699
 700         return 0;
 701 }
 702
 703 static int
 704 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
 705                    uint8_t port)
 706 {
 707         /* The GPIO should be swapped if swap register is set and active */
 708         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 709                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 710         int gpio_shift = gpio_num;
 711         if (gpio_port)
 712                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 713
 714         uint32_t gpio_mask = (1 << gpio_shift);
 715         uint32_t gpio_reg;
 716
 717         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 718                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 719                 return -1;
 720         }
 721
 722         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 723
 724         /* read GPIO int */
 725         gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
 726
 727         switch (mode) {
 728         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
 729                 /* clear SET and set CLR */
 730                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 731                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 732                 break;
 733
 734         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
 735                 /* clear CLR and set SET */
 736                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 737                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 738                 break;
 739
 740         default:
 741                 break;
 742         }
 743
 744         REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
 745         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 746
 747         return 0;
 748 }
 749
 750 uint32_t
 751 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
 752 {
 753         return bnx2x_gpio_read(sc, gpio_num, port);
 754 }
 755
 756 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,   /* 0=low 1=high */
 757                             uint8_t port)
 758 {
 759         return bnx2x_gpio_write(sc, gpio_num, mode, port);
 760 }
 761
 762 uint8_t
 763 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
 764                          uint8_t mode /* 0=low 1=high */ )
 765 {
 766         return bnx2x_gpio_mult_write(sc, pins, mode);
 767 }
 768
 769 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,       /* 0=low 1=high */
 770                                 uint8_t port)
 771 {
 772         return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
 773 }
 774
 775 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
 776 {
 777         REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
 778                     (SC_FUNC(sc) * sizeof(uint32_t))), 1);
 779 }
 780
 781 /* send the MCP a request, block until there is a reply */
 782 uint32_t
 783 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 784 {
 785         int mb_idx = SC_FW_MB_IDX(sc);
 786         uint32_t seq;
 787         uint32_t rc = 0;
 788         uint32_t cnt = 1;
 789         uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
 790
 791         seq = ++sc->fw_seq;
 792         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
 793         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
 794
 795         PMD_DRV_LOG(DEBUG, sc,
 796                     "wrote command 0x%08x to FW MB param 0x%08x",
 797                     (command | seq), param);
 798
 799         /* Let the FW do it's magic. GIve it up to 5 seconds... */
 800         do {
 801                 DELAY(delay * 1000);
 802                 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
 803         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
 804
 805         /* is this a reply to our command? */
 806         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
 807                 rc &= FW_MSG_CODE_MASK;
 808         } else {
 809                 /* Ruh-roh! */
 810                 PMD_DRV_LOG(NOTICE, sc, "FW failed to respond!");
 811                 rc = 0;
 812         }
 813
 814         return rc;
 815 }
 816
 817 static uint32_t
 818 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 819 {
 820         return elink_cb_fw_command(sc, command, param);
 821 }
 822
 823 static void
 824 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
 825                            rte_iova_t mapping)
 826 {
 827         REG_WR(sc, addr, U64_LO(mapping));
 828         REG_WR(sc, (addr + 4), U64_HI(mapping));
 829 }
 830
 831 static void
 832 storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping,
 833                       uint16_t abs_fid)
 834 {
 835         uint32_t addr = (XSEM_REG_FAST_MEMORY +
 836                          XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
 837         __storm_memset_dma_mapping(sc, addr, mapping);
 838 }
 839
 840 static void
 841 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
 842 {
 843         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
 844                 pf_id);
 845         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
 846                 pf_id);
 847         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
 848                 pf_id);
 849         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
 850                 pf_id);
 851 }
 852
 853 static void
 854 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
 855 {
 856         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
 857                 enable);
 858         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
 859                 enable);
 860         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
 861                 enable);
 862         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
 863                 enable);
 864 }
 865
 866 static void
 867 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
 868                      uint16_t pfid)
 869 {
 870         uint32_t addr;
 871         size_t size;
 872
 873         addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
 874         size = sizeof(struct event_ring_data);
 875         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
 876 }
 877
 878 static void
 879 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
 880 {
 881         uint32_t addr = (BAR_CSTRORM_INTMEM +
 882                          CSTORM_EVENT_RING_PROD_OFFSET(pfid));
 883         REG_WR16(sc, addr, eq_prod);
 884 }
 885
 886 /*
 887  * Post a slowpath command.
 888  *
 889  * A slowpath command is used to propagate a configuration change through
 890  * the controller in a controlled manner, allowing each STORM processor and
 891  * other H/W blocks to phase in the change.  The commands sent on the
 892  * slowpath are referred to as ramrods.  Depending on the ramrod used the
 893  * completion of the ramrod will occur in different ways.  Here's a
 894  * breakdown of ramrods and how they complete:
 895  *
 896  * RAMROD_CMD_ID_ETH_PORT_SETUP
 897  *   Used to setup the leading connection on a port.  Completes on the
 898  *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
 899  *
 900  * RAMROD_CMD_ID_ETH_CLIENT_SETUP
 901  *   Used to setup an additional connection on a port.  Completes on the
 902  *   RCQ of the multi-queue/RSS connection being initialized.
 903  *
 904  * RAMROD_CMD_ID_ETH_STAT_QUERY
 905  *   Used to force the storm processors to update the statistics database
 906  *   in host memory.  This ramrod is send on the leading connection CID and
 907  *   completes as an index increment of the CSTORM on the default status
 908  *   block.
 909  *
 910  * RAMROD_CMD_ID_ETH_UPDATE
 911  *   Used to update the state of the leading connection, usually to udpate
 912  *   the RSS indirection table.  Completes on the RCQ of the leading
 913  *   connection. (Not currently used under FreeBSD until OS support becomes
 914  *   available.)
 915  *
 916  * RAMROD_CMD_ID_ETH_HALT
 917  *   Used when tearing down a connection prior to driver unload.  Completes
 918  *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
 919  *   use this on the leading connection.
 920  *
 921  * RAMROD_CMD_ID_ETH_SET_MAC
 922  *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
 923  *   the RCQ of the leading connection.
 924  *
 925  * RAMROD_CMD_ID_ETH_CFC_DEL
 926  *   Used when tearing down a conneciton prior to driver unload.  Completes
 927  *   on the RCQ of the leading connection (since the current connection
 928  *   has been completely removed from controller memory).
 929  *
 930  * RAMROD_CMD_ID_ETH_PORT_DEL
 931  *   Used to tear down the leading connection prior to driver unload,
 932  *   typically fp[0].  Completes as an index increment of the CSTORM on the
 933  *   default status block.
 934  *
 935  * RAMROD_CMD_ID_ETH_FORWARD_SETUP
 936  *   Used for connection offload.  Completes on the RCQ of the multi-queue
 937  *   RSS connection that is being offloaded.  (Not currently used under
 938  *   FreeBSD.)
 939  *
 940  * There can only be one command pending per function.
 941  *
 942  * Returns:
 943  *   0 = Success, !0 = Failure.
 944  */
 945
 946 /* must be called under the spq lock */
 947 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
 948 {
 949         struct eth_spe *next_spe = sc->spq_prod_bd;
 950
 951         if (sc->spq_prod_bd == sc->spq_last_bd) {
 952                 /* wrap back to the first eth_spq */
 953                 sc->spq_prod_bd = sc->spq;
 954                 sc->spq_prod_idx = 0;
 955         } else {
 956                 sc->spq_prod_bd++;
 957                 sc->spq_prod_idx++;
 958         }
 959
 960         return next_spe;
 961 }
 962
 963 /* must be called under the spq lock */
 964 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
 965 {
 966         int func = SC_FUNC(sc);
 967
 968         /*
 969          * Make sure that BD data is updated before writing the producer.
 970          * BD data is written to the memory, the producer is read from the
 971          * memory, thus we need a full memory barrier to ensure the ordering.
 972          */
 973         mb();
 974
 975         REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
 976                  sc->spq_prod_idx);
 977
 978         mb();
 979 }
 980
 981 /**
 982  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
 983  *
 984  * @cmd:      command to check
 985  * @cmd_type: command type
 986  */
 987 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
 988 {
 989         if ((cmd_type == NONE_CONNECTION_TYPE) ||
 990             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
 991             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
 992             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
 993             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
 994             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
 995             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
 996                 return TRUE;
 997         } else {
 998                 return FALSE;
 999         }
1000 }
1001
1002 /**
1003  * bnx2x_sp_post - place a single command on an SP ring
1004  *
1005  * @sc:         driver handle
1006  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
1007  * @cid:        SW CID the command is related to
1008  * @data_hi:    command private data address (high 32 bits)
1009  * @data_lo:    command private data address (low 32 bits)
1010  * @cmd_type:   command type (e.g. NONE, ETH)
1011  *
1012  * SP data is handled as if it's always an address pair, thus data fields are
1013  * not swapped to little endian in upper functions. Instead this function swaps
1014  * data as if it's two uint32 fields.
1015  */
1016 int
1017 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1018             uint32_t data_lo, int cmd_type)
1019 {
1020         struct eth_spe *spe;
1021         uint16_t type;
1022         int common;
1023
1024         common = bnx2x_is_contextless_ramrod(command, cmd_type);
1025
1026         if (common) {
1027                 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1028                         PMD_DRV_LOG(INFO, sc, "EQ ring is full!");
1029                         return -1;
1030                 }
1031         } else {
1032                 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1033                         PMD_DRV_LOG(INFO, sc, "SPQ ring is full!");
1034                         return -1;
1035                 }
1036         }
1037
1038         spe = bnx2x_sp_get_next(sc);
1039
1040         /* CID needs port number to be encoded int it */
1041         spe->hdr.conn_and_cmd_data =
1042             htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1043
1044         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1045
1046         /* TBD: Check if it works for VFs */
1047         type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1048                  SPE_HDR_FUNCTION_ID);
1049
1050         spe->hdr.type = htole16(type);
1051
1052         spe->data.update_data_addr.hi = htole32(data_hi);
1053         spe->data.update_data_addr.lo = htole32(data_lo);
1054
1055         /*
1056          * It's ok if the actual decrement is issued towards the memory
1057          * somewhere between the lock and unlock. Thus no more explict
1058          * memory barrier is needed.
1059          */
1060         if (common) {
1061                 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1062         } else {
1063                 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1064         }
1065
1066         PMD_DRV_LOG(DEBUG, sc,
1067                     "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1068                     "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1069                     sc->spq_prod_idx,
1070                     (uint32_t) U64_HI(sc->spq_dma.paddr),
1071                     (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1072                                 (uint8_t *) sc->spq_prod_bd -
1073                                 (uint8_t *) sc->spq), command, common,
1074                     HW_CID(sc, cid), data_hi, data_lo, type,
1075                     atomic_load_acq_long(&sc->cq_spq_left),
1076                     atomic_load_acq_long(&sc->eq_spq_left));
1077
1078         bnx2x_sp_prod_update(sc);
1079
1080         return 0;
1081 }
1082
1083 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1084 {
1085         SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1086                  sc->fw_drv_pulse_wr_seq);
1087 }
1088
1089 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1090 {
1091         uint16_t hw_cons;
1092         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1093
1094         if (unlikely(!txq)) {
1095                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1096                 return 0;
1097         }
1098
1099         mb();                   /* status block fields can change */
1100         hw_cons = le16toh(*fp->tx_cons_sb);
1101         return hw_cons != txq->tx_pkt_head;
1102 }
1103
1104 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1105 {
1106         /* expand this for multi-cos if ever supported */
1107         return bnx2x_tx_queue_has_work(fp);
1108 }
1109
1110 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1111 {
1112         uint16_t rx_cq_cons_sb;
1113         struct bnx2x_rx_queue *rxq;
1114         rxq = fp->sc->rx_queues[fp->index];
1115         if (unlikely(!rxq)) {
1116                 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1117                 return 0;
1118         }
1119
1120         mb();                   /* status block fields can change */
1121         rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1122         if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1123                      MAX_RCQ_ENTRIES(rxq)))
1124                 rx_cq_cons_sb++;
1125         return rxq->rx_cq_head != rx_cq_cons_sb;
1126 }
1127
1128 static void
1129 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1130              union eth_rx_cqe *rr_cqe)
1131 {
1132         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1133         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1134         enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1135         struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1136
1137         PMD_DRV_LOG(DEBUG, sc,
1138                     "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1139                     fp->index, cid, command, sc->state,
1140                     rr_cqe->ramrod_cqe.ramrod_type);
1141
1142         switch (command) {
1143         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1144                 PMD_DRV_LOG(DEBUG, sc, "got UPDATE ramrod. CID %d", cid);
1145                 drv_cmd = ECORE_Q_CMD_UPDATE;
1146                 break;
1147
1148         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1149                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] setup ramrod", cid);
1150                 drv_cmd = ECORE_Q_CMD_SETUP;
1151                 break;
1152
1153         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1154                 PMD_DRV_LOG(DEBUG, sc,
1155                             "got MULTI[%d] tx-only setup ramrod", cid);
1156                 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1157                 break;
1158
1159         case (RAMROD_CMD_ID_ETH_HALT):
1160                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] halt ramrod", cid);
1161                 drv_cmd = ECORE_Q_CMD_HALT;
1162                 break;
1163
1164         case (RAMROD_CMD_ID_ETH_TERMINATE):
1165                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] teminate ramrod", cid);
1166                 drv_cmd = ECORE_Q_CMD_TERMINATE;
1167                 break;
1168
1169         case (RAMROD_CMD_ID_ETH_EMPTY):
1170                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] empty ramrod", cid);
1171                 drv_cmd = ECORE_Q_CMD_EMPTY;
1172                 break;
1173
1174         default:
1175                 PMD_DRV_LOG(DEBUG, sc,
1176                             "ERROR: unexpected MC reply (%d)"
1177                             "on fp[%d]", command, fp->index);
1178                 return;
1179         }
1180
1181         if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1182             q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1183                 /*
1184                  * q_obj->complete_cmd() failure means that this was
1185                  * an unexpected completion.
1186                  *
1187                  * In this case we don't want to increase the sc->spq_left
1188                  * because apparently we haven't sent this command the first
1189                  * place.
1190                  */
1191                 // rte_panic("Unexpected SP completion");
1192                 return;
1193         }
1194
1195         atomic_add_acq_long(&sc->cq_spq_left, 1);
1196
1197         PMD_DRV_LOG(DEBUG, sc, "sc->cq_spq_left 0x%lx",
1198                     atomic_load_acq_long(&sc->cq_spq_left));
1199 }
1200
1201 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1202 {
1203         struct bnx2x_rx_queue *rxq;
1204         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1205         uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1206
1207         rxq = sc->rx_queues[fp->index];
1208         if (!rxq) {
1209                 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1210                 return 0;
1211         }
1212
1213         /* CQ "next element" is of the size of the regular element */
1214         hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1215         if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1216                      USABLE_RCQ_ENTRIES_PER_PAGE)) {
1217                 hw_cq_cons++;
1218         }
1219
1220         bd_cons = rxq->rx_bd_head;
1221         bd_prod = rxq->rx_bd_tail;
1222         bd_prod_fw = bd_prod;
1223         sw_cq_cons = rxq->rx_cq_head;
1224         sw_cq_prod = rxq->rx_cq_tail;
1225
1226         /*
1227          * Memory barrier necessary as speculative reads of the rx
1228          * buffer can be ahead of the index in the status block
1229          */
1230         rmb();
1231
1232         while (sw_cq_cons != hw_cq_cons) {
1233                 union eth_rx_cqe *cqe;
1234                 struct eth_fast_path_rx_cqe *cqe_fp;
1235                 uint8_t cqe_fp_flags;
1236                 enum eth_rx_cqe_type cqe_fp_type;
1237
1238                 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1239                 bd_prod = RX_BD(bd_prod, rxq);
1240                 bd_cons = RX_BD(bd_cons, rxq);
1241
1242                 cqe = &rxq->cq_ring[comp_ring_cons];
1243                 cqe_fp = &cqe->fast_path_cqe;
1244                 cqe_fp_flags = cqe_fp->type_error_flags;
1245                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1246
1247                 /* is this a slowpath msg? */
1248                 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1249                         bnx2x_sp_event(sc, fp, cqe);
1250                         goto next_cqe;
1251                 }
1252
1253                 /* is this an error packet? */
1254                 if (unlikely(cqe_fp_flags &
1255                              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1256                         PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1257                                    cqe_fp_flags, sw_cq_cons);
1258                         goto next_rx;
1259                 }
1260
1261                 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1262
1263 next_rx:
1264                 bd_cons = NEXT_RX_BD(bd_cons);
1265                 bd_prod = NEXT_RX_BD(bd_prod);
1266                 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1267
1268 next_cqe:
1269                 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1270                 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1271
1272         }                       /* while work to do */
1273
1274         rxq->rx_bd_head = bd_cons;
1275         rxq->rx_bd_tail = bd_prod_fw;
1276         rxq->rx_cq_head = sw_cq_cons;
1277         rxq->rx_cq_tail = sw_cq_prod;
1278
1279         /* Update producers */
1280         bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1281
1282         return sw_cq_cons != hw_cq_cons;
1283 }
1284
1285 static uint16_t
1286 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1287                 uint16_t pkt_idx, uint16_t bd_idx)
1288 {
1289         struct eth_tx_start_bd *tx_start_bd =
1290             &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1291         uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1292         struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1293
1294         if (likely(tx_mbuf != NULL)) {
1295                 rte_pktmbuf_free_seg(tx_mbuf);
1296         } else {
1297                 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1298                            fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1299         }
1300
1301         txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1302         txq->nb_tx_avail += nbd;
1303
1304         while (nbd--)
1305                 bd_idx = NEXT_TX_BD(bd_idx);
1306
1307         return bd_idx;
1308 }
1309
1310 /* processes transmit completions */
1311 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1312 {
1313         uint16_t bd_cons, hw_cons, sw_cons;
1314         __rte_unused uint16_t tx_bd_avail;
1315
1316         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1317
1318         if (unlikely(!txq)) {
1319                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1320                 return 0;
1321         }
1322
1323         bd_cons = txq->tx_bd_head;
1324         hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1325         sw_cons = txq->tx_pkt_head;
1326
1327         while (sw_cons != hw_cons) {
1328                 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1329                 sw_cons++;
1330         }
1331
1332         txq->tx_pkt_head = sw_cons;
1333         txq->tx_bd_head = bd_cons;
1334
1335         tx_bd_avail = txq->nb_tx_avail;
1336
1337         PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1338                    "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1339                    fp->index, tx_bd_avail, hw_cons,
1340                    txq->tx_pkt_head, txq->tx_pkt_tail,
1341                    txq->tx_bd_head, txq->tx_bd_tail);
1342         return TRUE;
1343 }
1344
1345 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1346 {
1347         struct bnx2x_fastpath *fp;
1348         int i, count;
1349
1350         /* wait until all TX fastpath tasks have completed */
1351         for (i = 0; i < sc->num_queues; i++) {
1352                 fp = &sc->fp[i];
1353
1354                 count = 1000;
1355
1356                 while (bnx2x_has_tx_work(fp)) {
1357                         bnx2x_txeof(sc, fp);
1358
1359                         if (count == 0) {
1360                                 PMD_TX_LOG(ERR,
1361                                            "Timeout waiting for fp[%d] "
1362                                            "transmits to complete!", i);
1363                                 rte_panic("tx drain failure");
1364                                 return;
1365                         }
1366
1367                         count--;
1368                         DELAY(1000);
1369                         rmb();
1370                 }
1371         }
1372
1373         return;
1374 }
1375
1376 static int
1377 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1378                  int mac_type, uint8_t wait_for_comp)
1379 {
1380         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1381         int rc;
1382
1383         /* wait for completion of requested */
1384         if (wait_for_comp) {
1385                 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1386         }
1387
1388         /* Set the mac type of addresses we want to clear */
1389         bnx2x_set_bit(mac_type, &vlan_mac_flags);
1390
1391         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1392         if (rc < 0)
1393                 PMD_DRV_LOG(ERR, sc, "Failed to delete MACs (%d)", rc);
1394
1395         return rc;
1396 }
1397
1398 static int
1399 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1400                         unsigned long *rx_accept_flags,
1401                         unsigned long *tx_accept_flags)
1402 {
1403         /* Clear the flags first */
1404         *rx_accept_flags = 0;
1405         *tx_accept_flags = 0;
1406
1407         switch (rx_mode) {
1408         case BNX2X_RX_MODE_NONE:
1409                 /*
1410                  * 'drop all' supersedes any accept flags that may have been
1411                  * passed to the function.
1412                  */
1413                 break;
1414
1415         case BNX2X_RX_MODE_NORMAL:
1416                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1417                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1418                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1419
1420                 /* internal switching mode */
1421                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1422                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1423                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1424
1425                 break;
1426
1427         case BNX2X_RX_MODE_ALLMULTI:
1428                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1429                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1430                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1431
1432                 /* internal switching mode */
1433                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1434                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1435                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1436
1437                 break;
1438
1439         case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1440         case BNX2X_RX_MODE_PROMISC:
1441                 /*
1442                  * According to deffinition of SI mode, iface in promisc mode
1443                  * should receive matched and unmatched (in resolution of port)
1444                  * unicast packets.
1445                  */
1446                 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1447                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1448                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1449                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1450
1451                 /* internal switching mode */
1452                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1453                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1454
1455                 if (IS_MF_SI(sc)) {
1456                         bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1457                 } else {
1458                         bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1459                 }
1460
1461                 break;
1462
1463         default:
1464                 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1465                 return -1;
1466         }
1467
1468         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1469         if (rx_mode != BNX2X_RX_MODE_NONE) {
1470                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1471                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1472         }
1473
1474         return 0;
1475 }
1476
1477 static int
1478 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1479                   unsigned long rx_mode_flags,
1480                   unsigned long rx_accept_flags,
1481                   unsigned long tx_accept_flags, unsigned long ramrod_flags)
1482 {
1483         struct ecore_rx_mode_ramrod_params ramrod_param;
1484         int rc;
1485
1486         memset(&ramrod_param, 0, sizeof(ramrod_param));
1487
1488         /* Prepare ramrod parameters */
1489         ramrod_param.cid = 0;
1490         ramrod_param.cl_id = cl_id;
1491         ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1492         ramrod_param.func_id = SC_FUNC(sc);
1493
1494         ramrod_param.pstate = &sc->sp_state;
1495         ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1496
1497         ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1498         ramrod_param.rdata_mapping =
1499             (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1500             bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1501
1502         ramrod_param.ramrod_flags = ramrod_flags;
1503         ramrod_param.rx_mode_flags = rx_mode_flags;
1504
1505         ramrod_param.rx_accept_flags = rx_accept_flags;
1506         ramrod_param.tx_accept_flags = tx_accept_flags;
1507
1508         rc = ecore_config_rx_mode(sc, &ramrod_param);
1509         if (rc < 0) {
1510                 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1511                 return rc;
1512         }
1513
1514         return 0;
1515 }
1516
1517 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1518 {
1519         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1520         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1521         int rc;
1522
1523         rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1524                                    &tx_accept_flags);
1525         if (rc) {
1526                 return rc;
1527         }
1528
1529         bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1530         bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1531         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1532
1533         return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1534                                  rx_accept_flags, tx_accept_flags,
1535                                  ramrod_flags);
1536 }
1537
1538 /* returns the "mcp load_code" according to global load_count array */
1539 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1540 {
1541         int path = SC_PATH(sc);
1542         int port = SC_PORT(sc);
1543
1544         PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d]      %d, %d, %d",
1545                     path, load_count[path][0], load_count[path][1],
1546                     load_count[path][2]);
1547
1548         load_count[path][0]++;
1549         load_count[path][1 + port]++;
1550         PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d]  %d, %d, %d",
1551                     path, load_count[path][0], load_count[path][1],
1552                     load_count[path][2]);
1553         if (load_count[path][0] == 1)
1554                 return FW_MSG_CODE_DRV_LOAD_COMMON;
1555         else if (load_count[path][1 + port] == 1)
1556                 return FW_MSG_CODE_DRV_LOAD_PORT;
1557         else
1558                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1559 }
1560
1561 /* returns the "mcp load_code" according to global load_count array */
1562 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1563 {
1564         int port = SC_PORT(sc);
1565         int path = SC_PATH(sc);
1566
1567         PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d]      %d, %d, %d",
1568                     path, load_count[path][0], load_count[path][1],
1569                     load_count[path][2]);
1570         load_count[path][0]--;
1571         load_count[path][1 + port]--;
1572         PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d]  %d, %d, %d",
1573                     path, load_count[path][0], load_count[path][1],
1574                     load_count[path][2]);
1575         if (load_count[path][0] == 0) {
1576                 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1577         } else if (load_count[path][1 + port] == 0) {
1578                 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1579         } else {
1580                 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1581         }
1582 }
1583
1584 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1585 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1586 {
1587         uint32_t reset_code = 0;
1588
1589         /* Select the UNLOAD request mode */
1590         if (unload_mode == UNLOAD_NORMAL) {
1591                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1592         } else {
1593                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1594         }
1595
1596         /* Send the request to the MCP */
1597         if (!BNX2X_NOMCP(sc)) {
1598                 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1599         } else {
1600                 reset_code = bnx2x_nic_unload_no_mcp(sc);
1601         }
1602
1603         return reset_code;
1604 }
1605
1606 /* send UNLOAD_DONE command to the MCP */
1607 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1608 {
1609         uint32_t reset_param =
1610             keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1611
1612         /* Report UNLOAD_DONE to MCP */
1613         if (!BNX2X_NOMCP(sc)) {
1614                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1615         }
1616 }
1617
1618 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1619 {
1620         int tout = 50;
1621
1622         if (!sc->port.pmf) {
1623                 return 0;
1624         }
1625
1626         /*
1627          * (assumption: No Attention from MCP at this stage)
1628          * PMF probably in the middle of TX disable/enable transaction
1629          * 1. Sync IRS for default SB
1630          * 2. Sync SP queue - this guarantees us that attention handling started
1631          * 3. Wait, that TX disable/enable transaction completes
1632          *
1633          * 1+2 guarantee that if DCBX attention was scheduled it already changed
1634          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1635          * received completion for the transaction the state is TX_STOPPED.
1636          * State will return to STARTED after completion of TX_STOPPED-->STARTED
1637          * transaction.
1638          */
1639
1640         while (ecore_func_get_state(sc, &sc->func_obj) !=
1641                ECORE_F_STATE_STARTED && tout--) {
1642                 DELAY(20000);
1643         }
1644
1645         if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1646                 /*
1647                  * Failed to complete the transaction in a "good way"
1648                  * Force both transactions with CLR bit.
1649                  */
1650                 struct ecore_func_state_params func_params = { NULL };
1651
1652                 PMD_DRV_LOG(NOTICE, sc, "Unexpected function state! "
1653                             "Forcing STARTED-->TX_STOPPED-->STARTED");
1654
1655                 func_params.f_obj = &sc->func_obj;
1656                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1657
1658                 /* STARTED-->TX_STOPPED */
1659                 func_params.cmd = ECORE_F_CMD_TX_STOP;
1660                 ecore_func_state_change(sc, &func_params);
1661
1662                 /* TX_STOPPED-->STARTED */
1663                 func_params.cmd = ECORE_F_CMD_TX_START;
1664                 return ecore_func_state_change(sc, &func_params);
1665         }
1666
1667         return 0;
1668 }
1669
1670 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1671 {
1672         struct bnx2x_fastpath *fp = &sc->fp[index];
1673         struct ecore_queue_state_params q_params = { NULL };
1674         int rc;
1675
1676         PMD_DRV_LOG(DEBUG, sc, "stopping queue %d cid %d", index, fp->index);
1677
1678         q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1679         /* We want to wait for completion in this context */
1680         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1681
1682         /* Stop the primary connection: */
1683
1684         /* ...halt the connection */
1685         q_params.cmd = ECORE_Q_CMD_HALT;
1686         rc = ecore_queue_state_change(sc, &q_params);
1687         if (rc) {
1688                 return rc;
1689         }
1690
1691         /* ...terminate the connection */
1692         q_params.cmd = ECORE_Q_CMD_TERMINATE;
1693         memset(&q_params.params.terminate, 0,
1694                sizeof(q_params.params.terminate));
1695         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1696         rc = ecore_queue_state_change(sc, &q_params);
1697         if (rc) {
1698                 return rc;
1699         }
1700
1701         /* ...delete cfc entry */
1702         q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1703         memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1704         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1705         return ecore_queue_state_change(sc, &q_params);
1706 }
1707
1708 /* wait for the outstanding SP commands */
1709 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1710 {
1711         unsigned long tmp;
1712         int tout = 5000;        /* wait for 5 secs tops */
1713
1714         while (tout--) {
1715                 mb();
1716                 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1717                         return TRUE;
1718                 }
1719
1720                 DELAY(1000);
1721         }
1722
1723         mb();
1724
1725         tmp = atomic_load_acq_long(&sc->sp_state);
1726         if (tmp & mask) {
1727                 PMD_DRV_LOG(INFO, sc, "Filtering completion timed out: "
1728                             "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1729                 return FALSE;
1730         }
1731
1732         return FALSE;
1733 }
1734
1735 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1736 {
1737         struct ecore_func_state_params func_params = { NULL };
1738         int rc;
1739
1740         /* prepare parameters for function state transitions */
1741         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1742         func_params.f_obj = &sc->func_obj;
1743         func_params.cmd = ECORE_F_CMD_STOP;
1744
1745         /*
1746          * Try to stop the function the 'good way'. If it fails (in case
1747          * of a parity error during bnx2x_chip_cleanup()) and we are
1748          * not in a debug mode, perform a state transaction in order to
1749          * enable further HW_RESET transaction.
1750          */
1751         rc = ecore_func_state_change(sc, &func_params);
1752         if (rc) {
1753                 PMD_DRV_LOG(NOTICE, sc, "FUNC_STOP ramrod failed. "
1754                             "Running a dry transaction");
1755                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1756                 return ecore_func_state_change(sc, &func_params);
1757         }
1758
1759         return 0;
1760 }
1761
1762 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1763 {
1764         struct ecore_func_state_params func_params = { NULL };
1765
1766         /* Prepare parameters for function state transitions */
1767         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1768
1769         func_params.f_obj = &sc->func_obj;
1770         func_params.cmd = ECORE_F_CMD_HW_RESET;
1771
1772         func_params.params.hw_init.load_phase = load_code;
1773
1774         return ecore_func_state_change(sc, &func_params);
1775 }
1776
1777 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1778 {
1779         if (disable_hw) {
1780                 /* prevent the HW from sending interrupts */
1781                 bnx2x_int_disable(sc);
1782         }
1783 }
1784
1785 static void
1786 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1787 {
1788         int port = SC_PORT(sc);
1789         struct ecore_mcast_ramrod_params rparam = { NULL };
1790         uint32_t reset_code;
1791         int i, rc = 0;
1792
1793         bnx2x_drain_tx_queues(sc);
1794
1795         /* give HW time to discard old tx messages */
1796         DELAY(1000);
1797
1798         /* Clean all ETH MACs */
1799         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1800                               FALSE);
1801         if (rc < 0) {
1802                 PMD_DRV_LOG(NOTICE, sc,
1803                             "Failed to delete all ETH MACs (%d)", rc);
1804         }
1805
1806         /* Clean up UC list  */
1807         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1808                               TRUE);
1809         if (rc < 0) {
1810                 PMD_DRV_LOG(NOTICE, sc,
1811                             "Failed to delete UC MACs list (%d)", rc);
1812         }
1813
1814         /* Disable LLH */
1815         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1816
1817         /* Set "drop all" to stop Rx */
1818
1819         /*
1820          * We need to take the if_maddr_lock() here in order to prevent
1821          * a race between the completion code and this code.
1822          */
1823
1824         if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1825                 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1826         } else {
1827                 bnx2x_set_storm_rx_mode(sc);
1828         }
1829
1830         /* Clean up multicast configuration */
1831         rparam.mcast_obj = &sc->mcast_obj;
1832         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1833         if (rc < 0) {
1834                 PMD_DRV_LOG(NOTICE, sc,
1835                             "Failed to send DEL MCAST command (%d)", rc);
1836         }
1837
1838         /*
1839          * Send the UNLOAD_REQUEST to the MCP. This will return if
1840          * this function should perform FUNCTION, PORT, or COMMON HW
1841          * reset.
1842          */
1843         reset_code = bnx2x_send_unload_req(sc, unload_mode);
1844
1845         /*
1846          * (assumption: No Attention from MCP at this stage)
1847          * PMF probably in the middle of TX disable/enable transaction
1848          */
1849         rc = bnx2x_func_wait_started(sc);
1850         if (rc) {
1851                 PMD_DRV_LOG(NOTICE, sc, "bnx2x_func_wait_started failed");
1852         }
1853
1854         /*
1855          * Close multi and leading connections
1856          * Completions for ramrods are collected in a synchronous way
1857          */
1858         for (i = 0; i < sc->num_queues; i++) {
1859                 if (bnx2x_stop_queue(sc, i)) {
1860                         goto unload_error;
1861                 }
1862         }
1863
1864         /*
1865          * If SP settings didn't get completed so far - something
1866          * very wrong has happen.
1867          */
1868         if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1869                 PMD_DRV_LOG(NOTICE, sc, "Common slow path ramrods got stuck!");
1870         }
1871
1872 unload_error:
1873
1874         rc = bnx2x_func_stop(sc);
1875         if (rc) {
1876                 PMD_DRV_LOG(NOTICE, sc, "Function stop failed!");
1877         }
1878
1879         /* disable HW interrupts */
1880         bnx2x_int_disable_sync(sc, TRUE);
1881
1882         /* Reset the chip */
1883         rc = bnx2x_reset_hw(sc, reset_code);
1884         if (rc) {
1885                 PMD_DRV_LOG(NOTICE, sc, "Hardware reset failed");
1886         }
1887
1888         /* Report UNLOAD_DONE to MCP */
1889         bnx2x_send_unload_done(sc, keep_link);
1890 }
1891
1892 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1893 {
1894         uint32_t val;
1895
1896         PMD_DRV_LOG(DEBUG, sc, "Disabling 'close the gates'");
1897
1898         val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1899         val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1900                  MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1901         REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1902 }
1903
1904 /*
1905  * Cleans the object that have internal lists without sending
1906  * ramrods. Should be run when interrutps are disabled.
1907  */
1908 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1909 {
1910         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1911         struct ecore_mcast_ramrod_params rparam = { NULL };
1912         struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1913         int rc;
1914
1915         /* Cleanup MACs' object first... */
1916
1917         /* Wait for completion of requested */
1918         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1919         /* Perform a dry cleanup */
1920         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1921
1922         /* Clean ETH primary MAC */
1923         bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1924         rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1925                                  &ramrod_flags);
1926         if (rc != 0) {
1927                 PMD_DRV_LOG(NOTICE, sc, "Failed to clean ETH MACs (%d)", rc);
1928         }
1929
1930         /* Cleanup UC list */
1931         vlan_mac_flags = 0;
1932         bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1933         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1934         if (rc != 0) {
1935                 PMD_DRV_LOG(NOTICE, sc,
1936                             "Failed to clean UC list MACs (%d)", rc);
1937         }
1938
1939         /* Now clean mcast object... */
1940
1941         rparam.mcast_obj = &sc->mcast_obj;
1942         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1943
1944         /* Add a DEL command... */
1945         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1946         if (rc < 0) {
1947                 PMD_DRV_LOG(NOTICE, sc,
1948                             "Failed to send DEL MCAST command (%d)", rc);
1949         }
1950
1951         /* now wait until all pending commands are cleared */
1952
1953         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1954         while (rc != 0) {
1955                 if (rc < 0) {
1956                         PMD_DRV_LOG(NOTICE, sc,
1957                                     "Failed to clean MCAST object (%d)", rc);
1958                         return;
1959                 }
1960
1961                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1962         }
1963 }
1964
1965 /* stop the controller */
1966 __rte_noinline
1967 int
1968 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1969 {
1970         uint8_t global = FALSE;
1971         uint32_t val;
1972
1973         PMD_DRV_LOG(DEBUG, sc, "Starting NIC unload...");
1974
1975         /* mark driver as unloaded in shmem2 */
1976         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
1977                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
1978                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
1979                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
1980         }
1981
1982         if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
1983             (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
1984                 /*
1985                  * We can get here if the driver has been unloaded
1986                  * during parity error recovery and is either waiting for a
1987                  * leader to complete or for other functions to unload and
1988                  * then ifconfig down has been issued. In this case we want to
1989                  * unload and let other functions to complete a recovery
1990                  * process.
1991                  */
1992                 sc->recovery_state = BNX2X_RECOVERY_DONE;
1993                 sc->is_leader = 0;
1994                 bnx2x_release_leader_lock(sc);
1995                 mb();
1996
1997                 PMD_DRV_LOG(NOTICE, sc, "Can't unload in closed or error state");
1998                 return -1;
1999         }
2000
2001         /*
2002          * Nothing to do during unload if previous bnx2x_nic_load()
2003          * did not completed successfully - all resourses are released.
2004          */
2005         if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2006                 return 0;
2007         }
2008
2009         sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2010         mb();
2011
2012         sc->rx_mode = BNX2X_RX_MODE_NONE;
2013         bnx2x_set_rx_mode(sc);
2014         mb();
2015
2016         if (IS_PF(sc)) {
2017                 /* set ALWAYS_ALIVE bit in shmem */
2018                 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2019
2020                 bnx2x_drv_pulse(sc);
2021
2022                 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2023                 bnx2x_save_statistics(sc);
2024         }
2025
2026         /* wait till consumers catch up with producers in all queues */
2027         bnx2x_drain_tx_queues(sc);
2028
2029         /* if VF indicate to PF this function is going down (PF will delete sp
2030          * elements and clear initializations
2031          */
2032         if (IS_VF(sc)) {
2033                 bnx2x_vf_unload(sc);
2034         } else if (unload_mode != UNLOAD_RECOVERY) {
2035                 /* if this is a normal/close unload need to clean up chip */
2036                 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2037         } else {
2038                 /* Send the UNLOAD_REQUEST to the MCP */
2039                 bnx2x_send_unload_req(sc, unload_mode);
2040
2041                 /*
2042                  * Prevent transactions to host from the functions on the
2043                  * engine that doesn't reset global blocks in case of global
2044                  * attention once gloabl blocks are reset and gates are opened
2045                  * (the engine which leader will perform the recovery
2046                  * last).
2047                  */
2048                 if (!CHIP_IS_E1x(sc)) {
2049                         bnx2x_pf_disable(sc);
2050                 }
2051
2052                 /* disable HW interrupts */
2053                 bnx2x_int_disable_sync(sc, TRUE);
2054
2055                 /* Report UNLOAD_DONE to MCP */
2056                 bnx2x_send_unload_done(sc, FALSE);
2057         }
2058
2059         /*
2060          * At this stage no more interrupts will arrive so we may safely clean
2061          * the queue'able objects here in case they failed to get cleaned so far.
2062          */
2063         if (IS_PF(sc)) {
2064                 bnx2x_squeeze_objects(sc);
2065         }
2066
2067         /* There should be no more pending SP commands at this stage */
2068         sc->sp_state = 0;
2069
2070         sc->port.pmf = 0;
2071
2072         if (IS_PF(sc)) {
2073                 bnx2x_free_mem(sc);
2074         }
2075
2076         bnx2x_free_fw_stats_mem(sc);
2077
2078         sc->state = BNX2X_STATE_CLOSED;
2079
2080         /*
2081          * Check if there are pending parity attentions. If there are - set
2082          * RECOVERY_IN_PROGRESS.
2083          */
2084         if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2085                 bnx2x_set_reset_in_progress(sc);
2086
2087                 /* Set RESET_IS_GLOBAL if needed */
2088                 if (global) {
2089                         bnx2x_set_reset_global(sc);
2090                 }
2091         }
2092
2093         /*
2094          * The last driver must disable a "close the gate" if there is no
2095          * parity attention or "process kill" pending.
2096          */
2097         if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2098             bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2099                 bnx2x_disable_close_the_gate(sc);
2100         }
2101
2102         PMD_DRV_LOG(DEBUG, sc, "Ended NIC unload");
2103
2104         return 0;
2105 }
2106
2107 /*
2108  * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2109  * visible to the controller.
2110  *
2111  * If an mbuf is submitted to this routine and cannot be given to the
2112  * controller (e.g. it has too many fragments) then the function may free
2113  * the mbuf and return to the caller.
2114  *
2115  * Returns:
2116  *     int: Number of TX BDs used for the mbuf
2117  *
2118  *   Note the side effect that an mbuf may be freed if it causes a problem.
2119  */
2120 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2121 {
2122         struct eth_tx_start_bd *tx_start_bd;
2123         uint16_t bd_prod, pkt_prod;
2124         struct bnx2x_softc *sc;
2125         uint32_t nbds = 0;
2126
2127         sc = txq->sc;
2128         bd_prod = txq->tx_bd_tail;
2129         pkt_prod = txq->tx_pkt_tail;
2130
2131         txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2132
2133         tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2134
2135         tx_start_bd->addr =
2136             rte_cpu_to_le_64(rte_mbuf_data_iova(m0));
2137         tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2138         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2139         tx_start_bd->general_data =
2140             (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2141
2142         tx_start_bd->nbd = rte_cpu_to_le_16(2);
2143
2144         if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2145                 tx_start_bd->vlan_or_ethertype =
2146                     rte_cpu_to_le_16(m0->vlan_tci);
2147                 tx_start_bd->bd_flags.as_bitfield |=
2148                     (X_ETH_OUTBAND_VLAN <<
2149                      ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2150         } else {
2151                 if (IS_PF(sc))
2152                         tx_start_bd->vlan_or_ethertype =
2153                             rte_cpu_to_le_16(pkt_prod);
2154                 else {
2155                         struct ether_hdr *eh =
2156                             rte_pktmbuf_mtod(m0, struct ether_hdr *);
2157
2158                         tx_start_bd->vlan_or_ethertype =
2159                             rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2160                 }
2161         }
2162
2163         bd_prod = NEXT_TX_BD(bd_prod);
2164         if (IS_VF(sc)) {
2165                 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2166                 const struct ether_hdr *eh =
2167                     rte_pktmbuf_mtod(m0, struct ether_hdr *);
2168                 uint8_t mac_type = UNICAST_ADDRESS;
2169
2170                 tx_parse_bd =
2171                     &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2172                 if (is_multicast_ether_addr(&eh->d_addr)) {
2173                         if (is_broadcast_ether_addr(&eh->d_addr))
2174                                 mac_type = BROADCAST_ADDRESS;
2175                         else
2176                                 mac_type = MULTICAST_ADDRESS;
2177                 }
2178                 tx_parse_bd->parsing_data =
2179                     (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2180
2181                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2182                            &eh->d_addr.addr_bytes[0], 2);
2183                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2184                            &eh->d_addr.addr_bytes[2], 2);
2185                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2186                            &eh->d_addr.addr_bytes[4], 2);
2187                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2188                            &eh->s_addr.addr_bytes[0], 2);
2189                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2190                            &eh->s_addr.addr_bytes[2], 2);
2191                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2192                            &eh->s_addr.addr_bytes[4], 2);
2193
2194                 tx_parse_bd->data.mac_addr.dst_hi =
2195                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2196                 tx_parse_bd->data.mac_addr.dst_mid =
2197                     rte_cpu_to_be_16(tx_parse_bd->data.
2198                                      mac_addr.dst_mid);
2199                 tx_parse_bd->data.mac_addr.dst_lo =
2200                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2201                 tx_parse_bd->data.mac_addr.src_hi =
2202                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2203                 tx_parse_bd->data.mac_addr.src_mid =
2204                     rte_cpu_to_be_16(tx_parse_bd->data.
2205                                      mac_addr.src_mid);
2206                 tx_parse_bd->data.mac_addr.src_lo =
2207                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2208
2209                 PMD_TX_LOG(DEBUG,
2210                            "PBD dst %x %x %x src %x %x %x p_data %x",
2211                            tx_parse_bd->data.mac_addr.dst_hi,
2212                            tx_parse_bd->data.mac_addr.dst_mid,
2213                            tx_parse_bd->data.mac_addr.dst_lo,
2214                            tx_parse_bd->data.mac_addr.src_hi,
2215                            tx_parse_bd->data.mac_addr.src_mid,
2216                            tx_parse_bd->data.mac_addr.src_lo,
2217                            tx_parse_bd->parsing_data);
2218         }
2219
2220         PMD_TX_LOG(DEBUG,
2221                    "start bd: nbytes %d flags %x vlan %x",
2222                    tx_start_bd->nbytes,
2223                    tx_start_bd->bd_flags.as_bitfield,
2224                    tx_start_bd->vlan_or_ethertype);
2225
2226         bd_prod = NEXT_TX_BD(bd_prod);
2227         pkt_prod++;
2228
2229         if (TX_IDX(bd_prod) < 2)
2230                 nbds++;
2231
2232         txq->nb_tx_avail -= 2;
2233         txq->tx_bd_tail = bd_prod;
2234         txq->tx_pkt_tail = pkt_prod;
2235
2236         return nbds + 2;
2237 }
2238
2239 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2240 {
2241         return L2_ILT_LINES(sc);
2242 }
2243
2244 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2245 {
2246         struct ilt_client_info *ilt_client;
2247         struct ecore_ilt *ilt = sc->ilt;
2248         uint16_t line = 0;
2249
2250         PMD_INIT_FUNC_TRACE(sc);
2251
2252         ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2253
2254         /* CDU */
2255         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2256         ilt_client->client_num = ILT_CLIENT_CDU;
2257         ilt_client->page_size = CDU_ILT_PAGE_SZ;
2258         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2259         ilt_client->start = line;
2260         line += bnx2x_cid_ilt_lines(sc);
2261
2262         if (CNIC_SUPPORT(sc)) {
2263                 line += CNIC_ILT_LINES;
2264         }
2265
2266         ilt_client->end = (line - 1);
2267
2268         /* QM */
2269         if (QM_INIT(sc->qm_cid_count)) {
2270                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2271                 ilt_client->client_num = ILT_CLIENT_QM;
2272                 ilt_client->page_size = QM_ILT_PAGE_SZ;
2273                 ilt_client->flags = 0;
2274                 ilt_client->start = line;
2275
2276                 /* 4 bytes for each cid */
2277                 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2278                                      QM_ILT_PAGE_SZ);
2279
2280                 ilt_client->end = (line - 1);
2281         }
2282
2283         if (CNIC_SUPPORT(sc)) {
2284                 /* SRC */
2285                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2286                 ilt_client->client_num = ILT_CLIENT_SRC;
2287                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2288                 ilt_client->flags = 0;
2289                 ilt_client->start = line;
2290                 line += SRC_ILT_LINES;
2291                 ilt_client->end = (line - 1);
2292
2293                 /* TM */
2294                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2295                 ilt_client->client_num = ILT_CLIENT_TM;
2296                 ilt_client->page_size = TM_ILT_PAGE_SZ;
2297                 ilt_client->flags = 0;
2298                 ilt_client->start = line;
2299                 line += TM_ILT_LINES;
2300                 ilt_client->end = (line - 1);
2301         }
2302
2303         assert((line <= ILT_MAX_LINES));
2304 }
2305
2306 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2307 {
2308         int i;
2309
2310         for (i = 0; i < sc->num_queues; i++) {
2311                 /* get the Rx buffer size for RX frames */
2312                 sc->fp[i].rx_buf_size =
2313                     (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2314         }
2315 }
2316
2317 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2318 {
2319
2320         sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2321
2322         return sc->ilt == NULL;
2323 }
2324
2325 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2326 {
2327         sc->ilt->lines = rte_calloc("",
2328                                     sizeof(struct ilt_line), ILT_MAX_LINES,
2329                                     RTE_CACHE_LINE_SIZE);
2330         return sc->ilt->lines == NULL;
2331 }
2332
2333 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2334 {
2335         rte_free(sc->ilt);
2336         sc->ilt = NULL;
2337 }
2338
2339 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2340 {
2341         if (sc->ilt->lines != NULL) {
2342                 rte_free(sc->ilt->lines);
2343                 sc->ilt->lines = NULL;
2344         }
2345 }
2346
2347 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2348 {
2349         uint32_t i;
2350
2351         for (i = 0; i < L2_ILT_LINES(sc); i++) {
2352                 sc->context[i].vcxt = NULL;
2353                 sc->context[i].size = 0;
2354         }
2355
2356         ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2357
2358         bnx2x_free_ilt_lines_mem(sc);
2359 }
2360
2361 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2362 {
2363         int context_size;
2364         int allocated;
2365         int i;
2366         char cdu_name[RTE_MEMZONE_NAMESIZE];
2367
2368         /*
2369          * Allocate memory for CDU context:
2370          * This memory is allocated separately and not in the generic ILT
2371          * functions because CDU differs in few aspects:
2372          * 1. There can be multiple entities allocating memory for context -
2373          * regular L2, CNIC, and SRIOV drivers. Each separately controls
2374          * its own ILT lines.
2375          * 2. Since CDU page-size is not a single 4KB page (which is the case
2376          * for the other ILT clients), to be efficient we want to support
2377          * allocation of sub-page-size in the last entry.
2378          * 3. Context pointers are used by the driver to pass to FW / update
2379          * the context (for the other ILT clients the pointers are used just to
2380          * free the memory during unload).
2381          */
2382         context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2383         for (i = 0, allocated = 0; allocated < context_size; i++) {
2384                 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2385                                           (context_size - allocated));
2386
2387                 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2388                 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2389                                   &sc->context[i].vcxt_dma,
2390                                   cdu_name, BNX2X_PAGE_SIZE) != 0) {
2391                         bnx2x_free_mem(sc);
2392                         return -1;
2393                 }
2394
2395                 sc->context[i].vcxt =
2396                     (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2397
2398                 allocated += sc->context[i].size;
2399         }
2400
2401         bnx2x_alloc_ilt_lines_mem(sc);
2402
2403         if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2404                 PMD_DRV_LOG(NOTICE, sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2405                 bnx2x_free_mem(sc);
2406                 return -1;
2407         }
2408
2409         return 0;
2410 }
2411
2412 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2413 {
2414         sc->fw_stats_num = 0;
2415
2416         sc->fw_stats_req_size = 0;
2417         sc->fw_stats_req = NULL;
2418         sc->fw_stats_req_mapping = 0;
2419
2420         sc->fw_stats_data_size = 0;
2421         sc->fw_stats_data = NULL;
2422         sc->fw_stats_data_mapping = 0;
2423 }
2424
2425 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2426 {
2427         uint8_t num_queue_stats;
2428         int num_groups, vf_headroom = 0;
2429
2430         /* number of queues for statistics is number of eth queues */
2431         num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2432
2433         /*
2434          * Total number of FW statistics requests =
2435          *   1 for port stats + 1 for PF stats + num of queues
2436          */
2437         sc->fw_stats_num = (2 + num_queue_stats);
2438
2439         /*
2440          * Request is built from stats_query_header and an array of
2441          * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2442          * rules. The real number or requests is configured in the
2443          * stats_query_header.
2444          */
2445         num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2446         if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2447                 num_groups++;
2448
2449         sc->fw_stats_req_size =
2450             (sizeof(struct stats_query_header) +
2451              (num_groups * sizeof(struct stats_query_cmd_group)));
2452
2453         /*
2454          * Data for statistics requests + stats_counter.
2455          * stats_counter holds per-STORM counters that are incremented when
2456          * STORM has finished with the current request. Memory for FCoE
2457          * offloaded statistics are counted anyway, even if they will not be sent.
2458          * VF stats are not accounted for here as the data of VF stats is stored
2459          * in memory allocated by the VF, not here.
2460          */
2461         sc->fw_stats_data_size =
2462             (sizeof(struct stats_counter) +
2463              sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2464              /* sizeof(struct fcoe_statistics_params) + */
2465              (sizeof(struct per_queue_stats) * num_queue_stats));
2466
2467         if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2468                           &sc->fw_stats_dma, "fw_stats",
2469                           RTE_CACHE_LINE_SIZE) != 0) {
2470                 bnx2x_free_fw_stats_mem(sc);
2471                 return -1;
2472         }
2473
2474         /* set up the shortcuts */
2475
2476         sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2477         sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2478
2479         sc->fw_stats_data =
2480             (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2481                                          sc->fw_stats_req_size);
2482         sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2483                                      sc->fw_stats_req_size);
2484
2485         return 0;
2486 }
2487
2488 /*
2489  * Bits map:
2490  * 0-7  - Engine0 load counter.
2491  * 8-15 - Engine1 load counter.
2492  * 16   - Engine0 RESET_IN_PROGRESS bit.
2493  * 17   - Engine1 RESET_IN_PROGRESS bit.
2494  * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
2495  *        function on the engine
2496  * 19   - Engine1 ONE_IS_LOADED.
2497  * 20   - Chip reset flow bit. When set none-leader must wait for both engines
2498  *        leader to complete (check for both RESET_IN_PROGRESS bits and not
2499  *        for just the one belonging to its engine).
2500  */
2501 #define BNX2X_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
2502 #define BNX2X_PATH0_LOAD_CNT_MASK   0x000000ff
2503 #define BNX2X_PATH0_LOAD_CNT_SHIFT  0
2504 #define BNX2X_PATH1_LOAD_CNT_MASK   0x0000ff00
2505 #define BNX2X_PATH1_LOAD_CNT_SHIFT  8
2506 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2507 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2508 #define BNX2X_GLOBAL_RESET_BIT      0x00040000
2509
2510 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2511 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2512 {
2513         uint32_t val;
2514         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2515         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2516         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2517         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2518 }
2519
2520 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2521 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2522 {
2523         uint32_t val;
2524         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2525         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2526         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2527         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2528 }
2529
2530 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2531 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2532 {
2533         return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2534 }
2535
2536 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2537 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2538 {
2539         uint32_t val;
2540         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2541             BNX2X_PATH0_RST_IN_PROG_BIT;
2542
2543         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2544
2545         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2546         /* Clear the bit */
2547         val &= ~bit;
2548         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2549
2550         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2551 }
2552
2553 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2554 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2555 {
2556         uint32_t val;
2557         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2558             BNX2X_PATH0_RST_IN_PROG_BIT;
2559
2560         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2561
2562         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2563         /* Set the bit */
2564         val |= bit;
2565         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2566
2567         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2568 }
2569
2570 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2571 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2572 {
2573         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2574         uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2575             BNX2X_PATH0_RST_IN_PROG_BIT;
2576
2577         /* return false if bit is set */
2578         return (val & bit) ? FALSE : TRUE;
2579 }
2580
2581 /* get the load status for an engine, should be run under rtnl lock */
2582 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2583 {
2584         uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2585             BNX2X_PATH0_LOAD_CNT_MASK;
2586         uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2587             BNX2X_PATH0_LOAD_CNT_SHIFT;
2588         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2589
2590         val = ((val & mask) >> shift);
2591
2592         return val != 0;
2593 }
2594
2595 /* set pf load mark */
2596 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2597 {
2598         uint32_t val;
2599         uint32_t val1;
2600         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2601             BNX2X_PATH0_LOAD_CNT_MASK;
2602         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2603             BNX2X_PATH0_LOAD_CNT_SHIFT;
2604
2605         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2606
2607         PMD_INIT_FUNC_TRACE(sc);
2608
2609         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2610
2611         /* get the current counter value */
2612         val1 = ((val & mask) >> shift);
2613
2614         /* set bit of this PF */
2615         val1 |= (1 << SC_ABS_FUNC(sc));
2616
2617         /* clear the old value */
2618         val &= ~mask;
2619
2620         /* set the new one */
2621         val |= ((val1 << shift) & mask);
2622
2623         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2624
2625         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2626 }
2627
2628 /* clear pf load mark */
2629 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2630 {
2631         uint32_t val1, val;
2632         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2633             BNX2X_PATH0_LOAD_CNT_MASK;
2634         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2635             BNX2X_PATH0_LOAD_CNT_SHIFT;
2636
2637         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2638         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2639
2640         /* get the current counter value */
2641         val1 = (val & mask) >> shift;
2642
2643         /* clear bit of that PF */
2644         val1 &= ~(1 << SC_ABS_FUNC(sc));
2645
2646         /* clear the old value */
2647         val &= ~mask;
2648
2649         /* set the new one */
2650         val |= ((val1 << shift) & mask);
2651
2652         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2653         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2654         return val1 != 0;
2655 }
2656
2657 /* send load requrest to mcp and analyze response */
2658 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2659 {
2660         PMD_INIT_FUNC_TRACE(sc);
2661
2662         /* init fw_seq */
2663         sc->fw_seq =
2664             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2665              DRV_MSG_SEQ_NUMBER_MASK);
2666
2667         PMD_DRV_LOG(DEBUG, sc, "initial fw_seq 0x%04x", sc->fw_seq);
2668
2669 #ifdef BNX2X_PULSE
2670         /* get the current FW pulse sequence */
2671         sc->fw_drv_pulse_wr_seq =
2672             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2673              DRV_PULSE_SEQ_MASK);
2674 #else
2675         /* set ALWAYS_ALIVE bit in shmem */
2676         sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2677         bnx2x_drv_pulse(sc);
2678 #endif
2679
2680         /* load request */
2681         (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2682                                       DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2683
2684         /* if the MCP fails to respond we must abort */
2685         if (!(*load_code)) {
2686                 PMD_DRV_LOG(NOTICE, sc, "MCP response failure!");
2687                 return -1;
2688         }
2689
2690         /* if MCP refused then must abort */
2691         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2692                 PMD_DRV_LOG(NOTICE, sc, "MCP refused load request");
2693                 return -1;
2694         }
2695
2696         return 0;
2697 }
2698
2699 /*
2700  * Check whether another PF has already loaded FW to chip. In virtualized
2701  * environments a pf from anoth VM may have already initialized the device
2702  * including loading FW.
2703  */
2704 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2705 {
2706         uint32_t my_fw, loaded_fw;
2707
2708         /* is another pf loaded on this engine? */
2709         if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2710             (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2711                 /* build my FW version dword */
2712                 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2713                          (BNX2X_5710_FW_MINOR_VERSION << 8) +
2714                          (BNX2X_5710_FW_REVISION_VERSION << 16) +
2715                          (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2716
2717                 /* read loaded FW from chip */
2718                 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2719                 PMD_DRV_LOG(DEBUG, sc, "loaded FW 0x%08x / my FW 0x%08x",
2720                             loaded_fw, my_fw);
2721
2722                 /* abort nic load if version mismatch */
2723                 if (my_fw != loaded_fw) {
2724                         PMD_DRV_LOG(NOTICE, sc,
2725                                     "FW 0x%08x already loaded (mine is 0x%08x)",
2726                                     loaded_fw, my_fw);
2727                         return -1;
2728                 }
2729         }
2730
2731         return 0;
2732 }
2733
2734 /* mark PMF if applicable */
2735 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2736 {
2737         uint32_t ncsi_oem_data_addr;
2738
2739         PMD_INIT_FUNC_TRACE(sc);
2740
2741         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2742             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2743             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2744                 /*
2745                  * Barrier here for ordering between the writing to sc->port.pmf here
2746                  * and reading it from the periodic task.
2747                  */
2748                 sc->port.pmf = 1;
2749                 mb();
2750         } else {
2751                 sc->port.pmf = 0;
2752         }
2753
2754         PMD_DRV_LOG(DEBUG, sc, "pmf %d", sc->port.pmf);
2755
2756         if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2757                 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2758                         ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2759                         if (ncsi_oem_data_addr) {
2760                                 REG_WR(sc,
2761                                        (ncsi_oem_data_addr +
2762                                         offsetof(struct glob_ncsi_oem_data,
2763                                                  driver_version)), 0);
2764                         }
2765                 }
2766         }
2767 }
2768
2769 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2770 {
2771         int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2772         int abs_func;
2773         int vn;
2774
2775         if (BNX2X_NOMCP(sc)) {
2776                 return;         /* what should be the default bvalue in this case */
2777         }
2778
2779         /*
2780          * The formula for computing the absolute function number is...
2781          * For 2 port configuration (4 functions per port):
2782          *   abs_func = 2 * vn + SC_PORT + SC_PATH
2783          * For 4 port configuration (2 functions per port):
2784          *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2785          */
2786         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2787                 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2788                 if (abs_func >= E1H_FUNC_MAX) {
2789                         break;
2790                 }
2791                 sc->devinfo.mf_info.mf_config[vn] =
2792                     MFCFG_RD(sc, func_mf_config[abs_func].config);
2793         }
2794
2795         if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2796             FUNC_MF_CFG_FUNC_DISABLED) {
2797                 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
2798                 sc->flags |= BNX2X_MF_FUNC_DIS;
2799         } else {
2800                 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
2801                 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2802         }
2803 }
2804
2805 /* acquire split MCP access lock register */
2806 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2807 {
2808         uint32_t j, val;
2809
2810         for (j = 0; j < 1000; j++) {
2811                 val = (1UL << 31);
2812                 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2813                 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2814                 if (val & (1L << 31))
2815                         break;
2816
2817                 DELAY(5000);
2818         }
2819
2820         if (!(val & (1L << 31))) {
2821                 PMD_DRV_LOG(NOTICE, sc, "Cannot acquire MCP access lock register");
2822                 return -1;
2823         }
2824
2825         return 0;
2826 }
2827
2828 /* release split MCP access lock register */
2829 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2830 {
2831         REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2832 }
2833
2834 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2835 {
2836         int port = SC_PORT(sc);
2837         uint32_t ext_phy_config;
2838
2839         /* mark the failure */
2840         ext_phy_config =
2841             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2842
2843         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2844         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2845         SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2846                  ext_phy_config);
2847
2848         /* log the failure */
2849         PMD_DRV_LOG(INFO, sc,
2850                     "Fan Failure has caused the driver to shutdown "
2851                     "the card to prevent permanent damage. "
2852                     "Please contact OEM Support for assistance");
2853
2854         rte_panic("Schedule task to handle fan failure");
2855 }
2856
2857 /* this function is called upon a link interrupt */
2858 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2859 {
2860         uint32_t pause_enabled = 0;
2861         struct host_port_stats *pstats;
2862         int cmng_fns;
2863
2864         /* Make sure that we are synced with the current statistics */
2865         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2866
2867         elink_link_update(&sc->link_params, &sc->link_vars);
2868
2869         if (sc->link_vars.link_up) {
2870
2871                 /* dropless flow control */
2872                 if (sc->dropless_fc) {
2873                         pause_enabled = 0;
2874
2875                         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2876                                 pause_enabled = 1;
2877                         }
2878
2879                         REG_WR(sc,
2880                                (BAR_USTRORM_INTMEM +
2881                                 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2882                                pause_enabled);
2883                 }
2884
2885                 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2886                         pstats = BNX2X_SP(sc, port_stats);
2887                         /* reset old mac stats */
2888                         memset(&(pstats->mac_stx[0]), 0,
2889                                sizeof(struct mac_stx));
2890                 }
2891
2892                 if (sc->state == BNX2X_STATE_OPEN) {
2893                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2894                 }
2895         }
2896
2897         if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2898                 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2899
2900                 if (cmng_fns != CMNG_FNS_NONE) {
2901                         bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2902                         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2903                 }
2904         }
2905
2906         bnx2x_link_report(sc);
2907
2908         if (IS_MF(sc)) {
2909                 bnx2x_link_sync_notify(sc);
2910         }
2911 }
2912
2913 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2914 {
2915         int port = SC_PORT(sc);
2916         uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2917             MISC_REG_AEU_MASK_ATTN_FUNC_0;
2918         uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2919             NIG_REG_MASK_INTERRUPT_PORT0;
2920         uint32_t aeu_mask;
2921         uint32_t nig_mask = 0;
2922         uint32_t reg_addr;
2923         uint32_t igu_acked;
2924         uint32_t cnt;
2925
2926         if (sc->attn_state & asserted) {
2927                 PMD_DRV_LOG(ERR, sc, "IGU ERROR attn=0x%08x", asserted);
2928         }
2929
2930         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2931
2932         aeu_mask = REG_RD(sc, aeu_addr);
2933
2934         aeu_mask &= ~(asserted & 0x3ff);
2935
2936         REG_WR(sc, aeu_addr, aeu_mask);
2937
2938         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2939
2940         sc->attn_state |= asserted;
2941
2942         if (asserted & ATTN_HARD_WIRED_MASK) {
2943                 if (asserted & ATTN_NIG_FOR_FUNC) {
2944
2945                         /* save nig interrupt mask */
2946                         nig_mask = REG_RD(sc, nig_int_mask_addr);
2947
2948                         /* If nig_mask is not set, no need to call the update function */
2949                         if (nig_mask) {
2950                                 REG_WR(sc, nig_int_mask_addr, 0);
2951
2952                                 bnx2x_link_attn(sc);
2953                         }
2954
2955                         /* handle unicore attn? */
2956                 }
2957
2958                 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2959                         PMD_DRV_LOG(DEBUG, sc, "ATTN_SW_TIMER_4_FUNC!");
2960                 }
2961
2962                 if (asserted & GPIO_2_FUNC) {
2963                         PMD_DRV_LOG(DEBUG, sc, "GPIO_2_FUNC!");
2964                 }
2965
2966                 if (asserted & GPIO_3_FUNC) {
2967                         PMD_DRV_LOG(DEBUG, sc, "GPIO_3_FUNC!");
2968                 }
2969
2970                 if (asserted & GPIO_4_FUNC) {
2971                         PMD_DRV_LOG(DEBUG, sc, "GPIO_4_FUNC!");
2972                 }
2973
2974                 if (port == 0) {
2975                         if (asserted & ATTN_GENERAL_ATTN_1) {
2976                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_1!");
2977                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2978                         }
2979                         if (asserted & ATTN_GENERAL_ATTN_2) {
2980                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_2!");
2981                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2982                         }
2983                         if (asserted & ATTN_GENERAL_ATTN_3) {
2984                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_3!");
2985                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2986                         }
2987                 } else {
2988                         if (asserted & ATTN_GENERAL_ATTN_4) {
2989                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_4!");
2990                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2991                         }
2992                         if (asserted & ATTN_GENERAL_ATTN_5) {
2993                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_5!");
2994                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2995                         }
2996                         if (asserted & ATTN_GENERAL_ATTN_6) {
2997                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_6!");
2998                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2999                         }
3000                 }
3001         }
3002         /* hardwired */
3003         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3004                 reg_addr =
3005                     (HC_REG_COMMAND_REG + port * 32 +
3006                      COMMAND_REG_ATTN_BITS_SET);
3007         } else {
3008                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3009         }
3010
3011         PMD_DRV_LOG(DEBUG, sc, "about to mask 0x%08x at %s addr 0x%08x",
3012                     asserted,
3013                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3014                     reg_addr);
3015         REG_WR(sc, reg_addr, asserted);
3016
3017         /* now set back the mask */
3018         if (asserted & ATTN_NIG_FOR_FUNC) {
3019                 /*
3020                  * Verify that IGU ack through BAR was written before restoring
3021                  * NIG mask. This loop should exit after 2-3 iterations max.
3022                  */
3023                 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3024                         cnt = 0;
3025
3026                         do {
3027                                 igu_acked =
3028                                     REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3029                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3030                                  && (++cnt < MAX_IGU_ATTN_ACK_TO));
3031
3032                         if (!igu_acked) {
3033                                 PMD_DRV_LOG(ERR, sc,
3034                                             "Failed to verify IGU ack on time");
3035                         }
3036
3037                         mb();
3038                 }
3039
3040                 REG_WR(sc, nig_int_mask_addr, nig_mask);
3041
3042         }
3043 }
3044
3045 static void
3046 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3047                      __rte_unused const char *blk)
3048 {
3049         PMD_DRV_LOG(INFO, sc, "%s%s", idx ? ", " : "", blk);
3050 }
3051
3052 static int
3053 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3054                               uint8_t print)
3055 {
3056         uint32_t cur_bit = 0;
3057         int i = 0;
3058
3059         for (i = 0; sig; i++) {
3060                 cur_bit = ((uint32_t) 0x1 << i);
3061                 if (sig & cur_bit) {
3062                         switch (cur_bit) {
3063                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3064                                 if (print)
3065                                         bnx2x_print_next_block(sc, par_num++,
3066                                                              "BRB");
3067                                 break;
3068                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3069                                 if (print)
3070                                         bnx2x_print_next_block(sc, par_num++,
3071                                                              "PARSER");
3072                                 break;
3073                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3074                                 if (print)
3075                                         bnx2x_print_next_block(sc, par_num++,
3076                                                              "TSDM");
3077                                 break;
3078                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3079                                 if (print)
3080                                         bnx2x_print_next_block(sc, par_num++,
3081                                                              "SEARCHER");
3082                                 break;
3083                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3084                                 if (print)
3085                                         bnx2x_print_next_block(sc, par_num++,
3086                                                              "TCM");
3087                                 break;
3088                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3089                                 if (print)
3090                                         bnx2x_print_next_block(sc, par_num++,
3091                                                              "TSEMI");
3092                                 break;
3093                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3094                                 if (print)
3095                                         bnx2x_print_next_block(sc, par_num++,
3096                                                              "XPB");
3097                                 break;
3098                         }
3099
3100                         /* Clear the bit */
3101                         sig &= ~cur_bit;
3102                 }
3103         }
3104
3105         return par_num;
3106 }
3107
3108 static int
3109 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3110                               uint8_t * global, uint8_t print)
3111 {
3112         int i = 0;
3113         uint32_t cur_bit = 0;
3114         for (i = 0; sig; i++) {
3115                 cur_bit = ((uint32_t) 0x1 << i);
3116                 if (sig & cur_bit) {
3117                         switch (cur_bit) {
3118                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3119                                 if (print)
3120                                         bnx2x_print_next_block(sc, par_num++,
3121                                                              "PBF");
3122                                 break;
3123                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3124                                 if (print)
3125                                         bnx2x_print_next_block(sc, par_num++,
3126                                                              "QM");
3127                                 break;
3128                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3129                                 if (print)
3130                                         bnx2x_print_next_block(sc, par_num++,
3131                                                              "TM");
3132                                 break;
3133                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3134                                 if (print)
3135                                         bnx2x_print_next_block(sc, par_num++,
3136                                                              "XSDM");
3137                                 break;
3138                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3139                                 if (print)
3140                                         bnx2x_print_next_block(sc, par_num++,
3141                                                              "XCM");
3142                                 break;
3143                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3144                                 if (print)
3145                                         bnx2x_print_next_block(sc, par_num++,
3146                                                              "XSEMI");
3147                                 break;
3148                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3149                                 if (print)
3150                                         bnx2x_print_next_block(sc, par_num++,
3151                                                              "DOORBELLQ");
3152                                 break;
3153                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3154                                 if (print)
3155                                         bnx2x_print_next_block(sc, par_num++,
3156                                                              "NIG");
3157                                 break;
3158                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3159                                 if (print)
3160                                         bnx2x_print_next_block(sc, par_num++,
3161                                                              "VAUX PCI CORE");
3162                                 *global = TRUE;
3163                                 break;
3164                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3165                                 if (print)
3166                                         bnx2x_print_next_block(sc, par_num++,
3167                                                              "DEBUG");
3168                                 break;
3169                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3170                                 if (print)
3171                                         bnx2x_print_next_block(sc, par_num++,
3172                                                              "USDM");
3173                                 break;
3174                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3175                                 if (print)
3176                                         bnx2x_print_next_block(sc, par_num++,
3177                                                              "UCM");
3178                                 break;
3179                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3180                                 if (print)
3181                                         bnx2x_print_next_block(sc, par_num++,
3182                                                              "USEMI");
3183                                 break;
3184                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3185                                 if (print)
3186                                         bnx2x_print_next_block(sc, par_num++,
3187                                                              "UPB");
3188                                 break;
3189                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3190                                 if (print)
3191                                         bnx2x_print_next_block(sc, par_num++,
3192                                                              "CSDM");
3193                                 break;
3194                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3195                                 if (print)
3196                                         bnx2x_print_next_block(sc, par_num++,
3197                                                              "CCM");
3198                                 break;
3199                         }
3200
3201                         /* Clear the bit */
3202                         sig &= ~cur_bit;
3203                 }
3204         }
3205
3206         return par_num;
3207 }
3208
3209 static int
3210 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3211                               uint8_t print)
3212 {
3213         uint32_t cur_bit = 0;
3214         int i = 0;
3215
3216         for (i = 0; sig; i++) {
3217                 cur_bit = ((uint32_t) 0x1 << i);
3218                 if (sig & cur_bit) {
3219                         switch (cur_bit) {
3220                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3221                                 if (print)
3222                                         bnx2x_print_next_block(sc, par_num++,
3223                                                              "CSEMI");
3224                                 break;
3225                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3226                                 if (print)
3227                                         bnx2x_print_next_block(sc, par_num++,
3228                                                              "PXP");
3229                                 break;
3230                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3231                                 if (print)
3232                                         bnx2x_print_next_block(sc, par_num++,
3233                                                              "PXPPCICLOCKCLIENT");
3234                                 break;
3235                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3236                                 if (print)
3237                                         bnx2x_print_next_block(sc, par_num++,
3238                                                              "CFC");
3239                                 break;
3240                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3241                                 if (print)
3242                                         bnx2x_print_next_block(sc, par_num++,
3243                                                              "CDU");
3244                                 break;
3245                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3246                                 if (print)
3247                                         bnx2x_print_next_block(sc, par_num++,
3248                                                              "DMAE");
3249                                 break;
3250                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3251                                 if (print)
3252                                         bnx2x_print_next_block(sc, par_num++,
3253                                                              "IGU");
3254                                 break;
3255                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3256                                 if (print)
3257                                         bnx2x_print_next_block(sc, par_num++,
3258                                                              "MISC");
3259                                 break;
3260                         }
3261
3262                         /* Clear the bit */
3263                         sig &= ~cur_bit;
3264                 }
3265         }
3266
3267         return par_num;
3268 }
3269
3270 static int
3271 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3272                               uint8_t * global, uint8_t print)
3273 {
3274         uint32_t cur_bit = 0;
3275         int i = 0;
3276
3277         for (i = 0; sig; i++) {
3278                 cur_bit = ((uint32_t) 0x1 << i);
3279                 if (sig & cur_bit) {
3280                         switch (cur_bit) {
3281                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3282                                 if (print)
3283                                         bnx2x_print_next_block(sc, par_num++,
3284                                                              "MCP ROM");
3285                                 *global = TRUE;
3286                                 break;
3287                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3288                                 if (print)
3289                                         bnx2x_print_next_block(sc, par_num++,
3290                                                              "MCP UMP RX");
3291                                 *global = TRUE;
3292                                 break;
3293                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3294                                 if (print)
3295                                         bnx2x_print_next_block(sc, par_num++,
3296                                                              "MCP UMP TX");
3297                                 *global = TRUE;
3298                                 break;
3299                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3300                                 if (print)
3301                                         bnx2x_print_next_block(sc, par_num++,
3302                                                              "MCP SCPAD");
3303                                 *global = TRUE;
3304                                 break;
3305                         }
3306
3307                         /* Clear the bit */
3308                         sig &= ~cur_bit;
3309                 }
3310         }
3311
3312         return par_num;
3313 }
3314
3315 static int
3316 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3317                               uint8_t print)
3318 {
3319         uint32_t cur_bit = 0;
3320         int i = 0;
3321
3322         for (i = 0; sig; i++) {
3323                 cur_bit = ((uint32_t) 0x1 << i);
3324                 if (sig & cur_bit) {
3325                         switch (cur_bit) {
3326                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3327                                 if (print)
3328                                         bnx2x_print_next_block(sc, par_num++,
3329                                                              "PGLUE_B");
3330                                 break;
3331                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3332                                 if (print)
3333                                         bnx2x_print_next_block(sc, par_num++,
3334                                                              "ATC");
3335                                 break;
3336                         }
3337
3338                         /* Clear the bit */
3339                         sig &= ~cur_bit;
3340                 }
3341         }
3342
3343         return par_num;
3344 }
3345
3346 static uint8_t
3347 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3348                 uint32_t * sig)
3349 {
3350         int par_num = 0;
3351
3352         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3353             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3354             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3355             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3356             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3357                 PMD_DRV_LOG(ERR, sc,
3358                             "Parity error: HW block parity attention:"
3359                             "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3360                             (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3361                             (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3362                             (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3363                             (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3364                             (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3365
3366                 if (print)
3367                         PMD_DRV_LOG(INFO, sc, "Parity errors detected in blocks: ");
3368
3369                 par_num =
3370                     bnx2x_check_blocks_with_parity0(sc, sig[0] &
3371                                                   HW_PRTY_ASSERT_SET_0,
3372                                                   par_num, print);
3373                 par_num =
3374                     bnx2x_check_blocks_with_parity1(sc, sig[1] &
3375                                                   HW_PRTY_ASSERT_SET_1,
3376                                                   par_num, global, print);
3377                 par_num =
3378                     bnx2x_check_blocks_with_parity2(sc, sig[2] &
3379                                                   HW_PRTY_ASSERT_SET_2,
3380                                                   par_num, print);
3381                 par_num =
3382                     bnx2x_check_blocks_with_parity3(sc, sig[3] &
3383                                                   HW_PRTY_ASSERT_SET_3,
3384                                                   par_num, global, print);
3385                 par_num =
3386                     bnx2x_check_blocks_with_parity4(sc, sig[4] &
3387                                                   HW_PRTY_ASSERT_SET_4,
3388                                                   par_num, print);
3389
3390                 if (print)
3391                         PMD_DRV_LOG(INFO, sc, "");
3392
3393                 return TRUE;
3394         }
3395
3396         return FALSE;
3397 }
3398
3399 static uint8_t
3400 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3401 {
3402         struct attn_route attn = { {0} };
3403         int port = SC_PORT(sc);
3404
3405         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3406         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3407         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3408         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3409
3410         if (!CHIP_IS_E1x(sc))
3411                 attn.sig[4] =
3412                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3413
3414         return bnx2x_parity_attn(sc, global, print, attn.sig);
3415 }
3416
3417 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3418 {
3419         uint32_t val;
3420
3421         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3422                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3423                 PMD_DRV_LOG(INFO, sc, "ERROR: PGLUE hw attention 0x%08x", val);
3424                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3425                         PMD_DRV_LOG(INFO, sc,
3426                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3427                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3428                         PMD_DRV_LOG(INFO, sc,
3429                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3430                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3431                         PMD_DRV_LOG(INFO, sc,
3432                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3433                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3434                         PMD_DRV_LOG(INFO, sc,
3435                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3436                 if (val &
3437                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3438                         PMD_DRV_LOG(INFO, sc,
3439                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3440                 if (val &
3441                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3442                         PMD_DRV_LOG(INFO, sc,
3443                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3444                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3445                         PMD_DRV_LOG(INFO, sc,
3446                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3447                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3448                         PMD_DRV_LOG(INFO, sc,
3449                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3450                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3451                         PMD_DRV_LOG(INFO, sc,
3452                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3453         }
3454
3455         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3456                 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3457                 PMD_DRV_LOG(INFO, sc, "ERROR: ATC hw attention 0x%08x", val);
3458                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3459                         PMD_DRV_LOG(INFO, sc,
3460                                     "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3461                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3462                         PMD_DRV_LOG(INFO, sc,
3463                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3464                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3465                         PMD_DRV_LOG(INFO, sc,
3466                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3467                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3468                         PMD_DRV_LOG(INFO, sc,
3469                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3470                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3471                         PMD_DRV_LOG(INFO, sc,
3472                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3473                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3474                         PMD_DRV_LOG(INFO, sc,
3475                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3476         }
3477
3478         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3479                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3480                 PMD_DRV_LOG(INFO, sc,
3481                             "ERROR: FATAL parity attention set4 0x%08x",
3482                             (uint32_t) (attn &
3483                                         (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3484                                          |
3485                                          AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3486         }
3487 }
3488
3489 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3490 {
3491         int port = SC_PORT(sc);
3492
3493         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3494 }
3495
3496 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3497 {
3498         int port = SC_PORT(sc);
3499
3500         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3501 }
3502
3503 /*
3504  * called due to MCP event (on pmf):
3505  *   reread new bandwidth configuration
3506  *   configure FW
3507  *   notify others function about the change
3508  */
3509 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3510 {
3511         if (sc->link_vars.link_up) {
3512                 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3513                 bnx2x_link_sync_notify(sc);
3514         }
3515
3516         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3517 }
3518
3519 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3520 {
3521         bnx2x_config_mf_bw(sc);
3522         bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3523 }
3524
3525 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3526 {
3527         bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3528 }
3529
3530 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3531
3532 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3533 {
3534         struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3535
3536         strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3537                 ETH_STAT_INFO_VERSION_LEN);
3538
3539         sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3540                                               DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3541                                               ether_stat->mac_local + MAC_PAD,
3542                                               MAC_PAD, ETH_ALEN);
3543
3544         ether_stat->mtu_size = sc->mtu;
3545
3546         ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3547         ether_stat->promiscuous_mode = 0;       // (flags & PROMISC) ? 1 : 0;
3548
3549         ether_stat->txq_size = sc->tx_ring_size;
3550         ether_stat->rxq_size = sc->rx_ring_size;
3551 }
3552
3553 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3554 {
3555         enum drv_info_opcode op_code;
3556         uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3557
3558         /* if drv_info version supported by MFW doesn't match - send NACK */
3559         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3560                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3561                 return;
3562         }
3563
3564         op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3565                    DRV_INFO_CONTROL_OP_CODE_SHIFT);
3566
3567         memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3568
3569         switch (op_code) {
3570         case ETH_STATS_OPCODE:
3571                 bnx2x_drv_info_ether_stat(sc);
3572                 break;
3573         case FCOE_STATS_OPCODE:
3574         case ISCSI_STATS_OPCODE:
3575         default:
3576                 /* if op code isn't supported - send NACK */
3577                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3578                 return;
3579         }
3580
3581         /*
3582          * If we got drv_info attn from MFW then these fields are defined in
3583          * shmem2 for sure
3584          */
3585         SHMEM2_WR(sc, drv_info_host_addr_lo,
3586                   U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3587         SHMEM2_WR(sc, drv_info_host_addr_hi,
3588                   U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3589
3590         bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3591 }
3592
3593 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3594 {
3595         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3596 /*
3597  * This is the only place besides the function initialization
3598  * where the sc->flags can change so it is done without any
3599  * locks
3600  */
3601                 if (sc->devinfo.
3602                     mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3603                         PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
3604                         sc->flags |= BNX2X_MF_FUNC_DIS;
3605                         bnx2x_e1h_disable(sc);
3606                 } else {
3607                         PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
3608                         sc->flags &= ~BNX2X_MF_FUNC_DIS;
3609                         bnx2x_e1h_enable(sc);
3610                 }
3611                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3612         }
3613
3614         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3615                 bnx2x_config_mf_bw(sc);
3616                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3617         }
3618
3619         /* Report results to MCP */
3620         if (dcc_event)
3621                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3622         else
3623                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3624 }
3625
3626 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3627 {
3628         int port = SC_PORT(sc);
3629         uint32_t val;
3630
3631         sc->port.pmf = 1;
3632
3633         /*
3634          * We need the mb() to ensure the ordering between the writing to
3635          * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3636          */
3637         mb();
3638
3639         /* enable nig attention */
3640         val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3641         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3642                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3643                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3644         } else if (!CHIP_IS_E1x(sc)) {
3645                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3646                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3647         }
3648
3649         bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3650 }
3651
3652 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3653 {
3654         char last_idx;
3655         int i, rc = 0;
3656         __rte_unused uint32_t row0, row1, row2, row3;
3657
3658         /* XSTORM */
3659         last_idx =
3660             REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3661         if (last_idx)
3662                 PMD_DRV_LOG(ERR, sc, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3663
3664         /* print the asserts */
3665         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3666
3667                 row0 =
3668                     REG_RD(sc,
3669                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3670                 row1 =
3671                     REG_RD(sc,
3672                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3673                            4);
3674                 row2 =
3675                     REG_RD(sc,
3676                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3677                            8);
3678                 row3 =
3679                     REG_RD(sc,
3680                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3681                            12);
3682
3683                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3684                         PMD_DRV_LOG(ERR, sc,
3685                                     "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3686                                     i, row3, row2, row1, row0);
3687                         rc++;
3688                 } else {
3689                         break;
3690                 }
3691         }
3692
3693         /* TSTORM */
3694         last_idx =
3695             REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3696         if (last_idx) {
3697                 PMD_DRV_LOG(ERR, sc, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3698         }
3699
3700         /* print the asserts */
3701         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3702
3703                 row0 =
3704                     REG_RD(sc,
3705                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3706                 row1 =
3707                     REG_RD(sc,
3708                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3709                            4);
3710                 row2 =
3711                     REG_RD(sc,
3712                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3713                            8);
3714                 row3 =
3715                     REG_RD(sc,
3716                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3717                            12);
3718
3719                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3720                         PMD_DRV_LOG(ERR, sc,
3721                                     "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3722                                     i, row3, row2, row1, row0);
3723                         rc++;
3724                 } else {
3725                         break;
3726                 }
3727         }
3728
3729         /* CSTORM */
3730         last_idx =
3731             REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3732         if (last_idx) {
3733                 PMD_DRV_LOG(ERR, sc, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3734         }
3735
3736         /* print the asserts */
3737         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3738
3739                 row0 =
3740                     REG_RD(sc,
3741                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3742                 row1 =
3743                     REG_RD(sc,
3744                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3745                            4);
3746                 row2 =
3747                     REG_RD(sc,
3748                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3749                            8);
3750                 row3 =
3751                     REG_RD(sc,
3752                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3753                            12);
3754
3755                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3756                         PMD_DRV_LOG(ERR, sc,
3757                                     "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3758                                     i, row3, row2, row1, row0);
3759                         rc++;
3760                 } else {
3761                         break;
3762                 }
3763         }
3764
3765         /* USTORM */
3766         last_idx =
3767             REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3768         if (last_idx) {
3769                 PMD_DRV_LOG(ERR, sc, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3770         }
3771
3772         /* print the asserts */
3773         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3774
3775                 row0 =
3776                     REG_RD(sc,
3777                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3778                 row1 =
3779                     REG_RD(sc,
3780                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3781                            4);
3782                 row2 =
3783                     REG_RD(sc,
3784                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3785                            8);
3786                 row3 =
3787                     REG_RD(sc,
3788                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3789                            12);
3790
3791                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3792                         PMD_DRV_LOG(ERR, sc,
3793                                     "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3794                                     i, row3, row2, row1, row0);
3795                         rc++;
3796                 } else {
3797                         break;
3798                 }
3799         }
3800
3801         return rc;
3802 }
3803
3804 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3805 {
3806         int func = SC_FUNC(sc);
3807         uint32_t val;
3808
3809         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3810
3811                 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3812
3813                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3814                         bnx2x_read_mf_cfg(sc);
3815                         sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3816                             MFCFG_RD(sc,
3817                                      func_mf_config[SC_ABS_FUNC(sc)].config);
3818                         val =
3819                             SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3820
3821                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3822                                 bnx2x_dcc_event(sc,
3823                                               (val &
3824                                                DRV_STATUS_DCC_EVENT_MASK));
3825
3826                         if (val & DRV_STATUS_SET_MF_BW)
3827                                 bnx2x_set_mf_bw(sc);
3828
3829                         if (val & DRV_STATUS_DRV_INFO_REQ)
3830                                 bnx2x_handle_drv_info_req(sc);
3831
3832                         if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3833                                 bnx2x_pmf_update(sc);
3834
3835                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3836                                 bnx2x_handle_eee_event(sc);
3837
3838                         if (sc->link_vars.periodic_flags &
3839                             ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3840                                 /* sync with link */
3841                                 sc->link_vars.periodic_flags &=
3842                                     ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3843                                 if (IS_MF(sc)) {
3844                                         bnx2x_link_sync_notify(sc);
3845                                 }
3846                                 bnx2x_link_report(sc);
3847                         }
3848
3849                         /*
3850                          * Always call it here: bnx2x_link_report() will
3851                          * prevent the link indication duplication.
3852                          */
3853                         bnx2x_link_status_update(sc);
3854
3855                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3856
3857                         PMD_DRV_LOG(ERR, sc, "MC assert!");
3858                         bnx2x_mc_assert(sc);
3859                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3860                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3861                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3862                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3863                         rte_panic("MC assert!");
3864
3865                 } else if (attn & BNX2X_MCP_ASSERT) {
3866
3867                         PMD_DRV_LOG(ERR, sc, "MCP assert!");
3868                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3869
3870                 } else {
3871                         PMD_DRV_LOG(ERR, sc,
3872                                     "Unknown HW assert! (attn 0x%08x)", attn);
3873                 }
3874         }
3875
3876         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3877                 PMD_DRV_LOG(ERR, sc, "LATCHED attention 0x%08x (masked)", attn);
3878                 if (attn & BNX2X_GRC_TIMEOUT) {
3879                         val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3880                         PMD_DRV_LOG(ERR, sc, "GRC time-out 0x%08x", val);
3881                 }
3882                 if (attn & BNX2X_GRC_RSV) {
3883                         val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3884                         PMD_DRV_LOG(ERR, sc, "GRC reserved 0x%08x", val);
3885                 }
3886                 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3887         }
3888 }
3889
3890 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3891 {
3892         int port = SC_PORT(sc);
3893         int reg_offset;
3894         uint32_t val0, mask0, val1, mask1;
3895         uint32_t val;
3896
3897         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3898                 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3899                 PMD_DRV_LOG(ERR, sc, "CFC hw attention 0x%08x", val);
3900 /* CFC error attention */
3901                 if (val & 0x2) {
3902                         PMD_DRV_LOG(ERR, sc, "FATAL error from CFC");
3903                 }
3904         }
3905
3906         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3907                 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3908                 PMD_DRV_LOG(ERR, sc, "PXP hw attention-0 0x%08x", val);
3909 /* RQ_USDMDP_FIFO_OVERFLOW */
3910                 if (val & 0x18000) {
3911                         PMD_DRV_LOG(ERR, sc, "FATAL error from PXP");
3912                 }
3913
3914                 if (!CHIP_IS_E1x(sc)) {
3915                         val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3916                         PMD_DRV_LOG(ERR, sc, "PXP hw attention-1 0x%08x", val);
3917                 }
3918         }
3919 #define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3920 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3921
3922         if (attn & AEU_PXP2_HW_INT_BIT) {
3923 /*  CQ47854 workaround do not panic on
3924  *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3925  */
3926                 if (!CHIP_IS_E1x(sc)) {
3927                         mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3928                         val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3929                         mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3930                         val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3931                         /*
3932                          * If the only PXP2_EOP_ERROR_BIT is set in
3933                          * STS0 and STS1 - clear it
3934                          *
3935                          * probably we lose additional attentions between
3936                          * STS0 and STS_CLR0, in this case user will not
3937                          * be notified about them
3938                          */
3939                         if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3940                             !(val1 & mask1))
3941                                 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3942
3943                         /* print the register, since no one can restore it */
3944                         PMD_DRV_LOG(ERR, sc,
3945                                     "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3946
3947                         /*
3948                          * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3949                          * then notify
3950                          */
3951                         if (val0 & PXP2_EOP_ERROR_BIT) {
3952                                 PMD_DRV_LOG(ERR, sc, "PXP2_WR_PGLUE_EOP_ERROR");
3953
3954                                 /*
3955                                  * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3956                                  * set then clear attention from PXP2 block without panic
3957                                  */
3958                                 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3959                                     ((val1 & mask1) == 0))
3960                                         attn &= ~AEU_PXP2_HW_INT_BIT;
3961                         }
3962                 }
3963         }
3964
3965         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3966                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3967                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3968
3969                 val = REG_RD(sc, reg_offset);
3970                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3971                 REG_WR(sc, reg_offset, val);
3972
3973                 PMD_DRV_LOG(ERR, sc,
3974                             "FATAL HW block attention set2 0x%x",
3975                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
3976                 rte_panic("HW block attention set2");
3977         }
3978 }
3979
3980 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
3981 {
3982         int port = SC_PORT(sc);
3983         int reg_offset;
3984         uint32_t val;
3985
3986         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3987                 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
3988                 PMD_DRV_LOG(ERR, sc, "DB hw attention 0x%08x", val);
3989 /* DORQ discard attention */
3990                 if (val & 0x2) {
3991                         PMD_DRV_LOG(ERR, sc, "FATAL error from DORQ");
3992                 }
3993         }
3994
3995         if (attn & HW_INTERRUT_ASSERT_SET_1) {
3996                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3997                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3998
3999                 val = REG_RD(sc, reg_offset);
4000                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4001                 REG_WR(sc, reg_offset, val);
4002
4003                 PMD_DRV_LOG(ERR, sc,
4004                             "FATAL HW block attention set1 0x%08x",
4005                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4006                 rte_panic("HW block attention set1");
4007         }
4008 }
4009
4010 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4011 {
4012         int port = SC_PORT(sc);
4013         int reg_offset;
4014         uint32_t val;
4015
4016         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4017             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4018
4019         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4020                 val = REG_RD(sc, reg_offset);
4021                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4022                 REG_WR(sc, reg_offset, val);
4023
4024                 PMD_DRV_LOG(WARNING, sc, "SPIO5 hw attention");
4025
4026 /* Fan failure attention */
4027                 elink_hw_reset_phy(&sc->link_params);
4028                 bnx2x_fan_failure(sc);
4029         }
4030
4031         if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4032                 elink_handle_module_detect_int(&sc->link_params);
4033         }
4034
4035         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4036                 val = REG_RD(sc, reg_offset);
4037                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4038                 REG_WR(sc, reg_offset, val);
4039
4040                 rte_panic("FATAL HW block attention set0 0x%lx",
4041                           (attn & HW_INTERRUT_ASSERT_SET_0));
4042         }
4043 }
4044
4045 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4046 {
4047         struct attn_route attn;
4048         struct attn_route *group_mask;
4049         int port = SC_PORT(sc);
4050         int index;
4051         uint32_t reg_addr;
4052         uint32_t val;
4053         uint32_t aeu_mask;
4054         uint8_t global = FALSE;
4055
4056         /*
4057          * Need to take HW lock because MCP or other port might also
4058          * try to handle this event.
4059          */
4060         bnx2x_acquire_alr(sc);
4061
4062         if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4063                 sc->recovery_state = BNX2X_RECOVERY_INIT;
4064
4065 /* disable HW interrupts */
4066                 bnx2x_int_disable(sc);
4067                 bnx2x_release_alr(sc);
4068                 return;
4069         }
4070
4071         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4072         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4073         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4074         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4075         if (!CHIP_IS_E1x(sc)) {
4076                 attn.sig[4] =
4077                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4078         } else {
4079                 attn.sig[4] = 0;
4080         }
4081
4082         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4083                 if (deasserted & (1 << index)) {
4084                         group_mask = &sc->attn_group[index];
4085
4086                         bnx2x_attn_int_deasserted4(sc,
4087                                                  attn.
4088                                                  sig[4] & group_mask->sig[4]);
4089                         bnx2x_attn_int_deasserted3(sc,
4090                                                  attn.
4091                                                  sig[3] & group_mask->sig[3]);
4092                         bnx2x_attn_int_deasserted1(sc,
4093                                                  attn.
4094                                                  sig[1] & group_mask->sig[1]);
4095                         bnx2x_attn_int_deasserted2(sc,
4096                                                  attn.
4097                                                  sig[2] & group_mask->sig[2]);
4098                         bnx2x_attn_int_deasserted0(sc,
4099                                                  attn.
4100                                                  sig[0] & group_mask->sig[0]);
4101                 }
4102         }
4103
4104         bnx2x_release_alr(sc);
4105
4106         if (sc->devinfo.int_block == INT_BLOCK_HC) {
4107                 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4108                             COMMAND_REG_ATTN_BITS_CLR);
4109         } else {
4110                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4111         }
4112
4113         val = ~deasserted;
4114         PMD_DRV_LOG(DEBUG, sc,
4115                     "about to mask 0x%08x at %s addr 0x%08x", val,
4116                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4117                     reg_addr);
4118         REG_WR(sc, reg_addr, val);
4119
4120         if (~sc->attn_state & deasserted) {
4121                 PMD_DRV_LOG(ERR, sc, "IGU error");
4122         }
4123
4124         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4125             MISC_REG_AEU_MASK_ATTN_FUNC_0;
4126
4127         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4128
4129         aeu_mask = REG_RD(sc, reg_addr);
4130
4131         aeu_mask |= (deasserted & 0x3ff);
4132
4133         REG_WR(sc, reg_addr, aeu_mask);
4134         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4135
4136         sc->attn_state &= ~deasserted;
4137 }
4138
4139 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4140 {
4141         /* read local copy of bits */
4142         uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4143         uint32_t attn_ack =
4144             le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4145         uint32_t attn_state = sc->attn_state;
4146
4147         /* look for changed bits */
4148         uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4149         uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4150
4151         PMD_DRV_LOG(DEBUG, sc,
4152                     "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4153                     attn_bits, attn_ack, asserted, deasserted);
4154
4155         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4156                 PMD_DRV_LOG(ERR, sc, "BAD attention state");
4157         }
4158
4159         /* handle bits that were raised */
4160         if (asserted) {
4161                 bnx2x_attn_int_asserted(sc, asserted);
4162         }
4163
4164         if (deasserted) {
4165                 bnx2x_attn_int_deasserted(sc, deasserted);
4166         }
4167 }
4168
4169 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4170 {
4171         struct host_sp_status_block *def_sb = sc->def_sb;
4172         uint16_t rc = 0;
4173
4174         mb();                   /* status block is written to by the chip */
4175
4176         if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4177                 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4178                 rc |= BNX2X_DEF_SB_ATT_IDX;
4179         }
4180
4181         if (sc->def_idx != def_sb->sp_sb.running_index) {
4182                 sc->def_idx = def_sb->sp_sb.running_index;
4183                 rc |= BNX2X_DEF_SB_IDX;
4184         }
4185
4186         mb();
4187
4188         return rc;
4189 }
4190
4191 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4192                                                           uint32_t cid)
4193 {
4194         return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4195 }
4196
4197 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4198 {
4199         struct ecore_mcast_ramrod_params rparam;
4200         int rc;
4201
4202         memset(&rparam, 0, sizeof(rparam));
4203
4204         rparam.mcast_obj = &sc->mcast_obj;
4205
4206         /* clear pending state for the last command */
4207         sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4208
4209         /* if there are pending mcast commands - send them */
4210         if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4211                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4212                 if (rc < 0) {
4213                         PMD_DRV_LOG(INFO, sc,
4214                                     "Failed to send pending mcast commands (%d)",
4215                                     rc);
4216                 }
4217         }
4218 }
4219
4220 static void
4221 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4222 {
4223         unsigned long ramrod_flags = 0;
4224         int rc = 0;
4225         uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4226         struct ecore_vlan_mac_obj *vlan_mac_obj;
4227
4228         /* always push next commands out, don't wait here */
4229         bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4230
4231         switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4232         case ECORE_FILTER_MAC_PENDING:
4233                 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MAC completions");
4234                 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4235                 break;
4236
4237         case ECORE_FILTER_MCAST_PENDING:
4238                 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MCAST completions");
4239                 bnx2x_handle_mcast_eqe(sc);
4240                 return;
4241
4242         default:
4243                 PMD_DRV_LOG(NOTICE, sc, "Unsupported classification command: %d",
4244                             elem->message.data.eth_event.echo);
4245                 return;
4246         }
4247
4248         rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4249
4250         if (rc < 0) {
4251                 PMD_DRV_LOG(NOTICE, sc,
4252                             "Failed to schedule new commands (%d)", rc);
4253         } else if (rc > 0) {
4254                 PMD_DRV_LOG(DEBUG, sc, "Scheduled next pending commands...");
4255         }
4256 }
4257
4258 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4259 {
4260         bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4261
4262         /* send rx_mode command again if was requested */
4263         if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4264                 bnx2x_set_storm_rx_mode(sc);
4265         }
4266 }
4267
4268 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4269 {
4270         storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4271         wmb();                  /* keep prod updates ordered */
4272 }
4273
4274 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4275 {
4276         uint16_t hw_cons, sw_cons, sw_prod;
4277         union event_ring_elem *elem;
4278         uint8_t echo;
4279         uint32_t cid;
4280         uint8_t opcode;
4281         int spqe_cnt = 0;
4282         struct ecore_queue_sp_obj *q_obj;
4283         struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4284         struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4285
4286         hw_cons = le16toh(*sc->eq_cons_sb);
4287
4288         /*
4289          * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4290          * when we get to the next-page we need to adjust so the loop
4291          * condition below will be met. The next element is the size of a
4292          * regular element and hence incrementing by 1
4293          */
4294         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4295                 hw_cons++;
4296         }
4297
4298         /*
4299          * This function may never run in parallel with itself for a
4300          * specific sc and no need for a read memory barrier here.
4301          */
4302         sw_cons = sc->eq_cons;
4303         sw_prod = sc->eq_prod;
4304
4305         for (;
4306              sw_cons != hw_cons;
4307              sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4308
4309                 elem = &sc->eq[EQ_DESC(sw_cons)];
4310
4311 /* elem CID originates from FW, actually LE */
4312                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4313                 opcode = elem->message.opcode;
4314
4315 /* handle eq element */
4316                 switch (opcode) {
4317                 case EVENT_RING_OPCODE_STAT_QUERY:
4318                         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "got statistics completion event %d",
4319                                     sc->stats_comp++);
4320                         /* nothing to do with stats comp */
4321                         goto next_spqe;
4322
4323                 case EVENT_RING_OPCODE_CFC_DEL:
4324                         /* handle according to cid range */
4325                         /* we may want to verify here that the sc state is HALTING */
4326                         PMD_DRV_LOG(DEBUG, sc, "got delete ramrod for MULTI[%d]",
4327                                     cid);
4328                         q_obj = bnx2x_cid_to_q_obj(sc, cid);
4329                         if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4330                                 break;
4331                         }
4332                         goto next_spqe;
4333
4334                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4335                         PMD_DRV_LOG(DEBUG, sc, "got STOP TRAFFIC");
4336                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4337                                 break;
4338                         }
4339                         goto next_spqe;
4340
4341                 case EVENT_RING_OPCODE_START_TRAFFIC:
4342                         PMD_DRV_LOG(DEBUG, sc, "got START TRAFFIC");
4343                         if (f_obj->complete_cmd
4344                             (sc, f_obj, ECORE_F_CMD_TX_START)) {
4345                                 break;
4346                         }
4347                         goto next_spqe;
4348
4349                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4350                         echo = elem->message.data.function_update_event.echo;
4351                         if (echo == SWITCH_UPDATE) {
4352                                 PMD_DRV_LOG(DEBUG, sc,
4353                                             "got FUNC_SWITCH_UPDATE ramrod");
4354                                 if (f_obj->complete_cmd(sc, f_obj,
4355                                                         ECORE_F_CMD_SWITCH_UPDATE))
4356                                 {
4357                                         break;
4358                                 }
4359                         } else {
4360                                 PMD_DRV_LOG(DEBUG, sc,
4361                                             "AFEX: ramrod completed FUNCTION_UPDATE");
4362                                 f_obj->complete_cmd(sc, f_obj,
4363                                                     ECORE_F_CMD_AFEX_UPDATE);
4364                         }
4365                         goto next_spqe;
4366
4367                 case EVENT_RING_OPCODE_FORWARD_SETUP:
4368                         q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4369                         if (q_obj->complete_cmd(sc, q_obj,
4370                                                 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4371                                 break;
4372                         }
4373                         goto next_spqe;
4374
4375                 case EVENT_RING_OPCODE_FUNCTION_START:
4376                         PMD_DRV_LOG(DEBUG, sc, "got FUNC_START ramrod");
4377                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4378                                 break;
4379                         }
4380                         goto next_spqe;
4381
4382                 case EVENT_RING_OPCODE_FUNCTION_STOP:
4383                         PMD_DRV_LOG(DEBUG, sc, "got FUNC_STOP ramrod");
4384                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4385                                 break;
4386                         }
4387                         goto next_spqe;
4388                 }
4389
4390                 switch (opcode | sc->state) {
4391                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4392                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4393                         cid =
4394                             elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4395                         PMD_DRV_LOG(DEBUG, sc, "got RSS_UPDATE ramrod. CID %d",
4396                                     cid);
4397                         rss_raw->clear_pending(rss_raw);
4398                         break;
4399
4400                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4401                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4402                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4403                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4404                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4405                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4406                         PMD_DRV_LOG(DEBUG, sc,
4407                                     "got (un)set mac ramrod");
4408                         bnx2x_handle_classification_eqe(sc, elem);
4409                         break;
4410
4411                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4412                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4413                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4414                         PMD_DRV_LOG(DEBUG, sc,
4415                                     "got mcast ramrod");
4416                         bnx2x_handle_mcast_eqe(sc);
4417                         break;
4418
4419                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4420                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4421                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4422                         PMD_DRV_LOG(DEBUG, sc,
4423                                     "got rx_mode ramrod");
4424                         bnx2x_handle_rx_mode_eqe(sc);
4425                         break;
4426
4427                 default:
4428                         /* unknown event log error and continue */
4429                         PMD_DRV_LOG(INFO, sc, "Unknown EQ event %d, sc->state 0x%x",
4430                                     elem->message.opcode, sc->state);
4431                 }
4432
4433 next_spqe:
4434                 spqe_cnt++;
4435         }                       /* for */
4436
4437         mb();
4438         atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4439
4440         sc->eq_cons = sw_cons;
4441         sc->eq_prod = sw_prod;
4442
4443         /* make sure that above mem writes were issued towards the memory */
4444         wmb();
4445
4446         /* update producer */
4447         bnx2x_update_eq_prod(sc, sc->eq_prod);
4448 }
4449
4450 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4451 {
4452         uint16_t status;
4453         int rc = 0;
4454
4455         PMD_DRV_LOG(DEBUG, sc, "---> SP TASK <---");
4456
4457         /* what work needs to be performed? */
4458         status = bnx2x_update_dsb_idx(sc);
4459
4460         PMD_DRV_LOG(DEBUG, sc, "dsb status 0x%04x", status);
4461
4462         /* HW attentions */
4463         if (status & BNX2X_DEF_SB_ATT_IDX) {
4464                 PMD_DRV_LOG(DEBUG, sc, "---> ATTN INTR <---");
4465                 bnx2x_attn_int(sc);
4466                 status &= ~BNX2X_DEF_SB_ATT_IDX;
4467                 rc = 1;
4468         }
4469
4470         /* SP events: STAT_QUERY and others */
4471         if (status & BNX2X_DEF_SB_IDX) {
4472 /* handle EQ completions */
4473                 PMD_DRV_LOG(DEBUG, sc, "---> EQ INTR <---");
4474                 bnx2x_eq_int(sc);
4475                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4476                            le16toh(sc->def_idx), IGU_INT_NOP, 1);
4477                 status &= ~BNX2X_DEF_SB_IDX;
4478         }
4479
4480         /* if status is non zero then something went wrong */
4481         if (unlikely(status)) {
4482                 PMD_DRV_LOG(INFO, sc,
4483                             "Got an unknown SP interrupt! (0x%04x)", status);
4484         }
4485
4486         /* ack status block only if something was actually handled */
4487         bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4488                    le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4489
4490         return rc;
4491 }
4492
4493 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4494 {
4495         struct bnx2x_softc *sc = fp->sc;
4496         uint8_t more_rx = FALSE;
4497
4498         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc,
4499                                "---> FP TASK QUEUE (%d) <--", fp->index);
4500
4501         /* update the fastpath index */
4502         bnx2x_update_fp_sb_idx(fp);
4503
4504         if (scan_fp) {
4505                 if (bnx2x_has_rx_work(fp)) {
4506                         more_rx = bnx2x_rxeof(sc, fp);
4507                 }
4508
4509                 if (more_rx) {
4510                         /* still more work to do */
4511                         bnx2x_handle_fp_tq(fp, scan_fp);
4512                         return;
4513                 }
4514         }
4515
4516         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4517                    le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4518 }
4519
4520 /*
4521  * Legacy interrupt entry point.
4522  *
4523  * Verifies that the controller generated the interrupt and
4524  * then calls a separate routine to handle the various
4525  * interrupt causes: link, RX, and TX.
4526  */
4527 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4528 {
4529         struct bnx2x_fastpath *fp;
4530         uint32_t status, mask;
4531         int i, rc = 0;
4532
4533         /*
4534          * 0 for ustorm, 1 for cstorm
4535          * the bits returned from ack_int() are 0-15
4536          * bit 0 = attention status block
4537          * bit 1 = fast path status block
4538          * a mask of 0x2 or more = tx/rx event
4539          * a mask of 1 = slow path event
4540          */
4541
4542         status = bnx2x_ack_int(sc);
4543
4544         /* the interrupt is not for us */
4545         if (unlikely(status == 0)) {
4546                 return 0;
4547         }
4548
4549         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "Interrupt status 0x%04x", status);
4550         //bnx2x_dump_status_block(sc);
4551
4552         FOR_EACH_ETH_QUEUE(sc, i) {
4553                 fp = &sc->fp[i];
4554                 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4555                 if (status & mask) {
4556                         bnx2x_handle_fp_tq(fp, scan_fp);
4557                         status &= ~mask;
4558                 }
4559         }
4560
4561         if (unlikely(status & 0x1)) {
4562                 rc = bnx2x_handle_sp_tq(sc);
4563                 status &= ~0x1;
4564         }
4565
4566         if (unlikely(status)) {
4567                 PMD_DRV_LOG(WARNING, sc,
4568                             "Unexpected fastpath status (0x%08x)!", status);
4569         }
4570
4571         return rc;
4572 }
4573
4574 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4575 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4576 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4577 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4578 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4579 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4580 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4581 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4582 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4583
4584 static struct
4585 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4586         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4587         .init_hw_cmn = bnx2x_init_hw_common,
4588         .init_hw_port = bnx2x_init_hw_port,
4589         .init_hw_func = bnx2x_init_hw_func,
4590
4591         .reset_hw_cmn = bnx2x_reset_common,
4592         .reset_hw_port = bnx2x_reset_port,
4593         .reset_hw_func = bnx2x_reset_func,
4594
4595         .init_fw = bnx2x_init_firmware,
4596         .release_fw = bnx2x_release_firmware,
4597 };
4598
4599 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4600 {
4601         sc->dmae_ready = 0;
4602
4603         PMD_INIT_FUNC_TRACE(sc);
4604
4605         ecore_init_func_obj(sc,
4606                             &sc->func_obj,
4607                             BNX2X_SP(sc, func_rdata),
4608                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata),
4609                             BNX2X_SP(sc, func_afex_rdata),
4610                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4611                             &bnx2x_func_sp_drv);
4612 }
4613
4614 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4615 {
4616         struct ecore_func_state_params func_params = { NULL };
4617         int rc;
4618
4619         PMD_INIT_FUNC_TRACE(sc);
4620
4621         /* prepare the parameters for function state transitions */
4622         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4623
4624         func_params.f_obj = &sc->func_obj;
4625         func_params.cmd = ECORE_F_CMD_HW_INIT;
4626
4627         func_params.params.hw_init.load_phase = load_code;
4628
4629         /*
4630          * Via a plethora of function pointers, we will eventually reach
4631          * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4632          */
4633         rc = ecore_func_state_change(sc, &func_params);
4634
4635         return rc;
4636 }
4637
4638 static void
4639 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4640 {
4641         uint32_t i;
4642
4643         if (!(len % 4) && !(addr % 4)) {
4644                 for (i = 0; i < len; i += 4) {
4645                         REG_WR(sc, (addr + i), fill);
4646                 }
4647         } else {
4648                 for (i = 0; i < len; i++) {
4649                         REG_WR8(sc, (addr + i), fill);
4650                 }
4651         }
4652 }
4653
4654 /* writes FP SP data to FW - data_size in dwords */
4655 static void
4656 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4657                   uint32_t data_size)
4658 {
4659         uint32_t index;
4660
4661         for (index = 0; index < data_size; index++) {
4662                 REG_WR(sc,
4663                        (BAR_CSTRORM_INTMEM +
4664                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4665                         (sizeof(uint32_t) * index)), *(sb_data_p + index));
4666         }
4667 }
4668
4669 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4670 {
4671         struct hc_status_block_data_e2 sb_data_e2;
4672         struct hc_status_block_data_e1x sb_data_e1x;
4673         uint32_t *sb_data_p;
4674         uint32_t data_size = 0;
4675
4676         if (!CHIP_IS_E1x(sc)) {
4677                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4678                 sb_data_e2.common.state = SB_DISABLED;
4679                 sb_data_e2.common.p_func.vf_valid = FALSE;
4680                 sb_data_p = (uint32_t *) & sb_data_e2;
4681                 data_size = (sizeof(struct hc_status_block_data_e2) /
4682                              sizeof(uint32_t));
4683         } else {
4684                 memset(&sb_data_e1x, 0,
4685                        sizeof(struct hc_status_block_data_e1x));
4686                 sb_data_e1x.common.state = SB_DISABLED;
4687                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4688                 sb_data_p = (uint32_t *) & sb_data_e1x;
4689                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4690                              sizeof(uint32_t));
4691         }
4692
4693         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4694
4695         bnx2x_fill(sc,
4696                  (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4697                  CSTORM_STATUS_BLOCK_SIZE);
4698         bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4699                  0, CSTORM_SYNC_BLOCK_SIZE);
4700 }
4701
4702 static void
4703 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4704                   struct hc_sp_status_block_data *sp_sb_data)
4705 {
4706         uint32_t i;
4707
4708         for (i = 0;
4709              i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4710              i++) {
4711                 REG_WR(sc,
4712                        (BAR_CSTRORM_INTMEM +
4713                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4714                         (i * sizeof(uint32_t))),
4715                        *((uint32_t *) sp_sb_data + i));
4716         }
4717 }
4718
4719 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4720 {
4721         struct hc_sp_status_block_data sp_sb_data;
4722
4723         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4724
4725         sp_sb_data.state = SB_DISABLED;
4726         sp_sb_data.p_func.vf_valid = FALSE;
4727
4728         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4729
4730         bnx2x_fill(sc,
4731                  (BAR_CSTRORM_INTMEM +
4732                   CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4733                  0, CSTORM_SP_STATUS_BLOCK_SIZE);
4734         bnx2x_fill(sc,
4735                  (BAR_CSTRORM_INTMEM +
4736                   CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4737                  0, CSTORM_SP_SYNC_BLOCK_SIZE);
4738 }
4739
4740 static void
4741 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4742                              int igu_seg_id)
4743 {
4744         hc_sm->igu_sb_id = igu_sb_id;
4745         hc_sm->igu_seg_id = igu_seg_id;
4746         hc_sm->timer_value = 0xFF;
4747         hc_sm->time_to_expire = 0xFFFFFFFF;
4748 }
4749
4750 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4751 {
4752         /* zero out state machine indices */
4753
4754         /* rx indices */
4755         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4756
4757         /* tx indices */
4758         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4759         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4760         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4761         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4762
4763         /* map indices */
4764
4765         /* rx indices */
4766         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4767             (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4768
4769         /* tx indices */
4770         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4771             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4772         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4773             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4774         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4775             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4776         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4777             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4778 }
4779
4780 static void
4781 bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid,
4782             uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4783 {
4784         struct hc_status_block_data_e2 sb_data_e2;
4785         struct hc_status_block_data_e1x sb_data_e1x;
4786         struct hc_status_block_sm *hc_sm_p;
4787         uint32_t *sb_data_p;
4788         int igu_seg_id;
4789         int data_size;
4790
4791         if (CHIP_INT_MODE_IS_BC(sc)) {
4792                 igu_seg_id = HC_SEG_ACCESS_NORM;
4793         } else {
4794                 igu_seg_id = IGU_SEG_ACCESS_NORM;
4795         }
4796
4797         bnx2x_zero_fp_sb(sc, fw_sb_id);
4798
4799         if (!CHIP_IS_E1x(sc)) {
4800                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4801                 sb_data_e2.common.state = SB_ENABLED;
4802                 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4803                 sb_data_e2.common.p_func.vf_id = vfid;
4804                 sb_data_e2.common.p_func.vf_valid = vf_valid;
4805                 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4806                 sb_data_e2.common.same_igu_sb_1b = TRUE;
4807                 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4808                 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4809                 hc_sm_p = sb_data_e2.common.state_machine;
4810                 sb_data_p = (uint32_t *) & sb_data_e2;
4811                 data_size = (sizeof(struct hc_status_block_data_e2) /
4812                              sizeof(uint32_t));
4813                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4814         } else {
4815                 memset(&sb_data_e1x, 0,
4816                        sizeof(struct hc_status_block_data_e1x));
4817                 sb_data_e1x.common.state = SB_ENABLED;
4818                 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4819                 sb_data_e1x.common.p_func.vf_id = 0xff;
4820                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4821                 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4822                 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4823                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4824                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4825                 hc_sm_p = sb_data_e1x.common.state_machine;
4826                 sb_data_p = (uint32_t *) & sb_data_e1x;
4827                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4828                              sizeof(uint32_t));
4829                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4830         }
4831
4832         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4833         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4834
4835         /* write indices to HW - PCI guarantees endianity of regpairs */
4836         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4837 }
4838
4839 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4840 {
4841         if (CHIP_IS_E1x(fp->sc)) {
4842                 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4843         } else {
4844                 return fp->cl_id;
4845         }
4846 }
4847
4848 static uint32_t
4849 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4850 {
4851         uint32_t offset = BAR_USTRORM_INTMEM;
4852
4853         if (IS_VF(sc)) {
4854                 return PXP_VF_ADDR_USDM_QUEUES_START +
4855                         (sc->acquire_resp.resc.hw_qid[fp->index] *
4856                          sizeof(struct ustorm_queue_zone_data));
4857         } else if (!CHIP_IS_E1x(sc)) {
4858                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4859         } else {
4860                 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4861         }
4862
4863         return offset;
4864 }
4865
4866 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4867 {
4868         struct bnx2x_fastpath *fp = &sc->fp[idx];
4869         uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4870         unsigned long q_type = 0;
4871         int cos;
4872
4873         fp->sc = sc;
4874         fp->index = idx;
4875
4876         fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4877         fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4878
4879         if (CHIP_IS_E1x(sc))
4880                 fp->cl_id = SC_L_ID(sc) + idx;
4881         else
4882 /* want client ID same as IGU SB ID for non-E1 */
4883                 fp->cl_id = fp->igu_sb_id;
4884         fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4885
4886         /* setup sb indices */
4887         if (!CHIP_IS_E1x(sc)) {
4888                 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4889                 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4890         } else {
4891                 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4892                 fp->sb_running_index =
4893                     fp->status_block.e1x_sb->sb.running_index;
4894         }
4895
4896         /* init shortcut */
4897         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4898
4899         fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4900
4901         for (cos = 0; cos < sc->max_cos; cos++) {
4902                 cids[cos] = idx;
4903         }
4904         fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4905
4906         /* nothing more for a VF to do */
4907         if (IS_VF(sc)) {
4908                 return;
4909         }
4910
4911         bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4912                     fp->fw_sb_id, fp->igu_sb_id);
4913
4914         bnx2x_update_fp_sb_idx(fp);
4915
4916         /* Configure Queue State object */
4917         bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4918         bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4919
4920         ecore_init_queue_obj(sc,
4921                              &sc->sp_objs[idx].q_obj,
4922                              fp->cl_id,
4923                              cids,
4924                              sc->max_cos,
4925                              SC_FUNC(sc),
4926                              BNX2X_SP(sc, q_rdata),
4927                              (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata),
4928                              q_type);
4929
4930         /* configure classification DBs */
4931         ecore_init_mac_obj(sc,
4932                            &sc->sp_objs[idx].mac_obj,
4933                            fp->cl_id,
4934                            idx,
4935                            SC_FUNC(sc),
4936                            BNX2X_SP(sc, mac_rdata),
4937                            (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4938                            ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4939                            ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4940 }
4941
4942 static void
4943 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4944                    uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4945 {
4946         union ustorm_eth_rx_producers rx_prods;
4947         uint32_t i;
4948
4949         /* update producers */
4950         rx_prods.prod.bd_prod = rx_bd_prod;
4951         rx_prods.prod.cqe_prod = rx_cq_prod;
4952         rx_prods.prod.reserved = 0;
4953
4954         /*
4955          * Make sure that the BD and SGE data is updated before updating the
4956          * producers since FW might read the BD/SGE right after the producer
4957          * is updated.
4958          * This is only applicable for weak-ordered memory model archs such
4959          * as IA-64. The following barrier is also mandatory since FW will
4960          * assumes BDs must have buffers.
4961          */
4962         wmb();
4963
4964         for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
4965                 REG_WR(sc,
4966                        (fp->ustorm_rx_prods_offset + (i * 4)),
4967                        rx_prods.raw_data[i]);
4968         }
4969
4970         wmb();                  /* keep prod updates ordered */
4971 }
4972
4973 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
4974 {
4975         struct bnx2x_fastpath *fp;
4976         int i;
4977         struct bnx2x_rx_queue *rxq;
4978
4979         for (i = 0; i < sc->num_queues; i++) {
4980                 fp = &sc->fp[i];
4981                 rxq = sc->rx_queues[fp->index];
4982                 if (!rxq) {
4983                         PMD_RX_LOG(ERR, "RX queue is NULL");
4984                         return;
4985                 }
4986
4987                 rxq->rx_bd_head = 0;
4988                 rxq->rx_bd_tail = rxq->nb_rx_desc;
4989                 rxq->rx_cq_head = 0;
4990                 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
4991                 *fp->rx_cq_cons_sb = 0;
4992
4993                 /*
4994                  * Activate the BD ring...
4995                  * Warning, this will generate an interrupt (to the TSTORM)
4996                  * so this can only be done after the chip is initialized
4997                  */
4998                 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
4999
5000                 if (i != 0) {
5001                         continue;
5002                 }
5003         }
5004 }
5005
5006 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5007 {
5008         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5009
5010         fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5011         fp->tx_db.data.zero_fill1 = 0;
5012         fp->tx_db.data.prod = 0;
5013
5014         if (!txq) {
5015                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5016                 return;
5017         }
5018
5019         txq->tx_pkt_tail = 0;
5020         txq->tx_pkt_head = 0;
5021         txq->tx_bd_tail = 0;
5022         txq->tx_bd_head = 0;
5023 }
5024
5025 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5026 {
5027         int i;
5028
5029         for (i = 0; i < sc->num_queues; i++) {
5030                 bnx2x_init_tx_ring_one(&sc->fp[i]);
5031         }
5032 }
5033
5034 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5035 {
5036         struct host_sp_status_block *def_sb = sc->def_sb;
5037         rte_iova_t mapping = sc->def_sb_dma.paddr;
5038         int igu_sp_sb_index;
5039         int igu_seg_id;
5040         int port = SC_PORT(sc);
5041         int func = SC_FUNC(sc);
5042         int reg_offset, reg_offset_en5;
5043         uint64_t section;
5044         int index, sindex;
5045         struct hc_sp_status_block_data sp_sb_data;
5046
5047         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5048
5049         if (CHIP_INT_MODE_IS_BC(sc)) {
5050                 igu_sp_sb_index = DEF_SB_IGU_ID;
5051                 igu_seg_id = HC_SEG_ACCESS_DEF;
5052         } else {
5053                 igu_sp_sb_index = sc->igu_dsb_id;
5054                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5055         }
5056
5057         /* attentions */
5058         section = ((uint64_t) mapping +
5059                    offsetof(struct host_sp_status_block, atten_status_block));
5060         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5061         sc->attn_state = 0;
5062
5063         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5064             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5065
5066         reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5067             MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5068
5069         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5070 /* take care of sig[0]..sig[4] */
5071                 for (sindex = 0; sindex < 4; sindex++) {
5072                         sc->attn_group[index].sig[sindex] =
5073                             REG_RD(sc,
5074                                    (reg_offset + (sindex * 0x4) +
5075                                     (0x10 * index)));
5076                 }
5077
5078                 if (!CHIP_IS_E1x(sc)) {
5079                         /*
5080                          * enable5 is separate from the rest of the registers,
5081                          * and the address skip is 4 and not 16 between the
5082                          * different groups
5083                          */
5084                         sc->attn_group[index].sig[4] =
5085                             REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5086                 } else {
5087                         sc->attn_group[index].sig[4] = 0;
5088                 }
5089         }
5090
5091         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5092                 reg_offset =
5093                     port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5094                 REG_WR(sc, reg_offset, U64_LO(section));
5095                 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5096         } else if (!CHIP_IS_E1x(sc)) {
5097                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5098                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5099         }
5100
5101         section = ((uint64_t) mapping +
5102                    offsetof(struct host_sp_status_block, sp_sb));
5103
5104         bnx2x_zero_sp_sb(sc);
5105
5106         /* PCI guarantees endianity of regpair */
5107         sp_sb_data.state = SB_ENABLED;
5108         sp_sb_data.host_sb_addr.lo = U64_LO(section);
5109         sp_sb_data.host_sb_addr.hi = U64_HI(section);
5110         sp_sb_data.igu_sb_id = igu_sp_sb_index;
5111         sp_sb_data.igu_seg_id = igu_seg_id;
5112         sp_sb_data.p_func.pf_id = func;
5113         sp_sb_data.p_func.vnic_id = SC_VN(sc);
5114         sp_sb_data.p_func.vf_id = 0xff;
5115
5116         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5117
5118         bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5119 }
5120
5121 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5122 {
5123         atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5124         sc->spq_prod_idx = 0;
5125         sc->dsb_sp_prod =
5126             &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5127         sc->spq_prod_bd = sc->spq;
5128         sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5129 }
5130
5131 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5132 {
5133         union event_ring_elem *elem;
5134         int i;
5135
5136         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5137                 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5138
5139                 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5140                                                          BNX2X_PAGE_SIZE *
5141                                                          (i % NUM_EQ_PAGES)));
5142                 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5143                                                          BNX2X_PAGE_SIZE *
5144                                                          (i % NUM_EQ_PAGES)));
5145         }
5146
5147         sc->eq_cons = 0;
5148         sc->eq_prod = NUM_EQ_DESC;
5149         sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5150
5151         atomic_store_rel_long(&sc->eq_spq_left,
5152                               (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5153                                    NUM_EQ_DESC) - 1));
5154 }
5155
5156 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5157 {
5158         int i;
5159
5160         if (IS_MF_SI(sc)) {
5161 /*
5162  * In switch independent mode, the TSTORM needs to accept
5163  * packets that failed classification, since approximate match
5164  * mac addresses aren't written to NIG LLH.
5165  */
5166                 REG_WR8(sc,
5167                         (BAR_TSTRORM_INTMEM +
5168                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5169         } else
5170                 REG_WR8(sc,
5171                         (BAR_TSTRORM_INTMEM +
5172                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5173
5174         /*
5175          * Zero this manually as its initialization is currently missing
5176          * in the initTool.
5177          */
5178         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5179                 REG_WR(sc,
5180                        (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5181                        0);
5182         }
5183
5184         if (!CHIP_IS_E1x(sc)) {
5185                 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5186                         CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5187                         HC_IGU_NBC_MODE);
5188         }
5189 }
5190
5191 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5192 {
5193         switch (load_code) {
5194         case FW_MSG_CODE_DRV_LOAD_COMMON:
5195         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5196                 bnx2x_init_internal_common(sc);
5197                 /* no break */
5198
5199         case FW_MSG_CODE_DRV_LOAD_PORT:
5200                 /* nothing to do */
5201                 /* no break */
5202
5203         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5204                 /* internal memory per function is initialized inside bnx2x_pf_init */
5205                 break;
5206
5207         default:
5208                 PMD_DRV_LOG(NOTICE, sc, "Unknown load_code (0x%x) from MCP",
5209                             load_code);
5210                 break;
5211         }
5212 }
5213
5214 static void
5215 storm_memset_func_cfg(struct bnx2x_softc *sc,
5216                       struct tstorm_eth_function_common_config *tcfg,
5217                       uint16_t abs_fid)
5218 {
5219         uint32_t addr;
5220         size_t size;
5221
5222         addr = (BAR_TSTRORM_INTMEM +
5223                 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5224         size = sizeof(struct tstorm_eth_function_common_config);
5225         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5226 }
5227
5228 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5229 {
5230         struct tstorm_eth_function_common_config tcfg = { 0 };
5231
5232         if (CHIP_IS_E1x(sc)) {
5233                 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5234         }
5235
5236         /* Enable the function in the FW */
5237         storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5238         storm_memset_func_en(sc, p->func_id, 1);
5239
5240         /* spq */
5241         if (p->func_flgs & FUNC_FLG_SPQ) {
5242                 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5243                 REG_WR(sc,
5244                        (XSEM_REG_FAST_MEMORY +
5245                         XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5246         }
5247 }
5248
5249 /*
5250  * Calculates the sum of vn_min_rates.
5251  * It's needed for further normalizing of the min_rates.
5252  * Returns:
5253  *   sum of vn_min_rates.
5254  *     or
5255  *   0 - if all the min_rates are 0.
5256  * In the later case fainess algorithm should be deactivated.
5257  * If all min rates are not zero then those that are zeroes will be set to 1.
5258  */
5259 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5260 {
5261         uint32_t vn_cfg;
5262         uint32_t vn_min_rate;
5263         int all_zero = 1;
5264         int vn;
5265
5266         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5267                 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5268                 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5269                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5270
5271                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5272                         /* skip hidden VNs */
5273                         vn_min_rate = 0;
5274                 } else if (!vn_min_rate) {
5275                         /* If min rate is zero - set it to 100 */
5276                         vn_min_rate = DEF_MIN_RATE;
5277                 } else {
5278                         all_zero = 0;
5279                 }
5280
5281                 input->vnic_min_rate[vn] = vn_min_rate;
5282         }
5283
5284         /* if ETS or all min rates are zeros - disable fairness */
5285         if (all_zero) {
5286                 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5287         } else {
5288                 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5289         }
5290 }
5291
5292 static uint16_t
5293 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5294 {
5295         uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5296                             FUNC_MF_CFG_MAX_BW_SHIFT);
5297
5298         if (!max_cfg) {
5299                 PMD_DRV_LOG(DEBUG, sc,
5300                             "Max BW configured to 0 - using 100 instead");
5301                 max_cfg = 100;
5302         }
5303
5304         return max_cfg;
5305 }
5306
5307 static void
5308 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5309 {
5310         uint16_t vn_max_rate;
5311         uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5312         uint32_t max_cfg;
5313
5314         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5315                 vn_max_rate = 0;
5316         } else {
5317                 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5318
5319                 if (IS_MF_SI(sc)) {
5320                         /* max_cfg in percents of linkspeed */
5321                         vn_max_rate =
5322                             ((sc->link_vars.line_speed * max_cfg) / 100);
5323                 } else {        /* SD modes */
5324                         /* max_cfg is absolute in 100Mb units */
5325                         vn_max_rate = (max_cfg * 100);
5326                 }
5327         }
5328
5329         input->vnic_max_rate[vn] = vn_max_rate;
5330 }
5331
5332 static void
5333 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5334 {
5335         struct cmng_init_input input;
5336         int vn;
5337
5338         memset(&input, 0, sizeof(struct cmng_init_input));
5339
5340         input.port_rate = sc->link_vars.line_speed;
5341
5342         if (cmng_type == CMNG_FNS_MINMAX) {
5343 /* read mf conf from shmem */
5344                 if (read_cfg) {
5345                         bnx2x_read_mf_cfg(sc);
5346                 }
5347
5348 /* get VN min rate and enable fairness if not 0 */
5349                 bnx2x_calc_vn_min(sc, &input);
5350
5351 /* get VN max rate */
5352                 if (sc->port.pmf) {
5353                         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5354                                 bnx2x_calc_vn_max(sc, vn, &input);
5355                         }
5356                 }
5357
5358 /* always enable rate shaping and fairness */
5359                 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5360
5361                 ecore_init_cmng(&input, &sc->cmng);
5362                 return;
5363         }
5364 }
5365
5366 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5367 {
5368         if (CHIP_REV_IS_SLOW(sc)) {
5369                 return CMNG_FNS_NONE;
5370         }
5371
5372         if (IS_MF(sc)) {
5373                 return CMNG_FNS_MINMAX;
5374         }
5375
5376         return CMNG_FNS_NONE;
5377 }
5378
5379 static void
5380 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5381 {
5382         int vn;
5383         int func;
5384         uint32_t addr;
5385         size_t size;
5386
5387         addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5388         size = sizeof(struct cmng_struct_per_port);
5389         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5390
5391         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5392                 func = func_by_vn(sc, vn);
5393
5394                 addr = (BAR_XSTRORM_INTMEM +
5395                         XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5396                 size = sizeof(struct rate_shaping_vars_per_vn);
5397                 ecore_storm_memset_struct(sc, addr, size,
5398                                           (uint32_t *) & cmng->
5399                                           vnic.vnic_max_rate[vn]);
5400
5401                 addr = (BAR_XSTRORM_INTMEM +
5402                         XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5403                 size = sizeof(struct fairness_vars_per_vn);
5404                 ecore_storm_memset_struct(sc, addr, size,
5405                                           (uint32_t *) & cmng->
5406                                           vnic.vnic_min_rate[vn]);
5407         }
5408 }
5409
5410 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5411 {
5412         struct bnx2x_func_init_params func_init;
5413         struct event_ring_data eq_data;
5414         uint16_t flags;
5415
5416         memset(&eq_data, 0, sizeof(struct event_ring_data));
5417         memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5418
5419         if (!CHIP_IS_E1x(sc)) {
5420 /* reset IGU PF statistics: MSIX + ATTN */
5421 /* PF */
5422                 REG_WR(sc,
5423                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5424                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5425                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5426                          4)), 0);
5427 /* ATTN */
5428                 REG_WR(sc,
5429                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5430                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5431                         (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5432                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5433                          4)), 0);
5434         }
5435
5436         /* function setup flags */
5437         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5438
5439         func_init.func_flgs = flags;
5440         func_init.pf_id = SC_FUNC(sc);
5441         func_init.func_id = SC_FUNC(sc);
5442         func_init.spq_map = sc->spq_dma.paddr;
5443         func_init.spq_prod = sc->spq_prod_idx;
5444
5445         bnx2x_func_init(sc, &func_init);
5446
5447         memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5448
5449         /*
5450          * Congestion management values depend on the link rate.
5451          * There is no active link so initial link rate is set to 10Gbps.
5452          * When the link comes up the congestion management values are
5453          * re-calculated according to the actual link rate.
5454          */
5455         sc->link_vars.line_speed = SPEED_10000;
5456         bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5457
5458         /* Only the PMF sets the HW */
5459         if (sc->port.pmf) {
5460                 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5461         }
5462
5463         /* init Event Queue - PCI bus guarantees correct endainity */
5464         eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5465         eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5466         eq_data.producer = sc->eq_prod;
5467         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5468         eq_data.sb_id = DEF_SB_ID;
5469         storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5470 }
5471
5472 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5473 {
5474         int port = SC_PORT(sc);
5475         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5476         uint32_t val = REG_RD(sc, addr);
5477         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5478             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5479         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5480         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5481
5482         if (msix) {
5483                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5484                          HC_CONFIG_0_REG_INT_LINE_EN_0);
5485                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5486                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5487                 if (single_msix) {
5488                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5489                 }
5490         } else if (msi) {
5491                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5492                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5493                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5494                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5495         } else {
5496                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5497                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5498                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
5499                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5500
5501                 REG_WR(sc, addr, val);
5502
5503                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5504         }
5505
5506         REG_WR(sc, addr, val);
5507
5508         /* ensure that HC_CONFIG is written before leading/trailing edge config */
5509         mb();
5510
5511         /* init leading/trailing edge */
5512         if (IS_MF(sc)) {
5513                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5514                 if (sc->port.pmf) {
5515                         /* enable nig and gpio3 attention */
5516                         val |= 0x1100;
5517                 }
5518         } else {
5519                 val = 0xffff;
5520         }
5521
5522         REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5523         REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5524
5525         /* make sure that interrupts are indeed enabled from here on */
5526         mb();
5527 }
5528
5529 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5530 {
5531         uint32_t val;
5532         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5533             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5534         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5535         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5536
5537         val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5538
5539         if (msix) {
5540                 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5541                 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5542                 if (single_msix) {
5543                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
5544                 }
5545         } else if (msi) {
5546                 val &= ~IGU_PF_CONF_INT_LINE_EN;
5547                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5548                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5549         } else {
5550                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5551                 val |= (IGU_PF_CONF_INT_LINE_EN |
5552                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5553         }
5554
5555         /* clean previous status - need to configure igu prior to ack */
5556         if ((!msix) || single_msix) {
5557                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5558                 bnx2x_ack_int(sc);
5559         }
5560
5561         val |= IGU_PF_CONF_FUNC_EN;
5562
5563         PMD_DRV_LOG(DEBUG, sc, "write 0x%x to IGU mode %s",
5564                     val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5565
5566         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5567
5568         mb();
5569
5570         /* init leading/trailing edge */
5571         if (IS_MF(sc)) {
5572                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5573                 if (sc->port.pmf) {
5574                         /* enable nig and gpio3 attention */
5575                         val |= 0x1100;
5576                 }
5577         } else {
5578                 val = 0xffff;
5579         }
5580
5581         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5582         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5583
5584         /* make sure that interrupts are indeed enabled from here on */
5585         mb();
5586 }
5587
5588 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5589 {
5590         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5591                 bnx2x_hc_int_enable(sc);
5592         } else {
5593                 bnx2x_igu_int_enable(sc);
5594         }
5595 }
5596
5597 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5598 {
5599         int port = SC_PORT(sc);
5600         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5601         uint32_t val = REG_RD(sc, addr);
5602
5603         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5604                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5605                  HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5606         /* flush all outstanding writes */
5607         mb();
5608
5609         REG_WR(sc, addr, val);
5610         if (REG_RD(sc, addr) != val) {
5611                 PMD_DRV_LOG(ERR, sc, "proper val not read from HC IGU!");
5612         }
5613 }
5614
5615 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5616 {
5617         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5618
5619         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5620                  IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5621
5622         PMD_DRV_LOG(DEBUG, sc, "write %x to IGU", val);
5623
5624         /* flush all outstanding writes */
5625         mb();
5626
5627         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5628         if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5629                 PMD_DRV_LOG(ERR, sc, "proper val not read from IGU!");
5630         }
5631 }
5632
5633 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5634 {
5635         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5636                 bnx2x_hc_int_disable(sc);
5637         } else {
5638                 bnx2x_igu_int_disable(sc);
5639         }
5640 }
5641
5642 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5643 {
5644         int i;
5645
5646         PMD_INIT_FUNC_TRACE(sc);
5647
5648         for (i = 0; i < sc->num_queues; i++) {
5649                 bnx2x_init_eth_fp(sc, i);
5650         }
5651
5652         rmb();                  /* ensure status block indices were read */
5653
5654         bnx2x_init_rx_rings(sc);
5655         bnx2x_init_tx_rings(sc);
5656
5657         if (IS_VF(sc)) {
5658                 bnx2x_memset_stats(sc);
5659                 return;
5660         }
5661
5662         /* initialize MOD_ABS interrupts */
5663         elink_init_mod_abs_int(sc, &sc->link_vars,
5664                                sc->devinfo.chip_id,
5665                                sc->devinfo.shmem_base,
5666                                sc->devinfo.shmem2_base, SC_PORT(sc));
5667
5668         bnx2x_init_def_sb(sc);
5669         bnx2x_update_dsb_idx(sc);
5670         bnx2x_init_sp_ring(sc);
5671         bnx2x_init_eq_ring(sc);
5672         bnx2x_init_internal(sc, load_code);
5673         bnx2x_pf_init(sc);
5674         bnx2x_stats_init(sc);
5675
5676         /* flush all before enabling interrupts */
5677         mb();
5678
5679         bnx2x_int_enable(sc);
5680
5681         /* check for SPIO5 */
5682         bnx2x_attn_int_deasserted0(sc,
5683                                  REG_RD(sc,
5684                                         (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5685                                          SC_PORT(sc) * 4)) &
5686                                  AEU_INPUTS_ATTN_BITS_SPIO5);
5687 }
5688
5689 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5690 {
5691         /* mcast rules must be added to tx if tx switching is enabled */
5692         ecore_obj_type o_type;
5693         if (sc->flags & BNX2X_TX_SWITCHING)
5694                 o_type = ECORE_OBJ_TYPE_RX_TX;
5695         else
5696                 o_type = ECORE_OBJ_TYPE_RX;
5697
5698         /* RX_MODE controlling object */
5699         ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5700
5701         /* multicast configuration controlling object */
5702         ecore_init_mcast_obj(sc,
5703                              &sc->mcast_obj,
5704                              sc->fp[0].cl_id,
5705                              sc->fp[0].index,
5706                              SC_FUNC(sc),
5707                              SC_FUNC(sc),
5708                              BNX2X_SP(sc, mcast_rdata),
5709                              (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5710                              ECORE_FILTER_MCAST_PENDING,
5711                              &sc->sp_state, o_type);
5712
5713         /* Setup CAM credit pools */
5714         ecore_init_mac_credit_pool(sc,
5715                                    &sc->macs_pool,
5716                                    SC_FUNC(sc),
5717                                    CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5718                                    VNICS_PER_PATH(sc));
5719
5720         ecore_init_vlan_credit_pool(sc,
5721                                     &sc->vlans_pool,
5722                                     SC_ABS_FUNC(sc) >> 1,
5723                                     CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5724                                     VNICS_PER_PATH(sc));
5725
5726         /* RSS configuration object */
5727         ecore_init_rss_config_obj(&sc->rss_conf_obj,
5728                                   sc->fp[0].cl_id,
5729                                   sc->fp[0].index,
5730                                   SC_FUNC(sc),
5731                                   SC_FUNC(sc),
5732                                   BNX2X_SP(sc, rss_rdata),
5733                                   (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5734                                   ECORE_FILTER_RSS_CONF_PENDING,
5735                                   &sc->sp_state, ECORE_OBJ_TYPE_RX);
5736 }
5737
5738 /*
5739  * Initialize the function. This must be called before sending CLIENT_SETUP
5740  * for the first client.
5741  */
5742 static int bnx2x_func_start(struct bnx2x_softc *sc)
5743 {
5744         struct ecore_func_state_params func_params = { NULL };
5745         struct ecore_func_start_params *start_params =
5746             &func_params.params.start;
5747
5748         /* Prepare parameters for function state transitions */
5749         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5750
5751         func_params.f_obj = &sc->func_obj;
5752         func_params.cmd = ECORE_F_CMD_START;
5753
5754         /* Function parameters */
5755         start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5756         start_params->sd_vlan_tag = OVLAN(sc);
5757
5758         if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5759                 start_params->network_cos_mode = STATIC_COS;
5760         } else {                /* CHIP_IS_E1X */
5761                 start_params->network_cos_mode = FW_WRR;
5762         }
5763
5764         start_params->gre_tunnel_mode = 0;
5765         start_params->gre_tunnel_rss = 0;
5766
5767         return ecore_func_state_change(sc, &func_params);
5768 }
5769
5770 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5771 {
5772         uint16_t pmcsr;
5773
5774         /* If there is no power capability, silently succeed */
5775         if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5776                 PMD_DRV_LOG(WARNING, sc, "No power capability");
5777                 return 0;
5778         }
5779
5780         pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5781                  2);
5782
5783         switch (state) {
5784         case PCI_PM_D0:
5785                 pci_write_word(sc,
5786                                (sc->devinfo.pcie_pm_cap_reg +
5787                                 PCIR_POWER_STATUS),
5788                                ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5789
5790                 if (pmcsr & PCIM_PSTAT_DMASK) {
5791                         /* delay required during transition out of D3hot */
5792                         DELAY(20000);
5793                 }
5794
5795                 break;
5796
5797         case PCI_PM_D3hot:
5798                 /* don't shut down the power for emulation and FPGA */
5799                 if (CHIP_REV_IS_SLOW(sc)) {
5800                         return 0;
5801                 }
5802
5803                 pmcsr &= ~PCIM_PSTAT_DMASK;
5804                 pmcsr |= PCIM_PSTAT_D3;
5805
5806                 if (sc->wol) {
5807                         pmcsr |= PCIM_PSTAT_PMEENABLE;
5808                 }
5809
5810                 pci_write_long(sc,
5811                                (sc->devinfo.pcie_pm_cap_reg +
5812                                 PCIR_POWER_STATUS), pmcsr);
5813
5814                 /*
5815                  * No more memory access after this point until device is brought back
5816                  * to D0 state.
5817                  */
5818                 break;
5819
5820         default:
5821                 PMD_DRV_LOG(NOTICE, sc, "Can't support PCI power state = %d",
5822                             state);
5823                 return -1;
5824         }
5825
5826         return 0;
5827 }
5828
5829 /* return true if succeeded to acquire the lock */
5830 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5831 {
5832         uint32_t lock_status;
5833         uint32_t resource_bit = (1 << resource);
5834         int func = SC_FUNC(sc);
5835         uint32_t hw_lock_control_reg;
5836
5837         /* Validating that the resource is within range */
5838         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5839                 PMD_DRV_LOG(INFO, sc,
5840                             "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5841                             resource, HW_LOCK_MAX_RESOURCE_VALUE);
5842                 return FALSE;
5843         }
5844
5845         if (func <= 5) {
5846                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5847         } else {
5848                 hw_lock_control_reg =
5849                     (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5850         }
5851
5852         /* try to acquire the lock */
5853         REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5854         lock_status = REG_RD(sc, hw_lock_control_reg);
5855         if (lock_status & resource_bit) {
5856                 return TRUE;
5857         }
5858
5859         PMD_DRV_LOG(NOTICE, sc, "Failed to get a resource lock 0x%x", resource);
5860
5861         return FALSE;
5862 }
5863
5864 /*
5865  * Get the recovery leader resource id according to the engine this function
5866  * belongs to. Currently only only 2 engines is supported.
5867  */
5868 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5869 {
5870         if (SC_PATH(sc)) {
5871                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5872         } else {
5873                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5874         }
5875 }
5876
5877 /* try to acquire a leader lock for current engine */
5878 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5879 {
5880         return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5881 }
5882
5883 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5884 {
5885         return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5886 }
5887
5888 /* close gates #2, #3 and #4 */
5889 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5890 {
5891         uint32_t val;
5892
5893         /* gates #2 and #4a are closed/opened */
5894         /* #4 */
5895         REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5896         /* #2 */
5897         REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5898
5899         /* #3 */
5900         if (CHIP_IS_E1x(sc)) {
5901 /* prevent interrupts from HC on both ports */
5902                 val = REG_RD(sc, HC_REG_CONFIG_1);
5903                 if (close)
5904                         REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5905                                                      HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5906                 else
5907                         REG_WR(sc, HC_REG_CONFIG_1,
5908                                (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5909
5910                 val = REG_RD(sc, HC_REG_CONFIG_0);
5911                 if (close)
5912                         REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5913                                                      HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5914                 else
5915                         REG_WR(sc, HC_REG_CONFIG_0,
5916                                (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5917
5918         } else {
5919 /* Prevent incoming interrupts in IGU */
5920                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5921
5922                 if (close)
5923                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5924                                (val & ~(uint32_t)
5925                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5926                 else
5927                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5928                                (val |
5929                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5930         }
5931
5932         wmb();
5933 }
5934
5935 /* poll for pending writes bit, it should get cleared in no more than 1s */
5936 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5937 {
5938         uint32_t cnt = 1000;
5939         uint32_t pend_bits = 0;
5940
5941         do {
5942                 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5943
5944                 if (pend_bits == 0) {
5945                         break;
5946                 }
5947
5948                 DELAY(1000);
5949         } while (cnt-- > 0);
5950
5951         if (cnt <= 0) {
5952                 PMD_DRV_LOG(NOTICE, sc, "Still pending IGU requests bits=0x%08x!",
5953                             pend_bits);
5954                 return -1;
5955         }
5956
5957         return 0;
5958 }
5959
5960 #define SHARED_MF_CLP_MAGIC  0x80000000 /* 'magic' bit */
5961
5962 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5963 {
5964         /* Do some magic... */
5965         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5966         *magic_val = val & SHARED_MF_CLP_MAGIC;
5967         MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
5968 }
5969
5970 /* restore the value of the 'magic' bit */
5971 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
5972 {
5973         /* Restore the 'magic' bit value... */
5974         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5975         MFCFG_WR(sc, shared_mf_config.clp_mb,
5976                  (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
5977 }
5978
5979 /* prepare for MCP reset, takes care of CLP configurations */
5980 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5981 {
5982         uint32_t shmem;
5983         uint32_t validity_offset;
5984
5985         /* set `magic' bit in order to save MF config */
5986         bnx2x_clp_reset_prep(sc, magic_val);
5987
5988         /* get shmem offset */
5989         shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
5990         validity_offset =
5991             offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
5992
5993         /* Clear validity map flags */
5994         if (shmem > 0) {
5995                 REG_WR(sc, shmem + validity_offset, 0);
5996         }
5997 }
5998
5999 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
6000 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
6001
6002 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6003 {
6004         /* special handling for emulation and FPGA (10 times longer) */
6005         if (CHIP_REV_IS_SLOW(sc)) {
6006                 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6007         } else {
6008                 DELAY((MCP_ONE_TIMEOUT) * 1000);
6009         }
6010 }
6011
6012 /* initialize shmem_base and waits for validity signature to appear */
6013 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6014 {
6015         int cnt = 0;
6016         uint32_t val = 0;
6017
6018         do {
6019                 sc->devinfo.shmem_base =
6020                     sc->link_params.shmem_base =
6021                     REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6022
6023                 if (sc->devinfo.shmem_base) {
6024                         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6025                         if (val & SHR_MEM_VALIDITY_MB)
6026                                 return 0;
6027                 }
6028
6029                 bnx2x_mcp_wait_one(sc);
6030
6031         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6032
6033         PMD_DRV_LOG(NOTICE, sc, "BAD MCP validity signature");
6034
6035         return -1;
6036 }
6037
6038 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6039 {
6040         int rc = bnx2x_init_shmem(sc);
6041
6042         /* Restore the `magic' bit value */
6043         bnx2x_clp_reset_done(sc, magic_val);
6044
6045         return rc;
6046 }
6047
6048 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6049 {
6050         REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6051         REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6052         wmb();
6053 }
6054
6055 /*
6056  * Reset the whole chip except for:
6057  *      - PCIE core
6058  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6059  *      - IGU
6060  *      - MISC (including AEU)
6061  *      - GRC
6062  *      - RBCN, RBCP
6063  */
6064 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6065 {
6066         uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6067         uint32_t global_bits2, stay_reset2;
6068
6069         /*
6070          * Bits that have to be set in reset_mask2 if we want to reset 'global'
6071          * (per chip) blocks.
6072          */
6073         global_bits2 =
6074             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6075             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6076
6077         /*
6078          * Don't reset the following blocks.
6079          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6080          *            reset, as in 4 port device they might still be owned
6081          *            by the MCP (there is only one leader per path).
6082          */
6083         not_reset_mask1 =
6084             MISC_REGISTERS_RESET_REG_1_RST_HC |
6085             MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6086             MISC_REGISTERS_RESET_REG_1_RST_PXP;
6087
6088         not_reset_mask2 =
6089             MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6090             MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6091             MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6092             MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6093             MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6094             MISC_REGISTERS_RESET_REG_2_RST_GRC |
6095             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6096             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6097             MISC_REGISTERS_RESET_REG_2_RST_ATC |
6098             MISC_REGISTERS_RESET_REG_2_PGLC |
6099             MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6100             MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6101             MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6102             MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6103             MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6104
6105         /*
6106          * Keep the following blocks in reset:
6107          *  - all xxMACs are handled by the elink code.
6108          */
6109         stay_reset2 =
6110             MISC_REGISTERS_RESET_REG_2_XMAC |
6111             MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6112
6113         /* Full reset masks according to the chip */
6114         reset_mask1 = 0xffffffff;
6115
6116         if (CHIP_IS_E1H(sc))
6117                 reset_mask2 = 0x1ffff;
6118         else if (CHIP_IS_E2(sc))
6119                 reset_mask2 = 0xfffff;
6120         else                    /* CHIP_IS_E3 */
6121                 reset_mask2 = 0x3ffffff;
6122
6123         /* Don't reset global blocks unless we need to */
6124         if (!global)
6125                 reset_mask2 &= ~global_bits2;
6126
6127         /*
6128          * In case of attention in the QM, we need to reset PXP
6129          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6130          * because otherwise QM reset would release 'close the gates' shortly
6131          * before resetting the PXP, then the PSWRQ would send a write
6132          * request to PGLUE. Then when PXP is reset, PGLUE would try to
6133          * read the payload data from PSWWR, but PSWWR would not
6134          * respond. The write queue in PGLUE would stuck, dmae commands
6135          * would not return. Therefore it's important to reset the second
6136          * reset register (containing the
6137          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6138          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6139          * bit).
6140          */
6141         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6142                reset_mask2 & (~not_reset_mask2));
6143
6144         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6145                reset_mask1 & (~not_reset_mask1));
6146
6147         mb();
6148         wmb();
6149
6150         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6151                reset_mask2 & (~stay_reset2));
6152
6153         mb();
6154         wmb();
6155
6156         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6157         wmb();
6158 }
6159
6160 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6161 {
6162         int cnt = 1000;
6163         uint32_t val = 0;
6164         uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6165         uint32_t tags_63_32 = 0;
6166
6167         /* Empty the Tetris buffer, wait for 1s */
6168         do {
6169                 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6170                 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6171                 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6172                 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6173                 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6174                 if (CHIP_IS_E3(sc)) {
6175                         tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6176                 }
6177
6178                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6179                     ((port_is_idle_0 & 0x1) == 0x1) &&
6180                     ((port_is_idle_1 & 0x1) == 0x1) &&
6181                     (pgl_exp_rom2 == 0xffffffff) &&
6182                     (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6183                         break;
6184                 DELAY(1000);
6185         } while (cnt-- > 0);
6186
6187         if (cnt <= 0) {
6188                 PMD_DRV_LOG(NOTICE, sc,
6189                             "ERROR: Tetris buffer didn't get empty or there "
6190                             "are still outstanding read requests after 1s! "
6191                             "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6192                             "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6193                             sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6194                             pgl_exp_rom2);
6195                 return -1;
6196         }
6197
6198         mb();
6199
6200         /* Close gates #2, #3 and #4 */
6201         bnx2x_set_234_gates(sc, TRUE);
6202
6203         /* Poll for IGU VQs for 57712 and newer chips */
6204         if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6205                 return -1;
6206         }
6207
6208         /* clear "unprepared" bit */
6209         REG_WR(sc, MISC_REG_UNPREPARED, 0);
6210         mb();
6211
6212         /* Make sure all is written to the chip before the reset */
6213         wmb();
6214
6215         /*
6216          * Wait for 1ms to empty GLUE and PCI-E core queues,
6217          * PSWHST, GRC and PSWRD Tetris buffer.
6218          */
6219         DELAY(1000);
6220
6221         /* Prepare to chip reset: */
6222         /* MCP */
6223         if (global) {
6224                 bnx2x_reset_mcp_prep(sc, &val);
6225         }
6226
6227         /* PXP */
6228         bnx2x_pxp_prep(sc);
6229         mb();
6230
6231         /* reset the chip */
6232         bnx2x_process_kill_chip_reset(sc, global);
6233         mb();
6234
6235         /* Recover after reset: */
6236         /* MCP */
6237         if (global && bnx2x_reset_mcp_comp(sc, val)) {
6238                 return -1;
6239         }
6240
6241         /* Open the gates #2, #3 and #4 */
6242         bnx2x_set_234_gates(sc, FALSE);
6243
6244         return 0;
6245 }
6246
6247 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6248 {
6249         int rc = 0;
6250         uint8_t global = bnx2x_reset_is_global(sc);
6251         uint32_t load_code;
6252
6253         /*
6254          * If not going to reset MCP, load "fake" driver to reset HW while
6255          * driver is owner of the HW.
6256          */
6257         if (!global && !BNX2X_NOMCP(sc)) {
6258                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6259                                            DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6260                 if (!load_code) {
6261                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6262                         rc = -1;
6263                         goto exit_leader_reset;
6264                 }
6265
6266                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6267                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6268                         PMD_DRV_LOG(NOTICE, sc,
6269                                     "MCP unexpected response, aborting");
6270                         rc = -1;
6271                         goto exit_leader_reset2;
6272                 }
6273
6274                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6275                 if (!load_code) {
6276                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6277                         rc = -1;
6278                         goto exit_leader_reset2;
6279                 }
6280         }
6281
6282         /* try to recover after the failure */
6283         if (bnx2x_process_kill(sc, global)) {
6284                 PMD_DRV_LOG(NOTICE, sc, "Something bad occurred on engine %d!",
6285                             SC_PATH(sc));
6286                 rc = -1;
6287                 goto exit_leader_reset2;
6288         }
6289
6290         /*
6291          * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6292          * state.
6293          */
6294         bnx2x_set_reset_done(sc);
6295         if (global) {
6296                 bnx2x_clear_reset_global(sc);
6297         }
6298
6299 exit_leader_reset2:
6300
6301         /* unload "fake driver" if it was loaded */
6302         if (!global &&!BNX2X_NOMCP(sc)) {
6303                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6304                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6305         }
6306
6307 exit_leader_reset:
6308
6309         sc->is_leader = 0;
6310         bnx2x_release_leader_lock(sc);
6311
6312         mb();
6313         return rc;
6314 }
6315
6316 /*
6317  * prepare INIT transition, parameters configured:
6318  *   - HC configuration
6319  *   - Queue's CDU context
6320  */
6321 static void
6322 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6323                    struct ecore_queue_init_params *init_params)
6324 {
6325         uint8_t cos;
6326         int cxt_index, cxt_offset;
6327
6328         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6329         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6330
6331         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6332         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6333
6334         /* HC rate */
6335         init_params->rx.hc_rate =
6336             sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6337         init_params->tx.hc_rate =
6338             sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6339
6340         /* FW SB ID */
6341         init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6342
6343         /* CQ index among the SB indices */
6344         init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6345         init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6346
6347         /* set maximum number of COSs supported by this queue */
6348         init_params->max_cos = sc->max_cos;
6349
6350         /* set the context pointers queue object */
6351         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6352                 cxt_index = fp->index / ILT_PAGE_CIDS;
6353                 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6354                 init_params->cxts[cos] =
6355                     &sc->context[cxt_index].vcxt[cxt_offset].eth;
6356         }
6357 }
6358
6359 /* set flags that are common for the Tx-only and not normal connections */
6360 static unsigned long
6361 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6362 {
6363         unsigned long flags = 0;
6364
6365         /* PF driver will always initialize the Queue to an ACTIVE state */
6366         bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6367
6368         /*
6369          * tx only connections collect statistics (on the same index as the
6370          * parent connection). The statistics are zeroed when the parent
6371          * connection is initialized.
6372          */
6373
6374         bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6375         if (zero_stats) {
6376                 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6377         }
6378
6379         /*
6380          * tx only connections can support tx-switching, though their
6381          * CoS-ness doesn't survive the loopback
6382          */
6383         if (sc->flags & BNX2X_TX_SWITCHING) {
6384                 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6385         }
6386
6387         bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6388
6389         return flags;
6390 }
6391
6392 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6393 {
6394         unsigned long flags = 0;
6395
6396         if (IS_MF_SD(sc)) {
6397                 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6398         }
6399
6400         if (leading) {
6401                 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6402                 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6403         }
6404
6405         bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6406
6407         /* merge with common flags */
6408         return flags | bnx2x_get_common_flags(sc, TRUE);
6409 }
6410
6411 static void
6412 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6413                       struct ecore_general_setup_params *gen_init, uint8_t cos)
6414 {
6415         gen_init->stat_id = bnx2x_stats_id(fp);
6416         gen_init->spcl_id = fp->cl_id;
6417         gen_init->mtu = sc->mtu;
6418         gen_init->cos = cos;
6419 }
6420
6421 static void
6422 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6423                  struct rxq_pause_params *pause,
6424                  struct ecore_rxq_setup_params *rxq_init)
6425 {
6426         struct bnx2x_rx_queue *rxq;
6427
6428         rxq = sc->rx_queues[fp->index];
6429         if (!rxq) {
6430                 PMD_RX_LOG(ERR, "RX queue is NULL");
6431                 return;
6432         }
6433         /* pause */
6434         pause->bd_th_lo = BD_TH_LO(sc);
6435         pause->bd_th_hi = BD_TH_HI(sc);
6436
6437         pause->rcq_th_lo = RCQ_TH_LO(sc);
6438         pause->rcq_th_hi = RCQ_TH_HI(sc);
6439
6440         /* validate rings have enough entries to cross high thresholds */
6441         if (sc->dropless_fc &&
6442             pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6443                 PMD_DRV_LOG(WARNING, sc, "rx bd ring threshold limit");
6444         }
6445
6446         if (sc->dropless_fc &&
6447             pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6448                 PMD_DRV_LOG(WARNING, sc, "rcq ring threshold limit");
6449         }
6450
6451         pause->pri_map = 1;
6452
6453         /* rxq setup */
6454         rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr;
6455         rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr;
6456         rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr +
6457                                               BNX2X_PAGE_SIZE);
6458
6459         /*
6460          * This should be a maximum number of data bytes that may be
6461          * placed on the BD (not including paddings).
6462          */
6463         rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6464
6465         rxq_init->cl_qzone_id = fp->cl_qzone_id;
6466         rxq_init->rss_engine_id = SC_FUNC(sc);
6467         rxq_init->mcast_engine_id = SC_FUNC(sc);
6468
6469         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6470         rxq_init->fw_sb_id = fp->fw_sb_id;
6471
6472         rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6473
6474         /*
6475          * configure silent vlan removal
6476          * if multi function mode is afex, then mask default vlan
6477          */
6478         if (IS_MF_AFEX(sc)) {
6479                 rxq_init->silent_removal_value =
6480                     sc->devinfo.mf_info.afex_def_vlan_tag;
6481                 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6482         }
6483 }
6484
6485 static void
6486 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6487                  struct ecore_txq_setup_params *txq_init, uint8_t cos)
6488 {
6489         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6490
6491         if (!txq) {
6492                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6493                 return;
6494         }
6495         txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr;
6496         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6497         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6498         txq_init->fw_sb_id = fp->fw_sb_id;
6499
6500         /*
6501          * set the TSS leading client id for TX classfication to the
6502          * leading RSS client id
6503          */
6504         txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6505 }
6506
6507 /*
6508  * This function performs 2 steps in a queue state machine:
6509  *   1) RESET->INIT
6510  *   2) INIT->SETUP
6511  */
6512 static int
6513 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6514 {
6515         struct ecore_queue_state_params q_params = { NULL };
6516         struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6517         int rc;
6518
6519         PMD_DRV_LOG(DEBUG, sc, "setting up queue %d", fp->index);
6520
6521         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6522
6523         q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6524
6525         /* we want to wait for completion in this context */
6526         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6527
6528         /* prepare the INIT parameters */
6529         bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6530
6531         /* Set the command */
6532         q_params.cmd = ECORE_Q_CMD_INIT;
6533
6534         /* Change the state to INIT */
6535         rc = ecore_queue_state_change(sc, &q_params);
6536         if (rc) {
6537                 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) INIT failed", fp->index);
6538                 return rc;
6539         }
6540
6541         PMD_DRV_LOG(DEBUG, sc, "init complete");
6542
6543         /* now move the Queue to the SETUP state */
6544         memset(setup_params, 0, sizeof(*setup_params));
6545
6546         /* set Queue flags */
6547         setup_params->flags = bnx2x_get_q_flags(sc, leading);
6548
6549         /* set general SETUP parameters */
6550         bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6551                               FIRST_TX_COS_INDEX);
6552
6553         bnx2x_pf_rx_q_prep(sc, fp,
6554                          &setup_params->pause_params,
6555                          &setup_params->rxq_params);
6556
6557         bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6558
6559         /* Set the command */
6560         q_params.cmd = ECORE_Q_CMD_SETUP;
6561
6562         /* change the state to SETUP */
6563         rc = ecore_queue_state_change(sc, &q_params);
6564         if (rc) {
6565                 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) SETUP failed", fp->index);
6566                 return rc;
6567         }
6568
6569         return rc;
6570 }
6571
6572 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6573 {
6574         if (IS_PF(sc))
6575                 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6576         else                    /* VF */
6577                 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6578 }
6579
6580 static int
6581 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6582                   uint8_t config_hash)
6583 {
6584         struct ecore_config_rss_params params = { NULL };
6585         uint32_t i;
6586
6587         /*
6588          * Although RSS is meaningless when there is a single HW queue we
6589          * still need it enabled in order to have HW Rx hash generated.
6590          */
6591
6592         params.rss_obj = rss_obj;
6593
6594         bnx2x_set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
6595
6596         bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, &params.rss_flags);
6597
6598         /* RSS configuration */
6599         bnx2x_set_bit(ECORE_RSS_IPV4, &params.rss_flags);
6600         bnx2x_set_bit(ECORE_RSS_IPV4_TCP, &params.rss_flags);
6601         bnx2x_set_bit(ECORE_RSS_IPV6, &params.rss_flags);
6602         bnx2x_set_bit(ECORE_RSS_IPV6_TCP, &params.rss_flags);
6603         if (rss_obj->udp_rss_v4) {
6604                 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, &params.rss_flags);
6605         }
6606         if (rss_obj->udp_rss_v6) {
6607                 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, &params.rss_flags);
6608         }
6609
6610         /* Hash bits */
6611         params.rss_result_mask = MULTI_MASK;
6612
6613         rte_memcpy(params.ind_table, rss_obj->ind_table,
6614                          sizeof(params.ind_table));
6615
6616         if (config_hash) {
6617 /* RSS keys */
6618                 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6619                         params.rss_key[i] = (uint32_t) rte_rand();
6620                 }
6621
6622                 bnx2x_set_bit(ECORE_RSS_SET_SRCH, &params.rss_flags);
6623         }
6624
6625         if (IS_PF(sc))
6626                 return ecore_config_rss(sc, &params);
6627         else
6628                 return bnx2x_vf_config_rss(sc, &params);
6629 }
6630
6631 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6632 {
6633         return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6634 }
6635
6636 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6637 {
6638         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6639         uint32_t i;
6640
6641         /*
6642          * Prepare the initial contents of the indirection table if
6643          * RSS is enabled
6644          */
6645         for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6646                 sc->rss_conf_obj.ind_table[i] =
6647                     (sc->fp->cl_id + (i % num_eth_queues));
6648         }
6649
6650         if (sc->udp_rss) {
6651                 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6652         }
6653
6654         /*
6655          * For 57711 SEARCHER configuration (rss_keys) is
6656          * per-port, so if explicit configuration is needed, do it only
6657          * for a PMF.
6658          *
6659          * For 57712 and newer it's a per-function configuration.
6660          */
6661         return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6662 }
6663
6664 static int
6665 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6666                 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6667                 unsigned long *ramrod_flags)
6668 {
6669         struct ecore_vlan_mac_ramrod_params ramrod_param;
6670         int rc;
6671
6672         memset(&ramrod_param, 0, sizeof(ramrod_param));
6673
6674         /* fill in general parameters */
6675         ramrod_param.vlan_mac_obj = obj;
6676         ramrod_param.ramrod_flags = *ramrod_flags;
6677
6678         /* fill a user request section if needed */
6679         if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6680                 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6681                                  ETH_ALEN);
6682
6683                 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6684
6685 /* Set the command: ADD or DEL */
6686                 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6687                     ECORE_VLAN_MAC_DEL;
6688         }
6689
6690         rc = ecore_config_vlan_mac(sc, &ramrod_param);
6691
6692         if (rc == ECORE_EXISTS) {
6693                 PMD_DRV_LOG(INFO, sc, "Failed to schedule ADD operations (EEXIST)");
6694 /* do not treat adding same MAC as error */
6695                 rc = 0;
6696         } else if (rc < 0) {
6697                 PMD_DRV_LOG(ERR, sc,
6698                             "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6699         }
6700
6701         return rc;
6702 }
6703
6704 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6705 {
6706         unsigned long ramrod_flags = 0;
6707
6708         PMD_DRV_LOG(DEBUG, sc, "Adding Ethernet MAC");
6709
6710         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6711
6712         /* Eth MAC is set on RSS leading client (fp[0]) */
6713         return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6714                                &sc->sp_objs->mac_obj,
6715                                set, ECORE_ETH_MAC, &ramrod_flags);
6716 }
6717
6718 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6719 {
6720         uint32_t sel_phy_idx = 0;
6721
6722         if (sc->link_params.num_phys <= 1) {
6723                 return ELINK_INT_PHY;
6724         }
6725
6726         if (sc->link_vars.link_up) {
6727                 sel_phy_idx = ELINK_EXT_PHY1;
6728 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6729                 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6730                     (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6731                      ELINK_SUPPORTED_FIBRE))
6732                         sel_phy_idx = ELINK_EXT_PHY2;
6733         } else {
6734                 switch (elink_phy_selection(&sc->link_params)) {
6735                 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6736                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6737                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6738                         sel_phy_idx = ELINK_EXT_PHY1;
6739                         break;
6740                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6741                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6742                         sel_phy_idx = ELINK_EXT_PHY2;
6743                         break;
6744                 }
6745         }
6746
6747         return sel_phy_idx;
6748 }
6749
6750 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6751 {
6752         uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6753
6754         /*
6755          * The selected activated PHY is always after swapping (in case PHY
6756          * swapping is enabled). So when swapping is enabled, we need to reverse
6757          * the configuration
6758          */
6759
6760         if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6761                 if (sel_phy_idx == ELINK_EXT_PHY1)
6762                         sel_phy_idx = ELINK_EXT_PHY2;
6763                 else if (sel_phy_idx == ELINK_EXT_PHY2)
6764                         sel_phy_idx = ELINK_EXT_PHY1;
6765         }
6766
6767         return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6768 }
6769
6770 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6771 {
6772         /*
6773          * Initialize link parameters structure variables
6774          * It is recommended to turn off RX FC for jumbo frames
6775          * for better performance
6776          */
6777         if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6778                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6779         } else {
6780                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6781         }
6782 }
6783
6784 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6785 {
6786         uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6787         switch (sc->link_vars.ieee_fc &
6788                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6789         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6790         default:
6791                 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6792                                                    ADVERTISED_Pause);
6793                 break;
6794
6795         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6796                 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6797                                                   ADVERTISED_Pause);
6798                 break;
6799
6800         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6801                 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6802                 break;
6803         }
6804 }
6805
6806 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6807 {
6808         uint16_t line_speed = sc->link_vars.line_speed;
6809         if (IS_MF(sc)) {
6810                 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6811                                                       sc->devinfo.
6812                                                       mf_info.mf_config[SC_VN
6813                                                                         (sc)]);
6814
6815 /* calculate the current MAX line speed limit for the MF devices */
6816                 if (IS_MF_SI(sc)) {
6817                         line_speed = (line_speed * maxCfg) / 100;
6818                 } else {        /* SD mode */
6819                         uint16_t vn_max_rate = maxCfg * 100;
6820
6821                         if (vn_max_rate < line_speed) {
6822                                 line_speed = vn_max_rate;
6823                         }
6824                 }
6825         }
6826
6827         return line_speed;
6828 }
6829
6830 static void
6831 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6832 {
6833         uint16_t line_speed = bnx2x_get_mf_speed(sc);
6834
6835         memset(data, 0, sizeof(*data));
6836
6837         /* fill the report data with the effective line speed */
6838         data->line_speed = line_speed;
6839
6840         /* Link is down */
6841         if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6842                 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6843                             &data->link_report_flags);
6844         }
6845
6846         /* Full DUPLEX */
6847         if (sc->link_vars.duplex == DUPLEX_FULL) {
6848                 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6849                             &data->link_report_flags);
6850         }
6851
6852         /* Rx Flow Control is ON */
6853         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6854                 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6855         }
6856
6857         /* Tx Flow Control is ON */
6858         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6859                 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6860         }
6861 }
6862
6863 /* report link status to OS, should be called under phy_lock */
6864 static void bnx2x_link_report(struct bnx2x_softc *sc)
6865 {
6866         struct bnx2x_link_report_data cur_data;
6867
6868         /* reread mf_cfg */
6869         if (IS_PF(sc)) {
6870                 bnx2x_read_mf_cfg(sc);
6871         }
6872
6873         /* Read the current link report info */
6874         bnx2x_fill_report_data(sc, &cur_data);
6875
6876         /* Don't report link down or exactly the same link status twice */
6877         if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6878             (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6879                           &sc->last_reported_link.link_report_flags) &&
6880              bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6881                           &cur_data.link_report_flags))) {
6882                 return;
6883         }
6884
6885         sc->link_cnt++;
6886
6887         /* report new link params and remember the state for the next time */
6888         rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6889
6890         if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6891                          &cur_data.link_report_flags)) {
6892                 PMD_DRV_LOG(INFO, sc, "NIC Link is Down");
6893         } else {
6894                 __rte_unused const char *duplex;
6895                 __rte_unused const char *flow;
6896
6897                 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6898                                            &cur_data.link_report_flags)) {
6899                         duplex = "full";
6900                 } else {
6901                         duplex = "half";
6902                 }
6903
6904 /*
6905  * Handle the FC at the end so that only these flags would be
6906  * possibly set. This way we may easily check if there is no FC
6907  * enabled.
6908  */
6909                 if (cur_data.link_report_flags) {
6910                         if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6911                                          &cur_data.link_report_flags) &&
6912                             bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6913                                          &cur_data.link_report_flags)) {
6914                                 flow = "ON - receive & transmit";
6915                         } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6916                                                 &cur_data.link_report_flags) &&
6917                                    !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6918                                                  &cur_data.link_report_flags)) {
6919                                 flow = "ON - receive";
6920                         } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6921                                                  &cur_data.link_report_flags) &&
6922                                    bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6923                                                 &cur_data.link_report_flags)) {
6924                                 flow = "ON - transmit";
6925                         } else {
6926                                 flow = "none";  /* possible? */
6927                         }
6928                 } else {
6929                         flow = "none";
6930                 }
6931
6932                 PMD_DRV_LOG(INFO, sc,
6933                             "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6934                             cur_data.line_speed, duplex, flow);
6935         }
6936 }
6937
6938 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6939 {
6940         if (sc->state != BNX2X_STATE_OPEN) {
6941                 return;
6942         }
6943
6944         if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
6945                 elink_link_status_update(&sc->link_params, &sc->link_vars);
6946         } else {
6947                 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
6948                                           ELINK_SUPPORTED_10baseT_Full |
6949                                           ELINK_SUPPORTED_100baseT_Half |
6950                                           ELINK_SUPPORTED_100baseT_Full |
6951                                           ELINK_SUPPORTED_1000baseT_Full |
6952                                           ELINK_SUPPORTED_2500baseX_Full |
6953                                           ELINK_SUPPORTED_10000baseT_Full |
6954                                           ELINK_SUPPORTED_TP |
6955                                           ELINK_SUPPORTED_FIBRE |
6956                                           ELINK_SUPPORTED_Autoneg |
6957                                           ELINK_SUPPORTED_Pause |
6958                                           ELINK_SUPPORTED_Asym_Pause);
6959                 sc->port.advertising[0] = sc->port.supported[0];
6960
6961                 sc->link_params.sc = sc;
6962                 sc->link_params.port = SC_PORT(sc);
6963                 sc->link_params.req_duplex[0] = DUPLEX_FULL;
6964                 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
6965                 sc->link_params.req_line_speed[0] = SPEED_10000;
6966                 sc->link_params.speed_cap_mask[0] = 0x7f0000;
6967                 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
6968
6969                 if (CHIP_REV_IS_FPGA(sc)) {
6970                         sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
6971                         sc->link_vars.line_speed = ELINK_SPEED_1000;
6972                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6973                                                      LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
6974                 } else {
6975                         sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
6976                         sc->link_vars.line_speed = ELINK_SPEED_10000;
6977                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6978                                                      LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
6979                 }
6980
6981                 sc->link_vars.link_up = 1;
6982
6983                 sc->link_vars.duplex = DUPLEX_FULL;
6984                 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
6985
6986                 if (IS_PF(sc)) {
6987                         REG_WR(sc,
6988                                NIG_REG_EGRESS_DRAIN0_MODE +
6989                                sc->link_params.port * 4, 0);
6990                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6991                         bnx2x_link_report(sc);
6992                 }
6993         }
6994
6995         if (IS_PF(sc)) {
6996                 if (sc->link_vars.link_up) {
6997                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6998                 } else {
6999                         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7000                 }
7001                 bnx2x_link_report(sc);
7002         } else {
7003                 bnx2x_link_report(sc);
7004                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7005         }
7006 }
7007
7008 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7009 {
7010         int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7011         uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7012         struct elink_params *lp = &sc->link_params;
7013
7014         bnx2x_set_requested_fc(sc);
7015
7016         if (load_mode == LOAD_DIAG) {
7017                 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7018 /* Prefer doing PHY loopback at 10G speed, if possible */
7019                 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7020                         if (lp->speed_cap_mask[cfg_idx] &
7021                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7022                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7023                         } else {
7024                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7025                         }
7026                 }
7027         }
7028
7029         if (load_mode == LOAD_LOOPBACK_EXT) {
7030                 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7031         }
7032
7033         rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7034
7035         bnx2x_calc_fc_adv(sc);
7036
7037         if (sc->link_vars.link_up) {
7038                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7039                 bnx2x_link_report(sc);
7040         }
7041
7042         sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7043         return rc;
7044 }
7045
7046 /* update flags in shmem */
7047 static void
7048 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7049 {
7050         uint32_t drv_flags;
7051
7052         if (SHMEM2_HAS(sc, drv_flags)) {
7053                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7054                 drv_flags = SHMEM2_RD(sc, drv_flags);
7055
7056                 if (set) {
7057                         drv_flags |= flags;
7058                 } else {
7059                         drv_flags &= ~flags;
7060                 }
7061
7062                 SHMEM2_WR(sc, drv_flags, drv_flags);
7063
7064                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7065         }
7066 }
7067
7068 /* periodic timer callout routine, only runs when the interface is up */
7069 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7070 {
7071         if ((sc->state != BNX2X_STATE_OPEN) ||
7072             (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7073                 PMD_DRV_LOG(INFO, sc, "periodic callout exit (state=0x%x)",
7074                             sc->state);
7075                 return;
7076         }
7077         if (!CHIP_REV_IS_SLOW(sc)) {
7078 /*
7079  * This barrier is needed to ensure the ordering between the writing
7080  * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7081  * the reading here.
7082  */
7083                 mb();
7084                 if (sc->port.pmf) {
7085                         elink_period_func(&sc->link_params, &sc->link_vars);
7086                 }
7087         }
7088 #ifdef BNX2X_PULSE
7089         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7090                 int mb_idx = SC_FW_MB_IDX(sc);
7091                 uint32_t drv_pulse;
7092                 uint32_t mcp_pulse;
7093
7094                 ++sc->fw_drv_pulse_wr_seq;
7095                 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7096
7097                 drv_pulse = sc->fw_drv_pulse_wr_seq;
7098                 bnx2x_drv_pulse(sc);
7099
7100                 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7101                              MCP_PULSE_SEQ_MASK);
7102
7103 /*
7104  * The delta between driver pulse and mcp response should
7105  * be 1 (before mcp response) or 0 (after mcp response).
7106  */
7107                 if ((drv_pulse != mcp_pulse) &&
7108                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7109                         /* someone lost a heartbeat... */
7110                         PMD_DRV_LOG(ERR, sc,
7111                                     "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7112                                     drv_pulse, mcp_pulse);
7113                 }
7114         }
7115 #endif
7116 }
7117
7118 /* start the controller */
7119 static __rte_noinline
7120 int bnx2x_nic_load(struct bnx2x_softc *sc)
7121 {
7122         uint32_t val;
7123         uint32_t load_code = 0;
7124         int i, rc = 0;
7125
7126         PMD_INIT_FUNC_TRACE(sc);
7127
7128         sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7129
7130         if (IS_PF(sc)) {
7131 /* must be called before memory allocation and HW init */
7132                 bnx2x_ilt_set_info(sc);
7133         }
7134
7135         bnx2x_set_fp_rx_buf_size(sc);
7136
7137         if (IS_PF(sc)) {
7138                 if (bnx2x_alloc_mem(sc) != 0) {
7139                         sc->state = BNX2X_STATE_CLOSED;
7140                         rc = -ENOMEM;
7141                         goto bnx2x_nic_load_error0;
7142                 }
7143         }
7144
7145         if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7146                 sc->state = BNX2X_STATE_CLOSED;
7147                 rc = -ENOMEM;
7148                 goto bnx2x_nic_load_error0;
7149         }
7150
7151         if (IS_VF(sc)) {
7152                 rc = bnx2x_vf_init(sc);
7153                 if (rc) {
7154                         sc->state = BNX2X_STATE_ERROR;
7155                         goto bnx2x_nic_load_error0;
7156                 }
7157         }
7158
7159         if (IS_PF(sc)) {
7160 /* set pf load just before approaching the MCP */
7161                 bnx2x_set_pf_load(sc);
7162
7163 /* if MCP exists send load request and analyze response */
7164                 if (!BNX2X_NOMCP(sc)) {
7165                         /* attempt to load pf */
7166                         if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7167                                 sc->state = BNX2X_STATE_CLOSED;
7168                                 rc = -ENXIO;
7169                                 goto bnx2x_nic_load_error1;
7170                         }
7171
7172                         /* what did the MCP say? */
7173                         if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7174                                 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7175                                 sc->state = BNX2X_STATE_CLOSED;
7176                                 rc = -ENXIO;
7177                                 goto bnx2x_nic_load_error2;
7178                         }
7179                 } else {
7180                         PMD_DRV_LOG(INFO, sc, "Device has no MCP!");
7181                         load_code = bnx2x_nic_load_no_mcp(sc);
7182                 }
7183
7184 /* mark PMF if applicable */
7185                 bnx2x_nic_load_pmf(sc, load_code);
7186
7187 /* Init Function state controlling object */
7188                 bnx2x_init_func_obj(sc);
7189
7190 /* Initialize HW */
7191                 if (bnx2x_init_hw(sc, load_code) != 0) {
7192                         PMD_DRV_LOG(NOTICE, sc, "HW init failed");
7193                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7194                         sc->state = BNX2X_STATE_CLOSED;
7195                         rc = -ENXIO;
7196                         goto bnx2x_nic_load_error2;
7197                 }
7198         }
7199
7200         bnx2x_nic_init(sc, load_code);
7201
7202         /* Init per-function objects */
7203         if (IS_PF(sc)) {
7204                 bnx2x_init_objs(sc);
7205
7206 /* set AFEX default VLAN tag to an invalid value */
7207                 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7208
7209                 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7210                 rc = bnx2x_func_start(sc);
7211                 if (rc) {
7212                         PMD_DRV_LOG(NOTICE, sc, "Function start failed!");
7213                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7214                         sc->state = BNX2X_STATE_ERROR;
7215                         goto bnx2x_nic_load_error3;
7216                 }
7217
7218 /* send LOAD_DONE command to MCP */
7219                 if (!BNX2X_NOMCP(sc)) {
7220                         load_code =
7221                             bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7222                         if (!load_code) {
7223                                 PMD_DRV_LOG(NOTICE, sc,
7224                                             "MCP response failure, aborting");
7225                                 sc->state = BNX2X_STATE_ERROR;
7226                                 rc = -ENXIO;
7227                                 goto bnx2x_nic_load_error3;
7228                         }
7229                 }
7230         }
7231
7232         rc = bnx2x_setup_leading(sc);
7233         if (rc) {
7234                 PMD_DRV_LOG(NOTICE, sc, "Setup leading failed!");
7235                 sc->state = BNX2X_STATE_ERROR;
7236                 goto bnx2x_nic_load_error3;
7237         }
7238
7239         FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7240                 if (IS_PF(sc))
7241                         rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7242                 else            /* IS_VF(sc) */
7243                         rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7244
7245                 if (rc) {
7246                         PMD_DRV_LOG(NOTICE, sc, "Queue(%d) setup failed", i);
7247                         sc->state = BNX2X_STATE_ERROR;
7248                         goto bnx2x_nic_load_error3;
7249                 }
7250         }
7251
7252         rc = bnx2x_init_rss_pf(sc);
7253         if (rc) {
7254                 PMD_DRV_LOG(NOTICE, sc, "PF RSS init failed");
7255                 sc->state = BNX2X_STATE_ERROR;
7256                 goto bnx2x_nic_load_error3;
7257         }
7258
7259         /* now when Clients are configured we are ready to work */
7260         sc->state = BNX2X_STATE_OPEN;
7261
7262         /* Configure a ucast MAC */
7263         if (IS_PF(sc)) {
7264                 rc = bnx2x_set_eth_mac(sc, TRUE);
7265         } else {                /* IS_VF(sc) */
7266                 rc = bnx2x_vf_set_mac(sc, TRUE);
7267         }
7268
7269         if (rc) {
7270                 PMD_DRV_LOG(NOTICE, sc, "Setting Ethernet MAC failed");
7271                 sc->state = BNX2X_STATE_ERROR;
7272                 goto bnx2x_nic_load_error3;
7273         }
7274
7275         if (sc->port.pmf) {
7276                 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7277                 if (rc) {
7278                         sc->state = BNX2X_STATE_ERROR;
7279                         goto bnx2x_nic_load_error3;
7280                 }
7281         }
7282
7283         sc->link_params.feature_config_flags &=
7284             ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7285
7286         /* start the Tx */
7287         switch (LOAD_OPEN) {
7288         case LOAD_NORMAL:
7289         case LOAD_OPEN:
7290                 break;
7291
7292         case LOAD_DIAG:
7293         case LOAD_LOOPBACK_EXT:
7294                 sc->state = BNX2X_STATE_DIAG;
7295                 break;
7296
7297         default:
7298                 break;
7299         }
7300
7301         if (sc->port.pmf) {
7302                 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7303         } else {
7304                 bnx2x_link_status_update(sc);
7305         }
7306
7307         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7308 /* mark driver is loaded in shmem2 */
7309                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7310                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7311                           (val |
7312                            DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7313                            DRV_FLAGS_CAPABILITIES_LOADED_L2));
7314         }
7315
7316         /* start fast path */
7317         /* Initialize Rx filter */
7318         bnx2x_set_rx_mode(sc);
7319
7320         /* wait for all pending SP commands to complete */
7321         if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7322                 PMD_DRV_LOG(NOTICE, sc, "Timeout waiting for all SPs to complete!");
7323                 bnx2x_periodic_stop(sc);
7324                 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7325                 return -ENXIO;
7326         }
7327
7328         PMD_DRV_LOG(DEBUG, sc, "NIC successfully loaded");
7329
7330         return 0;
7331
7332 bnx2x_nic_load_error3:
7333
7334         if (IS_PF(sc)) {
7335                 bnx2x_int_disable_sync(sc, 1);
7336
7337 /* clean out queued objects */
7338                 bnx2x_squeeze_objects(sc);
7339         }
7340
7341 bnx2x_nic_load_error2:
7342
7343         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7344                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7345                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7346         }
7347
7348         sc->port.pmf = 0;
7349
7350 bnx2x_nic_load_error1:
7351
7352         /* clear pf_load status, as it was already set */
7353         if (IS_PF(sc)) {
7354                 bnx2x_clear_pf_load(sc);
7355         }
7356
7357 bnx2x_nic_load_error0:
7358
7359         bnx2x_free_fw_stats_mem(sc);
7360         bnx2x_free_mem(sc);
7361
7362         return rc;
7363 }
7364
7365 /*
7366 * Handles controller initialization.
7367 */
7368 int bnx2x_init(struct bnx2x_softc *sc)
7369 {
7370         int other_engine = SC_PATH(sc) ? 0 : 1;
7371         uint8_t other_load_status, load_status;
7372         uint8_t global = FALSE;
7373         int rc;
7374
7375         /* Check if the driver is still running and bail out if it is. */
7376         if (sc->state != BNX2X_STATE_CLOSED) {
7377                 PMD_DRV_LOG(DEBUG, sc, "Init called while driver is running!");
7378                 rc = 0;
7379                 goto bnx2x_init_done;
7380         }
7381
7382         bnx2x_set_power_state(sc, PCI_PM_D0);
7383
7384         /*
7385          * If parity occurred during the unload, then attentions and/or
7386          * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7387          * loaded on the current engine to complete the recovery. Parity recovery
7388          * is only relevant for PF driver.
7389          */
7390         if (IS_PF(sc)) {
7391                 other_load_status = bnx2x_get_load_status(sc, other_engine);
7392                 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7393
7394                 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7395                     bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7396                         do {
7397                                 /*
7398                                  * If there are attentions and they are in global blocks, set
7399                                  * the GLOBAL_RESET bit regardless whether it will be this
7400                                  * function that will complete the recovery or not.
7401                                  */
7402                                 if (global) {
7403                                         bnx2x_set_reset_global(sc);
7404                                 }
7405
7406                                 /*
7407                                  * Only the first function on the current engine should try
7408                                  * to recover in open. In case of attentions in global blocks
7409                                  * only the first in the chip should try to recover.
7410                                  */
7411                                 if ((!load_status
7412                                      && (!global ||!other_load_status))
7413                                     && bnx2x_trylock_leader_lock(sc)
7414                                     && !bnx2x_leader_reset(sc)) {
7415                                         PMD_DRV_LOG(INFO, sc,
7416                                                     "Recovered during init");
7417                                         break;
7418                                 }
7419
7420                                 /* recovery has failed... */
7421                                 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7422
7423                                 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7424
7425                                 PMD_DRV_LOG(NOTICE, sc,
7426                                             "Recovery flow hasn't properly "
7427                                             "completed yet, try again later. "
7428                                             "If you still see this message after a "
7429                                             "few retries then power cycle is required.");
7430
7431                                 rc = -ENXIO;
7432                                 goto bnx2x_init_done;
7433                         } while (0);
7434                 }
7435         }
7436
7437         sc->recovery_state = BNX2X_RECOVERY_DONE;
7438
7439         rc = bnx2x_nic_load(sc);
7440
7441 bnx2x_init_done:
7442
7443         if (rc) {
7444                 PMD_DRV_LOG(NOTICE, sc, "Initialization failed, "
7445                             "stack notified driver is NOT running!");
7446         }
7447
7448         return rc;
7449 }
7450
7451 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7452 {
7453         uint32_t val = 0;
7454
7455         /*
7456          * Read the ME register to get the function number. The ME register
7457          * holds the relative-function number and absolute-function number. The
7458          * absolute-function number appears only in E2 and above. Before that
7459          * these bits always contained zero, therefore we cannot blindly use them.
7460          */
7461
7462         val = REG_RD(sc, BAR_ME_REGISTER);
7463
7464         sc->pfunc_rel =
7465             (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7466         sc->path_id =
7467             (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7468             1;
7469
7470         if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7471                 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7472         } else {
7473                 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7474         }
7475
7476         PMD_DRV_LOG(DEBUG, sc,
7477                     "Relative function %d, Absolute function %d, Path %d",
7478                     sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7479 }
7480
7481 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7482 {
7483         uint32_t shmem2_size;
7484         uint32_t offset;
7485         uint32_t mf_cfg_offset_value;
7486
7487         /* Non 57712 */
7488         offset = (SHMEM_ADDR(sc, func_mb) +
7489                   (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7490
7491         /* 57712 plus */
7492         if (sc->devinfo.shmem2_base != 0) {
7493                 shmem2_size = SHMEM2_RD(sc, size);
7494                 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7495                         mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7496                         if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7497                                 offset = mf_cfg_offset_value;
7498                         }
7499                 }
7500         }
7501
7502         return offset;
7503 }
7504
7505 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7506 {
7507         uint32_t ret;
7508         struct bnx2x_pci_cap *caps;
7509
7510         /* ensure PCIe capability is enabled */
7511         caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7512         if (NULL != caps) {
7513                 PMD_DRV_LOG(DEBUG, sc, "Found PCIe capability: "
7514                             "id=0x%04X type=0x%04X addr=0x%08X",
7515                             caps->id, caps->type, caps->addr);
7516                 pci_read(sc, (caps->addr + reg), &ret, 2);
7517                 return ret;
7518         }
7519
7520         PMD_DRV_LOG(WARNING, sc, "PCIe capability NOT FOUND!!!");
7521
7522         return 0;
7523 }
7524
7525 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7526 {
7527         return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7528                 PCIM_EXP_STA_TRANSACTION_PND;
7529 }
7530
7531 /*
7532 * Walk the PCI capabiites list for the device to find what features are
7533 * supported. These capabilites may be enabled/disabled by firmware so it's
7534 * best to walk the list rather than make assumptions.
7535 */
7536 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7537 {
7538         PMD_INIT_FUNC_TRACE(sc);
7539
7540         struct bnx2x_pci_cap *caps;
7541         uint16_t link_status;
7542         int reg = 0;
7543
7544         /* check if PCI Power Management is enabled */
7545         caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7546         if (NULL != caps) {
7547                 PMD_DRV_LOG(DEBUG, sc, "Found PM capability: "
7548                             "id=0x%04X type=0x%04X addr=0x%08X",
7549                             caps->id, caps->type, caps->addr);
7550
7551                 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7552                 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7553         }
7554
7555         link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7556
7557         sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7558         sc->devinfo.pcie_link_width =
7559             ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7560
7561         PMD_DRV_LOG(DEBUG, sc, "PCIe link speed=%d width=%d",
7562                     sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7563
7564         sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7565
7566         /* check if MSI capability is enabled */
7567         caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7568         if (NULL != caps) {
7569                 PMD_DRV_LOG(DEBUG, sc, "Found MSI capability at 0x%04x", reg);
7570
7571                 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7572                 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7573         }
7574
7575         /* check if MSI-X capability is enabled */
7576         caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7577         if (NULL != caps) {
7578                 PMD_DRV_LOG(DEBUG, sc, "Found MSI-X capability at 0x%04x", reg);
7579
7580                 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7581                 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7582         }
7583 }
7584
7585 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7586 {
7587         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7588         uint32_t val;
7589
7590         /* get the outer vlan if we're in switch-dependent mode */
7591
7592         val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7593         mf_info->ext_id = (uint16_t) val;
7594
7595         mf_info->multi_vnics_mode = 1;
7596
7597         if (!VALID_OVLAN(mf_info->ext_id)) {
7598                 PMD_DRV_LOG(NOTICE, sc, "Invalid VLAN (%d)", mf_info->ext_id);
7599                 return 1;
7600         }
7601
7602         /* get the capabilities */
7603         if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7604             FUNC_MF_CFG_PROTOCOL_ISCSI) {
7605                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7606         } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7607                    == FUNC_MF_CFG_PROTOCOL_FCOE) {
7608                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7609         } else {
7610                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7611         }
7612
7613         mf_info->vnics_per_port =
7614             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7615
7616         return 0;
7617 }
7618
7619 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7620 {
7621         uint32_t retval = 0;
7622         uint32_t val;
7623
7624         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7625
7626         if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7627                 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7628                         retval |= MF_PROTO_SUPPORT_ETHERNET;
7629                 }
7630                 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7631                         retval |= MF_PROTO_SUPPORT_ISCSI;
7632                 }
7633                 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7634                         retval |= MF_PROTO_SUPPORT_FCOE;
7635                 }
7636         }
7637
7638         return retval;
7639 }
7640
7641 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7642 {
7643         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7644         uint32_t val;
7645
7646         /*
7647          * There is no outer vlan if we're in switch-independent mode.
7648          * If the mac is valid then assume multi-function.
7649          */
7650
7651         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7652
7653         mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7654
7655         mf_info->mf_protos_supported =
7656             bnx2x_get_shmem_ext_proto_support_flags(sc);
7657
7658         mf_info->vnics_per_port =
7659             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7660
7661         return 0;
7662 }
7663
7664 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7665 {
7666         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7667         uint32_t e1hov_tag;
7668         uint32_t func_config;
7669         uint32_t niv_config;
7670
7671         mf_info->multi_vnics_mode = 1;
7672
7673         e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7674         func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7675         niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7676
7677         mf_info->ext_id =
7678             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7679                         FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7680
7681         mf_info->default_vlan =
7682             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7683                         FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7684
7685         mf_info->niv_allowed_priorities =
7686             (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7687                        FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7688
7689         mf_info->niv_default_cos =
7690             (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7691                        FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7692
7693         mf_info->afex_vlan_mode =
7694             ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7695              FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7696
7697         mf_info->niv_mba_enabled =
7698             ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7699              FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7700
7701         mf_info->mf_protos_supported =
7702             bnx2x_get_shmem_ext_proto_support_flags(sc);
7703
7704         mf_info->vnics_per_port =
7705             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7706
7707         return 0;
7708 }
7709
7710 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7711 {
7712         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7713         uint32_t mf_cfg1;
7714         uint32_t mf_cfg2;
7715         uint32_t ovlan1;
7716         uint32_t ovlan2;
7717         uint8_t i, j;
7718
7719         /* various MF mode sanity checks... */
7720
7721         if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7722                 PMD_DRV_LOG(NOTICE, sc,
7723                             "Enumerated function %d is marked as hidden",
7724                             SC_PORT(sc));
7725                 return 1;
7726         }
7727
7728         if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7729                 PMD_DRV_LOG(NOTICE, sc, "vnics_per_port=%d multi_vnics_mode=%d",
7730                             mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7731                 return 1;
7732         }
7733
7734         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7735 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7736                 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7737                         PMD_DRV_LOG(NOTICE, sc, "mf_mode=SD vnic_id=%d ovlan=%d",
7738                                     SC_VN(sc), OVLAN(sc));
7739                         return 1;
7740                 }
7741
7742                 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7743                         PMD_DRV_LOG(NOTICE, sc,
7744                                     "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7745                                     mf_info->multi_vnics_mode, OVLAN(sc));
7746                         return 1;
7747                 }
7748
7749 /*
7750  * Verify all functions are either MF or SF mode. If MF, make sure
7751  * sure that all non-hidden functions have a valid ovlan. If SF,
7752  * make sure that all non-hidden functions have an invalid ovlan.
7753  */
7754                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7755                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7756                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7757                         if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7758                             (((mf_info->multi_vnics_mode)
7759                               && !VALID_OVLAN(ovlan1))
7760                              || ((!mf_info->multi_vnics_mode)
7761                                  && VALID_OVLAN(ovlan1)))) {
7762                                 PMD_DRV_LOG(NOTICE, sc,
7763                                             "mf_mode=SD function %d MF config "
7764                                             "mismatch, multi_vnics_mode=%d ovlan=%d",
7765                                             i, mf_info->multi_vnics_mode,
7766                                             ovlan1);
7767                                 return 1;
7768                         }
7769                 }
7770
7771 /* Verify all funcs on the same port each have a different ovlan. */
7772                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7773                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7774                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7775                         /* iterate from the next function on the port to the max func */
7776                         for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7777                                 mf_cfg2 =
7778                                     MFCFG_RD(sc, func_mf_config[j].config);
7779                                 ovlan2 =
7780                                     MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7781                                 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7782                                     && VALID_OVLAN(ovlan1)
7783                                     && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7784                                     && VALID_OVLAN(ovlan2)
7785                                     && (ovlan1 == ovlan2)) {
7786                                         PMD_DRV_LOG(NOTICE, sc,
7787                                                     "mf_mode=SD functions %d and %d "
7788                                                     "have the same ovlan (%d)",
7789                                                     i, j, ovlan1);
7790                                         return 1;
7791                                 }
7792                         }
7793                 }
7794         }
7795         /* MULTI_FUNCTION_SD */
7796         return 0;
7797 }
7798
7799 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7800 {
7801         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7802         uint32_t val, mac_upper;
7803         uint8_t i, vnic;
7804
7805         /* initialize mf_info defaults */
7806         mf_info->vnics_per_port = 1;
7807         mf_info->multi_vnics_mode = FALSE;
7808         mf_info->path_has_ovlan = FALSE;
7809         mf_info->mf_mode = SINGLE_FUNCTION;
7810
7811         if (!CHIP_IS_MF_CAP(sc)) {
7812                 return 0;
7813         }
7814
7815         if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7816                 PMD_DRV_LOG(NOTICE, sc, "Invalid mf_cfg_base!");
7817                 return 1;
7818         }
7819
7820         /* get the MF mode (switch dependent / independent / single-function) */
7821
7822         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7823
7824         switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7825         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7826
7827                 mac_upper =
7828                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7829
7830                 /* check for legal upper mac bytes */
7831                 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7832                         mf_info->mf_mode = MULTI_FUNCTION_SI;
7833                 } else {
7834                         PMD_DRV_LOG(NOTICE, sc,
7835                                     "Invalid config for Switch Independent mode");
7836                 }
7837
7838                 break;
7839
7840         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7841         case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7842
7843                 /* get outer vlan configuration */
7844                 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7845
7846                 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7847                     FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7848                         mf_info->mf_mode = MULTI_FUNCTION_SD;
7849                 } else {
7850                         PMD_DRV_LOG(NOTICE, sc,
7851                                     "Invalid config for Switch Dependent mode");
7852                 }
7853
7854                 break;
7855
7856         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7857
7858                 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7859                 return 0;
7860
7861         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7862
7863                 /*
7864                  * Mark MF mode as NIV if MCP version includes NPAR-SD support
7865                  * and the MAC address is valid.
7866                  */
7867                 mac_upper =
7868                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7869
7870                 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7871                     (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7872                         mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7873                 } else {
7874                         PMD_DRV_LOG(NOTICE, sc, "Invalid config for AFEX mode");
7875                 }
7876
7877                 break;
7878
7879         default:
7880
7881                 PMD_DRV_LOG(NOTICE, sc, "Unknown MF mode (0x%08x)",
7882                             (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7883
7884                 return 1;
7885         }
7886
7887         /* set path mf_mode (which could be different than function mf_mode) */
7888         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7889                 mf_info->path_has_ovlan = TRUE;
7890         } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7891 /*
7892  * Decide on path multi vnics mode. If we're not in MF mode and in
7893  * 4-port mode, this is good enough to check vnic-0 of the other port
7894  * on the same path
7895  */
7896                 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7897                         uint8_t other_port = !(PORT_ID(sc) & 1);
7898                         uint8_t abs_func_other_port =
7899                             (SC_PATH(sc) + (2 * other_port));
7900
7901                         val =
7902                             MFCFG_RD(sc,
7903                                      func_mf_config
7904                                      [abs_func_other_port].e1hov_tag);
7905
7906                         mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7907                 }
7908         }
7909
7910         if (mf_info->mf_mode == SINGLE_FUNCTION) {
7911 /* invalid MF config */
7912                 if (SC_VN(sc) >= 1) {
7913                         PMD_DRV_LOG(NOTICE, sc, "VNIC ID >= 1 in SF mode");
7914                         return 1;
7915                 }
7916
7917                 return 0;
7918         }
7919
7920         /* get the MF configuration */
7921         mf_info->mf_config[SC_VN(sc)] =
7922             MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7923
7924         switch (mf_info->mf_mode) {
7925         case MULTI_FUNCTION_SD:
7926
7927                 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7928                 break;
7929
7930         case MULTI_FUNCTION_SI:
7931
7932                 bnx2x_get_shmem_mf_cfg_info_si(sc);
7933                 break;
7934
7935         case MULTI_FUNCTION_AFEX:
7936
7937                 bnx2x_get_shmem_mf_cfg_info_niv(sc);
7938                 break;
7939
7940         default:
7941
7942                 PMD_DRV_LOG(NOTICE, sc, "Get MF config failed (mf_mode=0x%08x)",
7943                             mf_info->mf_mode);
7944                 return 1;
7945         }
7946
7947         /* get the congestion management parameters */
7948
7949         vnic = 0;
7950         FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7951 /* get min/max bw */
7952                 val = MFCFG_RD(sc, func_mf_config[i].config);
7953                 mf_info->min_bw[vnic] =
7954                     ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
7955                      FUNC_MF_CFG_MIN_BW_SHIFT);
7956                 mf_info->max_bw[vnic] =
7957                     ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
7958                      FUNC_MF_CFG_MAX_BW_SHIFT);
7959                 vnic++;
7960         }
7961
7962         return bnx2x_check_valid_mf_cfg(sc);
7963 }
7964
7965 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
7966 {
7967         int port;
7968         uint32_t mac_hi, mac_lo, val;
7969
7970         PMD_INIT_FUNC_TRACE(sc);
7971
7972         port = SC_PORT(sc);
7973         mac_hi = mac_lo = 0;
7974
7975         sc->link_params.sc = sc;
7976         sc->link_params.port = port;
7977
7978         /* get the hardware config info */
7979         sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
7980         sc->devinfo.hw_config2 =
7981             SHMEM_RD(sc, dev_info.shared_hw_config.config2);
7982
7983         sc->link_params.hw_led_mode =
7984             ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
7985              SHARED_HW_CFG_LED_MODE_SHIFT);
7986
7987         /* get the port feature config */
7988         sc->port.config =
7989             SHMEM_RD(sc, dev_info.port_feature_config[port].config);
7990
7991         /* get the link params */
7992         sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
7993             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
7994             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
7995         sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
7996             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
7997             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
7998
7999         /* get the lane config */
8000         sc->link_params.lane_config =
8001             SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8002
8003         /* get the link config */
8004         val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8005         sc->port.link_config[ELINK_INT_PHY] = val;
8006         sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8007         sc->port.link_config[ELINK_EXT_PHY1] =
8008             SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8009
8010         /* get the override preemphasis flag and enable it or turn it off */
8011         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8012         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8013                 sc->link_params.feature_config_flags |=
8014                     ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8015         } else {
8016                 sc->link_params.feature_config_flags &=
8017                     ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8018         }
8019
8020         /* get the initial value of the link params */
8021         sc->link_params.multi_phy_config =
8022             SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8023
8024         /* get external phy info */
8025         sc->port.ext_phy_config =
8026             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8027
8028         /* get the multifunction configuration */
8029         bnx2x_get_mf_cfg_info(sc);
8030
8031         /* get the mac address */
8032         if (IS_MF(sc)) {
8033                 mac_hi =
8034                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8035                 mac_lo =
8036                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8037         } else {
8038                 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8039                 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8040         }
8041
8042         if ((mac_lo == 0) && (mac_hi == 0)) {
8043                 *sc->mac_addr_str = 0;
8044                 PMD_DRV_LOG(NOTICE, sc, "No Ethernet address programmed!");
8045         } else {
8046                 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8047                 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8048                 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8049                 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8050                 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8051                 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8052                 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8053                          "%02x:%02x:%02x:%02x:%02x:%02x",
8054                          sc->link_params.mac_addr[0],
8055                          sc->link_params.mac_addr[1],
8056                          sc->link_params.mac_addr[2],
8057                          sc->link_params.mac_addr[3],
8058                          sc->link_params.mac_addr[4],
8059                          sc->link_params.mac_addr[5]);
8060                 PMD_DRV_LOG(DEBUG, sc,
8061                             "Ethernet address: %s", sc->mac_addr_str);
8062         }
8063
8064         return 0;
8065 }
8066
8067 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8068 {
8069         uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8070         switch (sc->link_params.phy[phy_idx].media_type) {
8071         case ELINK_ETH_PHY_SFPP_10G_FIBER:
8072         case ELINK_ETH_PHY_SFP_1G_FIBER:
8073         case ELINK_ETH_PHY_XFP_FIBER:
8074         case ELINK_ETH_PHY_KR:
8075         case ELINK_ETH_PHY_CX4:
8076                 PMD_DRV_LOG(INFO, sc, "Found 10GBase-CX4 media.");
8077                 sc->media = IFM_10G_CX4;
8078                 break;
8079         case ELINK_ETH_PHY_DA_TWINAX:
8080                 PMD_DRV_LOG(INFO, sc, "Found 10Gb Twinax media.");
8081                 sc->media = IFM_10G_TWINAX;
8082                 break;
8083         case ELINK_ETH_PHY_BASE_T:
8084                 PMD_DRV_LOG(INFO, sc, "Found 10GBase-T media.");
8085                 sc->media = IFM_10G_T;
8086                 break;
8087         case ELINK_ETH_PHY_NOT_PRESENT:
8088                 PMD_DRV_LOG(INFO, sc, "Media not present.");
8089                 sc->media = 0;
8090                 break;
8091         case ELINK_ETH_PHY_UNSPECIFIED:
8092         default:
8093                 PMD_DRV_LOG(INFO, sc, "Unknown media!");
8094                 sc->media = 0;
8095                 break;
8096         }
8097 }
8098
8099 #define GET_FIELD(value, fname)                     \
8100 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8101 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8102 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8103
8104 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8105 {
8106         int pfid = SC_FUNC(sc);
8107         int igu_sb_id;
8108         uint32_t val;
8109         uint8_t fid, igu_sb_cnt = 0;
8110
8111         sc->igu_base_sb = 0xff;
8112
8113         if (CHIP_INT_MODE_IS_BC(sc)) {
8114                 int vn = SC_VN(sc);
8115                 igu_sb_cnt = sc->igu_sb_cnt;
8116                 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8117                                    FP_SB_MAX_E1x);
8118                 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8119                                   (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8120                 return 0;
8121         }
8122
8123         /* IGU in normal mode - read CAM */
8124         for (igu_sb_id = 0;
8125              igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8126                 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8127                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8128                         continue;
8129                 }
8130                 fid = IGU_FID(val);
8131                 if (fid & IGU_FID_ENCODE_IS_PF) {
8132                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8133                                 continue;
8134                         }
8135                         if (IGU_VEC(val) == 0) {
8136                                 /* default status block */
8137                                 sc->igu_dsb_id = igu_sb_id;
8138                         } else {
8139                                 if (sc->igu_base_sb == 0xff) {
8140                                         sc->igu_base_sb = igu_sb_id;
8141                                 }
8142                                 igu_sb_cnt++;
8143                         }
8144                 }
8145         }
8146
8147         /*
8148          * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8149          * that number of CAM entries will not be equal to the value advertised in
8150          * PCI. Driver should use the minimal value of both as the actual status
8151          * block count
8152          */
8153         sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8154
8155         if (igu_sb_cnt == 0) {
8156                 PMD_DRV_LOG(ERR, sc, "CAM configuration error");
8157                 return -1;
8158         }
8159
8160         return 0;
8161 }
8162
8163 /*
8164 * Gather various information from the device config space, the device itself,
8165 * shmem, and the user input.
8166 */
8167 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8168 {
8169         uint32_t val;
8170         int rc;
8171
8172         /* get the chip revision (chip metal comes from pci config space) */
8173         sc->devinfo.chip_id = sc->link_params.chip_id =
8174             (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8175              ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8176              (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8177              ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8178
8179         /* force 57811 according to MISC register */
8180         if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8181                 if (CHIP_IS_57810(sc)) {
8182                         sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8183                                                (sc->
8184                                                 devinfo.chip_id & 0x0000ffff));
8185                 } else if (CHIP_IS_57810_MF(sc)) {
8186                         sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8187                                                (sc->
8188                                                 devinfo.chip_id & 0x0000ffff));
8189                 }
8190                 sc->devinfo.chip_id |= 0x1;
8191         }
8192
8193         PMD_DRV_LOG(DEBUG, sc,
8194                     "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8195                     sc->devinfo.chip_id,
8196                     ((sc->devinfo.chip_id >> 16) & 0xffff),
8197                     ((sc->devinfo.chip_id >> 12) & 0xf),
8198                     ((sc->devinfo.chip_id >> 4) & 0xff),
8199                     ((sc->devinfo.chip_id >> 0) & 0xf));
8200
8201         val = (REG_RD(sc, 0x2874) & 0x55);
8202         if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8203                 sc->flags |= BNX2X_ONE_PORT_FLAG;
8204                 PMD_DRV_LOG(DEBUG, sc, "single port device");
8205         }
8206
8207         /* set the doorbell size */
8208         sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8209
8210         /* determine whether the device is in 2 port or 4 port mode */
8211         sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE;       /* E1h */
8212         if (CHIP_IS_E2E3(sc)) {
8213 /*
8214  * Read port4mode_en_ovwr[0]:
8215  *   If 1, four port mode is in port4mode_en_ovwr[1].
8216  *   If 0, four port mode is in port4mode_en[0].
8217  */
8218                 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8219                 if (val & 1) {
8220                         val = ((val >> 1) & 1);
8221                 } else {
8222                         val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8223                 }
8224
8225                 sc->devinfo.chip_port_mode =
8226                     (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8227
8228                 PMD_DRV_LOG(DEBUG, sc, "Port mode = %s", (val) ? "4" : "2");
8229         }
8230
8231         /* get the function and path info for the device */
8232         bnx2x_get_function_num(sc);
8233
8234         /* get the shared memory base address */
8235         sc->devinfo.shmem_base =
8236             sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8237         sc->devinfo.shmem2_base =
8238             REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8239                         MISC_REG_GENERIC_CR_0));
8240
8241         if (!sc->devinfo.shmem_base) {
8242 /* this should ONLY prevent upcoming shmem reads */
8243                 PMD_DRV_LOG(INFO, sc, "MCP not active");
8244                 sc->flags |= BNX2X_NO_MCP_FLAG;
8245                 return 0;
8246         }
8247
8248         /* make sure the shared memory contents are valid */
8249         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8250         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8251             (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8252                 PMD_DRV_LOG(NOTICE, sc, "Invalid SHMEM validity signature: 0x%08x",
8253                             val);
8254                 return 0;
8255         }
8256
8257         /* get the bootcode version */
8258         sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8259         snprintf(sc->devinfo.bc_ver_str,
8260                  sizeof(sc->devinfo.bc_ver_str),
8261                  "%d.%d.%d",
8262                  ((sc->devinfo.bc_ver >> 24) & 0xff),
8263                  ((sc->devinfo.bc_ver >> 16) & 0xff),
8264                  ((sc->devinfo.bc_ver >> 8) & 0xff));
8265         PMD_DRV_LOG(INFO, sc, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8266
8267         /* get the bootcode shmem address */
8268         sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8269
8270         /* clean indirect addresses as they're not used */
8271         pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8272         if (IS_PF(sc)) {
8273                 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8274                 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8275                 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8276                 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8277                 if (CHIP_IS_E1x(sc)) {
8278                         REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8279                         REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8280                         REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8281                         REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8282                 }
8283         }
8284
8285         /* get the nvram size */
8286         val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8287         sc->devinfo.flash_size =
8288             (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8289
8290         bnx2x_set_power_state(sc, PCI_PM_D0);
8291         /* get various configuration parameters from shmem */
8292         bnx2x_get_shmem_info(sc);
8293
8294         /* initialize IGU parameters */
8295         if (CHIP_IS_E1x(sc)) {
8296                 sc->devinfo.int_block = INT_BLOCK_HC;
8297                 sc->igu_dsb_id = DEF_SB_IGU_ID;
8298                 sc->igu_base_sb = 0;
8299         } else {
8300                 sc->devinfo.int_block = INT_BLOCK_IGU;
8301
8302 /* do not allow device reset during IGU info preocessing */
8303                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8304
8305                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8306
8307                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8308                         int tout = 5000;
8309
8310                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8311                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8312                         REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8313
8314                         while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8315                                 tout--;
8316                                 DELAY(1000);
8317                         }
8318
8319                         if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8320                                 PMD_DRV_LOG(NOTICE, sc,
8321                                             "FORCING IGU Normal Mode failed!!!");
8322                                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8323                                 return -1;
8324                         }
8325                 }
8326
8327                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8328                         PMD_DRV_LOG(DEBUG, sc, "IGU Backward Compatible Mode");
8329                         sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8330                 } else {
8331                         PMD_DRV_LOG(DEBUG, sc, "IGU Normal Mode");
8332                 }
8333
8334                 rc = bnx2x_get_igu_cam_info(sc);
8335
8336                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8337
8338                 if (rc) {
8339                         return rc;
8340                 }
8341         }
8342
8343         /*
8344          * Get base FW non-default (fast path) status block ID. This value is
8345          * used to initialize the fw_sb_id saved on the fp/queue structure to
8346          * determine the id used by the FW.
8347          */
8348         if (CHIP_IS_E1x(sc)) {
8349                 sc->base_fw_ndsb =
8350                     ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8351         } else {
8352 /*
8353  * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8354  * the same queue are indicated on the same IGU SB). So we prefer
8355  * FW and IGU SBs to be the same value.
8356  */
8357                 sc->base_fw_ndsb = sc->igu_base_sb;
8358         }
8359
8360         elink_phy_probe(&sc->link_params);
8361
8362         return 0;
8363 }
8364
8365 static void
8366 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8367 {
8368         uint32_t cfg_size = 0;
8369         uint32_t idx;
8370         uint8_t port = SC_PORT(sc);
8371
8372         /* aggregation of supported attributes of all external phys */
8373         sc->port.supported[0] = 0;
8374         sc->port.supported[1] = 0;
8375
8376         switch (sc->link_params.num_phys) {
8377         case 1:
8378                 sc->port.supported[0] =
8379                     sc->link_params.phy[ELINK_INT_PHY].supported;
8380                 cfg_size = 1;
8381                 break;
8382         case 2:
8383                 sc->port.supported[0] =
8384                     sc->link_params.phy[ELINK_EXT_PHY1].supported;
8385                 cfg_size = 1;
8386                 break;
8387         case 3:
8388                 if (sc->link_params.multi_phy_config &
8389                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8390                         sc->port.supported[1] =
8391                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8392                         sc->port.supported[0] =
8393                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8394                 } else {
8395                         sc->port.supported[0] =
8396                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8397                         sc->port.supported[1] =
8398                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8399                 }
8400                 cfg_size = 2;
8401                 break;
8402         }
8403
8404         if (!(sc->port.supported[0] || sc->port.supported[1])) {
8405                 PMD_DRV_LOG(ERR, sc,
8406                             "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8407                             SHMEM_RD(sc,
8408                                      dev_info.port_hw_config
8409                                      [port].external_phy_config),
8410                             SHMEM_RD(sc,
8411                                      dev_info.port_hw_config
8412                                      [port].external_phy_config2));
8413                 return;
8414         }
8415
8416         if (CHIP_IS_E3(sc))
8417                 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8418         else {
8419                 switch (switch_cfg) {
8420                 case ELINK_SWITCH_CFG_1G:
8421                         sc->port.phy_addr =
8422                             REG_RD(sc,
8423                                    NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8424                         break;
8425                 case ELINK_SWITCH_CFG_10G:
8426                         sc->port.phy_addr =
8427                             REG_RD(sc,
8428                                    NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8429                         break;
8430                 default:
8431                         PMD_DRV_LOG(ERR, sc,
8432                                     "Invalid switch config in"
8433                                     "link_config=0x%08x",
8434                                     sc->port.link_config[0]);
8435                         return;
8436                 }
8437         }
8438
8439         PMD_DRV_LOG(INFO, sc, "PHY addr 0x%08x", sc->port.phy_addr);
8440
8441         /* mask what we support according to speed_cap_mask per configuration */
8442         for (idx = 0; idx < cfg_size; idx++) {
8443                 if (!(sc->link_params.speed_cap_mask[idx] &
8444                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8445                         sc->port.supported[idx] &=
8446                             ~ELINK_SUPPORTED_10baseT_Half;
8447                 }
8448
8449                 if (!(sc->link_params.speed_cap_mask[idx] &
8450                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8451                         sc->port.supported[idx] &=
8452                             ~ELINK_SUPPORTED_10baseT_Full;
8453                 }
8454
8455                 if (!(sc->link_params.speed_cap_mask[idx] &
8456                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8457                         sc->port.supported[idx] &=
8458                             ~ELINK_SUPPORTED_100baseT_Half;
8459                 }
8460
8461                 if (!(sc->link_params.speed_cap_mask[idx] &
8462                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8463                         sc->port.supported[idx] &=
8464                             ~ELINK_SUPPORTED_100baseT_Full;
8465                 }
8466
8467                 if (!(sc->link_params.speed_cap_mask[idx] &
8468                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8469                         sc->port.supported[idx] &=
8470                             ~ELINK_SUPPORTED_1000baseT_Full;
8471                 }
8472
8473                 if (!(sc->link_params.speed_cap_mask[idx] &
8474                       PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8475                         sc->port.supported[idx] &=
8476                             ~ELINK_SUPPORTED_2500baseX_Full;
8477                 }
8478
8479                 if (!(sc->link_params.speed_cap_mask[idx] &
8480                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8481                         sc->port.supported[idx] &=
8482                             ~ELINK_SUPPORTED_10000baseT_Full;
8483                 }
8484
8485                 if (!(sc->link_params.speed_cap_mask[idx] &
8486                       PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8487                         sc->port.supported[idx] &=
8488                             ~ELINK_SUPPORTED_20000baseKR2_Full;
8489                 }
8490         }
8491
8492         PMD_DRV_LOG(INFO, sc, "PHY supported 0=0x%08x 1=0x%08x",
8493                     sc->port.supported[0], sc->port.supported[1]);
8494 }
8495
8496 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8497 {
8498         uint32_t link_config;
8499         uint32_t idx;
8500         uint32_t cfg_size = 0;
8501
8502         sc->port.advertising[0] = 0;
8503         sc->port.advertising[1] = 0;
8504
8505         switch (sc->link_params.num_phys) {
8506         case 1:
8507         case 2:
8508                 cfg_size = 1;
8509                 break;
8510         case 3:
8511                 cfg_size = 2;
8512                 break;
8513         }
8514
8515         for (idx = 0; idx < cfg_size; idx++) {
8516                 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8517                 link_config = sc->port.link_config[idx];
8518
8519                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8520                 case PORT_FEATURE_LINK_SPEED_AUTO:
8521                         if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8522                                 sc->link_params.req_line_speed[idx] =
8523                                     ELINK_SPEED_AUTO_NEG;
8524                                 sc->port.advertising[idx] |=
8525                                     sc->port.supported[idx];
8526                                 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8527                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8528                                         sc->port.advertising[idx] |=
8529                                             (ELINK_SUPPORTED_100baseT_Half |
8530                                              ELINK_SUPPORTED_100baseT_Full);
8531                         } else {
8532                                 /* force 10G, no AN */
8533                                 sc->link_params.req_line_speed[idx] =
8534                                     ELINK_SPEED_10000;
8535                                 sc->port.advertising[idx] |=
8536                                     (ADVERTISED_10000baseT_Full |
8537                                      ADVERTISED_FIBRE);
8538                                 continue;
8539                         }
8540                         break;
8541
8542                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8543                         if (sc->
8544                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8545                         {
8546                                 sc->link_params.req_line_speed[idx] =
8547                                     ELINK_SPEED_10;
8548                                 sc->port.advertising[idx] |=
8549                                     (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8550                         } else {
8551                                 PMD_DRV_LOG(ERR, sc,
8552                                             "Invalid NVRAM config link_config=0x%08x "
8553                                             "speed_cap_mask=0x%08x",
8554                                             link_config,
8555                                             sc->
8556                                             link_params.speed_cap_mask[idx]);
8557                                 return;
8558                         }
8559                         break;
8560
8561                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8562                         if (sc->
8563                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8564                         {
8565                                 sc->link_params.req_line_speed[idx] =
8566                                     ELINK_SPEED_10;
8567                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8568                                 sc->port.advertising[idx] |=
8569                                     (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8570                         } else {
8571                                 PMD_DRV_LOG(ERR, sc,
8572                                             "Invalid NVRAM config link_config=0x%08x "
8573                                             "speed_cap_mask=0x%08x",
8574                                             link_config,
8575                                             sc->
8576                                             link_params.speed_cap_mask[idx]);
8577                                 return;
8578                         }
8579                         break;
8580
8581                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8582                         if (sc->
8583                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8584                         {
8585                                 sc->link_params.req_line_speed[idx] =
8586                                     ELINK_SPEED_100;
8587                                 sc->port.advertising[idx] |=
8588                                     (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8589                         } else {
8590                                 PMD_DRV_LOG(ERR, sc,
8591                                             "Invalid NVRAM config link_config=0x%08x "
8592                                             "speed_cap_mask=0x%08x",
8593                                             link_config,
8594                                             sc->
8595                                             link_params.speed_cap_mask[idx]);
8596                                 return;
8597                         }
8598                         break;
8599
8600                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8601                         if (sc->
8602                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8603                         {
8604                                 sc->link_params.req_line_speed[idx] =
8605                                     ELINK_SPEED_100;
8606                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8607                                 sc->port.advertising[idx] |=
8608                                     (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8609                         } else {
8610                                 PMD_DRV_LOG(ERR, sc,
8611                                             "Invalid NVRAM config link_config=0x%08x "
8612                                             "speed_cap_mask=0x%08x",
8613                                             link_config,
8614                                             sc->
8615                                             link_params.speed_cap_mask[idx]);
8616                                 return;
8617                         }
8618                         break;
8619
8620                 case PORT_FEATURE_LINK_SPEED_1G:
8621                         if (sc->port.supported[idx] &
8622                             ELINK_SUPPORTED_1000baseT_Full) {
8623                                 sc->link_params.req_line_speed[idx] =
8624                                     ELINK_SPEED_1000;
8625                                 sc->port.advertising[idx] |=
8626                                     (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8627                         } else {
8628                                 PMD_DRV_LOG(ERR, sc,
8629                                             "Invalid NVRAM config link_config=0x%08x "
8630                                             "speed_cap_mask=0x%08x",
8631                                             link_config,
8632                                             sc->
8633                                             link_params.speed_cap_mask[idx]);
8634                                 return;
8635                         }
8636                         break;
8637
8638                 case PORT_FEATURE_LINK_SPEED_2_5G:
8639                         if (sc->port.supported[idx] &
8640                             ELINK_SUPPORTED_2500baseX_Full) {
8641                                 sc->link_params.req_line_speed[idx] =
8642                                     ELINK_SPEED_2500;
8643                                 sc->port.advertising[idx] |=
8644                                     (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8645                         } else {
8646                                 PMD_DRV_LOG(ERR, sc,
8647                                             "Invalid NVRAM config link_config=0x%08x "
8648                                             "speed_cap_mask=0x%08x",
8649                                             link_config,
8650                                             sc->
8651                                             link_params.speed_cap_mask[idx]);
8652                                 return;
8653                         }
8654                         break;
8655
8656                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8657                         if (sc->port.supported[idx] &
8658                             ELINK_SUPPORTED_10000baseT_Full) {
8659                                 sc->link_params.req_line_speed[idx] =
8660                                     ELINK_SPEED_10000;
8661                                 sc->port.advertising[idx] |=
8662                                     (ADVERTISED_10000baseT_Full |
8663                                      ADVERTISED_FIBRE);
8664                         } else {
8665                                 PMD_DRV_LOG(ERR, sc,
8666                                             "Invalid NVRAM config link_config=0x%08x "
8667                                             "speed_cap_mask=0x%08x",
8668                                             link_config,
8669                                             sc->
8670                                             link_params.speed_cap_mask[idx]);
8671                                 return;
8672                         }
8673                         break;
8674
8675                 case PORT_FEATURE_LINK_SPEED_20G:
8676                         sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8677                         break;
8678
8679                 default:
8680                         PMD_DRV_LOG(ERR, sc,
8681                                     "Invalid NVRAM config link_config=0x%08x "
8682                                     "speed_cap_mask=0x%08x", link_config,
8683                                     sc->link_params.speed_cap_mask[idx]);
8684                         sc->link_params.req_line_speed[idx] =
8685                             ELINK_SPEED_AUTO_NEG;
8686                         sc->port.advertising[idx] = sc->port.supported[idx];
8687                         break;
8688                 }
8689
8690                 sc->link_params.req_flow_ctrl[idx] =
8691                     (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8692
8693                 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8694                         if (!
8695                             (sc->
8696                              port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8697                                 sc->link_params.req_flow_ctrl[idx] =
8698                                     ELINK_FLOW_CTRL_NONE;
8699                         } else {
8700                                 bnx2x_set_requested_fc(sc);
8701                         }
8702                 }
8703         }
8704 }
8705
8706 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8707 {
8708         uint8_t port = SC_PORT(sc);
8709         uint32_t eee_mode;
8710
8711         PMD_INIT_FUNC_TRACE(sc);
8712
8713         /* shmem data already read in bnx2x_get_shmem_info() */
8714
8715         bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8716         bnx2x_link_settings_requested(sc);
8717
8718         /* configure link feature according to nvram value */
8719         eee_mode =
8720             (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8721               & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8722              PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8723         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8724                 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8725                                             ELINK_EEE_MODE_ENABLE_LPI |
8726                                             ELINK_EEE_MODE_OUTPUT_TIME);
8727         } else {
8728                 sc->link_params.eee_mode = 0;
8729         }
8730
8731         /* get the media type */
8732         bnx2x_media_detect(sc);
8733 }
8734
8735 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8736 {
8737         uint32_t flags = MODE_ASIC | MODE_PORT2;
8738
8739         if (CHIP_IS_E2(sc)) {
8740                 flags |= MODE_E2;
8741         } else if (CHIP_IS_E3(sc)) {
8742                 flags |= MODE_E3;
8743                 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8744                         flags |= MODE_E3_A0;
8745                 } else {        /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8746
8747                         flags |= MODE_E3_B0 | MODE_COS3;
8748                 }
8749         }
8750
8751         if (IS_MF(sc)) {
8752                 flags |= MODE_MF;
8753                 switch (sc->devinfo.mf_info.mf_mode) {
8754                 case MULTI_FUNCTION_SD:
8755                         flags |= MODE_MF_SD;
8756                         break;
8757                 case MULTI_FUNCTION_SI:
8758                         flags |= MODE_MF_SI;
8759                         break;
8760                 case MULTI_FUNCTION_AFEX:
8761                         flags |= MODE_MF_AFEX;
8762                         break;
8763                 }
8764         } else {
8765                 flags |= MODE_SF;
8766         }
8767
8768 #if defined(__LITTLE_ENDIAN)
8769         flags |= MODE_LITTLE_ENDIAN;
8770 #else /* __BIG_ENDIAN */
8771         flags |= MODE_BIG_ENDIAN;
8772 #endif
8773
8774         INIT_MODE_FLAGS(sc) = flags;
8775 }
8776
8777 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8778 {
8779         struct bnx2x_fastpath *fp;
8780         char buf[32];
8781         uint32_t i;
8782
8783         if (IS_PF(sc)) {
8784 /************************/
8785 /* DEFAULT STATUS BLOCK */
8786 /************************/
8787
8788                 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8789                                   &sc->def_sb_dma, "def_sb",
8790                                   RTE_CACHE_LINE_SIZE) != 0) {
8791                         return -1;
8792                 }
8793
8794                 sc->def_sb =
8795                     (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8796 /***************/
8797 /* EVENT QUEUE */
8798 /***************/
8799
8800                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8801                                   &sc->eq_dma, "ev_queue",
8802                                   RTE_CACHE_LINE_SIZE) != 0) {
8803                         sc->def_sb = NULL;
8804                         return -1;
8805                 }
8806
8807                 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8808
8809 /*************/
8810 /* SLOW PATH */
8811 /*************/
8812
8813                 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8814                                   &sc->sp_dma, "sp",
8815                                   RTE_CACHE_LINE_SIZE) != 0) {
8816                         sc->eq = NULL;
8817                         sc->def_sb = NULL;
8818                         return -1;
8819                 }
8820
8821                 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8822
8823 /*******************/
8824 /* SLOW PATH QUEUE */
8825 /*******************/
8826
8827                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8828                                   &sc->spq_dma, "sp_queue",
8829                                   RTE_CACHE_LINE_SIZE) != 0) {
8830                         sc->sp = NULL;
8831                         sc->eq = NULL;
8832                         sc->def_sb = NULL;
8833                         return -1;
8834                 }
8835
8836                 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8837
8838 /***************************/
8839 /* FW DECOMPRESSION BUFFER */
8840 /***************************/
8841
8842                 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8843                                   "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8844                         sc->spq = NULL;
8845                         sc->sp = NULL;
8846                         sc->eq = NULL;
8847                         sc->def_sb = NULL;
8848                         return -1;
8849                 }
8850
8851                 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8852         }
8853
8854         /*************/
8855         /* FASTPATHS */
8856         /*************/
8857
8858         /* allocate DMA memory for each fastpath structure */
8859         for (i = 0; i < sc->num_queues; i++) {
8860                 fp = &sc->fp[i];
8861                 fp->sc = sc;
8862                 fp->index = i;
8863
8864 /*******************/
8865 /* FP STATUS BLOCK */
8866 /*******************/
8867
8868                 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8869                 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8870                                   &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8871                         PMD_DRV_LOG(NOTICE, sc, "Failed to alloc %s", buf);
8872                         return -1;
8873                 } else {
8874                         if (CHIP_IS_E2E3(sc)) {
8875                                 fp->status_block.e2_sb =
8876                                     (struct host_hc_status_block_e2 *)
8877                                     fp->sb_dma.vaddr;
8878                         } else {
8879                                 fp->status_block.e1x_sb =
8880                                     (struct host_hc_status_block_e1x *)
8881                                     fp->sb_dma.vaddr;
8882                         }
8883                 }
8884         }
8885
8886         return 0;
8887 }
8888
8889 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8890 {
8891         struct bnx2x_fastpath *fp;
8892         int i;
8893
8894         for (i = 0; i < sc->num_queues; i++) {
8895                 fp = &sc->fp[i];
8896
8897 /*******************/
8898 /* FP STATUS BLOCK */
8899 /*******************/
8900
8901                 memset(&fp->status_block, 0, sizeof(fp->status_block));
8902         }
8903
8904         /***************************/
8905         /* FW DECOMPRESSION BUFFER */
8906         /***************************/
8907
8908         sc->gz_buf = NULL;
8909
8910         /*******************/
8911         /* SLOW PATH QUEUE */
8912         /*******************/
8913
8914         sc->spq = NULL;
8915
8916         /*************/
8917         /* SLOW PATH */
8918         /*************/
8919
8920         sc->sp = NULL;
8921
8922         /***************/
8923         /* EVENT QUEUE */
8924         /***************/
8925
8926         sc->eq = NULL;
8927
8928         /************************/
8929         /* DEFAULT STATUS BLOCK */
8930         /************************/
8931
8932         sc->def_sb = NULL;
8933
8934 }
8935
8936 /*
8937 * Previous driver DMAE transaction may have occurred when pre-boot stage
8938 * ended and boot began. This would invalidate the addresses of the
8939 * transaction, resulting in was-error bit set in the PCI causing all
8940 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
8941 * the interrupt which detected this from the pglueb and the was-done bit
8942 */
8943 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
8944 {
8945         uint32_t val;
8946
8947         if (!CHIP_IS_E1x(sc)) {
8948                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
8949                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
8950                         REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
8951                                1 << SC_FUNC(sc));
8952                 }
8953         }
8954 }
8955
8956 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
8957 {
8958         uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
8959                                      DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
8960         if (!rc) {
8961                 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
8962                 return -1;
8963         }
8964
8965         return 0;
8966 }
8967
8968 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
8969 {
8970         struct bnx2x_prev_list_node *tmp;
8971
8972         LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
8973                 if ((sc->pcie_bus == tmp->bus) &&
8974                     (sc->pcie_device == tmp->slot) &&
8975                     (SC_PATH(sc) == tmp->path)) {
8976                         return tmp;
8977                 }
8978         }
8979
8980         return NULL;
8981 }
8982
8983 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
8984 {
8985         struct bnx2x_prev_list_node *tmp;
8986         int rc = FALSE;
8987
8988         rte_spinlock_lock(&bnx2x_prev_mtx);
8989
8990         tmp = bnx2x_prev_path_get_entry(sc);
8991         if (tmp) {
8992                 if (tmp->aer) {
8993                         PMD_DRV_LOG(DEBUG, sc,
8994                                     "Path %d/%d/%d was marked by AER",
8995                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
8996                 } else {
8997                         rc = TRUE;
8998                         PMD_DRV_LOG(DEBUG, sc,
8999                                     "Path %d/%d/%d was already cleaned from previous drivers",
9000                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9001                 }
9002         }
9003
9004         rte_spinlock_unlock(&bnx2x_prev_mtx);
9005
9006         return rc;
9007 }
9008
9009 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9010 {
9011         struct bnx2x_prev_list_node *tmp;
9012
9013         rte_spinlock_lock(&bnx2x_prev_mtx);
9014
9015         /* Check whether the entry for this path already exists */
9016         tmp = bnx2x_prev_path_get_entry(sc);
9017         if (tmp) {
9018                 if (!tmp->aer) {
9019                         PMD_DRV_LOG(DEBUG, sc,
9020                                     "Re-marking AER in path %d/%d/%d",
9021                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9022                 } else {
9023                         PMD_DRV_LOG(DEBUG, sc,
9024                                     "Removing AER indication from path %d/%d/%d",
9025                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9026                         tmp->aer = 0;
9027                 }
9028
9029                 rte_spinlock_unlock(&bnx2x_prev_mtx);
9030                 return 0;
9031         }
9032
9033         rte_spinlock_unlock(&bnx2x_prev_mtx);
9034
9035         /* Create an entry for this path and add it */
9036         tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9037                          RTE_CACHE_LINE_SIZE);
9038         if (!tmp) {
9039                 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate 'bnx2x_prev_list_node'");
9040                 return -1;
9041         }
9042
9043         tmp->bus = sc->pcie_bus;
9044         tmp->slot = sc->pcie_device;
9045         tmp->path = SC_PATH(sc);
9046         tmp->aer = 0;
9047         tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9048
9049         rte_spinlock_lock(&bnx2x_prev_mtx);
9050
9051         LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9052
9053         rte_spinlock_unlock(&bnx2x_prev_mtx);
9054
9055         return 0;
9056 }
9057
9058 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9059 {
9060         int i;
9061
9062         /* only E2 and onwards support FLR */
9063         if (CHIP_IS_E1x(sc)) {
9064                 PMD_DRV_LOG(WARNING, sc, "FLR not supported in E1H");
9065                 return -1;
9066         }
9067
9068         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9069         if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9070                 PMD_DRV_LOG(WARNING, sc,
9071                             "FLR not supported by BC_VER: 0x%08x",
9072                             sc->devinfo.bc_ver);
9073                 return -1;
9074         }
9075
9076         /* Wait for Transaction Pending bit clean */
9077         for (i = 0; i < 4; i++) {
9078                 if (i) {
9079                         DELAY(((1 << (i - 1)) * 100) * 1000);
9080                 }
9081
9082                 if (!bnx2x_is_pcie_pending(sc)) {
9083                         goto clear;
9084                 }
9085         }
9086
9087         PMD_DRV_LOG(NOTICE, sc, "PCIE transaction is not cleared, "
9088                     "proceeding with reset anyway");
9089
9090 clear:
9091         bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9092
9093         return 0;
9094 }
9095
9096 struct bnx2x_mac_vals {
9097         uint32_t xmac_addr;
9098         uint32_t xmac_val;
9099         uint32_t emac_addr;
9100         uint32_t emac_val;
9101         uint32_t umac_addr;
9102         uint32_t umac_val;
9103         uint32_t bmac_addr;
9104         uint32_t bmac_val[2];
9105 };
9106
9107 static void
9108 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9109 {
9110         uint32_t val, base_addr, offset, mask, reset_reg;
9111         uint8_t mac_stopped = FALSE;
9112         uint8_t port = SC_PORT(sc);
9113         uint32_t wb_data[2];
9114
9115         /* reset addresses as they also mark which values were changed */
9116         vals->bmac_addr = 0;
9117         vals->umac_addr = 0;
9118         vals->xmac_addr = 0;
9119         vals->emac_addr = 0;
9120
9121         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9122
9123         if (!CHIP_IS_E3(sc)) {
9124                 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9125                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9126                 if ((mask & reset_reg) && val) {
9127                         base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9128                             : NIG_REG_INGRESS_BMAC0_MEM;
9129                         offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9130                             : BIGMAC_REGISTER_BMAC_CONTROL;
9131
9132                         /*
9133                          * use rd/wr since we cannot use dmae. This is safe
9134                          * since MCP won't access the bus due to the request
9135                          * to unload, and no function on the path can be
9136                          * loaded at this time.
9137                          */
9138                         wb_data[0] = REG_RD(sc, base_addr + offset);
9139                         wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9140                         vals->bmac_addr = base_addr + offset;
9141                         vals->bmac_val[0] = wb_data[0];
9142                         vals->bmac_val[1] = wb_data[1];
9143                         wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9144                         REG_WR(sc, vals->bmac_addr, wb_data[0]);
9145                         REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9146                 }
9147
9148                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9149                 vals->emac_val = REG_RD(sc, vals->emac_addr);
9150                 REG_WR(sc, vals->emac_addr, 0);
9151                 mac_stopped = TRUE;
9152         } else {
9153                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9154                         base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9155                         val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9156                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9157                                val & ~(1 << 1));
9158                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9159                                val | (1 << 1));
9160                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9161                         vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9162                         REG_WR(sc, vals->xmac_addr, 0);
9163                         mac_stopped = TRUE;
9164                 }
9165
9166                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9167                 if (mask & reset_reg) {
9168                         base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9169                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9170                         vals->umac_val = REG_RD(sc, vals->umac_addr);
9171                         REG_WR(sc, vals->umac_addr, 0);
9172                         mac_stopped = TRUE;
9173                 }
9174         }
9175
9176         if (mac_stopped) {
9177                 DELAY(20000);
9178         }
9179 }
9180
9181 #define BNX2X_PREV_UNDI_PROD_ADDR(p)  (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9182 #define BNX2X_PREV_UNDI_RCQ(val)      ((val) & 0xffff)
9183 #define BNX2X_PREV_UNDI_BD(val)       ((val) >> 16 & 0xffff)
9184 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9185
9186 static void
9187 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9188 {
9189         uint16_t rcq, bd;
9190         uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9191
9192         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9193         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9194
9195         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9196         REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9197 }
9198
9199 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9200 {
9201         uint32_t reset_reg, tmp_reg = 0, rc;
9202         uint8_t prev_undi = FALSE;
9203         struct bnx2x_mac_vals mac_vals;
9204         uint32_t timer_count = 1000;
9205         uint32_t prev_brb;
9206
9207         /*
9208          * It is possible a previous function received 'common' answer,
9209          * but hasn't loaded yet, therefore creating a scenario of
9210          * multiple functions receiving 'common' on the same path.
9211          */
9212         memset(&mac_vals, 0, sizeof(mac_vals));
9213
9214         if (bnx2x_prev_is_path_marked(sc)) {
9215                 return bnx2x_prev_mcp_done(sc);
9216         }
9217
9218         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9219
9220         /* Reset should be performed after BRB is emptied */
9221         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9222                 /* Close the MAC Rx to prevent BRB from filling up */
9223                 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9224
9225                 /* close LLH filters towards the BRB */
9226                 elink_set_rx_filter(&sc->link_params, 0);
9227
9228                 /*
9229                  * Check if the UNDI driver was previously loaded.
9230                  * UNDI driver initializes CID offset for normal bell to 0x7
9231                  */
9232                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9233                         tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9234                         if (tmp_reg == 0x7) {
9235                                 PMD_DRV_LOG(DEBUG, sc, "UNDI previously loaded");
9236                                 prev_undi = TRUE;
9237                                 /* clear the UNDI indication */
9238                                 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9239                                 /* clear possible idle check errors */
9240                                 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9241                         }
9242                 }
9243
9244                 /* wait until BRB is empty */
9245                 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9246                 while (timer_count) {
9247                         prev_brb = tmp_reg;
9248
9249                         tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9250                         if (!tmp_reg) {
9251                                 break;
9252                         }
9253
9254                         PMD_DRV_LOG(DEBUG, sc, "BRB still has 0x%08x", tmp_reg);
9255
9256                         /* reset timer as long as BRB actually gets emptied */
9257                         if (prev_brb > tmp_reg) {
9258                                 timer_count = 1000;
9259                         } else {
9260                                 timer_count--;
9261                         }
9262
9263                         /* If UNDI resides in memory, manually increment it */
9264                         if (prev_undi) {
9265                                 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9266                         }
9267
9268                         DELAY(10);
9269                 }
9270
9271                 if (!timer_count) {
9272                         PMD_DRV_LOG(NOTICE, sc, "Failed to empty BRB");
9273                 }
9274         }
9275
9276         /* No packets are in the pipeline, path is ready for reset */
9277         bnx2x_reset_common(sc);
9278
9279         if (mac_vals.xmac_addr) {
9280                 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9281         }
9282         if (mac_vals.umac_addr) {
9283                 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9284         }
9285         if (mac_vals.emac_addr) {
9286                 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9287         }
9288         if (mac_vals.bmac_addr) {
9289                 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9290                 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9291         }
9292
9293         rc = bnx2x_prev_mark_path(sc, prev_undi);
9294         if (rc) {
9295                 bnx2x_prev_mcp_done(sc);
9296                 return rc;
9297         }
9298
9299         return bnx2x_prev_mcp_done(sc);
9300 }
9301
9302 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9303 {
9304         int rc;
9305
9306         /* Test if previous unload process was already finished for this path */
9307         if (bnx2x_prev_is_path_marked(sc)) {
9308                 return bnx2x_prev_mcp_done(sc);
9309         }
9310
9311         /*
9312          * If function has FLR capabilities, and existing FW version matches
9313          * the one required, then FLR will be sufficient to clean any residue
9314          * left by previous driver
9315          */
9316         rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9317         if (!rc) {
9318                 /* fw version is good */
9319                 rc = bnx2x_do_flr(sc);
9320         }
9321
9322         if (!rc) {
9323                 /* FLR was performed */
9324                 return 0;
9325         }
9326
9327         PMD_DRV_LOG(INFO, sc, "Could not FLR");
9328
9329         /* Close the MCP request, return failure */
9330         rc = bnx2x_prev_mcp_done(sc);
9331         if (!rc) {
9332                 rc = BNX2X_PREV_WAIT_NEEDED;
9333         }
9334
9335         return rc;
9336 }
9337
9338 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9339 {
9340         int time_counter = 10;
9341         uint32_t fw, hw_lock_reg, hw_lock_val;
9342         uint32_t rc = 0;
9343
9344         /*
9345          * Clear HW from errors which may have resulted from an interrupted
9346          * DMAE transaction.
9347          */
9348         bnx2x_prev_interrupted_dmae(sc);
9349
9350         /* Release previously held locks */
9351         if (SC_FUNC(sc) <= 5)
9352                 hw_lock_reg = (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8);
9353         else
9354                 hw_lock_reg =
9355                     (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9356
9357         hw_lock_val = (REG_RD(sc, hw_lock_reg));
9358         if (hw_lock_val) {
9359                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9360                         REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9361                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9362                 }
9363                 REG_WR(sc, hw_lock_reg, 0xffffffff);
9364         }
9365
9366         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9367                 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9368         }
9369
9370         do {
9371                 /* Lock MCP using an unload request */
9372                 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9373                 if (!fw) {
9374                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9375                         rc = -1;
9376                         break;
9377                 }
9378
9379                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9380                         rc = bnx2x_prev_unload_common(sc);
9381                         break;
9382                 }
9383
9384                 /* non-common reply from MCP might require looping */
9385                 rc = bnx2x_prev_unload_uncommon(sc);
9386                 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9387                         break;
9388                 }
9389
9390                 DELAY(20000);
9391         } while (--time_counter);
9392
9393         if (!time_counter || rc) {
9394                 PMD_DRV_LOG(NOTICE, sc, "Failed to unload previous driver!");
9395                 rc = -1;
9396         }
9397
9398         return rc;
9399 }
9400
9401 static void
9402 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9403 {
9404         if (!CHIP_IS_E1x(sc)) {
9405                 sc->dcb_state = dcb_on;
9406                 sc->dcbx_enabled = dcbx_enabled;
9407         } else {
9408                 sc->dcb_state = FALSE;
9409                 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9410         }
9411         PMD_DRV_LOG(DEBUG, sc,
9412                     "DCB state [%s:%s]",
9413                     dcb_on ? "ON" : "OFF",
9414                     (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9415                     (dcbx_enabled ==
9416                      BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9417                     : (dcbx_enabled ==
9418                        BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9419                     "on-chip with negotiation" : "invalid");
9420 }
9421
9422 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9423 {
9424         int cid_count = BNX2X_L2_MAX_CID(sc);
9425
9426         if (CNIC_SUPPORT(sc)) {
9427                 cid_count += CNIC_CID_MAX;
9428         }
9429
9430         return roundup(cid_count, QM_CID_ROUND);
9431 }
9432
9433 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9434 {
9435         int pri, cos;
9436
9437         uint32_t pri_map = 0;
9438
9439         for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9440                 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9441                 if (cos < sc->max_cos) {
9442                         sc->prio_to_cos[pri] = cos;
9443                 } else {
9444                         PMD_DRV_LOG(WARNING, sc,
9445                                     "Invalid COS %d for priority %d "
9446                                     "(max COS is %d), setting to 0", cos, pri,
9447                                     (sc->max_cos - 1));
9448                         sc->prio_to_cos[pri] = 0;
9449                 }
9450         }
9451 }
9452
9453 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9454 {
9455         struct {
9456                 uint8_t id;
9457                 uint8_t next;
9458         } pci_cap;
9459         uint16_t status;
9460         struct bnx2x_pci_cap *cap;
9461
9462         cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9463                                          RTE_CACHE_LINE_SIZE);
9464         if (!cap) {
9465                 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9466                 return -ENOMEM;
9467         }
9468
9469 #ifndef __FreeBSD__
9470         pci_read(sc, PCI_STATUS, &status, 2);
9471         if (!(status & PCI_STATUS_CAP_LIST)) {
9472 #else
9473         pci_read(sc, PCIR_STATUS, &status, 2);
9474         if (!(status & PCIM_STATUS_CAPPRESENT)) {
9475 #endif
9476                 PMD_DRV_LOG(NOTICE, sc, "PCIe capability reading failed");
9477                 return -1;
9478         }
9479
9480 #ifndef __FreeBSD__
9481         pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9482 #else
9483         pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9484 #endif
9485         while (pci_cap.next) {
9486                 cap->addr = pci_cap.next & ~3;
9487                 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9488                 if (pci_cap.id == 0xff)
9489                         break;
9490                 cap->id = pci_cap.id;
9491                 cap->type = BNX2X_PCI_CAP;
9492                 cap->next = rte_zmalloc("pci_cap",
9493                                         sizeof(struct bnx2x_pci_cap),
9494                                         RTE_CACHE_LINE_SIZE);
9495                 if (!cap->next) {
9496                         PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9497                         return -ENOMEM;
9498                 }
9499                 cap = cap->next;
9500         }
9501
9502         return 0;
9503 }
9504
9505 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9506 {
9507         if (IS_VF(sc)) {
9508                 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9509                                         sc->igu_sb_cnt);
9510                 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9511                                         sc->igu_sb_cnt);
9512         } else {
9513                 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9514                 sc->max_tx_queues = sc->max_rx_queues;
9515         }
9516 }
9517
9518 #define FW_HEADER_LEN 104
9519 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9520 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9521
9522 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9523 {
9524         const char *fwname;
9525         int f;
9526         struct stat st;
9527
9528         fwname = sc->devinfo.device_id == CHIP_NUM_57711
9529                 ? FW_NAME_57711 : FW_NAME_57810;
9530         f = open(fwname, O_RDONLY);
9531         if (f < 0) {
9532                 PMD_DRV_LOG(NOTICE, sc, "Can't open firmware file");
9533                 return;
9534         }
9535
9536         if (fstat(f, &st) < 0) {
9537                 PMD_DRV_LOG(NOTICE, sc, "Can't stat firmware file");
9538                 close(f);
9539                 return;
9540         }
9541
9542         sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9543         if (!sc->firmware) {
9544                 PMD_DRV_LOG(NOTICE, sc, "Can't allocate memory for firmware");
9545                 close(f);
9546                 return;
9547         }
9548
9549         if (read(f, sc->firmware, st.st_size) != st.st_size) {
9550                 PMD_DRV_LOG(NOTICE, sc, "Can't read firmware data");
9551                 close(f);
9552                 return;
9553         }
9554         close(f);
9555
9556         sc->fw_len = st.st_size;
9557         if (sc->fw_len < FW_HEADER_LEN) {
9558                 PMD_DRV_LOG(NOTICE, sc,
9559                             "Invalid fw size: %" PRIu64, sc->fw_len);
9560                 return;
9561         }
9562         PMD_DRV_LOG(DEBUG, sc, "fw_len = %" PRIu64, sc->fw_len);
9563 }
9564
9565 static void
9566 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9567 {
9568         uint32_t *src = (uint32_t *) data;
9569         uint32_t i, j, tmp;
9570
9571         for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9572                 tmp = rte_be_to_cpu_32(src[j]);
9573                 dst[i].op = (tmp >> 24) & 0xFF;
9574                 dst[i].offset = tmp & 0xFFFFFF;
9575                 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9576         }
9577 }
9578
9579 static void
9580 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9581 {
9582         uint16_t *src = (uint16_t *) data;
9583         uint32_t i;
9584
9585         for (i = 0; i < len / 2; ++i)
9586                 dst[i] = rte_be_to_cpu_16(src[i]);
9587 }
9588
9589 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9590 {
9591         uint32_t *src = (uint32_t *) data;
9592         uint32_t i;
9593
9594         for (i = 0; i < len / 4; ++i)
9595                 dst[i] = rte_be_to_cpu_32(src[i]);
9596 }
9597
9598 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9599 {
9600         uint32_t *src = (uint32_t *) data;
9601         uint32_t i, j, tmp;
9602
9603         for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9604                 dst[i].base = rte_be_to_cpu_32(src[j++]);
9605                 tmp = rte_be_to_cpu_32(src[j]);
9606                 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9607                 dst[i].m2 = tmp & 0xFFFF;
9608                 ++j;
9609                 tmp = rte_be_to_cpu_32(src[j]);
9610                 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9611                 dst[i].size = tmp & 0xFFFF;
9612         }
9613 }
9614
9615 /*
9616 * Device attach function.
9617 *
9618 * Allocates device resources, performs secondary chip identification, and
9619 * initializes driver instance variables. This function is called from driver
9620 * load after a successful probe.
9621 *
9622 * Returns:
9623 *   0 = Success, >0 = Failure
9624 */
9625 int bnx2x_attach(struct bnx2x_softc *sc)
9626 {
9627         int rc;
9628
9629         PMD_DRV_LOG(DEBUG, sc, "Starting attach...");
9630
9631         rc = bnx2x_pci_get_caps(sc);
9632         if (rc) {
9633                 PMD_DRV_LOG(NOTICE, sc, "PCIe caps reading was failed");
9634                 return rc;
9635         }
9636
9637         sc->state = BNX2X_STATE_CLOSED;
9638
9639         pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9640
9641         sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9642
9643         /* get PCI capabilites */
9644         bnx2x_probe_pci_caps(sc);
9645
9646         if (sc->devinfo.pcie_msix_cap_reg != 0) {
9647                 uint32_t val;
9648                 pci_read(sc,
9649                          (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9650                          2);
9651                 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9652         } else {
9653                 sc->igu_sb_cnt = 1;
9654         }
9655
9656         /* Init RTE stuff */
9657         bnx2x_init_rte(sc);
9658
9659         if (IS_PF(sc)) {
9660                 /* Enable internal target-read (in case we are probed after PF
9661                  * FLR). Must be done prior to any BAR read access. Only for
9662                  * 57712 and up
9663                  */
9664                 if (!CHIP_IS_E1x(sc)) {
9665                         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9666                                1);
9667                         DELAY(200000);
9668                 }
9669
9670                 /* get device info and set params */
9671                 if (bnx2x_get_device_info(sc) != 0) {
9672                         PMD_DRV_LOG(NOTICE, sc, "getting device info");
9673                         return -ENXIO;
9674                 }
9675
9676 /* get phy settings from shmem and 'and' against admin settings */
9677                 bnx2x_get_phy_info(sc);
9678         } else {
9679                 /* Left mac of VF unfilled, PF should set it for VF */
9680                 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9681         }
9682
9683         sc->wol = 0;
9684
9685         /* set the default MTU (changed via ifconfig) */
9686         sc->mtu = ETHER_MTU;
9687
9688         bnx2x_set_modes_bitmap(sc);
9689
9690         /* need to reset chip if UNDI was active */
9691         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9692 /* init fw_seq */
9693                 sc->fw_seq =
9694                     (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9695                      DRV_MSG_SEQ_NUMBER_MASK);
9696                 bnx2x_prev_unload(sc);
9697         }
9698
9699         bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9700
9701         /* calculate qm_cid_count */
9702         sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9703
9704         sc->max_cos = 1;
9705         bnx2x_init_multi_cos(sc);
9706
9707         return 0;
9708 }
9709
9710 static void
9711 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9712                uint16_t index, uint8_t op, uint8_t update)
9713 {
9714         uint32_t igu_addr = sc->igu_base_addr;
9715         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9716         bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9717 }
9718
9719 static void
9720 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9721            uint16_t index, uint8_t op, uint8_t update)
9722 {
9723         if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9724                 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9725         else {
9726                 uint8_t segment;
9727                 if (CHIP_INT_MODE_IS_BC(sc)) {
9728                         segment = storm;
9729                 } else if (igu_sb_id != sc->igu_dsb_id) {
9730                         segment = IGU_SEG_ACCESS_DEF;
9731                 } else if (storm == ATTENTION_ID) {
9732                         segment = IGU_SEG_ACCESS_ATTN;
9733                 } else {
9734                         segment = IGU_SEG_ACCESS_DEF;
9735                 }
9736                 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9737         }
9738 }
9739
9740 static void
9741 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9742                      uint8_t is_pf)
9743 {
9744         uint32_t data, ctl, cnt = 100;
9745         uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9746         uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9747         uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9748             (idu_sb_id / 32) * 4;
9749         uint32_t sb_bit = 1 << (idu_sb_id % 32);
9750         uint32_t func_encode = func |
9751             (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9752         uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9753
9754         /* Not supported in BC mode */
9755         if (CHIP_INT_MODE_IS_BC(sc)) {
9756                 return;
9757         }
9758
9759         data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9760                  IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9761                 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9762
9763         ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9764                (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9765                (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9766
9767         REG_WR(sc, igu_addr_data, data);
9768
9769         mb();
9770
9771         PMD_DRV_LOG(DEBUG, sc, "write 0x%08x to IGU(via GRC) addr 0x%x",
9772                     ctl, igu_addr_ctl);
9773         REG_WR(sc, igu_addr_ctl, ctl);
9774
9775         mb();
9776
9777         /* wait for clean up to finish */
9778         while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9779                 DELAY(20000);
9780         }
9781
9782         if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9783                 PMD_DRV_LOG(DEBUG, sc,
9784                             "Unable to finish IGU cleanup: "
9785                             "idu_sb_id %d offset %d bit %d (cnt %d)",
9786                             idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9787         }
9788 }
9789
9790 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9791 {
9792         bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9793 }
9794
9795 /*******************/
9796 /* ECORE CALLBACKS */
9797 /*******************/
9798
9799 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9800 {
9801         uint32_t val = 0x1400;
9802
9803         PMD_INIT_FUNC_TRACE(sc);
9804
9805         /* reset_common */
9806         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9807                0xd3ffff7f);
9808
9809         if (CHIP_IS_E3(sc)) {
9810                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9811                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9812         }
9813
9814         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9815 }
9816
9817 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9818 {
9819         uint32_t shmem_base[2];
9820         uint32_t shmem2_base[2];
9821
9822         /* Avoid common init in case MFW supports LFA */
9823         if (SHMEM2_RD(sc, size) >
9824             (uint32_t) offsetof(struct shmem2_region,
9825                                 lfa_host_addr[SC_PORT(sc)])) {
9826                 return;
9827         }
9828
9829         shmem_base[0] = sc->devinfo.shmem_base;
9830         shmem2_base[0] = sc->devinfo.shmem2_base;
9831
9832         if (!CHIP_IS_E1x(sc)) {
9833                 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9834                 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9835         }
9836
9837         elink_common_init_phy(sc, shmem_base, shmem2_base,
9838                               sc->devinfo.chip_id, 0);
9839 }
9840
9841 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9842 {
9843         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9844
9845         val &= ~IGU_PF_CONF_FUNC_EN;
9846
9847         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9848         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9849         REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9850 }
9851
9852 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9853 {
9854         uint16_t devctl;
9855         int r_order, w_order;
9856
9857         devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9858
9859         w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9860         r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9861
9862         ecore_init_pxp_arb(sc, r_order, w_order);
9863 }
9864
9865 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9866 {
9867         uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9868         uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9869         return base + (SC_ABS_FUNC(sc)) * stride;
9870 }
9871
9872 /*
9873  * Called only on E1H or E2.
9874  * When pretending to be PF, the pretend value is the function number 0..7.
9875  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9876  * combination.
9877  */
9878 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9879 {
9880         uint32_t pretend_reg;
9881
9882         if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9883                 return -1;
9884
9885         /* get my own pretend register */
9886         pretend_reg = bnx2x_get_pretend_reg(sc);
9887         REG_WR(sc, pretend_reg, pretend_func_val);
9888         REG_RD(sc, pretend_reg);
9889         return 0;
9890 }
9891
9892 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9893 {
9894         int is_required;
9895         uint32_t val;
9896         int port;
9897
9898         is_required = 0;
9899         val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9900                SHARED_HW_CFG_FAN_FAILURE_MASK);
9901
9902         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9903                 is_required = 1;
9904         }
9905         /*
9906          * The fan failure mechanism is usually related to the PHY type since
9907          * the power consumption of the board is affected by the PHY. Currently,
9908          * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9909          */
9910         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9911                 for (port = PORT_0; port < PORT_MAX; port++) {
9912                         is_required |= elink_fan_failure_det_req(sc,
9913                                                                  sc->
9914                                                                  devinfo.shmem_base,
9915                                                                  sc->
9916                                                                  devinfo.shmem2_base,
9917                                                                  port);
9918                 }
9919         }
9920
9921         if (is_required == 0) {
9922                 return;
9923         }
9924
9925         /* Fan failure is indicated by SPIO 5 */
9926         bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9927
9928         /* set to active low mode */
9929         val = REG_RD(sc, MISC_REG_SPIO_INT);
9930         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
9931         REG_WR(sc, MISC_REG_SPIO_INT, val);
9932
9933         /* enable interrupt to signal the IGU */
9934         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
9935         val |= MISC_SPIO_SPIO5;
9936         REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
9937 }
9938
9939 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
9940 {
9941         uint32_t val;
9942
9943         REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
9944         if (!CHIP_IS_E1x(sc)) {
9945                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
9946         } else {
9947                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
9948         }
9949         REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
9950         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
9951         /*
9952          * mask read length error interrupts in brb for parser
9953          * (parsing unit and 'checksum and crc' unit)
9954          * these errors are legal (PU reads fixed length and CAC can cause
9955          * read length error on truncated packets)
9956          */
9957         REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
9958         REG_WR(sc, QM_REG_QM_INT_MASK, 0);
9959         REG_WR(sc, TM_REG_TM_INT_MASK, 0);
9960         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
9961         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
9962         REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
9963         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
9964         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
9965         REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
9966         REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
9967         REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
9968         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
9969         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
9970         REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
9971         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
9972         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
9973         REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
9974         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
9975         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
9976
9977         val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
9978                PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
9979                PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
9980         if (!CHIP_IS_E1x(sc)) {
9981                 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
9982                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
9983         }
9984         REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
9985
9986         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
9987         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
9988         REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
9989         /*      REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
9990
9991         if (!CHIP_IS_E1x(sc)) {
9992 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
9993                 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
9994         }
9995
9996         REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
9997         REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
9998         /*      REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
9999         REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10000 }
10001
10002 /**
10003  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10004  *
10005  * @sc:     driver handle
10006  */
10007 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10008 {
10009         uint8_t abs_func_id;
10010         uint32_t val;
10011
10012         PMD_DRV_LOG(DEBUG, sc,
10013                     "starting common init for func %d", SC_ABS_FUNC(sc));
10014
10015         /*
10016          * take the RESET lock to protect undi_unload flow from accessing
10017          * registers while we are resetting the chip
10018          */
10019         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10020
10021         bnx2x_reset_common(sc);
10022
10023         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10024
10025         val = 0xfffc;
10026         if (CHIP_IS_E3(sc)) {
10027                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10028                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10029         }
10030
10031         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10032
10033         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10034
10035         ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10036
10037         if (!CHIP_IS_E1x(sc)) {
10038 /*
10039  * 4-port mode or 2-port mode we need to turn off master-enable for
10040  * everyone. After that we turn it back on for self. So, we disregard
10041  * multi-function, and always disable all functions on the given path,
10042  * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10043  */
10044                 for (abs_func_id = SC_PATH(sc);
10045                      abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10046                         if (abs_func_id == SC_ABS_FUNC(sc)) {
10047                                 REG_WR(sc,
10048                                        PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10049                                        1);
10050                                 continue;
10051                         }
10052
10053                         bnx2x_pretend_func(sc, abs_func_id);
10054
10055                         /* clear pf enable */
10056                         bnx2x_pf_disable(sc);
10057
10058                         bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10059                 }
10060         }
10061
10062         ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10063
10064         ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10065         bnx2x_init_pxp(sc);
10066
10067 #ifdef __BIG_ENDIAN
10068         REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10069         REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10070         REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10071         REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10072         REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10073         /* make sure this value is 0 */
10074         REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10075
10076         //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10077         REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10078         REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10079         REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10080         REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10081 #endif
10082
10083         ecore_ilt_init_page_size(sc, INITOP_SET);
10084
10085         if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10086                 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10087         }
10088
10089         /* let the HW do it's magic... */
10090         DELAY(100000);
10091
10092         /* finish PXP init */
10093
10094         val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10095         if (val != 1) {
10096                 PMD_DRV_LOG(NOTICE, sc, "PXP2 CFG failed");
10097                 return -1;
10098         }
10099         val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10100         if (val != 1) {
10101                 PMD_DRV_LOG(NOTICE, sc, "PXP2 RD_INIT failed");
10102                 return -1;
10103         }
10104
10105         /*
10106          * Timer bug workaround for E2 only. We need to set the entire ILT to have
10107          * entries with value "0" and valid bit on. This needs to be done by the
10108          * first PF that is loaded in a path (i.e. common phase)
10109          */
10110         if (!CHIP_IS_E1x(sc)) {
10111 /*
10112  * In E2 there is a bug in the timers block that can cause function 6 / 7
10113  * (i.e. vnic3) to start even if it is marked as "scan-off".
10114  * This occurs when a different function (func2,3) is being marked
10115  * as "scan-off". Real-life scenario for example: if a driver is being
10116  * load-unloaded while func6,7 are down. This will cause the timer to access
10117  * the ilt, translate to a logical address and send a request to read/write.
10118  * Since the ilt for the function that is down is not valid, this will cause
10119  * a translation error which is unrecoverable.
10120  * The Workaround is intended to make sure that when this happens nothing
10121  * fatal will occur. The workaround:
10122  *  1.  First PF driver which loads on a path will:
10123  *      a.  After taking the chip out of reset, by using pretend,
10124  *          it will write "0" to the following registers of
10125  *          the other vnics.
10126  *          REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10127  *          REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10128  *          REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10129  *          And for itself it will write '1' to
10130  *          PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10131  *          dmae-operations (writing to pram for example.)
10132  *          note: can be done for only function 6,7 but cleaner this
10133  *            way.
10134  *      b.  Write zero+valid to the entire ILT.
10135  *      c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
10136  *          VNIC3 (of that port). The range allocated will be the
10137  *          entire ILT. This is needed to prevent  ILT range error.
10138  *  2.  Any PF driver load flow:
10139  *      a.  ILT update with the physical addresses of the allocated
10140  *          logical pages.
10141  *      b.  Wait 20msec. - note that this timeout is needed to make
10142  *          sure there are no requests in one of the PXP internal
10143  *          queues with "old" ILT addresses.
10144  *      c.  PF enable in the PGLC.
10145  *      d.  Clear the was_error of the PF in the PGLC. (could have
10146  *          occurred while driver was down)
10147  *      e.  PF enable in the CFC (WEAK + STRONG)
10148  *      f.  Timers scan enable
10149  *  3.  PF driver unload flow:
10150  *      a.  Clear the Timers scan_en.
10151  *      b.  Polling for scan_on=0 for that PF.
10152  *      c.  Clear the PF enable bit in the PXP.
10153  *      d.  Clear the PF enable in the CFC (WEAK + STRONG)
10154  *      e.  Write zero+valid to all ILT entries (The valid bit must
10155  *          stay set)
10156  *      f.  If this is VNIC 3 of a port then also init
10157  *          first_timers_ilt_entry to zero and last_timers_ilt_entry
10158  *          to the last enrty in the ILT.
10159  *
10160  *      Notes:
10161  *      Currently the PF error in the PGLC is non recoverable.
10162  *      In the future the there will be a recovery routine for this error.
10163  *      Currently attention is masked.
10164  *      Having an MCP lock on the load/unload process does not guarantee that
10165  *      there is no Timer disable during Func6/7 enable. This is because the
10166  *      Timers scan is currently being cleared by the MCP on FLR.
10167  *      Step 2.d can be done only for PF6/7 and the driver can also check if
10168  *      there is error before clearing it. But the flow above is simpler and
10169  *      more general.
10170  *      All ILT entries are written by zero+valid and not just PF6/7
10171  *      ILT entries since in the future the ILT entries allocation for
10172  *      PF-s might be dynamic.
10173  */
10174                 struct ilt_client_info ilt_cli;
10175                 struct ecore_ilt ilt;
10176
10177                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10178                 memset(&ilt, 0, sizeof(struct ecore_ilt));
10179
10180 /* initialize dummy TM client */
10181                 ilt_cli.start = 0;
10182                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10183                 ilt_cli.client_num = ILT_CLIENT_TM;
10184
10185 /*
10186  * Step 1: set zeroes to all ilt page entries with valid bit on
10187  * Step 2: set the timers first/last ilt entry to point
10188  * to the entire range to prevent ILT range error for 3rd/4th
10189  * vnic (this code assumes existence of the vnic)
10190  *
10191  * both steps performed by call to ecore_ilt_client_init_op()
10192  * with dummy TM client
10193  *
10194  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10195  * and his brother are split registers
10196  */
10197
10198                 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10199                 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10200                 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10201
10202                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10203                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10204                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10205         }
10206
10207         REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10208         REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10209
10210         if (!CHIP_IS_E1x(sc)) {
10211                 int factor = 0;
10212
10213                 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10214                 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10215
10216 /* let the HW do it's magic... */
10217                 do {
10218                         DELAY(200000);
10219                         val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10220                 } while (factor-- && (val != 1));
10221
10222                 if (val != 1) {
10223                         PMD_DRV_LOG(NOTICE, sc, "ATC_INIT failed");
10224                         return -1;
10225                 }
10226         }
10227
10228         ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10229
10230         /* clean the DMAE memory */
10231         sc->dmae_ready = 1;
10232         ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10233
10234         ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10235
10236         ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10237
10238         ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10239
10240         ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10241
10242         bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10243         bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10244         bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10245         bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10246
10247         ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10248
10249         /* QM queues pointers table */
10250         ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10251
10252         /* soft reset pulse */
10253         REG_WR(sc, QM_REG_SOFT_RESET, 1);
10254         REG_WR(sc, QM_REG_SOFT_RESET, 0);
10255
10256         if (CNIC_SUPPORT(sc))
10257                 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10258
10259         ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10260         REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10261
10262         if (!CHIP_REV_IS_SLOW(sc)) {
10263 /* enable hw interrupt from doorbell Q */
10264                 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10265         }
10266
10267         ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10268
10269         ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10270         REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10271         REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10272
10273         if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10274                 if (IS_MF_AFEX(sc)) {
10275                         /*
10276                          * configure that AFEX and VLAN headers must be
10277                          * received in AFEX mode
10278                          */
10279                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10280                         REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10281                         REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10282                         REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10283                         REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10284                 } else {
10285                         /*
10286                          * Bit-map indicating which L2 hdrs may appear
10287                          * after the basic Ethernet header
10288                          */
10289                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10290                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10291                 }
10292         }
10293
10294         ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10295         ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10296         ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10297         ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10298
10299         if (!CHIP_IS_E1x(sc)) {
10300 /* reset VFC memories */
10301                 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10302                        VFC_MEMORIES_RST_REG_CAM_RST |
10303                        VFC_MEMORIES_RST_REG_RAM_RST);
10304                 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10305                        VFC_MEMORIES_RST_REG_CAM_RST |
10306                        VFC_MEMORIES_RST_REG_RAM_RST);
10307
10308                 DELAY(20000);
10309         }
10310
10311         ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10312         ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10313         ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10314         ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10315
10316         /* sync semi rtc */
10317         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10318         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10319
10320         ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10321         ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10322         ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10323
10324         if (!CHIP_IS_E1x(sc)) {
10325                 if (IS_MF_AFEX(sc)) {
10326                         /*
10327                          * configure that AFEX and VLAN headers must be
10328                          * sent in AFEX mode
10329                          */
10330                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10331                         REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10332                         REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10333                         REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10334                         REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10335                 } else {
10336                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10337                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10338                 }
10339         }
10340
10341         REG_WR(sc, SRC_REG_SOFT_RST, 1);
10342
10343         ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10344
10345         if (CNIC_SUPPORT(sc)) {
10346                 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10347                 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10348                 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10349                 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10350                 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10351                 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10352                 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10353                 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10354                 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10355                 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10356         }
10357         REG_WR(sc, SRC_REG_SOFT_RST, 0);
10358
10359         if (sizeof(union cdu_context) != 1024) {
10360 /* we currently assume that a context is 1024 bytes */
10361                 PMD_DRV_LOG(NOTICE, sc,
10362                             "please adjust the size of cdu_context(%ld)",
10363                             (long)sizeof(union cdu_context));
10364         }
10365
10366         ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10367         val = (4 << 24) + (0 << 12) + 1024;
10368         REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10369
10370         ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10371
10372         REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10373         /* enable context validation interrupt from CFC */
10374         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10375
10376         /* set the thresholds to prevent CFC/CDU race */
10377         REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10378         ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10379
10380         if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10381                 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10382         }
10383
10384         ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10385         ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10386
10387         /* Reset PCIE errors for debug */
10388         REG_WR(sc, 0x2814, 0xffffffff);
10389         REG_WR(sc, 0x3820, 0xffffffff);
10390
10391         if (!CHIP_IS_E1x(sc)) {
10392                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10393                        (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10394                         PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10395                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10396                        (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10397                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10398                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10399                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10400                        (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10401                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10402                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10403         }
10404
10405         ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10406
10407         /* in E3 this done in per-port section */
10408         if (!CHIP_IS_E3(sc))
10409                 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10410
10411         if (CHIP_IS_E1H(sc)) {
10412 /* not applicable for E2 (and above ...) */
10413                 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10414         }
10415
10416         if (CHIP_REV_IS_SLOW(sc)) {
10417                 DELAY(200000);
10418         }
10419
10420         /* finish CFC init */
10421         val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10422         if (val != 1) {
10423                 PMD_DRV_LOG(NOTICE, sc, "CFC LL_INIT failed");
10424                 return -1;
10425         }
10426         val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10427         if (val != 1) {
10428                 PMD_DRV_LOG(NOTICE, sc, "CFC AC_INIT failed");
10429                 return -1;
10430         }
10431         val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10432         if (val != 1) {
10433                 PMD_DRV_LOG(NOTICE, sc, "CFC CAM_INIT failed");
10434                 return -1;
10435         }
10436         REG_WR(sc, CFC_REG_DEBUG0, 0);
10437
10438         bnx2x_setup_fan_failure_detection(sc);
10439
10440         /* clear PXP2 attentions */
10441         REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10442
10443         bnx2x_enable_blocks_attention(sc);
10444
10445         if (!CHIP_REV_IS_SLOW(sc)) {
10446                 ecore_enable_blocks_parity(sc);
10447         }
10448
10449         if (!BNX2X_NOMCP(sc)) {
10450                 if (CHIP_IS_E1x(sc)) {
10451                         bnx2x_common_init_phy(sc);
10452                 }
10453         }
10454
10455         return 0;
10456 }
10457
10458 /**
10459  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10460  *
10461  * @sc:     driver handle
10462  */
10463 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10464 {
10465         int rc = bnx2x_init_hw_common(sc);
10466
10467         if (rc) {
10468                 return rc;
10469         }
10470
10471         /* In E2 2-PORT mode, same ext phy is used for the two paths */
10472         if (!BNX2X_NOMCP(sc)) {
10473                 bnx2x_common_init_phy(sc);
10474         }
10475
10476         return 0;
10477 }
10478
10479 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10480 {
10481         int port = SC_PORT(sc);
10482         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10483         uint32_t low, high;
10484         uint32_t val;
10485
10486         PMD_DRV_LOG(DEBUG, sc, "starting port init for port %d", port);
10487
10488         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10489
10490         ecore_init_block(sc, BLOCK_MISC, init_phase);
10491         ecore_init_block(sc, BLOCK_PXP, init_phase);
10492         ecore_init_block(sc, BLOCK_PXP2, init_phase);
10493
10494         /*
10495          * Timers bug workaround: disables the pf_master bit in pglue at
10496          * common phase, we need to enable it here before any dmae access are
10497          * attempted. Therefore we manually added the enable-master to the
10498          * port phase (it also happens in the function phase)
10499          */
10500         if (!CHIP_IS_E1x(sc)) {
10501                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10502         }
10503
10504         ecore_init_block(sc, BLOCK_ATC, init_phase);
10505         ecore_init_block(sc, BLOCK_DMAE, init_phase);
10506         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10507         ecore_init_block(sc, BLOCK_QM, init_phase);
10508
10509         ecore_init_block(sc, BLOCK_TCM, init_phase);
10510         ecore_init_block(sc, BLOCK_UCM, init_phase);
10511         ecore_init_block(sc, BLOCK_CCM, init_phase);
10512         ecore_init_block(sc, BLOCK_XCM, init_phase);
10513
10514         /* QM cid (connection) count */
10515         ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10516
10517         if (CNIC_SUPPORT(sc)) {
10518                 ecore_init_block(sc, BLOCK_TM, init_phase);
10519                 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10520                 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10521         }
10522
10523         ecore_init_block(sc, BLOCK_DORQ, init_phase);
10524
10525         ecore_init_block(sc, BLOCK_BRB1, init_phase);
10526
10527         if (CHIP_IS_E1H(sc)) {
10528                 if (IS_MF(sc)) {
10529                         low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10530                 } else if (sc->mtu > 4096) {
10531                         if (BNX2X_ONE_PORT(sc)) {
10532                                 low = 160;
10533                         } else {
10534                                 val = sc->mtu;
10535                                 /* (24*1024 + val*4)/256 */
10536                                 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10537                         }
10538                 } else {
10539                         low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10540                 }
10541                 high = (low + 56);      /* 14*1024/256 */
10542                 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10543                 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10544         }
10545
10546         if (CHIP_IS_MODE_4_PORT(sc)) {
10547                 REG_WR(sc, SC_PORT(sc) ?
10548                        BRB1_REG_MAC_GUARANTIED_1 :
10549                        BRB1_REG_MAC_GUARANTIED_0, 40);
10550         }
10551
10552         ecore_init_block(sc, BLOCK_PRS, init_phase);
10553         if (CHIP_IS_E3B0(sc)) {
10554                 if (IS_MF_AFEX(sc)) {
10555                         /* configure headers for AFEX mode */
10556                         if (SC_PORT(sc)) {
10557                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10558                                        0xE);
10559                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10560                                        0x6);
10561                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10562                         } else {
10563                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10564                                        0xE);
10565                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10566                                        0x6);
10567                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10568                         }
10569                 } else {
10570                         /* Ovlan exists only if we are in multi-function +
10571                          * switch-dependent mode, in switch-independent there
10572                          * is no ovlan headers
10573                          */
10574                         REG_WR(sc, SC_PORT(sc) ?
10575                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10576                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10577                                (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10578                 }
10579         }
10580
10581         ecore_init_block(sc, BLOCK_TSDM, init_phase);
10582         ecore_init_block(sc, BLOCK_CSDM, init_phase);
10583         ecore_init_block(sc, BLOCK_USDM, init_phase);
10584         ecore_init_block(sc, BLOCK_XSDM, init_phase);
10585
10586         ecore_init_block(sc, BLOCK_TSEM, init_phase);
10587         ecore_init_block(sc, BLOCK_USEM, init_phase);
10588         ecore_init_block(sc, BLOCK_CSEM, init_phase);
10589         ecore_init_block(sc, BLOCK_XSEM, init_phase);
10590
10591         ecore_init_block(sc, BLOCK_UPB, init_phase);
10592         ecore_init_block(sc, BLOCK_XPB, init_phase);
10593
10594         ecore_init_block(sc, BLOCK_PBF, init_phase);
10595
10596         if (CHIP_IS_E1x(sc)) {
10597 /* configure PBF to work without PAUSE mtu 9000 */
10598                 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10599
10600 /* update threshold */
10601                 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10602 /* update init credit */
10603                 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10604                        (9040 / 16) + 553 - 22);
10605
10606 /* probe changes */
10607                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10608                 DELAY(50);
10609                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10610         }
10611
10612         if (CNIC_SUPPORT(sc)) {
10613                 ecore_init_block(sc, BLOCK_SRC, init_phase);
10614         }
10615
10616         ecore_init_block(sc, BLOCK_CDU, init_phase);
10617         ecore_init_block(sc, BLOCK_CFC, init_phase);
10618         ecore_init_block(sc, BLOCK_HC, init_phase);
10619         ecore_init_block(sc, BLOCK_IGU, init_phase);
10620         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10621         /* init aeu_mask_attn_func_0/1:
10622          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10623          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10624          *             bits 4-7 are used for "per vn group attention" */
10625         val = IS_MF(sc) ? 0xF7 : 0x7;
10626         val |= 0x10;
10627         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10628
10629         ecore_init_block(sc, BLOCK_NIG, init_phase);
10630
10631         if (!CHIP_IS_E1x(sc)) {
10632 /* Bit-map indicating which L2 hdrs may appear after the
10633  * basic Ethernet header
10634  */
10635                 if (IS_MF_AFEX(sc)) {
10636                         REG_WR(sc, SC_PORT(sc) ?
10637                                NIG_REG_P1_HDRS_AFTER_BASIC :
10638                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10639                 } else {
10640                         REG_WR(sc, SC_PORT(sc) ?
10641                                NIG_REG_P1_HDRS_AFTER_BASIC :
10642                                NIG_REG_P0_HDRS_AFTER_BASIC,
10643                                IS_MF_SD(sc) ? 7 : 6);
10644                 }
10645
10646                 if (CHIP_IS_E3(sc)) {
10647                         REG_WR(sc, SC_PORT(sc) ?
10648                                NIG_REG_LLH1_MF_MODE :
10649                                NIG_REG_LLH_MF_MODE, IS_MF(sc));
10650                 }
10651         }
10652         if (!CHIP_IS_E3(sc)) {
10653                 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10654         }
10655
10656         /* 0x2 disable mf_ov, 0x1 enable */
10657         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10658                (IS_MF_SD(sc) ? 0x1 : 0x2));
10659
10660         if (!CHIP_IS_E1x(sc)) {
10661                 val = 0;
10662                 switch (sc->devinfo.mf_info.mf_mode) {
10663                 case MULTI_FUNCTION_SD:
10664                         val = 1;
10665                         break;
10666                 case MULTI_FUNCTION_SI:
10667                 case MULTI_FUNCTION_AFEX:
10668                         val = 2;
10669                         break;
10670                 }
10671
10672                 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10673                             NIG_REG_LLH0_CLS_TYPE), val);
10674         }
10675         REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10676         REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10677         REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10678
10679         /* If SPIO5 is set to generate interrupts, enable it for this port */
10680         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10681         if (val & MISC_SPIO_SPIO5) {
10682                 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10683                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10684                 val = REG_RD(sc, reg_addr);
10685                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10686                 REG_WR(sc, reg_addr, val);
10687         }
10688
10689         return 0;
10690 }
10691
10692 static uint32_t
10693 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10694                        uint32_t expected, uint32_t poll_count)
10695 {
10696         uint32_t cur_cnt = poll_count;
10697         uint32_t val;
10698
10699         while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10700                 DELAY(FLR_WAIT_INTERVAL);
10701         }
10702
10703         return val;
10704 }
10705
10706 static int
10707 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10708                               __rte_unused const char *msg, uint32_t poll_cnt)
10709 {
10710         uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10711
10712         if (val != 0) {
10713                 PMD_DRV_LOG(NOTICE, sc, "%s usage count=%d", msg, val);
10714                 return -1;
10715         }
10716
10717         return 0;
10718 }
10719
10720 /* Common routines with VF FLR cleanup */
10721 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10722 {
10723         /* adjust polling timeout */
10724         if (CHIP_REV_IS_EMUL(sc)) {
10725                 return FLR_POLL_CNT * 2000;
10726         }
10727
10728         if (CHIP_REV_IS_FPGA(sc)) {
10729                 return FLR_POLL_CNT * 120;
10730         }
10731
10732         return FLR_POLL_CNT;
10733 }
10734
10735 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10736 {
10737         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10738         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10739                                           CFC_REG_NUM_LCIDS_INSIDE_PF,
10740                                           "CFC PF usage counter timed out",
10741                                           poll_cnt)) {
10742                 return -1;
10743         }
10744
10745         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10746         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10747                                           DORQ_REG_PF_USAGE_CNT,
10748                                           "DQ PF usage counter timed out",
10749                                           poll_cnt)) {
10750                 return -1;
10751         }
10752
10753         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10754         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10755                                           QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10756                                           "QM PF usage counter timed out",
10757                                           poll_cnt)) {
10758                 return -1;
10759         }
10760
10761         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10762         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10763                                           TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10764                                           "Timers VNIC usage counter timed out",
10765                                           poll_cnt)) {
10766                 return -1;
10767         }
10768
10769         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10770                                           TM_REG_LIN0_NUM_SCANS +
10771                                           4 * SC_PORT(sc),
10772                                           "Timers NUM_SCANS usage counter timed out",
10773                                           poll_cnt)) {
10774                 return -1;
10775         }
10776
10777         /* Wait DMAE PF usage counter to zero */
10778         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10779                                           dmae_reg_go_c[INIT_DMAE_C(sc)],
10780                                           "DMAE dommand register timed out",
10781                                           poll_cnt)) {
10782                 return -1;
10783         }
10784
10785         return 0;
10786 }
10787
10788 #define OP_GEN_PARAM(param)                                            \
10789         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10790 #define OP_GEN_TYPE(type)                                           \
10791         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10792 #define OP_GEN_AGG_VECT(index)                                             \
10793         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10794
10795 static int
10796 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10797                      uint32_t poll_cnt)
10798 {
10799         uint32_t op_gen_command = 0;
10800         uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10801                               CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10802         int ret = 0;
10803
10804         if (REG_RD(sc, comp_addr)) {
10805                 PMD_DRV_LOG(NOTICE, sc,
10806                             "Cleanup complete was not 0 before sending");
10807                 return -1;
10808         }
10809
10810         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10811         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10812         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10813         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10814
10815         REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10816
10817         if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10818                 PMD_DRV_LOG(NOTICE, sc, "FW final cleanup did not succeed");
10819                 PMD_DRV_LOG(DEBUG, sc, "At timeout completion address contained %x",
10820                             (REG_RD(sc, comp_addr)));
10821                 rte_panic("FLR cleanup failed");
10822                 return -1;
10823         }
10824
10825         /* Zero completion for nxt FLR */
10826         REG_WR(sc, comp_addr, 0);
10827
10828         return ret;
10829 }
10830
10831 static void
10832 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10833                        uint32_t poll_count)
10834 {
10835         uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10836         uint32_t cur_cnt = poll_count;
10837
10838         crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10839         crd = crd_start = REG_RD(sc, regs->crd);
10840         init_crd = REG_RD(sc, regs->init_crd);
10841
10842         while ((crd != init_crd) &&
10843                ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10844                 (init_crd - crd_start))) {
10845                 if (cur_cnt--) {
10846                         DELAY(FLR_WAIT_INTERVAL);
10847                         crd = REG_RD(sc, regs->crd);
10848                         crd_freed = REG_RD(sc, regs->crd_freed);
10849                 } else {
10850                         break;
10851                 }
10852         }
10853 }
10854
10855 static void
10856 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10857                        uint32_t poll_count)
10858 {
10859         uint32_t occup, to_free, freed, freed_start;
10860         uint32_t cur_cnt = poll_count;
10861
10862         occup = to_free = REG_RD(sc, regs->lines_occup);
10863         freed = freed_start = REG_RD(sc, regs->lines_freed);
10864
10865         while (occup &&
10866                ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10867                 to_free)) {
10868                 if (cur_cnt--) {
10869                         DELAY(FLR_WAIT_INTERVAL);
10870                         occup = REG_RD(sc, regs->lines_occup);
10871                         freed = REG_RD(sc, regs->lines_freed);
10872                 } else {
10873                         break;
10874                 }
10875         }
10876 }
10877
10878 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10879 {
10880         struct pbf_pN_cmd_regs cmd_regs[] = {
10881                 {0, (CHIP_IS_E3B0(sc)) ?
10882                  PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10883                  (CHIP_IS_E3B0(sc)) ?
10884                  PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10885                 {1, (CHIP_IS_E3B0(sc)) ?
10886                  PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10887                  (CHIP_IS_E3B0(sc)) ?
10888                  PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10889                 {4, (CHIP_IS_E3B0(sc)) ?
10890                  PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10891                  (CHIP_IS_E3B0(sc)) ?
10892                  PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10893                  PBF_REG_P4_TQ_LINES_FREED_CNT}
10894         };
10895
10896         struct pbf_pN_buf_regs buf_regs[] = {
10897                 {0, (CHIP_IS_E3B0(sc)) ?
10898                  PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10899                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10900                  (CHIP_IS_E3B0(sc)) ?
10901                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10902                  PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10903                 {1, (CHIP_IS_E3B0(sc)) ?
10904                  PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10905                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10906                  (CHIP_IS_E3B0(sc)) ?
10907                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10908                  PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10909                 {4, (CHIP_IS_E3B0(sc)) ?
10910                  PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10911                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10912                  (CHIP_IS_E3B0(sc)) ?
10913                  PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10914                  PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10915         };
10916
10917         uint32_t i;
10918
10919         /* Verify the command queues are flushed P0, P1, P4 */
10920         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10921                 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10922         }
10923
10924         /* Verify the transmission buffers are flushed P0, P1, P4 */
10925         for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10926                 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
10927         }
10928 }
10929
10930 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
10931 {
10932         __rte_unused uint32_t val;
10933
10934         val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
10935         PMD_DRV_LOG(DEBUG, sc, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
10936
10937         val = REG_RD(sc, PBF_REG_DISABLE_PF);
10938         PMD_DRV_LOG(DEBUG, sc, "PBF_REG_DISABLE_PF is 0x%x", val);
10939
10940         val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
10941         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
10942
10943         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
10944         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
10945
10946         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
10947         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
10948
10949         val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
10950         PMD_DRV_LOG(DEBUG, sc,
10951                     "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
10952
10953         val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
10954         PMD_DRV_LOG(DEBUG, sc,
10955                     "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
10956
10957         val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
10958         PMD_DRV_LOG(DEBUG, sc, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
10959                     val);
10960 }
10961
10962 /**
10963  *      bnx2x_pf_flr_clnup
10964  *      a. re-enable target read on the PF
10965  *      b. poll cfc per function usgae counter
10966  *      c. poll the qm perfunction usage counter
10967  *      d. poll the tm per function usage counter
10968  *      e. poll the tm per function scan-done indication
10969  *      f. clear the dmae channel associated wit hthe PF
10970  *      g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
10971  *      h. call the common flr cleanup code with -1 (pf indication)
10972  */
10973 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
10974 {
10975         uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
10976
10977         /* Re-enable PF target read access */
10978         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10979
10980         /* Poll HW usage counters */
10981         if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
10982                 return -1;
10983         }
10984
10985         /* Zero the igu 'trailing edge' and 'leading edge' */
10986
10987         /* Send the FW cleanup command */
10988         if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
10989                 return -1;
10990         }
10991
10992         /* ATC cleanup */
10993
10994         /* Verify TX hw is flushed */
10995         bnx2x_tx_hw_flushed(sc, poll_cnt);
10996
10997         /* Wait 100ms (not adjusted according to platform) */
10998         DELAY(100000);
10999
11000         /* Verify no pending pci transactions */
11001         if (bnx2x_is_pcie_pending(sc)) {
11002                 PMD_DRV_LOG(NOTICE, sc, "PCIE Transactions still pending");
11003         }
11004
11005         /* Debug */
11006         bnx2x_hw_enable_status(sc);
11007
11008         /*
11009          * Master enable - Due to WB DMAE writes performed before this
11010          * register is re-initialized as part of the regular function init
11011          */
11012         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11013
11014         return 0;
11015 }
11016
11017 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11018 {
11019         int port = SC_PORT(sc);
11020         int func = SC_FUNC(sc);
11021         int init_phase = PHASE_PF0 + func;
11022         struct ecore_ilt *ilt = sc->ilt;
11023         uint16_t cdu_ilt_start;
11024         uint32_t addr, val;
11025         uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11026         int main_mem_width, rc;
11027         uint32_t i;
11028
11029         PMD_DRV_LOG(DEBUG, sc, "starting func init for func %d", func);
11030
11031         /* FLR cleanup */
11032         if (!CHIP_IS_E1x(sc)) {
11033                 rc = bnx2x_pf_flr_clnup(sc);
11034                 if (rc) {
11035                         PMD_DRV_LOG(NOTICE, sc, "FLR cleanup failed!");
11036                         return rc;
11037                 }
11038         }
11039
11040         /* set MSI reconfigure capability */
11041         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11042                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11043                 val = REG_RD(sc, addr);
11044                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11045                 REG_WR(sc, addr, val);
11046         }
11047
11048         ecore_init_block(sc, BLOCK_PXP, init_phase);
11049         ecore_init_block(sc, BLOCK_PXP2, init_phase);
11050
11051         ilt = sc->ilt;
11052         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11053
11054         for (i = 0; i < L2_ILT_LINES(sc); i++) {
11055                 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11056                 ilt->lines[cdu_ilt_start + i].page_mapping =
11057                     (rte_iova_t)sc->context[i].vcxt_dma.paddr;
11058                 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11059         }
11060         ecore_ilt_init_op(sc, INITOP_SET);
11061
11062         REG_WR(sc, PRS_REG_NIC_MODE, 1);
11063
11064         if (!CHIP_IS_E1x(sc)) {
11065                 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11066
11067 /* Turn on a single ISR mode in IGU if driver is going to use
11068  * INT#x or MSI
11069  */
11070                 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11071                     || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11072                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11073                 }
11074
11075 /*
11076  * Timers workaround bug: function init part.
11077  * Need to wait 20msec after initializing ILT,
11078  * needed to make sure there are no requests in
11079  * one of the PXP internal queues with "old" ILT addresses
11080  */
11081                 DELAY(20000);
11082
11083 /*
11084  * Master enable - Due to WB DMAE writes performed before this
11085  * register is re-initialized as part of the regular function
11086  * init
11087  */
11088                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11089 /* Enable the function in IGU */
11090                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11091         }
11092
11093         sc->dmae_ready = 1;
11094
11095         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11096
11097         if (!CHIP_IS_E1x(sc))
11098                 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11099
11100         ecore_init_block(sc, BLOCK_ATC, init_phase);
11101         ecore_init_block(sc, BLOCK_DMAE, init_phase);
11102         ecore_init_block(sc, BLOCK_NIG, init_phase);
11103         ecore_init_block(sc, BLOCK_SRC, init_phase);
11104         ecore_init_block(sc, BLOCK_MISC, init_phase);
11105         ecore_init_block(sc, BLOCK_TCM, init_phase);
11106         ecore_init_block(sc, BLOCK_UCM, init_phase);
11107         ecore_init_block(sc, BLOCK_CCM, init_phase);
11108         ecore_init_block(sc, BLOCK_XCM, init_phase);
11109         ecore_init_block(sc, BLOCK_TSEM, init_phase);
11110         ecore_init_block(sc, BLOCK_USEM, init_phase);
11111         ecore_init_block(sc, BLOCK_CSEM, init_phase);
11112         ecore_init_block(sc, BLOCK_XSEM, init_phase);
11113
11114         if (!CHIP_IS_E1x(sc))
11115                 REG_WR(sc, QM_REG_PF_EN, 1);
11116
11117         if (!CHIP_IS_E1x(sc)) {
11118                 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11119                 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11120                 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11121                 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11122         }
11123         ecore_init_block(sc, BLOCK_QM, init_phase);
11124
11125         ecore_init_block(sc, BLOCK_TM, init_phase);
11126         ecore_init_block(sc, BLOCK_DORQ, init_phase);
11127
11128         ecore_init_block(sc, BLOCK_BRB1, init_phase);
11129         ecore_init_block(sc, BLOCK_PRS, init_phase);
11130         ecore_init_block(sc, BLOCK_TSDM, init_phase);
11131         ecore_init_block(sc, BLOCK_CSDM, init_phase);
11132         ecore_init_block(sc, BLOCK_USDM, init_phase);
11133         ecore_init_block(sc, BLOCK_XSDM, init_phase);
11134         ecore_init_block(sc, BLOCK_UPB, init_phase);
11135         ecore_init_block(sc, BLOCK_XPB, init_phase);
11136         ecore_init_block(sc, BLOCK_PBF, init_phase);
11137         if (!CHIP_IS_E1x(sc))
11138                 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11139
11140         ecore_init_block(sc, BLOCK_CDU, init_phase);
11141
11142         ecore_init_block(sc, BLOCK_CFC, init_phase);
11143
11144         if (!CHIP_IS_E1x(sc))
11145                 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11146
11147         if (IS_MF(sc)) {
11148                 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11149                 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11150         }
11151
11152         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11153
11154         /* HC init per function */
11155         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11156                 if (CHIP_IS_E1H(sc)) {
11157                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11158
11159                         REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11160                         REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11161                 }
11162                 ecore_init_block(sc, BLOCK_HC, init_phase);
11163
11164         } else {
11165                 uint32_t num_segs, sb_idx, prod_offset;
11166
11167                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11168
11169                 if (!CHIP_IS_E1x(sc)) {
11170                         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11171                         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11172                 }
11173
11174                 ecore_init_block(sc, BLOCK_IGU, init_phase);
11175
11176                 if (!CHIP_IS_E1x(sc)) {
11177                         int dsb_idx = 0;
11178         /**
11179          * Producer memory:
11180          * E2 mode: address 0-135 match to the mapping memory;
11181          * 136 - PF0 default prod; 137 - PF1 default prod;
11182          * 138 - PF2 default prod; 139 - PF3 default prod;
11183          * 140 - PF0 attn prod;    141 - PF1 attn prod;
11184          * 142 - PF2 attn prod;    143 - PF3 attn prod;
11185          * 144-147 reserved.
11186          *
11187          * E1.5 mode - In backward compatible mode;
11188          * for non default SB; each even line in the memory
11189          * holds the U producer and each odd line hold
11190          * the C producer. The first 128 producers are for
11191          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11192          * producers are for the DSB for each PF.
11193          * Each PF has five segments: (the order inside each
11194          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11195          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11196          * 144-147 attn prods;
11197          */
11198                         /* non-default-status-blocks */
11199                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11200                             IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11201                         for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11202                                 prod_offset = (sc->igu_base_sb + sb_idx) *
11203                                     num_segs;
11204
11205                                 for (i = 0; i < num_segs; i++) {
11206                                         addr = IGU_REG_PROD_CONS_MEMORY +
11207                                             (prod_offset + i) * 4;
11208                                         REG_WR(sc, addr, 0);
11209                                 }
11210                                 /* send consumer update with value 0 */
11211                                 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11212                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11213                                 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11214                         }
11215
11216                         /* default-status-blocks */
11217                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11218                             IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11219
11220                         if (CHIP_IS_MODE_4_PORT(sc))
11221                                 dsb_idx = SC_FUNC(sc);
11222                         else
11223                                 dsb_idx = SC_VN(sc);
11224
11225                         prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11226                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
11227                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
11228
11229                         /*
11230                          * igu prods come in chunks of E1HVN_MAX (4) -
11231                          * does not matters what is the current chip mode
11232                          */
11233                         for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11234                                 addr = IGU_REG_PROD_CONS_MEMORY +
11235                                     (prod_offset + i) * 4;
11236                                 REG_WR(sc, addr, 0);
11237                         }
11238                         /* send consumer update with 0 */
11239                         if (CHIP_INT_MODE_IS_BC(sc)) {
11240                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11241                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11242                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11243                                            CSTORM_ID, 0, IGU_INT_NOP, 1);
11244                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11245                                            XSTORM_ID, 0, IGU_INT_NOP, 1);
11246                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11247                                            TSTORM_ID, 0, IGU_INT_NOP, 1);
11248                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11249                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11250                         } else {
11251                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11252                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11253                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11254                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11255                         }
11256                         bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11257
11258                         /* !!! these should become driver const once
11259                            rf-tool supports split-68 const */
11260                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11261                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11262                         REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11263                         REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11264                         REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11265                         REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11266                 }
11267         }
11268
11269         /* Reset PCIE errors for debug */
11270         REG_WR(sc, 0x2114, 0xffffffff);
11271         REG_WR(sc, 0x2120, 0xffffffff);
11272
11273         if (CHIP_IS_E1x(sc)) {
11274                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2;    /*dwords */
11275                 main_mem_base = HC_REG_MAIN_MEMORY +
11276                     SC_PORT(sc) * (main_mem_size * 4);
11277                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11278                 main_mem_width = 8;
11279
11280                 val = REG_RD(sc, main_mem_prty_clr);
11281                 if (val) {
11282                         PMD_DRV_LOG(DEBUG, sc,
11283                                     "Parity errors in HC block during function init (0x%x)!",
11284                                     val);
11285                 }
11286
11287 /* Clear "false" parity errors in MSI-X table */
11288                 for (i = main_mem_base;
11289                      i < main_mem_base + main_mem_size * 4;
11290                      i += main_mem_width) {
11291                         bnx2x_read_dmae(sc, i, main_mem_width / 4);
11292                         bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11293                                        i, main_mem_width / 4);
11294                 }
11295 /* Clear HC parity attention */
11296                 REG_RD(sc, main_mem_prty_clr);
11297         }
11298
11299         /* Enable STORMs SP logging */
11300         REG_WR8(sc, BAR_USTRORM_INTMEM +
11301                 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11302         REG_WR8(sc, BAR_TSTRORM_INTMEM +
11303                 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11304         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11305                 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11306         REG_WR8(sc, BAR_XSTRORM_INTMEM +
11307                 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11308
11309         elink_phy_probe(&sc->link_params);
11310
11311         return 0;
11312 }
11313
11314 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11315 {
11316         if (!BNX2X_NOMCP(sc)) {
11317                 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11318         } else {
11319                 if (!CHIP_REV_IS_SLOW(sc)) {
11320                         PMD_DRV_LOG(WARNING, sc,
11321                                     "Bootcode is missing - cannot reset link");
11322                 }
11323         }
11324 }
11325
11326 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11327 {
11328         int port = SC_PORT(sc);
11329         uint32_t val;
11330
11331         /* reset physical Link */
11332         bnx2x_link_reset(sc);
11333
11334         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11335
11336         /* Do not rcv packets to BRB */
11337         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11338         /* Do not direct rcv packets that are not for MCP to the BRB */
11339         REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11340                     NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11341
11342         /* Configure AEU */
11343         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11344
11345         DELAY(100000);
11346
11347         /* Check for BRB port occupancy */
11348         val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11349         if (val) {
11350                 PMD_DRV_LOG(DEBUG, sc,
11351                             "BRB1 is not empty, %d blocks are occupied", val);
11352         }
11353 }
11354
11355 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr)
11356 {
11357         int reg;
11358         uint32_t wb_write[2];
11359
11360         reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11361
11362         wb_write[0] = ONCHIP_ADDR1(addr);
11363         wb_write[1] = ONCHIP_ADDR2(addr);
11364         REG_WR_DMAE(sc, reg, wb_write, 2);
11365 }
11366
11367 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11368 {
11369         uint32_t i, base = FUNC_ILT_BASE(func);
11370         for (i = base; i < base + ILT_PER_FUNC; i++) {
11371                 bnx2x_ilt_wr(sc, i, 0);
11372         }
11373 }
11374
11375 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11376 {
11377         struct bnx2x_fastpath *fp;
11378         int port = SC_PORT(sc);
11379         int func = SC_FUNC(sc);
11380         int i;
11381
11382         /* Disable the function in the FW */
11383         REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11384         REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11385         REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11386         REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11387
11388         /* FP SBs */
11389         FOR_EACH_ETH_QUEUE(sc, i) {
11390                 fp = &sc->fp[i];
11391                 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11392                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11393                         SB_DISABLED);
11394         }
11395
11396         /* SP SB */
11397         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11398                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11399
11400         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11401                 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11402                        0);
11403         }
11404
11405         /* Configure IGU */
11406         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11407                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11408                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11409         } else {
11410                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11411                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11412         }
11413
11414         if (CNIC_LOADED(sc)) {
11415 /* Disable Timer scan */
11416                 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11417 /*
11418  * Wait for at least 10ms and up to 2 second for the timers
11419  * scan to complete
11420  */
11421                 for (i = 0; i < 200; i++) {
11422                         DELAY(10000);
11423                         if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11424                                 break;
11425                 }
11426         }
11427
11428         /* Clear ILT */
11429         bnx2x_clear_func_ilt(sc, func);
11430
11431         /*
11432          * Timers workaround bug for E2: if this is vnic-3,
11433          * we need to set the entire ilt range for this timers.
11434          */
11435         if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11436                 struct ilt_client_info ilt_cli;
11437 /* use dummy TM client */
11438                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11439                 ilt_cli.start = 0;
11440                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11441                 ilt_cli.client_num = ILT_CLIENT_TM;
11442
11443                 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11444         }
11445
11446         /* this assumes that reset_port() called before reset_func() */
11447         if (!CHIP_IS_E1x(sc)) {
11448                 bnx2x_pf_disable(sc);
11449         }
11450
11451         sc->dmae_ready = 0;
11452 }
11453
11454 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11455 {
11456         rte_free(sc->init_ops);
11457         rte_free(sc->init_ops_offsets);
11458         rte_free(sc->init_data);
11459         rte_free(sc->iro_array);
11460 }
11461
11462 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11463 {
11464         uint32_t len, i;
11465         uint8_t *p = sc->firmware;
11466         uint32_t off[24];
11467
11468         for (i = 0; i < 24; ++i)
11469                 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11470
11471         len = off[0];
11472         sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11473         if (!sc->init_ops)
11474                 goto alloc_failed;
11475         bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11476
11477         len = off[2];
11478         sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11479         if (!sc->init_ops_offsets)
11480                 goto alloc_failed;
11481         bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11482
11483         len = off[4];
11484         sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11485         if (!sc->init_data)
11486                 goto alloc_failed;
11487         bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11488
11489         sc->tsem_int_table_data = p + off[7];
11490         sc->tsem_pram_data = p + off[9];
11491         sc->usem_int_table_data = p + off[11];
11492         sc->usem_pram_data = p + off[13];
11493         sc->csem_int_table_data = p + off[15];
11494         sc->csem_pram_data = p + off[17];
11495         sc->xsem_int_table_data = p + off[19];
11496         sc->xsem_pram_data = p + off[21];
11497
11498         len = off[22];
11499         sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11500         if (!sc->iro_array)
11501                 goto alloc_failed;
11502         bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11503
11504         return 0;
11505
11506 alloc_failed:
11507         bnx2x_release_firmware(sc);
11508         return -1;
11509 }
11510
11511 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11512 {
11513 #define MIN_PREFIX_SIZE (10)
11514
11515         int n = MIN_PREFIX_SIZE;
11516         uint16_t xlen;
11517
11518         if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11519             len <= MIN_PREFIX_SIZE) {
11520                 return -1;
11521         }
11522
11523         /* optional extra fields are present */
11524         if (zbuf[3] & 0x4) {
11525                 xlen = zbuf[13];
11526                 xlen <<= 8;
11527                 xlen += zbuf[12];
11528
11529                 n += xlen;
11530         }
11531         /* file name is present */
11532         if (zbuf[3] & 0x8) {
11533                 while ((zbuf[n++] != 0) && (n < len)) ;
11534         }
11535
11536         return n;
11537 }
11538
11539 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11540 {
11541         int ret;
11542         int data_begin = cut_gzip_prefix(zbuf, len);
11543
11544         PMD_DRV_LOG(DEBUG, sc, "ecore_gunzip %d", len);
11545
11546         if (data_begin <= 0) {
11547                 PMD_DRV_LOG(NOTICE, sc, "bad gzip prefix");
11548                 return -1;
11549         }
11550
11551         memset(&zlib_stream, 0, sizeof(zlib_stream));
11552         zlib_stream.next_in = zbuf + data_begin;
11553         zlib_stream.avail_in = len - data_begin;
11554         zlib_stream.next_out = sc->gz_buf;
11555         zlib_stream.avail_out = FW_BUF_SIZE;
11556
11557         ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11558         if (ret != Z_OK) {
11559                 PMD_DRV_LOG(NOTICE, sc, "zlib inflateInit2 error");
11560                 return ret;
11561         }
11562
11563         ret = inflate(&zlib_stream, Z_FINISH);
11564         if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11565                 PMD_DRV_LOG(NOTICE, sc, "zlib inflate error: %d %s", ret,
11566                             zlib_stream.msg);
11567         }
11568
11569         sc->gz_outlen = zlib_stream.total_out;
11570         if (sc->gz_outlen & 0x3) {
11571                 PMD_DRV_LOG(NOTICE, sc, "firmware is not aligned. gz_outlen == %d",
11572                             sc->gz_outlen);
11573         }
11574         sc->gz_outlen >>= 2;
11575
11576         inflateEnd(&zlib_stream);
11577
11578         if (ret == Z_STREAM_END)
11579                 return 0;
11580
11581         return ret;
11582 }
11583
11584 static void
11585 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
11586                           uint32_t addr, uint32_t len)
11587 {
11588         bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11589 }
11590
11591 void
11592 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11593                           uint32_t * data)
11594 {
11595         uint8_t i;
11596         for (i = 0; i < size / 4; i++) {
11597                 REG_WR(sc, addr + (i * 4), data[i]);
11598         }
11599 }
11600
11601 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11602 {
11603         uint32_t phy_type_idx = ext_phy_type >> 8;
11604         static const char *types[] =
11605             { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11606                 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11607                 "BNX2X-8727",
11608                 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11609         };
11610
11611         if (phy_type_idx < 12)
11612                 return types[phy_type_idx];
11613         else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11614                 return types[12];
11615         else
11616                 return types[13];
11617 }
11618
11619 static const char *get_state(uint32_t state)
11620 {
11621         uint32_t state_idx = state >> 12;
11622         static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11623                 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11624                 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11625                 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11626                 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11627         };
11628
11629         if (state_idx <= 0xF)
11630                 return states[state_idx];
11631         else
11632                 return states[0x10];
11633 }
11634
11635 static const char *get_recovery_state(uint32_t state)
11636 {
11637         static const char *states[] = { "NONE", "DONE", "INIT",
11638                 "WAIT", "FAILED", "NIC_LOADING"
11639         };
11640         return states[state];
11641 }
11642
11643 static const char *get_rx_mode(uint32_t mode)
11644 {
11645         static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11646                 "PROMISC", "MAX_MULTICAST", "ERROR"
11647         };
11648
11649         if (mode < 0x4)
11650                 return modes[mode];
11651         else if (BNX2X_MAX_MULTICAST == mode)
11652                 return modes[4];
11653         else
11654                 return modes[5];
11655 }
11656
11657 #define BNX2X_INFO_STR_MAX 256
11658 static const char *get_bnx2x_flags(uint32_t flags)
11659 {
11660         int i;
11661         static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11662                 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11663                 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11664                 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11665         };
11666         static char flag_str[BNX2X_INFO_STR_MAX];
11667         memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11668
11669         for (i = 0; i < 5; i++)
11670                 if (flags & (1 << i)) {
11671                         strcat(flag_str, flag[i]);
11672                         flags ^= (1 << i);
11673                 }
11674         if (flags) {
11675                 static char unknown[BNX2X_INFO_STR_MAX];
11676                 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11677                 strcat(flag_str, unknown);
11678         }
11679         return flag_str;
11680 }
11681
11682 /*
11683  * Prints useful adapter info.
11684  */
11685 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11686 {
11687         int i = 0;
11688         __rte_unused uint32_t ext_phy_type;
11689
11690         PMD_INIT_FUNC_TRACE(sc);
11691         if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11692                 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
11693                                                               sc->
11694                                                               devinfo.shmem_base
11695                                                               + offsetof(struct
11696                                                                          shmem_region,
11697                                                                          dev_info.port_hw_config
11698                                                                          [0].external_phy_config)));
11699         else
11700                 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
11701                                                                 sc->
11702                                                                 devinfo.shmem_base
11703                                                                 +
11704                                                                 offsetof(struct
11705                                                                          shmem_region,
11706                                                                          dev_info.port_hw_config
11707                                                                          [0].external_phy_config)));
11708
11709         PMD_DRV_LOG(INFO, sc, "\n\n===================================\n");
11710         /* Hardware chip info. */
11711         PMD_DRV_LOG(INFO, sc, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11712         PMD_DRV_LOG(INFO, sc, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11713                      (CHIP_METAL(sc) >> 4));
11714
11715         /* Bus info. */
11716         PMD_DRV_LOG(INFO, sc,
11717                     "%12s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
11718         switch (sc->devinfo.pcie_link_speed) {
11719         case 1:
11720                 PMD_DRV_LOG(INFO, sc, "%23s", "2.5 Gbps");
11721                 break;
11722         case 2:
11723                 PMD_DRV_LOG(INFO, sc, "%21s", "5 Gbps");
11724                 break;
11725         case 4:
11726                 PMD_DRV_LOG(INFO, sc, "%21s", "8 Gbps");
11727                 break;
11728         default:
11729                 PMD_DRV_LOG(INFO, sc, "%33s", "Unknown link speed");
11730         }
11731
11732         /* Device features. */
11733         PMD_DRV_LOG(INFO, sc, "%12s : ", "Flags");
11734
11735         /* Miscellaneous flags. */
11736         if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11737                 PMD_DRV_LOG(INFO, sc, "%18s", "MSI");
11738                 i++;
11739         }
11740
11741         if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11742                 if (i > 0)
11743                         PMD_DRV_LOG(INFO, sc, "|");
11744                 PMD_DRV_LOG(INFO, sc, "%20s", "MSI-X");
11745                 i++;
11746         }
11747
11748         if (IS_PF(sc)) {
11749                 PMD_DRV_LOG(INFO, sc, "%12s : ", "Queues");
11750                 switch (sc->sp->rss_rdata.rss_mode) {
11751                 case ETH_RSS_MODE_DISABLED:
11752                         PMD_DRV_LOG(INFO, sc, "%19s", "None");
11753                         break;
11754                 case ETH_RSS_MODE_REGULAR:
11755                         PMD_DRV_LOG(INFO, sc,
11756                                     "%18s : %d", "RSS", sc->num_queues);
11757                         break;
11758                 default:
11759                         PMD_DRV_LOG(INFO, sc, "%22s", "Unknown");
11760                         break;
11761                 }
11762         }
11763
11764         /* RTE and Driver versions */
11765         PMD_DRV_LOG(INFO, sc, "%12s : %s", "DPDK",
11766                         rte_version());
11767         PMD_DRV_LOG(INFO, sc, "%12s : %s", "Driver",
11768                         bnx2x_pmd_version());
11769
11770         /* Firmware versions and device features. */
11771         PMD_DRV_LOG(INFO, sc, "%12s : %d.%d.%d",
11772                      "Firmware",
11773                      BNX2X_5710_FW_MAJOR_VERSION,
11774                      BNX2X_5710_FW_MINOR_VERSION,
11775                      BNX2X_5710_FW_REVISION_VERSION);
11776         PMD_DRV_LOG(INFO, sc, "%12s : %s",
11777                      "Bootcode", sc->devinfo.bc_ver_str);
11778
11779         PMD_DRV_LOG(INFO, sc, "\n\n===================================\n");
11780         PMD_DRV_LOG(INFO, sc, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11781         PMD_DRV_LOG(INFO, sc,
11782                     "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11783         PMD_DRV_LOG(INFO, sc, "%12s : %s", "DMAE Is",
11784                      (sc->dmae_ready ? "Ready" : "Not Ready"));
11785         PMD_DRV_LOG(INFO, sc, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11786         PMD_DRV_LOG(INFO, sc, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11787         PMD_DRV_LOG(INFO, sc, "%12s : %u", "MTU", sc->mtu);
11788         PMD_DRV_LOG(INFO, sc,
11789                     "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11790         PMD_DRV_LOG(INFO, sc, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11791                         sc->link_params.mac_addr[0],
11792                         sc->link_params.mac_addr[1],
11793                         sc->link_params.mac_addr[2],
11794                         sc->link_params.mac_addr[3],
11795                         sc->link_params.mac_addr[4],
11796                         sc->link_params.mac_addr[5]);
11797         PMD_DRV_LOG(INFO, sc, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11798         PMD_DRV_LOG(INFO, sc, "%12s : %s", "State", get_state(sc->state));
11799         if (sc->recovery_state)
11800                 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Recovery",
11801                              get_recovery_state(sc->recovery_state));
11802         PMD_DRV_LOG(INFO, sc, "%12s : CQ = %lx,  EQ = %lx", "SPQ Left",
11803                      sc->cq_spq_left, sc->eq_spq_left);
11804         PMD_DRV_LOG(INFO, sc,
11805                     "%12s : %x", "Switch", sc->link_params.switch_cfg);
11806         PMD_DRV_LOG(INFO, sc, "\n\n===================================\n");
11807 }