drivers/net/bnx2x/bnx2x.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2007-2013 Broadcom Corporation.
   3  *
   4  * Eric Davis        <edavis@broadcom.com>
   5  * David Christensen <davidch@broadcom.com>
   6  * Gary Zambrano     <zambrano@broadcom.com>
   7  *
   8  * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
   9  * Copyright (c) 2015-2018 Cavium Inc.
  10  * All rights reserved.
  11  * www.cavium.com
  12  */
  13
  14 #define BNX2X_DRIVER_VERSION "1.78.18"
  15
  16 #include "bnx2x.h"
  17 #include "bnx2x_vfpf.h"
  18 #include "ecore_sp.h"
  19 #include "ecore_init.h"
  20 #include "ecore_init_ops.h"
  21
  22 #include "rte_version.h"
  23
  24 #include <sys/types.h>
  25 #include <sys/stat.h>
  26 #include <fcntl.h>
  27 #include <zlib.h>
  28 #include <rte_string_fns.h>
  29
  30 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
  31 #define BNX2X_PMD_VERSION_MAJOR 1
  32 #define BNX2X_PMD_VERSION_MINOR 0
  33 #define BNX2X_PMD_VERSION_REVISION 7
  34 #define BNX2X_PMD_VERSION_PATCH 1
  35
  36 static inline const char *
  37 bnx2x_pmd_version(void)
  38 {
  39         static char version[32];
  40
  41         snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
  42                         BNX2X_PMD_VER_PREFIX,
  43                         BNX2X_DRIVER_VERSION,
  44                         BNX2X_PMD_VERSION_MAJOR,
  45                         BNX2X_PMD_VERSION_MINOR,
  46                         BNX2X_PMD_VERSION_REVISION,
  47                         BNX2X_PMD_VERSION_PATCH);
  48
  49         return version;
  50 }
  51
  52 static z_stream zlib_stream;
  53
  54 #define EVL_VLID_MASK 0x0FFF
  55
  56 #define BNX2X_DEF_SB_ATT_IDX 0x0001
  57 #define BNX2X_DEF_SB_IDX     0x0002
  58
  59 /*
  60  * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
  61  * function HW initialization.
  62  */
  63 #define FLR_WAIT_USEC     10000 /* 10 msecs */
  64 #define FLR_WAIT_INTERVAL 50    /* usecs */
  65 #define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)   /* 200 */
  66
  67 struct pbf_pN_buf_regs {
  68         int pN;
  69         uint32_t init_crd;
  70         uint32_t crd;
  71         uint32_t crd_freed;
  72 };
  73
  74 struct pbf_pN_cmd_regs {
  75         int pN;
  76         uint32_t lines_occup;
  77         uint32_t lines_freed;
  78 };
  79
  80 /* resources needed for unloading a previously loaded device */
  81
  82 #define BNX2X_PREV_WAIT_NEEDED 1
  83 rte_spinlock_t bnx2x_prev_mtx;
  84 struct bnx2x_prev_list_node {
  85         LIST_ENTRY(bnx2x_prev_list_node) node;
  86         uint8_t bus;
  87         uint8_t slot;
  88         uint8_t path;
  89         uint8_t aer;
  90         uint8_t undi;
  91 };
  92
  93 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
  94         = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
  95
  96 static int load_count[2][3] = { { 0 } };
  97         /* per-path: 0-common, 1-port0, 2-port1 */
  98
  99 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
 100                                 uint8_t cmng_type);
 101 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
 102 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
 103                               uint8_t port);
 104 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
 105 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
 106 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
 107 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
 108 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
 109                                      uint8_t print);
 110 static void bnx2x_int_disable(struct bnx2x_softc *sc);
 111 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
 112 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
 113 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
 114                                  struct bnx2x_fastpath *fp,
 115                                  uint16_t rx_bd_prod, uint16_t rx_cq_prod);
 116 static void bnx2x_link_report_locked(struct bnx2x_softc *sc);
 117 static void bnx2x_link_report(struct bnx2x_softc *sc);
 118 void bnx2x_link_status_update(struct bnx2x_softc *sc);
 119 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
 120 static void bnx2x_free_mem(struct bnx2x_softc *sc);
 121 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
 122 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
 123 static __rte_noinline
 124 int bnx2x_nic_load(struct bnx2x_softc *sc);
 125
 126 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
 127 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
 128 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
 129                          uint8_t storm, uint16_t index, uint8_t op,
 130                          uint8_t update);
 131
 132 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
 133 {
 134         int res;
 135
 136         mb();
 137         res = ((*addr) & (1UL << nr)) != 0;
 138         mb();
 139         return res;
 140 }
 141
 142 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
 143 {
 144         __sync_fetch_and_or(addr, (1UL << nr));
 145 }
 146
 147 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
 148 {
 149         __sync_fetch_and_and(addr, ~(1UL << nr));
 150 }
 151
 152 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
 153 {
 154         unsigned long mask = (1UL << nr);
 155         return __sync_fetch_and_and(addr, ~mask) & mask;
 156 }
 157
 158 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
 159 {
 160         return __sync_val_compare_and_swap(addr, old, new);
 161 }
 162
 163 int
 164 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
 165               const char *msg, uint32_t align)
 166 {
 167         char mz_name[RTE_MEMZONE_NAMESIZE];
 168         const struct rte_memzone *z;
 169
 170         dma->sc = sc;
 171         if (IS_PF(sc))
 172                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
 173                         rte_get_timer_cycles());
 174         else
 175                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
 176                         rte_get_timer_cycles());
 177
 178         /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
 179         z = rte_memzone_reserve_aligned(mz_name, (uint64_t)size,
 180                                         SOCKET_ID_ANY,
 181                                         RTE_MEMZONE_IOVA_CONTIG, align);
 182         if (z == NULL) {
 183                 PMD_DRV_LOG(ERR, sc, "DMA alloc failed for %s", msg);
 184                 return -ENOMEM;
 185         }
 186         dma->paddr = (uint64_t) z->iova;
 187         dma->vaddr = z->addr;
 188
 189         PMD_DRV_LOG(DEBUG, sc,
 190                     "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
 191
 192         return 0;
 193 }
 194
 195 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 196 {
 197         uint32_t lock_status;
 198         uint32_t resource_bit = (1 << resource);
 199         int func = SC_FUNC(sc);
 200         uint32_t hw_lock_control_reg;
 201         int cnt;
 202
 203 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
 204         if (resource)
 205                 PMD_INIT_FUNC_TRACE(sc);
 206 #else
 207         PMD_INIT_FUNC_TRACE(sc);
 208 #endif
 209
 210         /* validate the resource is within range */
 211         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 212                 PMD_DRV_LOG(NOTICE, sc,
 213                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 214                             resource);
 215                 return -1;
 216         }
 217
 218         if (func <= 5) {
 219                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 220         } else {
 221                 hw_lock_control_reg =
 222                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 223         }
 224
 225         /* validate the resource is not already taken */
 226         lock_status = REG_RD(sc, hw_lock_control_reg);
 227         if (lock_status & resource_bit) {
 228                 PMD_DRV_LOG(NOTICE, sc,
 229                             "resource in use (status 0x%x bit 0x%x)",
 230                             lock_status, resource_bit);
 231                 return -1;
 232         }
 233
 234         /* try every 5ms for 5 seconds */
 235         for (cnt = 0; cnt < 1000; cnt++) {
 236                 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
 237                 lock_status = REG_RD(sc, hw_lock_control_reg);
 238                 if (lock_status & resource_bit) {
 239                         return 0;
 240                 }
 241                 DELAY(5000);
 242         }
 243
 244         PMD_DRV_LOG(NOTICE, sc, "Resource 0x%x resource_bit 0x%x lock timeout!",
 245                     resource, resource_bit);
 246         return -1;
 247 }
 248
 249 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 250 {
 251         uint32_t lock_status;
 252         uint32_t resource_bit = (1 << resource);
 253         int func = SC_FUNC(sc);
 254         uint32_t hw_lock_control_reg;
 255
 256 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
 257         if (resource)
 258                 PMD_INIT_FUNC_TRACE(sc);
 259 #else
 260         PMD_INIT_FUNC_TRACE(sc);
 261 #endif
 262
 263         /* validate the resource is within range */
 264         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 265                 PMD_DRV_LOG(NOTICE, sc,
 266                             "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
 267                             " resource_bit 0x%x", resource, resource_bit);
 268                 return -1;
 269         }
 270
 271         if (func <= 5) {
 272                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 273         } else {
 274                 hw_lock_control_reg =
 275                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 276         }
 277
 278         /* validate the resource is currently taken */
 279         lock_status = REG_RD(sc, hw_lock_control_reg);
 280         if (!(lock_status & resource_bit)) {
 281                 PMD_DRV_LOG(NOTICE, sc,
 282                             "resource not in use (status 0x%x bit 0x%x)",
 283                             lock_status, resource_bit);
 284                 return -1;
 285         }
 286
 287         REG_WR(sc, hw_lock_control_reg, resource_bit);
 288         return 0;
 289 }
 290
 291 static void bnx2x_acquire_phy_lock(struct bnx2x_softc *sc)
 292 {
 293         BNX2X_PHY_LOCK(sc);
 294         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
 295 }
 296
 297 static void bnx2x_release_phy_lock(struct bnx2x_softc *sc)
 298 {
 299         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
 300         BNX2X_PHY_UNLOCK(sc);
 301 }
 302
 303 /* copy command into DMAE command memory and set DMAE command Go */
 304 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
 305 {
 306         uint32_t cmd_offset;
 307         uint32_t i;
 308
 309         cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
 310         for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
 311                 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
 312         }
 313
 314         REG_WR(sc, dmae_reg_go_c[idx], 1);
 315 }
 316
 317 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
 318 {
 319         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 320                           DMAE_COMMAND_C_TYPE_ENABLE);
 321 }
 322
 323 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
 324 {
 325         return opcode & ~DMAE_COMMAND_SRC_RESET;
 326 }
 327
 328 uint32_t
 329 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
 330                 uint8_t with_comp, uint8_t comp_type)
 331 {
 332         uint32_t opcode = 0;
 333
 334         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 335                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 336
 337         opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
 338
 339         opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 340
 341         opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
 342                    (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
 343
 344         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 345
 346 #ifdef __BIG_ENDIAN
 347         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 348 #else
 349         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 350 #endif
 351
 352         if (with_comp) {
 353                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 354         }
 355
 356         return opcode;
 357 }
 358
 359 static void
 360 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
 361                         uint8_t src_type, uint8_t dst_type)
 362 {
 363         memset(dmae, 0, sizeof(struct dmae_command));
 364
 365         /* set the opcode */
 366         dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
 367                                        TRUE, DMAE_COMP_PCI);
 368
 369         /* fill in the completion parameters */
 370         dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
 371         dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
 372         dmae->comp_val = DMAE_COMP_VAL;
 373 }
 374
 375 /* issue a DMAE command over the init channel and wait for completion */
 376 static int
 377 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
 378 {
 379         uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
 380         int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
 381
 382         /* reset completion */
 383         *wb_comp = 0;
 384
 385         /* post the command on the channel used for initializations */
 386         bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
 387
 388         /* wait for completion */
 389         DELAY(500);
 390
 391         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 392                 if (!timeout ||
 393                     (sc->recovery_state != BNX2X_RECOVERY_DONE &&
 394                      sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 395                         PMD_DRV_LOG(INFO, sc, "DMAE timeout!");
 396                         return DMAE_TIMEOUT;
 397                 }
 398
 399                 timeout--;
 400                 DELAY(50);
 401         }
 402
 403         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 404                 PMD_DRV_LOG(INFO, sc, "DMAE PCI error!");
 405                 return DMAE_PCI_ERROR;
 406         }
 407
 408         return 0;
 409 }
 410
 411 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
 412 {
 413         struct dmae_command dmae;
 414         uint32_t *data;
 415         uint32_t i;
 416         int rc;
 417
 418         if (!sc->dmae_ready) {
 419                 data = BNX2X_SP(sc, wb_data[0]);
 420
 421                 for (i = 0; i < len32; i++) {
 422                         data[i] = REG_RD(sc, (src_addr + (i * 4)));
 423                 }
 424
 425                 return;
 426         }
 427
 428         /* set opcode and fixed command fields */
 429         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 430
 431         /* fill in addresses and len */
 432         dmae.src_addr_lo = (src_addr >> 2);     /* GRC addr has dword resolution */
 433         dmae.src_addr_hi = 0;
 434         dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
 435         dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
 436         dmae.len = len32;
 437
 438         /* issue the command and wait for completion */
 439         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 440                 rte_panic("DMAE failed (%d)", rc);
 441         };
 442 }
 443
 444 void
 445 bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr,
 446                uint32_t len32)
 447 {
 448         struct dmae_command dmae;
 449         int rc;
 450
 451         if (!sc->dmae_ready) {
 452                 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
 453                 return;
 454         }
 455
 456         /* set opcode and fixed command fields */
 457         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 458
 459         /* fill in addresses and len */
 460         dmae.src_addr_lo = U64_LO(dma_addr);
 461         dmae.src_addr_hi = U64_HI(dma_addr);
 462         dmae.dst_addr_lo = (dst_addr >> 2);     /* GRC addr has dword resolution */
 463         dmae.dst_addr_hi = 0;
 464         dmae.len = len32;
 465
 466         /* issue the command and wait for completion */
 467         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 468                 rte_panic("DMAE failed (%d)", rc);
 469         }
 470 }
 471
 472 static void
 473 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
 474                         uint32_t addr, uint32_t len)
 475 {
 476         uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
 477         uint32_t offset = 0;
 478
 479         while (len > dmae_wr_max) {
 480                 bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 481                                (addr + offset), /* dst GRC address */
 482                                dmae_wr_max);
 483                 offset += (dmae_wr_max * 4);
 484                 len -= dmae_wr_max;
 485         }
 486
 487         bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 488                        (addr + offset), /* dst GRC address */
 489                        len);
 490 }
 491
 492 void
 493 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
 494                        uint32_t cid)
 495 {
 496         /* ustorm cxt validation */
 497         cxt->ustorm_ag_context.cdu_usage =
 498             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 499                                    CDU_REGION_NUMBER_UCM_AG,
 500                                    ETH_CONNECTION_TYPE);
 501         /* xcontext validation */
 502         cxt->xstorm_ag_context.cdu_reserved =
 503             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 504                                    CDU_REGION_NUMBER_XCM_AG,
 505                                    ETH_CONNECTION_TYPE);
 506 }
 507
 508 static void
 509 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 510                             uint8_t sb_index, uint8_t ticks)
 511 {
 512         uint32_t addr =
 513             (BAR_CSTRORM_INTMEM +
 514              CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
 515
 516         REG_WR8(sc, addr, ticks);
 517 }
 518
 519 static void
 520 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
 521                             uint8_t sb_index, uint8_t disable)
 522 {
 523         uint32_t enable_flag =
 524             (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
 525         uint32_t addr =
 526             (BAR_CSTRORM_INTMEM +
 527              CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
 528         uint8_t flags;
 529
 530         /* clear and set */
 531         flags = REG_RD8(sc, addr);
 532         flags &= ~HC_INDEX_DATA_HC_ENABLED;
 533         flags |= enable_flag;
 534         REG_WR8(sc, addr, flags);
 535 }
 536
 537 void
 538 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 539                              uint8_t sb_index, uint8_t disable, uint16_t usec)
 540 {
 541         uint8_t ticks = (usec / 4);
 542
 543         bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
 544
 545         disable = (disable) ? 1 : ((usec) ? 0 : 1);
 546         bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
 547 }
 548
 549 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
 550 {
 551         return REG_RD(sc, reg_addr);
 552 }
 553
 554 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
 555 {
 556         REG_WR(sc, reg_addr, val);
 557 }
 558
 559 void
 560 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
 561                    __rte_unused const elink_log_id_t elink_log_id, ...)
 562 {
 563         PMD_DRV_LOG(DEBUG, sc, "ELINK EVENT LOG (%d)", elink_log_id);
 564 }
 565
 566 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
 567 {
 568         uint32_t spio_reg;
 569
 570         /* Only 2 SPIOs are configurable */
 571         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
 572                 PMD_DRV_LOG(NOTICE, sc, "Invalid SPIO 0x%x", spio);
 573                 return -1;
 574         }
 575
 576         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 577
 578         /* read SPIO and mask except the float bits */
 579         spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
 580
 581         switch (mode) {
 582         case MISC_SPIO_OUTPUT_LOW:
 583                 /* clear FLOAT and set CLR */
 584                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 585                 spio_reg |= (spio << MISC_SPIO_CLR_POS);
 586                 break;
 587
 588         case MISC_SPIO_OUTPUT_HIGH:
 589                 /* clear FLOAT and set SET */
 590                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 591                 spio_reg |= (spio << MISC_SPIO_SET_POS);
 592                 break;
 593
 594         case MISC_SPIO_INPUT_HI_Z:
 595                 /* set FLOAT */
 596                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
 597                 break;
 598
 599         default:
 600                 break;
 601         }
 602
 603         REG_WR(sc, MISC_REG_SPIO, spio_reg);
 604         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 605
 606         return 0;
 607 }
 608
 609 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
 610 {
 611         /* The GPIO should be swapped if swap register is set and active */
 612         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 613                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 614         int gpio_shift = gpio_num;
 615         if (gpio_port)
 616                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 617
 618         uint32_t gpio_mask = (1 << gpio_shift);
 619         uint32_t gpio_reg;
 620
 621         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 622                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 623                 return -1;
 624         }
 625
 626         /* read GPIO value */
 627         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 628
 629         /* get the requested pin value */
 630         return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
 631 }
 632
 633 static int
 634 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
 635 {
 636         /* The GPIO should be swapped if swap register is set and active */
 637         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 638                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 639         int gpio_shift = gpio_num;
 640         if (gpio_port)
 641                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 642
 643         uint32_t gpio_mask = (1 << gpio_shift);
 644         uint32_t gpio_reg;
 645
 646         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 647                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 648                 return -1;
 649         }
 650
 651         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 652
 653         /* read GPIO and mask except the float bits */
 654         gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
 655
 656         switch (mode) {
 657         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 658                 /* clear FLOAT and set CLR */
 659                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 660                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
 661                 break;
 662
 663         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 664                 /* clear FLOAT and set SET */
 665                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 666                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
 667                 break;
 668
 669         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 670                 /* set FLOAT */
 671                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 672                 break;
 673
 674         default:
 675                 break;
 676         }
 677
 678         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 679         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 680
 681         return 0;
 682 }
 683
 684 static int
 685 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
 686 {
 687         uint32_t gpio_reg;
 688
 689         /* any port swapping should be handled by caller */
 690
 691         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 692
 693         /* read GPIO and mask except the float bits */
 694         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 695         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 696         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
 697         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
 698
 699         switch (mode) {
 700         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 701                 /* set CLR */
 702                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
 703                 break;
 704
 705         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 706                 /* set SET */
 707                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
 708                 break;
 709
 710         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 711                 /* set FLOAT */
 712                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 713                 break;
 714
 715         default:
 716                 PMD_DRV_LOG(NOTICE, sc,
 717                             "Invalid GPIO mode assignment %d", mode);
 718                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 719                 return -1;
 720         }
 721
 722         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 723         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 724
 725         return 0;
 726 }
 727
 728 static int
 729 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
 730                    uint8_t port)
 731 {
 732         /* The GPIO should be swapped if swap register is set and active */
 733         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 734                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 735         int gpio_shift = gpio_num;
 736         if (gpio_port)
 737                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 738
 739         uint32_t gpio_mask = (1 << gpio_shift);
 740         uint32_t gpio_reg;
 741
 742         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 743                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 744                 return -1;
 745         }
 746
 747         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 748
 749         /* read GPIO int */
 750         gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
 751
 752         switch (mode) {
 753         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
 754                 /* clear SET and set CLR */
 755                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 756                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 757                 break;
 758
 759         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
 760                 /* clear CLR and set SET */
 761                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 762                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 763                 break;
 764
 765         default:
 766                 break;
 767         }
 768
 769         REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
 770         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 771
 772         return 0;
 773 }
 774
 775 uint32_t
 776 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
 777 {
 778         return bnx2x_gpio_read(sc, gpio_num, port);
 779 }
 780
 781 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,   /* 0=low 1=high */
 782                             uint8_t port)
 783 {
 784         return bnx2x_gpio_write(sc, gpio_num, mode, port);
 785 }
 786
 787 uint8_t
 788 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
 789                          uint8_t mode /* 0=low 1=high */ )
 790 {
 791         return bnx2x_gpio_mult_write(sc, pins, mode);
 792 }
 793
 794 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,       /* 0=low 1=high */
 795                                 uint8_t port)
 796 {
 797         return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
 798 }
 799
 800 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
 801 {
 802         REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
 803                     (SC_FUNC(sc) * sizeof(uint32_t))), 1);
 804 }
 805
 806 /* send the MCP a request, block until there is a reply */
 807 uint32_t
 808 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 809 {
 810         int mb_idx = SC_FW_MB_IDX(sc);
 811         uint32_t seq;
 812         uint32_t rc = 0;
 813         uint32_t cnt = 1;
 814         uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
 815
 816         seq = ++sc->fw_seq;
 817         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
 818         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
 819
 820         PMD_DRV_LOG(DEBUG, sc,
 821                     "wrote command 0x%08x to FW MB param 0x%08x",
 822                     (command | seq), param);
 823
 824         /* Let the FW do it's magic. GIve it up to 5 seconds... */
 825         do {
 826                 DELAY(delay * 1000);
 827                 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
 828         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
 829
 830         /* is this a reply to our command? */
 831         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
 832                 rc &= FW_MSG_CODE_MASK;
 833         } else {
 834                 /* Ruh-roh! */
 835                 PMD_DRV_LOG(NOTICE, sc, "FW failed to respond!");
 836                 rc = 0;
 837         }
 838
 839         return rc;
 840 }
 841
 842 static uint32_t
 843 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 844 {
 845         return elink_cb_fw_command(sc, command, param);
 846 }
 847
 848 static void
 849 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
 850                            rte_iova_t mapping)
 851 {
 852         REG_WR(sc, addr, U64_LO(mapping));
 853         REG_WR(sc, (addr + 4), U64_HI(mapping));
 854 }
 855
 856 static void
 857 storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping,
 858                       uint16_t abs_fid)
 859 {
 860         uint32_t addr = (XSEM_REG_FAST_MEMORY +
 861                          XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
 862         __storm_memset_dma_mapping(sc, addr, mapping);
 863 }
 864
 865 static void
 866 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
 867 {
 868         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
 869                 pf_id);
 870         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
 871                 pf_id);
 872         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
 873                 pf_id);
 874         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
 875                 pf_id);
 876 }
 877
 878 static void
 879 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
 880 {
 881         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
 882                 enable);
 883         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
 884                 enable);
 885         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
 886                 enable);
 887         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
 888                 enable);
 889 }
 890
 891 static void
 892 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
 893                      uint16_t pfid)
 894 {
 895         uint32_t addr;
 896         size_t size;
 897
 898         addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
 899         size = sizeof(struct event_ring_data);
 900         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
 901 }
 902
 903 static void
 904 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
 905 {
 906         uint32_t addr = (BAR_CSTRORM_INTMEM +
 907                          CSTORM_EVENT_RING_PROD_OFFSET(pfid));
 908         REG_WR16(sc, addr, eq_prod);
 909 }
 910
 911 /*
 912  * Post a slowpath command.
 913  *
 914  * A slowpath command is used to propagate a configuration change through
 915  * the controller in a controlled manner, allowing each STORM processor and
 916  * other H/W blocks to phase in the change.  The commands sent on the
 917  * slowpath are referred to as ramrods.  Depending on the ramrod used the
 918  * completion of the ramrod will occur in different ways.  Here's a
 919  * breakdown of ramrods and how they complete:
 920  *
 921  * RAMROD_CMD_ID_ETH_PORT_SETUP
 922  *   Used to setup the leading connection on a port.  Completes on the
 923  *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
 924  *
 925  * RAMROD_CMD_ID_ETH_CLIENT_SETUP
 926  *   Used to setup an additional connection on a port.  Completes on the
 927  *   RCQ of the multi-queue/RSS connection being initialized.
 928  *
 929  * RAMROD_CMD_ID_ETH_STAT_QUERY
 930  *   Used to force the storm processors to update the statistics database
 931  *   in host memory.  This ramrod is send on the leading connection CID and
 932  *   completes as an index increment of the CSTORM on the default status
 933  *   block.
 934  *
 935  * RAMROD_CMD_ID_ETH_UPDATE
 936  *   Used to update the state of the leading connection, usually to udpate
 937  *   the RSS indirection table.  Completes on the RCQ of the leading
 938  *   connection. (Not currently used under FreeBSD until OS support becomes
 939  *   available.)
 940  *
 941  * RAMROD_CMD_ID_ETH_HALT
 942  *   Used when tearing down a connection prior to driver unload.  Completes
 943  *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
 944  *   use this on the leading connection.
 945  *
 946  * RAMROD_CMD_ID_ETH_SET_MAC
 947  *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
 948  *   the RCQ of the leading connection.
 949  *
 950  * RAMROD_CMD_ID_ETH_CFC_DEL
 951  *   Used when tearing down a conneciton prior to driver unload.  Completes
 952  *   on the RCQ of the leading connection (since the current connection
 953  *   has been completely removed from controller memory).
 954  *
 955  * RAMROD_CMD_ID_ETH_PORT_DEL
 956  *   Used to tear down the leading connection prior to driver unload,
 957  *   typically fp[0].  Completes as an index increment of the CSTORM on the
 958  *   default status block.
 959  *
 960  * RAMROD_CMD_ID_ETH_FORWARD_SETUP
 961  *   Used for connection offload.  Completes on the RCQ of the multi-queue
 962  *   RSS connection that is being offloaded.  (Not currently used under
 963  *   FreeBSD.)
 964  *
 965  * There can only be one command pending per function.
 966  *
 967  * Returns:
 968  *   0 = Success, !0 = Failure.
 969  */
 970
 971 /* must be called under the spq lock */
 972 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
 973 {
 974         struct eth_spe *next_spe = sc->spq_prod_bd;
 975
 976         if (sc->spq_prod_bd == sc->spq_last_bd) {
 977                 /* wrap back to the first eth_spq */
 978                 sc->spq_prod_bd = sc->spq;
 979                 sc->spq_prod_idx = 0;
 980         } else {
 981                 sc->spq_prod_bd++;
 982                 sc->spq_prod_idx++;
 983         }
 984
 985         return next_spe;
 986 }
 987
 988 /* must be called under the spq lock */
 989 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
 990 {
 991         int func = SC_FUNC(sc);
 992
 993         /*
 994          * Make sure that BD data is updated before writing the producer.
 995          * BD data is written to the memory, the producer is read from the
 996          * memory, thus we need a full memory barrier to ensure the ordering.
 997          */
 998         mb();
 999
1000         REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
1001                  sc->spq_prod_idx);
1002
1003         mb();
1004 }
1005
1006 /**
1007  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
1008  *
1009  * @cmd:      command to check
1010  * @cmd_type: command type
1011  */
1012 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
1013 {
1014         if ((cmd_type == NONE_CONNECTION_TYPE) ||
1015             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
1016             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
1017             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
1018             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
1019             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
1020             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
1021                 return TRUE;
1022         } else {
1023                 return FALSE;
1024         }
1025 }
1026
1027 /**
1028  * bnx2x_sp_post - place a single command on an SP ring
1029  *
1030  * @sc:         driver handle
1031  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
1032  * @cid:        SW CID the command is related to
1033  * @data_hi:    command private data address (high 32 bits)
1034  * @data_lo:    command private data address (low 32 bits)
1035  * @cmd_type:   command type (e.g. NONE, ETH)
1036  *
1037  * SP data is handled as if it's always an address pair, thus data fields are
1038  * not swapped to little endian in upper functions. Instead this function swaps
1039  * data as if it's two uint32 fields.
1040  */
1041 int
1042 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1043             uint32_t data_lo, int cmd_type)
1044 {
1045         struct eth_spe *spe;
1046         uint16_t type;
1047         int common;
1048
1049         common = bnx2x_is_contextless_ramrod(command, cmd_type);
1050
1051         if (common) {
1052                 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1053                         PMD_DRV_LOG(INFO, sc, "EQ ring is full!");
1054                         return -1;
1055                 }
1056         } else {
1057                 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1058                         PMD_DRV_LOG(INFO, sc, "SPQ ring is full!");
1059                         return -1;
1060                 }
1061         }
1062
1063         spe = bnx2x_sp_get_next(sc);
1064
1065         /* CID needs port number to be encoded int it */
1066         spe->hdr.conn_and_cmd_data =
1067             htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1068
1069         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1070
1071         /* TBD: Check if it works for VFs */
1072         type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1073                  SPE_HDR_FUNCTION_ID);
1074
1075         spe->hdr.type = htole16(type);
1076
1077         spe->data.update_data_addr.hi = htole32(data_hi);
1078         spe->data.update_data_addr.lo = htole32(data_lo);
1079
1080         /*
1081          * It's ok if the actual decrement is issued towards the memory
1082          * somewhere between the lock and unlock. Thus no more explict
1083          * memory barrier is needed.
1084          */
1085         if (common) {
1086                 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1087         } else {
1088                 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1089         }
1090
1091         PMD_DRV_LOG(DEBUG, sc,
1092                     "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1093                     "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1094                     sc->spq_prod_idx,
1095                     (uint32_t) U64_HI(sc->spq_dma.paddr),
1096                     (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1097                                 (uint8_t *) sc->spq_prod_bd -
1098                                 (uint8_t *) sc->spq), command, common,
1099                     HW_CID(sc, cid), data_hi, data_lo, type,
1100                     atomic_load_acq_long(&sc->cq_spq_left),
1101                     atomic_load_acq_long(&sc->eq_spq_left));
1102
1103         bnx2x_sp_prod_update(sc);
1104
1105         return 0;
1106 }
1107
1108 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1109 {
1110         SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1111                  sc->fw_drv_pulse_wr_seq);
1112 }
1113
1114 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1115 {
1116         uint16_t hw_cons;
1117         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1118
1119         if (unlikely(!txq)) {
1120                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1121                 return 0;
1122         }
1123
1124         mb();                   /* status block fields can change */
1125         hw_cons = le16toh(*fp->tx_cons_sb);
1126         return hw_cons != txq->tx_pkt_head;
1127 }
1128
1129 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1130 {
1131         /* expand this for multi-cos if ever supported */
1132         return bnx2x_tx_queue_has_work(fp);
1133 }
1134
1135 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1136 {
1137         uint16_t rx_cq_cons_sb;
1138         struct bnx2x_rx_queue *rxq;
1139         rxq = fp->sc->rx_queues[fp->index];
1140         if (unlikely(!rxq)) {
1141                 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1142                 return 0;
1143         }
1144
1145         mb();                   /* status block fields can change */
1146         rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1147         if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1148                      MAX_RCQ_ENTRIES(rxq)))
1149                 rx_cq_cons_sb++;
1150         return rxq->rx_cq_head != rx_cq_cons_sb;
1151 }
1152
1153 static void
1154 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1155              union eth_rx_cqe *rr_cqe)
1156 {
1157         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1158         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1159         enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1160         struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1161
1162         PMD_DRV_LOG(DEBUG, sc,
1163                     "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1164                     fp->index, cid, command, sc->state,
1165                     rr_cqe->ramrod_cqe.ramrod_type);
1166
1167         switch (command) {
1168         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1169                 PMD_DRV_LOG(DEBUG, sc, "got UPDATE ramrod. CID %d", cid);
1170                 drv_cmd = ECORE_Q_CMD_UPDATE;
1171                 break;
1172
1173         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1174                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] setup ramrod", cid);
1175                 drv_cmd = ECORE_Q_CMD_SETUP;
1176                 break;
1177
1178         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1179                 PMD_DRV_LOG(DEBUG, sc,
1180                             "got MULTI[%d] tx-only setup ramrod", cid);
1181                 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1182                 break;
1183
1184         case (RAMROD_CMD_ID_ETH_HALT):
1185                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] halt ramrod", cid);
1186                 drv_cmd = ECORE_Q_CMD_HALT;
1187                 break;
1188
1189         case (RAMROD_CMD_ID_ETH_TERMINATE):
1190                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] teminate ramrod", cid);
1191                 drv_cmd = ECORE_Q_CMD_TERMINATE;
1192                 break;
1193
1194         case (RAMROD_CMD_ID_ETH_EMPTY):
1195                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] empty ramrod", cid);
1196                 drv_cmd = ECORE_Q_CMD_EMPTY;
1197                 break;
1198
1199         default:
1200                 PMD_DRV_LOG(DEBUG, sc,
1201                             "ERROR: unexpected MC reply (%d)"
1202                             "on fp[%d]", command, fp->index);
1203                 return;
1204         }
1205
1206         if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1207             q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1208                 /*
1209                  * q_obj->complete_cmd() failure means that this was
1210                  * an unexpected completion.
1211                  *
1212                  * In this case we don't want to increase the sc->spq_left
1213                  * because apparently we haven't sent this command the first
1214                  * place.
1215                  */
1216                 // rte_panic("Unexpected SP completion");
1217                 return;
1218         }
1219
1220         atomic_add_acq_long(&sc->cq_spq_left, 1);
1221
1222         PMD_DRV_LOG(DEBUG, sc, "sc->cq_spq_left 0x%lx",
1223                     atomic_load_acq_long(&sc->cq_spq_left));
1224 }
1225
1226 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1227 {
1228         struct bnx2x_rx_queue *rxq;
1229         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1230         uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1231
1232         rxq = sc->rx_queues[fp->index];
1233         if (!rxq) {
1234                 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1235                 return 0;
1236         }
1237
1238         /* CQ "next element" is of the size of the regular element */
1239         hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1240         if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1241                      USABLE_RCQ_ENTRIES_PER_PAGE)) {
1242                 hw_cq_cons++;
1243         }
1244
1245         bd_cons = rxq->rx_bd_head;
1246         bd_prod = rxq->rx_bd_tail;
1247         bd_prod_fw = bd_prod;
1248         sw_cq_cons = rxq->rx_cq_head;
1249         sw_cq_prod = rxq->rx_cq_tail;
1250
1251         /*
1252          * Memory barrier necessary as speculative reads of the rx
1253          * buffer can be ahead of the index in the status block
1254          */
1255         rmb();
1256
1257         while (sw_cq_cons != hw_cq_cons) {
1258                 union eth_rx_cqe *cqe;
1259                 struct eth_fast_path_rx_cqe *cqe_fp;
1260                 uint8_t cqe_fp_flags;
1261                 enum eth_rx_cqe_type cqe_fp_type;
1262
1263                 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1264                 bd_prod = RX_BD(bd_prod, rxq);
1265                 bd_cons = RX_BD(bd_cons, rxq);
1266
1267                 cqe = &rxq->cq_ring[comp_ring_cons];
1268                 cqe_fp = &cqe->fast_path_cqe;
1269                 cqe_fp_flags = cqe_fp->type_error_flags;
1270                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1271
1272                 /* is this a slowpath msg? */
1273                 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1274                         bnx2x_sp_event(sc, fp, cqe);
1275                         goto next_cqe;
1276                 }
1277
1278                 /* is this an error packet? */
1279                 if (unlikely(cqe_fp_flags &
1280                              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1281                         PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1282                                    cqe_fp_flags, sw_cq_cons);
1283                         goto next_rx;
1284                 }
1285
1286                 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1287
1288 next_rx:
1289                 bd_cons = NEXT_RX_BD(bd_cons);
1290                 bd_prod = NEXT_RX_BD(bd_prod);
1291                 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1292
1293 next_cqe:
1294                 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1295                 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1296
1297         }                       /* while work to do */
1298
1299         rxq->rx_bd_head = bd_cons;
1300         rxq->rx_bd_tail = bd_prod_fw;
1301         rxq->rx_cq_head = sw_cq_cons;
1302         rxq->rx_cq_tail = sw_cq_prod;
1303
1304         /* Update producers */
1305         bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1306
1307         return sw_cq_cons != hw_cq_cons;
1308 }
1309
1310 static uint16_t
1311 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1312                 uint16_t pkt_idx, uint16_t bd_idx)
1313 {
1314         struct eth_tx_start_bd *tx_start_bd =
1315             &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1316         uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1317         struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1318
1319         if (likely(tx_mbuf != NULL)) {
1320                 rte_pktmbuf_free_seg(tx_mbuf);
1321         } else {
1322                 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1323                            fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1324         }
1325
1326         txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1327         txq->nb_tx_avail += nbd;
1328
1329         while (nbd--)
1330                 bd_idx = NEXT_TX_BD(bd_idx);
1331
1332         return bd_idx;
1333 }
1334
1335 /* processes transmit completions */
1336 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1337 {
1338         uint16_t bd_cons, hw_cons, sw_cons;
1339         __rte_unused uint16_t tx_bd_avail;
1340
1341         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1342
1343         if (unlikely(!txq)) {
1344                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1345                 return 0;
1346         }
1347
1348         bd_cons = txq->tx_bd_head;
1349         hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1350         sw_cons = txq->tx_pkt_head;
1351
1352         while (sw_cons != hw_cons) {
1353                 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1354                 sw_cons++;
1355         }
1356
1357         txq->tx_pkt_head = sw_cons;
1358         txq->tx_bd_head = bd_cons;
1359
1360         tx_bd_avail = txq->nb_tx_avail;
1361
1362         PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1363                    "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1364                    fp->index, tx_bd_avail, hw_cons,
1365                    txq->tx_pkt_head, txq->tx_pkt_tail,
1366                    txq->tx_bd_head, txq->tx_bd_tail);
1367         return TRUE;
1368 }
1369
1370 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1371 {
1372         struct bnx2x_fastpath *fp;
1373         int i, count;
1374
1375         /* wait until all TX fastpath tasks have completed */
1376         for (i = 0; i < sc->num_queues; i++) {
1377                 fp = &sc->fp[i];
1378
1379                 count = 1000;
1380
1381                 while (bnx2x_has_tx_work(fp)) {
1382                         bnx2x_txeof(sc, fp);
1383
1384                         if (count == 0) {
1385                                 PMD_TX_LOG(ERR,
1386                                            "Timeout waiting for fp[%d] "
1387                                            "transmits to complete!", i);
1388                                 rte_panic("tx drain failure");
1389                                 return;
1390                         }
1391
1392                         count--;
1393                         DELAY(1000);
1394                         rmb();
1395                 }
1396         }
1397
1398         return;
1399 }
1400
1401 static int
1402 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1403                  int mac_type, uint8_t wait_for_comp)
1404 {
1405         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1406         int rc;
1407
1408         /* wait for completion of requested */
1409         if (wait_for_comp) {
1410                 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1411         }
1412
1413         /* Set the mac type of addresses we want to clear */
1414         bnx2x_set_bit(mac_type, &vlan_mac_flags);
1415
1416         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1417         if (rc < 0)
1418                 PMD_DRV_LOG(ERR, sc, "Failed to delete MACs (%d)", rc);
1419
1420         return rc;
1421 }
1422
1423 static int
1424 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1425                         unsigned long *rx_accept_flags,
1426                         unsigned long *tx_accept_flags)
1427 {
1428         /* Clear the flags first */
1429         *rx_accept_flags = 0;
1430         *tx_accept_flags = 0;
1431
1432         switch (rx_mode) {
1433         case BNX2X_RX_MODE_NONE:
1434                 /*
1435                  * 'drop all' supersedes any accept flags that may have been
1436                  * passed to the function.
1437                  */
1438                 break;
1439
1440         case BNX2X_RX_MODE_NORMAL:
1441                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1442                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1443                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1444
1445                 /* internal switching mode */
1446                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1447                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1448                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1449
1450                 break;
1451
1452         case BNX2X_RX_MODE_ALLMULTI:
1453                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1454                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1455                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1456
1457                 /* internal switching mode */
1458                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1459                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1460                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1461
1462                 break;
1463
1464         case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1465         case BNX2X_RX_MODE_PROMISC:
1466                 /*
1467                  * According to deffinition of SI mode, iface in promisc mode
1468                  * should receive matched and unmatched (in resolution of port)
1469                  * unicast packets.
1470                  */
1471                 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1472                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1473                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1474                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1475
1476                 /* internal switching mode */
1477                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1478                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1479
1480                 if (IS_MF_SI(sc)) {
1481                         bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1482                 } else {
1483                         bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1484                 }
1485
1486                 break;
1487
1488         default:
1489                 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1490                 return -1;
1491         }
1492
1493         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1494         if (rx_mode != BNX2X_RX_MODE_NONE) {
1495                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1496                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1497         }
1498
1499         return 0;
1500 }
1501
1502 static int
1503 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1504                   unsigned long rx_mode_flags,
1505                   unsigned long rx_accept_flags,
1506                   unsigned long tx_accept_flags, unsigned long ramrod_flags)
1507 {
1508         struct ecore_rx_mode_ramrod_params ramrod_param;
1509         int rc;
1510
1511         memset(&ramrod_param, 0, sizeof(ramrod_param));
1512
1513         /* Prepare ramrod parameters */
1514         ramrod_param.cid = 0;
1515         ramrod_param.cl_id = cl_id;
1516         ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1517         ramrod_param.func_id = SC_FUNC(sc);
1518
1519         ramrod_param.pstate = &sc->sp_state;
1520         ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1521
1522         ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1523         ramrod_param.rdata_mapping =
1524             (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1525             bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1526
1527         ramrod_param.ramrod_flags = ramrod_flags;
1528         ramrod_param.rx_mode_flags = rx_mode_flags;
1529
1530         ramrod_param.rx_accept_flags = rx_accept_flags;
1531         ramrod_param.tx_accept_flags = tx_accept_flags;
1532
1533         rc = ecore_config_rx_mode(sc, &ramrod_param);
1534         if (rc < 0) {
1535                 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1536                 return rc;
1537         }
1538
1539         return 0;
1540 }
1541
1542 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1543 {
1544         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1545         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1546         int rc;
1547
1548         rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1549                                    &tx_accept_flags);
1550         if (rc) {
1551                 return rc;
1552         }
1553
1554         bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1555         bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1556         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1557
1558         return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1559                                  rx_accept_flags, tx_accept_flags,
1560                                  ramrod_flags);
1561 }
1562
1563 /* returns the "mcp load_code" according to global load_count array */
1564 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1565 {
1566         int path = SC_PATH(sc);
1567         int port = SC_PORT(sc);
1568
1569         PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d]      %d, %d, %d",
1570                     path, load_count[path][0], load_count[path][1],
1571                     load_count[path][2]);
1572
1573         load_count[path][0]++;
1574         load_count[path][1 + port]++;
1575         PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d]  %d, %d, %d",
1576                     path, load_count[path][0], load_count[path][1],
1577                     load_count[path][2]);
1578         if (load_count[path][0] == 1)
1579                 return FW_MSG_CODE_DRV_LOAD_COMMON;
1580         else if (load_count[path][1 + port] == 1)
1581                 return FW_MSG_CODE_DRV_LOAD_PORT;
1582         else
1583                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1584 }
1585
1586 /* returns the "mcp load_code" according to global load_count array */
1587 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1588 {
1589         int port = SC_PORT(sc);
1590         int path = SC_PATH(sc);
1591
1592         PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d]      %d, %d, %d",
1593                     path, load_count[path][0], load_count[path][1],
1594                     load_count[path][2]);
1595         load_count[path][0]--;
1596         load_count[path][1 + port]--;
1597         PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d]  %d, %d, %d",
1598                     path, load_count[path][0], load_count[path][1],
1599                     load_count[path][2]);
1600         if (load_count[path][0] == 0) {
1601                 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1602         } else if (load_count[path][1 + port] == 0) {
1603                 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1604         } else {
1605                 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1606         }
1607 }
1608
1609 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1610 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1611 {
1612         uint32_t reset_code = 0;
1613
1614         /* Select the UNLOAD request mode */
1615         if (unload_mode == UNLOAD_NORMAL) {
1616                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1617         } else {
1618                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1619         }
1620
1621         /* Send the request to the MCP */
1622         if (!BNX2X_NOMCP(sc)) {
1623                 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1624         } else {
1625                 reset_code = bnx2x_nic_unload_no_mcp(sc);
1626         }
1627
1628         return reset_code;
1629 }
1630
1631 /* send UNLOAD_DONE command to the MCP */
1632 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1633 {
1634         uint32_t reset_param =
1635             keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1636
1637         /* Report UNLOAD_DONE to MCP */
1638         if (!BNX2X_NOMCP(sc)) {
1639                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1640         }
1641 }
1642
1643 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1644 {
1645         int tout = 50;
1646
1647         if (!sc->port.pmf) {
1648                 return 0;
1649         }
1650
1651         /*
1652          * (assumption: No Attention from MCP at this stage)
1653          * PMF probably in the middle of TX disable/enable transaction
1654          * 1. Sync IRS for default SB
1655          * 2. Sync SP queue - this guarantees us that attention handling started
1656          * 3. Wait, that TX disable/enable transaction completes
1657          *
1658          * 1+2 guarantee that if DCBX attention was scheduled it already changed
1659          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1660          * received completion for the transaction the state is TX_STOPPED.
1661          * State will return to STARTED after completion of TX_STOPPED-->STARTED
1662          * transaction.
1663          */
1664
1665         while (ecore_func_get_state(sc, &sc->func_obj) !=
1666                ECORE_F_STATE_STARTED && tout--) {
1667                 DELAY(20000);
1668         }
1669
1670         if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1671                 /*
1672                  * Failed to complete the transaction in a "good way"
1673                  * Force both transactions with CLR bit.
1674                  */
1675                 struct ecore_func_state_params func_params = { NULL };
1676
1677                 PMD_DRV_LOG(NOTICE, sc, "Unexpected function state! "
1678                             "Forcing STARTED-->TX_STOPPED-->STARTED");
1679
1680                 func_params.f_obj = &sc->func_obj;
1681                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1682
1683                 /* STARTED-->TX_STOPPED */
1684                 func_params.cmd = ECORE_F_CMD_TX_STOP;
1685                 ecore_func_state_change(sc, &func_params);
1686
1687                 /* TX_STOPPED-->STARTED */
1688                 func_params.cmd = ECORE_F_CMD_TX_START;
1689                 return ecore_func_state_change(sc, &func_params);
1690         }
1691
1692         return 0;
1693 }
1694
1695 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1696 {
1697         struct bnx2x_fastpath *fp = &sc->fp[index];
1698         struct ecore_queue_state_params q_params = { NULL };
1699         int rc;
1700
1701         PMD_DRV_LOG(DEBUG, sc, "stopping queue %d cid %d", index, fp->index);
1702
1703         q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1704         /* We want to wait for completion in this context */
1705         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1706
1707         /* Stop the primary connection: */
1708
1709         /* ...halt the connection */
1710         q_params.cmd = ECORE_Q_CMD_HALT;
1711         rc = ecore_queue_state_change(sc, &q_params);
1712         if (rc) {
1713                 return rc;
1714         }
1715
1716         /* ...terminate the connection */
1717         q_params.cmd = ECORE_Q_CMD_TERMINATE;
1718         memset(&q_params.params.terminate, 0,
1719                sizeof(q_params.params.terminate));
1720         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1721         rc = ecore_queue_state_change(sc, &q_params);
1722         if (rc) {
1723                 return rc;
1724         }
1725
1726         /* ...delete cfc entry */
1727         q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1728         memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1729         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1730         return ecore_queue_state_change(sc, &q_params);
1731 }
1732
1733 /* wait for the outstanding SP commands */
1734 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1735 {
1736         unsigned long tmp;
1737         int tout = 5000;        /* wait for 5 secs tops */
1738
1739         while (tout--) {
1740                 mb();
1741                 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1742                         return TRUE;
1743                 }
1744
1745                 DELAY(1000);
1746         }
1747
1748         mb();
1749
1750         tmp = atomic_load_acq_long(&sc->sp_state);
1751         if (tmp & mask) {
1752                 PMD_DRV_LOG(INFO, sc, "Filtering completion timed out: "
1753                             "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1754                 return FALSE;
1755         }
1756
1757         return FALSE;
1758 }
1759
1760 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1761 {
1762         struct ecore_func_state_params func_params = { NULL };
1763         int rc;
1764
1765         /* prepare parameters for function state transitions */
1766         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1767         func_params.f_obj = &sc->func_obj;
1768         func_params.cmd = ECORE_F_CMD_STOP;
1769
1770         /*
1771          * Try to stop the function the 'good way'. If it fails (in case
1772          * of a parity error during bnx2x_chip_cleanup()) and we are
1773          * not in a debug mode, perform a state transaction in order to
1774          * enable further HW_RESET transaction.
1775          */
1776         rc = ecore_func_state_change(sc, &func_params);
1777         if (rc) {
1778                 PMD_DRV_LOG(NOTICE, sc, "FUNC_STOP ramrod failed. "
1779                             "Running a dry transaction");
1780                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1781                 return ecore_func_state_change(sc, &func_params);
1782         }
1783
1784         return 0;
1785 }
1786
1787 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1788 {
1789         struct ecore_func_state_params func_params = { NULL };
1790
1791         /* Prepare parameters for function state transitions */
1792         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1793
1794         func_params.f_obj = &sc->func_obj;
1795         func_params.cmd = ECORE_F_CMD_HW_RESET;
1796
1797         func_params.params.hw_init.load_phase = load_code;
1798
1799         return ecore_func_state_change(sc, &func_params);
1800 }
1801
1802 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1803 {
1804         if (disable_hw) {
1805                 /* prevent the HW from sending interrupts */
1806                 bnx2x_int_disable(sc);
1807         }
1808 }
1809
1810 static void
1811 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1812 {
1813         int port = SC_PORT(sc);
1814         struct ecore_mcast_ramrod_params rparam = { NULL };
1815         uint32_t reset_code;
1816         int i, rc = 0;
1817
1818         bnx2x_drain_tx_queues(sc);
1819
1820         /* give HW time to discard old tx messages */
1821         DELAY(1000);
1822
1823         /* Clean all ETH MACs */
1824         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1825                               FALSE);
1826         if (rc < 0) {
1827                 PMD_DRV_LOG(NOTICE, sc,
1828                             "Failed to delete all ETH MACs (%d)", rc);
1829         }
1830
1831         /* Clean up UC list  */
1832         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1833                               TRUE);
1834         if (rc < 0) {
1835                 PMD_DRV_LOG(NOTICE, sc,
1836                             "Failed to delete UC MACs list (%d)", rc);
1837         }
1838
1839         /* Disable LLH */
1840         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1841
1842         /* Set "drop all" to stop Rx */
1843
1844         /*
1845          * We need to take the if_maddr_lock() here in order to prevent
1846          * a race between the completion code and this code.
1847          */
1848
1849         if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1850                 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1851         } else {
1852                 bnx2x_set_storm_rx_mode(sc);
1853         }
1854
1855         /* Clean up multicast configuration */
1856         rparam.mcast_obj = &sc->mcast_obj;
1857         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1858         if (rc < 0) {
1859                 PMD_DRV_LOG(NOTICE, sc,
1860                             "Failed to send DEL MCAST command (%d)", rc);
1861         }
1862
1863         /*
1864          * Send the UNLOAD_REQUEST to the MCP. This will return if
1865          * this function should perform FUNCTION, PORT, or COMMON HW
1866          * reset.
1867          */
1868         reset_code = bnx2x_send_unload_req(sc, unload_mode);
1869
1870         /*
1871          * (assumption: No Attention from MCP at this stage)
1872          * PMF probably in the middle of TX disable/enable transaction
1873          */
1874         rc = bnx2x_func_wait_started(sc);
1875         if (rc) {
1876                 PMD_DRV_LOG(NOTICE, sc, "bnx2x_func_wait_started failed");
1877         }
1878
1879         /*
1880          * Close multi and leading connections
1881          * Completions for ramrods are collected in a synchronous way
1882          */
1883         for (i = 0; i < sc->num_queues; i++) {
1884                 if (bnx2x_stop_queue(sc, i)) {
1885                         goto unload_error;
1886                 }
1887         }
1888
1889         /*
1890          * If SP settings didn't get completed so far - something
1891          * very wrong has happen.
1892          */
1893         if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1894                 PMD_DRV_LOG(NOTICE, sc, "Common slow path ramrods got stuck!");
1895         }
1896
1897 unload_error:
1898
1899         rc = bnx2x_func_stop(sc);
1900         if (rc) {
1901                 PMD_DRV_LOG(NOTICE, sc, "Function stop failed!");
1902         }
1903
1904         /* disable HW interrupts */
1905         bnx2x_int_disable_sync(sc, TRUE);
1906
1907         /* Reset the chip */
1908         rc = bnx2x_reset_hw(sc, reset_code);
1909         if (rc) {
1910                 PMD_DRV_LOG(NOTICE, sc, "Hardware reset failed");
1911         }
1912
1913         /* Report UNLOAD_DONE to MCP */
1914         bnx2x_send_unload_done(sc, keep_link);
1915 }
1916
1917 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1918 {
1919         uint32_t val;
1920
1921         PMD_DRV_LOG(DEBUG, sc, "Disabling 'close the gates'");
1922
1923         val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1924         val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1925                  MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1926         REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1927 }
1928
1929 /*
1930  * Cleans the object that have internal lists without sending
1931  * ramrods. Should be run when interrutps are disabled.
1932  */
1933 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1934 {
1935         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1936         struct ecore_mcast_ramrod_params rparam = { NULL };
1937         struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1938         int rc;
1939
1940         /* Cleanup MACs' object first... */
1941
1942         /* Wait for completion of requested */
1943         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1944         /* Perform a dry cleanup */
1945         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1946
1947         /* Clean ETH primary MAC */
1948         bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1949         rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1950                                  &ramrod_flags);
1951         if (rc != 0) {
1952                 PMD_DRV_LOG(NOTICE, sc, "Failed to clean ETH MACs (%d)", rc);
1953         }
1954
1955         /* Cleanup UC list */
1956         vlan_mac_flags = 0;
1957         bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1958         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1959         if (rc != 0) {
1960                 PMD_DRV_LOG(NOTICE, sc,
1961                             "Failed to clean UC list MACs (%d)", rc);
1962         }
1963
1964         /* Now clean mcast object... */
1965
1966         rparam.mcast_obj = &sc->mcast_obj;
1967         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1968
1969         /* Add a DEL command... */
1970         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1971         if (rc < 0) {
1972                 PMD_DRV_LOG(NOTICE, sc,
1973                             "Failed to send DEL MCAST command (%d)", rc);
1974         }
1975
1976         /* now wait until all pending commands are cleared */
1977
1978         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1979         while (rc != 0) {
1980                 if (rc < 0) {
1981                         PMD_DRV_LOG(NOTICE, sc,
1982                                     "Failed to clean MCAST object (%d)", rc);
1983                         return;
1984                 }
1985
1986                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1987         }
1988 }
1989
1990 /* stop the controller */
1991 __rte_noinline
1992 int
1993 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1994 {
1995         uint8_t global = FALSE;
1996         uint32_t val;
1997
1998         PMD_DRV_LOG(DEBUG, sc, "Starting NIC unload...");
1999
2000         /* mark driver as unloaded in shmem2 */
2001         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
2002                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
2003                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
2004                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
2005         }
2006
2007         if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
2008             (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
2009                 /*
2010                  * We can get here if the driver has been unloaded
2011                  * during parity error recovery and is either waiting for a
2012                  * leader to complete or for other functions to unload and
2013                  * then ifconfig down has been issued. In this case we want to
2014                  * unload and let other functions to complete a recovery
2015                  * process.
2016                  */
2017                 sc->recovery_state = BNX2X_RECOVERY_DONE;
2018                 sc->is_leader = 0;
2019                 bnx2x_release_leader_lock(sc);
2020                 mb();
2021
2022                 PMD_DRV_LOG(NOTICE, sc, "Can't unload in closed or error state");
2023                 return -1;
2024         }
2025
2026         /*
2027          * Nothing to do during unload if previous bnx2x_nic_load()
2028          * did not completed successfully - all resourses are released.
2029          */
2030         if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2031                 return 0;
2032         }
2033
2034         sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2035         mb();
2036
2037         sc->rx_mode = BNX2X_RX_MODE_NONE;
2038         bnx2x_set_rx_mode(sc);
2039         mb();
2040
2041         if (IS_PF(sc)) {
2042                 /* set ALWAYS_ALIVE bit in shmem */
2043                 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2044
2045                 bnx2x_drv_pulse(sc);
2046
2047                 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2048                 bnx2x_save_statistics(sc);
2049         }
2050
2051         /* wait till consumers catch up with producers in all queues */
2052         bnx2x_drain_tx_queues(sc);
2053
2054         /* if VF indicate to PF this function is going down (PF will delete sp
2055          * elements and clear initializations
2056          */
2057         if (IS_VF(sc)) {
2058                 bnx2x_vf_unload(sc);
2059         } else if (unload_mode != UNLOAD_RECOVERY) {
2060                 /* if this is a normal/close unload need to clean up chip */
2061                 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2062         } else {
2063                 /* Send the UNLOAD_REQUEST to the MCP */
2064                 bnx2x_send_unload_req(sc, unload_mode);
2065
2066                 /*
2067                  * Prevent transactions to host from the functions on the
2068                  * engine that doesn't reset global blocks in case of global
2069                  * attention once gloabl blocks are reset and gates are opened
2070                  * (the engine which leader will perform the recovery
2071                  * last).
2072                  */
2073                 if (!CHIP_IS_E1x(sc)) {
2074                         bnx2x_pf_disable(sc);
2075                 }
2076
2077                 /* disable HW interrupts */
2078                 bnx2x_int_disable_sync(sc, TRUE);
2079
2080                 /* Report UNLOAD_DONE to MCP */
2081                 bnx2x_send_unload_done(sc, FALSE);
2082         }
2083
2084         /*
2085          * At this stage no more interrupts will arrive so we may safely clean
2086          * the queue'able objects here in case they failed to get cleaned so far.
2087          */
2088         if (IS_PF(sc)) {
2089                 bnx2x_squeeze_objects(sc);
2090         }
2091
2092         /* There should be no more pending SP commands at this stage */
2093         sc->sp_state = 0;
2094
2095         sc->port.pmf = 0;
2096
2097         if (IS_PF(sc)) {
2098                 bnx2x_free_mem(sc);
2099         }
2100
2101         bnx2x_free_fw_stats_mem(sc);
2102
2103         sc->state = BNX2X_STATE_CLOSED;
2104
2105         /*
2106          * Check if there are pending parity attentions. If there are - set
2107          * RECOVERY_IN_PROGRESS.
2108          */
2109         if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2110                 bnx2x_set_reset_in_progress(sc);
2111
2112                 /* Set RESET_IS_GLOBAL if needed */
2113                 if (global) {
2114                         bnx2x_set_reset_global(sc);
2115                 }
2116         }
2117
2118         /*
2119          * The last driver must disable a "close the gate" if there is no
2120          * parity attention or "process kill" pending.
2121          */
2122         if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2123             bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2124                 bnx2x_disable_close_the_gate(sc);
2125         }
2126
2127         PMD_DRV_LOG(DEBUG, sc, "Ended NIC unload");
2128
2129         return 0;
2130 }
2131
2132 /*
2133  * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2134  * visible to the controller.
2135  *
2136  * If an mbuf is submitted to this routine and cannot be given to the
2137  * controller (e.g. it has too many fragments) then the function may free
2138  * the mbuf and return to the caller.
2139  *
2140  * Returns:
2141  *     int: Number of TX BDs used for the mbuf
2142  *
2143  *   Note the side effect that an mbuf may be freed if it causes a problem.
2144  */
2145 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2146 {
2147         struct eth_tx_start_bd *tx_start_bd;
2148         uint16_t bd_prod, pkt_prod;
2149         struct bnx2x_softc *sc;
2150         uint32_t nbds = 0;
2151
2152         sc = txq->sc;
2153         bd_prod = txq->tx_bd_tail;
2154         pkt_prod = txq->tx_pkt_tail;
2155
2156         txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2157
2158         tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2159
2160         tx_start_bd->addr =
2161             rte_cpu_to_le_64(rte_mbuf_data_iova(m0));
2162         tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2163         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2164         tx_start_bd->general_data =
2165             (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2166
2167         tx_start_bd->nbd = rte_cpu_to_le_16(2);
2168
2169         if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2170                 tx_start_bd->vlan_or_ethertype =
2171                     rte_cpu_to_le_16(m0->vlan_tci);
2172                 tx_start_bd->bd_flags.as_bitfield |=
2173                     (X_ETH_OUTBAND_VLAN <<
2174                      ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2175         } else {
2176                 if (IS_PF(sc))
2177                         tx_start_bd->vlan_or_ethertype =
2178                             rte_cpu_to_le_16(pkt_prod);
2179                 else {
2180                         struct ether_hdr *eh =
2181                             rte_pktmbuf_mtod(m0, struct ether_hdr *);
2182
2183                         tx_start_bd->vlan_or_ethertype =
2184                             rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2185                 }
2186         }
2187
2188         bd_prod = NEXT_TX_BD(bd_prod);
2189         if (IS_VF(sc)) {
2190                 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2191                 const struct ether_hdr *eh =
2192                     rte_pktmbuf_mtod(m0, struct ether_hdr *);
2193                 uint8_t mac_type = UNICAST_ADDRESS;
2194
2195                 tx_parse_bd =
2196                     &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2197                 if (is_multicast_ether_addr(&eh->d_addr)) {
2198                         if (is_broadcast_ether_addr(&eh->d_addr))
2199                                 mac_type = BROADCAST_ADDRESS;
2200                         else
2201                                 mac_type = MULTICAST_ADDRESS;
2202                 }
2203                 tx_parse_bd->parsing_data =
2204                     (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2205
2206                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2207                            &eh->d_addr.addr_bytes[0], 2);
2208                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2209                            &eh->d_addr.addr_bytes[2], 2);
2210                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2211                            &eh->d_addr.addr_bytes[4], 2);
2212                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2213                            &eh->s_addr.addr_bytes[0], 2);
2214                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2215                            &eh->s_addr.addr_bytes[2], 2);
2216                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2217                            &eh->s_addr.addr_bytes[4], 2);
2218
2219                 tx_parse_bd->data.mac_addr.dst_hi =
2220                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2221                 tx_parse_bd->data.mac_addr.dst_mid =
2222                     rte_cpu_to_be_16(tx_parse_bd->data.
2223                                      mac_addr.dst_mid);
2224                 tx_parse_bd->data.mac_addr.dst_lo =
2225                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2226                 tx_parse_bd->data.mac_addr.src_hi =
2227                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2228                 tx_parse_bd->data.mac_addr.src_mid =
2229                     rte_cpu_to_be_16(tx_parse_bd->data.
2230                                      mac_addr.src_mid);
2231                 tx_parse_bd->data.mac_addr.src_lo =
2232                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2233
2234                 PMD_TX_LOG(DEBUG,
2235                            "PBD dst %x %x %x src %x %x %x p_data %x",
2236                            tx_parse_bd->data.mac_addr.dst_hi,
2237                            tx_parse_bd->data.mac_addr.dst_mid,
2238                            tx_parse_bd->data.mac_addr.dst_lo,
2239                            tx_parse_bd->data.mac_addr.src_hi,
2240                            tx_parse_bd->data.mac_addr.src_mid,
2241                            tx_parse_bd->data.mac_addr.src_lo,
2242                            tx_parse_bd->parsing_data);
2243         }
2244
2245         PMD_TX_LOG(DEBUG,
2246                    "start bd: nbytes %d flags %x vlan %x",
2247                    tx_start_bd->nbytes,
2248                    tx_start_bd->bd_flags.as_bitfield,
2249                    tx_start_bd->vlan_or_ethertype);
2250
2251         bd_prod = NEXT_TX_BD(bd_prod);
2252         pkt_prod++;
2253
2254         if (TX_IDX(bd_prod) < 2)
2255                 nbds++;
2256
2257         txq->nb_tx_avail -= 2;
2258         txq->tx_bd_tail = bd_prod;
2259         txq->tx_pkt_tail = pkt_prod;
2260
2261         return nbds + 2;
2262 }
2263
2264 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2265 {
2266         return L2_ILT_LINES(sc);
2267 }
2268
2269 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2270 {
2271         struct ilt_client_info *ilt_client;
2272         struct ecore_ilt *ilt = sc->ilt;
2273         uint16_t line = 0;
2274
2275         PMD_INIT_FUNC_TRACE(sc);
2276
2277         ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2278
2279         /* CDU */
2280         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2281         ilt_client->client_num = ILT_CLIENT_CDU;
2282         ilt_client->page_size = CDU_ILT_PAGE_SZ;
2283         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2284         ilt_client->start = line;
2285         line += bnx2x_cid_ilt_lines(sc);
2286
2287         if (CNIC_SUPPORT(sc)) {
2288                 line += CNIC_ILT_LINES;
2289         }
2290
2291         ilt_client->end = (line - 1);
2292
2293         /* QM */
2294         if (QM_INIT(sc->qm_cid_count)) {
2295                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2296                 ilt_client->client_num = ILT_CLIENT_QM;
2297                 ilt_client->page_size = QM_ILT_PAGE_SZ;
2298                 ilt_client->flags = 0;
2299                 ilt_client->start = line;
2300
2301                 /* 4 bytes for each cid */
2302                 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2303                                      QM_ILT_PAGE_SZ);
2304
2305                 ilt_client->end = (line - 1);
2306         }
2307
2308         if (CNIC_SUPPORT(sc)) {
2309                 /* SRC */
2310                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2311                 ilt_client->client_num = ILT_CLIENT_SRC;
2312                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2313                 ilt_client->flags = 0;
2314                 ilt_client->start = line;
2315                 line += SRC_ILT_LINES;
2316                 ilt_client->end = (line - 1);
2317
2318                 /* TM */
2319                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2320                 ilt_client->client_num = ILT_CLIENT_TM;
2321                 ilt_client->page_size = TM_ILT_PAGE_SZ;
2322                 ilt_client->flags = 0;
2323                 ilt_client->start = line;
2324                 line += TM_ILT_LINES;
2325                 ilt_client->end = (line - 1);
2326         }
2327
2328         assert((line <= ILT_MAX_LINES));
2329 }
2330
2331 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2332 {
2333         int i;
2334
2335         for (i = 0; i < sc->num_queues; i++) {
2336                 /* get the Rx buffer size for RX frames */
2337                 sc->fp[i].rx_buf_size =
2338                     (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2339         }
2340 }
2341
2342 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2343 {
2344
2345         sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2346
2347         return sc->ilt == NULL;
2348 }
2349
2350 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2351 {
2352         sc->ilt->lines = rte_calloc("",
2353                                     sizeof(struct ilt_line), ILT_MAX_LINES,
2354                                     RTE_CACHE_LINE_SIZE);
2355         return sc->ilt->lines == NULL;
2356 }
2357
2358 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2359 {
2360         rte_free(sc->ilt);
2361         sc->ilt = NULL;
2362 }
2363
2364 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2365 {
2366         if (sc->ilt->lines != NULL) {
2367                 rte_free(sc->ilt->lines);
2368                 sc->ilt->lines = NULL;
2369         }
2370 }
2371
2372 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2373 {
2374         uint32_t i;
2375
2376         for (i = 0; i < L2_ILT_LINES(sc); i++) {
2377                 sc->context[i].vcxt = NULL;
2378                 sc->context[i].size = 0;
2379         }
2380
2381         ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2382
2383         bnx2x_free_ilt_lines_mem(sc);
2384 }
2385
2386 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2387 {
2388         int context_size;
2389         int allocated;
2390         int i;
2391         char cdu_name[RTE_MEMZONE_NAMESIZE];
2392
2393         /*
2394          * Allocate memory for CDU context:
2395          * This memory is allocated separately and not in the generic ILT
2396          * functions because CDU differs in few aspects:
2397          * 1. There can be multiple entities allocating memory for context -
2398          * regular L2, CNIC, and SRIOV drivers. Each separately controls
2399          * its own ILT lines.
2400          * 2. Since CDU page-size is not a single 4KB page (which is the case
2401          * for the other ILT clients), to be efficient we want to support
2402          * allocation of sub-page-size in the last entry.
2403          * 3. Context pointers are used by the driver to pass to FW / update
2404          * the context (for the other ILT clients the pointers are used just to
2405          * free the memory during unload).
2406          */
2407         context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2408         for (i = 0, allocated = 0; allocated < context_size; i++) {
2409                 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2410                                           (context_size - allocated));
2411
2412                 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2413                 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2414                                   &sc->context[i].vcxt_dma,
2415                                   cdu_name, BNX2X_PAGE_SIZE) != 0) {
2416                         bnx2x_free_mem(sc);
2417                         return -1;
2418                 }
2419
2420                 sc->context[i].vcxt =
2421                     (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2422
2423                 allocated += sc->context[i].size;
2424         }
2425
2426         bnx2x_alloc_ilt_lines_mem(sc);
2427
2428         if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2429                 PMD_DRV_LOG(NOTICE, sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2430                 bnx2x_free_mem(sc);
2431                 return -1;
2432         }
2433
2434         return 0;
2435 }
2436
2437 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2438 {
2439         sc->fw_stats_num = 0;
2440
2441         sc->fw_stats_req_size = 0;
2442         sc->fw_stats_req = NULL;
2443         sc->fw_stats_req_mapping = 0;
2444
2445         sc->fw_stats_data_size = 0;
2446         sc->fw_stats_data = NULL;
2447         sc->fw_stats_data_mapping = 0;
2448 }
2449
2450 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2451 {
2452         uint8_t num_queue_stats;
2453         int num_groups, vf_headroom = 0;
2454
2455         /* number of queues for statistics is number of eth queues */
2456         num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2457
2458         /*
2459          * Total number of FW statistics requests =
2460          *   1 for port stats + 1 for PF stats + num of queues
2461          */
2462         sc->fw_stats_num = (2 + num_queue_stats);
2463
2464         /*
2465          * Request is built from stats_query_header and an array of
2466          * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2467          * rules. The real number or requests is configured in the
2468          * stats_query_header.
2469          */
2470         num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2471         if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2472                 num_groups++;
2473
2474         sc->fw_stats_req_size =
2475             (sizeof(struct stats_query_header) +
2476              (num_groups * sizeof(struct stats_query_cmd_group)));
2477
2478         /*
2479          * Data for statistics requests + stats_counter.
2480          * stats_counter holds per-STORM counters that are incremented when
2481          * STORM has finished with the current request. Memory for FCoE
2482          * offloaded statistics are counted anyway, even if they will not be sent.
2483          * VF stats are not accounted for here as the data of VF stats is stored
2484          * in memory allocated by the VF, not here.
2485          */
2486         sc->fw_stats_data_size =
2487             (sizeof(struct stats_counter) +
2488              sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2489              /* sizeof(struct fcoe_statistics_params) + */
2490              (sizeof(struct per_queue_stats) * num_queue_stats));
2491
2492         if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2493                           &sc->fw_stats_dma, "fw_stats",
2494                           RTE_CACHE_LINE_SIZE) != 0) {
2495                 bnx2x_free_fw_stats_mem(sc);
2496                 return -1;
2497         }
2498
2499         /* set up the shortcuts */
2500
2501         sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2502         sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2503
2504         sc->fw_stats_data =
2505             (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2506                                          sc->fw_stats_req_size);
2507         sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2508                                      sc->fw_stats_req_size);
2509
2510         return 0;
2511 }
2512
2513 /*
2514  * Bits map:
2515  * 0-7  - Engine0 load counter.
2516  * 8-15 - Engine1 load counter.
2517  * 16   - Engine0 RESET_IN_PROGRESS bit.
2518  * 17   - Engine1 RESET_IN_PROGRESS bit.
2519  * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
2520  *        function on the engine
2521  * 19   - Engine1 ONE_IS_LOADED.
2522  * 20   - Chip reset flow bit. When set none-leader must wait for both engines
2523  *        leader to complete (check for both RESET_IN_PROGRESS bits and not
2524  *        for just the one belonging to its engine).
2525  */
2526 #define BNX2X_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
2527 #define BNX2X_PATH0_LOAD_CNT_MASK   0x000000ff
2528 #define BNX2X_PATH0_LOAD_CNT_SHIFT  0
2529 #define BNX2X_PATH1_LOAD_CNT_MASK   0x0000ff00
2530 #define BNX2X_PATH1_LOAD_CNT_SHIFT  8
2531 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2532 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2533 #define BNX2X_GLOBAL_RESET_BIT      0x00040000
2534
2535 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2536 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2537 {
2538         uint32_t val;
2539         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2540         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2541         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2542         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2543 }
2544
2545 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2546 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2547 {
2548         uint32_t val;
2549         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2550         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2551         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2552         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2553 }
2554
2555 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2556 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2557 {
2558         return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2559 }
2560
2561 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2562 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2563 {
2564         uint32_t val;
2565         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2566             BNX2X_PATH0_RST_IN_PROG_BIT;
2567
2568         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2569
2570         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2571         /* Clear the bit */
2572         val &= ~bit;
2573         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2574
2575         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2576 }
2577
2578 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2579 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2580 {
2581         uint32_t val;
2582         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2583             BNX2X_PATH0_RST_IN_PROG_BIT;
2584
2585         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2586
2587         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2588         /* Set the bit */
2589         val |= bit;
2590         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2591
2592         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2593 }
2594
2595 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2596 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2597 {
2598         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2599         uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2600             BNX2X_PATH0_RST_IN_PROG_BIT;
2601
2602         /* return false if bit is set */
2603         return (val & bit) ? FALSE : TRUE;
2604 }
2605
2606 /* get the load status for an engine, should be run under rtnl lock */
2607 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2608 {
2609         uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2610             BNX2X_PATH0_LOAD_CNT_MASK;
2611         uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2612             BNX2X_PATH0_LOAD_CNT_SHIFT;
2613         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2614
2615         val = ((val & mask) >> shift);
2616
2617         return val != 0;
2618 }
2619
2620 /* set pf load mark */
2621 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2622 {
2623         uint32_t val;
2624         uint32_t val1;
2625         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2626             BNX2X_PATH0_LOAD_CNT_MASK;
2627         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2628             BNX2X_PATH0_LOAD_CNT_SHIFT;
2629
2630         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2631
2632         PMD_INIT_FUNC_TRACE(sc);
2633
2634         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2635
2636         /* get the current counter value */
2637         val1 = ((val & mask) >> shift);
2638
2639         /* set bit of this PF */
2640         val1 |= (1 << SC_ABS_FUNC(sc));
2641
2642         /* clear the old value */
2643         val &= ~mask;
2644
2645         /* set the new one */
2646         val |= ((val1 << shift) & mask);
2647
2648         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2649
2650         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2651 }
2652
2653 /* clear pf load mark */
2654 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2655 {
2656         uint32_t val1, val;
2657         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2658             BNX2X_PATH0_LOAD_CNT_MASK;
2659         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2660             BNX2X_PATH0_LOAD_CNT_SHIFT;
2661
2662         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2663         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2664
2665         /* get the current counter value */
2666         val1 = (val & mask) >> shift;
2667
2668         /* clear bit of that PF */
2669         val1 &= ~(1 << SC_ABS_FUNC(sc));
2670
2671         /* clear the old value */
2672         val &= ~mask;
2673
2674         /* set the new one */
2675         val |= ((val1 << shift) & mask);
2676
2677         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2678         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2679         return val1 != 0;
2680 }
2681
2682 /* send load requrest to mcp and analyze response */
2683 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2684 {
2685         PMD_INIT_FUNC_TRACE(sc);
2686
2687         /* init fw_seq */
2688         sc->fw_seq =
2689             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2690              DRV_MSG_SEQ_NUMBER_MASK);
2691
2692         PMD_DRV_LOG(DEBUG, sc, "initial fw_seq 0x%04x", sc->fw_seq);
2693
2694 #ifdef BNX2X_PULSE
2695         /* get the current FW pulse sequence */
2696         sc->fw_drv_pulse_wr_seq =
2697             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2698              DRV_PULSE_SEQ_MASK);
2699 #else
2700         /* set ALWAYS_ALIVE bit in shmem */
2701         sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2702         bnx2x_drv_pulse(sc);
2703 #endif
2704
2705         /* load request */
2706         (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2707                                       DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2708
2709         /* if the MCP fails to respond we must abort */
2710         if (!(*load_code)) {
2711                 PMD_DRV_LOG(NOTICE, sc, "MCP response failure!");
2712                 return -1;
2713         }
2714
2715         /* if MCP refused then must abort */
2716         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2717                 PMD_DRV_LOG(NOTICE, sc, "MCP refused load request");
2718                 return -1;
2719         }
2720
2721         return 0;
2722 }
2723
2724 /*
2725  * Check whether another PF has already loaded FW to chip. In virtualized
2726  * environments a pf from anoth VM may have already initialized the device
2727  * including loading FW.
2728  */
2729 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2730 {
2731         uint32_t my_fw, loaded_fw;
2732
2733         /* is another pf loaded on this engine? */
2734         if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2735             (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2736                 /* build my FW version dword */
2737                 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2738                          (BNX2X_5710_FW_MINOR_VERSION << 8) +
2739                          (BNX2X_5710_FW_REVISION_VERSION << 16) +
2740                          (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2741
2742                 /* read loaded FW from chip */
2743                 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2744                 PMD_DRV_LOG(DEBUG, sc, "loaded FW 0x%08x / my FW 0x%08x",
2745                             loaded_fw, my_fw);
2746
2747                 /* abort nic load if version mismatch */
2748                 if (my_fw != loaded_fw) {
2749                         PMD_DRV_LOG(NOTICE, sc,
2750                                     "FW 0x%08x already loaded (mine is 0x%08x)",
2751                                     loaded_fw, my_fw);
2752                         return -1;
2753                 }
2754         }
2755
2756         return 0;
2757 }
2758
2759 /* mark PMF if applicable */
2760 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2761 {
2762         uint32_t ncsi_oem_data_addr;
2763
2764         PMD_INIT_FUNC_TRACE(sc);
2765
2766         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2767             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2768             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2769                 /*
2770                  * Barrier here for ordering between the writing to sc->port.pmf here
2771                  * and reading it from the periodic task.
2772                  */
2773                 sc->port.pmf = 1;
2774                 mb();
2775         } else {
2776                 sc->port.pmf = 0;
2777         }
2778
2779         PMD_DRV_LOG(DEBUG, sc, "pmf %d", sc->port.pmf);
2780
2781         if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2782                 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2783                         ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2784                         if (ncsi_oem_data_addr) {
2785                                 REG_WR(sc,
2786                                        (ncsi_oem_data_addr +
2787                                         offsetof(struct glob_ncsi_oem_data,
2788                                                  driver_version)), 0);
2789                         }
2790                 }
2791         }
2792 }
2793
2794 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2795 {
2796         int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2797         int abs_func;
2798         int vn;
2799
2800         if (BNX2X_NOMCP(sc)) {
2801                 return;         /* what should be the default bvalue in this case */
2802         }
2803
2804         /*
2805          * The formula for computing the absolute function number is...
2806          * For 2 port configuration (4 functions per port):
2807          *   abs_func = 2 * vn + SC_PORT + SC_PATH
2808          * For 4 port configuration (2 functions per port):
2809          *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2810          */
2811         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2812                 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2813                 if (abs_func >= E1H_FUNC_MAX) {
2814                         break;
2815                 }
2816                 sc->devinfo.mf_info.mf_config[vn] =
2817                     MFCFG_RD(sc, func_mf_config[abs_func].config);
2818         }
2819
2820         if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2821             FUNC_MF_CFG_FUNC_DISABLED) {
2822                 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
2823                 sc->flags |= BNX2X_MF_FUNC_DIS;
2824         } else {
2825                 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
2826                 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2827         }
2828 }
2829
2830 /* acquire split MCP access lock register */
2831 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2832 {
2833         uint32_t j, val;
2834
2835         for (j = 0; j < 1000; j++) {
2836                 val = (1UL << 31);
2837                 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2838                 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2839                 if (val & (1L << 31))
2840                         break;
2841
2842                 DELAY(5000);
2843         }
2844
2845         if (!(val & (1L << 31))) {
2846                 PMD_DRV_LOG(NOTICE, sc, "Cannot acquire MCP access lock register");
2847                 return -1;
2848         }
2849
2850         return 0;
2851 }
2852
2853 /* release split MCP access lock register */
2854 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2855 {
2856         REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2857 }
2858
2859 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2860 {
2861         int port = SC_PORT(sc);
2862         uint32_t ext_phy_config;
2863
2864         /* mark the failure */
2865         ext_phy_config =
2866             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2867
2868         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2869         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2870         SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2871                  ext_phy_config);
2872
2873         /* log the failure */
2874         PMD_DRV_LOG(INFO, sc,
2875                     "Fan Failure has caused the driver to shutdown "
2876                     "the card to prevent permanent damage. "
2877                     "Please contact OEM Support for assistance");
2878
2879         rte_panic("Schedule task to handle fan failure");
2880 }
2881
2882 /* this function is called upon a link interrupt */
2883 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2884 {
2885         uint32_t pause_enabled = 0;
2886         struct host_port_stats *pstats;
2887         int cmng_fns;
2888
2889         /* Make sure that we are synced with the current statistics */
2890         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2891
2892         elink_link_update(&sc->link_params, &sc->link_vars);
2893
2894         if (sc->link_vars.link_up) {
2895
2896                 /* dropless flow control */
2897                 if (sc->dropless_fc) {
2898                         pause_enabled = 0;
2899
2900                         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2901                                 pause_enabled = 1;
2902                         }
2903
2904                         REG_WR(sc,
2905                                (BAR_USTRORM_INTMEM +
2906                                 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2907                                pause_enabled);
2908                 }
2909
2910                 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2911                         pstats = BNX2X_SP(sc, port_stats);
2912                         /* reset old mac stats */
2913                         memset(&(pstats->mac_stx[0]), 0,
2914                                sizeof(struct mac_stx));
2915                 }
2916
2917                 if (sc->state == BNX2X_STATE_OPEN) {
2918                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2919                 }
2920         }
2921
2922         if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2923                 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2924
2925                 if (cmng_fns != CMNG_FNS_NONE) {
2926                         bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2927                         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2928                 }
2929         }
2930
2931         bnx2x_link_report_locked(sc);
2932
2933         if (IS_MF(sc)) {
2934                 bnx2x_link_sync_notify(sc);
2935         }
2936 }
2937
2938 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2939 {
2940         int port = SC_PORT(sc);
2941         uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2942             MISC_REG_AEU_MASK_ATTN_FUNC_0;
2943         uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2944             NIG_REG_MASK_INTERRUPT_PORT0;
2945         uint32_t aeu_mask;
2946         uint32_t nig_mask = 0;
2947         uint32_t reg_addr;
2948         uint32_t igu_acked;
2949         uint32_t cnt;
2950
2951         if (sc->attn_state & asserted) {
2952                 PMD_DRV_LOG(ERR, sc, "IGU ERROR attn=0x%08x", asserted);
2953         }
2954
2955         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2956
2957         aeu_mask = REG_RD(sc, aeu_addr);
2958
2959         aeu_mask &= ~(asserted & 0x3ff);
2960
2961         REG_WR(sc, aeu_addr, aeu_mask);
2962
2963         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2964
2965         sc->attn_state |= asserted;
2966
2967         if (asserted & ATTN_HARD_WIRED_MASK) {
2968                 if (asserted & ATTN_NIG_FOR_FUNC) {
2969
2970                         bnx2x_acquire_phy_lock(sc);
2971                         /* save nig interrupt mask */
2972                         nig_mask = REG_RD(sc, nig_int_mask_addr);
2973
2974                         /* If nig_mask is not set, no need to call the update function */
2975                         if (nig_mask) {
2976                                 REG_WR(sc, nig_int_mask_addr, 0);
2977
2978                                 bnx2x_link_attn(sc);
2979                         }
2980
2981                         /* handle unicore attn? */
2982                 }
2983
2984                 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2985                         PMD_DRV_LOG(DEBUG, sc, "ATTN_SW_TIMER_4_FUNC!");
2986                 }
2987
2988                 if (asserted & GPIO_2_FUNC) {
2989                         PMD_DRV_LOG(DEBUG, sc, "GPIO_2_FUNC!");
2990                 }
2991
2992                 if (asserted & GPIO_3_FUNC) {
2993                         PMD_DRV_LOG(DEBUG, sc, "GPIO_3_FUNC!");
2994                 }
2995
2996                 if (asserted & GPIO_4_FUNC) {
2997                         PMD_DRV_LOG(DEBUG, sc, "GPIO_4_FUNC!");
2998                 }
2999
3000                 if (port == 0) {
3001                         if (asserted & ATTN_GENERAL_ATTN_1) {
3002                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_1!");
3003                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3004                         }
3005                         if (asserted & ATTN_GENERAL_ATTN_2) {
3006                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_2!");
3007                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3008                         }
3009                         if (asserted & ATTN_GENERAL_ATTN_3) {
3010                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_3!");
3011                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3012                         }
3013                 } else {
3014                         if (asserted & ATTN_GENERAL_ATTN_4) {
3015                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_4!");
3016                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3017                         }
3018                         if (asserted & ATTN_GENERAL_ATTN_5) {
3019                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_5!");
3020                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3021                         }
3022                         if (asserted & ATTN_GENERAL_ATTN_6) {
3023                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_6!");
3024                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3025                         }
3026                 }
3027         }
3028         /* hardwired */
3029         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3030                 reg_addr =
3031                     (HC_REG_COMMAND_REG + port * 32 +
3032                      COMMAND_REG_ATTN_BITS_SET);
3033         } else {
3034                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3035         }
3036
3037         PMD_DRV_LOG(DEBUG, sc, "about to mask 0x%08x at %s addr 0x%08x",
3038                     asserted,
3039                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3040                     reg_addr);
3041         REG_WR(sc, reg_addr, asserted);
3042
3043         /* now set back the mask */
3044         if (asserted & ATTN_NIG_FOR_FUNC) {
3045                 /*
3046                  * Verify that IGU ack through BAR was written before restoring
3047                  * NIG mask. This loop should exit after 2-3 iterations max.
3048                  */
3049                 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3050                         cnt = 0;
3051
3052                         do {
3053                                 igu_acked =
3054                                     REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3055                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3056                                  && (++cnt < MAX_IGU_ATTN_ACK_TO));
3057
3058                         if (!igu_acked) {
3059                                 PMD_DRV_LOG(ERR, sc,
3060                                             "Failed to verify IGU ack on time");
3061                         }
3062
3063                         mb();
3064                 }
3065
3066                 REG_WR(sc, nig_int_mask_addr, nig_mask);
3067
3068                 bnx2x_release_phy_lock(sc);
3069         }
3070 }
3071
3072 static void
3073 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3074                      __rte_unused const char *blk)
3075 {
3076         PMD_DRV_LOG(INFO, sc, "%s%s", idx ? ", " : "", blk);
3077 }
3078
3079 static int
3080 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3081                               uint8_t print)
3082 {
3083         uint32_t cur_bit = 0;
3084         int i = 0;
3085
3086         for (i = 0; sig; i++) {
3087                 cur_bit = ((uint32_t) 0x1 << i);
3088                 if (sig & cur_bit) {
3089                         switch (cur_bit) {
3090                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3091                                 if (print)
3092                                         bnx2x_print_next_block(sc, par_num++,
3093                                                              "BRB");
3094                                 break;
3095                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3096                                 if (print)
3097                                         bnx2x_print_next_block(sc, par_num++,
3098                                                              "PARSER");
3099                                 break;
3100                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3101                                 if (print)
3102                                         bnx2x_print_next_block(sc, par_num++,
3103                                                              "TSDM");
3104                                 break;
3105                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3106                                 if (print)
3107                                         bnx2x_print_next_block(sc, par_num++,
3108                                                              "SEARCHER");
3109                                 break;
3110                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3111                                 if (print)
3112                                         bnx2x_print_next_block(sc, par_num++,
3113                                                              "TCM");
3114                                 break;
3115                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3116                                 if (print)
3117                                         bnx2x_print_next_block(sc, par_num++,
3118                                                              "TSEMI");
3119                                 break;
3120                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3121                                 if (print)
3122                                         bnx2x_print_next_block(sc, par_num++,
3123                                                              "XPB");
3124                                 break;
3125                         }
3126
3127                         /* Clear the bit */
3128                         sig &= ~cur_bit;
3129                 }
3130         }
3131
3132         return par_num;
3133 }
3134
3135 static int
3136 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3137                               uint8_t * global, uint8_t print)
3138 {
3139         int i = 0;
3140         uint32_t cur_bit = 0;
3141         for (i = 0; sig; i++) {
3142                 cur_bit = ((uint32_t) 0x1 << i);
3143                 if (sig & cur_bit) {
3144                         switch (cur_bit) {
3145                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3146                                 if (print)
3147                                         bnx2x_print_next_block(sc, par_num++,
3148                                                              "PBF");
3149                                 break;
3150                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3151                                 if (print)
3152                                         bnx2x_print_next_block(sc, par_num++,
3153                                                              "QM");
3154                                 break;
3155                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3156                                 if (print)
3157                                         bnx2x_print_next_block(sc, par_num++,
3158                                                              "TM");
3159                                 break;
3160                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3161                                 if (print)
3162                                         bnx2x_print_next_block(sc, par_num++,
3163                                                              "XSDM");
3164                                 break;
3165                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3166                                 if (print)
3167                                         bnx2x_print_next_block(sc, par_num++,
3168                                                              "XCM");
3169                                 break;
3170                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3171                                 if (print)
3172                                         bnx2x_print_next_block(sc, par_num++,
3173                                                              "XSEMI");
3174                                 break;
3175                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3176                                 if (print)
3177                                         bnx2x_print_next_block(sc, par_num++,
3178                                                              "DOORBELLQ");
3179                                 break;
3180                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3181                                 if (print)
3182                                         bnx2x_print_next_block(sc, par_num++,
3183                                                              "NIG");
3184                                 break;
3185                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3186                                 if (print)
3187                                         bnx2x_print_next_block(sc, par_num++,
3188                                                              "VAUX PCI CORE");
3189                                 *global = TRUE;
3190                                 break;
3191                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3192                                 if (print)
3193                                         bnx2x_print_next_block(sc, par_num++,
3194                                                              "DEBUG");
3195                                 break;
3196                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3197                                 if (print)
3198                                         bnx2x_print_next_block(sc, par_num++,
3199                                                              "USDM");
3200                                 break;
3201                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3202                                 if (print)
3203                                         bnx2x_print_next_block(sc, par_num++,
3204                                                              "UCM");
3205                                 break;
3206                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3207                                 if (print)
3208                                         bnx2x_print_next_block(sc, par_num++,
3209                                                              "USEMI");
3210                                 break;
3211                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3212                                 if (print)
3213                                         bnx2x_print_next_block(sc, par_num++,
3214                                                              "UPB");
3215                                 break;
3216                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3217                                 if (print)
3218                                         bnx2x_print_next_block(sc, par_num++,
3219                                                              "CSDM");
3220                                 break;
3221                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3222                                 if (print)
3223                                         bnx2x_print_next_block(sc, par_num++,
3224                                                              "CCM");
3225                                 break;
3226                         }
3227
3228                         /* Clear the bit */
3229                         sig &= ~cur_bit;
3230                 }
3231         }
3232
3233         return par_num;
3234 }
3235
3236 static int
3237 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3238                               uint8_t print)
3239 {
3240         uint32_t cur_bit = 0;
3241         int i = 0;
3242
3243         for (i = 0; sig; i++) {
3244                 cur_bit = ((uint32_t) 0x1 << i);
3245                 if (sig & cur_bit) {
3246                         switch (cur_bit) {
3247                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3248                                 if (print)
3249                                         bnx2x_print_next_block(sc, par_num++,
3250                                                              "CSEMI");
3251                                 break;
3252                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3253                                 if (print)
3254                                         bnx2x_print_next_block(sc, par_num++,
3255                                                              "PXP");
3256                                 break;
3257                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3258                                 if (print)
3259                                         bnx2x_print_next_block(sc, par_num++,
3260                                                              "PXPPCICLOCKCLIENT");
3261                                 break;
3262                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3263                                 if (print)
3264                                         bnx2x_print_next_block(sc, par_num++,
3265                                                              "CFC");
3266                                 break;
3267                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3268                                 if (print)
3269                                         bnx2x_print_next_block(sc, par_num++,
3270                                                              "CDU");
3271                                 break;
3272                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3273                                 if (print)
3274                                         bnx2x_print_next_block(sc, par_num++,
3275                                                              "DMAE");
3276                                 break;
3277                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3278                                 if (print)
3279                                         bnx2x_print_next_block(sc, par_num++,
3280                                                              "IGU");
3281                                 break;
3282                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3283                                 if (print)
3284                                         bnx2x_print_next_block(sc, par_num++,
3285                                                              "MISC");
3286                                 break;
3287                         }
3288
3289                         /* Clear the bit */
3290                         sig &= ~cur_bit;
3291                 }
3292         }
3293
3294         return par_num;
3295 }
3296
3297 static int
3298 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3299                               uint8_t * global, uint8_t print)
3300 {
3301         uint32_t cur_bit = 0;
3302         int i = 0;
3303
3304         for (i = 0; sig; i++) {
3305                 cur_bit = ((uint32_t) 0x1 << i);
3306                 if (sig & cur_bit) {
3307                         switch (cur_bit) {
3308                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3309                                 if (print)
3310                                         bnx2x_print_next_block(sc, par_num++,
3311                                                              "MCP ROM");
3312                                 *global = TRUE;
3313                                 break;
3314                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3315                                 if (print)
3316                                         bnx2x_print_next_block(sc, par_num++,
3317                                                              "MCP UMP RX");
3318                                 *global = TRUE;
3319                                 break;
3320                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3321                                 if (print)
3322                                         bnx2x_print_next_block(sc, par_num++,
3323                                                              "MCP UMP TX");
3324                                 *global = TRUE;
3325                                 break;
3326                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3327                                 if (print)
3328                                         bnx2x_print_next_block(sc, par_num++,
3329                                                              "MCP SCPAD");
3330                                 *global = TRUE;
3331                                 break;
3332                         }
3333
3334                         /* Clear the bit */
3335                         sig &= ~cur_bit;
3336                 }
3337         }
3338
3339         return par_num;
3340 }
3341
3342 static int
3343 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3344                               uint8_t print)
3345 {
3346         uint32_t cur_bit = 0;
3347         int i = 0;
3348
3349         for (i = 0; sig; i++) {
3350                 cur_bit = ((uint32_t) 0x1 << i);
3351                 if (sig & cur_bit) {
3352                         switch (cur_bit) {
3353                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3354                                 if (print)
3355                                         bnx2x_print_next_block(sc, par_num++,
3356                                                              "PGLUE_B");
3357                                 break;
3358                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3359                                 if (print)
3360                                         bnx2x_print_next_block(sc, par_num++,
3361                                                              "ATC");
3362                                 break;
3363                         }
3364
3365                         /* Clear the bit */
3366                         sig &= ~cur_bit;
3367                 }
3368         }
3369
3370         return par_num;
3371 }
3372
3373 static uint8_t
3374 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3375                 uint32_t * sig)
3376 {
3377         int par_num = 0;
3378
3379         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3380             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3381             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3382             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3383             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3384                 PMD_DRV_LOG(ERR, sc,
3385                             "Parity error: HW block parity attention:"
3386                             "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3387                             (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3388                             (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3389                             (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3390                             (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3391                             (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3392
3393                 if (print)
3394                         PMD_DRV_LOG(INFO, sc, "Parity errors detected in blocks: ");
3395
3396                 par_num =
3397                     bnx2x_check_blocks_with_parity0(sc, sig[0] &
3398                                                   HW_PRTY_ASSERT_SET_0,
3399                                                   par_num, print);
3400                 par_num =
3401                     bnx2x_check_blocks_with_parity1(sc, sig[1] &
3402                                                   HW_PRTY_ASSERT_SET_1,
3403                                                   par_num, global, print);
3404                 par_num =
3405                     bnx2x_check_blocks_with_parity2(sc, sig[2] &
3406                                                   HW_PRTY_ASSERT_SET_2,
3407                                                   par_num, print);
3408                 par_num =
3409                     bnx2x_check_blocks_with_parity3(sc, sig[3] &
3410                                                   HW_PRTY_ASSERT_SET_3,
3411                                                   par_num, global, print);
3412                 par_num =
3413                     bnx2x_check_blocks_with_parity4(sc, sig[4] &
3414                                                   HW_PRTY_ASSERT_SET_4,
3415                                                   par_num, print);
3416
3417                 if (print)
3418                         PMD_DRV_LOG(INFO, sc, "");
3419
3420                 return TRUE;
3421         }
3422
3423         return FALSE;
3424 }
3425
3426 static uint8_t
3427 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3428 {
3429         struct attn_route attn = { {0} };
3430         int port = SC_PORT(sc);
3431
3432         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3433         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3434         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3435         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3436
3437         if (!CHIP_IS_E1x(sc))
3438                 attn.sig[4] =
3439                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3440
3441         return bnx2x_parity_attn(sc, global, print, attn.sig);
3442 }
3443
3444 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3445 {
3446         uint32_t val;
3447
3448         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3449                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3450                 PMD_DRV_LOG(INFO, sc, "ERROR: PGLUE hw attention 0x%08x", val);
3451                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3452                         PMD_DRV_LOG(INFO, sc,
3453                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3454                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3455                         PMD_DRV_LOG(INFO, sc,
3456                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3457                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3458                         PMD_DRV_LOG(INFO, sc,
3459                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3460                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3461                         PMD_DRV_LOG(INFO, sc,
3462                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3463                 if (val &
3464                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3465                         PMD_DRV_LOG(INFO, sc,
3466                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3467                 if (val &
3468                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3469                         PMD_DRV_LOG(INFO, sc,
3470                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3471                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3472                         PMD_DRV_LOG(INFO, sc,
3473                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3474                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3475                         PMD_DRV_LOG(INFO, sc,
3476                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3477                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3478                         PMD_DRV_LOG(INFO, sc,
3479                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3480         }
3481
3482         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3483                 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3484                 PMD_DRV_LOG(INFO, sc, "ERROR: ATC hw attention 0x%08x", val);
3485                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3486                         PMD_DRV_LOG(INFO, sc,
3487                                     "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3488                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3489                         PMD_DRV_LOG(INFO, sc,
3490                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3491                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3492                         PMD_DRV_LOG(INFO, sc,
3493                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3494                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3495                         PMD_DRV_LOG(INFO, sc,
3496                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3497                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3498                         PMD_DRV_LOG(INFO, sc,
3499                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3500                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3501                         PMD_DRV_LOG(INFO, sc,
3502                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3503         }
3504
3505         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3506                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3507                 PMD_DRV_LOG(INFO, sc,
3508                             "ERROR: FATAL parity attention set4 0x%08x",
3509                             (uint32_t) (attn &
3510                                         (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3511                                          |
3512                                          AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3513         }
3514 }
3515
3516 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3517 {
3518         int port = SC_PORT(sc);
3519
3520         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3521 }
3522
3523 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3524 {
3525         int port = SC_PORT(sc);
3526
3527         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3528 }
3529
3530 /*
3531  * called due to MCP event (on pmf):
3532  *   reread new bandwidth configuration
3533  *   configure FW
3534  *   notify others function about the change
3535  */
3536 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3537 {
3538         if (sc->link_vars.link_up) {
3539                 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3540                 bnx2x_link_sync_notify(sc);
3541         }
3542
3543         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3544 }
3545
3546 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3547 {
3548         bnx2x_config_mf_bw(sc);
3549         bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3550 }
3551
3552 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3553 {
3554         bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3555 }
3556
3557 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3558
3559 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3560 {
3561         struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3562
3563         strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3564                 ETH_STAT_INFO_VERSION_LEN);
3565
3566         sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3567                                               DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3568                                               ether_stat->mac_local + MAC_PAD,
3569                                               MAC_PAD, ETH_ALEN);
3570
3571         ether_stat->mtu_size = sc->mtu;
3572
3573         ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3574         ether_stat->promiscuous_mode = 0;       // (flags & PROMISC) ? 1 : 0;
3575
3576         ether_stat->txq_size = sc->tx_ring_size;
3577         ether_stat->rxq_size = sc->rx_ring_size;
3578 }
3579
3580 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3581 {
3582         enum drv_info_opcode op_code;
3583         uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3584
3585         /* if drv_info version supported by MFW doesn't match - send NACK */
3586         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3587                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3588                 return;
3589         }
3590
3591         op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3592                    DRV_INFO_CONTROL_OP_CODE_SHIFT);
3593
3594         memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3595
3596         switch (op_code) {
3597         case ETH_STATS_OPCODE:
3598                 bnx2x_drv_info_ether_stat(sc);
3599                 break;
3600         case FCOE_STATS_OPCODE:
3601         case ISCSI_STATS_OPCODE:
3602         default:
3603                 /* if op code isn't supported - send NACK */
3604                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3605                 return;
3606         }
3607
3608         /*
3609          * If we got drv_info attn from MFW then these fields are defined in
3610          * shmem2 for sure
3611          */
3612         SHMEM2_WR(sc, drv_info_host_addr_lo,
3613                   U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3614         SHMEM2_WR(sc, drv_info_host_addr_hi,
3615                   U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3616
3617         bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3618 }
3619
3620 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3621 {
3622         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3623 /*
3624  * This is the only place besides the function initialization
3625  * where the sc->flags can change so it is done without any
3626  * locks
3627  */
3628                 if (sc->devinfo.
3629                     mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3630                         PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
3631                         sc->flags |= BNX2X_MF_FUNC_DIS;
3632                         bnx2x_e1h_disable(sc);
3633                 } else {
3634                         PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
3635                         sc->flags &= ~BNX2X_MF_FUNC_DIS;
3636                         bnx2x_e1h_enable(sc);
3637                 }
3638                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3639         }
3640
3641         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3642                 bnx2x_config_mf_bw(sc);
3643                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3644         }
3645
3646         /* Report results to MCP */
3647         if (dcc_event)
3648                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3649         else
3650                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3651 }
3652
3653 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3654 {
3655         int port = SC_PORT(sc);
3656         uint32_t val;
3657
3658         sc->port.pmf = 1;
3659
3660         /*
3661          * We need the mb() to ensure the ordering between the writing to
3662          * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3663          */
3664         mb();
3665
3666         /* enable nig attention */
3667         val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3668         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3669                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3670                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3671         } else if (!CHIP_IS_E1x(sc)) {
3672                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3673                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3674         }
3675
3676         bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3677 }
3678
3679 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3680 {
3681         char last_idx;
3682         int i, rc = 0;
3683         __rte_unused uint32_t row0, row1, row2, row3;
3684
3685         /* XSTORM */
3686         last_idx =
3687             REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3688         if (last_idx)
3689                 PMD_DRV_LOG(ERR, sc, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3690
3691         /* print the asserts */
3692         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3693
3694                 row0 =
3695                     REG_RD(sc,
3696                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3697                 row1 =
3698                     REG_RD(sc,
3699                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3700                            4);
3701                 row2 =
3702                     REG_RD(sc,
3703                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3704                            8);
3705                 row3 =
3706                     REG_RD(sc,
3707                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3708                            12);
3709
3710                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3711                         PMD_DRV_LOG(ERR, sc,
3712                                     "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3713                                     i, row3, row2, row1, row0);
3714                         rc++;
3715                 } else {
3716                         break;
3717                 }
3718         }
3719
3720         /* TSTORM */
3721         last_idx =
3722             REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3723         if (last_idx) {
3724                 PMD_DRV_LOG(ERR, sc, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3725         }
3726
3727         /* print the asserts */
3728         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3729
3730                 row0 =
3731                     REG_RD(sc,
3732                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3733                 row1 =
3734                     REG_RD(sc,
3735                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3736                            4);
3737                 row2 =
3738                     REG_RD(sc,
3739                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3740                            8);
3741                 row3 =
3742                     REG_RD(sc,
3743                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3744                            12);
3745
3746                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3747                         PMD_DRV_LOG(ERR, sc,
3748                                     "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3749                                     i, row3, row2, row1, row0);
3750                         rc++;
3751                 } else {
3752                         break;
3753                 }
3754         }
3755
3756         /* CSTORM */
3757         last_idx =
3758             REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3759         if (last_idx) {
3760                 PMD_DRV_LOG(ERR, sc, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3761         }
3762
3763         /* print the asserts */
3764         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3765
3766                 row0 =
3767                     REG_RD(sc,
3768                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3769                 row1 =
3770                     REG_RD(sc,
3771                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3772                            4);
3773                 row2 =
3774                     REG_RD(sc,
3775                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3776                            8);
3777                 row3 =
3778                     REG_RD(sc,
3779                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3780                            12);
3781
3782                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3783                         PMD_DRV_LOG(ERR, sc,
3784                                     "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3785                                     i, row3, row2, row1, row0);
3786                         rc++;
3787                 } else {
3788                         break;
3789                 }
3790         }
3791
3792         /* USTORM */
3793         last_idx =
3794             REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3795         if (last_idx) {
3796                 PMD_DRV_LOG(ERR, sc, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3797         }
3798
3799         /* print the asserts */
3800         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3801
3802                 row0 =
3803                     REG_RD(sc,
3804                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3805                 row1 =
3806                     REG_RD(sc,
3807                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3808                            4);
3809                 row2 =
3810                     REG_RD(sc,
3811                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3812                            8);
3813                 row3 =
3814                     REG_RD(sc,
3815                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3816                            12);
3817
3818                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3819                         PMD_DRV_LOG(ERR, sc,
3820                                     "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3821                                     i, row3, row2, row1, row0);
3822                         rc++;
3823                 } else {
3824                         break;
3825                 }
3826         }
3827
3828         return rc;
3829 }
3830
3831 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3832 {
3833         int func = SC_FUNC(sc);
3834         uint32_t val;
3835
3836         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3837
3838                 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3839
3840                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3841                         bnx2x_read_mf_cfg(sc);
3842                         sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3843                             MFCFG_RD(sc,
3844                                      func_mf_config[SC_ABS_FUNC(sc)].config);
3845                         val =
3846                             SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3847
3848                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3849                                 bnx2x_dcc_event(sc,
3850                                               (val &
3851                                                DRV_STATUS_DCC_EVENT_MASK));
3852
3853                         if (val & DRV_STATUS_SET_MF_BW)
3854                                 bnx2x_set_mf_bw(sc);
3855
3856                         if (val & DRV_STATUS_DRV_INFO_REQ)
3857                                 bnx2x_handle_drv_info_req(sc);
3858
3859                         if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3860                                 bnx2x_pmf_update(sc);
3861
3862                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3863                                 bnx2x_handle_eee_event(sc);
3864
3865                         if (sc->link_vars.periodic_flags &
3866                             ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3867                                 /* sync with link */
3868                                 bnx2x_acquire_phy_lock(sc);
3869                                 sc->link_vars.periodic_flags &=
3870                                     ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3871                                 bnx2x_release_phy_lock(sc);
3872                                 if (IS_MF(sc)) {
3873                                         bnx2x_link_sync_notify(sc);
3874                                 }
3875                                 bnx2x_link_report(sc);
3876                         }
3877
3878                         /*
3879                          * Always call it here: bnx2x_link_report() will
3880                          * prevent the link indication duplication.
3881                          */
3882                         bnx2x_link_status_update(sc);
3883
3884                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3885
3886                         PMD_DRV_LOG(ERR, sc, "MC assert!");
3887                         bnx2x_mc_assert(sc);
3888                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3889                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3890                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3891                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3892                         rte_panic("MC assert!");
3893
3894                 } else if (attn & BNX2X_MCP_ASSERT) {
3895
3896                         PMD_DRV_LOG(ERR, sc, "MCP assert!");
3897                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3898
3899                 } else {
3900                         PMD_DRV_LOG(ERR, sc,
3901                                     "Unknown HW assert! (attn 0x%08x)", attn);
3902                 }
3903         }
3904
3905         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3906                 PMD_DRV_LOG(ERR, sc, "LATCHED attention 0x%08x (masked)", attn);
3907                 if (attn & BNX2X_GRC_TIMEOUT) {
3908                         val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3909                         PMD_DRV_LOG(ERR, sc, "GRC time-out 0x%08x", val);
3910                 }
3911                 if (attn & BNX2X_GRC_RSV) {
3912                         val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3913                         PMD_DRV_LOG(ERR, sc, "GRC reserved 0x%08x", val);
3914                 }
3915                 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3916         }
3917 }
3918
3919 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3920 {
3921         int port = SC_PORT(sc);
3922         int reg_offset;
3923         uint32_t val0, mask0, val1, mask1;
3924         uint32_t val;
3925
3926         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3927                 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3928                 PMD_DRV_LOG(ERR, sc, "CFC hw attention 0x%08x", val);
3929 /* CFC error attention */
3930                 if (val & 0x2) {
3931                         PMD_DRV_LOG(ERR, sc, "FATAL error from CFC");
3932                 }
3933         }
3934
3935         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3936                 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3937                 PMD_DRV_LOG(ERR, sc, "PXP hw attention-0 0x%08x", val);
3938 /* RQ_USDMDP_FIFO_OVERFLOW */
3939                 if (val & 0x18000) {
3940                         PMD_DRV_LOG(ERR, sc, "FATAL error from PXP");
3941                 }
3942
3943                 if (!CHIP_IS_E1x(sc)) {
3944                         val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3945                         PMD_DRV_LOG(ERR, sc, "PXP hw attention-1 0x%08x", val);
3946                 }
3947         }
3948 #define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3949 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3950
3951         if (attn & AEU_PXP2_HW_INT_BIT) {
3952 /*  CQ47854 workaround do not panic on
3953  *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3954  */
3955                 if (!CHIP_IS_E1x(sc)) {
3956                         mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3957                         val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3958                         mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3959                         val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3960                         /*
3961                          * If the only PXP2_EOP_ERROR_BIT is set in
3962                          * STS0 and STS1 - clear it
3963                          *
3964                          * probably we lose additional attentions between
3965                          * STS0 and STS_CLR0, in this case user will not
3966                          * be notified about them
3967                          */
3968                         if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3969                             !(val1 & mask1))
3970                                 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3971
3972                         /* print the register, since no one can restore it */
3973                         PMD_DRV_LOG(ERR, sc,
3974                                     "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3975
3976                         /*
3977                          * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3978                          * then notify
3979                          */
3980                         if (val0 & PXP2_EOP_ERROR_BIT) {
3981                                 PMD_DRV_LOG(ERR, sc, "PXP2_WR_PGLUE_EOP_ERROR");
3982
3983                                 /*
3984                                  * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3985                                  * set then clear attention from PXP2 block without panic
3986                                  */
3987                                 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3988                                     ((val1 & mask1) == 0))
3989                                         attn &= ~AEU_PXP2_HW_INT_BIT;
3990                         }
3991                 }
3992         }
3993
3994         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3995                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3996                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3997
3998                 val = REG_RD(sc, reg_offset);
3999                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4000                 REG_WR(sc, reg_offset, val);
4001
4002                 PMD_DRV_LOG(ERR, sc,
4003                             "FATAL HW block attention set2 0x%x",
4004                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
4005                 rte_panic("HW block attention set2");
4006         }
4007 }
4008
4009 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
4010 {
4011         int port = SC_PORT(sc);
4012         int reg_offset;
4013         uint32_t val;
4014
4015         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4016                 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
4017                 PMD_DRV_LOG(ERR, sc, "DB hw attention 0x%08x", val);
4018 /* DORQ discard attention */
4019                 if (val & 0x2) {
4020                         PMD_DRV_LOG(ERR, sc, "FATAL error from DORQ");
4021                 }
4022         }
4023
4024         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4025                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4026                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4027
4028                 val = REG_RD(sc, reg_offset);
4029                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4030                 REG_WR(sc, reg_offset, val);
4031
4032                 PMD_DRV_LOG(ERR, sc,
4033                             "FATAL HW block attention set1 0x%08x",
4034                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4035                 rte_panic("HW block attention set1");
4036         }
4037 }
4038
4039 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4040 {
4041         int port = SC_PORT(sc);
4042         int reg_offset;
4043         uint32_t val;
4044
4045         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4046             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4047
4048         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4049                 val = REG_RD(sc, reg_offset);
4050                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4051                 REG_WR(sc, reg_offset, val);
4052
4053                 PMD_DRV_LOG(WARNING, sc, "SPIO5 hw attention");
4054
4055 /* Fan failure attention */
4056                 elink_hw_reset_phy(&sc->link_params);
4057                 bnx2x_fan_failure(sc);
4058         }
4059
4060         if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4061                 bnx2x_acquire_phy_lock(sc);
4062                 elink_handle_module_detect_int(&sc->link_params);
4063                 bnx2x_release_phy_lock(sc);
4064         }
4065
4066         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4067                 val = REG_RD(sc, reg_offset);
4068                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4069                 REG_WR(sc, reg_offset, val);
4070
4071                 rte_panic("FATAL HW block attention set0 0x%lx",
4072                           (attn & HW_INTERRUT_ASSERT_SET_0));
4073         }
4074 }
4075
4076 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4077 {
4078         struct attn_route attn;
4079         struct attn_route *group_mask;
4080         int port = SC_PORT(sc);
4081         int index;
4082         uint32_t reg_addr;
4083         uint32_t val;
4084         uint32_t aeu_mask;
4085         uint8_t global = FALSE;
4086
4087         /*
4088          * Need to take HW lock because MCP or other port might also
4089          * try to handle this event.
4090          */
4091         bnx2x_acquire_alr(sc);
4092
4093         if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4094                 sc->recovery_state = BNX2X_RECOVERY_INIT;
4095
4096 /* disable HW interrupts */
4097                 bnx2x_int_disable(sc);
4098                 bnx2x_release_alr(sc);
4099                 return;
4100         }
4101
4102         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4103         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4104         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4105         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4106         if (!CHIP_IS_E1x(sc)) {
4107                 attn.sig[4] =
4108                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4109         } else {
4110                 attn.sig[4] = 0;
4111         }
4112
4113         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4114                 if (deasserted & (1 << index)) {
4115                         group_mask = &sc->attn_group[index];
4116
4117                         bnx2x_attn_int_deasserted4(sc,
4118                                                  attn.
4119                                                  sig[4] & group_mask->sig[4]);
4120                         bnx2x_attn_int_deasserted3(sc,
4121                                                  attn.
4122                                                  sig[3] & group_mask->sig[3]);
4123                         bnx2x_attn_int_deasserted1(sc,
4124                                                  attn.
4125                                                  sig[1] & group_mask->sig[1]);
4126                         bnx2x_attn_int_deasserted2(sc,
4127                                                  attn.
4128                                                  sig[2] & group_mask->sig[2]);
4129                         bnx2x_attn_int_deasserted0(sc,
4130                                                  attn.
4131                                                  sig[0] & group_mask->sig[0]);
4132                 }
4133         }
4134
4135         bnx2x_release_alr(sc);
4136
4137         if (sc->devinfo.int_block == INT_BLOCK_HC) {
4138                 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4139                             COMMAND_REG_ATTN_BITS_CLR);
4140         } else {
4141                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4142         }
4143
4144         val = ~deasserted;
4145         PMD_DRV_LOG(DEBUG, sc,
4146                     "about to mask 0x%08x at %s addr 0x%08x", val,
4147                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4148                     reg_addr);
4149         REG_WR(sc, reg_addr, val);
4150
4151         if (~sc->attn_state & deasserted) {
4152                 PMD_DRV_LOG(ERR, sc, "IGU error");
4153         }
4154
4155         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4156             MISC_REG_AEU_MASK_ATTN_FUNC_0;
4157
4158         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4159
4160         aeu_mask = REG_RD(sc, reg_addr);
4161
4162         aeu_mask |= (deasserted & 0x3ff);
4163
4164         REG_WR(sc, reg_addr, aeu_mask);
4165         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4166
4167         sc->attn_state &= ~deasserted;
4168 }
4169
4170 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4171 {
4172         /* read local copy of bits */
4173         uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4174         uint32_t attn_ack =
4175             le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4176         uint32_t attn_state = sc->attn_state;
4177
4178         /* look for changed bits */
4179         uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4180         uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4181
4182         PMD_DRV_LOG(DEBUG, sc,
4183                     "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4184                     attn_bits, attn_ack, asserted, deasserted);
4185
4186         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4187                 PMD_DRV_LOG(ERR, sc, "BAD attention state");
4188         }
4189
4190         /* handle bits that were raised */
4191         if (asserted) {
4192                 bnx2x_attn_int_asserted(sc, asserted);
4193         }
4194
4195         if (deasserted) {
4196                 bnx2x_attn_int_deasserted(sc, deasserted);
4197         }
4198 }
4199
4200 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4201 {
4202         struct host_sp_status_block *def_sb = sc->def_sb;
4203         uint16_t rc = 0;
4204
4205         if (!def_sb)
4206                 return 0;
4207
4208         mb();                   /* status block is written to by the chip */
4209
4210         if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4211                 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4212                 rc |= BNX2X_DEF_SB_ATT_IDX;
4213         }
4214
4215         if (sc->def_idx != def_sb->sp_sb.running_index) {
4216                 sc->def_idx = def_sb->sp_sb.running_index;
4217                 rc |= BNX2X_DEF_SB_IDX;
4218         }
4219
4220         mb();
4221
4222         return rc;
4223 }
4224
4225 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4226                                                           uint32_t cid)
4227 {
4228         return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4229 }
4230
4231 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4232 {
4233         struct ecore_mcast_ramrod_params rparam;
4234         int rc;
4235
4236         memset(&rparam, 0, sizeof(rparam));
4237
4238         rparam.mcast_obj = &sc->mcast_obj;
4239
4240         /* clear pending state for the last command */
4241         sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4242
4243         /* if there are pending mcast commands - send them */
4244         if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4245                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4246                 if (rc < 0) {
4247                         PMD_DRV_LOG(INFO, sc,
4248                                     "Failed to send pending mcast commands (%d)",
4249                                     rc);
4250                 }
4251         }
4252 }
4253
4254 static void
4255 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4256 {
4257         unsigned long ramrod_flags = 0;
4258         int rc = 0;
4259         uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4260         struct ecore_vlan_mac_obj *vlan_mac_obj;
4261
4262         /* always push next commands out, don't wait here */
4263         bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4264
4265         switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4266         case ECORE_FILTER_MAC_PENDING:
4267                 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MAC completions");
4268                 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4269                 break;
4270
4271         case ECORE_FILTER_MCAST_PENDING:
4272                 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MCAST completions");
4273                 bnx2x_handle_mcast_eqe(sc);
4274                 return;
4275
4276         default:
4277                 PMD_DRV_LOG(NOTICE, sc, "Unsupported classification command: %d",
4278                             elem->message.data.eth_event.echo);
4279                 return;
4280         }
4281
4282         rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4283
4284         if (rc < 0) {
4285                 PMD_DRV_LOG(NOTICE, sc,
4286                             "Failed to schedule new commands (%d)", rc);
4287         } else if (rc > 0) {
4288                 PMD_DRV_LOG(DEBUG, sc, "Scheduled next pending commands...");
4289         }
4290 }
4291
4292 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4293 {
4294         bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4295
4296         /* send rx_mode command again if was requested */
4297         if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4298                 bnx2x_set_storm_rx_mode(sc);
4299         }
4300 }
4301
4302 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4303 {
4304         storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4305         wmb();                  /* keep prod updates ordered */
4306 }
4307
4308 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4309 {
4310         uint16_t hw_cons, sw_cons, sw_prod;
4311         union event_ring_elem *elem;
4312         uint8_t echo;
4313         uint32_t cid;
4314         uint8_t opcode;
4315         int spqe_cnt = 0;
4316         struct ecore_queue_sp_obj *q_obj;
4317         struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4318         struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4319
4320         hw_cons = le16toh(*sc->eq_cons_sb);
4321
4322         /*
4323          * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4324          * when we get to the next-page we need to adjust so the loop
4325          * condition below will be met. The next element is the size of a
4326          * regular element and hence incrementing by 1
4327          */
4328         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4329                 hw_cons++;
4330         }
4331
4332         /*
4333          * This function may never run in parallel with itself for a
4334          * specific sc and no need for a read memory barrier here.
4335          */
4336         sw_cons = sc->eq_cons;
4337         sw_prod = sc->eq_prod;
4338
4339         for (;
4340              sw_cons != hw_cons;
4341              sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4342
4343                 elem = &sc->eq[EQ_DESC(sw_cons)];
4344
4345 /* elem CID originates from FW, actually LE */
4346                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4347                 opcode = elem->message.opcode;
4348
4349 /* handle eq element */
4350                 switch (opcode) {
4351                 case EVENT_RING_OPCODE_STAT_QUERY:
4352                         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "got statistics completion event %d",
4353                                     sc->stats_comp++);
4354                         /* nothing to do with stats comp */
4355                         goto next_spqe;
4356
4357                 case EVENT_RING_OPCODE_CFC_DEL:
4358                         /* handle according to cid range */
4359                         /* we may want to verify here that the sc state is HALTING */
4360                         PMD_DRV_LOG(DEBUG, sc, "got delete ramrod for MULTI[%d]",
4361                                     cid);
4362                         q_obj = bnx2x_cid_to_q_obj(sc, cid);
4363                         if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4364                                 break;
4365                         }
4366                         goto next_spqe;
4367
4368                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4369                         PMD_DRV_LOG(DEBUG, sc, "got STOP TRAFFIC");
4370                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4371                                 break;
4372                         }
4373                         goto next_spqe;
4374
4375                 case EVENT_RING_OPCODE_START_TRAFFIC:
4376                         PMD_DRV_LOG(DEBUG, sc, "got START TRAFFIC");
4377                         if (f_obj->complete_cmd
4378                             (sc, f_obj, ECORE_F_CMD_TX_START)) {
4379                                 break;
4380                         }
4381                         goto next_spqe;
4382
4383                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4384                         echo = elem->message.data.function_update_event.echo;
4385                         if (echo == SWITCH_UPDATE) {
4386                                 PMD_DRV_LOG(DEBUG, sc,
4387                                             "got FUNC_SWITCH_UPDATE ramrod");
4388                                 if (f_obj->complete_cmd(sc, f_obj,
4389                                                         ECORE_F_CMD_SWITCH_UPDATE))
4390                                 {
4391                                         break;
4392                                 }
4393                         } else {
4394                                 PMD_DRV_LOG(DEBUG, sc,
4395                                             "AFEX: ramrod completed FUNCTION_UPDATE");
4396                                 f_obj->complete_cmd(sc, f_obj,
4397                                                     ECORE_F_CMD_AFEX_UPDATE);
4398                         }
4399                         goto next_spqe;
4400
4401                 case EVENT_RING_OPCODE_FORWARD_SETUP:
4402                         q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4403                         if (q_obj->complete_cmd(sc, q_obj,
4404                                                 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4405                                 break;
4406                         }
4407                         goto next_spqe;
4408
4409                 case EVENT_RING_OPCODE_FUNCTION_START:
4410                         PMD_DRV_LOG(DEBUG, sc, "got FUNC_START ramrod");
4411                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4412                                 break;
4413                         }
4414                         goto next_spqe;
4415
4416                 case EVENT_RING_OPCODE_FUNCTION_STOP:
4417                         PMD_DRV_LOG(DEBUG, sc, "got FUNC_STOP ramrod");
4418                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4419                                 break;
4420                         }
4421                         goto next_spqe;
4422                 }
4423
4424                 switch (opcode | sc->state) {
4425                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4426                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4427                         cid =
4428                             elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4429                         PMD_DRV_LOG(DEBUG, sc, "got RSS_UPDATE ramrod. CID %d",
4430                                     cid);
4431                         rss_raw->clear_pending(rss_raw);
4432                         break;
4433
4434                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4435                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4436                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4437                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4438                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4439                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4440                         PMD_DRV_LOG(DEBUG, sc,
4441                                     "got (un)set mac ramrod");
4442                         bnx2x_handle_classification_eqe(sc, elem);
4443                         break;
4444
4445                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4446                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4447                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4448                         PMD_DRV_LOG(DEBUG, sc,
4449                                     "got mcast ramrod");
4450                         bnx2x_handle_mcast_eqe(sc);
4451                         break;
4452
4453                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4454                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4455                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4456                         PMD_DRV_LOG(DEBUG, sc,
4457                                     "got rx_mode ramrod");
4458                         bnx2x_handle_rx_mode_eqe(sc);
4459                         break;
4460
4461                 default:
4462                         /* unknown event log error and continue */
4463                         PMD_DRV_LOG(INFO, sc, "Unknown EQ event %d, sc->state 0x%x",
4464                                     elem->message.opcode, sc->state);
4465                 }
4466
4467 next_spqe:
4468                 spqe_cnt++;
4469         }                       /* for */
4470
4471         mb();
4472         atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4473
4474         sc->eq_cons = sw_cons;
4475         sc->eq_prod = sw_prod;
4476
4477         /* make sure that above mem writes were issued towards the memory */
4478         wmb();
4479
4480         /* update producer */
4481         bnx2x_update_eq_prod(sc, sc->eq_prod);
4482 }
4483
4484 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4485 {
4486         uint16_t status;
4487         int rc = 0;
4488
4489         PMD_DRV_LOG(DEBUG, sc, "---> SP TASK <---");
4490
4491         /* what work needs to be performed? */
4492         status = bnx2x_update_dsb_idx(sc);
4493
4494         PMD_DRV_LOG(DEBUG, sc, "dsb status 0x%04x", status);
4495
4496         /* HW attentions */
4497         if (status & BNX2X_DEF_SB_ATT_IDX) {
4498                 PMD_DRV_LOG(DEBUG, sc, "---> ATTN INTR <---");
4499                 bnx2x_attn_int(sc);
4500                 status &= ~BNX2X_DEF_SB_ATT_IDX;
4501                 rc = 1;
4502         }
4503
4504         /* SP events: STAT_QUERY and others */
4505         if (status & BNX2X_DEF_SB_IDX) {
4506 /* handle EQ completions */
4507                 PMD_DRV_LOG(DEBUG, sc, "---> EQ INTR <---");
4508                 bnx2x_eq_int(sc);
4509                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4510                            le16toh(sc->def_idx), IGU_INT_NOP, 1);
4511                 status &= ~BNX2X_DEF_SB_IDX;
4512         }
4513
4514         /* if status is non zero then something went wrong */
4515         if (unlikely(status)) {
4516                 PMD_DRV_LOG(INFO, sc,
4517                             "Got an unknown SP interrupt! (0x%04x)", status);
4518         }
4519
4520         /* ack status block only if something was actually handled */
4521         bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4522                    le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4523
4524         return rc;
4525 }
4526
4527 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4528 {
4529         struct bnx2x_softc *sc = fp->sc;
4530         uint8_t more_rx = FALSE;
4531
4532         /* Make sure FP is initialized */
4533         if (!fp->sb_running_index)
4534                 return;
4535
4536         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc,
4537                                "---> FP TASK QUEUE (%d) <--", fp->index);
4538
4539         /* update the fastpath index */
4540         bnx2x_update_fp_sb_idx(fp);
4541
4542         if (scan_fp) {
4543                 if (bnx2x_has_rx_work(fp)) {
4544                         more_rx = bnx2x_rxeof(sc, fp);
4545                 }
4546
4547                 if (more_rx) {
4548                         /* still more work to do */
4549                         bnx2x_handle_fp_tq(fp, scan_fp);
4550                         return;
4551                 }
4552         }
4553
4554         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4555                    le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4556 }
4557
4558 /*
4559  * Legacy interrupt entry point.
4560  *
4561  * Verifies that the controller generated the interrupt and
4562  * then calls a separate routine to handle the various
4563  * interrupt causes: link, RX, and TX.
4564  */
4565 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4566 {
4567         struct bnx2x_fastpath *fp;
4568         uint32_t status, mask;
4569         int i, rc = 0;
4570
4571         /*
4572          * 0 for ustorm, 1 for cstorm
4573          * the bits returned from ack_int() are 0-15
4574          * bit 0 = attention status block
4575          * bit 1 = fast path status block
4576          * a mask of 0x2 or more = tx/rx event
4577          * a mask of 1 = slow path event
4578          */
4579
4580         status = bnx2x_ack_int(sc);
4581
4582         /* the interrupt is not for us */
4583         if (unlikely(status == 0)) {
4584                 return 0;
4585         }
4586
4587         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "Interrupt status 0x%04x", status);
4588         //bnx2x_dump_status_block(sc);
4589
4590         FOR_EACH_ETH_QUEUE(sc, i) {
4591                 fp = &sc->fp[i];
4592                 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4593                 if (status & mask) {
4594                 /* acknowledge and disable further fastpath interrupts */
4595                         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4596                                      0, IGU_INT_DISABLE, 0);
4597                         bnx2x_handle_fp_tq(fp, scan_fp);
4598                         status &= ~mask;
4599                 }
4600         }
4601
4602         if (unlikely(status & 0x1)) {
4603                 /* acknowledge and disable further slowpath interrupts */
4604                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4605                              0, IGU_INT_DISABLE, 0);
4606                 rc = bnx2x_handle_sp_tq(sc);
4607                 status &= ~0x1;
4608         }
4609
4610         if (unlikely(status)) {
4611                 PMD_DRV_LOG(WARNING, sc,
4612                             "Unexpected fastpath status (0x%08x)!", status);
4613         }
4614
4615         return rc;
4616 }
4617
4618 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4619 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4620 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4621 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4622 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4623 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4624 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4625 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4626 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4627
4628 static struct
4629 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4630         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4631         .init_hw_cmn = bnx2x_init_hw_common,
4632         .init_hw_port = bnx2x_init_hw_port,
4633         .init_hw_func = bnx2x_init_hw_func,
4634
4635         .reset_hw_cmn = bnx2x_reset_common,
4636         .reset_hw_port = bnx2x_reset_port,
4637         .reset_hw_func = bnx2x_reset_func,
4638
4639         .init_fw = bnx2x_init_firmware,
4640         .release_fw = bnx2x_release_firmware,
4641 };
4642
4643 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4644 {
4645         sc->dmae_ready = 0;
4646
4647         PMD_INIT_FUNC_TRACE(sc);
4648
4649         ecore_init_func_obj(sc,
4650                             &sc->func_obj,
4651                             BNX2X_SP(sc, func_rdata),
4652                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata),
4653                             BNX2X_SP(sc, func_afex_rdata),
4654                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4655                             &bnx2x_func_sp_drv);
4656 }
4657
4658 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4659 {
4660         struct ecore_func_state_params func_params = { NULL };
4661         int rc;
4662
4663         PMD_INIT_FUNC_TRACE(sc);
4664
4665         /* prepare the parameters for function state transitions */
4666         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4667
4668         func_params.f_obj = &sc->func_obj;
4669         func_params.cmd = ECORE_F_CMD_HW_INIT;
4670
4671         func_params.params.hw_init.load_phase = load_code;
4672
4673         /*
4674          * Via a plethora of function pointers, we will eventually reach
4675          * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4676          */
4677         rc = ecore_func_state_change(sc, &func_params);
4678
4679         return rc;
4680 }
4681
4682 static void
4683 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4684 {
4685         uint32_t i;
4686
4687         if (!(len % 4) && !(addr % 4)) {
4688                 for (i = 0; i < len; i += 4) {
4689                         REG_WR(sc, (addr + i), fill);
4690                 }
4691         } else {
4692                 for (i = 0; i < len; i++) {
4693                         REG_WR8(sc, (addr + i), fill);
4694                 }
4695         }
4696 }
4697
4698 /* writes FP SP data to FW - data_size in dwords */
4699 static void
4700 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4701                   uint32_t data_size)
4702 {
4703         uint32_t index;
4704
4705         for (index = 0; index < data_size; index++) {
4706                 REG_WR(sc,
4707                        (BAR_CSTRORM_INTMEM +
4708                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4709                         (sizeof(uint32_t) * index)), *(sb_data_p + index));
4710         }
4711 }
4712
4713 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4714 {
4715         struct hc_status_block_data_e2 sb_data_e2;
4716         struct hc_status_block_data_e1x sb_data_e1x;
4717         uint32_t *sb_data_p;
4718         uint32_t data_size = 0;
4719
4720         if (!CHIP_IS_E1x(sc)) {
4721                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4722                 sb_data_e2.common.state = SB_DISABLED;
4723                 sb_data_e2.common.p_func.vf_valid = FALSE;
4724                 sb_data_p = (uint32_t *) & sb_data_e2;
4725                 data_size = (sizeof(struct hc_status_block_data_e2) /
4726                              sizeof(uint32_t));
4727         } else {
4728                 memset(&sb_data_e1x, 0,
4729                        sizeof(struct hc_status_block_data_e1x));
4730                 sb_data_e1x.common.state = SB_DISABLED;
4731                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4732                 sb_data_p = (uint32_t *) & sb_data_e1x;
4733                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4734                              sizeof(uint32_t));
4735         }
4736
4737         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4738
4739         bnx2x_fill(sc,
4740                  (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4741                  CSTORM_STATUS_BLOCK_SIZE);
4742         bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4743                  0, CSTORM_SYNC_BLOCK_SIZE);
4744 }
4745
4746 static void
4747 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4748                   struct hc_sp_status_block_data *sp_sb_data)
4749 {
4750         uint32_t i;
4751
4752         for (i = 0;
4753              i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4754              i++) {
4755                 REG_WR(sc,
4756                        (BAR_CSTRORM_INTMEM +
4757                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4758                         (i * sizeof(uint32_t))),
4759                        *((uint32_t *) sp_sb_data + i));
4760         }
4761 }
4762
4763 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4764 {
4765         struct hc_sp_status_block_data sp_sb_data;
4766
4767         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4768
4769         sp_sb_data.state = SB_DISABLED;
4770         sp_sb_data.p_func.vf_valid = FALSE;
4771
4772         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4773
4774         bnx2x_fill(sc,
4775                  (BAR_CSTRORM_INTMEM +
4776                   CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4777                  0, CSTORM_SP_STATUS_BLOCK_SIZE);
4778         bnx2x_fill(sc,
4779                  (BAR_CSTRORM_INTMEM +
4780                   CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4781                  0, CSTORM_SP_SYNC_BLOCK_SIZE);
4782 }
4783
4784 static void
4785 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4786                              int igu_seg_id)
4787 {
4788         hc_sm->igu_sb_id = igu_sb_id;
4789         hc_sm->igu_seg_id = igu_seg_id;
4790         hc_sm->timer_value = 0xFF;
4791         hc_sm->time_to_expire = 0xFFFFFFFF;
4792 }
4793
4794 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4795 {
4796         /* zero out state machine indices */
4797
4798         /* rx indices */
4799         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4800
4801         /* tx indices */
4802         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4803         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4804         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4805         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4806
4807         /* map indices */
4808
4809         /* rx indices */
4810         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4811             (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4812
4813         /* tx indices */
4814         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4815             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4816         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4817             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4818         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4819             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4820         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4821             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4822 }
4823
4824 static void
4825 bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid,
4826             uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4827 {
4828         struct hc_status_block_data_e2 sb_data_e2;
4829         struct hc_status_block_data_e1x sb_data_e1x;
4830         struct hc_status_block_sm *hc_sm_p;
4831         uint32_t *sb_data_p;
4832         int igu_seg_id;
4833         int data_size;
4834
4835         if (CHIP_INT_MODE_IS_BC(sc)) {
4836                 igu_seg_id = HC_SEG_ACCESS_NORM;
4837         } else {
4838                 igu_seg_id = IGU_SEG_ACCESS_NORM;
4839         }
4840
4841         bnx2x_zero_fp_sb(sc, fw_sb_id);
4842
4843         if (!CHIP_IS_E1x(sc)) {
4844                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4845                 sb_data_e2.common.state = SB_ENABLED;
4846                 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4847                 sb_data_e2.common.p_func.vf_id = vfid;
4848                 sb_data_e2.common.p_func.vf_valid = vf_valid;
4849                 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4850                 sb_data_e2.common.same_igu_sb_1b = TRUE;
4851                 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4852                 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4853                 hc_sm_p = sb_data_e2.common.state_machine;
4854                 sb_data_p = (uint32_t *) & sb_data_e2;
4855                 data_size = (sizeof(struct hc_status_block_data_e2) /
4856                              sizeof(uint32_t));
4857                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4858         } else {
4859                 memset(&sb_data_e1x, 0,
4860                        sizeof(struct hc_status_block_data_e1x));
4861                 sb_data_e1x.common.state = SB_ENABLED;
4862                 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4863                 sb_data_e1x.common.p_func.vf_id = 0xff;
4864                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4865                 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4866                 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4867                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4868                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4869                 hc_sm_p = sb_data_e1x.common.state_machine;
4870                 sb_data_p = (uint32_t *) & sb_data_e1x;
4871                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4872                              sizeof(uint32_t));
4873                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4874         }
4875
4876         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4877         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4878
4879         /* write indices to HW - PCI guarantees endianity of regpairs */
4880         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4881 }
4882
4883 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4884 {
4885         if (CHIP_IS_E1x(fp->sc)) {
4886                 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4887         } else {
4888                 return fp->cl_id;
4889         }
4890 }
4891
4892 static uint32_t
4893 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4894 {
4895         uint32_t offset = BAR_USTRORM_INTMEM;
4896
4897         if (IS_VF(sc)) {
4898                 return PXP_VF_ADDR_USDM_QUEUES_START +
4899                         (sc->acquire_resp.resc.hw_qid[fp->index] *
4900                          sizeof(struct ustorm_queue_zone_data));
4901         } else if (!CHIP_IS_E1x(sc)) {
4902                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4903         } else {
4904                 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4905         }
4906
4907         return offset;
4908 }
4909
4910 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4911 {
4912         struct bnx2x_fastpath *fp = &sc->fp[idx];
4913         uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4914         unsigned long q_type = 0;
4915         int cos;
4916
4917         fp->sc = sc;
4918         fp->index = idx;
4919
4920         fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4921         fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4922
4923         if (CHIP_IS_E1x(sc))
4924                 fp->cl_id = SC_L_ID(sc) + idx;
4925         else
4926 /* want client ID same as IGU SB ID for non-E1 */
4927                 fp->cl_id = fp->igu_sb_id;
4928         fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4929
4930         /* setup sb indices */
4931         if (!CHIP_IS_E1x(sc)) {
4932                 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4933                 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4934         } else {
4935                 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4936                 fp->sb_running_index =
4937                     fp->status_block.e1x_sb->sb.running_index;
4938         }
4939
4940         /* init shortcut */
4941         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4942
4943         fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4944
4945         for (cos = 0; cos < sc->max_cos; cos++) {
4946                 cids[cos] = idx;
4947         }
4948         fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4949
4950         /* nothing more for a VF to do */
4951         if (IS_VF(sc)) {
4952                 return;
4953         }
4954
4955         bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4956                     fp->fw_sb_id, fp->igu_sb_id);
4957
4958         bnx2x_update_fp_sb_idx(fp);
4959
4960         /* Configure Queue State object */
4961         bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4962         bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4963
4964         ecore_init_queue_obj(sc,
4965                              &sc->sp_objs[idx].q_obj,
4966                              fp->cl_id,
4967                              cids,
4968                              sc->max_cos,
4969                              SC_FUNC(sc),
4970                              BNX2X_SP(sc, q_rdata),
4971                              (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata),
4972                              q_type);
4973
4974         /* configure classification DBs */
4975         ecore_init_mac_obj(sc,
4976                            &sc->sp_objs[idx].mac_obj,
4977                            fp->cl_id,
4978                            idx,
4979                            SC_FUNC(sc),
4980                            BNX2X_SP(sc, mac_rdata),
4981                            (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4982                            ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4983                            ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4984 }
4985
4986 static void
4987 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4988                    uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4989 {
4990         union ustorm_eth_rx_producers rx_prods;
4991         uint32_t i;
4992
4993         /* update producers */
4994         rx_prods.prod.bd_prod = rx_bd_prod;
4995         rx_prods.prod.cqe_prod = rx_cq_prod;
4996         rx_prods.prod.reserved = 0;
4997
4998         /*
4999          * Make sure that the BD and SGE data is updated before updating the
5000          * producers since FW might read the BD/SGE right after the producer
5001          * is updated.
5002          * This is only applicable for weak-ordered memory model archs such
5003          * as IA-64. The following barrier is also mandatory since FW will
5004          * assumes BDs must have buffers.
5005          */
5006         wmb();
5007
5008         for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
5009                 REG_WR(sc,
5010                        (fp->ustorm_rx_prods_offset + (i * 4)),
5011                        rx_prods.raw_data[i]);
5012         }
5013
5014         wmb();                  /* keep prod updates ordered */
5015 }
5016
5017 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
5018 {
5019         struct bnx2x_fastpath *fp;
5020         int i;
5021         struct bnx2x_rx_queue *rxq;
5022
5023         for (i = 0; i < sc->num_queues; i++) {
5024                 fp = &sc->fp[i];
5025                 rxq = sc->rx_queues[fp->index];
5026                 if (!rxq) {
5027                         PMD_RX_LOG(ERR, "RX queue is NULL");
5028                         return;
5029                 }
5030
5031                 rxq->rx_bd_head = 0;
5032                 rxq->rx_bd_tail = rxq->nb_rx_desc;
5033                 rxq->rx_cq_head = 0;
5034                 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
5035                 *fp->rx_cq_cons_sb = 0;
5036
5037                 /*
5038                  * Activate the BD ring...
5039                  * Warning, this will generate an interrupt (to the TSTORM)
5040                  * so this can only be done after the chip is initialized
5041                  */
5042                 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5043
5044                 if (i != 0) {
5045                         continue;
5046                 }
5047         }
5048 }
5049
5050 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5051 {
5052         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5053
5054         fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5055         fp->tx_db.data.zero_fill1 = 0;
5056         fp->tx_db.data.prod = 0;
5057
5058         if (!txq) {
5059                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5060                 return;
5061         }
5062
5063         txq->tx_pkt_tail = 0;
5064         txq->tx_pkt_head = 0;
5065         txq->tx_bd_tail = 0;
5066         txq->tx_bd_head = 0;
5067 }
5068
5069 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5070 {
5071         int i;
5072
5073         for (i = 0; i < sc->num_queues; i++) {
5074                 bnx2x_init_tx_ring_one(&sc->fp[i]);
5075         }
5076 }
5077
5078 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5079 {
5080         struct host_sp_status_block *def_sb = sc->def_sb;
5081         rte_iova_t mapping = sc->def_sb_dma.paddr;
5082         int igu_sp_sb_index;
5083         int igu_seg_id;
5084         int port = SC_PORT(sc);
5085         int func = SC_FUNC(sc);
5086         int reg_offset, reg_offset_en5;
5087         uint64_t section;
5088         int index, sindex;
5089         struct hc_sp_status_block_data sp_sb_data;
5090
5091         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5092
5093         if (CHIP_INT_MODE_IS_BC(sc)) {
5094                 igu_sp_sb_index = DEF_SB_IGU_ID;
5095                 igu_seg_id = HC_SEG_ACCESS_DEF;
5096         } else {
5097                 igu_sp_sb_index = sc->igu_dsb_id;
5098                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5099         }
5100
5101         /* attentions */
5102         section = ((uint64_t) mapping +
5103                    offsetof(struct host_sp_status_block, atten_status_block));
5104         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5105         sc->attn_state = 0;
5106
5107         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5108             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5109
5110         reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5111             MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5112
5113         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5114 /* take care of sig[0]..sig[4] */
5115                 for (sindex = 0; sindex < 4; sindex++) {
5116                         sc->attn_group[index].sig[sindex] =
5117                             REG_RD(sc,
5118                                    (reg_offset + (sindex * 0x4) +
5119                                     (0x10 * index)));
5120                 }
5121
5122                 if (!CHIP_IS_E1x(sc)) {
5123                         /*
5124                          * enable5 is separate from the rest of the registers,
5125                          * and the address skip is 4 and not 16 between the
5126                          * different groups
5127                          */
5128                         sc->attn_group[index].sig[4] =
5129                             REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5130                 } else {
5131                         sc->attn_group[index].sig[4] = 0;
5132                 }
5133         }
5134
5135         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5136                 reg_offset =
5137                     port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5138                 REG_WR(sc, reg_offset, U64_LO(section));
5139                 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5140         } else if (!CHIP_IS_E1x(sc)) {
5141                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5142                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5143         }
5144
5145         section = ((uint64_t) mapping +
5146                    offsetof(struct host_sp_status_block, sp_sb));
5147
5148         bnx2x_zero_sp_sb(sc);
5149
5150         /* PCI guarantees endianity of regpair */
5151         sp_sb_data.state = SB_ENABLED;
5152         sp_sb_data.host_sb_addr.lo = U64_LO(section);
5153         sp_sb_data.host_sb_addr.hi = U64_HI(section);
5154         sp_sb_data.igu_sb_id = igu_sp_sb_index;
5155         sp_sb_data.igu_seg_id = igu_seg_id;
5156         sp_sb_data.p_func.pf_id = func;
5157         sp_sb_data.p_func.vnic_id = SC_VN(sc);
5158         sp_sb_data.p_func.vf_id = 0xff;
5159
5160         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5161
5162         bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5163 }
5164
5165 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5166 {
5167         atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5168         sc->spq_prod_idx = 0;
5169         sc->dsb_sp_prod =
5170             &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5171         sc->spq_prod_bd = sc->spq;
5172         sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5173 }
5174
5175 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5176 {
5177         union event_ring_elem *elem;
5178         int i;
5179
5180         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5181                 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5182
5183                 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5184                                                          BNX2X_PAGE_SIZE *
5185                                                          (i % NUM_EQ_PAGES)));
5186                 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5187                                                          BNX2X_PAGE_SIZE *
5188                                                          (i % NUM_EQ_PAGES)));
5189         }
5190
5191         sc->eq_cons = 0;
5192         sc->eq_prod = NUM_EQ_DESC;
5193         sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5194
5195         atomic_store_rel_long(&sc->eq_spq_left,
5196                               (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5197                                    NUM_EQ_DESC) - 1));
5198 }
5199
5200 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5201 {
5202         int i;
5203
5204         if (IS_MF_SI(sc)) {
5205 /*
5206  * In switch independent mode, the TSTORM needs to accept
5207  * packets that failed classification, since approximate match
5208  * mac addresses aren't written to NIG LLH.
5209  */
5210                 REG_WR8(sc,
5211                         (BAR_TSTRORM_INTMEM +
5212                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5213         } else
5214                 REG_WR8(sc,
5215                         (BAR_TSTRORM_INTMEM +
5216                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5217
5218         /*
5219          * Zero this manually as its initialization is currently missing
5220          * in the initTool.
5221          */
5222         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5223                 REG_WR(sc,
5224                        (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5225                        0);
5226         }
5227
5228         if (!CHIP_IS_E1x(sc)) {
5229                 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5230                         CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5231                         HC_IGU_NBC_MODE);
5232         }
5233 }
5234
5235 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5236 {
5237         switch (load_code) {
5238         case FW_MSG_CODE_DRV_LOAD_COMMON:
5239         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5240                 bnx2x_init_internal_common(sc);
5241                 /* no break */
5242
5243         case FW_MSG_CODE_DRV_LOAD_PORT:
5244                 /* nothing to do */
5245                 /* no break */
5246
5247         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5248                 /* internal memory per function is initialized inside bnx2x_pf_init */
5249                 break;
5250
5251         default:
5252                 PMD_DRV_LOG(NOTICE, sc, "Unknown load_code (0x%x) from MCP",
5253                             load_code);
5254                 break;
5255         }
5256 }
5257
5258 static void
5259 storm_memset_func_cfg(struct bnx2x_softc *sc,
5260                       struct tstorm_eth_function_common_config *tcfg,
5261                       uint16_t abs_fid)
5262 {
5263         uint32_t addr;
5264         size_t size;
5265
5266         addr = (BAR_TSTRORM_INTMEM +
5267                 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5268         size = sizeof(struct tstorm_eth_function_common_config);
5269         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5270 }
5271
5272 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5273 {
5274         struct tstorm_eth_function_common_config tcfg = { 0 };
5275
5276         if (CHIP_IS_E1x(sc)) {
5277                 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5278         }
5279
5280         /* Enable the function in the FW */
5281         storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5282         storm_memset_func_en(sc, p->func_id, 1);
5283
5284         /* spq */
5285         if (p->func_flgs & FUNC_FLG_SPQ) {
5286                 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5287                 REG_WR(sc,
5288                        (XSEM_REG_FAST_MEMORY +
5289                         XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5290         }
5291 }
5292
5293 /*
5294  * Calculates the sum of vn_min_rates.
5295  * It's needed for further normalizing of the min_rates.
5296  * Returns:
5297  *   sum of vn_min_rates.
5298  *     or
5299  *   0 - if all the min_rates are 0.
5300  * In the later case fainess algorithm should be deactivated.
5301  * If all min rates are not zero then those that are zeroes will be set to 1.
5302  */
5303 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5304 {
5305         uint32_t vn_cfg;
5306         uint32_t vn_min_rate;
5307         int all_zero = 1;
5308         int vn;
5309
5310         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5311                 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5312                 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5313                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5314
5315                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5316                         /* skip hidden VNs */
5317                         vn_min_rate = 0;
5318                 } else if (!vn_min_rate) {
5319                         /* If min rate is zero - set it to 100 */
5320                         vn_min_rate = DEF_MIN_RATE;
5321                 } else {
5322                         all_zero = 0;
5323                 }
5324
5325                 input->vnic_min_rate[vn] = vn_min_rate;
5326         }
5327
5328         /* if ETS or all min rates are zeros - disable fairness */
5329         if (all_zero) {
5330                 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5331         } else {
5332                 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5333         }
5334 }
5335
5336 static uint16_t
5337 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5338 {
5339         uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5340                             FUNC_MF_CFG_MAX_BW_SHIFT);
5341
5342         if (!max_cfg) {
5343                 PMD_DRV_LOG(DEBUG, sc,
5344                             "Max BW configured to 0 - using 100 instead");
5345                 max_cfg = 100;
5346         }
5347
5348         return max_cfg;
5349 }
5350
5351 static void
5352 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5353 {
5354         uint16_t vn_max_rate;
5355         uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5356         uint32_t max_cfg;
5357
5358         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5359                 vn_max_rate = 0;
5360         } else {
5361                 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5362
5363                 if (IS_MF_SI(sc)) {
5364                         /* max_cfg in percents of linkspeed */
5365                         vn_max_rate =
5366                             ((sc->link_vars.line_speed * max_cfg) / 100);
5367                 } else {        /* SD modes */
5368                         /* max_cfg is absolute in 100Mb units */
5369                         vn_max_rate = (max_cfg * 100);
5370                 }
5371         }
5372
5373         input->vnic_max_rate[vn] = vn_max_rate;
5374 }
5375
5376 static void
5377 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5378 {
5379         struct cmng_init_input input;
5380         int vn;
5381
5382         memset(&input, 0, sizeof(struct cmng_init_input));
5383
5384         input.port_rate = sc->link_vars.line_speed;
5385
5386         if (cmng_type == CMNG_FNS_MINMAX) {
5387 /* read mf conf from shmem */
5388                 if (read_cfg) {
5389                         bnx2x_read_mf_cfg(sc);
5390                 }
5391
5392 /* get VN min rate and enable fairness if not 0 */
5393                 bnx2x_calc_vn_min(sc, &input);
5394
5395 /* get VN max rate */
5396                 if (sc->port.pmf) {
5397                         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5398                                 bnx2x_calc_vn_max(sc, vn, &input);
5399                         }
5400                 }
5401
5402 /* always enable rate shaping and fairness */
5403                 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5404
5405                 ecore_init_cmng(&input, &sc->cmng);
5406                 return;
5407         }
5408 }
5409
5410 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5411 {
5412         if (CHIP_REV_IS_SLOW(sc)) {
5413                 return CMNG_FNS_NONE;
5414         }
5415
5416         if (IS_MF(sc)) {
5417                 return CMNG_FNS_MINMAX;
5418         }
5419
5420         return CMNG_FNS_NONE;
5421 }
5422
5423 static void
5424 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5425 {
5426         int vn;
5427         int func;
5428         uint32_t addr;
5429         size_t size;
5430
5431         addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5432         size = sizeof(struct cmng_struct_per_port);
5433         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5434
5435         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5436                 func = func_by_vn(sc, vn);
5437
5438                 addr = (BAR_XSTRORM_INTMEM +
5439                         XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5440                 size = sizeof(struct rate_shaping_vars_per_vn);
5441                 ecore_storm_memset_struct(sc, addr, size,
5442                                           (uint32_t *) & cmng->
5443                                           vnic.vnic_max_rate[vn]);
5444
5445                 addr = (BAR_XSTRORM_INTMEM +
5446                         XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5447                 size = sizeof(struct fairness_vars_per_vn);
5448                 ecore_storm_memset_struct(sc, addr, size,
5449                                           (uint32_t *) & cmng->
5450                                           vnic.vnic_min_rate[vn]);
5451         }
5452 }
5453
5454 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5455 {
5456         struct bnx2x_func_init_params func_init;
5457         struct event_ring_data eq_data;
5458         uint16_t flags;
5459
5460         memset(&eq_data, 0, sizeof(struct event_ring_data));
5461         memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5462
5463         if (!CHIP_IS_E1x(sc)) {
5464 /* reset IGU PF statistics: MSIX + ATTN */
5465 /* PF */
5466                 REG_WR(sc,
5467                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5468                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5469                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5470                          4)), 0);
5471 /* ATTN */
5472                 REG_WR(sc,
5473                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5474                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5475                         (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5476                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5477                          4)), 0);
5478         }
5479
5480         /* function setup flags */
5481         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5482
5483         func_init.func_flgs = flags;
5484         func_init.pf_id = SC_FUNC(sc);
5485         func_init.func_id = SC_FUNC(sc);
5486         func_init.spq_map = sc->spq_dma.paddr;
5487         func_init.spq_prod = sc->spq_prod_idx;
5488
5489         bnx2x_func_init(sc, &func_init);
5490
5491         memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5492
5493         /*
5494          * Congestion management values depend on the link rate.
5495          * There is no active link so initial link rate is set to 10Gbps.
5496          * When the link comes up the congestion management values are
5497          * re-calculated according to the actual link rate.
5498          */
5499         sc->link_vars.line_speed = SPEED_10000;
5500         bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5501
5502         /* Only the PMF sets the HW */
5503         if (sc->port.pmf) {
5504                 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5505         }
5506
5507         /* init Event Queue - PCI bus guarantees correct endainity */
5508         eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5509         eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5510         eq_data.producer = sc->eq_prod;
5511         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5512         eq_data.sb_id = DEF_SB_ID;
5513         storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5514 }
5515
5516 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5517 {
5518         int port = SC_PORT(sc);
5519         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5520         uint32_t val = REG_RD(sc, addr);
5521         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5522             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5523         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5524         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5525
5526         if (msix) {
5527                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5528                          HC_CONFIG_0_REG_INT_LINE_EN_0);
5529                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5530                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5531                 if (single_msix) {
5532                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5533                 }
5534         } else if (msi) {
5535                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5536                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5537                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5538                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5539         } else {
5540                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5541                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5542                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
5543                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5544
5545                 REG_WR(sc, addr, val);
5546
5547                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5548         }
5549
5550         REG_WR(sc, addr, val);
5551
5552         /* ensure that HC_CONFIG is written before leading/trailing edge config */
5553         mb();
5554
5555         /* init leading/trailing edge */
5556         if (IS_MF(sc)) {
5557                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5558                 if (sc->port.pmf) {
5559                         /* enable nig and gpio3 attention */
5560                         val |= 0x1100;
5561                 }
5562         } else {
5563                 val = 0xffff;
5564         }
5565
5566         REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5567         REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5568
5569         /* make sure that interrupts are indeed enabled from here on */
5570         mb();
5571 }
5572
5573 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5574 {
5575         uint32_t val;
5576         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5577             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5578         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5579         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5580
5581         val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5582
5583         if (msix) {
5584                 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5585                 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5586                 if (single_msix) {
5587                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
5588                 }
5589         } else if (msi) {
5590                 val &= ~IGU_PF_CONF_INT_LINE_EN;
5591                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5592                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5593         } else {
5594                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5595                 val |= (IGU_PF_CONF_INT_LINE_EN |
5596                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5597         }
5598
5599         /* clean previous status - need to configure igu prior to ack */
5600         if ((!msix) || single_msix) {
5601                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5602                 bnx2x_ack_int(sc);
5603         }
5604
5605         val |= IGU_PF_CONF_FUNC_EN;
5606
5607         PMD_DRV_LOG(DEBUG, sc, "write 0x%x to IGU mode %s",
5608                     val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5609
5610         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5611
5612         mb();
5613
5614         /* init leading/trailing edge */
5615         if (IS_MF(sc)) {
5616                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5617                 if (sc->port.pmf) {
5618                         /* enable nig and gpio3 attention */
5619                         val |= 0x1100;
5620                 }
5621         } else {
5622                 val = 0xffff;
5623         }
5624
5625         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5626         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5627
5628         /* make sure that interrupts are indeed enabled from here on */
5629         mb();
5630 }
5631
5632 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5633 {
5634         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5635                 bnx2x_hc_int_enable(sc);
5636         } else {
5637                 bnx2x_igu_int_enable(sc);
5638         }
5639 }
5640
5641 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5642 {
5643         int port = SC_PORT(sc);
5644         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5645         uint32_t val = REG_RD(sc, addr);
5646
5647         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5648                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5649                  HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5650         /* flush all outstanding writes */
5651         mb();
5652
5653         REG_WR(sc, addr, val);
5654         if (REG_RD(sc, addr) != val) {
5655                 PMD_DRV_LOG(ERR, sc, "proper val not read from HC IGU!");
5656         }
5657 }
5658
5659 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5660 {
5661         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5662
5663         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5664                  IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5665
5666         PMD_DRV_LOG(DEBUG, sc, "write %x to IGU", val);
5667
5668         /* flush all outstanding writes */
5669         mb();
5670
5671         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5672         if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5673                 PMD_DRV_LOG(ERR, sc, "proper val not read from IGU!");
5674         }
5675 }
5676
5677 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5678 {
5679         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5680                 bnx2x_hc_int_disable(sc);
5681         } else {
5682                 bnx2x_igu_int_disable(sc);
5683         }
5684 }
5685
5686 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5687 {
5688         int i;
5689
5690         PMD_INIT_FUNC_TRACE(sc);
5691
5692         for (i = 0; i < sc->num_queues; i++) {
5693                 bnx2x_init_eth_fp(sc, i);
5694         }
5695
5696         rmb();                  /* ensure status block indices were read */
5697
5698         bnx2x_init_rx_rings(sc);
5699         bnx2x_init_tx_rings(sc);
5700
5701         if (IS_VF(sc)) {
5702                 bnx2x_memset_stats(sc);
5703                 return;
5704         }
5705
5706         /* initialize MOD_ABS interrupts */
5707         elink_init_mod_abs_int(sc, &sc->link_vars,
5708                                sc->devinfo.chip_id,
5709                                sc->devinfo.shmem_base,
5710                                sc->devinfo.shmem2_base, SC_PORT(sc));
5711
5712         bnx2x_init_def_sb(sc);
5713         bnx2x_update_dsb_idx(sc);
5714         bnx2x_init_sp_ring(sc);
5715         bnx2x_init_eq_ring(sc);
5716         bnx2x_init_internal(sc, load_code);
5717         bnx2x_pf_init(sc);
5718         bnx2x_stats_init(sc);
5719
5720         /* flush all before enabling interrupts */
5721         mb();
5722
5723         bnx2x_int_enable(sc);
5724
5725         /* check for SPIO5 */
5726         bnx2x_attn_int_deasserted0(sc,
5727                                  REG_RD(sc,
5728                                         (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5729                                          SC_PORT(sc) * 4)) &
5730                                  AEU_INPUTS_ATTN_BITS_SPIO5);
5731 }
5732
5733 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5734 {
5735         /* mcast rules must be added to tx if tx switching is enabled */
5736         ecore_obj_type o_type;
5737         if (sc->flags & BNX2X_TX_SWITCHING)
5738                 o_type = ECORE_OBJ_TYPE_RX_TX;
5739         else
5740                 o_type = ECORE_OBJ_TYPE_RX;
5741
5742         /* RX_MODE controlling object */
5743         ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5744
5745         /* multicast configuration controlling object */
5746         ecore_init_mcast_obj(sc,
5747                              &sc->mcast_obj,
5748                              sc->fp[0].cl_id,
5749                              sc->fp[0].index,
5750                              SC_FUNC(sc),
5751                              SC_FUNC(sc),
5752                              BNX2X_SP(sc, mcast_rdata),
5753                              (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5754                              ECORE_FILTER_MCAST_PENDING,
5755                              &sc->sp_state, o_type);
5756
5757         /* Setup CAM credit pools */
5758         ecore_init_mac_credit_pool(sc,
5759                                    &sc->macs_pool,
5760                                    SC_FUNC(sc),
5761                                    CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5762                                    VNICS_PER_PATH(sc));
5763
5764         ecore_init_vlan_credit_pool(sc,
5765                                     &sc->vlans_pool,
5766                                     SC_ABS_FUNC(sc) >> 1,
5767                                     CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5768                                     VNICS_PER_PATH(sc));
5769
5770         /* RSS configuration object */
5771         ecore_init_rss_config_obj(&sc->rss_conf_obj,
5772                                   sc->fp[0].cl_id,
5773                                   sc->fp[0].index,
5774                                   SC_FUNC(sc),
5775                                   SC_FUNC(sc),
5776                                   BNX2X_SP(sc, rss_rdata),
5777                                   (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5778                                   ECORE_FILTER_RSS_CONF_PENDING,
5779                                   &sc->sp_state, ECORE_OBJ_TYPE_RX);
5780 }
5781
5782 /*
5783  * Initialize the function. This must be called before sending CLIENT_SETUP
5784  * for the first client.
5785  */
5786 static int bnx2x_func_start(struct bnx2x_softc *sc)
5787 {
5788         struct ecore_func_state_params func_params = { NULL };
5789         struct ecore_func_start_params *start_params =
5790             &func_params.params.start;
5791
5792         /* Prepare parameters for function state transitions */
5793         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5794
5795         func_params.f_obj = &sc->func_obj;
5796         func_params.cmd = ECORE_F_CMD_START;
5797
5798         /* Function parameters */
5799         start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5800         start_params->sd_vlan_tag = OVLAN(sc);
5801
5802         if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5803                 start_params->network_cos_mode = STATIC_COS;
5804         } else {                /* CHIP_IS_E1X */
5805                 start_params->network_cos_mode = FW_WRR;
5806         }
5807
5808         start_params->gre_tunnel_mode = 0;
5809         start_params->gre_tunnel_rss = 0;
5810
5811         return ecore_func_state_change(sc, &func_params);
5812 }
5813
5814 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5815 {
5816         uint16_t pmcsr;
5817
5818         /* If there is no power capability, silently succeed */
5819         if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5820                 PMD_DRV_LOG(INFO, sc, "No power capability");
5821                 return 0;
5822         }
5823
5824         pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5825                  2);
5826
5827         switch (state) {
5828         case PCI_PM_D0:
5829                 pci_write_word(sc,
5830                                (sc->devinfo.pcie_pm_cap_reg +
5831                                 PCIR_POWER_STATUS),
5832                                ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5833
5834                 if (pmcsr & PCIM_PSTAT_DMASK) {
5835                         /* delay required during transition out of D3hot */
5836                         DELAY(20000);
5837                 }
5838
5839                 break;
5840
5841         case PCI_PM_D3hot:
5842                 /* don't shut down the power for emulation and FPGA */
5843                 if (CHIP_REV_IS_SLOW(sc)) {
5844                         return 0;
5845                 }
5846
5847                 pmcsr &= ~PCIM_PSTAT_DMASK;
5848                 pmcsr |= PCIM_PSTAT_D3;
5849
5850                 if (sc->wol) {
5851                         pmcsr |= PCIM_PSTAT_PMEENABLE;
5852                 }
5853
5854                 pci_write_long(sc,
5855                                (sc->devinfo.pcie_pm_cap_reg +
5856                                 PCIR_POWER_STATUS), pmcsr);
5857
5858                 /*
5859                  * No more memory access after this point until device is brought back
5860                  * to D0 state.
5861                  */
5862                 break;
5863
5864         default:
5865                 PMD_DRV_LOG(NOTICE, sc, "Can't support PCI power state = %d",
5866                             state);
5867                 return -1;
5868         }
5869
5870         return 0;
5871 }
5872
5873 /* return true if succeeded to acquire the lock */
5874 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5875 {
5876         uint32_t lock_status;
5877         uint32_t resource_bit = (1 << resource);
5878         int func = SC_FUNC(sc);
5879         uint32_t hw_lock_control_reg;
5880
5881         /* Validating that the resource is within range */
5882         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5883                 PMD_DRV_LOG(INFO, sc,
5884                             "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5885                             resource, HW_LOCK_MAX_RESOURCE_VALUE);
5886                 return FALSE;
5887         }
5888
5889         if (func <= 5) {
5890                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5891         } else {
5892                 hw_lock_control_reg =
5893                     (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5894         }
5895
5896         /* try to acquire the lock */
5897         REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5898         lock_status = REG_RD(sc, hw_lock_control_reg);
5899         if (lock_status & resource_bit) {
5900                 return TRUE;
5901         }
5902
5903         PMD_DRV_LOG(NOTICE, sc, "Failed to get a resource lock 0x%x", resource);
5904
5905         return FALSE;
5906 }
5907
5908 /*
5909  * Get the recovery leader resource id according to the engine this function
5910  * belongs to. Currently only only 2 engines is supported.
5911  */
5912 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5913 {
5914         if (SC_PATH(sc)) {
5915                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5916         } else {
5917                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5918         }
5919 }
5920
5921 /* try to acquire a leader lock for current engine */
5922 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5923 {
5924         return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5925 }
5926
5927 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5928 {
5929         return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5930 }
5931
5932 /* close gates #2, #3 and #4 */
5933 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5934 {
5935         uint32_t val;
5936
5937         /* gates #2 and #4a are closed/opened */
5938         /* #4 */
5939         REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5940         /* #2 */
5941         REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5942
5943         /* #3 */
5944         if (CHIP_IS_E1x(sc)) {
5945 /* prevent interrupts from HC on both ports */
5946                 val = REG_RD(sc, HC_REG_CONFIG_1);
5947                 if (close)
5948                         REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5949                                                      HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5950                 else
5951                         REG_WR(sc, HC_REG_CONFIG_1,
5952                                (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5953
5954                 val = REG_RD(sc, HC_REG_CONFIG_0);
5955                 if (close)
5956                         REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5957                                                      HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5958                 else
5959                         REG_WR(sc, HC_REG_CONFIG_0,
5960                                (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5961
5962         } else {
5963 /* Prevent incoming interrupts in IGU */
5964                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5965
5966                 if (close)
5967                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5968                                (val & ~(uint32_t)
5969                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5970                 else
5971                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5972                                (val |
5973                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5974         }
5975
5976         wmb();
5977 }
5978
5979 /* poll for pending writes bit, it should get cleared in no more than 1s */
5980 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5981 {
5982         uint32_t cnt = 1000;
5983         uint32_t pend_bits = 0;
5984
5985         do {
5986                 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5987
5988                 if (pend_bits == 0) {
5989                         break;
5990                 }
5991
5992                 DELAY(1000);
5993         } while (cnt-- > 0);
5994
5995         if (cnt <= 0) {
5996                 PMD_DRV_LOG(NOTICE, sc, "Still pending IGU requests bits=0x%08x!",
5997                             pend_bits);
5998                 return -1;
5999         }
6000
6001         return 0;
6002 }
6003
6004 #define SHARED_MF_CLP_MAGIC  0x80000000 /* 'magic' bit */
6005
6006 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6007 {
6008         /* Do some magic... */
6009         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6010         *magic_val = val & SHARED_MF_CLP_MAGIC;
6011         MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
6012 }
6013
6014 /* restore the value of the 'magic' bit */
6015 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
6016 {
6017         /* Restore the 'magic' bit value... */
6018         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6019         MFCFG_WR(sc, shared_mf_config.clp_mb,
6020                  (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
6021 }
6022
6023 /* prepare for MCP reset, takes care of CLP configurations */
6024 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6025 {
6026         uint32_t shmem;
6027         uint32_t validity_offset;
6028
6029         /* set `magic' bit in order to save MF config */
6030         bnx2x_clp_reset_prep(sc, magic_val);
6031
6032         /* get shmem offset */
6033         shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6034         validity_offset =
6035             offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
6036
6037         /* Clear validity map flags */
6038         if (shmem > 0) {
6039                 REG_WR(sc, shmem + validity_offset, 0);
6040         }
6041 }
6042
6043 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
6044 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
6045
6046 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6047 {
6048         /* special handling for emulation and FPGA (10 times longer) */
6049         if (CHIP_REV_IS_SLOW(sc)) {
6050                 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6051         } else {
6052                 DELAY((MCP_ONE_TIMEOUT) * 1000);
6053         }
6054 }
6055
6056 /* initialize shmem_base and waits for validity signature to appear */
6057 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6058 {
6059         int cnt = 0;
6060         uint32_t val = 0;
6061
6062         do {
6063                 sc->devinfo.shmem_base =
6064                     sc->link_params.shmem_base =
6065                     REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6066
6067                 if (sc->devinfo.shmem_base) {
6068                         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6069                         if (val & SHR_MEM_VALIDITY_MB)
6070                                 return 0;
6071                 }
6072
6073                 bnx2x_mcp_wait_one(sc);
6074
6075         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6076
6077         PMD_DRV_LOG(NOTICE, sc, "BAD MCP validity signature");
6078
6079         return -1;
6080 }
6081
6082 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6083 {
6084         int rc = bnx2x_init_shmem(sc);
6085
6086         /* Restore the `magic' bit value */
6087         bnx2x_clp_reset_done(sc, magic_val);
6088
6089         return rc;
6090 }
6091
6092 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6093 {
6094         REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6095         REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6096         wmb();
6097 }
6098
6099 /*
6100  * Reset the whole chip except for:
6101  *      - PCIE core
6102  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6103  *      - IGU
6104  *      - MISC (including AEU)
6105  *      - GRC
6106  *      - RBCN, RBCP
6107  */
6108 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6109 {
6110         uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6111         uint32_t global_bits2, stay_reset2;
6112
6113         /*
6114          * Bits that have to be set in reset_mask2 if we want to reset 'global'
6115          * (per chip) blocks.
6116          */
6117         global_bits2 =
6118             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6119             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6120
6121         /*
6122          * Don't reset the following blocks.
6123          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6124          *            reset, as in 4 port device they might still be owned
6125          *            by the MCP (there is only one leader per path).
6126          */
6127         not_reset_mask1 =
6128             MISC_REGISTERS_RESET_REG_1_RST_HC |
6129             MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6130             MISC_REGISTERS_RESET_REG_1_RST_PXP;
6131
6132         not_reset_mask2 =
6133             MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6134             MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6135             MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6136             MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6137             MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6138             MISC_REGISTERS_RESET_REG_2_RST_GRC |
6139             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6140             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6141             MISC_REGISTERS_RESET_REG_2_RST_ATC |
6142             MISC_REGISTERS_RESET_REG_2_PGLC |
6143             MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6144             MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6145             MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6146             MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6147             MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6148
6149         /*
6150          * Keep the following blocks in reset:
6151          *  - all xxMACs are handled by the elink code.
6152          */
6153         stay_reset2 =
6154             MISC_REGISTERS_RESET_REG_2_XMAC |
6155             MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6156
6157         /* Full reset masks according to the chip */
6158         reset_mask1 = 0xffffffff;
6159
6160         if (CHIP_IS_E1H(sc))
6161                 reset_mask2 = 0x1ffff;
6162         else if (CHIP_IS_E2(sc))
6163                 reset_mask2 = 0xfffff;
6164         else                    /* CHIP_IS_E3 */
6165                 reset_mask2 = 0x3ffffff;
6166
6167         /* Don't reset global blocks unless we need to */
6168         if (!global)
6169                 reset_mask2 &= ~global_bits2;
6170
6171         /*
6172          * In case of attention in the QM, we need to reset PXP
6173          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6174          * because otherwise QM reset would release 'close the gates' shortly
6175          * before resetting the PXP, then the PSWRQ would send a write
6176          * request to PGLUE. Then when PXP is reset, PGLUE would try to
6177          * read the payload data from PSWWR, but PSWWR would not
6178          * respond. The write queue in PGLUE would stuck, dmae commands
6179          * would not return. Therefore it's important to reset the second
6180          * reset register (containing the
6181          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6182          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6183          * bit).
6184          */
6185         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6186                reset_mask2 & (~not_reset_mask2));
6187
6188         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6189                reset_mask1 & (~not_reset_mask1));
6190
6191         mb();
6192         wmb();
6193
6194         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6195                reset_mask2 & (~stay_reset2));
6196
6197         mb();
6198         wmb();
6199
6200         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6201         wmb();
6202 }
6203
6204 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6205 {
6206         int cnt = 1000;
6207         uint32_t val = 0;
6208         uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6209         uint32_t tags_63_32 = 0;
6210
6211         /* Empty the Tetris buffer, wait for 1s */
6212         do {
6213                 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6214                 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6215                 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6216                 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6217                 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6218                 if (CHIP_IS_E3(sc)) {
6219                         tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6220                 }
6221
6222                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6223                     ((port_is_idle_0 & 0x1) == 0x1) &&
6224                     ((port_is_idle_1 & 0x1) == 0x1) &&
6225                     (pgl_exp_rom2 == 0xffffffff) &&
6226                     (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6227                         break;
6228                 DELAY(1000);
6229         } while (cnt-- > 0);
6230
6231         if (cnt <= 0) {
6232                 PMD_DRV_LOG(NOTICE, sc,
6233                             "ERROR: Tetris buffer didn't get empty or there "
6234                             "are still outstanding read requests after 1s! "
6235                             "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6236                             "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6237                             sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6238                             pgl_exp_rom2);
6239                 return -1;
6240         }
6241
6242         mb();
6243
6244         /* Close gates #2, #3 and #4 */
6245         bnx2x_set_234_gates(sc, TRUE);
6246
6247         /* Poll for IGU VQs for 57712 and newer chips */
6248         if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6249                 return -1;
6250         }
6251
6252         /* clear "unprepared" bit */
6253         REG_WR(sc, MISC_REG_UNPREPARED, 0);
6254         mb();
6255
6256         /* Make sure all is written to the chip before the reset */
6257         wmb();
6258
6259         /*
6260          * Wait for 1ms to empty GLUE and PCI-E core queues,
6261          * PSWHST, GRC and PSWRD Tetris buffer.
6262          */
6263         DELAY(1000);
6264
6265         /* Prepare to chip reset: */
6266         /* MCP */
6267         if (global) {
6268                 bnx2x_reset_mcp_prep(sc, &val);
6269         }
6270
6271         /* PXP */
6272         bnx2x_pxp_prep(sc);
6273         mb();
6274
6275         /* reset the chip */
6276         bnx2x_process_kill_chip_reset(sc, global);
6277         mb();
6278
6279         /* Recover after reset: */
6280         /* MCP */
6281         if (global && bnx2x_reset_mcp_comp(sc, val)) {
6282                 return -1;
6283         }
6284
6285         /* Open the gates #2, #3 and #4 */
6286         bnx2x_set_234_gates(sc, FALSE);
6287
6288         return 0;
6289 }
6290
6291 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6292 {
6293         int rc = 0;
6294         uint8_t global = bnx2x_reset_is_global(sc);
6295         uint32_t load_code;
6296
6297         /*
6298          * If not going to reset MCP, load "fake" driver to reset HW while
6299          * driver is owner of the HW.
6300          */
6301         if (!global && !BNX2X_NOMCP(sc)) {
6302                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6303                                            DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6304                 if (!load_code) {
6305                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6306                         rc = -1;
6307                         goto exit_leader_reset;
6308                 }
6309
6310                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6311                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6312                         PMD_DRV_LOG(NOTICE, sc,
6313                                     "MCP unexpected response, aborting");
6314                         rc = -1;
6315                         goto exit_leader_reset2;
6316                 }
6317
6318                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6319                 if (!load_code) {
6320                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6321                         rc = -1;
6322                         goto exit_leader_reset2;
6323                 }
6324         }
6325
6326         /* try to recover after the failure */
6327         if (bnx2x_process_kill(sc, global)) {
6328                 PMD_DRV_LOG(NOTICE, sc, "Something bad occurred on engine %d!",
6329                             SC_PATH(sc));
6330                 rc = -1;
6331                 goto exit_leader_reset2;
6332         }
6333
6334         /*
6335          * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6336          * state.
6337          */
6338         bnx2x_set_reset_done(sc);
6339         if (global) {
6340                 bnx2x_clear_reset_global(sc);
6341         }
6342
6343 exit_leader_reset2:
6344
6345         /* unload "fake driver" if it was loaded */
6346         if (!global &&!BNX2X_NOMCP(sc)) {
6347                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6348                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6349         }
6350
6351 exit_leader_reset:
6352
6353         sc->is_leader = 0;
6354         bnx2x_release_leader_lock(sc);
6355
6356         mb();
6357         return rc;
6358 }
6359
6360 /*
6361  * prepare INIT transition, parameters configured:
6362  *   - HC configuration
6363  *   - Queue's CDU context
6364  */
6365 static void
6366 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6367                    struct ecore_queue_init_params *init_params)
6368 {
6369         uint8_t cos;
6370         int cxt_index, cxt_offset;
6371
6372         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6373         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6374
6375         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6376         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6377
6378         /* HC rate */
6379         init_params->rx.hc_rate =
6380             sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6381         init_params->tx.hc_rate =
6382             sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6383
6384         /* FW SB ID */
6385         init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6386
6387         /* CQ index among the SB indices */
6388         init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6389         init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6390
6391         /* set maximum number of COSs supported by this queue */
6392         init_params->max_cos = sc->max_cos;
6393
6394         /* set the context pointers queue object */
6395         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6396                 cxt_index = fp->index / ILT_PAGE_CIDS;
6397                 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6398                 init_params->cxts[cos] =
6399                     &sc->context[cxt_index].vcxt[cxt_offset].eth;
6400         }
6401 }
6402
6403 /* set flags that are common for the Tx-only and not normal connections */
6404 static unsigned long
6405 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6406 {
6407         unsigned long flags = 0;
6408
6409         /* PF driver will always initialize the Queue to an ACTIVE state */
6410         bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6411
6412         /*
6413          * tx only connections collect statistics (on the same index as the
6414          * parent connection). The statistics are zeroed when the parent
6415          * connection is initialized.
6416          */
6417
6418         bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6419         if (zero_stats) {
6420                 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6421         }
6422
6423         /*
6424          * tx only connections can support tx-switching, though their
6425          * CoS-ness doesn't survive the loopback
6426          */
6427         if (sc->flags & BNX2X_TX_SWITCHING) {
6428                 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6429         }
6430
6431         bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6432
6433         return flags;
6434 }
6435
6436 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6437 {
6438         unsigned long flags = 0;
6439
6440         if (IS_MF_SD(sc)) {
6441                 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6442         }
6443
6444         if (leading) {
6445                 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6446                 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6447         }
6448
6449         bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6450
6451         /* merge with common flags */
6452         return flags | bnx2x_get_common_flags(sc, TRUE);
6453 }
6454
6455 static void
6456 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6457                       struct ecore_general_setup_params *gen_init, uint8_t cos)
6458 {
6459         gen_init->stat_id = bnx2x_stats_id(fp);
6460         gen_init->spcl_id = fp->cl_id;
6461         gen_init->mtu = sc->mtu;
6462         gen_init->cos = cos;
6463 }
6464
6465 static void
6466 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6467                  struct rxq_pause_params *pause,
6468                  struct ecore_rxq_setup_params *rxq_init)
6469 {
6470         struct bnx2x_rx_queue *rxq;
6471
6472         rxq = sc->rx_queues[fp->index];
6473         if (!rxq) {
6474                 PMD_RX_LOG(ERR, "RX queue is NULL");
6475                 return;
6476         }
6477         /* pause */
6478         pause->bd_th_lo = BD_TH_LO(sc);
6479         pause->bd_th_hi = BD_TH_HI(sc);
6480
6481         pause->rcq_th_lo = RCQ_TH_LO(sc);
6482         pause->rcq_th_hi = RCQ_TH_HI(sc);
6483
6484         /* validate rings have enough entries to cross high thresholds */
6485         if (sc->dropless_fc &&
6486             pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6487                 PMD_DRV_LOG(WARNING, sc, "rx bd ring threshold limit");
6488         }
6489
6490         if (sc->dropless_fc &&
6491             pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6492                 PMD_DRV_LOG(WARNING, sc, "rcq ring threshold limit");
6493         }
6494
6495         pause->pri_map = 1;
6496
6497         /* rxq setup */
6498         rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr;
6499         rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr;
6500         rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr +
6501                                               BNX2X_PAGE_SIZE);
6502
6503         /*
6504          * This should be a maximum number of data bytes that may be
6505          * placed on the BD (not including paddings).
6506          */
6507         rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6508
6509         rxq_init->cl_qzone_id = fp->cl_qzone_id;
6510         rxq_init->rss_engine_id = SC_FUNC(sc);
6511         rxq_init->mcast_engine_id = SC_FUNC(sc);
6512
6513         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6514         rxq_init->fw_sb_id = fp->fw_sb_id;
6515
6516         rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6517
6518         /*
6519          * configure silent vlan removal
6520          * if multi function mode is afex, then mask default vlan
6521          */
6522         if (IS_MF_AFEX(sc)) {
6523                 rxq_init->silent_removal_value =
6524                     sc->devinfo.mf_info.afex_def_vlan_tag;
6525                 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6526         }
6527 }
6528
6529 static void
6530 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6531                  struct ecore_txq_setup_params *txq_init, uint8_t cos)
6532 {
6533         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6534
6535         if (!txq) {
6536                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6537                 return;
6538         }
6539         txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr;
6540         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6541         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6542         txq_init->fw_sb_id = fp->fw_sb_id;
6543
6544         /*
6545          * set the TSS leading client id for TX classfication to the
6546          * leading RSS client id
6547          */
6548         txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6549 }
6550
6551 /*
6552  * This function performs 2 steps in a queue state machine:
6553  *   1) RESET->INIT
6554  *   2) INIT->SETUP
6555  */
6556 static int
6557 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6558 {
6559         struct ecore_queue_state_params q_params = { NULL };
6560         struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6561         int rc;
6562
6563         PMD_DRV_LOG(DEBUG, sc, "setting up queue %d", fp->index);
6564
6565         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6566
6567         q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6568
6569         /* we want to wait for completion in this context */
6570         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6571
6572         /* prepare the INIT parameters */
6573         bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6574
6575         /* Set the command */
6576         q_params.cmd = ECORE_Q_CMD_INIT;
6577
6578         /* Change the state to INIT */
6579         rc = ecore_queue_state_change(sc, &q_params);
6580         if (rc) {
6581                 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) INIT failed", fp->index);
6582                 return rc;
6583         }
6584
6585         PMD_DRV_LOG(DEBUG, sc, "init complete");
6586
6587         /* now move the Queue to the SETUP state */
6588         memset(setup_params, 0, sizeof(*setup_params));
6589
6590         /* set Queue flags */
6591         setup_params->flags = bnx2x_get_q_flags(sc, leading);
6592
6593         /* set general SETUP parameters */
6594         bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6595                               FIRST_TX_COS_INDEX);
6596
6597         bnx2x_pf_rx_q_prep(sc, fp,
6598                          &setup_params->pause_params,
6599                          &setup_params->rxq_params);
6600
6601         bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6602
6603         /* Set the command */
6604         q_params.cmd = ECORE_Q_CMD_SETUP;
6605
6606         /* change the state to SETUP */
6607         rc = ecore_queue_state_change(sc, &q_params);
6608         if (rc) {
6609                 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) SETUP failed", fp->index);
6610                 return rc;
6611         }
6612
6613         return rc;
6614 }
6615
6616 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6617 {
6618         if (IS_PF(sc))
6619                 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6620         else                    /* VF */
6621                 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6622 }
6623
6624 static int
6625 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6626                   uint8_t config_hash)
6627 {
6628         struct ecore_config_rss_params params = { NULL };
6629         uint32_t i;
6630
6631         /*
6632          * Although RSS is meaningless when there is a single HW queue we
6633          * still need it enabled in order to have HW Rx hash generated.
6634          */
6635
6636         params.rss_obj = rss_obj;
6637
6638         bnx2x_set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
6639
6640         bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, &params.rss_flags);
6641
6642         /* RSS configuration */
6643         bnx2x_set_bit(ECORE_RSS_IPV4, &params.rss_flags);
6644         bnx2x_set_bit(ECORE_RSS_IPV4_TCP, &params.rss_flags);
6645         bnx2x_set_bit(ECORE_RSS_IPV6, &params.rss_flags);
6646         bnx2x_set_bit(ECORE_RSS_IPV6_TCP, &params.rss_flags);
6647         if (rss_obj->udp_rss_v4) {
6648                 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, &params.rss_flags);
6649         }
6650         if (rss_obj->udp_rss_v6) {
6651                 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, &params.rss_flags);
6652         }
6653
6654         /* Hash bits */
6655         params.rss_result_mask = MULTI_MASK;
6656
6657         rte_memcpy(params.ind_table, rss_obj->ind_table,
6658                          sizeof(params.ind_table));
6659
6660         if (config_hash) {
6661 /* RSS keys */
6662                 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6663                         params.rss_key[i] = (uint32_t) rte_rand();
6664                 }
6665
6666                 bnx2x_set_bit(ECORE_RSS_SET_SRCH, &params.rss_flags);
6667         }
6668
6669         if (IS_PF(sc))
6670                 return ecore_config_rss(sc, &params);
6671         else
6672                 return bnx2x_vf_config_rss(sc, &params);
6673 }
6674
6675 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6676 {
6677         return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6678 }
6679
6680 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6681 {
6682         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6683         uint32_t i;
6684
6685         /*
6686          * Prepare the initial contents of the indirection table if
6687          * RSS is enabled
6688          */
6689         for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6690                 sc->rss_conf_obj.ind_table[i] =
6691                     (sc->fp->cl_id + (i % num_eth_queues));
6692         }
6693
6694         if (sc->udp_rss) {
6695                 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6696         }
6697
6698         /*
6699          * For 57711 SEARCHER configuration (rss_keys) is
6700          * per-port, so if explicit configuration is needed, do it only
6701          * for a PMF.
6702          *
6703          * For 57712 and newer it's a per-function configuration.
6704          */
6705         return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6706 }
6707
6708 static int
6709 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6710                 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6711                 unsigned long *ramrod_flags)
6712 {
6713         struct ecore_vlan_mac_ramrod_params ramrod_param;
6714         int rc;
6715
6716         memset(&ramrod_param, 0, sizeof(ramrod_param));
6717
6718         /* fill in general parameters */
6719         ramrod_param.vlan_mac_obj = obj;
6720         ramrod_param.ramrod_flags = *ramrod_flags;
6721
6722         /* fill a user request section if needed */
6723         if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6724                 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6725                                  ETH_ALEN);
6726
6727                 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6728
6729 /* Set the command: ADD or DEL */
6730                 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6731                     ECORE_VLAN_MAC_DEL;
6732         }
6733
6734         rc = ecore_config_vlan_mac(sc, &ramrod_param);
6735
6736         if (rc == ECORE_EXISTS) {
6737                 PMD_DRV_LOG(INFO, sc, "Failed to schedule ADD operations (EEXIST)");
6738 /* do not treat adding same MAC as error */
6739                 rc = 0;
6740         } else if (rc < 0) {
6741                 PMD_DRV_LOG(ERR, sc,
6742                             "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6743         }
6744
6745         return rc;
6746 }
6747
6748 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6749 {
6750         unsigned long ramrod_flags = 0;
6751
6752         PMD_DRV_LOG(DEBUG, sc, "Adding Ethernet MAC");
6753
6754         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6755
6756         /* Eth MAC is set on RSS leading client (fp[0]) */
6757         return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6758                                &sc->sp_objs->mac_obj,
6759                                set, ECORE_ETH_MAC, &ramrod_flags);
6760 }
6761
6762 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6763 {
6764         uint32_t sel_phy_idx = 0;
6765
6766         if (sc->link_params.num_phys <= 1) {
6767                 return ELINK_INT_PHY;
6768         }
6769
6770         if (sc->link_vars.link_up) {
6771                 sel_phy_idx = ELINK_EXT_PHY1;
6772 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6773                 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6774                     (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6775                      ELINK_SUPPORTED_FIBRE))
6776                         sel_phy_idx = ELINK_EXT_PHY2;
6777         } else {
6778                 switch (elink_phy_selection(&sc->link_params)) {
6779                 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6780                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6781                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6782                         sel_phy_idx = ELINK_EXT_PHY1;
6783                         break;
6784                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6785                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6786                         sel_phy_idx = ELINK_EXT_PHY2;
6787                         break;
6788                 }
6789         }
6790
6791         return sel_phy_idx;
6792 }
6793
6794 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6795 {
6796         uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6797
6798         /*
6799          * The selected activated PHY is always after swapping (in case PHY
6800          * swapping is enabled). So when swapping is enabled, we need to reverse
6801          * the configuration
6802          */
6803
6804         if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6805                 if (sel_phy_idx == ELINK_EXT_PHY1)
6806                         sel_phy_idx = ELINK_EXT_PHY2;
6807                 else if (sel_phy_idx == ELINK_EXT_PHY2)
6808                         sel_phy_idx = ELINK_EXT_PHY1;
6809         }
6810
6811         return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6812 }
6813
6814 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6815 {
6816         /*
6817          * Initialize link parameters structure variables
6818          * It is recommended to turn off RX FC for jumbo frames
6819          * for better performance
6820          */
6821         if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6822                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6823         } else {
6824                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6825         }
6826 }
6827
6828 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6829 {
6830         uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6831         switch (sc->link_vars.ieee_fc &
6832                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6833         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6834         default:
6835                 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6836                                                    ADVERTISED_Pause);
6837                 break;
6838
6839         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6840                 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6841                                                   ADVERTISED_Pause);
6842                 break;
6843
6844         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6845                 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6846                 break;
6847         }
6848 }
6849
6850 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6851 {
6852         uint16_t line_speed = sc->link_vars.line_speed;
6853         if (IS_MF(sc)) {
6854                 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6855                                                       sc->devinfo.
6856                                                       mf_info.mf_config[SC_VN
6857                                                                         (sc)]);
6858
6859 /* calculate the current MAX line speed limit for the MF devices */
6860                 if (IS_MF_SI(sc)) {
6861                         line_speed = (line_speed * maxCfg) / 100;
6862                 } else {        /* SD mode */
6863                         uint16_t vn_max_rate = maxCfg * 100;
6864
6865                         if (vn_max_rate < line_speed) {
6866                                 line_speed = vn_max_rate;
6867                         }
6868                 }
6869         }
6870
6871         return line_speed;
6872 }
6873
6874 static void
6875 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6876 {
6877         uint16_t line_speed = bnx2x_get_mf_speed(sc);
6878
6879         memset(data, 0, sizeof(*data));
6880
6881         /* fill the report data with the effective line speed */
6882         data->line_speed = line_speed;
6883
6884         /* Link is down */
6885         if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6886                 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6887                             &data->link_report_flags);
6888         }
6889
6890         /* Full DUPLEX */
6891         if (sc->link_vars.duplex == DUPLEX_FULL) {
6892                 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6893                             &data->link_report_flags);
6894         }
6895
6896         /* Rx Flow Control is ON */
6897         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6898                 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6899         }
6900
6901         /* Tx Flow Control is ON */
6902         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6903                 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6904         }
6905 }
6906
6907 /* report link status to OS, should be called under phy_lock */
6908 static void bnx2x_link_report_locked(struct bnx2x_softc *sc)
6909 {
6910         struct bnx2x_link_report_data cur_data;
6911
6912         /* reread mf_cfg */
6913         if (IS_PF(sc)) {
6914                 bnx2x_read_mf_cfg(sc);
6915         }
6916
6917         /* Read the current link report info */
6918         bnx2x_fill_report_data(sc, &cur_data);
6919
6920         /* Don't report link down or exactly the same link status twice */
6921         if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6922             (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6923                           &sc->last_reported_link.link_report_flags) &&
6924              bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6925                           &cur_data.link_report_flags))) {
6926                 return;
6927         }
6928
6929         ELINK_DEBUG_P2(sc, "Change in link status : cur_data = %lx, last_reported_link = %lx",
6930                        cur_data.link_report_flags,
6931                        sc->last_reported_link.link_report_flags);
6932
6933         sc->link_cnt++;
6934
6935         ELINK_DEBUG_P1(sc, "link status change count = %x", sc->link_cnt);
6936         /* report new link params and remember the state for the next time */
6937         rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6938
6939         if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6940                          &cur_data.link_report_flags)) {
6941                 ELINK_DEBUG_P0(sc, "NIC Link is Down");
6942         } else {
6943                 __rte_unused const char *duplex;
6944                 __rte_unused const char *flow;
6945
6946                 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6947                                            &cur_data.link_report_flags)) {
6948                         duplex = "full";
6949                                 ELINK_DEBUG_P0(sc, "link set to full duplex");
6950                 } else {
6951                         duplex = "half";
6952                                 ELINK_DEBUG_P0(sc, "link set to half duplex");
6953                 }
6954
6955 /*
6956  * Handle the FC at the end so that only these flags would be
6957  * possibly set. This way we may easily check if there is no FC
6958  * enabled.
6959  */
6960                 if (cur_data.link_report_flags) {
6961                         if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6962                                          &cur_data.link_report_flags) &&
6963                             bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6964                                          &cur_data.link_report_flags)) {
6965                                 flow = "ON - receive & transmit";
6966                         } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6967                                                 &cur_data.link_report_flags) &&
6968                                    !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6969                                                  &cur_data.link_report_flags)) {
6970                                 flow = "ON - receive";
6971                         } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6972                                                  &cur_data.link_report_flags) &&
6973                                    bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6974                                                 &cur_data.link_report_flags)) {
6975                                 flow = "ON - transmit";
6976                         } else {
6977                                 flow = "none";  /* possible? */
6978                         }
6979                 } else {
6980                         flow = "none";
6981                 }
6982
6983                 PMD_DRV_LOG(INFO, sc,
6984                             "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6985                             cur_data.line_speed, duplex, flow);
6986         }
6987 }
6988
6989 static void
6990 bnx2x_link_report(struct bnx2x_softc *sc)
6991 {
6992         bnx2x_acquire_phy_lock(sc);
6993         bnx2x_link_report_locked(sc);
6994         bnx2x_release_phy_lock(sc);
6995 }
6996
6997 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6998 {
6999         if (sc->state != BNX2X_STATE_OPEN) {
7000                 return;
7001         }
7002
7003         if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
7004                 elink_link_status_update(&sc->link_params, &sc->link_vars);
7005         } else {
7006                 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
7007                                           ELINK_SUPPORTED_10baseT_Full |
7008                                           ELINK_SUPPORTED_100baseT_Half |
7009                                           ELINK_SUPPORTED_100baseT_Full |
7010                                           ELINK_SUPPORTED_1000baseT_Full |
7011                                           ELINK_SUPPORTED_2500baseX_Full |
7012                                           ELINK_SUPPORTED_10000baseT_Full |
7013                                           ELINK_SUPPORTED_TP |
7014                                           ELINK_SUPPORTED_FIBRE |
7015                                           ELINK_SUPPORTED_Autoneg |
7016                                           ELINK_SUPPORTED_Pause |
7017                                           ELINK_SUPPORTED_Asym_Pause);
7018                 sc->port.advertising[0] = sc->port.supported[0];
7019
7020                 sc->link_params.sc = sc;
7021                 sc->link_params.port = SC_PORT(sc);
7022                 sc->link_params.req_duplex[0] = DUPLEX_FULL;
7023                 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
7024                 sc->link_params.req_line_speed[0] = SPEED_10000;
7025                 sc->link_params.speed_cap_mask[0] = 0x7f0000;
7026                 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
7027
7028                 if (CHIP_REV_IS_FPGA(sc)) {
7029                         sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
7030                         sc->link_vars.line_speed = ELINK_SPEED_1000;
7031                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7032                                                      LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
7033                 } else {
7034                         sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
7035                         sc->link_vars.line_speed = ELINK_SPEED_10000;
7036                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7037                                                      LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
7038                 }
7039
7040                 sc->link_vars.link_up = 1;
7041
7042                 sc->link_vars.duplex = DUPLEX_FULL;
7043                 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
7044
7045                 if (IS_PF(sc)) {
7046                         REG_WR(sc,
7047                                NIG_REG_EGRESS_DRAIN0_MODE +
7048                                sc->link_params.port * 4, 0);
7049                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7050                         bnx2x_link_report(sc);
7051                 }
7052         }
7053
7054         if (IS_PF(sc)) {
7055                 if (sc->link_vars.link_up) {
7056                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7057                 } else {
7058                         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7059                 }
7060                 bnx2x_link_report(sc);
7061         } else {
7062                 bnx2x_link_report_locked(sc);
7063                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7064         }
7065 }
7066
7067 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7068 {
7069         int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7070         uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7071         struct elink_params *lp = &sc->link_params;
7072
7073         bnx2x_set_requested_fc(sc);
7074
7075         bnx2x_acquire_phy_lock(sc);
7076
7077         if (load_mode == LOAD_DIAG) {
7078                 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7079 /* Prefer doing PHY loopback at 10G speed, if possible */
7080                 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7081                         if (lp->speed_cap_mask[cfg_idx] &
7082                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7083                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7084                         } else {
7085                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7086                         }
7087                 }
7088         }
7089
7090         if (load_mode == LOAD_LOOPBACK_EXT) {
7091                 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7092         }
7093
7094         rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7095
7096         bnx2x_release_phy_lock(sc);
7097
7098         bnx2x_calc_fc_adv(sc);
7099
7100         if (sc->link_vars.link_up) {
7101                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7102                 bnx2x_link_report(sc);
7103         }
7104
7105         sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7106         return rc;
7107 }
7108
7109 /* update flags in shmem */
7110 static void
7111 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7112 {
7113         uint32_t drv_flags;
7114
7115         if (SHMEM2_HAS(sc, drv_flags)) {
7116                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7117                 drv_flags = SHMEM2_RD(sc, drv_flags);
7118
7119                 if (set) {
7120                         drv_flags |= flags;
7121                 } else {
7122                         drv_flags &= ~flags;
7123                 }
7124
7125                 SHMEM2_WR(sc, drv_flags, drv_flags);
7126
7127                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7128         }
7129 }
7130
7131 /* periodic timer callout routine, only runs when the interface is up */
7132 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7133 {
7134         if ((sc->state != BNX2X_STATE_OPEN) ||
7135             (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7136                 PMD_DRV_LOG(DEBUG, sc, "periodic callout exit (state=0x%x)",
7137                             sc->state);
7138                 return;
7139         }
7140         if (!CHIP_REV_IS_SLOW(sc)) {
7141 /*
7142  * This barrier is needed to ensure the ordering between the writing
7143  * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7144  * the reading here.
7145  */
7146                 mb();
7147                 if (sc->port.pmf) {
7148                         bnx2x_acquire_phy_lock(sc);
7149                         elink_period_func(&sc->link_params, &sc->link_vars);
7150                         bnx2x_release_phy_lock(sc);
7151                 }
7152         }
7153 #ifdef BNX2X_PULSE
7154         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7155                 int mb_idx = SC_FW_MB_IDX(sc);
7156                 uint32_t drv_pulse;
7157                 uint32_t mcp_pulse;
7158
7159                 ++sc->fw_drv_pulse_wr_seq;
7160                 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7161
7162                 drv_pulse = sc->fw_drv_pulse_wr_seq;
7163                 bnx2x_drv_pulse(sc);
7164
7165                 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7166                              MCP_PULSE_SEQ_MASK);
7167
7168 /*
7169  * The delta between driver pulse and mcp response should
7170  * be 1 (before mcp response) or 0 (after mcp response).
7171  */
7172                 if ((drv_pulse != mcp_pulse) &&
7173                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7174                         /* someone lost a heartbeat... */
7175                         PMD_DRV_LOG(ERR, sc,
7176                                     "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7177                                     drv_pulse, mcp_pulse);
7178                 }
7179         }
7180 #endif
7181 }
7182
7183 /* start the controller */
7184 static __rte_noinline
7185 int bnx2x_nic_load(struct bnx2x_softc *sc)
7186 {
7187         uint32_t val;
7188         uint32_t load_code = 0;
7189         int i, rc = 0;
7190
7191         PMD_INIT_FUNC_TRACE(sc);
7192
7193         sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7194
7195         if (IS_PF(sc)) {
7196 /* must be called before memory allocation and HW init */
7197                 bnx2x_ilt_set_info(sc);
7198         }
7199
7200         bnx2x_set_fp_rx_buf_size(sc);
7201
7202         if (IS_PF(sc)) {
7203                 if (bnx2x_alloc_mem(sc) != 0) {
7204                         sc->state = BNX2X_STATE_CLOSED;
7205                         rc = -ENOMEM;
7206                         goto bnx2x_nic_load_error0;
7207                 }
7208         }
7209
7210         if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7211                 sc->state = BNX2X_STATE_CLOSED;
7212                 rc = -ENOMEM;
7213                 goto bnx2x_nic_load_error0;
7214         }
7215
7216         if (IS_VF(sc)) {
7217                 rc = bnx2x_vf_init(sc);
7218                 if (rc) {
7219                         sc->state = BNX2X_STATE_ERROR;
7220                         goto bnx2x_nic_load_error0;
7221                 }
7222         }
7223
7224         if (IS_PF(sc)) {
7225 /* set pf load just before approaching the MCP */
7226                 bnx2x_set_pf_load(sc);
7227
7228 /* if MCP exists send load request and analyze response */
7229                 if (!BNX2X_NOMCP(sc)) {
7230                         /* attempt to load pf */
7231                         if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7232                                 sc->state = BNX2X_STATE_CLOSED;
7233                                 rc = -ENXIO;
7234                                 goto bnx2x_nic_load_error1;
7235                         }
7236
7237                         /* what did the MCP say? */
7238                         if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7239                                 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7240                                 sc->state = BNX2X_STATE_CLOSED;
7241                                 rc = -ENXIO;
7242                                 goto bnx2x_nic_load_error2;
7243                         }
7244                 } else {
7245                         PMD_DRV_LOG(INFO, sc, "Device has no MCP!");
7246                         load_code = bnx2x_nic_load_no_mcp(sc);
7247                 }
7248
7249 /* mark PMF if applicable */
7250                 bnx2x_nic_load_pmf(sc, load_code);
7251
7252 /* Init Function state controlling object */
7253                 bnx2x_init_func_obj(sc);
7254
7255 /* Initialize HW */
7256                 if (bnx2x_init_hw(sc, load_code) != 0) {
7257                         PMD_DRV_LOG(NOTICE, sc, "HW init failed");
7258                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7259                         sc->state = BNX2X_STATE_CLOSED;
7260                         rc = -ENXIO;
7261                         goto bnx2x_nic_load_error2;
7262                 }
7263         }
7264
7265         bnx2x_nic_init(sc, load_code);
7266
7267         /* Init per-function objects */
7268         if (IS_PF(sc)) {
7269                 bnx2x_init_objs(sc);
7270
7271 /* set AFEX default VLAN tag to an invalid value */
7272                 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7273
7274                 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7275                 rc = bnx2x_func_start(sc);
7276                 if (rc) {
7277                         PMD_DRV_LOG(NOTICE, sc, "Function start failed!");
7278                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7279                         sc->state = BNX2X_STATE_ERROR;
7280                         goto bnx2x_nic_load_error3;
7281                 }
7282
7283 /* send LOAD_DONE command to MCP */
7284                 if (!BNX2X_NOMCP(sc)) {
7285                         load_code =
7286                             bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7287                         if (!load_code) {
7288                                 PMD_DRV_LOG(NOTICE, sc,
7289                                             "MCP response failure, aborting");
7290                                 sc->state = BNX2X_STATE_ERROR;
7291                                 rc = -ENXIO;
7292                                 goto bnx2x_nic_load_error3;
7293                         }
7294                 }
7295         }
7296
7297         rc = bnx2x_setup_leading(sc);
7298         if (rc) {
7299                 PMD_DRV_LOG(NOTICE, sc, "Setup leading failed!");
7300                 sc->state = BNX2X_STATE_ERROR;
7301                 goto bnx2x_nic_load_error3;
7302         }
7303
7304         FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7305                 if (IS_PF(sc))
7306                         rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7307                 else            /* IS_VF(sc) */
7308                         rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7309
7310                 if (rc) {
7311                         PMD_DRV_LOG(NOTICE, sc, "Queue(%d) setup failed", i);
7312                         sc->state = BNX2X_STATE_ERROR;
7313                         goto bnx2x_nic_load_error3;
7314                 }
7315         }
7316
7317         rc = bnx2x_init_rss_pf(sc);
7318         if (rc) {
7319                 PMD_DRV_LOG(NOTICE, sc, "PF RSS init failed");
7320                 sc->state = BNX2X_STATE_ERROR;
7321                 goto bnx2x_nic_load_error3;
7322         }
7323
7324         /* now when Clients are configured we are ready to work */
7325         sc->state = BNX2X_STATE_OPEN;
7326
7327         /* Configure a ucast MAC */
7328         if (IS_PF(sc)) {
7329                 rc = bnx2x_set_eth_mac(sc, TRUE);
7330         } else {                /* IS_VF(sc) */
7331                 rc = bnx2x_vf_set_mac(sc, TRUE);
7332         }
7333
7334         if (rc) {
7335                 PMD_DRV_LOG(NOTICE, sc, "Setting Ethernet MAC failed");
7336                 sc->state = BNX2X_STATE_ERROR;
7337                 goto bnx2x_nic_load_error3;
7338         }
7339
7340         if (sc->port.pmf) {
7341                 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7342                 if (rc) {
7343                         sc->state = BNX2X_STATE_ERROR;
7344                         goto bnx2x_nic_load_error3;
7345                 }
7346         }
7347
7348         sc->link_params.feature_config_flags &=
7349             ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7350
7351         /* start the Tx */
7352         switch (LOAD_OPEN) {
7353         case LOAD_NORMAL:
7354         case LOAD_OPEN:
7355                 break;
7356
7357         case LOAD_DIAG:
7358         case LOAD_LOOPBACK_EXT:
7359                 sc->state = BNX2X_STATE_DIAG;
7360                 break;
7361
7362         default:
7363                 break;
7364         }
7365
7366         if (sc->port.pmf) {
7367                 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7368         } else {
7369                 bnx2x_link_status_update(sc);
7370         }
7371
7372         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7373 /* mark driver is loaded in shmem2 */
7374                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7375                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7376                           (val |
7377                            DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7378                            DRV_FLAGS_CAPABILITIES_LOADED_L2));
7379         }
7380
7381         /* start fast path */
7382         /* Initialize Rx filter */
7383         bnx2x_set_rx_mode(sc);
7384
7385         /* wait for all pending SP commands to complete */
7386         if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7387                 PMD_DRV_LOG(NOTICE, sc, "Timeout waiting for all SPs to complete!");
7388                 bnx2x_periodic_stop(sc);
7389                 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7390                 return -ENXIO;
7391         }
7392
7393         PMD_DRV_LOG(DEBUG, sc, "NIC successfully loaded");
7394
7395         return 0;
7396
7397 bnx2x_nic_load_error3:
7398
7399         if (IS_PF(sc)) {
7400                 bnx2x_int_disable_sync(sc, 1);
7401
7402 /* clean out queued objects */
7403                 bnx2x_squeeze_objects(sc);
7404         }
7405
7406 bnx2x_nic_load_error2:
7407
7408         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7409                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7410                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7411         }
7412
7413         sc->port.pmf = 0;
7414
7415 bnx2x_nic_load_error1:
7416
7417         /* clear pf_load status, as it was already set */
7418         if (IS_PF(sc)) {
7419                 bnx2x_clear_pf_load(sc);
7420         }
7421
7422 bnx2x_nic_load_error0:
7423
7424         bnx2x_free_fw_stats_mem(sc);
7425         bnx2x_free_mem(sc);
7426
7427         return rc;
7428 }
7429
7430 /*
7431 * Handles controller initialization.
7432 */
7433 int bnx2x_init(struct bnx2x_softc *sc)
7434 {
7435         int other_engine = SC_PATH(sc) ? 0 : 1;
7436         uint8_t other_load_status, load_status;
7437         uint8_t global = FALSE;
7438         int rc;
7439
7440         /* Check if the driver is still running and bail out if it is. */
7441         if (sc->state != BNX2X_STATE_CLOSED) {
7442                 PMD_DRV_LOG(DEBUG, sc, "Init called while driver is running!");
7443                 rc = 0;
7444                 goto bnx2x_init_done;
7445         }
7446
7447         bnx2x_set_power_state(sc, PCI_PM_D0);
7448
7449         /*
7450          * If parity occurred during the unload, then attentions and/or
7451          * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7452          * loaded on the current engine to complete the recovery. Parity recovery
7453          * is only relevant for PF driver.
7454          */
7455         if (IS_PF(sc)) {
7456                 other_load_status = bnx2x_get_load_status(sc, other_engine);
7457                 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7458
7459                 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7460                     bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7461                         do {
7462                                 /*
7463                                  * If there are attentions and they are in global blocks, set
7464                                  * the GLOBAL_RESET bit regardless whether it will be this
7465                                  * function that will complete the recovery or not.
7466                                  */
7467                                 if (global) {
7468                                         bnx2x_set_reset_global(sc);
7469                                 }
7470
7471                                 /*
7472                                  * Only the first function on the current engine should try
7473                                  * to recover in open. In case of attentions in global blocks
7474                                  * only the first in the chip should try to recover.
7475                                  */
7476                                 if ((!load_status
7477                                      && (!global ||!other_load_status))
7478                                     && bnx2x_trylock_leader_lock(sc)
7479                                     && !bnx2x_leader_reset(sc)) {
7480                                         PMD_DRV_LOG(INFO, sc,
7481                                                     "Recovered during init");
7482                                         break;
7483                                 }
7484
7485                                 /* recovery has failed... */
7486                                 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7487
7488                                 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7489
7490                                 PMD_DRV_LOG(NOTICE, sc,
7491                                             "Recovery flow hasn't properly "
7492                                             "completed yet, try again later. "
7493                                             "If you still see this message after a "
7494                                             "few retries then power cycle is required.");
7495
7496                                 rc = -ENXIO;
7497                                 goto bnx2x_init_done;
7498                         } while (0);
7499                 }
7500         }
7501
7502         sc->recovery_state = BNX2X_RECOVERY_DONE;
7503
7504         rc = bnx2x_nic_load(sc);
7505
7506 bnx2x_init_done:
7507
7508         if (rc) {
7509                 PMD_DRV_LOG(NOTICE, sc, "Initialization failed, "
7510                             "stack notified driver is NOT running!");
7511         }
7512
7513         return rc;
7514 }
7515
7516 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7517 {
7518         uint32_t val = 0;
7519
7520         /*
7521          * Read the ME register to get the function number. The ME register
7522          * holds the relative-function number and absolute-function number. The
7523          * absolute-function number appears only in E2 and above. Before that
7524          * these bits always contained zero, therefore we cannot blindly use them.
7525          */
7526
7527         val = REG_RD(sc, BAR_ME_REGISTER);
7528
7529         sc->pfunc_rel =
7530             (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7531         sc->path_id =
7532             (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7533             1;
7534
7535         if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7536                 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7537         } else {
7538                 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7539         }
7540
7541         PMD_DRV_LOG(DEBUG, sc,
7542                     "Relative function %d, Absolute function %d, Path %d",
7543                     sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7544 }
7545
7546 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7547 {
7548         uint32_t shmem2_size;
7549         uint32_t offset;
7550         uint32_t mf_cfg_offset_value;
7551
7552         /* Non 57712 */
7553         offset = (SHMEM_ADDR(sc, func_mb) +
7554                   (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7555
7556         /* 57712 plus */
7557         if (sc->devinfo.shmem2_base != 0) {
7558                 shmem2_size = SHMEM2_RD(sc, size);
7559                 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7560                         mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7561                         if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7562                                 offset = mf_cfg_offset_value;
7563                         }
7564                 }
7565         }
7566
7567         return offset;
7568 }
7569
7570 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7571 {
7572         uint32_t ret;
7573         struct bnx2x_pci_cap *caps;
7574
7575         /* ensure PCIe capability is enabled */
7576         caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7577         if (NULL != caps) {
7578                 PMD_DRV_LOG(DEBUG, sc, "Found PCIe capability: "
7579                             "id=0x%04X type=0x%04X addr=0x%08X",
7580                             caps->id, caps->type, caps->addr);
7581                 pci_read(sc, (caps->addr + reg), &ret, 2);
7582                 return ret;
7583         }
7584
7585         PMD_DRV_LOG(WARNING, sc, "PCIe capability NOT FOUND!!!");
7586
7587         return 0;
7588 }
7589
7590 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7591 {
7592         return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7593                 PCIM_EXP_STA_TRANSACTION_PND;
7594 }
7595
7596 /*
7597 * Walk the PCI capabiites list for the device to find what features are
7598 * supported. These capabilites may be enabled/disabled by firmware so it's
7599 * best to walk the list rather than make assumptions.
7600 */
7601 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7602 {
7603         PMD_INIT_FUNC_TRACE(sc);
7604
7605         struct bnx2x_pci_cap *caps;
7606         uint16_t link_status;
7607         int reg = 0;
7608
7609         /* check if PCI Power Management is enabled */
7610         caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7611         if (NULL != caps) {
7612                 PMD_DRV_LOG(DEBUG, sc, "Found PM capability: "
7613                             "id=0x%04X type=0x%04X addr=0x%08X",
7614                             caps->id, caps->type, caps->addr);
7615
7616                 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7617                 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7618         }
7619
7620         link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7621
7622         sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7623         sc->devinfo.pcie_link_width =
7624             ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7625
7626         PMD_DRV_LOG(DEBUG, sc, "PCIe link speed=%d width=%d",
7627                     sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7628
7629         sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7630
7631         /* check if MSI capability is enabled */
7632         caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7633         if (NULL != caps) {
7634                 PMD_DRV_LOG(DEBUG, sc, "Found MSI capability at 0x%04x", reg);
7635
7636                 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7637                 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7638         }
7639
7640         /* check if MSI-X capability is enabled */
7641         caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7642         if (NULL != caps) {
7643                 PMD_DRV_LOG(DEBUG, sc, "Found MSI-X capability at 0x%04x", reg);
7644
7645                 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7646                 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7647         }
7648 }
7649
7650 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7651 {
7652         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7653         uint32_t val;
7654
7655         /* get the outer vlan if we're in switch-dependent mode */
7656
7657         val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7658         mf_info->ext_id = (uint16_t) val;
7659
7660         mf_info->multi_vnics_mode = 1;
7661
7662         if (!VALID_OVLAN(mf_info->ext_id)) {
7663                 PMD_DRV_LOG(NOTICE, sc, "Invalid VLAN (%d)", mf_info->ext_id);
7664                 return 1;
7665         }
7666
7667         /* get the capabilities */
7668         if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7669             FUNC_MF_CFG_PROTOCOL_ISCSI) {
7670                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7671         } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7672                    == FUNC_MF_CFG_PROTOCOL_FCOE) {
7673                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7674         } else {
7675                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7676         }
7677
7678         mf_info->vnics_per_port =
7679             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7680
7681         return 0;
7682 }
7683
7684 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7685 {
7686         uint32_t retval = 0;
7687         uint32_t val;
7688
7689         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7690
7691         if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7692                 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7693                         retval |= MF_PROTO_SUPPORT_ETHERNET;
7694                 }
7695                 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7696                         retval |= MF_PROTO_SUPPORT_ISCSI;
7697                 }
7698                 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7699                         retval |= MF_PROTO_SUPPORT_FCOE;
7700                 }
7701         }
7702
7703         return retval;
7704 }
7705
7706 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7707 {
7708         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7709         uint32_t val;
7710
7711         /*
7712          * There is no outer vlan if we're in switch-independent mode.
7713          * If the mac is valid then assume multi-function.
7714          */
7715
7716         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7717
7718         mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7719
7720         mf_info->mf_protos_supported =
7721             bnx2x_get_shmem_ext_proto_support_flags(sc);
7722
7723         mf_info->vnics_per_port =
7724             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7725
7726         return 0;
7727 }
7728
7729 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7730 {
7731         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7732         uint32_t e1hov_tag;
7733         uint32_t func_config;
7734         uint32_t niv_config;
7735
7736         mf_info->multi_vnics_mode = 1;
7737
7738         e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7739         func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7740         niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7741
7742         mf_info->ext_id =
7743             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7744                         FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7745
7746         mf_info->default_vlan =
7747             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7748                         FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7749
7750         mf_info->niv_allowed_priorities =
7751             (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7752                        FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7753
7754         mf_info->niv_default_cos =
7755             (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7756                        FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7757
7758         mf_info->afex_vlan_mode =
7759             ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7760              FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7761
7762         mf_info->niv_mba_enabled =
7763             ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7764              FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7765
7766         mf_info->mf_protos_supported =
7767             bnx2x_get_shmem_ext_proto_support_flags(sc);
7768
7769         mf_info->vnics_per_port =
7770             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7771
7772         return 0;
7773 }
7774
7775 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7776 {
7777         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7778         uint32_t mf_cfg1;
7779         uint32_t mf_cfg2;
7780         uint32_t ovlan1;
7781         uint32_t ovlan2;
7782         uint8_t i, j;
7783
7784         /* various MF mode sanity checks... */
7785
7786         if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7787                 PMD_DRV_LOG(NOTICE, sc,
7788                             "Enumerated function %d is marked as hidden",
7789                             SC_PORT(sc));
7790                 return 1;
7791         }
7792
7793         if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7794                 PMD_DRV_LOG(NOTICE, sc, "vnics_per_port=%d multi_vnics_mode=%d",
7795                             mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7796                 return 1;
7797         }
7798
7799         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7800 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7801                 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7802                         PMD_DRV_LOG(NOTICE, sc, "mf_mode=SD vnic_id=%d ovlan=%d",
7803                                     SC_VN(sc), OVLAN(sc));
7804                         return 1;
7805                 }
7806
7807                 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7808                         PMD_DRV_LOG(NOTICE, sc,
7809                                     "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7810                                     mf_info->multi_vnics_mode, OVLAN(sc));
7811                         return 1;
7812                 }
7813
7814 /*
7815  * Verify all functions are either MF or SF mode. If MF, make sure
7816  * sure that all non-hidden functions have a valid ovlan. If SF,
7817  * make sure that all non-hidden functions have an invalid ovlan.
7818  */
7819                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7820                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7821                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7822                         if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7823                             (((mf_info->multi_vnics_mode)
7824                               && !VALID_OVLAN(ovlan1))
7825                              || ((!mf_info->multi_vnics_mode)
7826                                  && VALID_OVLAN(ovlan1)))) {
7827                                 PMD_DRV_LOG(NOTICE, sc,
7828                                             "mf_mode=SD function %d MF config "
7829                                             "mismatch, multi_vnics_mode=%d ovlan=%d",
7830                                             i, mf_info->multi_vnics_mode,
7831                                             ovlan1);
7832                                 return 1;
7833                         }
7834                 }
7835
7836 /* Verify all funcs on the same port each have a different ovlan. */
7837                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7838                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7839                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7840                         /* iterate from the next function on the port to the max func */
7841                         for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7842                                 mf_cfg2 =
7843                                     MFCFG_RD(sc, func_mf_config[j].config);
7844                                 ovlan2 =
7845                                     MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7846                                 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7847                                     && VALID_OVLAN(ovlan1)
7848                                     && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7849                                     && VALID_OVLAN(ovlan2)
7850                                     && (ovlan1 == ovlan2)) {
7851                                         PMD_DRV_LOG(NOTICE, sc,
7852                                                     "mf_mode=SD functions %d and %d "
7853                                                     "have the same ovlan (%d)",
7854                                                     i, j, ovlan1);
7855                                         return 1;
7856                                 }
7857                         }
7858                 }
7859         }
7860         /* MULTI_FUNCTION_SD */
7861         return 0;
7862 }
7863
7864 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7865 {
7866         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7867         uint32_t val, mac_upper;
7868         uint8_t i, vnic;
7869
7870         /* initialize mf_info defaults */
7871         mf_info->vnics_per_port = 1;
7872         mf_info->multi_vnics_mode = FALSE;
7873         mf_info->path_has_ovlan = FALSE;
7874         mf_info->mf_mode = SINGLE_FUNCTION;
7875
7876         if (!CHIP_IS_MF_CAP(sc)) {
7877                 return 0;
7878         }
7879
7880         if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7881                 PMD_DRV_LOG(NOTICE, sc, "Invalid mf_cfg_base!");
7882                 return 1;
7883         }
7884
7885         /* get the MF mode (switch dependent / independent / single-function) */
7886
7887         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7888
7889         switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7890         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7891
7892                 mac_upper =
7893                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7894
7895                 /* check for legal upper mac bytes */
7896                 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7897                         mf_info->mf_mode = MULTI_FUNCTION_SI;
7898                 } else {
7899                         PMD_DRV_LOG(NOTICE, sc,
7900                                     "Invalid config for Switch Independent mode");
7901                 }
7902
7903                 break;
7904
7905         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7906         case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7907
7908                 /* get outer vlan configuration */
7909                 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7910
7911                 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7912                     FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7913                         mf_info->mf_mode = MULTI_FUNCTION_SD;
7914                 } else {
7915                         PMD_DRV_LOG(NOTICE, sc,
7916                                     "Invalid config for Switch Dependent mode");
7917                 }
7918
7919                 break;
7920
7921         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7922
7923                 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7924                 return 0;
7925
7926         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7927
7928                 /*
7929                  * Mark MF mode as NIV if MCP version includes NPAR-SD support
7930                  * and the MAC address is valid.
7931                  */
7932                 mac_upper =
7933                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7934
7935                 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7936                     (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7937                         mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7938                 } else {
7939                         PMD_DRV_LOG(NOTICE, sc, "Invalid config for AFEX mode");
7940                 }
7941
7942                 break;
7943
7944         default:
7945
7946                 PMD_DRV_LOG(NOTICE, sc, "Unknown MF mode (0x%08x)",
7947                             (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7948
7949                 return 1;
7950         }
7951
7952         /* set path mf_mode (which could be different than function mf_mode) */
7953         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7954                 mf_info->path_has_ovlan = TRUE;
7955         } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7956 /*
7957  * Decide on path multi vnics mode. If we're not in MF mode and in
7958  * 4-port mode, this is good enough to check vnic-0 of the other port
7959  * on the same path
7960  */
7961                 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7962                         uint8_t other_port = !(PORT_ID(sc) & 1);
7963                         uint8_t abs_func_other_port =
7964                             (SC_PATH(sc) + (2 * other_port));
7965
7966                         val =
7967                             MFCFG_RD(sc,
7968                                      func_mf_config
7969                                      [abs_func_other_port].e1hov_tag);
7970
7971                         mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7972                 }
7973         }
7974
7975         if (mf_info->mf_mode == SINGLE_FUNCTION) {
7976 /* invalid MF config */
7977                 if (SC_VN(sc) >= 1) {
7978                         PMD_DRV_LOG(NOTICE, sc, "VNIC ID >= 1 in SF mode");
7979                         return 1;
7980                 }
7981
7982                 return 0;
7983         }
7984
7985         /* get the MF configuration */
7986         mf_info->mf_config[SC_VN(sc)] =
7987             MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7988
7989         switch (mf_info->mf_mode) {
7990         case MULTI_FUNCTION_SD:
7991
7992                 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7993                 break;
7994
7995         case MULTI_FUNCTION_SI:
7996
7997                 bnx2x_get_shmem_mf_cfg_info_si(sc);
7998                 break;
7999
8000         case MULTI_FUNCTION_AFEX:
8001
8002                 bnx2x_get_shmem_mf_cfg_info_niv(sc);
8003                 break;
8004
8005         default:
8006
8007                 PMD_DRV_LOG(NOTICE, sc, "Get MF config failed (mf_mode=0x%08x)",
8008                             mf_info->mf_mode);
8009                 return 1;
8010         }
8011
8012         /* get the congestion management parameters */
8013
8014         vnic = 0;
8015         FOREACH_ABS_FUNC_IN_PORT(sc, i) {
8016 /* get min/max bw */
8017                 val = MFCFG_RD(sc, func_mf_config[i].config);
8018                 mf_info->min_bw[vnic] =
8019                     ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
8020                      FUNC_MF_CFG_MIN_BW_SHIFT);
8021                 mf_info->max_bw[vnic] =
8022                     ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
8023                      FUNC_MF_CFG_MAX_BW_SHIFT);
8024                 vnic++;
8025         }
8026
8027         return bnx2x_check_valid_mf_cfg(sc);
8028 }
8029
8030 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8031 {
8032         int port;
8033         uint32_t mac_hi, mac_lo, val;
8034
8035         PMD_INIT_FUNC_TRACE(sc);
8036
8037         port = SC_PORT(sc);
8038         mac_hi = mac_lo = 0;
8039
8040         sc->link_params.sc = sc;
8041         sc->link_params.port = port;
8042
8043         /* get the hardware config info */
8044         sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8045         sc->devinfo.hw_config2 =
8046             SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8047
8048         sc->link_params.hw_led_mode =
8049             ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8050              SHARED_HW_CFG_LED_MODE_SHIFT);
8051
8052         /* get the port feature config */
8053         sc->port.config =
8054             SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8055
8056         /* get the link params */
8057         sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8058             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8059             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8060         sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8061             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8062             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8063
8064         /* get the lane config */
8065         sc->link_params.lane_config =
8066             SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8067
8068         /* get the link config */
8069         val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8070         sc->port.link_config[ELINK_INT_PHY] = val;
8071         sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8072         sc->port.link_config[ELINK_EXT_PHY1] =
8073             SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8074
8075         /* get the override preemphasis flag and enable it or turn it off */
8076         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8077         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8078                 sc->link_params.feature_config_flags |=
8079                     ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8080         } else {
8081                 sc->link_params.feature_config_flags &=
8082                     ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8083         }
8084
8085         /* get the initial value of the link params */
8086         sc->link_params.multi_phy_config =
8087             SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8088
8089         /* get external phy info */
8090         sc->port.ext_phy_config =
8091             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8092
8093         /* get the multifunction configuration */
8094         bnx2x_get_mf_cfg_info(sc);
8095
8096         /* get the mac address */
8097         if (IS_MF(sc)) {
8098                 mac_hi =
8099                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8100                 mac_lo =
8101                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8102         } else {
8103                 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8104                 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8105         }
8106
8107         if ((mac_lo == 0) && (mac_hi == 0)) {
8108                 *sc->mac_addr_str = 0;
8109                 PMD_DRV_LOG(NOTICE, sc, "No Ethernet address programmed!");
8110         } else {
8111                 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8112                 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8113                 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8114                 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8115                 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8116                 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8117                 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8118                          "%02x:%02x:%02x:%02x:%02x:%02x",
8119                          sc->link_params.mac_addr[0],
8120                          sc->link_params.mac_addr[1],
8121                          sc->link_params.mac_addr[2],
8122                          sc->link_params.mac_addr[3],
8123                          sc->link_params.mac_addr[4],
8124                          sc->link_params.mac_addr[5]);
8125                 PMD_DRV_LOG(DEBUG, sc,
8126                             "Ethernet address: %s", sc->mac_addr_str);
8127         }
8128
8129         return 0;
8130 }
8131
8132 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8133 {
8134         uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8135         switch (sc->link_params.phy[phy_idx].media_type) {
8136         case ELINK_ETH_PHY_SFPP_10G_FIBER:
8137         case ELINK_ETH_PHY_SFP_1G_FIBER:
8138         case ELINK_ETH_PHY_XFP_FIBER:
8139         case ELINK_ETH_PHY_KR:
8140         case ELINK_ETH_PHY_CX4:
8141                 PMD_DRV_LOG(INFO, sc, "Found 10GBase-CX4 media.");
8142                 sc->media = IFM_10G_CX4;
8143                 break;
8144         case ELINK_ETH_PHY_DA_TWINAX:
8145                 PMD_DRV_LOG(INFO, sc, "Found 10Gb Twinax media.");
8146                 sc->media = IFM_10G_TWINAX;
8147                 break;
8148         case ELINK_ETH_PHY_BASE_T:
8149                 PMD_DRV_LOG(INFO, sc, "Found 10GBase-T media.");
8150                 sc->media = IFM_10G_T;
8151                 break;
8152         case ELINK_ETH_PHY_NOT_PRESENT:
8153                 PMD_DRV_LOG(INFO, sc, "Media not present.");
8154                 sc->media = 0;
8155                 break;
8156         case ELINK_ETH_PHY_UNSPECIFIED:
8157         default:
8158                 PMD_DRV_LOG(INFO, sc, "Unknown media!");
8159                 sc->media = 0;
8160                 break;
8161         }
8162 }
8163
8164 #define GET_FIELD(value, fname)                     \
8165 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8166 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8167 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8168
8169 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8170 {
8171         int pfid = SC_FUNC(sc);
8172         int igu_sb_id;
8173         uint32_t val;
8174         uint8_t fid, igu_sb_cnt = 0;
8175
8176         sc->igu_base_sb = 0xff;
8177
8178         if (CHIP_INT_MODE_IS_BC(sc)) {
8179                 int vn = SC_VN(sc);
8180                 igu_sb_cnt = sc->igu_sb_cnt;
8181                 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8182                                    FP_SB_MAX_E1x);
8183                 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8184                                   (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8185                 return 0;
8186         }
8187
8188         /* IGU in normal mode - read CAM */
8189         for (igu_sb_id = 0;
8190              igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8191                 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8192                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8193                         continue;
8194                 }
8195                 fid = IGU_FID(val);
8196                 if (fid & IGU_FID_ENCODE_IS_PF) {
8197                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8198                                 continue;
8199                         }
8200                         if (IGU_VEC(val) == 0) {
8201                                 /* default status block */
8202                                 sc->igu_dsb_id = igu_sb_id;
8203                         } else {
8204                                 if (sc->igu_base_sb == 0xff) {
8205                                         sc->igu_base_sb = igu_sb_id;
8206                                 }
8207                                 igu_sb_cnt++;
8208                         }
8209                 }
8210         }
8211
8212         /*
8213          * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8214          * that number of CAM entries will not be equal to the value advertised in
8215          * PCI. Driver should use the minimal value of both as the actual status
8216          * block count
8217          */
8218         sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8219
8220         if (igu_sb_cnt == 0) {
8221                 PMD_DRV_LOG(ERR, sc, "CAM configuration error");
8222                 return -1;
8223         }
8224
8225         return 0;
8226 }
8227
8228 /*
8229 * Gather various information from the device config space, the device itself,
8230 * shmem, and the user input.
8231 */
8232 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8233 {
8234         uint32_t val;
8235         int rc;
8236
8237         /* get the chip revision (chip metal comes from pci config space) */
8238         sc->devinfo.chip_id = sc->link_params.chip_id =
8239             (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8240              ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8241              (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8242              ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8243
8244         /* force 57811 according to MISC register */
8245         if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8246                 if (CHIP_IS_57810(sc)) {
8247                         sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8248                                                (sc->
8249                                                 devinfo.chip_id & 0x0000ffff));
8250                 } else if (CHIP_IS_57810_MF(sc)) {
8251                         sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8252                                                (sc->
8253                                                 devinfo.chip_id & 0x0000ffff));
8254                 }
8255                 sc->devinfo.chip_id |= 0x1;
8256         }
8257
8258         PMD_DRV_LOG(DEBUG, sc,
8259                     "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8260                     sc->devinfo.chip_id,
8261                     ((sc->devinfo.chip_id >> 16) & 0xffff),
8262                     ((sc->devinfo.chip_id >> 12) & 0xf),
8263                     ((sc->devinfo.chip_id >> 4) & 0xff),
8264                     ((sc->devinfo.chip_id >> 0) & 0xf));
8265
8266         val = (REG_RD(sc, 0x2874) & 0x55);
8267         if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8268                 sc->flags |= BNX2X_ONE_PORT_FLAG;
8269                 PMD_DRV_LOG(DEBUG, sc, "single port device");
8270         }
8271
8272         /* set the doorbell size */
8273         sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8274
8275         /* determine whether the device is in 2 port or 4 port mode */
8276         sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE;       /* E1h */
8277         if (CHIP_IS_E2E3(sc)) {
8278 /*
8279  * Read port4mode_en_ovwr[0]:
8280  *   If 1, four port mode is in port4mode_en_ovwr[1].
8281  *   If 0, four port mode is in port4mode_en[0].
8282  */
8283                 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8284                 if (val & 1) {
8285                         val = ((val >> 1) & 1);
8286                 } else {
8287                         val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8288                 }
8289
8290                 sc->devinfo.chip_port_mode =
8291                     (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8292
8293                 PMD_DRV_LOG(DEBUG, sc, "Port mode = %s", (val) ? "4" : "2");
8294         }
8295
8296         /* get the function and path info for the device */
8297         bnx2x_get_function_num(sc);
8298
8299         /* get the shared memory base address */
8300         sc->devinfo.shmem_base =
8301             sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8302         sc->devinfo.shmem2_base =
8303             REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8304                         MISC_REG_GENERIC_CR_0));
8305
8306         if (!sc->devinfo.shmem_base) {
8307 /* this should ONLY prevent upcoming shmem reads */
8308                 PMD_DRV_LOG(INFO, sc, "MCP not active");
8309                 sc->flags |= BNX2X_NO_MCP_FLAG;
8310                 return 0;
8311         }
8312
8313         /* make sure the shared memory contents are valid */
8314         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8315         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8316             (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8317                 PMD_DRV_LOG(NOTICE, sc, "Invalid SHMEM validity signature: 0x%08x",
8318                             val);
8319                 return 0;
8320         }
8321
8322         /* get the bootcode version */
8323         sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8324         snprintf(sc->devinfo.bc_ver_str,
8325                  sizeof(sc->devinfo.bc_ver_str),
8326                  "%d.%d.%d",
8327                  ((sc->devinfo.bc_ver >> 24) & 0xff),
8328                  ((sc->devinfo.bc_ver >> 16) & 0xff),
8329                  ((sc->devinfo.bc_ver >> 8) & 0xff));
8330         PMD_DRV_LOG(DEBUG, sc, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8331
8332         /* get the bootcode shmem address */
8333         sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8334
8335         /* clean indirect addresses as they're not used */
8336         pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8337         if (IS_PF(sc)) {
8338                 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8339                 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8340                 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8341                 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8342                 if (CHIP_IS_E1x(sc)) {
8343                         REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8344                         REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8345                         REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8346                         REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8347                 }
8348         }
8349
8350         /* get the nvram size */
8351         val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8352         sc->devinfo.flash_size =
8353             (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8354
8355         bnx2x_set_power_state(sc, PCI_PM_D0);
8356         /* get various configuration parameters from shmem */
8357         bnx2x_get_shmem_info(sc);
8358
8359         /* initialize IGU parameters */
8360         if (CHIP_IS_E1x(sc)) {
8361                 sc->devinfo.int_block = INT_BLOCK_HC;
8362                 sc->igu_dsb_id = DEF_SB_IGU_ID;
8363                 sc->igu_base_sb = 0;
8364         } else {
8365                 sc->devinfo.int_block = INT_BLOCK_IGU;
8366
8367 /* do not allow device reset during IGU info preocessing */
8368                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8369
8370                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8371
8372                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8373                         int tout = 5000;
8374
8375                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8376                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8377                         REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8378
8379                         while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8380                                 tout--;
8381                                 DELAY(1000);
8382                         }
8383
8384                         if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8385                                 PMD_DRV_LOG(NOTICE, sc,
8386                                             "FORCING IGU Normal Mode failed!!!");
8387                                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8388                                 return -1;
8389                         }
8390                 }
8391
8392                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8393                         PMD_DRV_LOG(DEBUG, sc, "IGU Backward Compatible Mode");
8394                         sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8395                 } else {
8396                         PMD_DRV_LOG(DEBUG, sc, "IGU Normal Mode");
8397                 }
8398
8399                 rc = bnx2x_get_igu_cam_info(sc);
8400
8401                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8402
8403                 if (rc) {
8404                         return rc;
8405                 }
8406         }
8407
8408         /*
8409          * Get base FW non-default (fast path) status block ID. This value is
8410          * used to initialize the fw_sb_id saved on the fp/queue structure to
8411          * determine the id used by the FW.
8412          */
8413         if (CHIP_IS_E1x(sc)) {
8414                 sc->base_fw_ndsb =
8415                     ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8416         } else {
8417 /*
8418  * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8419  * the same queue are indicated on the same IGU SB). So we prefer
8420  * FW and IGU SBs to be the same value.
8421  */
8422                 sc->base_fw_ndsb = sc->igu_base_sb;
8423         }
8424
8425         elink_phy_probe(&sc->link_params);
8426
8427         return 0;
8428 }
8429
8430 static void
8431 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8432 {
8433         uint32_t cfg_size = 0;
8434         uint32_t idx;
8435         uint8_t port = SC_PORT(sc);
8436
8437         /* aggregation of supported attributes of all external phys */
8438         sc->port.supported[0] = 0;
8439         sc->port.supported[1] = 0;
8440
8441         switch (sc->link_params.num_phys) {
8442         case 1:
8443                 sc->port.supported[0] =
8444                     sc->link_params.phy[ELINK_INT_PHY].supported;
8445                 cfg_size = 1;
8446                 break;
8447         case 2:
8448                 sc->port.supported[0] =
8449                     sc->link_params.phy[ELINK_EXT_PHY1].supported;
8450                 cfg_size = 1;
8451                 break;
8452         case 3:
8453                 if (sc->link_params.multi_phy_config &
8454                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8455                         sc->port.supported[1] =
8456                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8457                         sc->port.supported[0] =
8458                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8459                 } else {
8460                         sc->port.supported[0] =
8461                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8462                         sc->port.supported[1] =
8463                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8464                 }
8465                 cfg_size = 2;
8466                 break;
8467         }
8468
8469         if (!(sc->port.supported[0] || sc->port.supported[1])) {
8470                 PMD_DRV_LOG(ERR, sc,
8471                             "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8472                             SHMEM_RD(sc,
8473                                      dev_info.port_hw_config
8474                                      [port].external_phy_config),
8475                             SHMEM_RD(sc,
8476                                      dev_info.port_hw_config
8477                                      [port].external_phy_config2));
8478                 return;
8479         }
8480
8481         if (CHIP_IS_E3(sc))
8482                 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8483         else {
8484                 switch (switch_cfg) {
8485                 case ELINK_SWITCH_CFG_1G:
8486                         sc->port.phy_addr =
8487                             REG_RD(sc,
8488                                    NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8489                         break;
8490                 case ELINK_SWITCH_CFG_10G:
8491                         sc->port.phy_addr =
8492                             REG_RD(sc,
8493                                    NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8494                         break;
8495                 default:
8496                         PMD_DRV_LOG(ERR, sc,
8497                                     "Invalid switch config in"
8498                                     "link_config=0x%08x",
8499                                     sc->port.link_config[0]);
8500                         return;
8501                 }
8502         }
8503
8504         PMD_DRV_LOG(INFO, sc, "PHY addr 0x%08x", sc->port.phy_addr);
8505
8506         /* mask what we support according to speed_cap_mask per configuration */
8507         for (idx = 0; idx < cfg_size; idx++) {
8508                 if (!(sc->link_params.speed_cap_mask[idx] &
8509                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8510                         sc->port.supported[idx] &=
8511                             ~ELINK_SUPPORTED_10baseT_Half;
8512                 }
8513
8514                 if (!(sc->link_params.speed_cap_mask[idx] &
8515                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8516                         sc->port.supported[idx] &=
8517                             ~ELINK_SUPPORTED_10baseT_Full;
8518                 }
8519
8520                 if (!(sc->link_params.speed_cap_mask[idx] &
8521                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8522                         sc->port.supported[idx] &=
8523                             ~ELINK_SUPPORTED_100baseT_Half;
8524                 }
8525
8526                 if (!(sc->link_params.speed_cap_mask[idx] &
8527                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8528                         sc->port.supported[idx] &=
8529                             ~ELINK_SUPPORTED_100baseT_Full;
8530                 }
8531
8532                 if (!(sc->link_params.speed_cap_mask[idx] &
8533                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8534                         sc->port.supported[idx] &=
8535                             ~ELINK_SUPPORTED_1000baseT_Full;
8536                 }
8537
8538                 if (!(sc->link_params.speed_cap_mask[idx] &
8539                       PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8540                         sc->port.supported[idx] &=
8541                             ~ELINK_SUPPORTED_2500baseX_Full;
8542                 }
8543
8544                 if (!(sc->link_params.speed_cap_mask[idx] &
8545                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8546                         sc->port.supported[idx] &=
8547                             ~ELINK_SUPPORTED_10000baseT_Full;
8548                 }
8549
8550                 if (!(sc->link_params.speed_cap_mask[idx] &
8551                       PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8552                         sc->port.supported[idx] &=
8553                             ~ELINK_SUPPORTED_20000baseKR2_Full;
8554                 }
8555         }
8556
8557         PMD_DRV_LOG(INFO, sc, "PHY supported 0=0x%08x 1=0x%08x",
8558                     sc->port.supported[0], sc->port.supported[1]);
8559 }
8560
8561 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8562 {
8563         uint32_t link_config;
8564         uint32_t idx;
8565         uint32_t cfg_size = 0;
8566
8567         sc->port.advertising[0] = 0;
8568         sc->port.advertising[1] = 0;
8569
8570         switch (sc->link_params.num_phys) {
8571         case 1:
8572         case 2:
8573                 cfg_size = 1;
8574                 break;
8575         case 3:
8576                 cfg_size = 2;
8577                 break;
8578         }
8579
8580         for (idx = 0; idx < cfg_size; idx++) {
8581                 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8582                 link_config = sc->port.link_config[idx];
8583
8584                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8585                 case PORT_FEATURE_LINK_SPEED_AUTO:
8586                         if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8587                                 sc->link_params.req_line_speed[idx] =
8588                                     ELINK_SPEED_AUTO_NEG;
8589                                 sc->port.advertising[idx] |=
8590                                     sc->port.supported[idx];
8591                                 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8592                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8593                                         sc->port.advertising[idx] |=
8594                                             (ELINK_SUPPORTED_100baseT_Half |
8595                                              ELINK_SUPPORTED_100baseT_Full);
8596                         } else {
8597                                 /* force 10G, no AN */
8598                                 sc->link_params.req_line_speed[idx] =
8599                                     ELINK_SPEED_10000;
8600                                 sc->port.advertising[idx] |=
8601                                     (ADVERTISED_10000baseT_Full |
8602                                      ADVERTISED_FIBRE);
8603                                 continue;
8604                         }
8605                         break;
8606
8607                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8608                         if (sc->
8609                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8610                         {
8611                                 sc->link_params.req_line_speed[idx] =
8612                                     ELINK_SPEED_10;
8613                                 sc->port.advertising[idx] |=
8614                                     (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8615                         } else {
8616                                 PMD_DRV_LOG(ERR, sc,
8617                                             "Invalid NVRAM config link_config=0x%08x "
8618                                             "speed_cap_mask=0x%08x",
8619                                             link_config,
8620                                             sc->
8621                                             link_params.speed_cap_mask[idx]);
8622                                 return;
8623                         }
8624                         break;
8625
8626                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8627                         if (sc->
8628                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8629                         {
8630                                 sc->link_params.req_line_speed[idx] =
8631                                     ELINK_SPEED_10;
8632                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8633                                 sc->port.advertising[idx] |=
8634                                     (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8635                         } else {
8636                                 PMD_DRV_LOG(ERR, sc,
8637                                             "Invalid NVRAM config link_config=0x%08x "
8638                                             "speed_cap_mask=0x%08x",
8639                                             link_config,
8640                                             sc->
8641                                             link_params.speed_cap_mask[idx]);
8642                                 return;
8643                         }
8644                         break;
8645
8646                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8647                         if (sc->
8648                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8649                         {
8650                                 sc->link_params.req_line_speed[idx] =
8651                                     ELINK_SPEED_100;
8652                                 sc->port.advertising[idx] |=
8653                                     (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8654                         } else {
8655                                 PMD_DRV_LOG(ERR, sc,
8656                                             "Invalid NVRAM config link_config=0x%08x "
8657                                             "speed_cap_mask=0x%08x",
8658                                             link_config,
8659                                             sc->
8660                                             link_params.speed_cap_mask[idx]);
8661                                 return;
8662                         }
8663                         break;
8664
8665                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8666                         if (sc->
8667                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8668                         {
8669                                 sc->link_params.req_line_speed[idx] =
8670                                     ELINK_SPEED_100;
8671                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8672                                 sc->port.advertising[idx] |=
8673                                     (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8674                         } else {
8675                                 PMD_DRV_LOG(ERR, sc,
8676                                             "Invalid NVRAM config link_config=0x%08x "
8677                                             "speed_cap_mask=0x%08x",
8678                                             link_config,
8679                                             sc->
8680                                             link_params.speed_cap_mask[idx]);
8681                                 return;
8682                         }
8683                         break;
8684
8685                 case PORT_FEATURE_LINK_SPEED_1G:
8686                         if (sc->port.supported[idx] &
8687                             ELINK_SUPPORTED_1000baseT_Full) {
8688                                 sc->link_params.req_line_speed[idx] =
8689                                     ELINK_SPEED_1000;
8690                                 sc->port.advertising[idx] |=
8691                                     (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8692                         } else {
8693                                 PMD_DRV_LOG(ERR, sc,
8694                                             "Invalid NVRAM config link_config=0x%08x "
8695                                             "speed_cap_mask=0x%08x",
8696                                             link_config,
8697                                             sc->
8698                                             link_params.speed_cap_mask[idx]);
8699                                 return;
8700                         }
8701                         break;
8702
8703                 case PORT_FEATURE_LINK_SPEED_2_5G:
8704                         if (sc->port.supported[idx] &
8705                             ELINK_SUPPORTED_2500baseX_Full) {
8706                                 sc->link_params.req_line_speed[idx] =
8707                                     ELINK_SPEED_2500;
8708                                 sc->port.advertising[idx] |=
8709                                     (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8710                         } else {
8711                                 PMD_DRV_LOG(ERR, sc,
8712                                             "Invalid NVRAM config link_config=0x%08x "
8713                                             "speed_cap_mask=0x%08x",
8714                                             link_config,
8715                                             sc->
8716                                             link_params.speed_cap_mask[idx]);
8717                                 return;
8718                         }
8719                         break;
8720
8721                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8722                         if (sc->port.supported[idx] &
8723                             ELINK_SUPPORTED_10000baseT_Full) {
8724                                 sc->link_params.req_line_speed[idx] =
8725                                     ELINK_SPEED_10000;
8726                                 sc->port.advertising[idx] |=
8727                                     (ADVERTISED_10000baseT_Full |
8728                                      ADVERTISED_FIBRE);
8729                         } else {
8730                                 PMD_DRV_LOG(ERR, sc,
8731                                             "Invalid NVRAM config link_config=0x%08x "
8732                                             "speed_cap_mask=0x%08x",
8733                                             link_config,
8734                                             sc->
8735                                             link_params.speed_cap_mask[idx]);
8736                                 return;
8737                         }
8738                         break;
8739
8740                 case PORT_FEATURE_LINK_SPEED_20G:
8741                         sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8742                         break;
8743
8744                 default:
8745                         PMD_DRV_LOG(ERR, sc,
8746                                     "Invalid NVRAM config link_config=0x%08x "
8747                                     "speed_cap_mask=0x%08x", link_config,
8748                                     sc->link_params.speed_cap_mask[idx]);
8749                         sc->link_params.req_line_speed[idx] =
8750                             ELINK_SPEED_AUTO_NEG;
8751                         sc->port.advertising[idx] = sc->port.supported[idx];
8752                         break;
8753                 }
8754
8755                 sc->link_params.req_flow_ctrl[idx] =
8756                     (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8757
8758                 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8759                         if (!
8760                             (sc->
8761                              port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8762                                 sc->link_params.req_flow_ctrl[idx] =
8763                                     ELINK_FLOW_CTRL_NONE;
8764                         } else {
8765                                 bnx2x_set_requested_fc(sc);
8766                         }
8767                 }
8768         }
8769 }
8770
8771 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8772 {
8773         uint8_t port = SC_PORT(sc);
8774         uint32_t eee_mode;
8775
8776         PMD_INIT_FUNC_TRACE(sc);
8777
8778         /* shmem data already read in bnx2x_get_shmem_info() */
8779
8780         bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8781         bnx2x_link_settings_requested(sc);
8782
8783         /* configure link feature according to nvram value */
8784         eee_mode =
8785             (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8786               & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8787              PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8788         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8789                 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8790                                             ELINK_EEE_MODE_ENABLE_LPI |
8791                                             ELINK_EEE_MODE_OUTPUT_TIME);
8792         } else {
8793                 sc->link_params.eee_mode = 0;
8794         }
8795
8796         /* get the media type */
8797         bnx2x_media_detect(sc);
8798 }
8799
8800 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8801 {
8802         uint32_t flags = MODE_ASIC | MODE_PORT2;
8803
8804         if (CHIP_IS_E2(sc)) {
8805                 flags |= MODE_E2;
8806         } else if (CHIP_IS_E3(sc)) {
8807                 flags |= MODE_E3;
8808                 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8809                         flags |= MODE_E3_A0;
8810                 } else {        /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8811
8812                         flags |= MODE_E3_B0 | MODE_COS3;
8813                 }
8814         }
8815
8816         if (IS_MF(sc)) {
8817                 flags |= MODE_MF;
8818                 switch (sc->devinfo.mf_info.mf_mode) {
8819                 case MULTI_FUNCTION_SD:
8820                         flags |= MODE_MF_SD;
8821                         break;
8822                 case MULTI_FUNCTION_SI:
8823                         flags |= MODE_MF_SI;
8824                         break;
8825                 case MULTI_FUNCTION_AFEX:
8826                         flags |= MODE_MF_AFEX;
8827                         break;
8828                 }
8829         } else {
8830                 flags |= MODE_SF;
8831         }
8832
8833 #if defined(__LITTLE_ENDIAN)
8834         flags |= MODE_LITTLE_ENDIAN;
8835 #else /* __BIG_ENDIAN */
8836         flags |= MODE_BIG_ENDIAN;
8837 #endif
8838
8839         INIT_MODE_FLAGS(sc) = flags;
8840 }
8841
8842 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8843 {
8844         struct bnx2x_fastpath *fp;
8845         char buf[32];
8846         uint32_t i;
8847
8848         if (IS_PF(sc)) {
8849 /************************/
8850 /* DEFAULT STATUS BLOCK */
8851 /************************/
8852
8853                 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8854                                   &sc->def_sb_dma, "def_sb",
8855                                   RTE_CACHE_LINE_SIZE) != 0) {
8856                         return -1;
8857                 }
8858
8859                 sc->def_sb =
8860                     (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8861 /***************/
8862 /* EVENT QUEUE */
8863 /***************/
8864
8865                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8866                                   &sc->eq_dma, "ev_queue",
8867                                   RTE_CACHE_LINE_SIZE) != 0) {
8868                         sc->def_sb = NULL;
8869                         return -1;
8870                 }
8871
8872                 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8873
8874 /*************/
8875 /* SLOW PATH */
8876 /*************/
8877
8878                 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8879                                   &sc->sp_dma, "sp",
8880                                   RTE_CACHE_LINE_SIZE) != 0) {
8881                         sc->eq = NULL;
8882                         sc->def_sb = NULL;
8883                         return -1;
8884                 }
8885
8886                 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8887
8888 /*******************/
8889 /* SLOW PATH QUEUE */
8890 /*******************/
8891
8892                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8893                                   &sc->spq_dma, "sp_queue",
8894                                   RTE_CACHE_LINE_SIZE) != 0) {
8895                         sc->sp = NULL;
8896                         sc->eq = NULL;
8897                         sc->def_sb = NULL;
8898                         return -1;
8899                 }
8900
8901                 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8902
8903 /***************************/
8904 /* FW DECOMPRESSION BUFFER */
8905 /***************************/
8906
8907                 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8908                                   "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8909                         sc->spq = NULL;
8910                         sc->sp = NULL;
8911                         sc->eq = NULL;
8912                         sc->def_sb = NULL;
8913                         return -1;
8914                 }
8915
8916                 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8917         }
8918
8919         /*************/
8920         /* FASTPATHS */
8921         /*************/
8922
8923         /* allocate DMA memory for each fastpath structure */
8924         for (i = 0; i < sc->num_queues; i++) {
8925                 fp = &sc->fp[i];
8926                 fp->sc = sc;
8927                 fp->index = i;
8928
8929 /*******************/
8930 /* FP STATUS BLOCK */
8931 /*******************/
8932
8933                 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8934                 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8935                                   &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8936                         PMD_DRV_LOG(NOTICE, sc, "Failed to alloc %s", buf);
8937                         return -1;
8938                 } else {
8939                         if (CHIP_IS_E2E3(sc)) {
8940                                 fp->status_block.e2_sb =
8941                                     (struct host_hc_status_block_e2 *)
8942                                     fp->sb_dma.vaddr;
8943                         } else {
8944                                 fp->status_block.e1x_sb =
8945                                     (struct host_hc_status_block_e1x *)
8946                                     fp->sb_dma.vaddr;
8947                         }
8948                 }
8949         }
8950
8951         return 0;
8952 }
8953
8954 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8955 {
8956         struct bnx2x_fastpath *fp;
8957         int i;
8958
8959         for (i = 0; i < sc->num_queues; i++) {
8960                 fp = &sc->fp[i];
8961
8962 /*******************/
8963 /* FP STATUS BLOCK */
8964 /*******************/
8965
8966                 memset(&fp->status_block, 0, sizeof(fp->status_block));
8967         }
8968
8969         /***************************/
8970         /* FW DECOMPRESSION BUFFER */
8971         /***************************/
8972
8973         sc->gz_buf = NULL;
8974
8975         /*******************/
8976         /* SLOW PATH QUEUE */
8977         /*******************/
8978
8979         sc->spq = NULL;
8980
8981         /*************/
8982         /* SLOW PATH */
8983         /*************/
8984
8985         sc->sp = NULL;
8986
8987         /***************/
8988         /* EVENT QUEUE */
8989         /***************/
8990
8991         sc->eq = NULL;
8992
8993         /************************/
8994         /* DEFAULT STATUS BLOCK */
8995         /************************/
8996
8997         sc->def_sb = NULL;
8998
8999 }
9000
9001 /*
9002 * Previous driver DMAE transaction may have occurred when pre-boot stage
9003 * ended and boot began. This would invalidate the addresses of the
9004 * transaction, resulting in was-error bit set in the PCI causing all
9005 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
9006 * the interrupt which detected this from the pglueb and the was-done bit
9007 */
9008 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
9009 {
9010         uint32_t val;
9011
9012         if (!CHIP_IS_E1x(sc)) {
9013                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
9014                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9015                         REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9016                                1 << SC_FUNC(sc));
9017                 }
9018         }
9019 }
9020
9021 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9022 {
9023         uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9024                                      DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9025         if (!rc) {
9026                 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9027                 return -1;
9028         }
9029
9030         return 0;
9031 }
9032
9033 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9034 {
9035         struct bnx2x_prev_list_node *tmp;
9036
9037         LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9038                 if ((sc->pcie_bus == tmp->bus) &&
9039                     (sc->pcie_device == tmp->slot) &&
9040                     (SC_PATH(sc) == tmp->path)) {
9041                         return tmp;
9042                 }
9043         }
9044
9045         return NULL;
9046 }
9047
9048 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9049 {
9050         struct bnx2x_prev_list_node *tmp;
9051         int rc = FALSE;
9052
9053         rte_spinlock_lock(&bnx2x_prev_mtx);
9054
9055         tmp = bnx2x_prev_path_get_entry(sc);
9056         if (tmp) {
9057                 if (tmp->aer) {
9058                         PMD_DRV_LOG(DEBUG, sc,
9059                                     "Path %d/%d/%d was marked by AER",
9060                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9061                 } else {
9062                         rc = TRUE;
9063                         PMD_DRV_LOG(DEBUG, sc,
9064                                     "Path %d/%d/%d was already cleaned from previous drivers",
9065                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9066                 }
9067         }
9068
9069         rte_spinlock_unlock(&bnx2x_prev_mtx);
9070
9071         return rc;
9072 }
9073
9074 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9075 {
9076         struct bnx2x_prev_list_node *tmp;
9077
9078         rte_spinlock_lock(&bnx2x_prev_mtx);
9079
9080         /* Check whether the entry for this path already exists */
9081         tmp = bnx2x_prev_path_get_entry(sc);
9082         if (tmp) {
9083                 if (!tmp->aer) {
9084                         PMD_DRV_LOG(DEBUG, sc,
9085                                     "Re-marking AER in path %d/%d/%d",
9086                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9087                 } else {
9088                         PMD_DRV_LOG(DEBUG, sc,
9089                                     "Removing AER indication from path %d/%d/%d",
9090                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9091                         tmp->aer = 0;
9092                 }
9093
9094                 rte_spinlock_unlock(&bnx2x_prev_mtx);
9095                 return 0;
9096         }
9097
9098         rte_spinlock_unlock(&bnx2x_prev_mtx);
9099
9100         /* Create an entry for this path and add it */
9101         tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9102                          RTE_CACHE_LINE_SIZE);
9103         if (!tmp) {
9104                 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate 'bnx2x_prev_list_node'");
9105                 return -1;
9106         }
9107
9108         tmp->bus = sc->pcie_bus;
9109         tmp->slot = sc->pcie_device;
9110         tmp->path = SC_PATH(sc);
9111         tmp->aer = 0;
9112         tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9113
9114         rte_spinlock_lock(&bnx2x_prev_mtx);
9115
9116         LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9117
9118         rte_spinlock_unlock(&bnx2x_prev_mtx);
9119
9120         return 0;
9121 }
9122
9123 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9124 {
9125         int i;
9126
9127         /* only E2 and onwards support FLR */
9128         if (CHIP_IS_E1x(sc)) {
9129                 PMD_DRV_LOG(WARNING, sc, "FLR not supported in E1H");
9130                 return -1;
9131         }
9132
9133         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9134         if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9135                 PMD_DRV_LOG(WARNING, sc,
9136                             "FLR not supported by BC_VER: 0x%08x",
9137                             sc->devinfo.bc_ver);
9138                 return -1;
9139         }
9140
9141         /* Wait for Transaction Pending bit clean */
9142         for (i = 0; i < 4; i++) {
9143                 if (i) {
9144                         DELAY(((1 << (i - 1)) * 100) * 1000);
9145                 }
9146
9147                 if (!bnx2x_is_pcie_pending(sc)) {
9148                         goto clear;
9149                 }
9150         }
9151
9152         PMD_DRV_LOG(NOTICE, sc, "PCIE transaction is not cleared, "
9153                     "proceeding with reset anyway");
9154
9155 clear:
9156         bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9157
9158         return 0;
9159 }
9160
9161 struct bnx2x_mac_vals {
9162         uint32_t xmac_addr;
9163         uint32_t xmac_val;
9164         uint32_t emac_addr;
9165         uint32_t emac_val;
9166         uint32_t umac_addr;
9167         uint32_t umac_val;
9168         uint32_t bmac_addr;
9169         uint32_t bmac_val[2];
9170 };
9171
9172 static void
9173 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9174 {
9175         uint32_t val, base_addr, offset, mask, reset_reg;
9176         uint8_t mac_stopped = FALSE;
9177         uint8_t port = SC_PORT(sc);
9178         uint32_t wb_data[2];
9179
9180         /* reset addresses as they also mark which values were changed */
9181         vals->bmac_addr = 0;
9182         vals->umac_addr = 0;
9183         vals->xmac_addr = 0;
9184         vals->emac_addr = 0;
9185
9186         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9187
9188         if (!CHIP_IS_E3(sc)) {
9189                 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9190                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9191                 if ((mask & reset_reg) && val) {
9192                         base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9193                             : NIG_REG_INGRESS_BMAC0_MEM;
9194                         offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9195                             : BIGMAC_REGISTER_BMAC_CONTROL;
9196
9197                         /*
9198                          * use rd/wr since we cannot use dmae. This is safe
9199                          * since MCP won't access the bus due to the request
9200                          * to unload, and no function on the path can be
9201                          * loaded at this time.
9202                          */
9203                         wb_data[0] = REG_RD(sc, base_addr + offset);
9204                         wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9205                         vals->bmac_addr = base_addr + offset;
9206                         vals->bmac_val[0] = wb_data[0];
9207                         vals->bmac_val[1] = wb_data[1];
9208                         wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9209                         REG_WR(sc, vals->bmac_addr, wb_data[0]);
9210                         REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9211                 }
9212
9213                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9214                 vals->emac_val = REG_RD(sc, vals->emac_addr);
9215                 REG_WR(sc, vals->emac_addr, 0);
9216                 mac_stopped = TRUE;
9217         } else {
9218                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9219                         base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9220                         val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9221                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9222                                val & ~(1 << 1));
9223                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9224                                val | (1 << 1));
9225                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9226                         vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9227                         REG_WR(sc, vals->xmac_addr, 0);
9228                         mac_stopped = TRUE;
9229                 }
9230
9231                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9232                 if (mask & reset_reg) {
9233                         base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9234                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9235                         vals->umac_val = REG_RD(sc, vals->umac_addr);
9236                         REG_WR(sc, vals->umac_addr, 0);
9237                         mac_stopped = TRUE;
9238                 }
9239         }
9240
9241         if (mac_stopped) {
9242                 DELAY(20000);
9243         }
9244 }
9245
9246 #define BNX2X_PREV_UNDI_PROD_ADDR(p)  (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9247 #define BNX2X_PREV_UNDI_RCQ(val)      ((val) & 0xffff)
9248 #define BNX2X_PREV_UNDI_BD(val)       ((val) >> 16 & 0xffff)
9249 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9250
9251 static void
9252 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9253 {
9254         uint16_t rcq, bd;
9255         uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9256
9257         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9258         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9259
9260         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9261         REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9262 }
9263
9264 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9265 {
9266         uint32_t reset_reg, tmp_reg = 0, rc;
9267         uint8_t prev_undi = FALSE;
9268         struct bnx2x_mac_vals mac_vals;
9269         uint32_t timer_count = 1000;
9270         uint32_t prev_brb;
9271
9272         /*
9273          * It is possible a previous function received 'common' answer,
9274          * but hasn't loaded yet, therefore creating a scenario of
9275          * multiple functions receiving 'common' on the same path.
9276          */
9277         memset(&mac_vals, 0, sizeof(mac_vals));
9278
9279         if (bnx2x_prev_is_path_marked(sc)) {
9280                 return bnx2x_prev_mcp_done(sc);
9281         }
9282
9283         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9284
9285         /* Reset should be performed after BRB is emptied */
9286         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9287                 /* Close the MAC Rx to prevent BRB from filling up */
9288                 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9289
9290                 /* close LLH filters towards the BRB */
9291                 elink_set_rx_filter(&sc->link_params, 0);
9292
9293                 /*
9294                  * Check if the UNDI driver was previously loaded.
9295                  * UNDI driver initializes CID offset for normal bell to 0x7
9296                  */
9297                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9298                         tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9299                         if (tmp_reg == 0x7) {
9300                                 PMD_DRV_LOG(DEBUG, sc, "UNDI previously loaded");
9301                                 prev_undi = TRUE;
9302                                 /* clear the UNDI indication */
9303                                 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9304                                 /* clear possible idle check errors */
9305                                 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9306                         }
9307                 }
9308
9309                 /* wait until BRB is empty */
9310                 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9311                 while (timer_count) {
9312                         prev_brb = tmp_reg;
9313
9314                         tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9315                         if (!tmp_reg) {
9316                                 break;
9317                         }
9318
9319                         PMD_DRV_LOG(DEBUG, sc, "BRB still has 0x%08x", tmp_reg);
9320
9321                         /* reset timer as long as BRB actually gets emptied */
9322                         if (prev_brb > tmp_reg) {
9323                                 timer_count = 1000;
9324                         } else {
9325                                 timer_count--;
9326                         }
9327
9328                         /* If UNDI resides in memory, manually increment it */
9329                         if (prev_undi) {
9330                                 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9331                         }
9332
9333                         DELAY(10);
9334                 }
9335
9336                 if (!timer_count) {
9337                         PMD_DRV_LOG(NOTICE, sc, "Failed to empty BRB");
9338                 }
9339         }
9340
9341         /* No packets are in the pipeline, path is ready for reset */
9342         bnx2x_reset_common(sc);
9343
9344         if (mac_vals.xmac_addr) {
9345                 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9346         }
9347         if (mac_vals.umac_addr) {
9348                 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9349         }
9350         if (mac_vals.emac_addr) {
9351                 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9352         }
9353         if (mac_vals.bmac_addr) {
9354                 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9355                 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9356         }
9357
9358         rc = bnx2x_prev_mark_path(sc, prev_undi);
9359         if (rc) {
9360                 bnx2x_prev_mcp_done(sc);
9361                 return rc;
9362         }
9363
9364         return bnx2x_prev_mcp_done(sc);
9365 }
9366
9367 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9368 {
9369         int rc;
9370
9371         /* Test if previous unload process was already finished for this path */
9372         if (bnx2x_prev_is_path_marked(sc)) {
9373                 return bnx2x_prev_mcp_done(sc);
9374         }
9375
9376         /*
9377          * If function has FLR capabilities, and existing FW version matches
9378          * the one required, then FLR will be sufficient to clean any residue
9379          * left by previous driver
9380          */
9381         rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9382         if (!rc) {
9383                 /* fw version is good */
9384                 rc = bnx2x_do_flr(sc);
9385         }
9386
9387         if (!rc) {
9388                 /* FLR was performed */
9389                 return 0;
9390         }
9391
9392         PMD_DRV_LOG(INFO, sc, "Could not FLR");
9393
9394         /* Close the MCP request, return failure */
9395         rc = bnx2x_prev_mcp_done(sc);
9396         if (!rc) {
9397                 rc = BNX2X_PREV_WAIT_NEEDED;
9398         }
9399
9400         return rc;
9401 }
9402
9403 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9404 {
9405         int time_counter = 10;
9406         uint32_t fw, hw_lock_reg, hw_lock_val;
9407         uint32_t rc = 0;
9408
9409         PMD_INIT_FUNC_TRACE(sc);
9410
9411         /*
9412          * Clear HW from errors which may have resulted from an interrupted
9413          * DMAE transaction.
9414          */
9415         bnx2x_prev_interrupted_dmae(sc);
9416
9417         /* Release previously held locks */
9418         hw_lock_reg = (SC_FUNC(sc) <= 5) ?
9419                         (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) :
9420                         (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9421
9422         hw_lock_val = (REG_RD(sc, hw_lock_reg));
9423         if (hw_lock_val) {
9424                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9425                         PMD_DRV_LOG(DEBUG, sc, "Releasing previously held NVRAM lock\n");
9426                         REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9427                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9428                 }
9429                 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held HW lock\n");
9430                 REG_WR(sc, hw_lock_reg, 0xffffffff);
9431         }
9432
9433         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9434                 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held ALR\n");
9435                 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9436         }
9437
9438         do {
9439                 /* Lock MCP using an unload request */
9440                 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9441                 if (!fw) {
9442                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9443                         rc = -1;
9444                         break;
9445                 }
9446
9447                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9448                         rc = bnx2x_prev_unload_common(sc);
9449                         break;
9450                 }
9451
9452                 /* non-common reply from MCP might require looping */
9453                 rc = bnx2x_prev_unload_uncommon(sc);
9454                 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9455                         break;
9456                 }
9457
9458                 DELAY(20000);
9459         } while (--time_counter);
9460
9461         if (!time_counter || rc) {
9462                 PMD_DRV_LOG(NOTICE, sc, "Failed to unload previous driver!");
9463                 rc = -1;
9464         }
9465
9466         return rc;
9467 }
9468
9469 static void
9470 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9471 {
9472         if (!CHIP_IS_E1x(sc)) {
9473                 sc->dcb_state = dcb_on;
9474                 sc->dcbx_enabled = dcbx_enabled;
9475         } else {
9476                 sc->dcb_state = FALSE;
9477                 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9478         }
9479         PMD_DRV_LOG(DEBUG, sc,
9480                     "DCB state [%s:%s]",
9481                     dcb_on ? "ON" : "OFF",
9482                     (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9483                     (dcbx_enabled ==
9484                      BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9485                     : (dcbx_enabled ==
9486                        BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9487                     "on-chip with negotiation" : "invalid");
9488 }
9489
9490 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9491 {
9492         int cid_count = BNX2X_L2_MAX_CID(sc);
9493
9494         if (CNIC_SUPPORT(sc)) {
9495                 cid_count += CNIC_CID_MAX;
9496         }
9497
9498         return roundup(cid_count, QM_CID_ROUND);
9499 }
9500
9501 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9502 {
9503         int pri, cos;
9504
9505         uint32_t pri_map = 0;
9506
9507         for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9508                 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9509                 if (cos < sc->max_cos) {
9510                         sc->prio_to_cos[pri] = cos;
9511                 } else {
9512                         PMD_DRV_LOG(WARNING, sc,
9513                                     "Invalid COS %d for priority %d "
9514                                     "(max COS is %d), setting to 0", cos, pri,
9515                                     (sc->max_cos - 1));
9516                         sc->prio_to_cos[pri] = 0;
9517                 }
9518         }
9519 }
9520
9521 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9522 {
9523         struct {
9524                 uint8_t id;
9525                 uint8_t next;
9526         } pci_cap;
9527         uint16_t status;
9528         struct bnx2x_pci_cap *cap;
9529
9530         cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9531                                          RTE_CACHE_LINE_SIZE);
9532         if (!cap) {
9533                 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9534                 return -ENOMEM;
9535         }
9536
9537 #ifndef __FreeBSD__
9538         pci_read(sc, PCI_STATUS, &status, 2);
9539         if (!(status & PCI_STATUS_CAP_LIST)) {
9540 #else
9541         pci_read(sc, PCIR_STATUS, &status, 2);
9542         if (!(status & PCIM_STATUS_CAPPRESENT)) {
9543 #endif
9544                 PMD_DRV_LOG(NOTICE, sc, "PCIe capability reading failed");
9545                 return -1;
9546         }
9547
9548 #ifndef __FreeBSD__
9549         pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9550 #else
9551         pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9552 #endif
9553         while (pci_cap.next) {
9554                 cap->addr = pci_cap.next & ~3;
9555                 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9556                 if (pci_cap.id == 0xff)
9557                         break;
9558                 cap->id = pci_cap.id;
9559                 cap->type = BNX2X_PCI_CAP;
9560                 cap->next = rte_zmalloc("pci_cap",
9561                                         sizeof(struct bnx2x_pci_cap),
9562                                         RTE_CACHE_LINE_SIZE);
9563                 if (!cap->next) {
9564                         PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9565                         return -ENOMEM;
9566                 }
9567                 cap = cap->next;
9568         }
9569
9570         return 0;
9571 }
9572
9573 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9574 {
9575         if (IS_VF(sc)) {
9576                 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9577                                         sc->igu_sb_cnt);
9578                 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9579                                         sc->igu_sb_cnt);
9580         } else {
9581                 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9582                 sc->max_tx_queues = sc->max_rx_queues;
9583         }
9584 }
9585
9586 #define FW_HEADER_LEN 104
9587 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9588 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9589
9590 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9591 {
9592         const char *fwname;
9593         int f;
9594         struct stat st;
9595
9596         fwname = sc->devinfo.device_id == CHIP_NUM_57711
9597                 ? FW_NAME_57711 : FW_NAME_57810;
9598         f = open(fwname, O_RDONLY);
9599         if (f < 0) {
9600                 PMD_DRV_LOG(NOTICE, sc, "Can't open firmware file");
9601                 return;
9602         }
9603
9604         if (fstat(f, &st) < 0) {
9605                 PMD_DRV_LOG(NOTICE, sc, "Can't stat firmware file");
9606                 close(f);
9607                 return;
9608         }
9609
9610         sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9611         if (!sc->firmware) {
9612                 PMD_DRV_LOG(NOTICE, sc, "Can't allocate memory for firmware");
9613                 close(f);
9614                 return;
9615         }
9616
9617         if (read(f, sc->firmware, st.st_size) != st.st_size) {
9618                 PMD_DRV_LOG(NOTICE, sc, "Can't read firmware data");
9619                 close(f);
9620                 return;
9621         }
9622         close(f);
9623
9624         sc->fw_len = st.st_size;
9625         if (sc->fw_len < FW_HEADER_LEN) {
9626                 PMD_DRV_LOG(NOTICE, sc,
9627                             "Invalid fw size: %" PRIu64, sc->fw_len);
9628                 return;
9629         }
9630         PMD_DRV_LOG(DEBUG, sc, "fw_len = %" PRIu64, sc->fw_len);
9631 }
9632
9633 static void
9634 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9635 {
9636         uint32_t *src = (uint32_t *) data;
9637         uint32_t i, j, tmp;
9638
9639         for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9640                 tmp = rte_be_to_cpu_32(src[j]);
9641                 dst[i].op = (tmp >> 24) & 0xFF;
9642                 dst[i].offset = tmp & 0xFFFFFF;
9643                 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9644         }
9645 }
9646
9647 static void
9648 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9649 {
9650         uint16_t *src = (uint16_t *) data;
9651         uint32_t i;
9652
9653         for (i = 0; i < len / 2; ++i)
9654                 dst[i] = rte_be_to_cpu_16(src[i]);
9655 }
9656
9657 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9658 {
9659         uint32_t *src = (uint32_t *) data;
9660         uint32_t i;
9661
9662         for (i = 0; i < len / 4; ++i)
9663                 dst[i] = rte_be_to_cpu_32(src[i]);
9664 }
9665
9666 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9667 {
9668         uint32_t *src = (uint32_t *) data;
9669         uint32_t i, j, tmp;
9670
9671         for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9672                 dst[i].base = rte_be_to_cpu_32(src[j++]);
9673                 tmp = rte_be_to_cpu_32(src[j]);
9674                 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9675                 dst[i].m2 = tmp & 0xFFFF;
9676                 ++j;
9677                 tmp = rte_be_to_cpu_32(src[j]);
9678                 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9679                 dst[i].size = tmp & 0xFFFF;
9680         }
9681 }
9682
9683 /*
9684 * Device attach function.
9685 *
9686 * Allocates device resources, performs secondary chip identification, and
9687 * initializes driver instance variables. This function is called from driver
9688 * load after a successful probe.
9689 *
9690 * Returns:
9691 *   0 = Success, >0 = Failure
9692 */
9693 int bnx2x_attach(struct bnx2x_softc *sc)
9694 {
9695         int rc;
9696
9697         PMD_DRV_LOG(DEBUG, sc, "Starting attach...");
9698
9699         rc = bnx2x_pci_get_caps(sc);
9700         if (rc) {
9701                 PMD_DRV_LOG(NOTICE, sc, "PCIe caps reading was failed");
9702                 return rc;
9703         }
9704
9705         sc->state = BNX2X_STATE_CLOSED;
9706
9707         pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9708
9709         sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9710
9711         /* get PCI capabilites */
9712         bnx2x_probe_pci_caps(sc);
9713
9714         if (sc->devinfo.pcie_msix_cap_reg != 0) {
9715                 uint32_t val;
9716                 pci_read(sc,
9717                          (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9718                          2);
9719                 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9720         } else {
9721                 sc->igu_sb_cnt = 1;
9722         }
9723
9724         /* Init RTE stuff */
9725         bnx2x_init_rte(sc);
9726
9727         if (IS_PF(sc)) {
9728                 /* Enable internal target-read (in case we are probed after PF
9729                  * FLR). Must be done prior to any BAR read access. Only for
9730                  * 57712 and up
9731                  */
9732                 if (!CHIP_IS_E1x(sc)) {
9733                         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9734                                1);
9735                         DELAY(200000);
9736                 }
9737
9738                 /* get device info and set params */
9739                 if (bnx2x_get_device_info(sc) != 0) {
9740                         PMD_DRV_LOG(NOTICE, sc, "getting device info");
9741                         return -ENXIO;
9742                 }
9743
9744 /* get phy settings from shmem and 'and' against admin settings */
9745                 bnx2x_get_phy_info(sc);
9746         } else {
9747                 /* Left mac of VF unfilled, PF should set it for VF */
9748                 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9749         }
9750
9751         sc->wol = 0;
9752
9753         /* set the default MTU (changed via ifconfig) */
9754         sc->mtu = ETHER_MTU;
9755
9756         bnx2x_set_modes_bitmap(sc);
9757
9758         /* need to reset chip if UNDI was active */
9759         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9760 /* init fw_seq */
9761                 sc->fw_seq =
9762                     (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9763                      DRV_MSG_SEQ_NUMBER_MASK);
9764                 PMD_DRV_LOG(DEBUG, sc, "prev unload fw_seq 0x%04x",
9765                             sc->fw_seq);
9766                 bnx2x_prev_unload(sc);
9767         }
9768
9769         bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9770
9771         /* calculate qm_cid_count */
9772         sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9773
9774         sc->max_cos = 1;
9775         bnx2x_init_multi_cos(sc);
9776
9777         return 0;
9778 }
9779
9780 static void
9781 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9782                uint16_t index, uint8_t op, uint8_t update)
9783 {
9784         uint32_t igu_addr = sc->igu_base_addr;
9785         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9786         bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9787 }
9788
9789 static void
9790 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9791            uint16_t index, uint8_t op, uint8_t update)
9792 {
9793         if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9794                 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9795         else {
9796                 uint8_t segment;
9797                 if (CHIP_INT_MODE_IS_BC(sc)) {
9798                         segment = storm;
9799                 } else if (igu_sb_id != sc->igu_dsb_id) {
9800                         segment = IGU_SEG_ACCESS_DEF;
9801                 } else if (storm == ATTENTION_ID) {
9802                         segment = IGU_SEG_ACCESS_ATTN;
9803                 } else {
9804                         segment = IGU_SEG_ACCESS_DEF;
9805                 }
9806                 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9807         }
9808 }
9809
9810 static void
9811 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9812                      uint8_t is_pf)
9813 {
9814         uint32_t data, ctl, cnt = 100;
9815         uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9816         uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9817         uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9818             (idu_sb_id / 32) * 4;
9819         uint32_t sb_bit = 1 << (idu_sb_id % 32);
9820         uint32_t func_encode = func |
9821             (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9822         uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9823
9824         /* Not supported in BC mode */
9825         if (CHIP_INT_MODE_IS_BC(sc)) {
9826                 return;
9827         }
9828
9829         data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9830                  IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9831                 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9832
9833         ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9834                (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9835                (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9836
9837         REG_WR(sc, igu_addr_data, data);
9838
9839         mb();
9840
9841         PMD_DRV_LOG(DEBUG, sc, "write 0x%08x to IGU(via GRC) addr 0x%x",
9842                     ctl, igu_addr_ctl);
9843         REG_WR(sc, igu_addr_ctl, ctl);
9844
9845         mb();
9846
9847         /* wait for clean up to finish */
9848         while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9849                 DELAY(20000);
9850         }
9851
9852         if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9853                 PMD_DRV_LOG(DEBUG, sc,
9854                             "Unable to finish IGU cleanup: "
9855                             "idu_sb_id %d offset %d bit %d (cnt %d)",
9856                             idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9857         }
9858 }
9859
9860 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9861 {
9862         bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9863 }
9864
9865 /*******************/
9866 /* ECORE CALLBACKS */
9867 /*******************/
9868
9869 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9870 {
9871         uint32_t val = 0x1400;
9872
9873         PMD_INIT_FUNC_TRACE(sc);
9874
9875         /* reset_common */
9876         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9877                0xd3ffff7f);
9878
9879         if (CHIP_IS_E3(sc)) {
9880                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9881                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9882         }
9883
9884         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9885 }
9886
9887 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9888 {
9889         uint32_t shmem_base[2];
9890         uint32_t shmem2_base[2];
9891
9892         /* Avoid common init in case MFW supports LFA */
9893         if (SHMEM2_RD(sc, size) >
9894             (uint32_t) offsetof(struct shmem2_region,
9895                                 lfa_host_addr[SC_PORT(sc)])) {
9896                 return;
9897         }
9898
9899         shmem_base[0] = sc->devinfo.shmem_base;
9900         shmem2_base[0] = sc->devinfo.shmem2_base;
9901
9902         if (!CHIP_IS_E1x(sc)) {
9903                 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9904                 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9905         }
9906
9907         bnx2x_acquire_phy_lock(sc);
9908         elink_common_init_phy(sc, shmem_base, shmem2_base,
9909                               sc->devinfo.chip_id, 0);
9910         bnx2x_release_phy_lock(sc);
9911 }
9912
9913 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9914 {
9915         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9916
9917         val &= ~IGU_PF_CONF_FUNC_EN;
9918
9919         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9920         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9921         REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9922 }
9923
9924 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9925 {
9926         uint16_t devctl;
9927         int r_order, w_order;
9928
9929         devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9930
9931         w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9932         r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9933
9934         ecore_init_pxp_arb(sc, r_order, w_order);
9935 }
9936
9937 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9938 {
9939         uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9940         uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9941         return base + (SC_ABS_FUNC(sc)) * stride;
9942 }
9943
9944 /*
9945  * Called only on E1H or E2.
9946  * When pretending to be PF, the pretend value is the function number 0..7.
9947  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9948  * combination.
9949  */
9950 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9951 {
9952         uint32_t pretend_reg;
9953
9954         if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9955                 return -1;
9956
9957         /* get my own pretend register */
9958         pretend_reg = bnx2x_get_pretend_reg(sc);
9959         REG_WR(sc, pretend_reg, pretend_func_val);
9960         REG_RD(sc, pretend_reg);
9961         return 0;
9962 }
9963
9964 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9965 {
9966         int is_required;
9967         uint32_t val;
9968         int port;
9969
9970         is_required = 0;
9971         val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9972                SHARED_HW_CFG_FAN_FAILURE_MASK);
9973
9974         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9975                 is_required = 1;
9976         }
9977         /*
9978          * The fan failure mechanism is usually related to the PHY type since
9979          * the power consumption of the board is affected by the PHY. Currently,
9980          * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9981          */
9982         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9983                 for (port = PORT_0; port < PORT_MAX; port++) {
9984                         is_required |= elink_fan_failure_det_req(sc,
9985                                                                  sc->
9986                                                                  devinfo.shmem_base,
9987                                                                  sc->
9988                                                                  devinfo.shmem2_base,
9989                                                                  port);
9990                 }
9991         }
9992
9993         if (is_required == 0) {
9994                 return;
9995         }
9996
9997         /* Fan failure is indicated by SPIO 5 */
9998         bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9999
10000         /* set to active low mode */
10001         val = REG_RD(sc, MISC_REG_SPIO_INT);
10002         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
10003         REG_WR(sc, MISC_REG_SPIO_INT, val);
10004
10005         /* enable interrupt to signal the IGU */
10006         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10007         val |= MISC_SPIO_SPIO5;
10008         REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
10009 }
10010
10011 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
10012 {
10013         uint32_t val;
10014
10015         REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
10016         if (!CHIP_IS_E1x(sc)) {
10017                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
10018         } else {
10019                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
10020         }
10021         REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10022         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10023         /*
10024          * mask read length error interrupts in brb for parser
10025          * (parsing unit and 'checksum and crc' unit)
10026          * these errors are legal (PU reads fixed length and CAC can cause
10027          * read length error on truncated packets)
10028          */
10029         REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
10030         REG_WR(sc, QM_REG_QM_INT_MASK, 0);
10031         REG_WR(sc, TM_REG_TM_INT_MASK, 0);
10032         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
10033         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
10034         REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
10035         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
10036         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
10037         REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
10038         REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10039         REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10040         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10041         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10042         REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10043         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10044         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10045         REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10046         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10047         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10048
10049         val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10050                PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10051                PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10052         if (!CHIP_IS_E1x(sc)) {
10053                 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10054                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10055         }
10056         REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10057
10058         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10059         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10060         REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10061         /*      REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10062
10063         if (!CHIP_IS_E1x(sc)) {
10064 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10065                 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10066         }
10067
10068         REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10069         REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10070         /*      REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10071         REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10072 }
10073
10074 /**
10075  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10076  *
10077  * @sc:     driver handle
10078  */
10079 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10080 {
10081         uint8_t abs_func_id;
10082         uint32_t val;
10083
10084         PMD_DRV_LOG(DEBUG, sc,
10085                     "starting common init for func %d", SC_ABS_FUNC(sc));
10086
10087         /*
10088          * take the RESET lock to protect undi_unload flow from accessing
10089          * registers while we are resetting the chip
10090          */
10091         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10092
10093         bnx2x_reset_common(sc);
10094
10095         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10096
10097         val = 0xfffc;
10098         if (CHIP_IS_E3(sc)) {
10099                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10100                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10101         }
10102
10103         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10104
10105         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10106
10107         ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10108
10109         if (!CHIP_IS_E1x(sc)) {
10110 /*
10111  * 4-port mode or 2-port mode we need to turn off master-enable for
10112  * everyone. After that we turn it back on for self. So, we disregard
10113  * multi-function, and always disable all functions on the given path,
10114  * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10115  */
10116                 for (abs_func_id = SC_PATH(sc);
10117                      abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10118                         if (abs_func_id == SC_ABS_FUNC(sc)) {
10119                                 REG_WR(sc,
10120                                        PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10121                                        1);
10122                                 continue;
10123                         }
10124
10125                         bnx2x_pretend_func(sc, abs_func_id);
10126
10127                         /* clear pf enable */
10128                         bnx2x_pf_disable(sc);
10129
10130                         bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10131                 }
10132         }
10133
10134         ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10135
10136         ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10137         bnx2x_init_pxp(sc);
10138
10139 #ifdef __BIG_ENDIAN
10140         REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10141         REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10142         REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10143         REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10144         REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10145         /* make sure this value is 0 */
10146         REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10147
10148         //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10149         REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10150         REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10151         REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10152         REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10153 #endif
10154
10155         ecore_ilt_init_page_size(sc, INITOP_SET);
10156
10157         if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10158                 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10159         }
10160
10161         /* let the HW do it's magic... */
10162         DELAY(100000);
10163
10164         /* finish PXP init */
10165
10166         val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10167         if (val != 1) {
10168                 PMD_DRV_LOG(NOTICE, sc, "PXP2 CFG failed");
10169                 return -1;
10170         }
10171         val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10172         if (val != 1) {
10173                 PMD_DRV_LOG(NOTICE, sc, "PXP2 RD_INIT failed");
10174                 return -1;
10175         }
10176
10177         /*
10178          * Timer bug workaround for E2 only. We need to set the entire ILT to have
10179          * entries with value "0" and valid bit on. This needs to be done by the
10180          * first PF that is loaded in a path (i.e. common phase)
10181          */
10182         if (!CHIP_IS_E1x(sc)) {
10183 /*
10184  * In E2 there is a bug in the timers block that can cause function 6 / 7
10185  * (i.e. vnic3) to start even if it is marked as "scan-off".
10186  * This occurs when a different function (func2,3) is being marked
10187  * as "scan-off". Real-life scenario for example: if a driver is being
10188  * load-unloaded while func6,7 are down. This will cause the timer to access
10189  * the ilt, translate to a logical address and send a request to read/write.
10190  * Since the ilt for the function that is down is not valid, this will cause
10191  * a translation error which is unrecoverable.
10192  * The Workaround is intended to make sure that when this happens nothing
10193  * fatal will occur. The workaround:
10194  *  1.  First PF driver which loads on a path will:
10195  *      a.  After taking the chip out of reset, by using pretend,
10196  *          it will write "0" to the following registers of
10197  *          the other vnics.
10198  *          REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10199  *          REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10200  *          REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10201  *          And for itself it will write '1' to
10202  *          PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10203  *          dmae-operations (writing to pram for example.)
10204  *          note: can be done for only function 6,7 but cleaner this
10205  *            way.
10206  *      b.  Write zero+valid to the entire ILT.
10207  *      c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
10208  *          VNIC3 (of that port). The range allocated will be the
10209  *          entire ILT. This is needed to prevent  ILT range error.
10210  *  2.  Any PF driver load flow:
10211  *      a.  ILT update with the physical addresses of the allocated
10212  *          logical pages.
10213  *      b.  Wait 20msec. - note that this timeout is needed to make
10214  *          sure there are no requests in one of the PXP internal
10215  *          queues with "old" ILT addresses.
10216  *      c.  PF enable in the PGLC.
10217  *      d.  Clear the was_error of the PF in the PGLC. (could have
10218  *          occurred while driver was down)
10219  *      e.  PF enable in the CFC (WEAK + STRONG)
10220  *      f.  Timers scan enable
10221  *  3.  PF driver unload flow:
10222  *      a.  Clear the Timers scan_en.
10223  *      b.  Polling for scan_on=0 for that PF.
10224  *      c.  Clear the PF enable bit in the PXP.
10225  *      d.  Clear the PF enable in the CFC (WEAK + STRONG)
10226  *      e.  Write zero+valid to all ILT entries (The valid bit must
10227  *          stay set)
10228  *      f.  If this is VNIC 3 of a port then also init
10229  *          first_timers_ilt_entry to zero and last_timers_ilt_entry
10230  *          to the last enrty in the ILT.
10231  *
10232  *      Notes:
10233  *      Currently the PF error in the PGLC is non recoverable.
10234  *      In the future the there will be a recovery routine for this error.
10235  *      Currently attention is masked.
10236  *      Having an MCP lock on the load/unload process does not guarantee that
10237  *      there is no Timer disable during Func6/7 enable. This is because the
10238  *      Timers scan is currently being cleared by the MCP on FLR.
10239  *      Step 2.d can be done only for PF6/7 and the driver can also check if
10240  *      there is error before clearing it. But the flow above is simpler and
10241  *      more general.
10242  *      All ILT entries are written by zero+valid and not just PF6/7
10243  *      ILT entries since in the future the ILT entries allocation for
10244  *      PF-s might be dynamic.
10245  */
10246                 struct ilt_client_info ilt_cli;
10247                 struct ecore_ilt ilt;
10248
10249                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10250                 memset(&ilt, 0, sizeof(struct ecore_ilt));
10251
10252 /* initialize dummy TM client */
10253                 ilt_cli.start = 0;
10254                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10255                 ilt_cli.client_num = ILT_CLIENT_TM;
10256
10257 /*
10258  * Step 1: set zeroes to all ilt page entries with valid bit on
10259  * Step 2: set the timers first/last ilt entry to point
10260  * to the entire range to prevent ILT range error for 3rd/4th
10261  * vnic (this code assumes existence of the vnic)
10262  *
10263  * both steps performed by call to ecore_ilt_client_init_op()
10264  * with dummy TM client
10265  *
10266  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10267  * and his brother are split registers
10268  */
10269
10270                 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10271                 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10272                 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10273
10274                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10275                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10276                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10277         }
10278
10279         REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10280         REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10281
10282         if (!CHIP_IS_E1x(sc)) {
10283                 int factor = 0;
10284
10285                 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10286                 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10287
10288 /* let the HW do it's magic... */
10289                 do {
10290                         DELAY(200000);
10291                         val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10292                 } while (factor-- && (val != 1));
10293
10294                 if (val != 1) {
10295                         PMD_DRV_LOG(NOTICE, sc, "ATC_INIT failed");
10296                         return -1;
10297                 }
10298         }
10299
10300         ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10301
10302         /* clean the DMAE memory */
10303         sc->dmae_ready = 1;
10304         ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10305
10306         ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10307
10308         ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10309
10310         ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10311
10312         ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10313
10314         bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10315         bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10316         bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10317         bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10318
10319         ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10320
10321         /* QM queues pointers table */
10322         ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10323
10324         /* soft reset pulse */
10325         REG_WR(sc, QM_REG_SOFT_RESET, 1);
10326         REG_WR(sc, QM_REG_SOFT_RESET, 0);
10327
10328         if (CNIC_SUPPORT(sc))
10329                 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10330
10331         ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10332         REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10333
10334         if (!CHIP_REV_IS_SLOW(sc)) {
10335 /* enable hw interrupt from doorbell Q */
10336                 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10337         }
10338
10339         ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10340
10341         ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10342         REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10343         REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10344
10345         if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10346                 if (IS_MF_AFEX(sc)) {
10347                         /*
10348                          * configure that AFEX and VLAN headers must be
10349                          * received in AFEX mode
10350                          */
10351                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10352                         REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10353                         REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10354                         REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10355                         REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10356                 } else {
10357                         /*
10358                          * Bit-map indicating which L2 hdrs may appear
10359                          * after the basic Ethernet header
10360                          */
10361                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10362                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10363                 }
10364         }
10365
10366         ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10367         ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10368         ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10369         ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10370
10371         if (!CHIP_IS_E1x(sc)) {
10372 /* reset VFC memories */
10373                 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10374                        VFC_MEMORIES_RST_REG_CAM_RST |
10375                        VFC_MEMORIES_RST_REG_RAM_RST);
10376                 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10377                        VFC_MEMORIES_RST_REG_CAM_RST |
10378                        VFC_MEMORIES_RST_REG_RAM_RST);
10379
10380                 DELAY(20000);
10381         }
10382
10383         ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10384         ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10385         ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10386         ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10387
10388         /* sync semi rtc */
10389         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10390         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10391
10392         ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10393         ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10394         ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10395
10396         if (!CHIP_IS_E1x(sc)) {
10397                 if (IS_MF_AFEX(sc)) {
10398                         /*
10399                          * configure that AFEX and VLAN headers must be
10400                          * sent in AFEX mode
10401                          */
10402                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10403                         REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10404                         REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10405                         REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10406                         REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10407                 } else {
10408                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10409                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10410                 }
10411         }
10412
10413         REG_WR(sc, SRC_REG_SOFT_RST, 1);
10414
10415         ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10416
10417         if (CNIC_SUPPORT(sc)) {
10418                 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10419                 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10420                 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10421                 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10422                 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10423                 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10424                 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10425                 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10426                 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10427                 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10428         }
10429         REG_WR(sc, SRC_REG_SOFT_RST, 0);
10430
10431         if (sizeof(union cdu_context) != 1024) {
10432 /* we currently assume that a context is 1024 bytes */
10433                 PMD_DRV_LOG(NOTICE, sc,
10434                             "please adjust the size of cdu_context(%ld)",
10435                             (long)sizeof(union cdu_context));
10436         }
10437
10438         ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10439         val = (4 << 24) + (0 << 12) + 1024;
10440         REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10441
10442         ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10443
10444         REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10445         /* enable context validation interrupt from CFC */
10446         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10447
10448         /* set the thresholds to prevent CFC/CDU race */
10449         REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10450         ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10451
10452         if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10453                 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10454         }
10455
10456         ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10457         ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10458
10459         /* Reset PCIE errors for debug */
10460         REG_WR(sc, 0x2814, 0xffffffff);
10461         REG_WR(sc, 0x3820, 0xffffffff);
10462
10463         if (!CHIP_IS_E1x(sc)) {
10464                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10465                        (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10466                         PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10467                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10468                        (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10469                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10470                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10471                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10472                        (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10473                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10474                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10475         }
10476
10477         ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10478
10479         /* in E3 this done in per-port section */
10480         if (!CHIP_IS_E3(sc))
10481                 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10482
10483         if (CHIP_IS_E1H(sc)) {
10484 /* not applicable for E2 (and above ...) */
10485                 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10486         }
10487
10488         if (CHIP_REV_IS_SLOW(sc)) {
10489                 DELAY(200000);
10490         }
10491
10492         /* finish CFC init */
10493         val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10494         if (val != 1) {
10495                 PMD_DRV_LOG(NOTICE, sc, "CFC LL_INIT failed");
10496                 return -1;
10497         }
10498         val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10499         if (val != 1) {
10500                 PMD_DRV_LOG(NOTICE, sc, "CFC AC_INIT failed");
10501                 return -1;
10502         }
10503         val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10504         if (val != 1) {
10505                 PMD_DRV_LOG(NOTICE, sc, "CFC CAM_INIT failed");
10506                 return -1;
10507         }
10508         REG_WR(sc, CFC_REG_DEBUG0, 0);
10509
10510         bnx2x_setup_fan_failure_detection(sc);
10511
10512         /* clear PXP2 attentions */
10513         REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10514
10515         bnx2x_enable_blocks_attention(sc);
10516
10517         if (!CHIP_REV_IS_SLOW(sc)) {
10518                 ecore_enable_blocks_parity(sc);
10519         }
10520
10521         if (!BNX2X_NOMCP(sc)) {
10522                 if (CHIP_IS_E1x(sc)) {
10523                         bnx2x_common_init_phy(sc);
10524                 }
10525         }
10526
10527         return 0;
10528 }
10529
10530 /**
10531  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10532  *
10533  * @sc:     driver handle
10534  */
10535 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10536 {
10537         int rc = bnx2x_init_hw_common(sc);
10538
10539         if (rc) {
10540                 return rc;
10541         }
10542
10543         /* In E2 2-PORT mode, same ext phy is used for the two paths */
10544         if (!BNX2X_NOMCP(sc)) {
10545                 bnx2x_common_init_phy(sc);
10546         }
10547
10548         return 0;
10549 }
10550
10551 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10552 {
10553         int port = SC_PORT(sc);
10554         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10555         uint32_t low, high;
10556         uint32_t val;
10557
10558         PMD_DRV_LOG(DEBUG, sc, "starting port init for port %d", port);
10559
10560         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10561
10562         ecore_init_block(sc, BLOCK_MISC, init_phase);
10563         ecore_init_block(sc, BLOCK_PXP, init_phase);
10564         ecore_init_block(sc, BLOCK_PXP2, init_phase);
10565
10566         /*
10567          * Timers bug workaround: disables the pf_master bit in pglue at
10568          * common phase, we need to enable it here before any dmae access are
10569          * attempted. Therefore we manually added the enable-master to the
10570          * port phase (it also happens in the function phase)
10571          */
10572         if (!CHIP_IS_E1x(sc)) {
10573                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10574         }
10575
10576         ecore_init_block(sc, BLOCK_ATC, init_phase);
10577         ecore_init_block(sc, BLOCK_DMAE, init_phase);
10578         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10579         ecore_init_block(sc, BLOCK_QM, init_phase);
10580
10581         ecore_init_block(sc, BLOCK_TCM, init_phase);
10582         ecore_init_block(sc, BLOCK_UCM, init_phase);
10583         ecore_init_block(sc, BLOCK_CCM, init_phase);
10584         ecore_init_block(sc, BLOCK_XCM, init_phase);
10585
10586         /* QM cid (connection) count */
10587         ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10588
10589         if (CNIC_SUPPORT(sc)) {
10590                 ecore_init_block(sc, BLOCK_TM, init_phase);
10591                 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10592                 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10593         }
10594
10595         ecore_init_block(sc, BLOCK_DORQ, init_phase);
10596
10597         ecore_init_block(sc, BLOCK_BRB1, init_phase);
10598
10599         if (CHIP_IS_E1H(sc)) {
10600                 if (IS_MF(sc)) {
10601                         low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10602                 } else if (sc->mtu > 4096) {
10603                         if (BNX2X_ONE_PORT(sc)) {
10604                                 low = 160;
10605                         } else {
10606                                 val = sc->mtu;
10607                                 /* (24*1024 + val*4)/256 */
10608                                 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10609                         }
10610                 } else {
10611                         low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10612                 }
10613                 high = (low + 56);      /* 14*1024/256 */
10614                 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10615                 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10616         }
10617
10618         if (CHIP_IS_MODE_4_PORT(sc)) {
10619                 REG_WR(sc, SC_PORT(sc) ?
10620                        BRB1_REG_MAC_GUARANTIED_1 :
10621                        BRB1_REG_MAC_GUARANTIED_0, 40);
10622         }
10623
10624         ecore_init_block(sc, BLOCK_PRS, init_phase);
10625         if (CHIP_IS_E3B0(sc)) {
10626                 if (IS_MF_AFEX(sc)) {
10627                         /* configure headers for AFEX mode */
10628                         if (SC_PORT(sc)) {
10629                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10630                                        0xE);
10631                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10632                                        0x6);
10633                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10634                         } else {
10635                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10636                                        0xE);
10637                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10638                                        0x6);
10639                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10640                         }
10641                 } else {
10642                         /* Ovlan exists only if we are in multi-function +
10643                          * switch-dependent mode, in switch-independent there
10644                          * is no ovlan headers
10645                          */
10646                         REG_WR(sc, SC_PORT(sc) ?
10647                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10648                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10649                                (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10650                 }
10651         }
10652
10653         ecore_init_block(sc, BLOCK_TSDM, init_phase);
10654         ecore_init_block(sc, BLOCK_CSDM, init_phase);
10655         ecore_init_block(sc, BLOCK_USDM, init_phase);
10656         ecore_init_block(sc, BLOCK_XSDM, init_phase);
10657
10658         ecore_init_block(sc, BLOCK_TSEM, init_phase);
10659         ecore_init_block(sc, BLOCK_USEM, init_phase);
10660         ecore_init_block(sc, BLOCK_CSEM, init_phase);
10661         ecore_init_block(sc, BLOCK_XSEM, init_phase);
10662
10663         ecore_init_block(sc, BLOCK_UPB, init_phase);
10664         ecore_init_block(sc, BLOCK_XPB, init_phase);
10665
10666         ecore_init_block(sc, BLOCK_PBF, init_phase);
10667
10668         if (CHIP_IS_E1x(sc)) {
10669 /* configure PBF to work without PAUSE mtu 9000 */
10670                 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10671
10672 /* update threshold */
10673                 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10674 /* update init credit */
10675                 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10676                        (9040 / 16) + 553 - 22);
10677
10678 /* probe changes */
10679                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10680                 DELAY(50);
10681                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10682         }
10683
10684         if (CNIC_SUPPORT(sc)) {
10685                 ecore_init_block(sc, BLOCK_SRC, init_phase);
10686         }
10687
10688         ecore_init_block(sc, BLOCK_CDU, init_phase);
10689         ecore_init_block(sc, BLOCK_CFC, init_phase);
10690         ecore_init_block(sc, BLOCK_HC, init_phase);
10691         ecore_init_block(sc, BLOCK_IGU, init_phase);
10692         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10693         /* init aeu_mask_attn_func_0/1:
10694          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10695          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10696          *             bits 4-7 are used for "per vn group attention" */
10697         val = IS_MF(sc) ? 0xF7 : 0x7;
10698         val |= 0x10;
10699         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10700
10701         ecore_init_block(sc, BLOCK_NIG, init_phase);
10702
10703         if (!CHIP_IS_E1x(sc)) {
10704 /* Bit-map indicating which L2 hdrs may appear after the
10705  * basic Ethernet header
10706  */
10707                 if (IS_MF_AFEX(sc)) {
10708                         REG_WR(sc, SC_PORT(sc) ?
10709                                NIG_REG_P1_HDRS_AFTER_BASIC :
10710                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10711                 } else {
10712                         REG_WR(sc, SC_PORT(sc) ?
10713                                NIG_REG_P1_HDRS_AFTER_BASIC :
10714                                NIG_REG_P0_HDRS_AFTER_BASIC,
10715                                IS_MF_SD(sc) ? 7 : 6);
10716                 }
10717
10718                 if (CHIP_IS_E3(sc)) {
10719                         REG_WR(sc, SC_PORT(sc) ?
10720                                NIG_REG_LLH1_MF_MODE :
10721                                NIG_REG_LLH_MF_MODE, IS_MF(sc));
10722                 }
10723         }
10724         if (!CHIP_IS_E3(sc)) {
10725                 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10726         }
10727
10728         /* 0x2 disable mf_ov, 0x1 enable */
10729         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10730                (IS_MF_SD(sc) ? 0x1 : 0x2));
10731
10732         if (!CHIP_IS_E1x(sc)) {
10733                 val = 0;
10734                 switch (sc->devinfo.mf_info.mf_mode) {
10735                 case MULTI_FUNCTION_SD:
10736                         val = 1;
10737                         break;
10738                 case MULTI_FUNCTION_SI:
10739                 case MULTI_FUNCTION_AFEX:
10740                         val = 2;
10741                         break;
10742                 }
10743
10744                 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10745                             NIG_REG_LLH0_CLS_TYPE), val);
10746         }
10747         REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10748         REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10749         REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10750
10751         /* If SPIO5 is set to generate interrupts, enable it for this port */
10752         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10753         if (val & MISC_SPIO_SPIO5) {
10754                 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10755                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10756                 val = REG_RD(sc, reg_addr);
10757                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10758                 REG_WR(sc, reg_addr, val);
10759         }
10760
10761         return 0;
10762 }
10763
10764 static uint32_t
10765 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10766                        uint32_t expected, uint32_t poll_count)
10767 {
10768         uint32_t cur_cnt = poll_count;
10769         uint32_t val;
10770
10771         while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10772                 DELAY(FLR_WAIT_INTERVAL);
10773         }
10774
10775         return val;
10776 }
10777
10778 static int
10779 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10780                               __rte_unused const char *msg, uint32_t poll_cnt)
10781 {
10782         uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10783
10784         if (val != 0) {
10785                 PMD_DRV_LOG(NOTICE, sc, "%s usage count=%d", msg, val);
10786                 return -1;
10787         }
10788
10789         return 0;
10790 }
10791
10792 /* Common routines with VF FLR cleanup */
10793 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10794 {
10795         /* adjust polling timeout */
10796         if (CHIP_REV_IS_EMUL(sc)) {
10797                 return FLR_POLL_CNT * 2000;
10798         }
10799
10800         if (CHIP_REV_IS_FPGA(sc)) {
10801                 return FLR_POLL_CNT * 120;
10802         }
10803
10804         return FLR_POLL_CNT;
10805 }
10806
10807 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10808 {
10809         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10810         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10811                                           CFC_REG_NUM_LCIDS_INSIDE_PF,
10812                                           "CFC PF usage counter timed out",
10813                                           poll_cnt)) {
10814                 return -1;
10815         }
10816
10817         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10818         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10819                                           DORQ_REG_PF_USAGE_CNT,
10820                                           "DQ PF usage counter timed out",
10821                                           poll_cnt)) {
10822                 return -1;
10823         }
10824
10825         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10826         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10827                                           QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10828                                           "QM PF usage counter timed out",
10829                                           poll_cnt)) {
10830                 return -1;
10831         }
10832
10833         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10834         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10835                                           TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10836                                           "Timers VNIC usage counter timed out",
10837                                           poll_cnt)) {
10838                 return -1;
10839         }
10840
10841         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10842                                           TM_REG_LIN0_NUM_SCANS +
10843                                           4 * SC_PORT(sc),
10844                                           "Timers NUM_SCANS usage counter timed out",
10845                                           poll_cnt)) {
10846                 return -1;
10847         }
10848
10849         /* Wait DMAE PF usage counter to zero */
10850         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10851                                           dmae_reg_go_c[INIT_DMAE_C(sc)],
10852                                           "DMAE dommand register timed out",
10853                                           poll_cnt)) {
10854                 return -1;
10855         }
10856
10857         return 0;
10858 }
10859
10860 #define OP_GEN_PARAM(param)                                            \
10861         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10862 #define OP_GEN_TYPE(type)                                           \
10863         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10864 #define OP_GEN_AGG_VECT(index)                                             \
10865         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10866
10867 static int
10868 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10869                      uint32_t poll_cnt)
10870 {
10871         uint32_t op_gen_command = 0;
10872         uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10873                               CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10874         int ret = 0;
10875
10876         if (REG_RD(sc, comp_addr)) {
10877                 PMD_DRV_LOG(NOTICE, sc,
10878                             "Cleanup complete was not 0 before sending");
10879                 return -1;
10880         }
10881
10882         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10883         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10884         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10885         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10886
10887         REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10888
10889         if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10890                 PMD_DRV_LOG(NOTICE, sc, "FW final cleanup did not succeed");
10891                 PMD_DRV_LOG(DEBUG, sc, "At timeout completion address contained %x",
10892                             (REG_RD(sc, comp_addr)));
10893                 rte_panic("FLR cleanup failed");
10894                 return -1;
10895         }
10896
10897         /* Zero completion for nxt FLR */
10898         REG_WR(sc, comp_addr, 0);
10899
10900         return ret;
10901 }
10902
10903 static void
10904 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10905                        uint32_t poll_count)
10906 {
10907         uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10908         uint32_t cur_cnt = poll_count;
10909
10910         crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10911         crd = crd_start = REG_RD(sc, regs->crd);
10912         init_crd = REG_RD(sc, regs->init_crd);
10913
10914         while ((crd != init_crd) &&
10915                ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10916                 (init_crd - crd_start))) {
10917                 if (cur_cnt--) {
10918                         DELAY(FLR_WAIT_INTERVAL);
10919                         crd = REG_RD(sc, regs->crd);
10920                         crd_freed = REG_RD(sc, regs->crd_freed);
10921                 } else {
10922                         break;
10923                 }
10924         }
10925 }
10926
10927 static void
10928 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10929                        uint32_t poll_count)
10930 {
10931         uint32_t occup, to_free, freed, freed_start;
10932         uint32_t cur_cnt = poll_count;
10933
10934         occup = to_free = REG_RD(sc, regs->lines_occup);
10935         freed = freed_start = REG_RD(sc, regs->lines_freed);
10936
10937         while (occup &&
10938                ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10939                 to_free)) {
10940                 if (cur_cnt--) {
10941                         DELAY(FLR_WAIT_INTERVAL);
10942                         occup = REG_RD(sc, regs->lines_occup);
10943                         freed = REG_RD(sc, regs->lines_freed);
10944                 } else {
10945                         break;
10946                 }
10947         }
10948 }
10949
10950 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10951 {
10952         struct pbf_pN_cmd_regs cmd_regs[] = {
10953                 {0, (CHIP_IS_E3B0(sc)) ?
10954                  PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10955                  (CHIP_IS_E3B0(sc)) ?
10956                  PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10957                 {1, (CHIP_IS_E3B0(sc)) ?
10958                  PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10959                  (CHIP_IS_E3B0(sc)) ?
10960                  PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10961                 {4, (CHIP_IS_E3B0(sc)) ?
10962                  PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10963                  (CHIP_IS_E3B0(sc)) ?
10964                  PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10965                  PBF_REG_P4_TQ_LINES_FREED_CNT}
10966         };
10967
10968         struct pbf_pN_buf_regs buf_regs[] = {
10969                 {0, (CHIP_IS_E3B0(sc)) ?
10970                  PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10971                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10972                  (CHIP_IS_E3B0(sc)) ?
10973                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10974                  PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10975                 {1, (CHIP_IS_E3B0(sc)) ?
10976                  PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10977                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10978                  (CHIP_IS_E3B0(sc)) ?
10979                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10980                  PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10981                 {4, (CHIP_IS_E3B0(sc)) ?
10982                  PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10983                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10984                  (CHIP_IS_E3B0(sc)) ?
10985                  PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10986                  PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10987         };
10988
10989         uint32_t i;
10990
10991         /* Verify the command queues are flushed P0, P1, P4 */
10992         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10993                 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10994         }
10995
10996         /* Verify the transmission buffers are flushed P0, P1, P4 */
10997         for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10998                 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
10999         }
11000 }
11001
11002 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
11003 {
11004         __rte_unused uint32_t val;
11005
11006         val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
11007         PMD_DRV_LOG(DEBUG, sc, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
11008
11009         val = REG_RD(sc, PBF_REG_DISABLE_PF);
11010         PMD_DRV_LOG(DEBUG, sc, "PBF_REG_DISABLE_PF is 0x%x", val);
11011
11012         val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
11013         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
11014
11015         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
11016         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
11017
11018         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
11019         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
11020
11021         val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
11022         PMD_DRV_LOG(DEBUG, sc,
11023                     "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
11024
11025         val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
11026         PMD_DRV_LOG(DEBUG, sc,
11027                     "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
11028
11029         val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
11030         PMD_DRV_LOG(DEBUG, sc, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
11031                     val);
11032 }
11033
11034 /**
11035  *      bnx2x_pf_flr_clnup
11036  *      a. re-enable target read on the PF
11037  *      b. poll cfc per function usgae counter
11038  *      c. poll the qm perfunction usage counter
11039  *      d. poll the tm per function usage counter
11040  *      e. poll the tm per function scan-done indication
11041  *      f. clear the dmae channel associated wit hthe PF
11042  *      g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11043  *      h. call the common flr cleanup code with -1 (pf indication)
11044  */
11045 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11046 {
11047         uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11048
11049         /* Re-enable PF target read access */
11050         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11051
11052         /* Poll HW usage counters */
11053         if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11054                 return -1;
11055         }
11056
11057         /* Zero the igu 'trailing edge' and 'leading edge' */
11058
11059         /* Send the FW cleanup command */
11060         if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11061                 return -1;
11062         }
11063
11064         /* ATC cleanup */
11065
11066         /* Verify TX hw is flushed */
11067         bnx2x_tx_hw_flushed(sc, poll_cnt);
11068
11069         /* Wait 100ms (not adjusted according to platform) */
11070         DELAY(100000);
11071
11072         /* Verify no pending pci transactions */
11073         if (bnx2x_is_pcie_pending(sc)) {
11074                 PMD_DRV_LOG(NOTICE, sc, "PCIE Transactions still pending");
11075         }
11076
11077         /* Debug */
11078         bnx2x_hw_enable_status(sc);
11079
11080         /*
11081          * Master enable - Due to WB DMAE writes performed before this
11082          * register is re-initialized as part of the regular function init
11083          */
11084         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11085
11086         return 0;
11087 }
11088
11089 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11090 {
11091         int port = SC_PORT(sc);
11092         int func = SC_FUNC(sc);
11093         int init_phase = PHASE_PF0 + func;
11094         struct ecore_ilt *ilt = sc->ilt;
11095         uint16_t cdu_ilt_start;
11096         uint32_t addr, val;
11097         uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11098         int main_mem_width, rc;
11099         uint32_t i;
11100
11101         PMD_DRV_LOG(DEBUG, sc, "starting func init for func %d", func);
11102
11103         /* FLR cleanup */
11104         if (!CHIP_IS_E1x(sc)) {
11105                 rc = bnx2x_pf_flr_clnup(sc);
11106                 if (rc) {
11107                         PMD_DRV_LOG(NOTICE, sc, "FLR cleanup failed!");
11108                         return rc;
11109                 }
11110         }
11111
11112         /* set MSI reconfigure capability */
11113         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11114                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11115                 val = REG_RD(sc, addr);
11116                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11117                 REG_WR(sc, addr, val);
11118         }
11119
11120         ecore_init_block(sc, BLOCK_PXP, init_phase);
11121         ecore_init_block(sc, BLOCK_PXP2, init_phase);
11122
11123         ilt = sc->ilt;
11124         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11125
11126         for (i = 0; i < L2_ILT_LINES(sc); i++) {
11127                 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11128                 ilt->lines[cdu_ilt_start + i].page_mapping =
11129                     (rte_iova_t)sc->context[i].vcxt_dma.paddr;
11130                 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11131         }
11132         ecore_ilt_init_op(sc, INITOP_SET);
11133
11134         REG_WR(sc, PRS_REG_NIC_MODE, 1);
11135
11136         if (!CHIP_IS_E1x(sc)) {
11137                 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11138
11139 /* Turn on a single ISR mode in IGU if driver is going to use
11140  * INT#x or MSI
11141  */
11142                 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11143                     || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11144                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11145                 }
11146
11147 /*
11148  * Timers workaround bug: function init part.
11149  * Need to wait 20msec after initializing ILT,
11150  * needed to make sure there are no requests in
11151  * one of the PXP internal queues with "old" ILT addresses
11152  */
11153                 DELAY(20000);
11154
11155 /*
11156  * Master enable - Due to WB DMAE writes performed before this
11157  * register is re-initialized as part of the regular function
11158  * init
11159  */
11160                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11161 /* Enable the function in IGU */
11162                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11163         }
11164
11165         sc->dmae_ready = 1;
11166
11167         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11168
11169         if (!CHIP_IS_E1x(sc))
11170                 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11171
11172         ecore_init_block(sc, BLOCK_ATC, init_phase);
11173         ecore_init_block(sc, BLOCK_DMAE, init_phase);
11174         ecore_init_block(sc, BLOCK_NIG, init_phase);
11175         ecore_init_block(sc, BLOCK_SRC, init_phase);
11176         ecore_init_block(sc, BLOCK_MISC, init_phase);
11177         ecore_init_block(sc, BLOCK_TCM, init_phase);
11178         ecore_init_block(sc, BLOCK_UCM, init_phase);
11179         ecore_init_block(sc, BLOCK_CCM, init_phase);
11180         ecore_init_block(sc, BLOCK_XCM, init_phase);
11181         ecore_init_block(sc, BLOCK_TSEM, init_phase);
11182         ecore_init_block(sc, BLOCK_USEM, init_phase);
11183         ecore_init_block(sc, BLOCK_CSEM, init_phase);
11184         ecore_init_block(sc, BLOCK_XSEM, init_phase);
11185
11186         if (!CHIP_IS_E1x(sc))
11187                 REG_WR(sc, QM_REG_PF_EN, 1);
11188
11189         if (!CHIP_IS_E1x(sc)) {
11190                 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11191                 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11192                 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11193                 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11194         }
11195         ecore_init_block(sc, BLOCK_QM, init_phase);
11196
11197         ecore_init_block(sc, BLOCK_TM, init_phase);
11198         ecore_init_block(sc, BLOCK_DORQ, init_phase);
11199
11200         ecore_init_block(sc, BLOCK_BRB1, init_phase);
11201         ecore_init_block(sc, BLOCK_PRS, init_phase);
11202         ecore_init_block(sc, BLOCK_TSDM, init_phase);
11203         ecore_init_block(sc, BLOCK_CSDM, init_phase);
11204         ecore_init_block(sc, BLOCK_USDM, init_phase);
11205         ecore_init_block(sc, BLOCK_XSDM, init_phase);
11206         ecore_init_block(sc, BLOCK_UPB, init_phase);
11207         ecore_init_block(sc, BLOCK_XPB, init_phase);
11208         ecore_init_block(sc, BLOCK_PBF, init_phase);
11209         if (!CHIP_IS_E1x(sc))
11210                 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11211
11212         ecore_init_block(sc, BLOCK_CDU, init_phase);
11213
11214         ecore_init_block(sc, BLOCK_CFC, init_phase);
11215
11216         if (!CHIP_IS_E1x(sc))
11217                 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11218
11219         if (IS_MF(sc)) {
11220                 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11221                 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11222         }
11223
11224         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11225
11226         /* HC init per function */
11227         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11228                 if (CHIP_IS_E1H(sc)) {
11229                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11230
11231                         REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11232                         REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11233                 }
11234                 ecore_init_block(sc, BLOCK_HC, init_phase);
11235
11236         } else {
11237                 uint32_t num_segs, sb_idx, prod_offset;
11238
11239                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11240
11241                 if (!CHIP_IS_E1x(sc)) {
11242                         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11243                         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11244                 }
11245
11246                 ecore_init_block(sc, BLOCK_IGU, init_phase);
11247
11248                 if (!CHIP_IS_E1x(sc)) {
11249                         int dsb_idx = 0;
11250         /**
11251          * Producer memory:
11252          * E2 mode: address 0-135 match to the mapping memory;
11253          * 136 - PF0 default prod; 137 - PF1 default prod;
11254          * 138 - PF2 default prod; 139 - PF3 default prod;
11255          * 140 - PF0 attn prod;    141 - PF1 attn prod;
11256          * 142 - PF2 attn prod;    143 - PF3 attn prod;
11257          * 144-147 reserved.
11258          *
11259          * E1.5 mode - In backward compatible mode;
11260          * for non default SB; each even line in the memory
11261          * holds the U producer and each odd line hold
11262          * the C producer. The first 128 producers are for
11263          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11264          * producers are for the DSB for each PF.
11265          * Each PF has five segments: (the order inside each
11266          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11267          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11268          * 144-147 attn prods;
11269          */
11270                         /* non-default-status-blocks */
11271                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11272                             IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11273                         for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11274                                 prod_offset = (sc->igu_base_sb + sb_idx) *
11275                                     num_segs;
11276
11277                                 for (i = 0; i < num_segs; i++) {
11278                                         addr = IGU_REG_PROD_CONS_MEMORY +
11279                                             (prod_offset + i) * 4;
11280                                         REG_WR(sc, addr, 0);
11281                                 }
11282                                 /* send consumer update with value 0 */
11283                                 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11284                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11285                                 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11286                         }
11287
11288                         /* default-status-blocks */
11289                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11290                             IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11291
11292                         if (CHIP_IS_MODE_4_PORT(sc))
11293                                 dsb_idx = SC_FUNC(sc);
11294                         else
11295                                 dsb_idx = SC_VN(sc);
11296
11297                         prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11298                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
11299                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
11300
11301                         /*
11302                          * igu prods come in chunks of E1HVN_MAX (4) -
11303                          * does not matters what is the current chip mode
11304                          */
11305                         for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11306                                 addr = IGU_REG_PROD_CONS_MEMORY +
11307                                     (prod_offset + i) * 4;
11308                                 REG_WR(sc, addr, 0);
11309                         }
11310                         /* send consumer update with 0 */
11311                         if (CHIP_INT_MODE_IS_BC(sc)) {
11312                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11313                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11314                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11315                                            CSTORM_ID, 0, IGU_INT_NOP, 1);
11316                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11317                                            XSTORM_ID, 0, IGU_INT_NOP, 1);
11318                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11319                                            TSTORM_ID, 0, IGU_INT_NOP, 1);
11320                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11321                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11322                         } else {
11323                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11324                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11325                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11326                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11327                         }
11328                         bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11329
11330                         /* !!! these should become driver const once
11331                            rf-tool supports split-68 const */
11332                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11333                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11334                         REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11335                         REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11336                         REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11337                         REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11338                 }
11339         }
11340
11341         /* Reset PCIE errors for debug */
11342         REG_WR(sc, 0x2114, 0xffffffff);
11343         REG_WR(sc, 0x2120, 0xffffffff);
11344
11345         if (CHIP_IS_E1x(sc)) {
11346                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2;    /*dwords */
11347                 main_mem_base = HC_REG_MAIN_MEMORY +
11348                     SC_PORT(sc) * (main_mem_size * 4);
11349                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11350                 main_mem_width = 8;
11351
11352                 val = REG_RD(sc, main_mem_prty_clr);
11353                 if (val) {
11354                         PMD_DRV_LOG(DEBUG, sc,
11355                                     "Parity errors in HC block during function init (0x%x)!",
11356                                     val);
11357                 }
11358
11359 /* Clear "false" parity errors in MSI-X table */
11360                 for (i = main_mem_base;
11361                      i < main_mem_base + main_mem_size * 4;
11362                      i += main_mem_width) {
11363                         bnx2x_read_dmae(sc, i, main_mem_width / 4);
11364                         bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11365                                        i, main_mem_width / 4);
11366                 }
11367 /* Clear HC parity attention */
11368                 REG_RD(sc, main_mem_prty_clr);
11369         }
11370
11371         /* Enable STORMs SP logging */
11372         REG_WR8(sc, BAR_USTRORM_INTMEM +
11373                 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11374         REG_WR8(sc, BAR_TSTRORM_INTMEM +
11375                 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11376         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11377                 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11378         REG_WR8(sc, BAR_XSTRORM_INTMEM +
11379                 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11380
11381         elink_phy_probe(&sc->link_params);
11382
11383         return 0;
11384 }
11385
11386 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11387 {
11388         if (!BNX2X_NOMCP(sc)) {
11389                 bnx2x_acquire_phy_lock(sc);
11390                 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11391                 bnx2x_release_phy_lock(sc);
11392         } else {
11393                 if (!CHIP_REV_IS_SLOW(sc)) {
11394                         PMD_DRV_LOG(WARNING, sc,
11395                                     "Bootcode is missing - cannot reset link");
11396                 }
11397         }
11398 }
11399
11400 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11401 {
11402         int port = SC_PORT(sc);
11403         uint32_t val;
11404
11405         /* reset physical Link */
11406         bnx2x_link_reset(sc);
11407
11408         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11409
11410         /* Do not rcv packets to BRB */
11411         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11412         /* Do not direct rcv packets that are not for MCP to the BRB */
11413         REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11414                     NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11415
11416         /* Configure AEU */
11417         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11418
11419         DELAY(100000);
11420
11421         /* Check for BRB port occupancy */
11422         val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11423         if (val) {
11424                 PMD_DRV_LOG(DEBUG, sc,
11425                             "BRB1 is not empty, %d blocks are occupied", val);
11426         }
11427 }
11428
11429 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr)
11430 {
11431         int reg;
11432         uint32_t wb_write[2];
11433
11434         reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11435
11436         wb_write[0] = ONCHIP_ADDR1(addr);
11437         wb_write[1] = ONCHIP_ADDR2(addr);
11438         REG_WR_DMAE(sc, reg, wb_write, 2);
11439 }
11440
11441 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11442 {
11443         uint32_t i, base = FUNC_ILT_BASE(func);
11444         for (i = base; i < base + ILT_PER_FUNC; i++) {
11445                 bnx2x_ilt_wr(sc, i, 0);
11446         }
11447 }
11448
11449 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11450 {
11451         struct bnx2x_fastpath *fp;
11452         int port = SC_PORT(sc);
11453         int func = SC_FUNC(sc);
11454         int i;
11455
11456         /* Disable the function in the FW */
11457         REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11458         REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11459         REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11460         REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11461
11462         /* FP SBs */
11463         FOR_EACH_ETH_QUEUE(sc, i) {
11464                 fp = &sc->fp[i];
11465                 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11466                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11467                         SB_DISABLED);
11468         }
11469
11470         /* SP SB */
11471         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11472                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11473
11474         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11475                 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11476                        0);
11477         }
11478
11479         /* Configure IGU */
11480         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11481                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11482                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11483         } else {
11484                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11485                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11486         }
11487
11488         if (CNIC_LOADED(sc)) {
11489 /* Disable Timer scan */
11490                 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11491 /*
11492  * Wait for at least 10ms and up to 2 second for the timers
11493  * scan to complete
11494  */
11495                 for (i = 0; i < 200; i++) {
11496                         DELAY(10000);
11497                         if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11498                                 break;
11499                 }
11500         }
11501
11502         /* Clear ILT */
11503         bnx2x_clear_func_ilt(sc, func);
11504
11505         /*
11506          * Timers workaround bug for E2: if this is vnic-3,
11507          * we need to set the entire ilt range for this timers.
11508          */
11509         if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11510                 struct ilt_client_info ilt_cli;
11511 /* use dummy TM client */
11512                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11513                 ilt_cli.start = 0;
11514                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11515                 ilt_cli.client_num = ILT_CLIENT_TM;
11516
11517                 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11518         }
11519
11520         /* this assumes that reset_port() called before reset_func() */
11521         if (!CHIP_IS_E1x(sc)) {
11522                 bnx2x_pf_disable(sc);
11523         }
11524
11525         sc->dmae_ready = 0;
11526 }
11527
11528 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11529 {
11530         rte_free(sc->init_ops);
11531         rte_free(sc->init_ops_offsets);
11532         rte_free(sc->init_data);
11533         rte_free(sc->iro_array);
11534 }
11535
11536 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11537 {
11538         uint32_t len, i;
11539         uint8_t *p = sc->firmware;
11540         uint32_t off[24];
11541
11542         for (i = 0; i < 24; ++i)
11543                 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11544
11545         len = off[0];
11546         sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11547         if (!sc->init_ops)
11548                 goto alloc_failed;
11549         bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11550
11551         len = off[2];
11552         sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11553         if (!sc->init_ops_offsets)
11554                 goto alloc_failed;
11555         bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11556
11557         len = off[4];
11558         sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11559         if (!sc->init_data)
11560                 goto alloc_failed;
11561         bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11562
11563         sc->tsem_int_table_data = p + off[7];
11564         sc->tsem_pram_data = p + off[9];
11565         sc->usem_int_table_data = p + off[11];
11566         sc->usem_pram_data = p + off[13];
11567         sc->csem_int_table_data = p + off[15];
11568         sc->csem_pram_data = p + off[17];
11569         sc->xsem_int_table_data = p + off[19];
11570         sc->xsem_pram_data = p + off[21];
11571
11572         len = off[22];
11573         sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11574         if (!sc->iro_array)
11575                 goto alloc_failed;
11576         bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11577
11578         return 0;
11579
11580 alloc_failed:
11581         bnx2x_release_firmware(sc);
11582         return -1;
11583 }
11584
11585 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11586 {
11587 #define MIN_PREFIX_SIZE (10)
11588
11589         int n = MIN_PREFIX_SIZE;
11590         uint16_t xlen;
11591
11592         if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11593             len <= MIN_PREFIX_SIZE) {
11594                 return -1;
11595         }
11596
11597         /* optional extra fields are present */
11598         if (zbuf[3] & 0x4) {
11599                 xlen = zbuf[13];
11600                 xlen <<= 8;
11601                 xlen += zbuf[12];
11602
11603                 n += xlen;
11604         }
11605         /* file name is present */
11606         if (zbuf[3] & 0x8) {
11607                 while ((zbuf[n++] != 0) && (n < len)) ;
11608         }
11609
11610         return n;
11611 }
11612
11613 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11614 {
11615         int ret;
11616         int data_begin = cut_gzip_prefix(zbuf, len);
11617
11618         PMD_DRV_LOG(DEBUG, sc, "ecore_gunzip %d", len);
11619
11620         if (data_begin <= 0) {
11621                 PMD_DRV_LOG(NOTICE, sc, "bad gzip prefix");
11622                 return -1;
11623         }
11624
11625         memset(&zlib_stream, 0, sizeof(zlib_stream));
11626         zlib_stream.next_in = zbuf + data_begin;
11627         zlib_stream.avail_in = len - data_begin;
11628         zlib_stream.next_out = sc->gz_buf;
11629         zlib_stream.avail_out = FW_BUF_SIZE;
11630
11631         ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11632         if (ret != Z_OK) {
11633                 PMD_DRV_LOG(NOTICE, sc, "zlib inflateInit2 error");
11634                 return ret;
11635         }
11636
11637         ret = inflate(&zlib_stream, Z_FINISH);
11638         if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11639                 PMD_DRV_LOG(NOTICE, sc, "zlib inflate error: %d %s", ret,
11640                             zlib_stream.msg);
11641         }
11642
11643         sc->gz_outlen = zlib_stream.total_out;
11644         if (sc->gz_outlen & 0x3) {
11645                 PMD_DRV_LOG(NOTICE, sc, "firmware is not aligned. gz_outlen == %d",
11646                             sc->gz_outlen);
11647         }
11648         sc->gz_outlen >>= 2;
11649
11650         inflateEnd(&zlib_stream);
11651
11652         if (ret == Z_STREAM_END)
11653                 return 0;
11654
11655         return ret;
11656 }
11657
11658 static void
11659 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
11660                           uint32_t addr, uint32_t len)
11661 {
11662         bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11663 }
11664
11665 void
11666 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11667                           uint32_t * data)
11668 {
11669         uint8_t i;
11670         for (i = 0; i < size / 4; i++) {
11671                 REG_WR(sc, addr + (i * 4), data[i]);
11672         }
11673 }
11674
11675 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11676 {
11677         uint32_t phy_type_idx = ext_phy_type >> 8;
11678         static const char *types[] =
11679             { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11680                 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11681                 "BNX2X-8727",
11682                 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11683         };
11684
11685         if (phy_type_idx < 12)
11686                 return types[phy_type_idx];
11687         else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11688                 return types[12];
11689         else
11690                 return types[13];
11691 }
11692
11693 static const char *get_state(uint32_t state)
11694 {
11695         uint32_t state_idx = state >> 12;
11696         static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11697                 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11698                 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11699                 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11700                 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11701         };
11702
11703         if (state_idx <= 0xF)
11704                 return states[state_idx];
11705         else
11706                 return states[0x10];
11707 }
11708
11709 static const char *get_recovery_state(uint32_t state)
11710 {
11711         static const char *states[] = { "NONE", "DONE", "INIT",
11712                 "WAIT", "FAILED", "NIC_LOADING"
11713         };
11714         return states[state];
11715 }
11716
11717 static const char *get_rx_mode(uint32_t mode)
11718 {
11719         static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11720                 "PROMISC", "MAX_MULTICAST", "ERROR"
11721         };
11722
11723         if (mode < 0x4)
11724                 return modes[mode];
11725         else if (BNX2X_MAX_MULTICAST == mode)
11726                 return modes[4];
11727         else
11728                 return modes[5];
11729 }
11730
11731 #define BNX2X_INFO_STR_MAX 256
11732 static const char *get_bnx2x_flags(uint32_t flags)
11733 {
11734         int i;
11735         static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11736                 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11737                 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11738                 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11739         };
11740         static char flag_str[BNX2X_INFO_STR_MAX];
11741         memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11742
11743         for (i = 0; i < 5; i++)
11744                 if (flags & (1 << i)) {
11745                         strlcat(flag_str, flag[i], sizeof(flag_str));
11746                         flags ^= (1 << i);
11747                 }
11748         if (flags) {
11749                 static char unknown[BNX2X_INFO_STR_MAX];
11750                 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11751                 strlcat(flag_str, unknown, sizeof(flag_str));
11752         }
11753         return flag_str;
11754 }
11755
11756 /* Prints useful adapter info. */
11757 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11758 {
11759         int i = 0;
11760
11761         PMD_DRV_LOG(INFO, sc, "========================================");
11762         /* DPDK and Driver versions */
11763         PMD_DRV_LOG(INFO, sc, "%12s : %s", "DPDK",
11764                         rte_version());
11765         PMD_DRV_LOG(INFO, sc, "%12s : %s", "Driver",
11766                         bnx2x_pmd_version());
11767         /* Firmware versions. */
11768         PMD_DRV_LOG(INFO, sc, "%12s : %d.%d.%d",
11769                      "Firmware",
11770                      BNX2X_5710_FW_MAJOR_VERSION,
11771                      BNX2X_5710_FW_MINOR_VERSION,
11772                      BNX2X_5710_FW_REVISION_VERSION);
11773         PMD_DRV_LOG(INFO, sc, "%12s : %s",
11774                      "Bootcode", sc->devinfo.bc_ver_str);
11775         /* Hardware chip info. */
11776         PMD_DRV_LOG(INFO, sc, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11777         PMD_DRV_LOG(INFO, sc, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11778                      (CHIP_METAL(sc) >> 4));
11779         /* Bus PCIe info. */
11780         PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Vendor Id",
11781                     sc->devinfo.vendor_id);
11782         PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Device Id",
11783                     sc->devinfo.device_id);
11784         PMD_DRV_LOG(INFO, sc, "%12s : width x%d, ", "Bus PCIe",
11785                     sc->devinfo.pcie_link_width);
11786         switch (sc->devinfo.pcie_link_speed) {
11787         case 1:
11788                 PMD_DRV_LOG(INFO, sc, "%23s", "2.5 Gbps");
11789                 break;
11790         case 2:
11791                 PMD_DRV_LOG(INFO, sc, "%21s", "5 Gbps");
11792                 break;
11793         case 4:
11794                 PMD_DRV_LOG(INFO, sc, "%21s", "8 Gbps");
11795                 break;
11796         default:
11797                 PMD_DRV_LOG(INFO, sc, "%33s", "Unknown link speed");
11798         }
11799         /* Device features. */
11800         PMD_DRV_LOG(INFO, sc, "%12s : ", "Flags");
11801         /* Miscellaneous flags. */
11802         if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11803                 PMD_DRV_LOG(INFO, sc, "%18s", "MSI");
11804                 i++;
11805         }
11806         if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11807                 if (i > 0)
11808                         PMD_DRV_LOG(INFO, sc, "|");
11809                 PMD_DRV_LOG(INFO, sc, "%20s", "MSI-X");
11810                 i++;
11811         }
11812         PMD_DRV_LOG(INFO, sc, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11813         PMD_DRV_LOG(INFO, sc, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11814         PMD_DRV_LOG(INFO, sc, "========================================");
11815 }
11816
11817 /* Prints useful device info. */
11818 void bnx2x_print_device_info(struct bnx2x_softc *sc)
11819 {
11820         __rte_unused uint32_t ext_phy_type;
11821         uint32_t offset, reg_val;
11822
11823         PMD_INIT_FUNC_TRACE(sc);
11824         offset = offsetof(struct shmem_region,
11825                           dev_info.port_hw_config[0].external_phy_config);
11826         reg_val = REG_RD(sc, sc->devinfo.shmem_base + offset);
11827         if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11828                 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(reg_val);
11829         else
11830                 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(reg_val);
11831
11832         /* Device features. */
11833         PMD_DRV_LOG(INFO, sc, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11834         PMD_DRV_LOG(INFO, sc,
11835                     "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11836         PMD_DRV_LOG(INFO, sc, "%12s : %s", "DMAE Is",
11837                      (sc->dmae_ready ? "Ready" : "Not Ready"));
11838         PMD_DRV_LOG(INFO, sc, "%12s : %u", "MTU", sc->mtu);
11839         PMD_DRV_LOG(INFO, sc,
11840                     "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11841         PMD_DRV_LOG(INFO, sc, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11842                         sc->link_params.mac_addr[0],
11843                         sc->link_params.mac_addr[1],
11844                         sc->link_params.mac_addr[2],
11845                         sc->link_params.mac_addr[3],
11846                         sc->link_params.mac_addr[4],
11847                         sc->link_params.mac_addr[5]);
11848         PMD_DRV_LOG(INFO, sc, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11849         PMD_DRV_LOG(INFO, sc, "%12s : %s", "State", get_state(sc->state));
11850         if (sc->recovery_state)
11851                 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Recovery",
11852                              get_recovery_state(sc->recovery_state));
11853         /* Queue info. */
11854         if (IS_PF(sc)) {
11855                 switch (sc->sp->rss_rdata.rss_mode) {
11856                 case ETH_RSS_MODE_DISABLED:
11857                         PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - None");
11858                         break;
11859                 case ETH_RSS_MODE_REGULAR:
11860                         PMD_DRV_LOG(INFO, sc, "%12s : %s,", "Queues", "RSS mode - Regular");
11861                         PMD_DRV_LOG(INFO, sc, "%16d", sc->num_queues);
11862                         break;
11863                 default:
11864                         PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - Unknown");
11865                         break;
11866                 }
11867         }
11868         PMD_DRV_LOG(INFO, sc, "%12s : CQ = %lx,  EQ = %lx", "SPQ Left",
11869                      sc->cq_spq_left, sc->eq_spq_left);
11870
11871         PMD_DRV_LOG(INFO, sc,
11872                     "%12s : %x", "Switch", sc->link_params.switch_cfg);
11873         PMD_DRV_LOG(INFO, sc, "pcie_bus=%d, pcie_device=%d",
11874                         sc->pcie_bus, sc->pcie_device);
11875         PMD_DRV_LOG(INFO, sc, "bar0.addr=%p, bar1.addr=%p",
11876                         sc->bar[BAR0].base_addr, sc->bar[BAR1].base_addr);
11877         PMD_DRV_LOG(INFO, sc, "port=%d, path=%d, vnic=%d, func=%d",
11878                         PORT_ID(sc), PATH_ID(sc), VNIC_ID(sc), FUNC_ID(sc));
11879 }