drivers/net/bnxt/bnxt.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _BNXT_H_
   7 #define _BNXT_H_
   8
   9 #include <inttypes.h>
  10 #include <stdbool.h>
  11 #include <sys/queue.h>
  12
  13 #include <rte_pci.h>
  14 #include <rte_bus_pci.h>
  15 #include <rte_ethdev_driver.h>
  16 #include <rte_memory.h>
  17 #include <rte_lcore.h>
  18 #include <rte_spinlock.h>
  19 #include <rte_time.h>
  20
  21 #include "bnxt_cpr.h"
  22 #include "bnxt_util.h"
  23
  24 #include "tf_core.h"
  25 #include "bnxt_ulp.h"
  26
  27 /* Vendor ID */
  28 #define PCI_VENDOR_ID_BROADCOM          0x14E4
  29
  30 /* Device IDs */
  31 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  32 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  33 #define BROADCOM_DEV_ID_STRATUS_NIC     0x1614
  34 #define BROADCOM_DEV_ID_57414_VF        0x16c1
  35 #define BROADCOM_DEV_ID_57301           0x16c8
  36 #define BROADCOM_DEV_ID_57302           0x16c9
  37 #define BROADCOM_DEV_ID_57304_PF        0x16ca
  38 #define BROADCOM_DEV_ID_57304_VF        0x16cb
  39 #define BROADCOM_DEV_ID_57417_MF        0x16cc
  40 #define BROADCOM_DEV_ID_NS2             0x16cd
  41 #define BROADCOM_DEV_ID_57311           0x16ce
  42 #define BROADCOM_DEV_ID_57312           0x16cf
  43 #define BROADCOM_DEV_ID_57402           0x16d0
  44 #define BROADCOM_DEV_ID_57404           0x16d1
  45 #define BROADCOM_DEV_ID_57406_PF        0x16d2
  46 #define BROADCOM_DEV_ID_57406_VF        0x16d3
  47 #define BROADCOM_DEV_ID_57402_MF        0x16d4
  48 #define BROADCOM_DEV_ID_57407_RJ45      0x16d5
  49 #define BROADCOM_DEV_ID_57412           0x16d6
  50 #define BROADCOM_DEV_ID_57414           0x16d7
  51 #define BROADCOM_DEV_ID_57416_RJ45      0x16d8
  52 #define BROADCOM_DEV_ID_57417_RJ45      0x16d9
  53 #define BROADCOM_DEV_ID_5741X_VF        0x16dc
  54 #define BROADCOM_DEV_ID_57412_MF        0x16de
  55 #define BROADCOM_DEV_ID_57314           0x16df
  56 #define BROADCOM_DEV_ID_57317_RJ45      0x16e0
  57 #define BROADCOM_DEV_ID_5731X_VF        0x16e1
  58 #define BROADCOM_DEV_ID_57417_SFP       0x16e2
  59 #define BROADCOM_DEV_ID_57416_SFP       0x16e3
  60 #define BROADCOM_DEV_ID_57317_SFP       0x16e4
  61 #define BROADCOM_DEV_ID_57404_MF        0x16e7
  62 #define BROADCOM_DEV_ID_57406_MF        0x16e8
  63 #define BROADCOM_DEV_ID_57407_SFP       0x16e9
  64 #define BROADCOM_DEV_ID_57407_MF        0x16ea
  65 #define BROADCOM_DEV_ID_57414_MF        0x16ec
  66 #define BROADCOM_DEV_ID_57416_MF        0x16ee
  67 #define BROADCOM_DEV_ID_57508           0x1750
  68 #define BROADCOM_DEV_ID_57504           0x1751
  69 #define BROADCOM_DEV_ID_57502           0x1752
  70 #define BROADCOM_DEV_ID_57508_MF1       0x1800
  71 #define BROADCOM_DEV_ID_57504_MF1       0x1801
  72 #define BROADCOM_DEV_ID_57502_MF1       0x1802
  73 #define BROADCOM_DEV_ID_57508_MF2       0x1803
  74 #define BROADCOM_DEV_ID_57504_MF2       0x1804
  75 #define BROADCOM_DEV_ID_57502_MF2       0x1805
  76 #define BROADCOM_DEV_ID_57500_VF1       0x1806
  77 #define BROADCOM_DEV_ID_57500_VF2       0x1807
  78 #define BROADCOM_DEV_ID_58802           0xd802
  79 #define BROADCOM_DEV_ID_58804           0xd804
  80 #define BROADCOM_DEV_ID_58808           0x16f0
  81 #define BROADCOM_DEV_ID_58802_VF        0xd800
  82
  83 #define BNXT_MAX_MTU            9574
  84 #define VLAN_TAG_SIZE           4
  85 #define BNXT_NUM_VLANS          2
  86 #define BNXT_MAX_PKT_LEN        (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\
  87                                  RTE_ETHER_CRC_LEN +\
  88                                  (BNXT_NUM_VLANS * VLAN_TAG_SIZE))
  89 /* FW adds extra 4 bytes for FCS */
  90 #define BNXT_VNIC_MRU(mtu)\
  91         ((mtu) + RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS)
  92 #define BNXT_VF_RSV_NUM_RSS_CTX 1
  93 #define BNXT_VF_RSV_NUM_L2_CTX  4
  94 /* TODO: For now, do not support VMDq/RFS on VFs. */
  95 #define BNXT_VF_RSV_NUM_VNIC    1
  96 #define BNXT_MAX_LED            4
  97 #define BNXT_MIN_RING_DESC      16
  98 #define BNXT_MAX_TX_RING_DESC   4096
  99 #define BNXT_MAX_RX_RING_DESC   8192
 100 #define BNXT_DB_SIZE            0x80
 101
 102 #define TPA_MAX_AGGS            64
 103 #define TPA_MAX_AGGS_TH         1024
 104
 105 #define TPA_MAX_NUM_SEGS        32
 106 #define TPA_MAX_SEGS_TH         8 /* 32 segments in 4-segment units */
 107 #define TPA_MAX_SEGS            5 /* 32 segments in log2 units */
 108
 109 #define BNXT_TPA_MAX_AGGS(bp) \
 110         (BNXT_CHIP_THOR(bp) ? TPA_MAX_AGGS_TH : \
 111                              TPA_MAX_AGGS)
 112
 113 #define BNXT_TPA_MAX_SEGS(bp) \
 114         (BNXT_CHIP_THOR(bp) ? TPA_MAX_SEGS_TH : \
 115                               TPA_MAX_SEGS)
 116
 117 #ifdef RTE_ARCH_ARM64
 118 #define BNXT_NUM_ASYNC_CPR(bp) (BNXT_STINGRAY(bp) ? 0 : 1)
 119 #else
 120 #define BNXT_NUM_ASYNC_CPR(bp) 1
 121 #endif
 122
 123 /* In FreeBSD OS, nic_uio driver does not support interrupts */
 124 #ifdef RTE_EXEC_ENV_FREEBSD
 125 #ifdef BNXT_NUM_ASYNC_CPR
 126 #undef BNXT_NUM_ASYNC_CPR
 127 #endif
 128 #define BNXT_NUM_ASYNC_CPR(bp)  0
 129 #endif
 130
 131 #define BNXT_MISC_VEC_ID               RTE_INTR_VEC_ZERO_OFFSET
 132 #define BNXT_RX_VEC_START              RTE_INTR_VEC_RXTX_OFFSET
 133
 134 /* Chimp Communication Channel */
 135 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET          0x0
 136 #define GRCPF_REG_CHIMP_COMM_TRIGGER            0x100
 137 /* Kong Communication Channel */
 138 #define GRCPF_REG_KONG_CHANNEL_OFFSET           0xA00
 139 #define GRCPF_REG_KONG_COMM_TRIGGER             0xB00
 140
 141 #define BNXT_INT_LAT_TMR_MIN                    75
 142 #define BNXT_INT_LAT_TMR_MAX                    150
 143 #define BNXT_NUM_CMPL_AGGR_INT                  36
 144 #define BNXT_CMPL_AGGR_DMA_TMR                  37
 145 #define BNXT_NUM_CMPL_DMA_AGGR                  36
 146 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT       50
 147 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT       12
 148
 149 struct bnxt_led_info {
 150         uint8_t      led_id;
 151         uint8_t      led_type;
 152         uint8_t      led_group_id;
 153         uint8_t      unused;
 154         uint16_t  led_state_caps;
 155 #define BNXT_LED_ALT_BLINK_CAP(x)       ((x) &  \
 156         rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
 157
 158         uint16_t  led_color_caps;
 159 };
 160
 161 struct bnxt_led_cfg {
 162         uint8_t led_id;
 163         uint8_t led_state;
 164         uint8_t led_color;
 165         uint8_t unused;
 166         uint16_t led_blink_on;
 167         uint16_t led_blink_off;
 168         uint8_t led_group_id;
 169         uint8_t rsvd;
 170 };
 171
 172 #define BNXT_LED_DFLT_ENA                               \
 173         (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID |             \
 174          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE |          \
 175          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON |       \
 176          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF |      \
 177          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
 178
 179 #define BNXT_LED_DFLT_ENA_SHIFT         6
 180
 181 #define BNXT_LED_DFLT_ENABLES(x)                        \
 182         rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
 183
 184 enum bnxt_hw_context {
 185         HW_CONTEXT_NONE     = 0,
 186         HW_CONTEXT_IS_RSS   = 1,
 187         HW_CONTEXT_IS_COS   = 2,
 188         HW_CONTEXT_IS_LB    = 3,
 189 };
 190
 191 struct bnxt_vlan_table_entry {
 192         uint16_t                tpid;
 193         uint16_t                vid;
 194 } __rte_packed;
 195
 196 struct bnxt_vlan_antispoof_table_entry {
 197         uint16_t                tpid;
 198         uint16_t                vid;
 199         uint16_t                mask;
 200 } __rte_packed;
 201
 202 struct bnxt_child_vf_info {
 203         void                    *req_buf;
 204         struct bnxt_vlan_table_entry    *vlan_table;
 205         struct bnxt_vlan_antispoof_table_entry  *vlan_as_table;
 206         STAILQ_HEAD(, bnxt_filter_info) filter;
 207         uint32_t                func_cfg_flags;
 208         uint32_t                l2_rx_mask;
 209         uint16_t                fid;
 210         uint16_t                max_tx_rate;
 211         uint16_t                dflt_vlan;
 212         uint16_t                vlan_count;
 213         uint8_t                 mac_spoof_en;
 214         uint8_t                 vlan_spoof_en;
 215         bool                    random_mac;
 216         bool                    persist_stats;
 217 };
 218
 219 struct bnxt_pf_info {
 220 #define BNXT_FIRST_PF_FID       1
 221 #define BNXT_MAX_VFS(bp)        (bp->pf.max_vfs)
 222 #define BNXT_TOTAL_VFS(bp)      ((bp)->pf.total_vfs)
 223 #define BNXT_FIRST_VF_FID       128
 224 #define BNXT_PF_RINGS_USED(bp)  bnxt_get_num_queues(bp)
 225 #define BNXT_PF_RINGS_AVAIL(bp) (bp->pf.max_cp_rings - BNXT_PF_RINGS_USED(bp))
 226         uint16_t                port_id;
 227         uint16_t                first_vf_id;
 228         uint16_t                active_vfs;
 229         uint16_t                max_vfs;
 230         uint16_t                total_vfs; /* Total VFs possible.
 231                                             * Not necessarily enabled.
 232                                             */
 233         uint32_t                func_cfg_flags;
 234         void                    *vf_req_buf;
 235         rte_iova_t              vf_req_buf_dma_addr;
 236         uint32_t                vf_req_fwd[8];
 237         uint16_t                total_vnics;
 238         struct bnxt_child_vf_info       *vf_info;
 239 #define BNXT_EVB_MODE_NONE      0
 240 #define BNXT_EVB_MODE_VEB       1
 241 #define BNXT_EVB_MODE_VEPA      2
 242         uint8_t                 evb_mode;
 243 };
 244
 245 /* Max wait time for link up is 10s and link down is 500ms */
 246 #define BNXT_LINK_UP_WAIT_CNT   200
 247 #define BNXT_LINK_DOWN_WAIT_CNT 10
 248 #define BNXT_LINK_WAIT_INTERVAL 50
 249 struct bnxt_link_info {
 250         uint32_t                phy_flags;
 251         uint8_t                 mac_type;
 252         uint8_t                 phy_link_status;
 253         uint8_t                 loop_back;
 254         uint8_t                 link_up;
 255         uint8_t                 duplex;
 256         uint8_t                 pause;
 257         uint8_t                 force_pause;
 258         uint8_t                 auto_pause;
 259         uint8_t                 auto_mode;
 260 #define PHY_VER_LEN             3
 261         uint8_t                 phy_ver[PHY_VER_LEN];
 262         uint16_t                link_speed;
 263         uint16_t                support_speeds;
 264         uint16_t                auto_link_speed;
 265         uint16_t                force_link_speed;
 266         uint16_t                auto_link_speed_mask;
 267         uint32_t                preemphasis;
 268         uint8_t                 phy_type;
 269         uint8_t                 media_type;
 270 };
 271
 272 #define BNXT_COS_QUEUE_COUNT    8
 273 struct bnxt_cos_queue_info {
 274         uint8_t id;
 275         uint8_t profile;
 276 };
 277
 278 struct rte_flow {
 279         STAILQ_ENTRY(rte_flow) next;
 280         struct bnxt_filter_info *filter;
 281         struct bnxt_vnic_info   *vnic;
 282 };
 283
 284 #define BNXT_PTP_FLAGS_PATH_TX          0x0
 285 #define BNXT_PTP_FLAGS_PATH_RX          0x1
 286 #define BNXT_PTP_FLAGS_CURRENT_TIME     0x2
 287
 288 struct bnxt_ptp_cfg {
 289 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT  0x400
 290 #define BNXT_GRCPF_REG_SYNC_TIME        0x480
 291 #define BNXT_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 292         struct rte_timecounter      tc;
 293         struct rte_timecounter      tx_tstamp_tc;
 294         struct rte_timecounter      rx_tstamp_tc;
 295         struct bnxt             *bp;
 296 #define BNXT_MAX_TX_TS  1
 297         uint16_t                        rxctl;
 298 #define BNXT_PTP_MSG_SYNC                       BIT(0)
 299 #define BNXT_PTP_MSG_DELAY_REQ                  BIT(1)
 300 #define BNXT_PTP_MSG_PDELAY_REQ                 BIT(2)
 301 #define BNXT_PTP_MSG_PDELAY_RESP                BIT(3)
 302 #define BNXT_PTP_MSG_FOLLOW_UP                  BIT(8)
 303 #define BNXT_PTP_MSG_DELAY_RESP                 BIT(9)
 304 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP      BIT(10)
 305 #define BNXT_PTP_MSG_ANNOUNCE                   BIT(11)
 306 #define BNXT_PTP_MSG_SIGNALING                  BIT(12)
 307 #define BNXT_PTP_MSG_MANAGEMENT                 BIT(13)
 308 #define BNXT_PTP_MSG_EVENTS             (BNXT_PTP_MSG_SYNC |            \
 309                                          BNXT_PTP_MSG_DELAY_REQ |       \
 310                                          BNXT_PTP_MSG_PDELAY_REQ |      \
 311                                          BNXT_PTP_MSG_PDELAY_RESP)
 312         uint8_t                 tx_tstamp_en:1;
 313         int                     rx_filter;
 314
 315 #define BNXT_PTP_RX_TS_L        0
 316 #define BNXT_PTP_RX_TS_H        1
 317 #define BNXT_PTP_RX_SEQ         2
 318 #define BNXT_PTP_RX_FIFO        3
 319 #define BNXT_PTP_RX_FIFO_PENDING 0x1
 320 #define BNXT_PTP_RX_FIFO_ADV    4
 321 #define BNXT_PTP_RX_REGS        5
 322
 323 #define BNXT_PTP_TX_TS_L        0
 324 #define BNXT_PTP_TX_TS_H        1
 325 #define BNXT_PTP_TX_SEQ         2
 326 #define BNXT_PTP_TX_FIFO        3
 327 #define BNXT_PTP_TX_FIFO_EMPTY   0x2
 328 #define BNXT_PTP_TX_REGS        4
 329         uint32_t                        rx_regs[BNXT_PTP_RX_REGS];
 330         uint32_t                        rx_mapped_regs[BNXT_PTP_RX_REGS];
 331         uint32_t                        tx_regs[BNXT_PTP_TX_REGS];
 332         uint32_t                        tx_mapped_regs[BNXT_PTP_TX_REGS];
 333
 334         /* On Thor, the Rx timestamp is present in the Rx completion record */
 335         uint64_t                        rx_timestamp;
 336 };
 337
 338 struct bnxt_coal {
 339         uint16_t                        num_cmpl_aggr_int;
 340         uint16_t                        num_cmpl_dma_aggr;
 341         uint16_t                        num_cmpl_dma_aggr_during_int;
 342         uint16_t                        int_lat_tmr_max;
 343         uint16_t                        int_lat_tmr_min;
 344         uint16_t                        cmpl_aggr_dma_tmr;
 345         uint16_t                        cmpl_aggr_dma_tmr_during_int;
 346 };
 347
 348 /* 64-bit doorbell */
 349 #define DBR_XID_SFT                             32
 350 #define DBR_PATH_L2                             (0x1ULL << 56)
 351 #define DBR_TYPE_SQ                             (0x0ULL << 60)
 352 #define DBR_TYPE_SRQ                            (0x2ULL << 60)
 353 #define DBR_TYPE_CQ                             (0x4ULL << 60)
 354 #define DBR_TYPE_NQ                             (0xaULL << 60)
 355 #define DBR_TYPE_NQ_ARM                         (0xbULL << 60)
 356
 357 #define BNXT_RSS_TBL_SIZE_THOR          512
 358 #define BNXT_RSS_ENTRIES_PER_CTX_THOR   64
 359 #define BNXT_MAX_RSS_CTXTS_THOR \
 360         (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR)
 361
 362 #define BNXT_MAX_TC    8
 363 #define BNXT_MAX_QUEUE 8
 364 #define BNXT_MAX_TC_Q  (BNXT_MAX_TC + 1)
 365 #define BNXT_MAX_Q     (bp->max_q + 1)
 366 #define BNXT_PAGE_SHFT 12
 367 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
 368 #define MAX_CTX_PAGES  (BNXT_PAGE_SIZE / 8)
 369
 370 #define PTU_PTE_VALID             0x1UL
 371 #define PTU_PTE_LAST              0x2UL
 372 #define PTU_PTE_NEXT_TO_LAST      0x4UL
 373
 374 struct bnxt_ring_mem_info {
 375         int                             nr_pages;
 376         int                             page_size;
 377         uint32_t                        flags;
 378 #define BNXT_RMEM_VALID_PTE_FLAG        1
 379 #define BNXT_RMEM_RING_PTE_FLAG         2
 380
 381         void                            **pg_arr;
 382         rte_iova_t                      *dma_arr;
 383         const struct rte_memzone        *mz;
 384
 385         uint64_t                        *pg_tbl;
 386         rte_iova_t                      pg_tbl_map;
 387         const struct rte_memzone        *pg_tbl_mz;
 388
 389         int                             vmem_size;
 390         void                            **vmem;
 391 };
 392
 393 struct bnxt_ctx_pg_info {
 394         uint32_t        entries;
 395         void            *ctx_pg_arr[MAX_CTX_PAGES];
 396         rte_iova_t      ctx_dma_arr[MAX_CTX_PAGES];
 397         struct bnxt_ring_mem_info ring_mem;
 398 };
 399
 400 struct bnxt_ctx_mem_info {
 401         uint32_t        qp_max_entries;
 402         uint16_t        qp_min_qp1_entries;
 403         uint16_t        qp_max_l2_entries;
 404         uint16_t        qp_entry_size;
 405         uint16_t        srq_max_l2_entries;
 406         uint32_t        srq_max_entries;
 407         uint16_t        srq_entry_size;
 408         uint16_t        cq_max_l2_entries;
 409         uint32_t        cq_max_entries;
 410         uint16_t        cq_entry_size;
 411         uint16_t        vnic_max_vnic_entries;
 412         uint16_t        vnic_max_ring_table_entries;
 413         uint16_t        vnic_entry_size;
 414         uint32_t        stat_max_entries;
 415         uint16_t        stat_entry_size;
 416         uint16_t        tqm_entry_size;
 417         uint32_t        tqm_min_entries_per_ring;
 418         uint32_t        tqm_max_entries_per_ring;
 419         uint32_t        mrav_max_entries;
 420         uint16_t        mrav_entry_size;
 421         uint16_t        tim_entry_size;
 422         uint32_t        tim_max_entries;
 423         uint8_t         tqm_entries_multiple;
 424
 425         uint32_t        flags;
 426 #define BNXT_CTX_FLAG_INITED    0x01
 427
 428         struct bnxt_ctx_pg_info qp_mem;
 429         struct bnxt_ctx_pg_info srq_mem;
 430         struct bnxt_ctx_pg_info cq_mem;
 431         struct bnxt_ctx_pg_info vnic_mem;
 432         struct bnxt_ctx_pg_info stat_mem;
 433         struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q];
 434 };
 435
 436 /* Maximum Firmware Reset bail out value in milliseconds */
 437 #define BNXT_MAX_FW_RESET_TIMEOUT       6000
 438 /* Minimum time required for the firmware readiness in milliseconds */
 439 #define BNXT_MIN_FW_READY_TIMEOUT       2000
 440 /* Frequency for the firmware readiness check in milliseconds */
 441 #define BNXT_FW_READY_WAIT_INTERVAL     100
 442
 443 #define US_PER_MS                       1000
 444 #define NS_PER_US                       1000
 445
 446 struct bnxt_error_recovery_info {
 447         /* All units in milliseconds */
 448         uint32_t        driver_polling_freq;
 449         uint32_t        master_func_wait_period;
 450         uint32_t        normal_func_wait_period;
 451         uint32_t        master_func_wait_period_after_reset;
 452         uint32_t        max_bailout_time_after_reset;
 453 #define BNXT_FW_STATUS_REG              0
 454 #define BNXT_FW_HEARTBEAT_CNT_REG       1
 455 #define BNXT_FW_RECOVERY_CNT_REG        2
 456 #define BNXT_FW_RESET_INPROG_REG        3
 457 #define BNXT_FW_STATUS_REG_CNT          4
 458         uint32_t        status_regs[BNXT_FW_STATUS_REG_CNT];
 459         uint32_t        mapped_status_regs[BNXT_FW_STATUS_REG_CNT];
 460         uint32_t        reset_inprogress_reg_mask;
 461 #define BNXT_NUM_RESET_REG      16
 462         uint8_t         reg_array_cnt;
 463         uint32_t        reset_reg[BNXT_NUM_RESET_REG];
 464         uint32_t        reset_reg_val[BNXT_NUM_RESET_REG];
 465         uint8_t         delay_after_reset[BNXT_NUM_RESET_REG];
 466 #define BNXT_FLAG_ERROR_RECOVERY_HOST   BIT(0)
 467 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1)
 468 #define BNXT_FLAG_MASTER_FUNC           BIT(2)
 469 #define BNXT_FLAG_RECOVERY_ENABLED      BIT(3)
 470         uint32_t        flags;
 471
 472         uint32_t        last_heart_beat;
 473         uint32_t        last_reset_counter;
 474 };
 475
 476 struct bnxt_mark_info {
 477         uint32_t        mark_id;
 478         bool            valid;
 479 };
 480
 481 /* address space location of register */
 482 #define BNXT_FW_STATUS_REG_TYPE_MASK    3
 483 /* register is located in PCIe config space */
 484 #define BNXT_FW_STATUS_REG_TYPE_CFG     0
 485 /* register is located in GRC address space */
 486 #define BNXT_FW_STATUS_REG_TYPE_GRC     1
 487 /* register is located in BAR0  */
 488 #define BNXT_FW_STATUS_REG_TYPE_BAR0    2
 489 /* register is located in BAR1  */
 490 #define BNXT_FW_STATUS_REG_TYPE_BAR1    3
 491
 492 #define BNXT_FW_STATUS_REG_TYPE(reg)    ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK)
 493 #define BNXT_FW_STATUS_REG_OFF(reg)     ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK)
 494
 495 #define BNXT_GRCP_WINDOW_2_BASE         0x2000
 496 #define BNXT_GRCP_WINDOW_3_BASE         0x3000
 497
 498 #define BNXT_FW_STATUS_SHUTDOWN         0x100000
 499
 500 #define BNXT_HWRM_SHORT_REQ_LEN         sizeof(struct hwrm_short_input)
 501 struct bnxt {
 502         void                            *bar0;
 503
 504         struct rte_eth_dev              *eth_dev;
 505         struct rte_eth_rss_conf         rss_conf;
 506         struct rte_pci_device           *pdev;
 507         void                            *doorbell_base;
 508
 509         uint32_t                flags;
 510 #define BNXT_FLAG_REGISTERED            BIT(0)
 511 #define BNXT_FLAG_VF                    BIT(1)
 512 #define BNXT_FLAG_PORT_STATS            BIT(2)
 513 #define BNXT_FLAG_JUMBO                 BIT(3)
 514 #define BNXT_FLAG_SHORT_CMD             BIT(4)
 515 #define BNXT_FLAG_UPDATE_HASH           BIT(5)
 516 #define BNXT_FLAG_PTP_SUPPORTED         BIT(6)
 517 #define BNXT_FLAG_MULTI_HOST            BIT(7)
 518 #define BNXT_FLAG_EXT_RX_PORT_STATS     BIT(8)
 519 #define BNXT_FLAG_EXT_TX_PORT_STATS     BIT(9)
 520 #define BNXT_FLAG_KONG_MB_EN            BIT(10)
 521 #define BNXT_FLAG_TRUSTED_VF_EN         BIT(11)
 522 #define BNXT_FLAG_DFLT_VNIC_SET         BIT(12)
 523 #define BNXT_FLAG_THOR_CHIP             BIT(13)
 524 #define BNXT_FLAG_STINGRAY              BIT(14)
 525 #define BNXT_FLAG_FW_RESET              BIT(15)
 526 #define BNXT_FLAG_FATAL_ERROR           BIT(16)
 527 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE   BIT(17)
 528 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED     BIT(18)
 529 #define BNXT_FLAG_EXT_STATS_SUPPORTED           BIT(19)
 530 #define BNXT_FLAG_NEW_RM                        BIT(20)
 531 #define BNXT_FLAG_NPAR_PF                       BIT(21)
 532 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS         BIT(22)
 533 #define BNXT_FLAG_ADV_FLOW_MGMT                 BIT(23)
 534 #define BNXT_FLAG_RX_VECTOR_PKT_MODE            BIT(24)
 535 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
 536 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
 537 #define BNXT_NPAR(bp)           ((bp)->flags & BNXT_FLAG_NPAR_PF)
 538 #define BNXT_MH(bp)             ((bp)->flags & BNXT_FLAG_MULTI_HOST)
 539 #define BNXT_SINGLE_PF(bp)      (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
 540 #define BNXT_USE_CHIMP_MB       0 //For non-CFA commands, everything uses Chimp.
 541 #define BNXT_USE_KONG(bp)       ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
 542 #define BNXT_VF_IS_TRUSTED(bp)  ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
 543 #define BNXT_CHIP_THOR(bp)      ((bp)->flags & BNXT_FLAG_THOR_CHIP)
 544 #define BNXT_STINGRAY(bp)       ((bp)->flags & BNXT_FLAG_STINGRAY)
 545 #define BNXT_HAS_NQ(bp)         BNXT_CHIP_THOR(bp)
 546 #define BNXT_HAS_RING_GRPS(bp)  (!BNXT_CHIP_THOR(bp))
 547
 548         uint32_t                fw_cap;
 549 #define BNXT_FW_CAP_HOT_RESET           BIT(0)
 550 #define BNXT_FW_CAP_IF_CHANGE           BIT(1)
 551 #define BNXT_FW_CAP_ERROR_RECOVERY      BIT(2)
 552 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD  BIT(3)
 553
 554         uint32_t                flow_flags;
 555 #define BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN     BIT(0)
 556         pthread_mutex_t         flow_lock;
 557
 558         uint32_t                vnic_cap_flags;
 559 #define BNXT_VNIC_CAP_COS_CLASSIFY      BIT(0)
 560         unsigned int            rx_nr_rings;
 561         unsigned int            rx_cp_nr_rings;
 562         unsigned int            rx_num_qs_per_vnic;
 563         struct bnxt_rx_queue **rx_queues;
 564         const void              *rx_mem_zone;
 565         struct rx_port_stats    *hw_rx_port_stats;
 566         rte_iova_t              hw_rx_port_stats_map;
 567         struct rx_port_stats_ext    *hw_rx_port_stats_ext;
 568         rte_iova_t              hw_rx_port_stats_ext_map;
 569         uint16_t                fw_rx_port_stats_ext_size;
 570
 571         unsigned int            tx_nr_rings;
 572         unsigned int            tx_cp_nr_rings;
 573         struct bnxt_tx_queue **tx_queues;
 574         const void              *tx_mem_zone;
 575         struct tx_port_stats    *hw_tx_port_stats;
 576         rte_iova_t              hw_tx_port_stats_map;
 577         struct tx_port_stats_ext    *hw_tx_port_stats_ext;
 578         rte_iova_t              hw_tx_port_stats_ext_map;
 579         uint16_t                fw_tx_port_stats_ext_size;
 580
 581         /* Default completion ring */
 582         struct bnxt_cp_ring_info        *async_cp_ring;
 583         struct bnxt_cp_ring_info        *rxtx_nq_ring;
 584         uint32_t                max_ring_grps;
 585         struct bnxt_ring_grp_info       *grp_info;
 586
 587         unsigned int            nr_vnics;
 588
 589 #define BNXT_GET_DEFAULT_VNIC(bp)       (&(bp)->vnic_info[0])
 590         struct bnxt_vnic_info   *vnic_info;
 591         STAILQ_HEAD(, bnxt_vnic_info)   free_vnic_list;
 592
 593         struct bnxt_filter_info *filter_info;
 594         STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
 595
 596         struct bnxt_irq         *irq_tbl;
 597
 598         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 599
 600         uint16_t                        chimp_cmd_seq;
 601         uint16_t                        kong_cmd_seq;
 602         void                            *hwrm_cmd_resp_addr;
 603         rte_iova_t                      hwrm_cmd_resp_dma_addr;
 604         void                            *hwrm_short_cmd_req_addr;
 605         rte_iova_t                      hwrm_short_cmd_req_dma_addr;
 606         rte_spinlock_t                  hwrm_lock;
 607         pthread_mutex_t                 def_cp_lock;
 608         uint16_t                        max_req_len;
 609         uint16_t                        max_resp_len;
 610         uint16_t                        hwrm_max_ext_req_len;
 611
 612          /* default command timeout value of 500ms */
 613 #define DFLT_HWRM_CMD_TIMEOUT           500000
 614          /* short command timeout value of 50ms */
 615 #define SHORT_HWRM_CMD_TIMEOUT          50000
 616         /* default HWRM request timeout value */
 617         uint32_t                        hwrm_cmd_timeout;
 618
 619         struct bnxt_link_info   link_info;
 620         struct bnxt_cos_queue_info      rx_cos_queue[BNXT_COS_QUEUE_COUNT];
 621         struct bnxt_cos_queue_info      tx_cos_queue[BNXT_COS_QUEUE_COUNT];
 622         uint8_t                 tx_cosq_id[BNXT_COS_QUEUE_COUNT];
 623         uint8_t                 rx_cosq_cnt;
 624         uint8_t                 max_tc;
 625         uint8_t                 max_lltc;
 626         uint8_t                 max_q;
 627
 628         uint16_t                fw_fid;
 629         uint8_t                 dflt_mac_addr[RTE_ETHER_ADDR_LEN];
 630         uint16_t                max_rsscos_ctx;
 631         uint16_t                max_cp_rings;
 632         uint16_t                max_tx_rings;
 633         uint16_t                max_rx_rings;
 634 #define MAX_STINGRAY_RINGS              128U
 635 /* For sake of symmetry, max Tx rings == max Rx rings, one stat ctx for each */
 636 #define BNXT_MAX_RX_RINGS(bp) \
 637         (BNXT_STINGRAY(bp) ? RTE_MIN(RTE_MIN(bp->max_rx_rings, \
 638                                              MAX_STINGRAY_RINGS), \
 639                                      bp->max_stat_ctx / 2U) : \
 640                                 RTE_MIN(bp->max_rx_rings, \
 641                                         bp->max_stat_ctx / 2U))
 642 #define BNXT_MAX_TX_RINGS(bp) \
 643         (RTE_MIN((bp)->max_tx_rings, BNXT_MAX_RX_RINGS(bp)))
 644
 645 #define BNXT_MAX_RINGS(bp) \
 646         (RTE_MIN((((bp)->max_cp_rings - BNXT_NUM_ASYNC_CPR(bp)) / 2U), \
 647                  BNXT_MAX_TX_RINGS(bp)))
 648         uint16_t                max_nq_rings;
 649         uint16_t                max_l2_ctx;
 650         uint16_t                max_rx_em_flows;
 651         uint16_t                max_vnics;
 652         uint16_t                max_stat_ctx;
 653         uint16_t                max_tpa_v2;
 654         uint16_t                first_vf_id;
 655         uint16_t                vlan;
 656 #define BNXT_OUTER_TPID_MASK    0x0000ffff
 657 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000
 658 #define BNXT_OUTER_TPID_BD_SHFT 16
 659         uint32_t                outer_tpid_bd;
 660         struct bnxt_pf_info     pf;
 661         uint8_t                 vxlan_port_cnt;
 662         uint8_t                 geneve_port_cnt;
 663         uint16_t                vxlan_port;
 664         uint16_t                geneve_port;
 665         uint16_t                vxlan_fw_dst_port_id;
 666         uint16_t                geneve_fw_dst_port_id;
 667         uint32_t                fw_ver;
 668         uint32_t                hwrm_spec_code;
 669
 670         struct bnxt_led_info    leds[BNXT_MAX_LED];
 671         uint8_t                 num_leds;
 672         struct bnxt_ptp_cfg     *ptp_cfg;
 673         uint16_t                vf_resv_strategy;
 674         struct bnxt_ctx_mem_info        *ctx;
 675
 676         uint16_t                fw_reset_min_msecs;
 677         uint16_t                fw_reset_max_msecs;
 678
 679         /* Struct to hold adapter error recovery related info */
 680         struct bnxt_error_recovery_info *recovery_info;
 681 #define BNXT_MARK_TABLE_SZ      (sizeof(struct bnxt_mark_info)  * 64 * 1024)
 682 /* TCAM and EM should be 16-bit only. Other modes not supported. */
 683 #define BNXT_FLOW_ID_MASK       0x0000ffff
 684         struct bnxt_mark_info   *mark_table;
 685
 686 #define BNXT_SVIF_INVALID       0xFFFF
 687         uint16_t                func_svif;
 688         uint16_t                port_svif;
 689
 690         struct tf               tfp;
 691         struct bnxt_ulp_context ulp_ctx;
 692         uint8_t                 truflow;
 693 };
 694
 695 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 696 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
 697                      bool exp_link_status);
 698 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
 699 int is_bnxt_in_error(struct bnxt *bp);
 700
 701 int bnxt_map_fw_health_status_regs(struct bnxt *bp);
 702 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index);
 703 void bnxt_schedule_fw_health_check(struct bnxt *bp);
 704
 705 bool is_bnxt_supported(struct rte_eth_dev *dev);
 706 bool bnxt_stratus_device(struct bnxt *bp);
 707 extern const struct rte_flow_ops bnxt_flow_ops;
 708 #define bnxt_acquire_flow_lock(bp) \
 709         pthread_mutex_lock(&(bp)->flow_lock)
 710
 711 #define bnxt_release_flow_lock(bp) \
 712         pthread_mutex_unlock(&(bp)->flow_lock)
 713
 714 #define BNXT_VALID_VNIC_OR_RET(bp, vnic_id) do { \
 715         if ((vnic_id) >= (bp)->max_vnics) { \
 716                 rte_flow_error_set(error, \
 717                                 EINVAL, \
 718                                 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, \
 719                                 NULL, \
 720                                 "Group id is invalid!"); \
 721                 rc = -rte_errno; \
 722                 goto ret; \
 723         } \
 724 } while (0)
 725
 726 extern int bnxt_logtype_driver;
 727 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
 728         rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
 729                 __func__, ## args)
 730
 731 #define PMD_DRV_LOG(level, fmt, args...) \
 732           PMD_DRV_LOG_RAW(level, fmt, ## args)
 733
 734 extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops;
 735 int32_t bnxt_ulp_init(struct bnxt *bp);
 736 void bnxt_ulp_deinit(struct bnxt *bp);
 737
 738 uint16_t bnxt_get_vnic_id(uint16_t port);
 739 uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif);
 740
 741 #endif