drivers/net/bnxt/bnxt.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _BNXT_H_
   7 #define _BNXT_H_
   8
   9 #include <inttypes.h>
  10 #include <stdbool.h>
  11 #include <sys/queue.h>
  12
  13 #include <rte_pci.h>
  14 #include <rte_bus_pci.h>
  15 #include <rte_ethdev_driver.h>
  16 #include <rte_memory.h>
  17 #include <rte_lcore.h>
  18 #include <rte_spinlock.h>
  19 #include <rte_time.h>
  20
  21 #include "bnxt_cpr.h"
  22
  23 #define BNXT_MAX_MTU            9574
  24 #define VLAN_TAG_SIZE           4
  25 #define BNXT_VF_RSV_NUM_RSS_CTX 1
  26 #define BNXT_VF_RSV_NUM_L2_CTX  4
  27 /* TODO: For now, do not support VMDq/RFS on VFs. */
  28 #define BNXT_VF_RSV_NUM_VNIC    1
  29 #define BNXT_MAX_LED            4
  30 #define BNXT_NUM_VLANS          2
  31 #define BNXT_MIN_RING_DESC      16
  32 #define BNXT_MAX_TX_RING_DESC   4096
  33 #define BNXT_MAX_RX_RING_DESC   8192
  34 #define BNXT_DB_SIZE            0x80
  35
  36 /* Chimp Communication Channel */
  37 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET          0x0
  38 #define GRCPF_REG_CHIMP_COMM_TRIGGER            0x100
  39 /* Kong Communication Channel */
  40 #define GRCPF_REG_KONG_CHANNEL_OFFSET           0xA00
  41 #define GRCPF_REG_KONG_COMM_TRIGGER             0xB00
  42
  43 #define BNXT_INT_LAT_TMR_MIN                    75
  44 #define BNXT_INT_LAT_TMR_MAX                    150
  45 #define BNXT_NUM_CMPL_AGGR_INT                  36
  46 #define BNXT_CMPL_AGGR_DMA_TMR                  37
  47 #define BNXT_NUM_CMPL_DMA_AGGR                  36
  48 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT       50
  49 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT       12
  50
  51 struct bnxt_led_info {
  52         uint8_t      led_id;
  53         uint8_t      led_type;
  54         uint8_t      led_group_id;
  55         uint8_t      unused;
  56         uint16_t  led_state_caps;
  57 #define BNXT_LED_ALT_BLINK_CAP(x)       ((x) &  \
  58         rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
  59
  60         uint16_t  led_color_caps;
  61 };
  62
  63 struct bnxt_led_cfg {
  64         uint8_t led_id;
  65         uint8_t led_state;
  66         uint8_t led_color;
  67         uint8_t unused;
  68         uint16_t led_blink_on;
  69         uint16_t led_blink_off;
  70         uint8_t led_group_id;
  71         uint8_t rsvd;
  72 };
  73
  74 #define BNXT_LED_DFLT_ENA                               \
  75         (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID |             \
  76          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE |          \
  77          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON |       \
  78          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF |      \
  79          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
  80
  81 #define BNXT_LED_DFLT_ENA_SHIFT         6
  82
  83 #define BNXT_LED_DFLT_ENABLES(x)                        \
  84         rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
  85
  86 enum bnxt_hw_context {
  87         HW_CONTEXT_NONE     = 0,
  88         HW_CONTEXT_IS_RSS   = 1,
  89         HW_CONTEXT_IS_COS   = 2,
  90         HW_CONTEXT_IS_LB    = 3,
  91 };
  92
  93 struct bnxt_vlan_table_entry {
  94         uint16_t                tpid;
  95         uint16_t                vid;
  96 } __attribute__((packed));
  97
  98 struct bnxt_vlan_antispoof_table_entry {
  99         uint16_t                tpid;
 100         uint16_t                vid;
 101         uint16_t                mask;
 102 } __attribute__((packed));
 103
 104 struct bnxt_child_vf_info {
 105         void                    *req_buf;
 106         struct bnxt_vlan_table_entry    *vlan_table;
 107         struct bnxt_vlan_antispoof_table_entry  *vlan_as_table;
 108         STAILQ_HEAD(, bnxt_filter_info) filter;
 109         uint32_t                func_cfg_flags;
 110         uint32_t                l2_rx_mask;
 111         uint16_t                fid;
 112         uint16_t                max_tx_rate;
 113         uint16_t                dflt_vlan;
 114         uint16_t                vlan_count;
 115         uint8_t                 mac_spoof_en;
 116         uint8_t                 vlan_spoof_en;
 117         bool                    random_mac;
 118         bool                    persist_stats;
 119 };
 120
 121 struct bnxt_pf_info {
 122 #define BNXT_FIRST_PF_FID       1
 123 #define BNXT_MAX_VFS(bp)        (bp->pf.max_vfs)
 124 #define BNXT_TOTAL_VFS(bp)      ((bp)->pf.total_vfs)
 125 #define BNXT_FIRST_VF_FID       128
 126 #define BNXT_PF_RINGS_USED(bp)  bnxt_get_num_queues(bp)
 127 #define BNXT_PF_RINGS_AVAIL(bp) (bp->pf.max_cp_rings - BNXT_PF_RINGS_USED(bp))
 128         uint16_t                port_id;
 129         uint16_t                first_vf_id;
 130         uint16_t                active_vfs;
 131         uint16_t                max_vfs;
 132         uint16_t                total_vfs; /* Total VFs possible.
 133                                             * Not necessarily enabled.
 134                                             */
 135         uint32_t                func_cfg_flags;
 136         void                    *vf_req_buf;
 137         rte_iova_t              vf_req_buf_dma_addr;
 138         uint32_t                vf_req_fwd[8];
 139         uint16_t                total_vnics;
 140         struct bnxt_child_vf_info       *vf_info;
 141 #define BNXT_EVB_MODE_NONE      0
 142 #define BNXT_EVB_MODE_VEB       1
 143 #define BNXT_EVB_MODE_VEPA      2
 144         uint8_t                 evb_mode;
 145 };
 146
 147 /* Max wait time is 10 * 100ms = 1s */
 148 #define BNXT_LINK_WAIT_CNT      10
 149 #define BNXT_LINK_WAIT_INTERVAL 100
 150 struct bnxt_link_info {
 151         uint32_t                phy_flags;
 152         uint8_t                 mac_type;
 153         uint8_t                 phy_link_status;
 154         uint8_t                 loop_back;
 155         uint8_t                 link_up;
 156         uint8_t                 duplex;
 157         uint8_t                 pause;
 158         uint8_t                 force_pause;
 159         uint8_t                 auto_pause;
 160         uint8_t                 auto_mode;
 161 #define PHY_VER_LEN             3
 162         uint8_t                 phy_ver[PHY_VER_LEN];
 163         uint16_t                link_speed;
 164         uint16_t                support_speeds;
 165         uint16_t                auto_link_speed;
 166         uint16_t                force_link_speed;
 167         uint16_t                auto_link_speed_mask;
 168         uint32_t                preemphasis;
 169         uint8_t                 phy_type;
 170         uint8_t                 media_type;
 171 };
 172
 173 #define BNXT_COS_QUEUE_COUNT    8
 174 struct bnxt_cos_queue_info {
 175         uint8_t id;
 176         uint8_t profile;
 177 };
 178
 179 struct rte_flow {
 180         STAILQ_ENTRY(rte_flow) next;
 181         struct bnxt_filter_info *filter;
 182         struct bnxt_vnic_info   *vnic;
 183 };
 184
 185 struct bnxt_ptp_cfg {
 186 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT  0x400
 187 #define BNXT_GRCPF_REG_SYNC_TIME        0x480
 188 #define BNXT_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 189         struct rte_timecounter      tc;
 190         struct rte_timecounter      tx_tstamp_tc;
 191         struct rte_timecounter      rx_tstamp_tc;
 192         struct bnxt             *bp;
 193 #define BNXT_MAX_TX_TS  1
 194         uint16_t                        rxctl;
 195 #define BNXT_PTP_MSG_SYNC                       (1 << 0)
 196 #define BNXT_PTP_MSG_DELAY_REQ                  (1 << 1)
 197 #define BNXT_PTP_MSG_PDELAY_REQ                 (1 << 2)
 198 #define BNXT_PTP_MSG_PDELAY_RESP                (1 << 3)
 199 #define BNXT_PTP_MSG_FOLLOW_UP                  (1 << 8)
 200 #define BNXT_PTP_MSG_DELAY_RESP                 (1 << 9)
 201 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP      (1 << 10)
 202 #define BNXT_PTP_MSG_ANNOUNCE                   (1 << 11)
 203 #define BNXT_PTP_MSG_SIGNALING                  (1 << 12)
 204 #define BNXT_PTP_MSG_MANAGEMENT                 (1 << 13)
 205 #define BNXT_PTP_MSG_EVENTS             (BNXT_PTP_MSG_SYNC |            \
 206                                          BNXT_PTP_MSG_DELAY_REQ |       \
 207                                          BNXT_PTP_MSG_PDELAY_REQ |      \
 208                                          BNXT_PTP_MSG_PDELAY_RESP)
 209         uint8_t                 tx_tstamp_en:1;
 210         int                     rx_filter;
 211
 212 #define BNXT_PTP_RX_TS_L        0
 213 #define BNXT_PTP_RX_TS_H        1
 214 #define BNXT_PTP_RX_SEQ         2
 215 #define BNXT_PTP_RX_FIFO        3
 216 #define BNXT_PTP_RX_FIFO_PENDING 0x1
 217 #define BNXT_PTP_RX_FIFO_ADV    4
 218 #define BNXT_PTP_RX_REGS        5
 219
 220 #define BNXT_PTP_TX_TS_L        0
 221 #define BNXT_PTP_TX_TS_H        1
 222 #define BNXT_PTP_TX_SEQ         2
 223 #define BNXT_PTP_TX_FIFO        3
 224 #define BNXT_PTP_TX_FIFO_EMPTY   0x2
 225 #define BNXT_PTP_TX_REGS        4
 226         uint32_t                        rx_regs[BNXT_PTP_RX_REGS];
 227         uint32_t                        rx_mapped_regs[BNXT_PTP_RX_REGS];
 228         uint32_t                        tx_regs[BNXT_PTP_TX_REGS];
 229         uint32_t                        tx_mapped_regs[BNXT_PTP_TX_REGS];
 230 };
 231
 232 struct bnxt_coal {
 233         uint16_t                        num_cmpl_aggr_int;
 234         uint16_t                        num_cmpl_dma_aggr;
 235         uint16_t                        num_cmpl_dma_aggr_during_int;
 236         uint16_t                        int_lat_tmr_max;
 237         uint16_t                        int_lat_tmr_min;
 238         uint16_t                        cmpl_aggr_dma_tmr;
 239         uint16_t                        cmpl_aggr_dma_tmr_during_int;
 240 };
 241
 242 /* 64-bit doorbell */
 243 #define DBR_XID_SFT                             32
 244 #define DBR_PATH_L2                             (0x1ULL << 56)
 245 #define DBR_TYPE_SQ                             (0x0ULL << 60)
 246 #define DBR_TYPE_SRQ                            (0x2ULL << 60)
 247 #define DBR_TYPE_CQ                             (0x4ULL << 60)
 248 #define DBR_TYPE_NQ                             (0xaULL << 60)
 249
 250 #define BNXT_RSS_TBL_SIZE_THOR          512
 251 #define BNXT_RSS_ENTRIES_PER_CTX_THOR   64
 252 #define BNXT_MAX_RSS_CTXTS_THOR \
 253         (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR)
 254
 255 #define BNXT_MAX_TC    8
 256 #define BNXT_MAX_QUEUE 8
 257 #define BNXT_MAX_TC_Q  (BNXT_MAX_TC + 1)
 258 #define BNXT_MAX_Q     (bp->max_q + 1)
 259 #define BNXT_PAGE_SHFT 12
 260 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
 261 #define MAX_CTX_PAGES  (BNXT_PAGE_SIZE / 8)
 262
 263 #define PTU_PTE_VALID             0x1UL
 264 #define PTU_PTE_LAST              0x2UL
 265 #define PTU_PTE_NEXT_TO_LAST      0x4UL
 266
 267 struct bnxt_ring_mem_info {
 268         int                             nr_pages;
 269         int                             page_size;
 270         uint32_t                        flags;
 271 #define BNXT_RMEM_VALID_PTE_FLAG        1
 272 #define BNXT_RMEM_RING_PTE_FLAG         2
 273
 274         void                            **pg_arr;
 275         rte_iova_t                      *dma_arr;
 276         const struct rte_memzone        *mz;
 277
 278         uint64_t                        *pg_tbl;
 279         rte_iova_t                      pg_tbl_map;
 280         const struct rte_memzone        *pg_tbl_mz;
 281
 282         int                             vmem_size;
 283         void                            **vmem;
 284 };
 285
 286 struct bnxt_ctx_pg_info {
 287         uint32_t        entries;
 288         void            *ctx_pg_arr[MAX_CTX_PAGES];
 289         rte_iova_t      ctx_dma_arr[MAX_CTX_PAGES];
 290         struct bnxt_ring_mem_info ring_mem;
 291 };
 292
 293 struct bnxt_ctx_mem_info {
 294         uint32_t        qp_max_entries;
 295         uint16_t        qp_min_qp1_entries;
 296         uint16_t        qp_max_l2_entries;
 297         uint16_t        qp_entry_size;
 298         uint16_t        srq_max_l2_entries;
 299         uint32_t        srq_max_entries;
 300         uint16_t        srq_entry_size;
 301         uint16_t        cq_max_l2_entries;
 302         uint32_t        cq_max_entries;
 303         uint16_t        cq_entry_size;
 304         uint16_t        vnic_max_vnic_entries;
 305         uint16_t        vnic_max_ring_table_entries;
 306         uint16_t        vnic_entry_size;
 307         uint32_t        stat_max_entries;
 308         uint16_t        stat_entry_size;
 309         uint16_t        tqm_entry_size;
 310         uint32_t        tqm_min_entries_per_ring;
 311         uint32_t        tqm_max_entries_per_ring;
 312         uint32_t        mrav_max_entries;
 313         uint16_t        mrav_entry_size;
 314         uint16_t        tim_entry_size;
 315         uint32_t        tim_max_entries;
 316         uint8_t         tqm_entries_multiple;
 317
 318         uint32_t        flags;
 319 #define BNXT_CTX_FLAG_INITED    0x01
 320
 321         struct bnxt_ctx_pg_info qp_mem;
 322         struct bnxt_ctx_pg_info srq_mem;
 323         struct bnxt_ctx_pg_info cq_mem;
 324         struct bnxt_ctx_pg_info vnic_mem;
 325         struct bnxt_ctx_pg_info stat_mem;
 326         struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q];
 327 };
 328
 329 #define BNXT_HWRM_SHORT_REQ_LEN         sizeof(struct hwrm_short_input)
 330 struct bnxt {
 331         void                            *bar0;
 332
 333         struct rte_eth_dev              *eth_dev;
 334         struct rte_eth_rss_conf         rss_conf;
 335         struct rte_pci_device           *pdev;
 336         void                            *doorbell_base;
 337
 338         uint32_t                flags;
 339 #define BNXT_FLAG_REGISTERED    (1 << 0)
 340 #define BNXT_FLAG_VF            (1 << 1)
 341 #define BNXT_FLAG_PORT_STATS    (1 << 2)
 342 #define BNXT_FLAG_JUMBO         (1 << 3)
 343 #define BNXT_FLAG_SHORT_CMD     (1 << 4)
 344 #define BNXT_FLAG_UPDATE_HASH   (1 << 5)
 345 #define BNXT_FLAG_PTP_SUPPORTED (1 << 6)
 346 #define BNXT_FLAG_MULTI_HOST    (1 << 7)
 347 #define BNXT_FLAG_EXT_RX_PORT_STATS     (1 << 8)
 348 #define BNXT_FLAG_EXT_TX_PORT_STATS     (1 << 9)
 349 #define BNXT_FLAG_KONG_MB_EN    (1 << 10)
 350 #define BNXT_FLAG_TRUSTED_VF_EN (1 << 11)
 351 #define BNXT_FLAG_DFLT_VNIC_SET (1 << 12)
 352 #define BNXT_FLAG_THOR_CHIP     (1 << 13)
 353 #define BNXT_FLAG_NEW_RM        (1 << 30)
 354 #define BNXT_FLAG_INIT_DONE     (1U << 31)
 355 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
 356 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
 357 #define BNXT_NPAR(bp)           ((bp)->port_partition_type)
 358 #define BNXT_MH(bp)             ((bp)->flags & BNXT_FLAG_MULTI_HOST)
 359 #define BNXT_SINGLE_PF(bp)      (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
 360 #define BNXT_USE_CHIMP_MB       0 //For non-CFA commands, everything uses Chimp.
 361 #define BNXT_USE_KONG(bp)       ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
 362 #define BNXT_VF_IS_TRUSTED(bp)  ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
 363 #define BNXT_CHIP_THOR(bp)      ((bp)->flags & BNXT_FLAG_THOR_CHIP)
 364 #define BNXT_HAS_NQ(bp)         BNXT_CHIP_THOR(bp)
 365 #define BNXT_HAS_RING_GRPS(bp)  (!BNXT_CHIP_THOR(bp))
 366
 367         unsigned int            rx_nr_rings;
 368         unsigned int            rx_cp_nr_rings;
 369         struct bnxt_rx_queue **rx_queues;
 370         const void              *rx_mem_zone;
 371         struct rx_port_stats    *hw_rx_port_stats;
 372         rte_iova_t              hw_rx_port_stats_map;
 373         struct rx_port_stats_ext    *hw_rx_port_stats_ext;
 374         rte_iova_t              hw_rx_port_stats_ext_map;
 375         uint16_t                fw_rx_port_stats_ext_size;
 376
 377         unsigned int            tx_nr_rings;
 378         unsigned int            tx_cp_nr_rings;
 379         struct bnxt_tx_queue **tx_queues;
 380         const void              *tx_mem_zone;
 381         struct tx_port_stats    *hw_tx_port_stats;
 382         rte_iova_t              hw_tx_port_stats_map;
 383         struct tx_port_stats_ext    *hw_tx_port_stats_ext;
 384         rte_iova_t              hw_tx_port_stats_ext_map;
 385         uint16_t                fw_tx_port_stats_ext_size;
 386
 387         /* Default completion ring */
 388         struct bnxt_cp_ring_info        *def_cp_ring;
 389         uint32_t                max_ring_grps;
 390         struct bnxt_ring_grp_info       *grp_info;
 391
 392         unsigned int            nr_vnics;
 393
 394         struct bnxt_vnic_info   *vnic_info;
 395         STAILQ_HEAD(, bnxt_vnic_info)   free_vnic_list;
 396
 397         struct bnxt_filter_info *filter_info;
 398         STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
 399
 400         struct bnxt_irq         *irq_tbl;
 401
 402 #define MAX_NUM_MAC_ADDR        32
 403         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 404
 405         uint16_t                        hwrm_cmd_seq;
 406         uint16_t                        kong_cmd_seq;
 407         void                            *hwrm_cmd_resp_addr;
 408         rte_iova_t                      hwrm_cmd_resp_dma_addr;
 409         void                            *hwrm_short_cmd_req_addr;
 410         rte_iova_t                      hwrm_short_cmd_req_dma_addr;
 411         rte_spinlock_t                  hwrm_lock;
 412         uint16_t                        max_req_len;
 413         uint16_t                        max_resp_len;
 414         uint16_t                        hwrm_max_ext_req_len;
 415
 416         struct bnxt_link_info   link_info;
 417         struct bnxt_cos_queue_info      cos_queue[BNXT_COS_QUEUE_COUNT];
 418         uint8_t                 tx_cosq_id;
 419         uint8_t                 max_tc;
 420         uint8_t                 max_lltc;
 421         uint8_t                 max_q;
 422
 423         uint16_t                fw_fid;
 424         uint8_t                 dflt_mac_addr[RTE_ETHER_ADDR_LEN];
 425         uint16_t                max_rsscos_ctx;
 426         uint16_t                max_cp_rings;
 427         uint16_t                max_tx_rings;
 428         uint16_t                max_rx_rings;
 429         uint16_t                max_nq_rings;
 430         uint16_t                max_l2_ctx;
 431         uint16_t                max_vnics;
 432         uint16_t                max_stat_ctx;
 433         uint16_t                vlan;
 434         struct bnxt_pf_info     pf;
 435         uint8_t                 port_partition_type;
 436         uint8_t                 dev_stopped;
 437         uint8_t                 vxlan_port_cnt;
 438         uint8_t                 geneve_port_cnt;
 439         uint16_t                vxlan_port;
 440         uint16_t                geneve_port;
 441         uint16_t                vxlan_fw_dst_port_id;
 442         uint16_t                geneve_fw_dst_port_id;
 443         uint32_t                fw_ver;
 444         uint32_t                hwrm_spec_code;
 445
 446         struct bnxt_led_info    leds[BNXT_MAX_LED];
 447         uint8_t                 num_leds;
 448         struct bnxt_ptp_cfg     *ptp_cfg;
 449         uint16_t                vf_resv_strategy;
 450         struct bnxt_ctx_mem_info        *ctx;
 451 };
 452
 453 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete);
 454 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
 455
 456 bool is_bnxt_supported(struct rte_eth_dev *dev);
 457 bool bnxt_stratus_device(struct bnxt *bp);
 458 extern const struct rte_flow_ops bnxt_flow_ops;
 459
 460 extern int bnxt_logtype_driver;
 461 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
 462         rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
 463                 __func__, ## args)
 464
 465 #define PMD_DRV_LOG(level, fmt, args...) \
 466         PMD_DRV_LOG_RAW(level, fmt, ## args)
 467 #endif