drivers/net/bnxt/bnxt.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _BNXT_H_
   7 #define _BNXT_H_
   8
   9 #include <inttypes.h>
  10 #include <stdbool.h>
  11 #include <sys/queue.h>
  12
  13 #include <rte_pci.h>
  14 #include <rte_bus_pci.h>
  15 #include <rte_ethdev_driver.h>
  16 #include <rte_memory.h>
  17 #include <rte_lcore.h>
  18 #include <rte_spinlock.h>
  19 #include <rte_time.h>
  20
  21 #include "bnxt_cpr.h"
  22
  23 #define BNXT_MAX_MTU            9574
  24 #define VLAN_TAG_SIZE           4
  25 #define BNXT_VF_RSV_NUM_RSS_CTX 1
  26 #define BNXT_VF_RSV_NUM_L2_CTX  4
  27 /* TODO: For now, do not support VMDq/RFS on VFs. */
  28 #define BNXT_VF_RSV_NUM_VNIC    1
  29 #define BNXT_MAX_LED            4
  30 #define BNXT_NUM_VLANS          2
  31 #define BNXT_MIN_RING_DESC      16
  32 #define BNXT_MAX_TX_RING_DESC   4096
  33 #define BNXT_MAX_RX_RING_DESC   8192
  34 #define BNXT_DB_SIZE            0x80
  35
  36 #ifdef RTE_ARCH_ARM64
  37 #define BNXT_NUM_ASYNC_CPR(bp) (BNXT_STINGRAY(bp) ? 0 : 1)
  38 #else
  39 #define BNXT_NUM_ASYNC_CPR(bp) 1
  40 #endif
  41
  42 /* Chimp Communication Channel */
  43 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET          0x0
  44 #define GRCPF_REG_CHIMP_COMM_TRIGGER            0x100
  45 /* Kong Communication Channel */
  46 #define GRCPF_REG_KONG_CHANNEL_OFFSET           0xA00
  47 #define GRCPF_REG_KONG_COMM_TRIGGER             0xB00
  48
  49 #define BNXT_INT_LAT_TMR_MIN                    75
  50 #define BNXT_INT_LAT_TMR_MAX                    150
  51 #define BNXT_NUM_CMPL_AGGR_INT                  36
  52 #define BNXT_CMPL_AGGR_DMA_TMR                  37
  53 #define BNXT_NUM_CMPL_DMA_AGGR                  36
  54 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT       50
  55 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT       12
  56
  57 struct bnxt_led_info {
  58         uint8_t      led_id;
  59         uint8_t      led_type;
  60         uint8_t      led_group_id;
  61         uint8_t      unused;
  62         uint16_t  led_state_caps;
  63 #define BNXT_LED_ALT_BLINK_CAP(x)       ((x) &  \
  64         rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
  65
  66         uint16_t  led_color_caps;
  67 };
  68
  69 struct bnxt_led_cfg {
  70         uint8_t led_id;
  71         uint8_t led_state;
  72         uint8_t led_color;
  73         uint8_t unused;
  74         uint16_t led_blink_on;
  75         uint16_t led_blink_off;
  76         uint8_t led_group_id;
  77         uint8_t rsvd;
  78 };
  79
  80 #define BNXT_LED_DFLT_ENA                               \
  81         (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID |             \
  82          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE |          \
  83          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON |       \
  84          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF |      \
  85          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
  86
  87 #define BNXT_LED_DFLT_ENA_SHIFT         6
  88
  89 #define BNXT_LED_DFLT_ENABLES(x)                        \
  90         rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
  91
  92 enum bnxt_hw_context {
  93         HW_CONTEXT_NONE     = 0,
  94         HW_CONTEXT_IS_RSS   = 1,
  95         HW_CONTEXT_IS_COS   = 2,
  96         HW_CONTEXT_IS_LB    = 3,
  97 };
  98
  99 struct bnxt_vlan_table_entry {
 100         uint16_t                tpid;
 101         uint16_t                vid;
 102 } __attribute__((packed));
 103
 104 struct bnxt_vlan_antispoof_table_entry {
 105         uint16_t                tpid;
 106         uint16_t                vid;
 107         uint16_t                mask;
 108 } __attribute__((packed));
 109
 110 struct bnxt_child_vf_info {
 111         void                    *req_buf;
 112         struct bnxt_vlan_table_entry    *vlan_table;
 113         struct bnxt_vlan_antispoof_table_entry  *vlan_as_table;
 114         STAILQ_HEAD(, bnxt_filter_info) filter;
 115         uint32_t                func_cfg_flags;
 116         uint32_t                l2_rx_mask;
 117         uint16_t                fid;
 118         uint16_t                max_tx_rate;
 119         uint16_t                dflt_vlan;
 120         uint16_t                vlan_count;
 121         uint8_t                 mac_spoof_en;
 122         uint8_t                 vlan_spoof_en;
 123         bool                    random_mac;
 124         bool                    persist_stats;
 125 };
 126
 127 struct bnxt_pf_info {
 128 #define BNXT_FIRST_PF_FID       1
 129 #define BNXT_MAX_VFS(bp)        (bp->pf.max_vfs)
 130 #define BNXT_TOTAL_VFS(bp)      ((bp)->pf.total_vfs)
 131 #define BNXT_FIRST_VF_FID       128
 132 #define BNXT_PF_RINGS_USED(bp)  bnxt_get_num_queues(bp)
 133 #define BNXT_PF_RINGS_AVAIL(bp) (bp->pf.max_cp_rings - BNXT_PF_RINGS_USED(bp))
 134         uint16_t                port_id;
 135         uint16_t                first_vf_id;
 136         uint16_t                active_vfs;
 137         uint16_t                max_vfs;
 138         uint16_t                total_vfs; /* Total VFs possible.
 139                                             * Not necessarily enabled.
 140                                             */
 141         uint32_t                func_cfg_flags;
 142         void                    *vf_req_buf;
 143         rte_iova_t              vf_req_buf_dma_addr;
 144         uint32_t                vf_req_fwd[8];
 145         uint16_t                total_vnics;
 146         struct bnxt_child_vf_info       *vf_info;
 147 #define BNXT_EVB_MODE_NONE      0
 148 #define BNXT_EVB_MODE_VEB       1
 149 #define BNXT_EVB_MODE_VEPA      2
 150         uint8_t                 evb_mode;
 151 };
 152
 153 /* Max wait time is 10 * 100ms = 1s */
 154 #define BNXT_LINK_WAIT_CNT      10
 155 #define BNXT_LINK_WAIT_INTERVAL 100
 156 struct bnxt_link_info {
 157         uint32_t                phy_flags;
 158         uint8_t                 mac_type;
 159         uint8_t                 phy_link_status;
 160         uint8_t                 loop_back;
 161         uint8_t                 link_up;
 162         uint8_t                 duplex;
 163         uint8_t                 pause;
 164         uint8_t                 force_pause;
 165         uint8_t                 auto_pause;
 166         uint8_t                 auto_mode;
 167 #define PHY_VER_LEN             3
 168         uint8_t                 phy_ver[PHY_VER_LEN];
 169         uint16_t                link_speed;
 170         uint16_t                support_speeds;
 171         uint16_t                auto_link_speed;
 172         uint16_t                force_link_speed;
 173         uint16_t                auto_link_speed_mask;
 174         uint32_t                preemphasis;
 175         uint8_t                 phy_type;
 176         uint8_t                 media_type;
 177 };
 178
 179 #define BNXT_COS_QUEUE_COUNT    8
 180 struct bnxt_cos_queue_info {
 181         uint8_t id;
 182         uint8_t profile;
 183 };
 184
 185 struct rte_flow {
 186         STAILQ_ENTRY(rte_flow) next;
 187         struct bnxt_filter_info *filter;
 188         struct bnxt_vnic_info   *vnic;
 189 };
 190
 191 struct bnxt_ptp_cfg {
 192 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT  0x400
 193 #define BNXT_GRCPF_REG_SYNC_TIME        0x480
 194 #define BNXT_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 195         struct rte_timecounter      tc;
 196         struct rte_timecounter      tx_tstamp_tc;
 197         struct rte_timecounter      rx_tstamp_tc;
 198         struct bnxt             *bp;
 199 #define BNXT_MAX_TX_TS  1
 200         uint16_t                        rxctl;
 201 #define BNXT_PTP_MSG_SYNC                       (1 << 0)
 202 #define BNXT_PTP_MSG_DELAY_REQ                  (1 << 1)
 203 #define BNXT_PTP_MSG_PDELAY_REQ                 (1 << 2)
 204 #define BNXT_PTP_MSG_PDELAY_RESP                (1 << 3)
 205 #define BNXT_PTP_MSG_FOLLOW_UP                  (1 << 8)
 206 #define BNXT_PTP_MSG_DELAY_RESP                 (1 << 9)
 207 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP      (1 << 10)
 208 #define BNXT_PTP_MSG_ANNOUNCE                   (1 << 11)
 209 #define BNXT_PTP_MSG_SIGNALING                  (1 << 12)
 210 #define BNXT_PTP_MSG_MANAGEMENT                 (1 << 13)
 211 #define BNXT_PTP_MSG_EVENTS             (BNXT_PTP_MSG_SYNC |            \
 212                                          BNXT_PTP_MSG_DELAY_REQ |       \
 213                                          BNXT_PTP_MSG_PDELAY_REQ |      \
 214                                          BNXT_PTP_MSG_PDELAY_RESP)
 215         uint8_t                 tx_tstamp_en:1;
 216         int                     rx_filter;
 217
 218 #define BNXT_PTP_RX_TS_L        0
 219 #define BNXT_PTP_RX_TS_H        1
 220 #define BNXT_PTP_RX_SEQ         2
 221 #define BNXT_PTP_RX_FIFO        3
 222 #define BNXT_PTP_RX_FIFO_PENDING 0x1
 223 #define BNXT_PTP_RX_FIFO_ADV    4
 224 #define BNXT_PTP_RX_REGS        5
 225
 226 #define BNXT_PTP_TX_TS_L        0
 227 #define BNXT_PTP_TX_TS_H        1
 228 #define BNXT_PTP_TX_SEQ         2
 229 #define BNXT_PTP_TX_FIFO        3
 230 #define BNXT_PTP_TX_FIFO_EMPTY   0x2
 231 #define BNXT_PTP_TX_REGS        4
 232         uint32_t                        rx_regs[BNXT_PTP_RX_REGS];
 233         uint32_t                        rx_mapped_regs[BNXT_PTP_RX_REGS];
 234         uint32_t                        tx_regs[BNXT_PTP_TX_REGS];
 235         uint32_t                        tx_mapped_regs[BNXT_PTP_TX_REGS];
 236 };
 237
 238 struct bnxt_coal {
 239         uint16_t                        num_cmpl_aggr_int;
 240         uint16_t                        num_cmpl_dma_aggr;
 241         uint16_t                        num_cmpl_dma_aggr_during_int;
 242         uint16_t                        int_lat_tmr_max;
 243         uint16_t                        int_lat_tmr_min;
 244         uint16_t                        cmpl_aggr_dma_tmr;
 245         uint16_t                        cmpl_aggr_dma_tmr_during_int;
 246 };
 247
 248 /* 64-bit doorbell */
 249 #define DBR_XID_SFT                             32
 250 #define DBR_PATH_L2                             (0x1ULL << 56)
 251 #define DBR_TYPE_SQ                             (0x0ULL << 60)
 252 #define DBR_TYPE_SRQ                            (0x2ULL << 60)
 253 #define DBR_TYPE_CQ                             (0x4ULL << 60)
 254 #define DBR_TYPE_NQ                             (0xaULL << 60)
 255 #define DBR_TYPE_NQ_ARM                         (0xbULL << 60)
 256
 257 #define BNXT_RSS_TBL_SIZE_THOR          512
 258 #define BNXT_RSS_ENTRIES_PER_CTX_THOR   64
 259 #define BNXT_MAX_RSS_CTXTS_THOR \
 260         (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR)
 261
 262 #define BNXT_MAX_TC    8
 263 #define BNXT_MAX_QUEUE 8
 264 #define BNXT_MAX_TC_Q  (BNXT_MAX_TC + 1)
 265 #define BNXT_MAX_Q     (bp->max_q + 1)
 266 #define BNXT_PAGE_SHFT 12
 267 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
 268 #define MAX_CTX_PAGES  (BNXT_PAGE_SIZE / 8)
 269
 270 #define PTU_PTE_VALID             0x1UL
 271 #define PTU_PTE_LAST              0x2UL
 272 #define PTU_PTE_NEXT_TO_LAST      0x4UL
 273
 274 struct bnxt_ring_mem_info {
 275         int                             nr_pages;
 276         int                             page_size;
 277         uint32_t                        flags;
 278 #define BNXT_RMEM_VALID_PTE_FLAG        1
 279 #define BNXT_RMEM_RING_PTE_FLAG         2
 280
 281         void                            **pg_arr;
 282         rte_iova_t                      *dma_arr;
 283         const struct rte_memzone        *mz;
 284
 285         uint64_t                        *pg_tbl;
 286         rte_iova_t                      pg_tbl_map;
 287         const struct rte_memzone        *pg_tbl_mz;
 288
 289         int                             vmem_size;
 290         void                            **vmem;
 291 };
 292
 293 struct bnxt_ctx_pg_info {
 294         uint32_t        entries;
 295         void            *ctx_pg_arr[MAX_CTX_PAGES];
 296         rte_iova_t      ctx_dma_arr[MAX_CTX_PAGES];
 297         struct bnxt_ring_mem_info ring_mem;
 298 };
 299
 300 struct bnxt_ctx_mem_info {
 301         uint32_t        qp_max_entries;
 302         uint16_t        qp_min_qp1_entries;
 303         uint16_t        qp_max_l2_entries;
 304         uint16_t        qp_entry_size;
 305         uint16_t        srq_max_l2_entries;
 306         uint32_t        srq_max_entries;
 307         uint16_t        srq_entry_size;
 308         uint16_t        cq_max_l2_entries;
 309         uint32_t        cq_max_entries;
 310         uint16_t        cq_entry_size;
 311         uint16_t        vnic_max_vnic_entries;
 312         uint16_t        vnic_max_ring_table_entries;
 313         uint16_t        vnic_entry_size;
 314         uint32_t        stat_max_entries;
 315         uint16_t        stat_entry_size;
 316         uint16_t        tqm_entry_size;
 317         uint32_t        tqm_min_entries_per_ring;
 318         uint32_t        tqm_max_entries_per_ring;
 319         uint32_t        mrav_max_entries;
 320         uint16_t        mrav_entry_size;
 321         uint16_t        tim_entry_size;
 322         uint32_t        tim_max_entries;
 323         uint8_t         tqm_entries_multiple;
 324
 325         uint32_t        flags;
 326 #define BNXT_CTX_FLAG_INITED    0x01
 327
 328         struct bnxt_ctx_pg_info qp_mem;
 329         struct bnxt_ctx_pg_info srq_mem;
 330         struct bnxt_ctx_pg_info cq_mem;
 331         struct bnxt_ctx_pg_info vnic_mem;
 332         struct bnxt_ctx_pg_info stat_mem;
 333         struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q];
 334 };
 335
 336 /* Maximum Firmware Reset bail out value in milliseconds */
 337 #define BNXT_MAX_FW_RESET_TIMEOUT       6000
 338 /* Minimum time required for the firmware readiness in milliseconds */
 339 #define BNXT_MIN_FW_READY_TIMEOUT       2000
 340 /* Frequency for the firmware readiness check in milliseconds */
 341 #define BNXT_FW_READY_WAIT_INTERVAL     100
 342
 343 #define US_PER_MS                       1000
 344 #define NS_PER_US                       1000
 345
 346 #define BNXT_HWRM_SHORT_REQ_LEN         sizeof(struct hwrm_short_input)
 347 struct bnxt {
 348         void                            *bar0;
 349
 350         struct rte_eth_dev              *eth_dev;
 351         struct rte_eth_rss_conf         rss_conf;
 352         struct rte_pci_device           *pdev;
 353         void                            *doorbell_base;
 354
 355         uint32_t                flags;
 356 #define BNXT_FLAG_REGISTERED    (1 << 0)
 357 #define BNXT_FLAG_VF            (1 << 1)
 358 #define BNXT_FLAG_PORT_STATS    (1 << 2)
 359 #define BNXT_FLAG_JUMBO         (1 << 3)
 360 #define BNXT_FLAG_SHORT_CMD     (1 << 4)
 361 #define BNXT_FLAG_UPDATE_HASH   (1 << 5)
 362 #define BNXT_FLAG_PTP_SUPPORTED (1 << 6)
 363 #define BNXT_FLAG_MULTI_HOST    (1 << 7)
 364 #define BNXT_FLAG_EXT_RX_PORT_STATS     (1 << 8)
 365 #define BNXT_FLAG_EXT_TX_PORT_STATS     (1 << 9)
 366 #define BNXT_FLAG_KONG_MB_EN    (1 << 10)
 367 #define BNXT_FLAG_TRUSTED_VF_EN (1 << 11)
 368 #define BNXT_FLAG_DFLT_VNIC_SET (1 << 12)
 369 #define BNXT_FLAG_THOR_CHIP     (1 << 13)
 370 #define BNXT_FLAG_STINGRAY      (1 << 14)
 371 #define BNXT_FLAG_FW_RESET      (1 << 15)
 372 #define BNXT_FLAG_FATAL_ERROR   (1 << 16)
 373 #define BNXT_FLAG_EXT_STATS_SUPPORTED   (1 << 29)
 374 #define BNXT_FLAG_NEW_RM        (1 << 30)
 375 #define BNXT_FLAG_INIT_DONE     (1U << 31)
 376 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
 377 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
 378 #define BNXT_NPAR(bp)           ((bp)->port_partition_type)
 379 #define BNXT_MH(bp)             ((bp)->flags & BNXT_FLAG_MULTI_HOST)
 380 #define BNXT_SINGLE_PF(bp)      (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
 381 #define BNXT_USE_CHIMP_MB       0 //For non-CFA commands, everything uses Chimp.
 382 #define BNXT_USE_KONG(bp)       ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
 383 #define BNXT_VF_IS_TRUSTED(bp)  ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
 384 #define BNXT_CHIP_THOR(bp)      ((bp)->flags & BNXT_FLAG_THOR_CHIP)
 385 #define BNXT_STINGRAY(bp)       ((bp)->flags & BNXT_FLAG_STINGRAY)
 386 #define BNXT_HAS_NQ(bp)         BNXT_CHIP_THOR(bp)
 387 #define BNXT_HAS_RING_GRPS(bp)  (!BNXT_CHIP_THOR(bp))
 388
 389         unsigned int            rx_nr_rings;
 390         unsigned int            rx_cp_nr_rings;
 391         struct bnxt_rx_queue **rx_queues;
 392         const void              *rx_mem_zone;
 393         struct rx_port_stats    *hw_rx_port_stats;
 394         rte_iova_t              hw_rx_port_stats_map;
 395         struct rx_port_stats_ext    *hw_rx_port_stats_ext;
 396         rte_iova_t              hw_rx_port_stats_ext_map;
 397         uint16_t                fw_rx_port_stats_ext_size;
 398
 399         unsigned int            tx_nr_rings;
 400         unsigned int            tx_cp_nr_rings;
 401         struct bnxt_tx_queue **tx_queues;
 402         const void              *tx_mem_zone;
 403         struct tx_port_stats    *hw_tx_port_stats;
 404         rte_iova_t              hw_tx_port_stats_map;
 405         struct tx_port_stats_ext    *hw_tx_port_stats_ext;
 406         rte_iova_t              hw_tx_port_stats_ext_map;
 407         uint16_t                fw_tx_port_stats_ext_size;
 408
 409         /* Default completion ring */
 410         struct bnxt_cp_ring_info        *async_cp_ring;
 411         uint32_t                max_ring_grps;
 412         struct bnxt_ring_grp_info       *grp_info;
 413
 414         unsigned int            nr_vnics;
 415
 416 #define BNXT_GET_DEFAULT_VNIC(bp)       (&(bp)->vnic_info[0])
 417         struct bnxt_vnic_info   *vnic_info;
 418         STAILQ_HEAD(, bnxt_vnic_info)   free_vnic_list;
 419
 420         struct bnxt_filter_info *filter_info;
 421         STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
 422
 423         struct bnxt_irq         *irq_tbl;
 424
 425 #define MAX_NUM_MAC_ADDR        32
 426         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 427
 428         uint16_t                        hwrm_cmd_seq;
 429         uint16_t                        kong_cmd_seq;
 430         void                            *hwrm_cmd_resp_addr;
 431         rte_iova_t                      hwrm_cmd_resp_dma_addr;
 432         void                            *hwrm_short_cmd_req_addr;
 433         rte_iova_t                      hwrm_short_cmd_req_dma_addr;
 434         rte_spinlock_t                  hwrm_lock;
 435         uint16_t                        max_req_len;
 436         uint16_t                        max_resp_len;
 437         uint16_t                        hwrm_max_ext_req_len;
 438
 439         struct bnxt_link_info   link_info;
 440         struct bnxt_cos_queue_info      cos_queue[BNXT_COS_QUEUE_COUNT];
 441         uint8_t                 tx_cosq_id;
 442         uint8_t                 max_tc;
 443         uint8_t                 max_lltc;
 444         uint8_t                 max_q;
 445
 446         uint16_t                fw_fid;
 447         uint8_t                 dflt_mac_addr[RTE_ETHER_ADDR_LEN];
 448         uint16_t                max_rsscos_ctx;
 449         uint16_t                max_cp_rings;
 450         uint16_t                max_tx_rings;
 451         uint16_t                max_rx_rings;
 452         uint16_t                max_nq_rings;
 453         uint16_t                max_l2_ctx;
 454         uint16_t                max_rx_em_flows;
 455         uint16_t                max_vnics;
 456         uint16_t                max_stat_ctx;
 457         uint16_t                first_vf_id;
 458         uint16_t                vlan;
 459         struct bnxt_pf_info     pf;
 460         uint8_t                 port_partition_type;
 461         uint8_t                 dev_stopped;
 462         uint8_t                 vxlan_port_cnt;
 463         uint8_t                 geneve_port_cnt;
 464         uint16_t                vxlan_port;
 465         uint16_t                geneve_port;
 466         uint16_t                vxlan_fw_dst_port_id;
 467         uint16_t                geneve_fw_dst_port_id;
 468         uint32_t                fw_ver;
 469         uint32_t                hwrm_spec_code;
 470
 471         struct bnxt_led_info    leds[BNXT_MAX_LED];
 472         uint8_t                 num_leds;
 473         struct bnxt_ptp_cfg     *ptp_cfg;
 474         uint16_t                vf_resv_strategy;
 475         struct bnxt_ctx_mem_info        *ctx;
 476
 477         uint16_t                fw_reset_min_msecs;
 478         uint16_t                fw_reset_max_msecs;
 479 };
 480
 481 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete);
 482 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
 483 int is_bnxt_in_error(struct bnxt *bp);
 484
 485 bool is_bnxt_supported(struct rte_eth_dev *dev);
 486 bool bnxt_stratus_device(struct bnxt *bp);
 487 extern const struct rte_flow_ops bnxt_flow_ops;
 488
 489 extern int bnxt_logtype_driver;
 490 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
 491         rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
 492                 __func__, ## args)
 493
 494 #define PMD_DRV_LOG(level, fmt, args...) \
 495         PMD_DRV_LOG_RAW(level, fmt, ## args)
 496 #endif