drivers/net/bnxt/bnxt.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _BNXT_H_
   7 #define _BNXT_H_
   8
   9 #include <inttypes.h>
  10 #include <stdbool.h>
  11 #include <sys/queue.h>
  12
  13 #include <rte_pci.h>
  14 #include <rte_bus_pci.h>
  15 #include <rte_ethdev_driver.h>
  16 #include <rte_memory.h>
  17 #include <rte_lcore.h>
  18 #include <rte_spinlock.h>
  19 #include <rte_time.h>
  20
  21 #include "bnxt_cpr.h"
  22 #include "bnxt_util.h"
  23
  24 #include "tf_core.h"
  25 #include "bnxt_ulp.h"
  26
  27 /* Vendor ID */
  28 #define PCI_VENDOR_ID_BROADCOM          0x14E4
  29
  30 /* Device IDs */
  31 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  32 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  33 #define BROADCOM_DEV_ID_STRATUS_NIC     0x1614
  34 #define BROADCOM_DEV_ID_57414_VF        0x16c1
  35 #define BROADCOM_DEV_ID_57301           0x16c8
  36 #define BROADCOM_DEV_ID_57302           0x16c9
  37 #define BROADCOM_DEV_ID_57304_PF        0x16ca
  38 #define BROADCOM_DEV_ID_57304_VF        0x16cb
  39 #define BROADCOM_DEV_ID_57417_MF        0x16cc
  40 #define BROADCOM_DEV_ID_NS2             0x16cd
  41 #define BROADCOM_DEV_ID_57311           0x16ce
  42 #define BROADCOM_DEV_ID_57312           0x16cf
  43 #define BROADCOM_DEV_ID_57402           0x16d0
  44 #define BROADCOM_DEV_ID_57404           0x16d1
  45 #define BROADCOM_DEV_ID_57406_PF        0x16d2
  46 #define BROADCOM_DEV_ID_57406_VF        0x16d3
  47 #define BROADCOM_DEV_ID_57402_MF        0x16d4
  48 #define BROADCOM_DEV_ID_57407_RJ45      0x16d5
  49 #define BROADCOM_DEV_ID_57412           0x16d6
  50 #define BROADCOM_DEV_ID_57414           0x16d7
  51 #define BROADCOM_DEV_ID_57416_RJ45      0x16d8
  52 #define BROADCOM_DEV_ID_57417_RJ45      0x16d9
  53 #define BROADCOM_DEV_ID_5741X_VF        0x16dc
  54 #define BROADCOM_DEV_ID_57412_MF        0x16de
  55 #define BROADCOM_DEV_ID_57314           0x16df
  56 #define BROADCOM_DEV_ID_57317_RJ45      0x16e0
  57 #define BROADCOM_DEV_ID_5731X_VF        0x16e1
  58 #define BROADCOM_DEV_ID_57417_SFP       0x16e2
  59 #define BROADCOM_DEV_ID_57416_SFP       0x16e3
  60 #define BROADCOM_DEV_ID_57317_SFP       0x16e4
  61 #define BROADCOM_DEV_ID_57404_MF        0x16e7
  62 #define BROADCOM_DEV_ID_57406_MF        0x16e8
  63 #define BROADCOM_DEV_ID_57407_SFP       0x16e9
  64 #define BROADCOM_DEV_ID_57407_MF        0x16ea
  65 #define BROADCOM_DEV_ID_57414_MF        0x16ec
  66 #define BROADCOM_DEV_ID_57416_MF        0x16ee
  67 #define BROADCOM_DEV_ID_57508           0x1750
  68 #define BROADCOM_DEV_ID_57504           0x1751
  69 #define BROADCOM_DEV_ID_57502           0x1752
  70 #define BROADCOM_DEV_ID_57508_MF1       0x1800
  71 #define BROADCOM_DEV_ID_57504_MF1       0x1801
  72 #define BROADCOM_DEV_ID_57502_MF1       0x1802
  73 #define BROADCOM_DEV_ID_57508_MF2       0x1803
  74 #define BROADCOM_DEV_ID_57504_MF2       0x1804
  75 #define BROADCOM_DEV_ID_57502_MF2       0x1805
  76 #define BROADCOM_DEV_ID_57500_VF1       0x1806
  77 #define BROADCOM_DEV_ID_57500_VF2       0x1807
  78 #define BROADCOM_DEV_ID_58802           0xd802
  79 #define BROADCOM_DEV_ID_58804           0xd804
  80 #define BROADCOM_DEV_ID_58808           0x16f0
  81 #define BROADCOM_DEV_ID_58802_VF        0xd800
  82
  83 #define BNXT_MAX_MTU            9574
  84 #define VLAN_TAG_SIZE           4
  85 #define BNXT_NUM_VLANS          2
  86 #define BNXT_MAX_PKT_LEN        (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\
  87                                  RTE_ETHER_CRC_LEN +\
  88                                  (BNXT_NUM_VLANS * VLAN_TAG_SIZE))
  89 /* FW adds extra 4 bytes for FCS */
  90 #define BNXT_VNIC_MRU(mtu)\
  91         ((mtu) + RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS)
  92 #define BNXT_VF_RSV_NUM_RSS_CTX 1
  93 #define BNXT_VF_RSV_NUM_L2_CTX  4
  94 /* TODO: For now, do not support VMDq/RFS on VFs. */
  95 #define BNXT_VF_RSV_NUM_VNIC    1
  96 #define BNXT_MAX_LED            4
  97 #define BNXT_MIN_RING_DESC      16
  98 #define BNXT_MAX_TX_RING_DESC   4096
  99 #define BNXT_MAX_RX_RING_DESC   8192
 100 #define BNXT_DB_SIZE            0x80
 101
 102 #define TPA_MAX_AGGS            64
 103 #define TPA_MAX_AGGS_TH         1024
 104
 105 #define TPA_MAX_NUM_SEGS        32
 106 #define TPA_MAX_SEGS_TH         8 /* 32 segments in 4-segment units */
 107 #define TPA_MAX_SEGS            5 /* 32 segments in log2 units */
 108
 109 #define BNXT_TPA_MAX_AGGS(bp) \
 110         (BNXT_CHIP_THOR(bp) ? TPA_MAX_AGGS_TH : \
 111                              TPA_MAX_AGGS)
 112
 113 #define BNXT_TPA_MAX_SEGS(bp) \
 114         (BNXT_CHIP_THOR(bp) ? TPA_MAX_SEGS_TH : \
 115                               TPA_MAX_SEGS)
 116
 117 #ifdef RTE_ARCH_ARM64
 118 #define BNXT_NUM_ASYNC_CPR(bp) (BNXT_STINGRAY(bp) ? 0 : 1)
 119 #else
 120 #define BNXT_NUM_ASYNC_CPR(bp) 1
 121 #endif
 122
 123 /* In FreeBSD OS, nic_uio driver does not support interrupts */
 124 #ifdef RTE_EXEC_ENV_FREEBSD
 125 #ifdef BNXT_NUM_ASYNC_CPR
 126 #undef BNXT_NUM_ASYNC_CPR
 127 #endif
 128 #define BNXT_NUM_ASYNC_CPR(bp)  0
 129 #endif
 130
 131 #define BNXT_MISC_VEC_ID               RTE_INTR_VEC_ZERO_OFFSET
 132 #define BNXT_RX_VEC_START              RTE_INTR_VEC_RXTX_OFFSET
 133
 134 /* Chimp Communication Channel */
 135 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET          0x0
 136 #define GRCPF_REG_CHIMP_COMM_TRIGGER            0x100
 137 /* Kong Communication Channel */
 138 #define GRCPF_REG_KONG_CHANNEL_OFFSET           0xA00
 139 #define GRCPF_REG_KONG_COMM_TRIGGER             0xB00
 140
 141 #define BNXT_INT_LAT_TMR_MIN                    75
 142 #define BNXT_INT_LAT_TMR_MAX                    150
 143 #define BNXT_NUM_CMPL_AGGR_INT                  36
 144 #define BNXT_CMPL_AGGR_DMA_TMR                  37
 145 #define BNXT_NUM_CMPL_DMA_AGGR                  36
 146 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT       50
 147 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT       12
 148
 149 struct bnxt_led_info {
 150         uint8_t      num_leds;
 151         uint8_t      led_id;
 152         uint8_t      led_type;
 153         uint8_t      led_group_id;
 154         uint8_t      unused;
 155         uint16_t  led_state_caps;
 156 #define BNXT_LED_ALT_BLINK_CAP(x)       ((x) &  \
 157         rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
 158
 159         uint16_t  led_color_caps;
 160 };
 161
 162 struct bnxt_led_cfg {
 163         uint8_t led_id;
 164         uint8_t led_state;
 165         uint8_t led_color;
 166         uint8_t unused;
 167         uint16_t led_blink_on;
 168         uint16_t led_blink_off;
 169         uint8_t led_group_id;
 170         uint8_t rsvd;
 171 };
 172
 173 #define BNXT_LED_DFLT_ENA                               \
 174         (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID |             \
 175          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE |          \
 176          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON |       \
 177          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF |      \
 178          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
 179
 180 #define BNXT_LED_DFLT_ENA_SHIFT         6
 181
 182 #define BNXT_LED_DFLT_ENABLES(x)                        \
 183         rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
 184
 185 enum bnxt_hw_context {
 186         HW_CONTEXT_NONE     = 0,
 187         HW_CONTEXT_IS_RSS   = 1,
 188         HW_CONTEXT_IS_COS   = 2,
 189         HW_CONTEXT_IS_LB    = 3,
 190 };
 191
 192 struct bnxt_vlan_table_entry {
 193         uint16_t                tpid;
 194         uint16_t                vid;
 195 } __rte_packed;
 196
 197 struct bnxt_vlan_antispoof_table_entry {
 198         uint16_t                tpid;
 199         uint16_t                vid;
 200         uint16_t                mask;
 201 } __rte_packed;
 202
 203 struct bnxt_child_vf_info {
 204         void                    *req_buf;
 205         struct bnxt_vlan_table_entry    *vlan_table;
 206         struct bnxt_vlan_antispoof_table_entry  *vlan_as_table;
 207         STAILQ_HEAD(, bnxt_filter_info) filter;
 208         uint32_t                func_cfg_flags;
 209         uint32_t                l2_rx_mask;
 210         uint16_t                fid;
 211         uint16_t                max_tx_rate;
 212         uint16_t                dflt_vlan;
 213         uint16_t                vlan_count;
 214         uint8_t                 mac_spoof_en;
 215         uint8_t                 vlan_spoof_en;
 216         bool                    random_mac;
 217         bool                    persist_stats;
 218 };
 219
 220 struct bnxt_pf_info {
 221 #define BNXT_FIRST_PF_FID       1
 222 #define BNXT_MAX_VFS(bp)        ((bp)->pf->max_vfs)
 223 #define BNXT_MAX_VF_REPS        64
 224 #define BNXT_TOTAL_VFS(bp)      ((bp)->pf->total_vfs)
 225 #define BNXT_FIRST_VF_FID       128
 226 #define BNXT_PF_RINGS_USED(bp)  bnxt_get_num_queues(bp)
 227 #define BNXT_PF_RINGS_AVAIL(bp) ((bp)->pf->max_cp_rings - \
 228                                  BNXT_PF_RINGS_USED(bp))
 229         uint16_t                port_id;
 230         uint16_t                first_vf_id;
 231         uint16_t                active_vfs;
 232         uint16_t                max_vfs;
 233         uint16_t                total_vfs; /* Total VFs possible.
 234                                             * Not necessarily enabled.
 235                                             */
 236         uint32_t                func_cfg_flags;
 237         void                    *vf_req_buf;
 238         rte_iova_t              vf_req_buf_dma_addr;
 239         uint32_t                vf_req_fwd[8];
 240         uint16_t                total_vnics;
 241         struct bnxt_child_vf_info       *vf_info;
 242 #define BNXT_EVB_MODE_NONE      0
 243 #define BNXT_EVB_MODE_VEB       1
 244 #define BNXT_EVB_MODE_VEPA      2
 245         uint8_t                 evb_mode;
 246 };
 247
 248 /* Max wait time for link up is 10s and link down is 500ms */
 249 #define BNXT_LINK_UP_WAIT_CNT   200
 250 #define BNXT_LINK_DOWN_WAIT_CNT 10
 251 #define BNXT_LINK_WAIT_INTERVAL 50
 252 struct bnxt_link_info {
 253         uint32_t                phy_flags;
 254         uint8_t                 mac_type;
 255         uint8_t                 phy_link_status;
 256         uint8_t                 loop_back;
 257         uint8_t                 link_up;
 258         uint8_t                 duplex;
 259         uint8_t                 pause;
 260         uint8_t                 force_pause;
 261         uint8_t                 auto_pause;
 262         uint8_t                 auto_mode;
 263 #define PHY_VER_LEN             3
 264         uint8_t                 phy_ver[PHY_VER_LEN];
 265         uint16_t                link_speed;
 266         uint16_t                support_speeds;
 267         uint16_t                auto_link_speed;
 268         uint16_t                force_link_speed;
 269         uint16_t                auto_link_speed_mask;
 270         uint32_t                preemphasis;
 271         uint8_t                 phy_type;
 272         uint8_t                 media_type;
 273 };
 274
 275 #define BNXT_COS_QUEUE_COUNT    8
 276 struct bnxt_cos_queue_info {
 277         uint8_t id;
 278         uint8_t profile;
 279 };
 280
 281 struct rte_flow {
 282         STAILQ_ENTRY(rte_flow) next;
 283         struct bnxt_filter_info *filter;
 284         struct bnxt_vnic_info   *vnic;
 285 };
 286
 287 #define BNXT_PTP_FLAGS_PATH_TX          0x0
 288 #define BNXT_PTP_FLAGS_PATH_RX          0x1
 289 #define BNXT_PTP_FLAGS_CURRENT_TIME     0x2
 290
 291 struct bnxt_ptp_cfg {
 292 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT  0x400
 293 #define BNXT_GRCPF_REG_SYNC_TIME        0x480
 294 #define BNXT_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 295         struct rte_timecounter      tc;
 296         struct rte_timecounter      tx_tstamp_tc;
 297         struct rte_timecounter      rx_tstamp_tc;
 298         struct bnxt             *bp;
 299 #define BNXT_MAX_TX_TS  1
 300         uint16_t                        rxctl;
 301 #define BNXT_PTP_MSG_SYNC                       BIT(0)
 302 #define BNXT_PTP_MSG_DELAY_REQ                  BIT(1)
 303 #define BNXT_PTP_MSG_PDELAY_REQ                 BIT(2)
 304 #define BNXT_PTP_MSG_PDELAY_RESP                BIT(3)
 305 #define BNXT_PTP_MSG_FOLLOW_UP                  BIT(8)
 306 #define BNXT_PTP_MSG_DELAY_RESP                 BIT(9)
 307 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP      BIT(10)
 308 #define BNXT_PTP_MSG_ANNOUNCE                   BIT(11)
 309 #define BNXT_PTP_MSG_SIGNALING                  BIT(12)
 310 #define BNXT_PTP_MSG_MANAGEMENT                 BIT(13)
 311 #define BNXT_PTP_MSG_EVENTS             (BNXT_PTP_MSG_SYNC |            \
 312                                          BNXT_PTP_MSG_DELAY_REQ |       \
 313                                          BNXT_PTP_MSG_PDELAY_REQ |      \
 314                                          BNXT_PTP_MSG_PDELAY_RESP)
 315         uint8_t                 tx_tstamp_en:1;
 316         int                     rx_filter;
 317
 318 #define BNXT_PTP_RX_TS_L        0
 319 #define BNXT_PTP_RX_TS_H        1
 320 #define BNXT_PTP_RX_SEQ         2
 321 #define BNXT_PTP_RX_FIFO        3
 322 #define BNXT_PTP_RX_FIFO_PENDING 0x1
 323 #define BNXT_PTP_RX_FIFO_ADV    4
 324 #define BNXT_PTP_RX_REGS        5
 325
 326 #define BNXT_PTP_TX_TS_L        0
 327 #define BNXT_PTP_TX_TS_H        1
 328 #define BNXT_PTP_TX_SEQ         2
 329 #define BNXT_PTP_TX_FIFO        3
 330 #define BNXT_PTP_TX_FIFO_EMPTY   0x2
 331 #define BNXT_PTP_TX_REGS        4
 332         uint32_t                        rx_regs[BNXT_PTP_RX_REGS];
 333         uint32_t                        rx_mapped_regs[BNXT_PTP_RX_REGS];
 334         uint32_t                        tx_regs[BNXT_PTP_TX_REGS];
 335         uint32_t                        tx_mapped_regs[BNXT_PTP_TX_REGS];
 336
 337         /* On Thor, the Rx timestamp is present in the Rx completion record */
 338         uint64_t                        rx_timestamp;
 339 };
 340
 341 struct bnxt_coal {
 342         uint16_t                        num_cmpl_aggr_int;
 343         uint16_t                        num_cmpl_dma_aggr;
 344         uint16_t                        num_cmpl_dma_aggr_during_int;
 345         uint16_t                        int_lat_tmr_max;
 346         uint16_t                        int_lat_tmr_min;
 347         uint16_t                        cmpl_aggr_dma_tmr;
 348         uint16_t                        cmpl_aggr_dma_tmr_during_int;
 349 };
 350
 351 /* 64-bit doorbell */
 352 #define DBR_XID_SFT                             32
 353 #define DBR_PATH_L2                             (0x1ULL << 56)
 354 #define DBR_TYPE_SQ                             (0x0ULL << 60)
 355 #define DBR_TYPE_SRQ                            (0x2ULL << 60)
 356 #define DBR_TYPE_CQ                             (0x4ULL << 60)
 357 #define DBR_TYPE_NQ                             (0xaULL << 60)
 358 #define DBR_TYPE_NQ_ARM                         (0xbULL << 60)
 359
 360 #define BNXT_RSS_TBL_SIZE_THOR          512
 361 #define BNXT_RSS_ENTRIES_PER_CTX_THOR   64
 362 #define BNXT_MAX_RSS_CTXTS_THOR \
 363         (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR)
 364
 365 #define BNXT_MAX_TC    8
 366 #define BNXT_MAX_QUEUE 8
 367 #define BNXT_MAX_TC_Q  (BNXT_MAX_TC + 1)
 368 #define BNXT_PAGE_SHFT 12
 369 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
 370 #define MAX_CTX_PAGES  (BNXT_PAGE_SIZE / 8)
 371
 372 #define PTU_PTE_VALID             0x1UL
 373 #define PTU_PTE_LAST              0x2UL
 374 #define PTU_PTE_NEXT_TO_LAST      0x4UL
 375
 376 struct bnxt_ring_mem_info {
 377         int                             nr_pages;
 378         int                             page_size;
 379         uint32_t                        flags;
 380 #define BNXT_RMEM_VALID_PTE_FLAG        1
 381 #define BNXT_RMEM_RING_PTE_FLAG         2
 382
 383         void                            **pg_arr;
 384         rte_iova_t                      *dma_arr;
 385         const struct rte_memzone        *mz;
 386
 387         uint64_t                        *pg_tbl;
 388         rte_iova_t                      pg_tbl_map;
 389         const struct rte_memzone        *pg_tbl_mz;
 390
 391         int                             vmem_size;
 392         void                            **vmem;
 393 };
 394
 395 struct bnxt_ctx_pg_info {
 396         uint32_t        entries;
 397         void            *ctx_pg_arr[MAX_CTX_PAGES];
 398         rte_iova_t      ctx_dma_arr[MAX_CTX_PAGES];
 399         struct bnxt_ring_mem_info ring_mem;
 400 };
 401
 402 struct bnxt_ctx_mem_info {
 403         uint32_t        qp_max_entries;
 404         uint16_t        qp_min_qp1_entries;
 405         uint16_t        qp_max_l2_entries;
 406         uint16_t        qp_entry_size;
 407         uint16_t        srq_max_l2_entries;
 408         uint32_t        srq_max_entries;
 409         uint16_t        srq_entry_size;
 410         uint16_t        cq_max_l2_entries;
 411         uint32_t        cq_max_entries;
 412         uint16_t        cq_entry_size;
 413         uint16_t        vnic_max_vnic_entries;
 414         uint16_t        vnic_max_ring_table_entries;
 415         uint16_t        vnic_entry_size;
 416         uint32_t        stat_max_entries;
 417         uint16_t        stat_entry_size;
 418         uint16_t        tqm_entry_size;
 419         uint32_t        tqm_min_entries_per_ring;
 420         uint32_t        tqm_max_entries_per_ring;
 421         uint32_t        mrav_max_entries;
 422         uint16_t        mrav_entry_size;
 423         uint16_t        tim_entry_size;
 424         uint32_t        tim_max_entries;
 425         uint8_t         tqm_entries_multiple;
 426         uint8_t         tqm_fp_rings_count;
 427
 428         uint32_t        flags;
 429 #define BNXT_CTX_FLAG_INITED    0x01
 430
 431         struct bnxt_ctx_pg_info qp_mem;
 432         struct bnxt_ctx_pg_info srq_mem;
 433         struct bnxt_ctx_pg_info cq_mem;
 434         struct bnxt_ctx_pg_info vnic_mem;
 435         struct bnxt_ctx_pg_info stat_mem;
 436         struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q];
 437 };
 438
 439 struct bnxt_ctx_mem_buf_info {
 440         void            *va;
 441         rte_iova_t      dma;
 442         uint16_t        ctx_id;
 443         size_t          size;
 444 };
 445
 446 /* Maximum Firmware Reset bail out value in milliseconds */
 447 #define BNXT_MAX_FW_RESET_TIMEOUT       6000
 448 /* Minimum time required for the firmware readiness in milliseconds */
 449 #define BNXT_MIN_FW_READY_TIMEOUT       2000
 450 /* Frequency for the firmware readiness check in milliseconds */
 451 #define BNXT_FW_READY_WAIT_INTERVAL     100
 452
 453 #define US_PER_MS                       1000
 454 #define NS_PER_US                       1000
 455
 456 struct bnxt_error_recovery_info {
 457         /* All units in milliseconds */
 458         uint32_t        driver_polling_freq;
 459         uint32_t        master_func_wait_period;
 460         uint32_t        normal_func_wait_period;
 461         uint32_t        master_func_wait_period_after_reset;
 462         uint32_t        max_bailout_time_after_reset;
 463 #define BNXT_FW_STATUS_REG              0
 464 #define BNXT_FW_HEARTBEAT_CNT_REG       1
 465 #define BNXT_FW_RECOVERY_CNT_REG        2
 466 #define BNXT_FW_RESET_INPROG_REG        3
 467 #define BNXT_FW_STATUS_REG_CNT          4
 468         uint32_t        status_regs[BNXT_FW_STATUS_REG_CNT];
 469         uint32_t        mapped_status_regs[BNXT_FW_STATUS_REG_CNT];
 470         uint32_t        reset_inprogress_reg_mask;
 471 #define BNXT_NUM_RESET_REG      16
 472         uint8_t         reg_array_cnt;
 473         uint32_t        reset_reg[BNXT_NUM_RESET_REG];
 474         uint32_t        reset_reg_val[BNXT_NUM_RESET_REG];
 475         uint8_t         delay_after_reset[BNXT_NUM_RESET_REG];
 476 #define BNXT_FLAG_ERROR_RECOVERY_HOST   BIT(0)
 477 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1)
 478 #define BNXT_FLAG_MASTER_FUNC           BIT(2)
 479 #define BNXT_FLAG_RECOVERY_ENABLED      BIT(3)
 480         uint32_t        flags;
 481
 482         uint32_t        last_heart_beat;
 483         uint32_t        last_reset_counter;
 484 };
 485
 486 /* Frequency for the FUNC_DRV_IF_CHANGE retry in milliseconds */
 487 #define BNXT_IF_CHANGE_RETRY_INTERVAL   50
 488 /* Maximum retry count for FUNC_DRV_IF_CHANGE */
 489 #define BNXT_IF_CHANGE_RETRY_COUNT      40
 490
 491 struct bnxt_mark_info {
 492         uint32_t        mark_id;
 493         bool            valid;
 494 };
 495
 496 struct bnxt_rep_info {
 497         struct rte_eth_dev      *vfr_eth_dev;
 498 };
 499
 500 /* address space location of register */
 501 #define BNXT_FW_STATUS_REG_TYPE_MASK    3
 502 /* register is located in PCIe config space */
 503 #define BNXT_FW_STATUS_REG_TYPE_CFG     0
 504 /* register is located in GRC address space */
 505 #define BNXT_FW_STATUS_REG_TYPE_GRC     1
 506 /* register is located in BAR0  */
 507 #define BNXT_FW_STATUS_REG_TYPE_BAR0    2
 508 /* register is located in BAR1  */
 509 #define BNXT_FW_STATUS_REG_TYPE_BAR1    3
 510
 511 #define BNXT_FW_STATUS_REG_TYPE(reg)    ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK)
 512 #define BNXT_FW_STATUS_REG_OFF(reg)     ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK)
 513
 514 #define BNXT_GRCP_WINDOW_2_BASE         0x2000
 515 #define BNXT_GRCP_WINDOW_3_BASE         0x3000
 516
 517 #define BNXT_GRCP_BASE_MASK             0xfffff000
 518 #define BNXT_GRCP_OFFSET_MASK           0x00000ffc
 519
 520 #define BNXT_FW_STATUS_HEALTHY          0x8000
 521 #define BNXT_FW_STATUS_SHUTDOWN         0x100000
 522
 523 #define BNXT_ETH_RSS_SUPPORT (  \
 524         ETH_RSS_IPV4 |          \
 525         ETH_RSS_NONFRAG_IPV4_TCP |      \
 526         ETH_RSS_NONFRAG_IPV4_UDP |      \
 527         ETH_RSS_IPV6 |          \
 528         ETH_RSS_NONFRAG_IPV6_TCP |      \
 529         ETH_RSS_NONFRAG_IPV6_UDP)
 530
 531 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 532                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 533                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 534                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 535                                      DEV_TX_OFFLOAD_TCP_TSO | \
 536                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 537                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 538                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 539                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 540                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 541                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 542                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 543
 544 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 545                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 546                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 547                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 548                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 549                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 550                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 551                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 552                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 553                                      DEV_RX_OFFLOAD_TCP_LRO | \
 554                                      DEV_RX_OFFLOAD_SCATTER | \
 555                                      DEV_RX_OFFLOAD_RSS_HASH)
 556
 557 #define BNXT_HWRM_SHORT_REQ_LEN         sizeof(struct hwrm_short_input)
 558
 559 struct bnxt_flow_stat_info {
 560         uint16_t                max_fc;
 561         uint16_t                flow_count;
 562         struct bnxt_ctx_mem_buf_info rx_fc_in_tbl;
 563         struct bnxt_ctx_mem_buf_info rx_fc_out_tbl;
 564         struct bnxt_ctx_mem_buf_info tx_fc_in_tbl;
 565         struct bnxt_ctx_mem_buf_info tx_fc_out_tbl;
 566 };
 567
 568 struct bnxt {
 569         void                            *bar0;
 570
 571         struct rte_eth_dev              *eth_dev;
 572         struct rte_pci_device           *pdev;
 573         void                            *doorbell_base;
 574
 575         uint32_t                flags;
 576 #define BNXT_FLAG_REGISTERED            BIT(0)
 577 #define BNXT_FLAG_VF                    BIT(1)
 578 #define BNXT_FLAG_PORT_STATS            BIT(2)
 579 #define BNXT_FLAG_JUMBO                 BIT(3)
 580 #define BNXT_FLAG_SHORT_CMD             BIT(4)
 581 #define BNXT_FLAG_UPDATE_HASH           BIT(5)
 582 #define BNXT_FLAG_PTP_SUPPORTED         BIT(6)
 583 #define BNXT_FLAG_MULTI_HOST            BIT(7)
 584 #define BNXT_FLAG_EXT_RX_PORT_STATS     BIT(8)
 585 #define BNXT_FLAG_EXT_TX_PORT_STATS     BIT(9)
 586 #define BNXT_FLAG_KONG_MB_EN            BIT(10)
 587 #define BNXT_FLAG_TRUSTED_VF_EN         BIT(11)
 588 #define BNXT_FLAG_DFLT_VNIC_SET         BIT(12)
 589 #define BNXT_FLAG_THOR_CHIP             BIT(13)
 590 #define BNXT_FLAG_STINGRAY              BIT(14)
 591 #define BNXT_FLAG_FW_RESET              BIT(15)
 592 #define BNXT_FLAG_FATAL_ERROR           BIT(16)
 593 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE   BIT(17)
 594 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED     BIT(18)
 595 #define BNXT_FLAG_EXT_STATS_SUPPORTED           BIT(19)
 596 #define BNXT_FLAG_NEW_RM                        BIT(20)
 597 #define BNXT_FLAG_NPAR_PF                       BIT(21)
 598 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS         BIT(22)
 599 #define BNXT_FLAG_FC_THREAD                     BIT(23)
 600 #define BNXT_FLAG_RX_VECTOR_PKT_MODE            BIT(24)
 601 #define BNXT_FLAG_FLOW_XSTATS_EN                BIT(25)
 602 #define BNXT_FLAG_DFLT_MAC_SET                  BIT(26)
 603 #define BNXT_FLAG_TRUFLOW_EN                    BIT(27)
 604 #define BNXT_FLAG_GFID_ENABLE                   BIT(28)
 605 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
 606 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
 607 #define BNXT_NPAR(bp)           ((bp)->flags & BNXT_FLAG_NPAR_PF)
 608 #define BNXT_MH(bp)             ((bp)->flags & BNXT_FLAG_MULTI_HOST)
 609 #define BNXT_SINGLE_PF(bp)      (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
 610 #define BNXT_USE_CHIMP_MB       0 //For non-CFA commands, everything uses Chimp.
 611 #define BNXT_USE_KONG(bp)       ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
 612 #define BNXT_VF_IS_TRUSTED(bp)  ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
 613 #define BNXT_CHIP_THOR(bp)      ((bp)->flags & BNXT_FLAG_THOR_CHIP)
 614 #define BNXT_STINGRAY(bp)       ((bp)->flags & BNXT_FLAG_STINGRAY)
 615 #define BNXT_HAS_NQ(bp)         BNXT_CHIP_THOR(bp)
 616 #define BNXT_HAS_RING_GRPS(bp)  (!BNXT_CHIP_THOR(bp))
 617 #define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN)
 618 #define BNXT_HAS_DFLT_MAC_SET(bp)      ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET)
 619 #define BNXT_TRUFLOW_EN(bp)     ((bp)->flags & BNXT_FLAG_TRUFLOW_EN)
 620 #define BNXT_GFID_ENABLED(bp)   ((bp)->flags & BNXT_FLAG_GFID_ENABLE)
 621
 622         uint32_t                fw_cap;
 623 #define BNXT_FW_CAP_HOT_RESET           BIT(0)
 624 #define BNXT_FW_CAP_IF_CHANGE           BIT(1)
 625 #define BNXT_FW_CAP_ERROR_RECOVERY      BIT(2)
 626 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD  BIT(3)
 627 #define BNXT_FW_CAP_ADV_FLOW_MGMT       BIT(5)
 628 #define BNXT_FW_CAP_ADV_FLOW_COUNTERS   BIT(6)
 629 #define BNXT_FW_CAP_HCOMM_FW_STATUS     BIT(7)
 630
 631         uint32_t                flow_flags;
 632 #define BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN     BIT(0)
 633         pthread_mutex_t         flow_lock;
 634
 635         uint32_t                vnic_cap_flags;
 636 #define BNXT_VNIC_CAP_COS_CLASSIFY      BIT(0)
 637         unsigned int            rx_nr_rings;
 638         unsigned int            rx_cp_nr_rings;
 639         unsigned int            rx_num_qs_per_vnic;
 640         struct bnxt_rx_queue **rx_queues;
 641         const void              *rx_mem_zone;
 642         struct rx_port_stats    *hw_rx_port_stats;
 643         rte_iova_t              hw_rx_port_stats_map;
 644         struct rx_port_stats_ext    *hw_rx_port_stats_ext;
 645         rte_iova_t              hw_rx_port_stats_ext_map;
 646         uint16_t                fw_rx_port_stats_ext_size;
 647
 648         unsigned int            tx_nr_rings;
 649         unsigned int            tx_cp_nr_rings;
 650         struct bnxt_tx_queue **tx_queues;
 651         const void              *tx_mem_zone;
 652         struct tx_port_stats    *hw_tx_port_stats;
 653         rte_iova_t              hw_tx_port_stats_map;
 654         struct tx_port_stats_ext    *hw_tx_port_stats_ext;
 655         rte_iova_t              hw_tx_port_stats_ext_map;
 656         uint16_t                fw_tx_port_stats_ext_size;
 657
 658         /* Default completion ring */
 659         struct bnxt_cp_ring_info        *async_cp_ring;
 660         struct bnxt_cp_ring_info        *rxtx_nq_ring;
 661         uint32_t                max_ring_grps;
 662         struct bnxt_ring_grp_info       *grp_info;
 663
 664         unsigned int            nr_vnics;
 665
 666 #define BNXT_GET_DEFAULT_VNIC(bp)       (&(bp)->vnic_info[0])
 667         struct bnxt_vnic_info   *vnic_info;
 668         STAILQ_HEAD(, bnxt_vnic_info)   free_vnic_list;
 669
 670         struct bnxt_filter_info *filter_info;
 671         STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
 672
 673         struct bnxt_irq         *irq_tbl;
 674
 675         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 676
 677         uint16_t                        chimp_cmd_seq;
 678         uint16_t                        kong_cmd_seq;
 679         void                            *hwrm_cmd_resp_addr;
 680         rte_iova_t                      hwrm_cmd_resp_dma_addr;
 681         void                            *hwrm_short_cmd_req_addr;
 682         rte_iova_t                      hwrm_short_cmd_req_dma_addr;
 683         rte_spinlock_t                  hwrm_lock;
 684         pthread_mutex_t                 def_cp_lock;
 685         uint16_t                        max_req_len;
 686         uint16_t                        max_resp_len;
 687         uint16_t                        hwrm_max_ext_req_len;
 688
 689          /* default command timeout value of 500ms */
 690 #define DFLT_HWRM_CMD_TIMEOUT           500000
 691          /* short command timeout value of 50ms */
 692 #define SHORT_HWRM_CMD_TIMEOUT          50000
 693         /* default HWRM request timeout value */
 694         uint32_t                        hwrm_cmd_timeout;
 695
 696         struct bnxt_link_info           *link_info;
 697         struct bnxt_cos_queue_info      *rx_cos_queue;
 698         struct bnxt_cos_queue_info      *tx_cos_queue;
 699         uint8_t                 tx_cosq_id[BNXT_COS_QUEUE_COUNT];
 700         uint8_t                 rx_cosq_cnt;
 701         uint8_t                 max_tc;
 702         uint8_t                 max_lltc;
 703         uint8_t                 max_q;
 704
 705         uint16_t                fw_fid;
 706         uint16_t                max_rsscos_ctx;
 707         uint16_t                max_cp_rings;
 708         uint16_t                max_tx_rings;
 709         uint16_t                max_rx_rings;
 710 #define MAX_STINGRAY_RINGS              128U
 711 /* For sake of symmetry, max Tx rings == max Rx rings, one stat ctx for each */
 712 #define BNXT_MAX_RX_RINGS(bp) \
 713         (BNXT_STINGRAY(bp) ? RTE_MIN(RTE_MIN(bp->max_rx_rings / 2U, \
 714                                              MAX_STINGRAY_RINGS), \
 715                                      bp->max_stat_ctx / 2U) : \
 716                                 RTE_MIN(bp->max_rx_rings / 2U, \
 717                                         bp->max_stat_ctx / 2U))
 718 #define BNXT_MAX_TX_RINGS(bp) \
 719         (RTE_MIN((bp)->max_tx_rings, BNXT_MAX_RX_RINGS(bp)))
 720
 721 #define BNXT_MAX_RINGS(bp) \
 722         (RTE_MIN((((bp)->max_cp_rings - BNXT_NUM_ASYNC_CPR(bp)) / 2U), \
 723                  BNXT_MAX_TX_RINGS(bp)))
 724
 725 #define BNXT_MAX_VF_REP_RINGS   8
 726
 727         uint16_t                max_nq_rings;
 728         uint16_t                max_l2_ctx;
 729         uint16_t                max_rx_em_flows;
 730         uint16_t                max_vnics;
 731         uint16_t                max_stat_ctx;
 732         uint16_t                max_tpa_v2;
 733         uint16_t                first_vf_id;
 734         uint16_t                vlan;
 735 #define BNXT_OUTER_TPID_MASK    0x0000ffff
 736 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000
 737 #define BNXT_OUTER_TPID_BD_SHFT 16
 738         uint32_t                outer_tpid_bd;
 739         struct bnxt_pf_info     *pf;
 740         uint8_t                 vxlan_port_cnt;
 741         uint8_t                 geneve_port_cnt;
 742         uint16_t                vxlan_port;
 743         uint16_t                geneve_port;
 744         uint16_t                vxlan_fw_dst_port_id;
 745         uint16_t                geneve_fw_dst_port_id;
 746         uint32_t                fw_ver;
 747         uint32_t                hwrm_spec_code;
 748
 749         struct bnxt_led_info    *leds;
 750         struct bnxt_ptp_cfg     *ptp_cfg;
 751         uint16_t                vf_resv_strategy;
 752         struct bnxt_ctx_mem_info        *ctx;
 753
 754         uint16_t                fw_reset_min_msecs;
 755         uint16_t                fw_reset_max_msecs;
 756         uint16_t                switch_domain_id;
 757         uint16_t                num_reps;
 758         struct bnxt_rep_info    rep_info[BNXT_MAX_VF_REPS];
 759         /* Struct to hold adapter error recovery related info */
 760         struct bnxt_error_recovery_info *recovery_info;
 761 #define BNXT_MARK_TABLE_SZ      (sizeof(struct bnxt_mark_info)  * 64 * 1024)
 762 /* TCAM and EM should be 16-bit only. Other modes not supported. */
 763 #define BNXT_FLOW_ID_MASK       0x0000ffff
 764         struct bnxt_mark_info   *mark_table;
 765
 766 #define BNXT_SVIF_INVALID       0xFFFF
 767         uint16_t                func_svif;
 768         uint16_t                port_svif;
 769
 770         struct tf               tfp;
 771         struct bnxt_ulp_context *ulp_ctx;
 772         struct bnxt_flow_stat_info *flow_stat;
 773         uint8_t                 flow_xstat;
 774         uint16_t                max_num_kflows;
 775 };
 776
 777 #define BNXT_FC_TIMER   1 /* Timer freq in Sec Flow Counters */
 778
 779 /**
 780  * Structure to store private data for each VF representor instance
 781  */
 782 struct bnxt_vf_representor {
 783         uint16_t switch_domain_id;
 784         uint16_t vf_id;
 785         /* Private data store of associated PF/Trusted VF */
 786         struct bnxt     *parent_priv;
 787         uint8_t         mac_addr[RTE_ETHER_ADDR_LEN];
 788         uint8_t         dflt_mac_addr[RTE_ETHER_ADDR_LEN];
 789 };
 790
 791 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 792 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
 793                      bool exp_link_status);
 794 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
 795 int is_bnxt_in_error(struct bnxt *bp);
 796
 797 int bnxt_map_fw_health_status_regs(struct bnxt *bp);
 798 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index);
 799 void bnxt_schedule_fw_health_check(struct bnxt *bp);
 800
 801 bool is_bnxt_supported(struct rte_eth_dev *dev);
 802 bool bnxt_stratus_device(struct bnxt *bp);
 803 void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 804 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp);
 805 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
 806                         int wait_to_complete);
 807
 808 extern const struct rte_flow_ops bnxt_flow_ops;
 809
 810 #define bnxt_acquire_flow_lock(bp) \
 811         pthread_mutex_lock(&(bp)->flow_lock)
 812
 813 #define bnxt_release_flow_lock(bp) \
 814         pthread_mutex_unlock(&(bp)->flow_lock)
 815
 816 #define BNXT_VALID_VNIC_OR_RET(bp, vnic_id) do { \
 817         if ((vnic_id) >= (bp)->max_vnics) { \
 818                 rte_flow_error_set(error, \
 819                                 EINVAL, \
 820                                 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, \
 821                                 NULL, \
 822                                 "Group id is invalid!"); \
 823                 rc = -rte_errno; \
 824                 goto ret; \
 825         } \
 826 } while (0)
 827
 828 extern int bnxt_logtype_driver;
 829 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
 830         rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
 831                 __func__, ## args)
 832
 833 #define PMD_DRV_LOG(level, fmt, args...) \
 834           PMD_DRV_LOG_RAW(level, fmt, ## args)
 835
 836 extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops;
 837 int32_t bnxt_ulp_init(struct bnxt *bp);
 838 void bnxt_ulp_deinit(struct bnxt *bp);
 839
 840 uint16_t bnxt_get_vnic_id(uint16_t port);
 841 uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif);
 842 uint16_t bnxt_get_fw_func_id(uint16_t port);
 843
 844 void bnxt_cancel_fc_thread(struct bnxt *bp);
 845 void bnxt_flow_cnt_alarm_cb(void *arg);
 846 int bnxt_flow_stats_req(struct bnxt *bp);
 847 int bnxt_flow_stats_cnt(struct bnxt *bp);
 848 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp);
 849 #endif