1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
11 #include <sys/queue.h>
14 #include <rte_bus_pci.h>
15 #include <rte_ethdev_driver.h>
16 #include <rte_memory.h>
17 #include <rte_lcore.h>
18 #include <rte_spinlock.h>
23 #define BNXT_MAX_MTU 9500
24 #define VLAN_TAG_SIZE 4
25 #define BNXT_MAX_LED 4
26 #define BNXT_NUM_VLANS 2
28 struct bnxt_led_info {
33 uint16_t led_state_caps;
34 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
35 rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
37 uint16_t led_color_caps;
45 uint16_t led_blink_on;
46 uint16_t led_blink_off;
51 #define BNXT_LED_DFLT_ENA \
52 (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \
53 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \
54 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \
55 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \
56 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
58 #define BNXT_LED_DFLT_ENA_SHIFT 6
60 #define BNXT_LED_DFLT_ENABLES(x) \
61 rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
63 enum bnxt_hw_context {
65 HW_CONTEXT_IS_RSS = 1,
66 HW_CONTEXT_IS_COS = 2,
70 struct bnxt_vlan_table_entry {
73 } __attribute__((packed));
75 struct bnxt_vlan_antispoof_table_entry {
79 } __attribute__((packed));
81 struct bnxt_child_vf_info {
83 struct bnxt_vlan_table_entry *vlan_table;
84 struct bnxt_vlan_antispoof_table_entry *vlan_as_table;
85 STAILQ_HEAD(, bnxt_filter_info) filter;
86 uint32_t func_cfg_flags;
93 uint8_t vlan_spoof_en;
99 #define BNXT_FIRST_PF_FID 1
100 #define BNXT_MAX_VFS(bp) (bp->pf.max_vfs)
101 #define BNXT_TOTAL_VFS(bp) ((bp)->pf.total_vfs)
102 #define BNXT_FIRST_VF_FID 128
103 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp)
104 #define BNXT_PF_RINGS_AVAIL(bp) (bp->pf.max_cp_rings - BNXT_PF_RINGS_USED(bp))
106 uint16_t first_vf_id;
109 uint16_t total_vfs; /* Total VFs possible.
110 * Not necessarily enabled.
112 uint32_t func_cfg_flags;
114 rte_iova_t vf_req_buf_dma_addr;
115 uint32_t vf_req_fwd[8];
116 uint16_t total_vnics;
117 struct bnxt_child_vf_info *vf_info;
118 #define BNXT_EVB_MODE_NONE 0
119 #define BNXT_EVB_MODE_VEB 1
120 #define BNXT_EVB_MODE_VEPA 2
124 /* Max wait time is 10 * 100ms = 1s */
125 #define BNXT_LINK_WAIT_CNT 10
126 #define BNXT_LINK_WAIT_INTERVAL 100
127 struct bnxt_link_info {
130 uint8_t phy_link_status;
138 #define PHY_VER_LEN 3
139 uint8_t phy_ver[PHY_VER_LEN];
141 uint16_t support_speeds;
142 uint16_t auto_link_speed;
143 uint16_t force_link_speed;
144 uint16_t auto_link_speed_mask;
145 uint32_t preemphasis;
150 #define BNXT_COS_QUEUE_COUNT 8
151 struct bnxt_cos_queue_info {
157 STAILQ_ENTRY(rte_flow) next;
158 struct bnxt_filter_info *filter;
159 struct bnxt_vnic_info *vnic;
162 struct bnxt_ptp_cfg {
163 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
164 #define BNXT_GRCPF_REG_SYNC_TIME 0x480
165 #define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL
166 struct rte_timecounter tc;
167 struct rte_timecounter tx_tstamp_tc;
168 struct rte_timecounter rx_tstamp_tc;
170 #define BNXT_MAX_TX_TS 1
172 #define BNXT_PTP_MSG_SYNC (1 << 0)
173 #define BNXT_PTP_MSG_DELAY_REQ (1 << 1)
174 #define BNXT_PTP_MSG_PDELAY_REQ (1 << 2)
175 #define BNXT_PTP_MSG_PDELAY_RESP (1 << 3)
176 #define BNXT_PTP_MSG_FOLLOW_UP (1 << 8)
177 #define BNXT_PTP_MSG_DELAY_RESP (1 << 9)
178 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP (1 << 10)
179 #define BNXT_PTP_MSG_ANNOUNCE (1 << 11)
180 #define BNXT_PTP_MSG_SIGNALING (1 << 12)
181 #define BNXT_PTP_MSG_MANAGEMENT (1 << 13)
182 #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \
183 BNXT_PTP_MSG_DELAY_REQ | \
184 BNXT_PTP_MSG_PDELAY_REQ | \
185 BNXT_PTP_MSG_PDELAY_RESP)
186 uint8_t tx_tstamp_en:1;
189 #define BNXT_PTP_RX_TS_L 0
190 #define BNXT_PTP_RX_TS_H 1
191 #define BNXT_PTP_RX_SEQ 2
192 #define BNXT_PTP_RX_FIFO 3
193 #define BNXT_PTP_RX_FIFO_PENDING 0x1
194 #define BNXT_PTP_RX_FIFO_ADV 4
195 #define BNXT_PTP_RX_REGS 5
197 #define BNXT_PTP_TX_TS_L 0
198 #define BNXT_PTP_TX_TS_H 1
199 #define BNXT_PTP_TX_SEQ 2
200 #define BNXT_PTP_TX_FIFO 3
201 #define BNXT_PTP_TX_FIFO_EMPTY 0x2
202 #define BNXT_PTP_TX_REGS 4
203 uint32_t rx_regs[BNXT_PTP_RX_REGS];
204 uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS];
205 uint32_t tx_regs[BNXT_PTP_TX_REGS];
206 uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS];
209 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
213 struct rte_eth_dev *eth_dev;
214 struct rte_eth_rss_conf rss_conf;
215 struct rte_pci_device *pdev;
219 #define BNXT_FLAG_REGISTERED (1 << 0)
220 #define BNXT_FLAG_VF (1 << 1)
221 #define BNXT_FLAG_PORT_STATS (1 << 2)
222 #define BNXT_FLAG_JUMBO (1 << 3)
223 #define BNXT_FLAG_SHORT_CMD (1 << 4)
224 #define BNXT_FLAG_UPDATE_HASH (1 << 5)
225 #define BNXT_FLAG_PTP_SUPPORTED (1 << 6)
226 #define BNXT_FLAG_MULTI_HOST (1 << 7)
227 #define BNXT_FLAG_NEW_RM (1 << 30)
228 #define BNXT_FLAG_INIT_DONE (1 << 31)
229 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
230 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
231 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
232 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
233 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
235 unsigned int rx_nr_rings;
236 unsigned int rx_cp_nr_rings;
237 struct bnxt_rx_queue **rx_queues;
238 const void *rx_mem_zone;
239 struct rx_port_stats *hw_rx_port_stats;
240 rte_iova_t hw_rx_port_stats_map;
242 unsigned int tx_nr_rings;
243 unsigned int tx_cp_nr_rings;
244 struct bnxt_tx_queue **tx_queues;
245 const void *tx_mem_zone;
246 struct tx_port_stats *hw_tx_port_stats;
247 rte_iova_t hw_tx_port_stats_map;
249 /* Default completion ring */
250 struct bnxt_cp_ring_info *def_cp_ring;
251 uint32_t max_ring_grps;
252 struct bnxt_ring_grp_info *grp_info;
254 unsigned int nr_vnics;
256 struct bnxt_vnic_info *vnic_info;
257 STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list;
259 struct bnxt_filter_info *filter_info;
260 STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
262 /* VNIC pointer for flow filter (VMDq) pools */
263 #define MAX_FF_POOLS 256
264 STAILQ_HEAD(, bnxt_vnic_info) ff_pool[MAX_FF_POOLS];
266 struct bnxt_irq *irq_tbl;
268 #define MAX_NUM_MAC_ADDR 32
269 uint8_t mac_addr[ETHER_ADDR_LEN];
271 uint16_t hwrm_cmd_seq;
272 void *hwrm_cmd_resp_addr;
273 rte_iova_t hwrm_cmd_resp_dma_addr;
274 void *hwrm_short_cmd_req_addr;
275 rte_iova_t hwrm_short_cmd_req_dma_addr;
276 rte_spinlock_t hwrm_lock;
277 uint16_t max_req_len;
278 uint16_t max_resp_len;
280 struct bnxt_link_info link_info;
281 struct bnxt_cos_queue_info cos_queue[BNXT_COS_QUEUE_COUNT];
285 uint8_t dflt_mac_addr[ETHER_ADDR_LEN];
286 uint16_t max_rsscos_ctx;
287 uint16_t max_cp_rings;
288 uint16_t max_tx_rings;
289 uint16_t max_rx_rings;
292 uint16_t max_stat_ctx;
294 struct bnxt_pf_info pf;
295 uint8_t port_partition_type;
297 uint8_t vxlan_port_cnt;
298 uint8_t geneve_port_cnt;
300 uint16_t geneve_port;
301 uint16_t vxlan_fw_dst_port_id;
302 uint16_t geneve_fw_dst_port_id;
304 uint32_t hwrm_spec_code;
306 struct bnxt_led_info leds[BNXT_MAX_LED];
308 struct bnxt_ptp_cfg *ptp_cfg;
311 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete);
312 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
314 bool is_bnxt_supported(struct rte_eth_dev *dev);
315 extern const struct rte_flow_ops bnxt_flow_ops;
317 extern int bnxt_logtype_driver;
318 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
319 rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
322 #define PMD_DRV_LOG(level, fmt, args...) \
323 PMD_DRV_LOG_RAW(level, fmt, ## args)