drivers/net/bnxt/bnxt.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _BNXT_H_
   7 #define _BNXT_H_
   8
   9 #include <inttypes.h>
  10 #include <stdbool.h>
  11 #include <sys/queue.h>
  12
  13 #include <rte_pci.h>
  14 #include <rte_bus_pci.h>
  15 #include <rte_ethdev_driver.h>
  16 #include <rte_memory.h>
  17 #include <rte_lcore.h>
  18 #include <rte_spinlock.h>
  19 #include <rte_time.h>
  20
  21 #include "bnxt_cpr.h"
  22 #include "bnxt_util.h"
  23
  24 #define BNXT_MAX_MTU            9574
  25 #define VLAN_TAG_SIZE           4
  26 #define BNXT_NUM_VLANS          2
  27 #define BNXT_MAX_PKT_LEN        (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\
  28                                  RTE_ETHER_CRC_LEN +\
  29                                  (BNXT_NUM_VLANS * VLAN_TAG_SIZE))
  30 #define BNXT_VF_RSV_NUM_RSS_CTX 1
  31 #define BNXT_VF_RSV_NUM_L2_CTX  4
  32 /* TODO: For now, do not support VMDq/RFS on VFs. */
  33 #define BNXT_VF_RSV_NUM_VNIC    1
  34 #define BNXT_MAX_LED            4
  35 #define BNXT_MIN_RING_DESC      16
  36 #define BNXT_MAX_TX_RING_DESC   4096
  37 #define BNXT_MAX_RX_RING_DESC   8192
  38 #define BNXT_DB_SIZE            0x80
  39
  40 #define TPA_MAX_AGGS            64
  41 #define TPA_MAX_AGGS_TH         1024
  42
  43 #define TPA_MAX_NUM_SEGS        32
  44 #define TPA_MAX_SEGS_TH         8 /* 32 segments in 4-segment units */
  45 #define TPA_MAX_SEGS            5 /* 32 segments in log2 units */
  46
  47 #define BNXT_TPA_MAX_AGGS(bp) \
  48         (BNXT_CHIP_THOR(bp) ? TPA_MAX_AGGS_TH : \
  49                              TPA_MAX_AGGS)
  50
  51 #define BNXT_TPA_MAX_SEGS(bp) \
  52         (BNXT_CHIP_THOR(bp) ? TPA_MAX_SEGS_TH : \
  53                               TPA_MAX_SEGS)
  54
  55 #ifdef RTE_ARCH_ARM64
  56 #define BNXT_NUM_ASYNC_CPR(bp) (BNXT_STINGRAY(bp) ? 0 : 1)
  57 #else
  58 #define BNXT_NUM_ASYNC_CPR(bp) 1
  59 #endif
  60
  61 /* Chimp Communication Channel */
  62 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET          0x0
  63 #define GRCPF_REG_CHIMP_COMM_TRIGGER            0x100
  64 /* Kong Communication Channel */
  65 #define GRCPF_REG_KONG_CHANNEL_OFFSET           0xA00
  66 #define GRCPF_REG_KONG_COMM_TRIGGER             0xB00
  67
  68 #define BNXT_INT_LAT_TMR_MIN                    75
  69 #define BNXT_INT_LAT_TMR_MAX                    150
  70 #define BNXT_NUM_CMPL_AGGR_INT                  36
  71 #define BNXT_CMPL_AGGR_DMA_TMR                  37
  72 #define BNXT_NUM_CMPL_DMA_AGGR                  36
  73 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT       50
  74 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT       12
  75
  76 struct bnxt_led_info {
  77         uint8_t      led_id;
  78         uint8_t      led_type;
  79         uint8_t      led_group_id;
  80         uint8_t      unused;
  81         uint16_t  led_state_caps;
  82 #define BNXT_LED_ALT_BLINK_CAP(x)       ((x) &  \
  83         rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
  84
  85         uint16_t  led_color_caps;
  86 };
  87
  88 struct bnxt_led_cfg {
  89         uint8_t led_id;
  90         uint8_t led_state;
  91         uint8_t led_color;
  92         uint8_t unused;
  93         uint16_t led_blink_on;
  94         uint16_t led_blink_off;
  95         uint8_t led_group_id;
  96         uint8_t rsvd;
  97 };
  98
  99 #define BNXT_LED_DFLT_ENA                               \
 100         (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID |             \
 101          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE |          \
 102          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON |       \
 103          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF |      \
 104          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
 105
 106 #define BNXT_LED_DFLT_ENA_SHIFT         6
 107
 108 #define BNXT_LED_DFLT_ENABLES(x)                        \
 109         rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
 110
 111 enum bnxt_hw_context {
 112         HW_CONTEXT_NONE     = 0,
 113         HW_CONTEXT_IS_RSS   = 1,
 114         HW_CONTEXT_IS_COS   = 2,
 115         HW_CONTEXT_IS_LB    = 3,
 116 };
 117
 118 struct bnxt_vlan_table_entry {
 119         uint16_t                tpid;
 120         uint16_t                vid;
 121 } __attribute__((packed));
 122
 123 struct bnxt_vlan_antispoof_table_entry {
 124         uint16_t                tpid;
 125         uint16_t                vid;
 126         uint16_t                mask;
 127 } __attribute__((packed));
 128
 129 struct bnxt_child_vf_info {
 130         void                    *req_buf;
 131         struct bnxt_vlan_table_entry    *vlan_table;
 132         struct bnxt_vlan_antispoof_table_entry  *vlan_as_table;
 133         STAILQ_HEAD(, bnxt_filter_info) filter;
 134         uint32_t                func_cfg_flags;
 135         uint32_t                l2_rx_mask;
 136         uint16_t                fid;
 137         uint16_t                max_tx_rate;
 138         uint16_t                dflt_vlan;
 139         uint16_t                vlan_count;
 140         uint8_t                 mac_spoof_en;
 141         uint8_t                 vlan_spoof_en;
 142         bool                    random_mac;
 143         bool                    persist_stats;
 144 };
 145
 146 struct bnxt_pf_info {
 147 #define BNXT_FIRST_PF_FID       1
 148 #define BNXT_MAX_VFS(bp)        (bp->pf.max_vfs)
 149 #define BNXT_TOTAL_VFS(bp)      ((bp)->pf.total_vfs)
 150 #define BNXT_FIRST_VF_FID       128
 151 #define BNXT_PF_RINGS_USED(bp)  bnxt_get_num_queues(bp)
 152 #define BNXT_PF_RINGS_AVAIL(bp) (bp->pf.max_cp_rings - BNXT_PF_RINGS_USED(bp))
 153         uint16_t                port_id;
 154         uint16_t                first_vf_id;
 155         uint16_t                active_vfs;
 156         uint16_t                max_vfs;
 157         uint16_t                total_vfs; /* Total VFs possible.
 158                                             * Not necessarily enabled.
 159                                             */
 160         uint32_t                func_cfg_flags;
 161         void                    *vf_req_buf;
 162         rte_iova_t              vf_req_buf_dma_addr;
 163         uint32_t                vf_req_fwd[8];
 164         uint16_t                total_vnics;
 165         struct bnxt_child_vf_info       *vf_info;
 166 #define BNXT_EVB_MODE_NONE      0
 167 #define BNXT_EVB_MODE_VEB       1
 168 #define BNXT_EVB_MODE_VEPA      2
 169         uint8_t                 evb_mode;
 170 };
 171
 172 /* Max wait time is 10 * 100ms = 1s */
 173 #define BNXT_LINK_WAIT_CNT      10
 174 #define BNXT_LINK_WAIT_INTERVAL 100
 175 struct bnxt_link_info {
 176         uint32_t                phy_flags;
 177         uint8_t                 mac_type;
 178         uint8_t                 phy_link_status;
 179         uint8_t                 loop_back;
 180         uint8_t                 link_up;
 181         uint8_t                 duplex;
 182         uint8_t                 pause;
 183         uint8_t                 force_pause;
 184         uint8_t                 auto_pause;
 185         uint8_t                 auto_mode;
 186 #define PHY_VER_LEN             3
 187         uint8_t                 phy_ver[PHY_VER_LEN];
 188         uint16_t                link_speed;
 189         uint16_t                support_speeds;
 190         uint16_t                auto_link_speed;
 191         uint16_t                force_link_speed;
 192         uint16_t                auto_link_speed_mask;
 193         uint32_t                preemphasis;
 194         uint8_t                 phy_type;
 195         uint8_t                 media_type;
 196 };
 197
 198 #define BNXT_COS_QUEUE_COUNT    8
 199 struct bnxt_cos_queue_info {
 200         uint8_t id;
 201         uint8_t profile;
 202 };
 203
 204 struct rte_flow {
 205         STAILQ_ENTRY(rte_flow) next;
 206         struct bnxt_filter_info *filter;
 207         struct bnxt_vnic_info   *vnic;
 208 };
 209
 210 #define BNXT_PTP_FLAGS_PATH_TX          0x0
 211 #define BNXT_PTP_FLAGS_PATH_RX          0x1
 212 #define BNXT_PTP_FLAGS_CURRENT_TIME     0x2
 213
 214 struct bnxt_ptp_cfg {
 215 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT  0x400
 216 #define BNXT_GRCPF_REG_SYNC_TIME        0x480
 217 #define BNXT_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 218         struct rte_timecounter      tc;
 219         struct rte_timecounter      tx_tstamp_tc;
 220         struct rte_timecounter      rx_tstamp_tc;
 221         struct bnxt             *bp;
 222 #define BNXT_MAX_TX_TS  1
 223         uint16_t                        rxctl;
 224 #define BNXT_PTP_MSG_SYNC                       BIT(0)
 225 #define BNXT_PTP_MSG_DELAY_REQ                  BIT(1)
 226 #define BNXT_PTP_MSG_PDELAY_REQ                 BIT(2)
 227 #define BNXT_PTP_MSG_PDELAY_RESP                BIT(3)
 228 #define BNXT_PTP_MSG_FOLLOW_UP                  BIT(8)
 229 #define BNXT_PTP_MSG_DELAY_RESP                 BIT(9)
 230 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP      BIT(10)
 231 #define BNXT_PTP_MSG_ANNOUNCE                   BIT(11)
 232 #define BNXT_PTP_MSG_SIGNALING                  BIT(12)
 233 #define BNXT_PTP_MSG_MANAGEMENT                 BIT(13)
 234 #define BNXT_PTP_MSG_EVENTS             (BNXT_PTP_MSG_SYNC |            \
 235                                          BNXT_PTP_MSG_DELAY_REQ |       \
 236                                          BNXT_PTP_MSG_PDELAY_REQ |      \
 237                                          BNXT_PTP_MSG_PDELAY_RESP)
 238         uint8_t                 tx_tstamp_en:1;
 239         int                     rx_filter;
 240
 241 #define BNXT_PTP_RX_TS_L        0
 242 #define BNXT_PTP_RX_TS_H        1
 243 #define BNXT_PTP_RX_SEQ         2
 244 #define BNXT_PTP_RX_FIFO        3
 245 #define BNXT_PTP_RX_FIFO_PENDING 0x1
 246 #define BNXT_PTP_RX_FIFO_ADV    4
 247 #define BNXT_PTP_RX_REGS        5
 248
 249 #define BNXT_PTP_TX_TS_L        0
 250 #define BNXT_PTP_TX_TS_H        1
 251 #define BNXT_PTP_TX_SEQ         2
 252 #define BNXT_PTP_TX_FIFO        3
 253 #define BNXT_PTP_TX_FIFO_EMPTY   0x2
 254 #define BNXT_PTP_TX_REGS        4
 255         uint32_t                        rx_regs[BNXT_PTP_RX_REGS];
 256         uint32_t                        rx_mapped_regs[BNXT_PTP_RX_REGS];
 257         uint32_t                        tx_regs[BNXT_PTP_TX_REGS];
 258         uint32_t                        tx_mapped_regs[BNXT_PTP_TX_REGS];
 259
 260         /* On Thor, the Rx timestamp is present in the Rx completion record */
 261         uint64_t                        rx_timestamp;
 262 };
 263
 264 struct bnxt_coal {
 265         uint16_t                        num_cmpl_aggr_int;
 266         uint16_t                        num_cmpl_dma_aggr;
 267         uint16_t                        num_cmpl_dma_aggr_during_int;
 268         uint16_t                        int_lat_tmr_max;
 269         uint16_t                        int_lat_tmr_min;
 270         uint16_t                        cmpl_aggr_dma_tmr;
 271         uint16_t                        cmpl_aggr_dma_tmr_during_int;
 272 };
 273
 274 /* 64-bit doorbell */
 275 #define DBR_XID_SFT                             32
 276 #define DBR_PATH_L2                             (0x1ULL << 56)
 277 #define DBR_TYPE_SQ                             (0x0ULL << 60)
 278 #define DBR_TYPE_SRQ                            (0x2ULL << 60)
 279 #define DBR_TYPE_CQ                             (0x4ULL << 60)
 280 #define DBR_TYPE_NQ                             (0xaULL << 60)
 281 #define DBR_TYPE_NQ_ARM                         (0xbULL << 60)
 282
 283 #define BNXT_RSS_TBL_SIZE_THOR          512
 284 #define BNXT_RSS_ENTRIES_PER_CTX_THOR   64
 285 #define BNXT_MAX_RSS_CTXTS_THOR \
 286         (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR)
 287
 288 #define BNXT_MAX_TC    8
 289 #define BNXT_MAX_QUEUE 8
 290 #define BNXT_MAX_TC_Q  (BNXT_MAX_TC + 1)
 291 #define BNXT_MAX_Q     (bp->max_q + 1)
 292 #define BNXT_PAGE_SHFT 12
 293 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
 294 #define MAX_CTX_PAGES  (BNXT_PAGE_SIZE / 8)
 295
 296 #define PTU_PTE_VALID             0x1UL
 297 #define PTU_PTE_LAST              0x2UL
 298 #define PTU_PTE_NEXT_TO_LAST      0x4UL
 299
 300 struct bnxt_ring_mem_info {
 301         int                             nr_pages;
 302         int                             page_size;
 303         uint32_t                        flags;
 304 #define BNXT_RMEM_VALID_PTE_FLAG        1
 305 #define BNXT_RMEM_RING_PTE_FLAG         2
 306
 307         void                            **pg_arr;
 308         rte_iova_t                      *dma_arr;
 309         const struct rte_memzone        *mz;
 310
 311         uint64_t                        *pg_tbl;
 312         rte_iova_t                      pg_tbl_map;
 313         const struct rte_memzone        *pg_tbl_mz;
 314
 315         int                             vmem_size;
 316         void                            **vmem;
 317 };
 318
 319 struct bnxt_ctx_pg_info {
 320         uint32_t        entries;
 321         void            *ctx_pg_arr[MAX_CTX_PAGES];
 322         rte_iova_t      ctx_dma_arr[MAX_CTX_PAGES];
 323         struct bnxt_ring_mem_info ring_mem;
 324 };
 325
 326 struct bnxt_ctx_mem_info {
 327         uint32_t        qp_max_entries;
 328         uint16_t        qp_min_qp1_entries;
 329         uint16_t        qp_max_l2_entries;
 330         uint16_t        qp_entry_size;
 331         uint16_t        srq_max_l2_entries;
 332         uint32_t        srq_max_entries;
 333         uint16_t        srq_entry_size;
 334         uint16_t        cq_max_l2_entries;
 335         uint32_t        cq_max_entries;
 336         uint16_t        cq_entry_size;
 337         uint16_t        vnic_max_vnic_entries;
 338         uint16_t        vnic_max_ring_table_entries;
 339         uint16_t        vnic_entry_size;
 340         uint32_t        stat_max_entries;
 341         uint16_t        stat_entry_size;
 342         uint16_t        tqm_entry_size;
 343         uint32_t        tqm_min_entries_per_ring;
 344         uint32_t        tqm_max_entries_per_ring;
 345         uint32_t        mrav_max_entries;
 346         uint16_t        mrav_entry_size;
 347         uint16_t        tim_entry_size;
 348         uint32_t        tim_max_entries;
 349         uint8_t         tqm_entries_multiple;
 350
 351         uint32_t        flags;
 352 #define BNXT_CTX_FLAG_INITED    0x01
 353
 354         struct bnxt_ctx_pg_info qp_mem;
 355         struct bnxt_ctx_pg_info srq_mem;
 356         struct bnxt_ctx_pg_info cq_mem;
 357         struct bnxt_ctx_pg_info vnic_mem;
 358         struct bnxt_ctx_pg_info stat_mem;
 359         struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q];
 360 };
 361
 362 /* Maximum Firmware Reset bail out value in milliseconds */
 363 #define BNXT_MAX_FW_RESET_TIMEOUT       6000
 364 /* Minimum time required for the firmware readiness in milliseconds */
 365 #define BNXT_MIN_FW_READY_TIMEOUT       2000
 366 /* Frequency for the firmware readiness check in milliseconds */
 367 #define BNXT_FW_READY_WAIT_INTERVAL     100
 368
 369 #define US_PER_MS                       1000
 370 #define NS_PER_US                       1000
 371
 372 struct bnxt_error_recovery_info {
 373         /* All units in milliseconds */
 374         uint32_t        driver_polling_freq;
 375         uint32_t        master_func_wait_period;
 376         uint32_t        normal_func_wait_period;
 377         uint32_t        master_func_wait_period_after_reset;
 378         uint32_t        max_bailout_time_after_reset;
 379 #define BNXT_FW_STATUS_REG              0
 380 #define BNXT_FW_HEARTBEAT_CNT_REG       1
 381 #define BNXT_FW_RECOVERY_CNT_REG        2
 382 #define BNXT_FW_RESET_INPROG_REG        3
 383 #define BNXT_FW_STATUS_REG_CNT          4
 384         uint32_t        status_regs[BNXT_FW_STATUS_REG_CNT];
 385         uint32_t        mapped_status_regs[BNXT_FW_STATUS_REG_CNT];
 386         uint32_t        reset_inprogress_reg_mask;
 387 #define BNXT_NUM_RESET_REG      16
 388         uint8_t         reg_array_cnt;
 389         uint32_t        reset_reg[BNXT_NUM_RESET_REG];
 390         uint32_t        reset_reg_val[BNXT_NUM_RESET_REG];
 391         uint8_t         delay_after_reset[BNXT_NUM_RESET_REG];
 392 #define BNXT_FLAG_ERROR_RECOVERY_HOST   BIT(0)
 393 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1)
 394 #define BNXT_FLAG_MASTER_FUNC           BIT(2)
 395 #define BNXT_FLAG_RECOVERY_ENABLED      BIT(3)
 396         uint32_t        flags;
 397
 398         uint32_t        last_heart_beat;
 399         uint32_t        last_reset_counter;
 400 };
 401
 402 /* address space location of register */
 403 #define BNXT_FW_STATUS_REG_TYPE_MASK    3
 404 /* register is located in PCIe config space */
 405 #define BNXT_FW_STATUS_REG_TYPE_CFG     0
 406 /* register is located in GRC address space */
 407 #define BNXT_FW_STATUS_REG_TYPE_GRC     1
 408 /* register is located in BAR0  */
 409 #define BNXT_FW_STATUS_REG_TYPE_BAR0    2
 410 /* register is located in BAR1  */
 411 #define BNXT_FW_STATUS_REG_TYPE_BAR1    3
 412
 413 #define BNXT_FW_STATUS_REG_TYPE(reg)    ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK)
 414 #define BNXT_FW_STATUS_REG_OFF(reg)     ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK)
 415
 416 #define BNXT_GRCP_WINDOW_2_BASE         0x2000
 417 #define BNXT_GRCP_WINDOW_3_BASE         0x3000
 418
 419 #define BNXT_FW_STATUS_SHUTDOWN         0x100000
 420
 421 #define BNXT_HWRM_SHORT_REQ_LEN         sizeof(struct hwrm_short_input)
 422 struct bnxt {
 423         void                            *bar0;
 424
 425         struct rte_eth_dev              *eth_dev;
 426         struct rte_eth_rss_conf         rss_conf;
 427         struct rte_pci_device           *pdev;
 428         void                            *doorbell_base;
 429
 430         uint32_t                flags;
 431 #define BNXT_FLAG_REGISTERED            BIT(0)
 432 #define BNXT_FLAG_VF                    BIT(1)
 433 #define BNXT_FLAG_PORT_STATS            BIT(2)
 434 #define BNXT_FLAG_JUMBO                 BIT(3)
 435 #define BNXT_FLAG_SHORT_CMD             BIT(4)
 436 #define BNXT_FLAG_UPDATE_HASH           BIT(5)
 437 #define BNXT_FLAG_PTP_SUPPORTED         BIT(6)
 438 #define BNXT_FLAG_MULTI_HOST            BIT(7)
 439 #define BNXT_FLAG_EXT_RX_PORT_STATS     BIT(8)
 440 #define BNXT_FLAG_EXT_TX_PORT_STATS     BIT(9)
 441 #define BNXT_FLAG_KONG_MB_EN            BIT(10)
 442 #define BNXT_FLAG_TRUSTED_VF_EN         BIT(11)
 443 #define BNXT_FLAG_DFLT_VNIC_SET         BIT(12)
 444 #define BNXT_FLAG_THOR_CHIP             BIT(13)
 445 #define BNXT_FLAG_STINGRAY              BIT(14)
 446 #define BNXT_FLAG_FW_RESET              BIT(15)
 447 #define BNXT_FLAG_FATAL_ERROR           BIT(16)
 448 #define BNXT_FLAG_FW_CAP_IF_CHANGE              BIT(17)
 449 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE   BIT(18)
 450 #define BNXT_FLAG_FW_CAP_ERROR_RECOVERY         BIT(19)
 451 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED     BIT(20)
 452 #define BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD     BIT(21)
 453 #define BNXT_FLAG_EXT_STATS_SUPPORTED           BIT(22)
 454 #define BNXT_FLAG_NEW_RM                        BIT(23)
 455 #define BNXT_FLAG_INIT_DONE                     BIT(24)
 456 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS         BIT(25)
 457 #define BNXT_FLAG_ADV_FLOW_MGMT                 BIT(26)
 458 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
 459 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
 460 #define BNXT_NPAR(bp)           ((bp)->port_partition_type)
 461 #define BNXT_MH(bp)             ((bp)->flags & BNXT_FLAG_MULTI_HOST)
 462 #define BNXT_SINGLE_PF(bp)      (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
 463 #define BNXT_USE_CHIMP_MB       0 //For non-CFA commands, everything uses Chimp.
 464 #define BNXT_USE_KONG(bp)       ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
 465 #define BNXT_VF_IS_TRUSTED(bp)  ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
 466 #define BNXT_CHIP_THOR(bp)      ((bp)->flags & BNXT_FLAG_THOR_CHIP)
 467 #define BNXT_STINGRAY(bp)       ((bp)->flags & BNXT_FLAG_STINGRAY)
 468 #define BNXT_HAS_NQ(bp)         BNXT_CHIP_THOR(bp)
 469 #define BNXT_HAS_RING_GRPS(bp)  (!BNXT_CHIP_THOR(bp))
 470
 471         uint32_t                flow_flags;
 472 #define BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN     BIT(0)
 473         pthread_mutex_t         flow_lock;
 474
 475         uint32_t                vnic_cap_flags;
 476 #define BNXT_VNIC_CAP_COS_CLASSIFY      BIT(0)
 477         unsigned int            rx_nr_rings;
 478         unsigned int            rx_cp_nr_rings;
 479         unsigned int            rx_num_qs_per_vnic;
 480         struct bnxt_rx_queue **rx_queues;
 481         const void              *rx_mem_zone;
 482         struct rx_port_stats    *hw_rx_port_stats;
 483         rte_iova_t              hw_rx_port_stats_map;
 484         struct rx_port_stats_ext    *hw_rx_port_stats_ext;
 485         rte_iova_t              hw_rx_port_stats_ext_map;
 486         uint16_t                fw_rx_port_stats_ext_size;
 487
 488         unsigned int            tx_nr_rings;
 489         unsigned int            tx_cp_nr_rings;
 490         struct bnxt_tx_queue **tx_queues;
 491         const void              *tx_mem_zone;
 492         struct tx_port_stats    *hw_tx_port_stats;
 493         rte_iova_t              hw_tx_port_stats_map;
 494         struct tx_port_stats_ext    *hw_tx_port_stats_ext;
 495         rte_iova_t              hw_tx_port_stats_ext_map;
 496         uint16_t                fw_tx_port_stats_ext_size;
 497
 498         /* Default completion ring */
 499         struct bnxt_cp_ring_info        *async_cp_ring;
 500         struct bnxt_cp_ring_info        *rxtx_nq_ring;
 501         uint32_t                max_ring_grps;
 502         struct bnxt_ring_grp_info       *grp_info;
 503
 504         unsigned int            nr_vnics;
 505
 506 #define BNXT_GET_DEFAULT_VNIC(bp)       (&(bp)->vnic_info[0])
 507         struct bnxt_vnic_info   *vnic_info;
 508         STAILQ_HEAD(, bnxt_vnic_info)   free_vnic_list;
 509
 510         struct bnxt_filter_info *filter_info;
 511         STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
 512
 513         struct bnxt_irq         *irq_tbl;
 514
 515         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 516
 517         uint16_t                        hwrm_cmd_seq;
 518         uint16_t                        kong_cmd_seq;
 519         void                            *hwrm_cmd_resp_addr;
 520         rte_iova_t                      hwrm_cmd_resp_dma_addr;
 521         void                            *hwrm_short_cmd_req_addr;
 522         rte_iova_t                      hwrm_short_cmd_req_dma_addr;
 523         rte_spinlock_t                  hwrm_lock;
 524         uint16_t                        max_req_len;
 525         uint16_t                        max_resp_len;
 526         uint16_t                        hwrm_max_ext_req_len;
 527
 528          /* default command timeout value of 50ms */
 529 #define HWRM_CMD_TIMEOUT                50000
 530         /* default HWRM request timeout value */
 531         uint32_t                        hwrm_cmd_timeout;
 532
 533         struct bnxt_link_info   link_info;
 534         struct bnxt_cos_queue_info      rx_cos_queue[BNXT_COS_QUEUE_COUNT];
 535         struct bnxt_cos_queue_info      tx_cos_queue[BNXT_COS_QUEUE_COUNT];
 536         uint8_t                 tx_cosq_id[BNXT_COS_QUEUE_COUNT];
 537         uint8_t                 rx_cosq_cnt;
 538         uint8_t                 max_tc;
 539         uint8_t                 max_lltc;
 540         uint8_t                 max_q;
 541
 542         uint16_t                fw_fid;
 543         uint8_t                 dflt_mac_addr[RTE_ETHER_ADDR_LEN];
 544         uint16_t                max_rsscos_ctx;
 545         uint16_t                max_cp_rings;
 546         uint16_t                max_tx_rings;
 547         uint16_t                max_rx_rings;
 548         uint16_t                max_nq_rings;
 549         uint16_t                max_l2_ctx;
 550         uint16_t                max_rx_em_flows;
 551         uint16_t                max_vnics;
 552         uint16_t                max_stat_ctx;
 553         uint16_t                max_tpa_v2;
 554         uint16_t                first_vf_id;
 555         uint16_t                vlan;
 556 #define BNXT_OUTER_TPID_MASK    0x0000ffff
 557 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000
 558 #define BNXT_OUTER_TPID_BD_SHFT 16
 559         uint32_t                outer_tpid_bd;
 560         struct bnxt_pf_info     pf;
 561         uint8_t                 port_partition_type;
 562         uint8_t                 dev_stopped;
 563         uint8_t                 vxlan_port_cnt;
 564         uint8_t                 geneve_port_cnt;
 565         uint16_t                vxlan_port;
 566         uint16_t                geneve_port;
 567         uint16_t                vxlan_fw_dst_port_id;
 568         uint16_t                geneve_fw_dst_port_id;
 569         uint32_t                fw_ver;
 570         uint32_t                hwrm_spec_code;
 571
 572         struct bnxt_led_info    leds[BNXT_MAX_LED];
 573         uint8_t                 num_leds;
 574         struct bnxt_ptp_cfg     *ptp_cfg;
 575         uint16_t                vf_resv_strategy;
 576         struct bnxt_ctx_mem_info        *ctx;
 577
 578         uint16_t                fw_reset_min_msecs;
 579         uint16_t                fw_reset_max_msecs;
 580
 581         /* Struct to hold adapter error recovery related info */
 582         struct bnxt_error_recovery_info *recovery_info;
 583 };
 584
 585 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete);
 586 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
 587 int is_bnxt_in_error(struct bnxt *bp);
 588 uint16_t bnxt_rss_ctxts(const struct bnxt *bp);
 589
 590 int bnxt_map_fw_health_status_regs(struct bnxt *bp);
 591 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index);
 592 void bnxt_schedule_fw_health_check(struct bnxt *bp);
 593
 594 bool is_bnxt_supported(struct rte_eth_dev *dev);
 595 bool bnxt_stratus_device(struct bnxt *bp);
 596 extern const struct rte_flow_ops bnxt_flow_ops;
 597 #define bnxt_acquire_flow_lock(bp) \
 598         pthread_mutex_lock(&(bp)->flow_lock)
 599
 600 #define bnxt_release_flow_lock(bp) \
 601         pthread_mutex_unlock(&(bp)->flow_lock)
 602
 603 extern int bnxt_logtype_driver;
 604 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
 605         rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
 606                 __func__, ## args)
 607
 608 #define PMD_DRV_LOG(level, fmt, args...) \
 609         PMD_DRV_LOG_RAW(level, fmt, ## args)
 610 #endif