drivers/net/bnxt/bnxt.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _BNXT_H_
   7 #define _BNXT_H_
   8
   9 #include <inttypes.h>
  10 #include <stdbool.h>
  11 #include <sys/queue.h>
  12
  13 #include <rte_pci.h>
  14 #include <rte_bus_pci.h>
  15 #include <rte_ethdev_driver.h>
  16 #include <rte_memory.h>
  17 #include <rte_lcore.h>
  18 #include <rte_spinlock.h>
  19 #include <rte_time.h>
  20
  21 #include "bnxt_cpr.h"
  22 #include "bnxt_util.h"
  23
  24 #include "tf_core.h"
  25
  26 /* Vendor ID */
  27 #define PCI_VENDOR_ID_BROADCOM          0x14E4
  28
  29 /* Device IDs */
  30 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  31 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  32 #define BROADCOM_DEV_ID_STRATUS_NIC     0x1614
  33 #define BROADCOM_DEV_ID_57414_VF        0x16c1
  34 #define BROADCOM_DEV_ID_57301           0x16c8
  35 #define BROADCOM_DEV_ID_57302           0x16c9
  36 #define BROADCOM_DEV_ID_57304_PF        0x16ca
  37 #define BROADCOM_DEV_ID_57304_VF        0x16cb
  38 #define BROADCOM_DEV_ID_57417_MF        0x16cc
  39 #define BROADCOM_DEV_ID_NS2             0x16cd
  40 #define BROADCOM_DEV_ID_57311           0x16ce
  41 #define BROADCOM_DEV_ID_57312           0x16cf
  42 #define BROADCOM_DEV_ID_57402           0x16d0
  43 #define BROADCOM_DEV_ID_57404           0x16d1
  44 #define BROADCOM_DEV_ID_57406_PF        0x16d2
  45 #define BROADCOM_DEV_ID_57406_VF        0x16d3
  46 #define BROADCOM_DEV_ID_57402_MF        0x16d4
  47 #define BROADCOM_DEV_ID_57407_RJ45      0x16d5
  48 #define BROADCOM_DEV_ID_57412           0x16d6
  49 #define BROADCOM_DEV_ID_57414           0x16d7
  50 #define BROADCOM_DEV_ID_57416_RJ45      0x16d8
  51 #define BROADCOM_DEV_ID_57417_RJ45      0x16d9
  52 #define BROADCOM_DEV_ID_5741X_VF        0x16dc
  53 #define BROADCOM_DEV_ID_57412_MF        0x16de
  54 #define BROADCOM_DEV_ID_57314           0x16df
  55 #define BROADCOM_DEV_ID_57317_RJ45      0x16e0
  56 #define BROADCOM_DEV_ID_5731X_VF        0x16e1
  57 #define BROADCOM_DEV_ID_57417_SFP       0x16e2
  58 #define BROADCOM_DEV_ID_57416_SFP       0x16e3
  59 #define BROADCOM_DEV_ID_57317_SFP       0x16e4
  60 #define BROADCOM_DEV_ID_57404_MF        0x16e7
  61 #define BROADCOM_DEV_ID_57406_MF        0x16e8
  62 #define BROADCOM_DEV_ID_57407_SFP       0x16e9
  63 #define BROADCOM_DEV_ID_57407_MF        0x16ea
  64 #define BROADCOM_DEV_ID_57414_MF        0x16ec
  65 #define BROADCOM_DEV_ID_57416_MF        0x16ee
  66 #define BROADCOM_DEV_ID_57508           0x1750
  67 #define BROADCOM_DEV_ID_57504           0x1751
  68 #define BROADCOM_DEV_ID_57502           0x1752
  69 #define BROADCOM_DEV_ID_57508_MF1       0x1800
  70 #define BROADCOM_DEV_ID_57504_MF1       0x1801
  71 #define BROADCOM_DEV_ID_57502_MF1       0x1802
  72 #define BROADCOM_DEV_ID_57508_MF2       0x1803
  73 #define BROADCOM_DEV_ID_57504_MF2       0x1804
  74 #define BROADCOM_DEV_ID_57502_MF2       0x1805
  75 #define BROADCOM_DEV_ID_57500_VF1       0x1806
  76 #define BROADCOM_DEV_ID_57500_VF2       0x1807
  77 #define BROADCOM_DEV_ID_58802           0xd802
  78 #define BROADCOM_DEV_ID_58804           0xd804
  79 #define BROADCOM_DEV_ID_58808           0x16f0
  80 #define BROADCOM_DEV_ID_58802_VF        0xd800
  81
  82 #define BNXT_MAX_MTU            9574
  83 #define VLAN_TAG_SIZE           4
  84 #define BNXT_NUM_VLANS          2
  85 #define BNXT_MAX_PKT_LEN        (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\
  86                                  RTE_ETHER_CRC_LEN +\
  87                                  (BNXT_NUM_VLANS * VLAN_TAG_SIZE))
  88 /* FW adds extra 4 bytes for FCS */
  89 #define BNXT_VNIC_MRU(mtu)\
  90         ((mtu) + RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS)
  91 #define BNXT_VF_RSV_NUM_RSS_CTX 1
  92 #define BNXT_VF_RSV_NUM_L2_CTX  4
  93 /* TODO: For now, do not support VMDq/RFS on VFs. */
  94 #define BNXT_VF_RSV_NUM_VNIC    1
  95 #define BNXT_MAX_LED            4
  96 #define BNXT_MIN_RING_DESC      16
  97 #define BNXT_MAX_TX_RING_DESC   4096
  98 #define BNXT_MAX_RX_RING_DESC   8192
  99 #define BNXT_DB_SIZE            0x80
 100
 101 #define TPA_MAX_AGGS            64
 102 #define TPA_MAX_AGGS_TH         1024
 103
 104 #define TPA_MAX_NUM_SEGS        32
 105 #define TPA_MAX_SEGS_TH         8 /* 32 segments in 4-segment units */
 106 #define TPA_MAX_SEGS            5 /* 32 segments in log2 units */
 107
 108 #define BNXT_TPA_MAX_AGGS(bp) \
 109         (BNXT_CHIP_THOR(bp) ? TPA_MAX_AGGS_TH : \
 110                              TPA_MAX_AGGS)
 111
 112 #define BNXT_TPA_MAX_SEGS(bp) \
 113         (BNXT_CHIP_THOR(bp) ? TPA_MAX_SEGS_TH : \
 114                               TPA_MAX_SEGS)
 115
 116 #ifdef RTE_ARCH_ARM64
 117 #define BNXT_NUM_ASYNC_CPR(bp) (BNXT_STINGRAY(bp) ? 0 : 1)
 118 #else
 119 #define BNXT_NUM_ASYNC_CPR(bp) 1
 120 #endif
 121
 122 /* In FreeBSD OS, nic_uio driver does not support interrupts */
 123 #ifdef RTE_EXEC_ENV_FREEBSD
 124 #ifdef BNXT_NUM_ASYNC_CPR
 125 #undef BNXT_NUM_ASYNC_CPR
 126 #endif
 127 #define BNXT_NUM_ASYNC_CPR(bp)  0
 128 #endif
 129
 130 #define BNXT_MISC_VEC_ID               RTE_INTR_VEC_ZERO_OFFSET
 131 #define BNXT_RX_VEC_START              RTE_INTR_VEC_RXTX_OFFSET
 132
 133 /* Chimp Communication Channel */
 134 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET          0x0
 135 #define GRCPF_REG_CHIMP_COMM_TRIGGER            0x100
 136 /* Kong Communication Channel */
 137 #define GRCPF_REG_KONG_CHANNEL_OFFSET           0xA00
 138 #define GRCPF_REG_KONG_COMM_TRIGGER             0xB00
 139
 140 #define BNXT_INT_LAT_TMR_MIN                    75
 141 #define BNXT_INT_LAT_TMR_MAX                    150
 142 #define BNXT_NUM_CMPL_AGGR_INT                  36
 143 #define BNXT_CMPL_AGGR_DMA_TMR                  37
 144 #define BNXT_NUM_CMPL_DMA_AGGR                  36
 145 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT       50
 146 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT       12
 147
 148 struct bnxt_led_info {
 149         uint8_t      led_id;
 150         uint8_t      led_type;
 151         uint8_t      led_group_id;
 152         uint8_t      unused;
 153         uint16_t  led_state_caps;
 154 #define BNXT_LED_ALT_BLINK_CAP(x)       ((x) &  \
 155         rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
 156
 157         uint16_t  led_color_caps;
 158 };
 159
 160 struct bnxt_led_cfg {
 161         uint8_t led_id;
 162         uint8_t led_state;
 163         uint8_t led_color;
 164         uint8_t unused;
 165         uint16_t led_blink_on;
 166         uint16_t led_blink_off;
 167         uint8_t led_group_id;
 168         uint8_t rsvd;
 169 };
 170
 171 #define BNXT_LED_DFLT_ENA                               \
 172         (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID |             \
 173          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE |          \
 174          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON |       \
 175          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF |      \
 176          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
 177
 178 #define BNXT_LED_DFLT_ENA_SHIFT         6
 179
 180 #define BNXT_LED_DFLT_ENABLES(x)                        \
 181         rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
 182
 183 enum bnxt_hw_context {
 184         HW_CONTEXT_NONE     = 0,
 185         HW_CONTEXT_IS_RSS   = 1,
 186         HW_CONTEXT_IS_COS   = 2,
 187         HW_CONTEXT_IS_LB    = 3,
 188 };
 189
 190 struct bnxt_vlan_table_entry {
 191         uint16_t                tpid;
 192         uint16_t                vid;
 193 } __rte_packed;
 194
 195 struct bnxt_vlan_antispoof_table_entry {
 196         uint16_t                tpid;
 197         uint16_t                vid;
 198         uint16_t                mask;
 199 } __rte_packed;
 200
 201 struct bnxt_child_vf_info {
 202         void                    *req_buf;
 203         struct bnxt_vlan_table_entry    *vlan_table;
 204         struct bnxt_vlan_antispoof_table_entry  *vlan_as_table;
 205         STAILQ_HEAD(, bnxt_filter_info) filter;
 206         uint32_t                func_cfg_flags;
 207         uint32_t                l2_rx_mask;
 208         uint16_t                fid;
 209         uint16_t                max_tx_rate;
 210         uint16_t                dflt_vlan;
 211         uint16_t                vlan_count;
 212         uint8_t                 mac_spoof_en;
 213         uint8_t                 vlan_spoof_en;
 214         bool                    random_mac;
 215         bool                    persist_stats;
 216 };
 217
 218 struct bnxt_pf_info {
 219 #define BNXT_FIRST_PF_FID       1
 220 #define BNXT_MAX_VFS(bp)        (bp->pf.max_vfs)
 221 #define BNXT_TOTAL_VFS(bp)      ((bp)->pf.total_vfs)
 222 #define BNXT_FIRST_VF_FID       128
 223 #define BNXT_PF_RINGS_USED(bp)  bnxt_get_num_queues(bp)
 224 #define BNXT_PF_RINGS_AVAIL(bp) (bp->pf.max_cp_rings - BNXT_PF_RINGS_USED(bp))
 225         uint16_t                port_id;
 226         uint16_t                first_vf_id;
 227         uint16_t                active_vfs;
 228         uint16_t                max_vfs;
 229         uint16_t                total_vfs; /* Total VFs possible.
 230                                             * Not necessarily enabled.
 231                                             */
 232         uint32_t                func_cfg_flags;
 233         void                    *vf_req_buf;
 234         rte_iova_t              vf_req_buf_dma_addr;
 235         uint32_t                vf_req_fwd[8];
 236         uint16_t                total_vnics;
 237         struct bnxt_child_vf_info       *vf_info;
 238 #define BNXT_EVB_MODE_NONE      0
 239 #define BNXT_EVB_MODE_VEB       1
 240 #define BNXT_EVB_MODE_VEPA      2
 241         uint8_t                 evb_mode;
 242 };
 243
 244 /* Max wait time for link up is 10s and link down is 500ms */
 245 #define BNXT_LINK_UP_WAIT_CNT   200
 246 #define BNXT_LINK_DOWN_WAIT_CNT 10
 247 #define BNXT_LINK_WAIT_INTERVAL 50
 248 struct bnxt_link_info {
 249         uint32_t                phy_flags;
 250         uint8_t                 mac_type;
 251         uint8_t                 phy_link_status;
 252         uint8_t                 loop_back;
 253         uint8_t                 link_up;
 254         uint8_t                 duplex;
 255         uint8_t                 pause;
 256         uint8_t                 force_pause;
 257         uint8_t                 auto_pause;
 258         uint8_t                 auto_mode;
 259 #define PHY_VER_LEN             3
 260         uint8_t                 phy_ver[PHY_VER_LEN];
 261         uint16_t                link_speed;
 262         uint16_t                support_speeds;
 263         uint16_t                auto_link_speed;
 264         uint16_t                force_link_speed;
 265         uint16_t                auto_link_speed_mask;
 266         uint32_t                preemphasis;
 267         uint8_t                 phy_type;
 268         uint8_t                 media_type;
 269 };
 270
 271 #define BNXT_COS_QUEUE_COUNT    8
 272 struct bnxt_cos_queue_info {
 273         uint8_t id;
 274         uint8_t profile;
 275 };
 276
 277 struct rte_flow {
 278         STAILQ_ENTRY(rte_flow) next;
 279         struct bnxt_filter_info *filter;
 280         struct bnxt_vnic_info   *vnic;
 281 };
 282
 283 #define BNXT_PTP_FLAGS_PATH_TX          0x0
 284 #define BNXT_PTP_FLAGS_PATH_RX          0x1
 285 #define BNXT_PTP_FLAGS_CURRENT_TIME     0x2
 286
 287 struct bnxt_ptp_cfg {
 288 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT  0x400
 289 #define BNXT_GRCPF_REG_SYNC_TIME        0x480
 290 #define BNXT_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 291         struct rte_timecounter      tc;
 292         struct rte_timecounter      tx_tstamp_tc;
 293         struct rte_timecounter      rx_tstamp_tc;
 294         struct bnxt             *bp;
 295 #define BNXT_MAX_TX_TS  1
 296         uint16_t                        rxctl;
 297 #define BNXT_PTP_MSG_SYNC                       BIT(0)
 298 #define BNXT_PTP_MSG_DELAY_REQ                  BIT(1)
 299 #define BNXT_PTP_MSG_PDELAY_REQ                 BIT(2)
 300 #define BNXT_PTP_MSG_PDELAY_RESP                BIT(3)
 301 #define BNXT_PTP_MSG_FOLLOW_UP                  BIT(8)
 302 #define BNXT_PTP_MSG_DELAY_RESP                 BIT(9)
 303 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP      BIT(10)
 304 #define BNXT_PTP_MSG_ANNOUNCE                   BIT(11)
 305 #define BNXT_PTP_MSG_SIGNALING                  BIT(12)
 306 #define BNXT_PTP_MSG_MANAGEMENT                 BIT(13)
 307 #define BNXT_PTP_MSG_EVENTS             (BNXT_PTP_MSG_SYNC |            \
 308                                          BNXT_PTP_MSG_DELAY_REQ |       \
 309                                          BNXT_PTP_MSG_PDELAY_REQ |      \
 310                                          BNXT_PTP_MSG_PDELAY_RESP)
 311         uint8_t                 tx_tstamp_en:1;
 312         int                     rx_filter;
 313
 314 #define BNXT_PTP_RX_TS_L        0
 315 #define BNXT_PTP_RX_TS_H        1
 316 #define BNXT_PTP_RX_SEQ         2
 317 #define BNXT_PTP_RX_FIFO        3
 318 #define BNXT_PTP_RX_FIFO_PENDING 0x1
 319 #define BNXT_PTP_RX_FIFO_ADV    4
 320 #define BNXT_PTP_RX_REGS        5
 321
 322 #define BNXT_PTP_TX_TS_L        0
 323 #define BNXT_PTP_TX_TS_H        1
 324 #define BNXT_PTP_TX_SEQ         2
 325 #define BNXT_PTP_TX_FIFO        3
 326 #define BNXT_PTP_TX_FIFO_EMPTY   0x2
 327 #define BNXT_PTP_TX_REGS        4
 328         uint32_t                        rx_regs[BNXT_PTP_RX_REGS];
 329         uint32_t                        rx_mapped_regs[BNXT_PTP_RX_REGS];
 330         uint32_t                        tx_regs[BNXT_PTP_TX_REGS];
 331         uint32_t                        tx_mapped_regs[BNXT_PTP_TX_REGS];
 332
 333         /* On Thor, the Rx timestamp is present in the Rx completion record */
 334         uint64_t                        rx_timestamp;
 335 };
 336
 337 struct bnxt_coal {
 338         uint16_t                        num_cmpl_aggr_int;
 339         uint16_t                        num_cmpl_dma_aggr;
 340         uint16_t                        num_cmpl_dma_aggr_during_int;
 341         uint16_t                        int_lat_tmr_max;
 342         uint16_t                        int_lat_tmr_min;
 343         uint16_t                        cmpl_aggr_dma_tmr;
 344         uint16_t                        cmpl_aggr_dma_tmr_during_int;
 345 };
 346
 347 /* 64-bit doorbell */
 348 #define DBR_XID_SFT                             32
 349 #define DBR_PATH_L2                             (0x1ULL << 56)
 350 #define DBR_TYPE_SQ                             (0x0ULL << 60)
 351 #define DBR_TYPE_SRQ                            (0x2ULL << 60)
 352 #define DBR_TYPE_CQ                             (0x4ULL << 60)
 353 #define DBR_TYPE_NQ                             (0xaULL << 60)
 354 #define DBR_TYPE_NQ_ARM                         (0xbULL << 60)
 355
 356 #define BNXT_RSS_TBL_SIZE_THOR          512
 357 #define BNXT_RSS_ENTRIES_PER_CTX_THOR   64
 358 #define BNXT_MAX_RSS_CTXTS_THOR \
 359         (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR)
 360
 361 #define BNXT_MAX_TC    8
 362 #define BNXT_MAX_QUEUE 8
 363 #define BNXT_MAX_TC_Q  (BNXT_MAX_TC + 1)
 364 #define BNXT_MAX_Q     (bp->max_q + 1)
 365 #define BNXT_PAGE_SHFT 12
 366 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
 367 #define MAX_CTX_PAGES  (BNXT_PAGE_SIZE / 8)
 368
 369 #define PTU_PTE_VALID             0x1UL
 370 #define PTU_PTE_LAST              0x2UL
 371 #define PTU_PTE_NEXT_TO_LAST      0x4UL
 372
 373 struct bnxt_ring_mem_info {
 374         int                             nr_pages;
 375         int                             page_size;
 376         uint32_t                        flags;
 377 #define BNXT_RMEM_VALID_PTE_FLAG        1
 378 #define BNXT_RMEM_RING_PTE_FLAG         2
 379
 380         void                            **pg_arr;
 381         rte_iova_t                      *dma_arr;
 382         const struct rte_memzone        *mz;
 383
 384         uint64_t                        *pg_tbl;
 385         rte_iova_t                      pg_tbl_map;
 386         const struct rte_memzone        *pg_tbl_mz;
 387
 388         int                             vmem_size;
 389         void                            **vmem;
 390 };
 391
 392 struct bnxt_ctx_pg_info {
 393         uint32_t        entries;
 394         void            *ctx_pg_arr[MAX_CTX_PAGES];
 395         rte_iova_t      ctx_dma_arr[MAX_CTX_PAGES];
 396         struct bnxt_ring_mem_info ring_mem;
 397 };
 398
 399 struct bnxt_ctx_mem_info {
 400         uint32_t        qp_max_entries;
 401         uint16_t        qp_min_qp1_entries;
 402         uint16_t        qp_max_l2_entries;
 403         uint16_t        qp_entry_size;
 404         uint16_t        srq_max_l2_entries;
 405         uint32_t        srq_max_entries;
 406         uint16_t        srq_entry_size;
 407         uint16_t        cq_max_l2_entries;
 408         uint32_t        cq_max_entries;
 409         uint16_t        cq_entry_size;
 410         uint16_t        vnic_max_vnic_entries;
 411         uint16_t        vnic_max_ring_table_entries;
 412         uint16_t        vnic_entry_size;
 413         uint32_t        stat_max_entries;
 414         uint16_t        stat_entry_size;
 415         uint16_t        tqm_entry_size;
 416         uint32_t        tqm_min_entries_per_ring;
 417         uint32_t        tqm_max_entries_per_ring;
 418         uint32_t        mrav_max_entries;
 419         uint16_t        mrav_entry_size;
 420         uint16_t        tim_entry_size;
 421         uint32_t        tim_max_entries;
 422         uint8_t         tqm_entries_multiple;
 423
 424         uint32_t        flags;
 425 #define BNXT_CTX_FLAG_INITED    0x01
 426
 427         struct bnxt_ctx_pg_info qp_mem;
 428         struct bnxt_ctx_pg_info srq_mem;
 429         struct bnxt_ctx_pg_info cq_mem;
 430         struct bnxt_ctx_pg_info vnic_mem;
 431         struct bnxt_ctx_pg_info stat_mem;
 432         struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q];
 433 };
 434
 435 /* Maximum Firmware Reset bail out value in milliseconds */
 436 #define BNXT_MAX_FW_RESET_TIMEOUT       6000
 437 /* Minimum time required for the firmware readiness in milliseconds */
 438 #define BNXT_MIN_FW_READY_TIMEOUT       2000
 439 /* Frequency for the firmware readiness check in milliseconds */
 440 #define BNXT_FW_READY_WAIT_INTERVAL     100
 441
 442 #define US_PER_MS                       1000
 443 #define NS_PER_US                       1000
 444
 445 struct bnxt_error_recovery_info {
 446         /* All units in milliseconds */
 447         uint32_t        driver_polling_freq;
 448         uint32_t        master_func_wait_period;
 449         uint32_t        normal_func_wait_period;
 450         uint32_t        master_func_wait_period_after_reset;
 451         uint32_t        max_bailout_time_after_reset;
 452 #define BNXT_FW_STATUS_REG              0
 453 #define BNXT_FW_HEARTBEAT_CNT_REG       1
 454 #define BNXT_FW_RECOVERY_CNT_REG        2
 455 #define BNXT_FW_RESET_INPROG_REG        3
 456 #define BNXT_FW_STATUS_REG_CNT          4
 457         uint32_t        status_regs[BNXT_FW_STATUS_REG_CNT];
 458         uint32_t        mapped_status_regs[BNXT_FW_STATUS_REG_CNT];
 459         uint32_t        reset_inprogress_reg_mask;
 460 #define BNXT_NUM_RESET_REG      16
 461         uint8_t         reg_array_cnt;
 462         uint32_t        reset_reg[BNXT_NUM_RESET_REG];
 463         uint32_t        reset_reg_val[BNXT_NUM_RESET_REG];
 464         uint8_t         delay_after_reset[BNXT_NUM_RESET_REG];
 465 #define BNXT_FLAG_ERROR_RECOVERY_HOST   BIT(0)
 466 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1)
 467 #define BNXT_FLAG_MASTER_FUNC           BIT(2)
 468 #define BNXT_FLAG_RECOVERY_ENABLED      BIT(3)
 469         uint32_t        flags;
 470
 471         uint32_t        last_heart_beat;
 472         uint32_t        last_reset_counter;
 473 };
 474
 475 struct bnxt_mark_info {
 476         uint32_t        mark_id;
 477         bool            valid;
 478 };
 479
 480 /* address space location of register */
 481 #define BNXT_FW_STATUS_REG_TYPE_MASK    3
 482 /* register is located in PCIe config space */
 483 #define BNXT_FW_STATUS_REG_TYPE_CFG     0
 484 /* register is located in GRC address space */
 485 #define BNXT_FW_STATUS_REG_TYPE_GRC     1
 486 /* register is located in BAR0  */
 487 #define BNXT_FW_STATUS_REG_TYPE_BAR0    2
 488 /* register is located in BAR1  */
 489 #define BNXT_FW_STATUS_REG_TYPE_BAR1    3
 490
 491 #define BNXT_FW_STATUS_REG_TYPE(reg)    ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK)
 492 #define BNXT_FW_STATUS_REG_OFF(reg)     ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK)
 493
 494 #define BNXT_GRCP_WINDOW_2_BASE         0x2000
 495 #define BNXT_GRCP_WINDOW_3_BASE         0x3000
 496
 497 #define BNXT_FW_STATUS_SHUTDOWN         0x100000
 498
 499 #define BNXT_HWRM_SHORT_REQ_LEN         sizeof(struct hwrm_short_input)
 500 struct bnxt {
 501         void                            *bar0;
 502
 503         struct rte_eth_dev              *eth_dev;
 504         struct rte_eth_rss_conf         rss_conf;
 505         struct rte_pci_device           *pdev;
 506         void                            *doorbell_base;
 507
 508         uint32_t                flags;
 509 #define BNXT_FLAG_REGISTERED            BIT(0)
 510 #define BNXT_FLAG_VF                    BIT(1)
 511 #define BNXT_FLAG_PORT_STATS            BIT(2)
 512 #define BNXT_FLAG_JUMBO                 BIT(3)
 513 #define BNXT_FLAG_SHORT_CMD             BIT(4)
 514 #define BNXT_FLAG_UPDATE_HASH           BIT(5)
 515 #define BNXT_FLAG_PTP_SUPPORTED         BIT(6)
 516 #define BNXT_FLAG_MULTI_HOST            BIT(7)
 517 #define BNXT_FLAG_EXT_RX_PORT_STATS     BIT(8)
 518 #define BNXT_FLAG_EXT_TX_PORT_STATS     BIT(9)
 519 #define BNXT_FLAG_KONG_MB_EN            BIT(10)
 520 #define BNXT_FLAG_TRUSTED_VF_EN         BIT(11)
 521 #define BNXT_FLAG_DFLT_VNIC_SET         BIT(12)
 522 #define BNXT_FLAG_THOR_CHIP             BIT(13)
 523 #define BNXT_FLAG_STINGRAY              BIT(14)
 524 #define BNXT_FLAG_FW_RESET              BIT(15)
 525 #define BNXT_FLAG_FATAL_ERROR           BIT(16)
 526 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE   BIT(17)
 527 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED     BIT(18)
 528 #define BNXT_FLAG_EXT_STATS_SUPPORTED           BIT(19)
 529 #define BNXT_FLAG_NEW_RM                        BIT(20)
 530 #define BNXT_FLAG_NPAR_PF                       BIT(21)
 531 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS         BIT(22)
 532 #define BNXT_FLAG_ADV_FLOW_MGMT                 BIT(23)
 533 #define BNXT_FLAG_RX_VECTOR_PKT_MODE            BIT(24)
 534 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
 535 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
 536 #define BNXT_NPAR(bp)           ((bp)->flags & BNXT_FLAG_NPAR_PF)
 537 #define BNXT_MH(bp)             ((bp)->flags & BNXT_FLAG_MULTI_HOST)
 538 #define BNXT_SINGLE_PF(bp)      (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
 539 #define BNXT_USE_CHIMP_MB       0 //For non-CFA commands, everything uses Chimp.
 540 #define BNXT_USE_KONG(bp)       ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
 541 #define BNXT_VF_IS_TRUSTED(bp)  ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
 542 #define BNXT_CHIP_THOR(bp)      ((bp)->flags & BNXT_FLAG_THOR_CHIP)
 543 #define BNXT_STINGRAY(bp)       ((bp)->flags & BNXT_FLAG_STINGRAY)
 544 #define BNXT_HAS_NQ(bp)         BNXT_CHIP_THOR(bp)
 545 #define BNXT_HAS_RING_GRPS(bp)  (!BNXT_CHIP_THOR(bp))
 546
 547         uint32_t                fw_cap;
 548 #define BNXT_FW_CAP_HOT_RESET           BIT(0)
 549 #define BNXT_FW_CAP_IF_CHANGE           BIT(1)
 550 #define BNXT_FW_CAP_ERROR_RECOVERY      BIT(2)
 551 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD  BIT(3)
 552
 553         uint32_t                flow_flags;
 554 #define BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN     BIT(0)
 555         pthread_mutex_t         flow_lock;
 556
 557         uint32_t                vnic_cap_flags;
 558 #define BNXT_VNIC_CAP_COS_CLASSIFY      BIT(0)
 559         unsigned int            rx_nr_rings;
 560         unsigned int            rx_cp_nr_rings;
 561         unsigned int            rx_num_qs_per_vnic;
 562         struct bnxt_rx_queue **rx_queues;
 563         const void              *rx_mem_zone;
 564         struct rx_port_stats    *hw_rx_port_stats;
 565         rte_iova_t              hw_rx_port_stats_map;
 566         struct rx_port_stats_ext    *hw_rx_port_stats_ext;
 567         rte_iova_t              hw_rx_port_stats_ext_map;
 568         uint16_t                fw_rx_port_stats_ext_size;
 569
 570         unsigned int            tx_nr_rings;
 571         unsigned int            tx_cp_nr_rings;
 572         struct bnxt_tx_queue **tx_queues;
 573         const void              *tx_mem_zone;
 574         struct tx_port_stats    *hw_tx_port_stats;
 575         rte_iova_t              hw_tx_port_stats_map;
 576         struct tx_port_stats_ext    *hw_tx_port_stats_ext;
 577         rte_iova_t              hw_tx_port_stats_ext_map;
 578         uint16_t                fw_tx_port_stats_ext_size;
 579
 580         /* Default completion ring */
 581         struct bnxt_cp_ring_info        *async_cp_ring;
 582         struct bnxt_cp_ring_info        *rxtx_nq_ring;
 583         uint32_t                max_ring_grps;
 584         struct bnxt_ring_grp_info       *grp_info;
 585
 586         unsigned int            nr_vnics;
 587
 588 #define BNXT_GET_DEFAULT_VNIC(bp)       (&(bp)->vnic_info[0])
 589         struct bnxt_vnic_info   *vnic_info;
 590         STAILQ_HEAD(, bnxt_vnic_info)   free_vnic_list;
 591
 592         struct bnxt_filter_info *filter_info;
 593         STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
 594
 595         struct bnxt_irq         *irq_tbl;
 596
 597         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 598
 599         uint16_t                        chimp_cmd_seq;
 600         uint16_t                        kong_cmd_seq;
 601         void                            *hwrm_cmd_resp_addr;
 602         rte_iova_t                      hwrm_cmd_resp_dma_addr;
 603         void                            *hwrm_short_cmd_req_addr;
 604         rte_iova_t                      hwrm_short_cmd_req_dma_addr;
 605         rte_spinlock_t                  hwrm_lock;
 606         pthread_mutex_t                 def_cp_lock;
 607         uint16_t                        max_req_len;
 608         uint16_t                        max_resp_len;
 609         uint16_t                        hwrm_max_ext_req_len;
 610
 611          /* default command timeout value of 500ms */
 612 #define DFLT_HWRM_CMD_TIMEOUT           500000
 613          /* short command timeout value of 50ms */
 614 #define SHORT_HWRM_CMD_TIMEOUT          50000
 615         /* default HWRM request timeout value */
 616         uint32_t                        hwrm_cmd_timeout;
 617
 618         struct bnxt_link_info   link_info;
 619         struct bnxt_cos_queue_info      rx_cos_queue[BNXT_COS_QUEUE_COUNT];
 620         struct bnxt_cos_queue_info      tx_cos_queue[BNXT_COS_QUEUE_COUNT];
 621         uint8_t                 tx_cosq_id[BNXT_COS_QUEUE_COUNT];
 622         uint8_t                 rx_cosq_cnt;
 623         uint8_t                 max_tc;
 624         uint8_t                 max_lltc;
 625         uint8_t                 max_q;
 626
 627         uint16_t                fw_fid;
 628         uint8_t                 dflt_mac_addr[RTE_ETHER_ADDR_LEN];
 629         uint16_t                max_rsscos_ctx;
 630         uint16_t                max_cp_rings;
 631         uint16_t                max_tx_rings;
 632         uint16_t                max_rx_rings;
 633 #define MAX_STINGRAY_RINGS              128U
 634 /* For sake of symmetry, max Tx rings == max Rx rings, one stat ctx for each */
 635 #define BNXT_MAX_RX_RINGS(bp) \
 636         (BNXT_STINGRAY(bp) ? RTE_MIN(RTE_MIN(bp->max_rx_rings, \
 637                                              MAX_STINGRAY_RINGS), \
 638                                      bp->max_stat_ctx / 2U) : \
 639                                 RTE_MIN(bp->max_rx_rings, \
 640                                         bp->max_stat_ctx / 2U))
 641 #define BNXT_MAX_TX_RINGS(bp) \
 642         (RTE_MIN((bp)->max_tx_rings, BNXT_MAX_RX_RINGS(bp)))
 643
 644 #define BNXT_MAX_RINGS(bp) \
 645         (RTE_MIN((((bp)->max_cp_rings - BNXT_NUM_ASYNC_CPR(bp)) / 2U), \
 646                  BNXT_MAX_TX_RINGS(bp)))
 647         uint16_t                max_nq_rings;
 648         uint16_t                max_l2_ctx;
 649         uint16_t                max_rx_em_flows;
 650         uint16_t                max_vnics;
 651         uint16_t                max_stat_ctx;
 652         uint16_t                max_tpa_v2;
 653         uint16_t                first_vf_id;
 654         uint16_t                vlan;
 655 #define BNXT_OUTER_TPID_MASK    0x0000ffff
 656 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000
 657 #define BNXT_OUTER_TPID_BD_SHFT 16
 658         uint32_t                outer_tpid_bd;
 659         struct bnxt_pf_info     pf;
 660         uint8_t                 vxlan_port_cnt;
 661         uint8_t                 geneve_port_cnt;
 662         uint16_t                vxlan_port;
 663         uint16_t                geneve_port;
 664         uint16_t                vxlan_fw_dst_port_id;
 665         uint16_t                geneve_fw_dst_port_id;
 666         uint32_t                fw_ver;
 667         uint32_t                hwrm_spec_code;
 668
 669         struct bnxt_led_info    leds[BNXT_MAX_LED];
 670         uint8_t                 num_leds;
 671         struct bnxt_ptp_cfg     *ptp_cfg;
 672         uint16_t                vf_resv_strategy;
 673         struct bnxt_ctx_mem_info        *ctx;
 674
 675         uint16_t                fw_reset_min_msecs;
 676         uint16_t                fw_reset_max_msecs;
 677
 678         /* Struct to hold adapter error recovery related info */
 679         struct bnxt_error_recovery_info *recovery_info;
 680 #define BNXT_MARK_TABLE_SZ      (sizeof(struct bnxt_mark_info)  * 64 * 1024)
 681 /* TCAM and EM should be 16-bit only. Other modes not supported. */
 682 #define BNXT_FLOW_ID_MASK       0x0000ffff
 683         struct bnxt_mark_info   *mark_table;
 684
 685 #define BNXT_SVIF_INVALID       0xFFFF
 686         uint16_t                func_svif;
 687         uint16_t                port_svif;
 688
 689         struct tf               tfp;
 690         uint8_t                 truflow;
 691 };
 692
 693 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 694 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
 695                      bool exp_link_status);
 696 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
 697 int is_bnxt_in_error(struct bnxt *bp);
 698
 699 int bnxt_map_fw_health_status_regs(struct bnxt *bp);
 700 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index);
 701 void bnxt_schedule_fw_health_check(struct bnxt *bp);
 702
 703 bool is_bnxt_supported(struct rte_eth_dev *dev);
 704 bool bnxt_stratus_device(struct bnxt *bp);
 705 extern const struct rte_flow_ops bnxt_flow_ops;
 706 #define bnxt_acquire_flow_lock(bp) \
 707         pthread_mutex_lock(&(bp)->flow_lock)
 708
 709 #define bnxt_release_flow_lock(bp) \
 710         pthread_mutex_unlock(&(bp)->flow_lock)
 711
 712 #define BNXT_VALID_VNIC_OR_RET(bp, vnic_id) do { \
 713         if ((vnic_id) >= (bp)->max_vnics) { \
 714                 rte_flow_error_set(error, \
 715                                 EINVAL, \
 716                                 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, \
 717                                 NULL, \
 718                                 "Group id is invalid!"); \
 719                 rc = -rte_errno; \
 720                 goto ret; \
 721         } \
 722 } while (0)
 723
 724 extern int bnxt_logtype_driver;
 725 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
 726         rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
 727                 __func__, ## args)
 728
 729 #define PMD_DRV_LOG(level, fmt, args...) \
 730           PMD_DRV_LOG_RAW(level, fmt, ## args)
 731
 732 uint16_t bnxt_get_vnic_id(uint16_t port);
 733 uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif);
 734
 735 #endif