drivers/net/bnxt/bnxt.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _BNXT_H_
   7 #define _BNXT_H_
   8
   9 #include <inttypes.h>
  10 #include <stdbool.h>
  11 #include <sys/queue.h>
  12
  13 #include <rte_pci.h>
  14 #include <rte_bus_pci.h>
  15 #include <rte_ethdev_driver.h>
  16 #include <rte_memory.h>
  17 #include <rte_lcore.h>
  18 #include <rte_spinlock.h>
  19 #include <rte_time.h>
  20
  21 #include "bnxt_cpr.h"
  22 #include "bnxt_util.h"
  23
  24 /* Vendor ID */
  25 #define PCI_VENDOR_ID_BROADCOM          0x14E4
  26
  27 /* Device IDs */
  28 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  29 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  30 #define BROADCOM_DEV_ID_STRATUS_NIC     0x1614
  31 #define BROADCOM_DEV_ID_57414_VF        0x16c1
  32 #define BROADCOM_DEV_ID_57301           0x16c8
  33 #define BROADCOM_DEV_ID_57302           0x16c9
  34 #define BROADCOM_DEV_ID_57304_PF        0x16ca
  35 #define BROADCOM_DEV_ID_57304_VF        0x16cb
  36 #define BROADCOM_DEV_ID_57417_MF        0x16cc
  37 #define BROADCOM_DEV_ID_NS2             0x16cd
  38 #define BROADCOM_DEV_ID_57311           0x16ce
  39 #define BROADCOM_DEV_ID_57312           0x16cf
  40 #define BROADCOM_DEV_ID_57402           0x16d0
  41 #define BROADCOM_DEV_ID_57404           0x16d1
  42 #define BROADCOM_DEV_ID_57406_PF        0x16d2
  43 #define BROADCOM_DEV_ID_57406_VF        0x16d3
  44 #define BROADCOM_DEV_ID_57402_MF        0x16d4
  45 #define BROADCOM_DEV_ID_57407_RJ45      0x16d5
  46 #define BROADCOM_DEV_ID_57412           0x16d6
  47 #define BROADCOM_DEV_ID_57414           0x16d7
  48 #define BROADCOM_DEV_ID_57416_RJ45      0x16d8
  49 #define BROADCOM_DEV_ID_57417_RJ45      0x16d9
  50 #define BROADCOM_DEV_ID_5741X_VF        0x16dc
  51 #define BROADCOM_DEV_ID_57412_MF        0x16de
  52 #define BROADCOM_DEV_ID_57314           0x16df
  53 #define BROADCOM_DEV_ID_57317_RJ45      0x16e0
  54 #define BROADCOM_DEV_ID_5731X_VF        0x16e1
  55 #define BROADCOM_DEV_ID_57417_SFP       0x16e2
  56 #define BROADCOM_DEV_ID_57416_SFP       0x16e3
  57 #define BROADCOM_DEV_ID_57317_SFP       0x16e4
  58 #define BROADCOM_DEV_ID_57404_MF        0x16e7
  59 #define BROADCOM_DEV_ID_57406_MF        0x16e8
  60 #define BROADCOM_DEV_ID_57407_SFP       0x16e9
  61 #define BROADCOM_DEV_ID_57407_MF        0x16ea
  62 #define BROADCOM_DEV_ID_57414_MF        0x16ec
  63 #define BROADCOM_DEV_ID_57416_MF        0x16ee
  64 #define BROADCOM_DEV_ID_57508           0x1750
  65 #define BROADCOM_DEV_ID_57504           0x1751
  66 #define BROADCOM_DEV_ID_57502           0x1752
  67 #define BROADCOM_DEV_ID_57500_VF1       0x1806
  68 #define BROADCOM_DEV_ID_57500_VF2       0x1807
  69 #define BROADCOM_DEV_ID_58802           0xd802
  70 #define BROADCOM_DEV_ID_58804           0xd804
  71 #define BROADCOM_DEV_ID_58808           0x16f0
  72 #define BROADCOM_DEV_ID_58802_VF        0xd800
  73
  74 #define BNXT_MAX_MTU            9574
  75 #define VLAN_TAG_SIZE           4
  76 #define BNXT_NUM_VLANS          2
  77 #define BNXT_MAX_PKT_LEN        (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\
  78                                  RTE_ETHER_CRC_LEN +\
  79                                  (BNXT_NUM_VLANS * VLAN_TAG_SIZE))
  80 /* FW adds extra 4 bytes for FCS */
  81 #define BNXT_VNIC_MRU(mtu)\
  82         ((mtu) + RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS)
  83 #define BNXT_VF_RSV_NUM_RSS_CTX 1
  84 #define BNXT_VF_RSV_NUM_L2_CTX  4
  85 /* TODO: For now, do not support VMDq/RFS on VFs. */
  86 #define BNXT_VF_RSV_NUM_VNIC    1
  87 #define BNXT_MAX_LED            4
  88 #define BNXT_MIN_RING_DESC      16
  89 #define BNXT_MAX_TX_RING_DESC   4096
  90 #define BNXT_MAX_RX_RING_DESC   8192
  91 #define BNXT_DB_SIZE            0x80
  92
  93 #define TPA_MAX_AGGS            64
  94 #define TPA_MAX_AGGS_TH         1024
  95
  96 #define TPA_MAX_NUM_SEGS        32
  97 #define TPA_MAX_SEGS_TH         8 /* 32 segments in 4-segment units */
  98 #define TPA_MAX_SEGS            5 /* 32 segments in log2 units */
  99
 100 #define BNXT_TPA_MAX_AGGS(bp) \
 101         (BNXT_CHIP_THOR(bp) ? TPA_MAX_AGGS_TH : \
 102                              TPA_MAX_AGGS)
 103
 104 #define BNXT_TPA_MAX_SEGS(bp) \
 105         (BNXT_CHIP_THOR(bp) ? TPA_MAX_SEGS_TH : \
 106                               TPA_MAX_SEGS)
 107
 108 #ifdef RTE_ARCH_ARM64
 109 #define BNXT_NUM_ASYNC_CPR(bp) (BNXT_STINGRAY(bp) ? 0 : 1)
 110 #else
 111 #define BNXT_NUM_ASYNC_CPR(bp) 1
 112 #endif
 113
 114 #define BNXT_MISC_VEC_ID               RTE_INTR_VEC_ZERO_OFFSET
 115 #define BNXT_RX_VEC_START              RTE_INTR_VEC_RXTX_OFFSET
 116
 117 /* Chimp Communication Channel */
 118 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET          0x0
 119 #define GRCPF_REG_CHIMP_COMM_TRIGGER            0x100
 120 /* Kong Communication Channel */
 121 #define GRCPF_REG_KONG_CHANNEL_OFFSET           0xA00
 122 #define GRCPF_REG_KONG_COMM_TRIGGER             0xB00
 123
 124 #define BNXT_INT_LAT_TMR_MIN                    75
 125 #define BNXT_INT_LAT_TMR_MAX                    150
 126 #define BNXT_NUM_CMPL_AGGR_INT                  36
 127 #define BNXT_CMPL_AGGR_DMA_TMR                  37
 128 #define BNXT_NUM_CMPL_DMA_AGGR                  36
 129 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT       50
 130 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT       12
 131
 132 struct bnxt_led_info {
 133         uint8_t      led_id;
 134         uint8_t      led_type;
 135         uint8_t      led_group_id;
 136         uint8_t      unused;
 137         uint16_t  led_state_caps;
 138 #define BNXT_LED_ALT_BLINK_CAP(x)       ((x) &  \
 139         rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
 140
 141         uint16_t  led_color_caps;
 142 };
 143
 144 struct bnxt_led_cfg {
 145         uint8_t led_id;
 146         uint8_t led_state;
 147         uint8_t led_color;
 148         uint8_t unused;
 149         uint16_t led_blink_on;
 150         uint16_t led_blink_off;
 151         uint8_t led_group_id;
 152         uint8_t rsvd;
 153 };
 154
 155 #define BNXT_LED_DFLT_ENA                               \
 156         (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID |             \
 157          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE |          \
 158          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON |       \
 159          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF |      \
 160          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
 161
 162 #define BNXT_LED_DFLT_ENA_SHIFT         6
 163
 164 #define BNXT_LED_DFLT_ENABLES(x)                        \
 165         rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
 166
 167 enum bnxt_hw_context {
 168         HW_CONTEXT_NONE     = 0,
 169         HW_CONTEXT_IS_RSS   = 1,
 170         HW_CONTEXT_IS_COS   = 2,
 171         HW_CONTEXT_IS_LB    = 3,
 172 };
 173
 174 struct bnxt_vlan_table_entry {
 175         uint16_t                tpid;
 176         uint16_t                vid;
 177 } __attribute__((packed));
 178
 179 struct bnxt_vlan_antispoof_table_entry {
 180         uint16_t                tpid;
 181         uint16_t                vid;
 182         uint16_t                mask;
 183 } __attribute__((packed));
 184
 185 struct bnxt_child_vf_info {
 186         void                    *req_buf;
 187         struct bnxt_vlan_table_entry    *vlan_table;
 188         struct bnxt_vlan_antispoof_table_entry  *vlan_as_table;
 189         STAILQ_HEAD(, bnxt_filter_info) filter;
 190         uint32_t                func_cfg_flags;
 191         uint32_t                l2_rx_mask;
 192         uint16_t                fid;
 193         uint16_t                max_tx_rate;
 194         uint16_t                dflt_vlan;
 195         uint16_t                vlan_count;
 196         uint8_t                 mac_spoof_en;
 197         uint8_t                 vlan_spoof_en;
 198         bool                    random_mac;
 199         bool                    persist_stats;
 200 };
 201
 202 struct bnxt_pf_info {
 203 #define BNXT_FIRST_PF_FID       1
 204 #define BNXT_MAX_VFS(bp)        (bp->pf.max_vfs)
 205 #define BNXT_TOTAL_VFS(bp)      ((bp)->pf.total_vfs)
 206 #define BNXT_FIRST_VF_FID       128
 207 #define BNXT_PF_RINGS_USED(bp)  bnxt_get_num_queues(bp)
 208 #define BNXT_PF_RINGS_AVAIL(bp) (bp->pf.max_cp_rings - BNXT_PF_RINGS_USED(bp))
 209         uint16_t                port_id;
 210         uint16_t                first_vf_id;
 211         uint16_t                active_vfs;
 212         uint16_t                max_vfs;
 213         uint16_t                total_vfs; /* Total VFs possible.
 214                                             * Not necessarily enabled.
 215                                             */
 216         uint32_t                func_cfg_flags;
 217         void                    *vf_req_buf;
 218         rte_iova_t              vf_req_buf_dma_addr;
 219         uint32_t                vf_req_fwd[8];
 220         uint16_t                total_vnics;
 221         struct bnxt_child_vf_info       *vf_info;
 222 #define BNXT_EVB_MODE_NONE      0
 223 #define BNXT_EVB_MODE_VEB       1
 224 #define BNXT_EVB_MODE_VEPA      2
 225         uint8_t                 evb_mode;
 226 };
 227
 228 /* Max wait time is 10 * 100ms = 1s */
 229 #define BNXT_LINK_WAIT_CNT      10
 230 #define BNXT_LINK_WAIT_INTERVAL 100
 231 struct bnxt_link_info {
 232         uint32_t                phy_flags;
 233         uint8_t                 mac_type;
 234         uint8_t                 phy_link_status;
 235         uint8_t                 loop_back;
 236         uint8_t                 link_up;
 237         uint8_t                 duplex;
 238         uint8_t                 pause;
 239         uint8_t                 force_pause;
 240         uint8_t                 auto_pause;
 241         uint8_t                 auto_mode;
 242 #define PHY_VER_LEN             3
 243         uint8_t                 phy_ver[PHY_VER_LEN];
 244         uint16_t                link_speed;
 245         uint16_t                support_speeds;
 246         uint16_t                auto_link_speed;
 247         uint16_t                force_link_speed;
 248         uint16_t                auto_link_speed_mask;
 249         uint32_t                preemphasis;
 250         uint8_t                 phy_type;
 251         uint8_t                 media_type;
 252 };
 253
 254 #define BNXT_COS_QUEUE_COUNT    8
 255 struct bnxt_cos_queue_info {
 256         uint8_t id;
 257         uint8_t profile;
 258 };
 259
 260 struct rte_flow {
 261         STAILQ_ENTRY(rte_flow) next;
 262         struct bnxt_filter_info *filter;
 263         struct bnxt_vnic_info   *vnic;
 264 };
 265
 266 #define BNXT_PTP_FLAGS_PATH_TX          0x0
 267 #define BNXT_PTP_FLAGS_PATH_RX          0x1
 268 #define BNXT_PTP_FLAGS_CURRENT_TIME     0x2
 269
 270 struct bnxt_ptp_cfg {
 271 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT  0x400
 272 #define BNXT_GRCPF_REG_SYNC_TIME        0x480
 273 #define BNXT_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 274         struct rte_timecounter      tc;
 275         struct rte_timecounter      tx_tstamp_tc;
 276         struct rte_timecounter      rx_tstamp_tc;
 277         struct bnxt             *bp;
 278 #define BNXT_MAX_TX_TS  1
 279         uint16_t                        rxctl;
 280 #define BNXT_PTP_MSG_SYNC                       BIT(0)
 281 #define BNXT_PTP_MSG_DELAY_REQ                  BIT(1)
 282 #define BNXT_PTP_MSG_PDELAY_REQ                 BIT(2)
 283 #define BNXT_PTP_MSG_PDELAY_RESP                BIT(3)
 284 #define BNXT_PTP_MSG_FOLLOW_UP                  BIT(8)
 285 #define BNXT_PTP_MSG_DELAY_RESP                 BIT(9)
 286 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP      BIT(10)
 287 #define BNXT_PTP_MSG_ANNOUNCE                   BIT(11)
 288 #define BNXT_PTP_MSG_SIGNALING                  BIT(12)
 289 #define BNXT_PTP_MSG_MANAGEMENT                 BIT(13)
 290 #define BNXT_PTP_MSG_EVENTS             (BNXT_PTP_MSG_SYNC |            \
 291                                          BNXT_PTP_MSG_DELAY_REQ |       \
 292                                          BNXT_PTP_MSG_PDELAY_REQ |      \
 293                                          BNXT_PTP_MSG_PDELAY_RESP)
 294         uint8_t                 tx_tstamp_en:1;
 295         int                     rx_filter;
 296
 297 #define BNXT_PTP_RX_TS_L        0
 298 #define BNXT_PTP_RX_TS_H        1
 299 #define BNXT_PTP_RX_SEQ         2
 300 #define BNXT_PTP_RX_FIFO        3
 301 #define BNXT_PTP_RX_FIFO_PENDING 0x1
 302 #define BNXT_PTP_RX_FIFO_ADV    4
 303 #define BNXT_PTP_RX_REGS        5
 304
 305 #define BNXT_PTP_TX_TS_L        0
 306 #define BNXT_PTP_TX_TS_H        1
 307 #define BNXT_PTP_TX_SEQ         2
 308 #define BNXT_PTP_TX_FIFO        3
 309 #define BNXT_PTP_TX_FIFO_EMPTY   0x2
 310 #define BNXT_PTP_TX_REGS        4
 311         uint32_t                        rx_regs[BNXT_PTP_RX_REGS];
 312         uint32_t                        rx_mapped_regs[BNXT_PTP_RX_REGS];
 313         uint32_t                        tx_regs[BNXT_PTP_TX_REGS];
 314         uint32_t                        tx_mapped_regs[BNXT_PTP_TX_REGS];
 315
 316         /* On Thor, the Rx timestamp is present in the Rx completion record */
 317         uint64_t                        rx_timestamp;
 318 };
 319
 320 struct bnxt_coal {
 321         uint16_t                        num_cmpl_aggr_int;
 322         uint16_t                        num_cmpl_dma_aggr;
 323         uint16_t                        num_cmpl_dma_aggr_during_int;
 324         uint16_t                        int_lat_tmr_max;
 325         uint16_t                        int_lat_tmr_min;
 326         uint16_t                        cmpl_aggr_dma_tmr;
 327         uint16_t                        cmpl_aggr_dma_tmr_during_int;
 328 };
 329
 330 /* 64-bit doorbell */
 331 #define DBR_XID_SFT                             32
 332 #define DBR_PATH_L2                             (0x1ULL << 56)
 333 #define DBR_TYPE_SQ                             (0x0ULL << 60)
 334 #define DBR_TYPE_SRQ                            (0x2ULL << 60)
 335 #define DBR_TYPE_CQ                             (0x4ULL << 60)
 336 #define DBR_TYPE_NQ                             (0xaULL << 60)
 337 #define DBR_TYPE_NQ_ARM                         (0xbULL << 60)
 338
 339 #define BNXT_RSS_TBL_SIZE_THOR          512
 340 #define BNXT_RSS_ENTRIES_PER_CTX_THOR   64
 341 #define BNXT_MAX_RSS_CTXTS_THOR \
 342         (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR)
 343
 344 #define BNXT_MAX_TC    8
 345 #define BNXT_MAX_QUEUE 8
 346 #define BNXT_MAX_TC_Q  (BNXT_MAX_TC + 1)
 347 #define BNXT_MAX_Q     (bp->max_q + 1)
 348 #define BNXT_PAGE_SHFT 12
 349 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
 350 #define MAX_CTX_PAGES  (BNXT_PAGE_SIZE / 8)
 351
 352 #define PTU_PTE_VALID             0x1UL
 353 #define PTU_PTE_LAST              0x2UL
 354 #define PTU_PTE_NEXT_TO_LAST      0x4UL
 355
 356 struct bnxt_ring_mem_info {
 357         int                             nr_pages;
 358         int                             page_size;
 359         uint32_t                        flags;
 360 #define BNXT_RMEM_VALID_PTE_FLAG        1
 361 #define BNXT_RMEM_RING_PTE_FLAG         2
 362
 363         void                            **pg_arr;
 364         rte_iova_t                      *dma_arr;
 365         const struct rte_memzone        *mz;
 366
 367         uint64_t                        *pg_tbl;
 368         rte_iova_t                      pg_tbl_map;
 369         const struct rte_memzone        *pg_tbl_mz;
 370
 371         int                             vmem_size;
 372         void                            **vmem;
 373 };
 374
 375 struct bnxt_ctx_pg_info {
 376         uint32_t        entries;
 377         void            *ctx_pg_arr[MAX_CTX_PAGES];
 378         rte_iova_t      ctx_dma_arr[MAX_CTX_PAGES];
 379         struct bnxt_ring_mem_info ring_mem;
 380 };
 381
 382 struct bnxt_ctx_mem_info {
 383         uint32_t        qp_max_entries;
 384         uint16_t        qp_min_qp1_entries;
 385         uint16_t        qp_max_l2_entries;
 386         uint16_t        qp_entry_size;
 387         uint16_t        srq_max_l2_entries;
 388         uint32_t        srq_max_entries;
 389         uint16_t        srq_entry_size;
 390         uint16_t        cq_max_l2_entries;
 391         uint32_t        cq_max_entries;
 392         uint16_t        cq_entry_size;
 393         uint16_t        vnic_max_vnic_entries;
 394         uint16_t        vnic_max_ring_table_entries;
 395         uint16_t        vnic_entry_size;
 396         uint32_t        stat_max_entries;
 397         uint16_t        stat_entry_size;
 398         uint16_t        tqm_entry_size;
 399         uint32_t        tqm_min_entries_per_ring;
 400         uint32_t        tqm_max_entries_per_ring;
 401         uint32_t        mrav_max_entries;
 402         uint16_t        mrav_entry_size;
 403         uint16_t        tim_entry_size;
 404         uint32_t        tim_max_entries;
 405         uint8_t         tqm_entries_multiple;
 406
 407         uint32_t        flags;
 408 #define BNXT_CTX_FLAG_INITED    0x01
 409
 410         struct bnxt_ctx_pg_info qp_mem;
 411         struct bnxt_ctx_pg_info srq_mem;
 412         struct bnxt_ctx_pg_info cq_mem;
 413         struct bnxt_ctx_pg_info vnic_mem;
 414         struct bnxt_ctx_pg_info stat_mem;
 415         struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q];
 416 };
 417
 418 /* Maximum Firmware Reset bail out value in milliseconds */
 419 #define BNXT_MAX_FW_RESET_TIMEOUT       6000
 420 /* Minimum time required for the firmware readiness in milliseconds */
 421 #define BNXT_MIN_FW_READY_TIMEOUT       2000
 422 /* Frequency for the firmware readiness check in milliseconds */
 423 #define BNXT_FW_READY_WAIT_INTERVAL     100
 424
 425 #define US_PER_MS                       1000
 426 #define NS_PER_US                       1000
 427
 428 struct bnxt_error_recovery_info {
 429         /* All units in milliseconds */
 430         uint32_t        driver_polling_freq;
 431         uint32_t        master_func_wait_period;
 432         uint32_t        normal_func_wait_period;
 433         uint32_t        master_func_wait_period_after_reset;
 434         uint32_t        max_bailout_time_after_reset;
 435 #define BNXT_FW_STATUS_REG              0
 436 #define BNXT_FW_HEARTBEAT_CNT_REG       1
 437 #define BNXT_FW_RECOVERY_CNT_REG        2
 438 #define BNXT_FW_RESET_INPROG_REG        3
 439 #define BNXT_FW_STATUS_REG_CNT          4
 440         uint32_t        status_regs[BNXT_FW_STATUS_REG_CNT];
 441         uint32_t        mapped_status_regs[BNXT_FW_STATUS_REG_CNT];
 442         uint32_t        reset_inprogress_reg_mask;
 443 #define BNXT_NUM_RESET_REG      16
 444         uint8_t         reg_array_cnt;
 445         uint32_t        reset_reg[BNXT_NUM_RESET_REG];
 446         uint32_t        reset_reg_val[BNXT_NUM_RESET_REG];
 447         uint8_t         delay_after_reset[BNXT_NUM_RESET_REG];
 448 #define BNXT_FLAG_ERROR_RECOVERY_HOST   BIT(0)
 449 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1)
 450 #define BNXT_FLAG_MASTER_FUNC           BIT(2)
 451 #define BNXT_FLAG_RECOVERY_ENABLED      BIT(3)
 452         uint32_t        flags;
 453
 454         uint32_t        last_heart_beat;
 455         uint32_t        last_reset_counter;
 456 };
 457
 458 /* address space location of register */
 459 #define BNXT_FW_STATUS_REG_TYPE_MASK    3
 460 /* register is located in PCIe config space */
 461 #define BNXT_FW_STATUS_REG_TYPE_CFG     0
 462 /* register is located in GRC address space */
 463 #define BNXT_FW_STATUS_REG_TYPE_GRC     1
 464 /* register is located in BAR0  */
 465 #define BNXT_FW_STATUS_REG_TYPE_BAR0    2
 466 /* register is located in BAR1  */
 467 #define BNXT_FW_STATUS_REG_TYPE_BAR1    3
 468
 469 #define BNXT_FW_STATUS_REG_TYPE(reg)    ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK)
 470 #define BNXT_FW_STATUS_REG_OFF(reg)     ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK)
 471
 472 #define BNXT_GRCP_WINDOW_2_BASE         0x2000
 473 #define BNXT_GRCP_WINDOW_3_BASE         0x3000
 474
 475 #define BNXT_FW_STATUS_SHUTDOWN         0x100000
 476
 477 #define BNXT_HWRM_SHORT_REQ_LEN         sizeof(struct hwrm_short_input)
 478 struct bnxt {
 479         void                            *bar0;
 480
 481         struct rte_eth_dev              *eth_dev;
 482         struct rte_eth_rss_conf         rss_conf;
 483         struct rte_pci_device           *pdev;
 484         void                            *doorbell_base;
 485
 486         uint32_t                flags;
 487 #define BNXT_FLAG_REGISTERED            BIT(0)
 488 #define BNXT_FLAG_VF                    BIT(1)
 489 #define BNXT_FLAG_PORT_STATS            BIT(2)
 490 #define BNXT_FLAG_JUMBO                 BIT(3)
 491 #define BNXT_FLAG_SHORT_CMD             BIT(4)
 492 #define BNXT_FLAG_UPDATE_HASH           BIT(5)
 493 #define BNXT_FLAG_PTP_SUPPORTED         BIT(6)
 494 #define BNXT_FLAG_MULTI_HOST            BIT(7)
 495 #define BNXT_FLAG_EXT_RX_PORT_STATS     BIT(8)
 496 #define BNXT_FLAG_EXT_TX_PORT_STATS     BIT(9)
 497 #define BNXT_FLAG_KONG_MB_EN            BIT(10)
 498 #define BNXT_FLAG_TRUSTED_VF_EN         BIT(11)
 499 #define BNXT_FLAG_DFLT_VNIC_SET         BIT(12)
 500 #define BNXT_FLAG_THOR_CHIP             BIT(13)
 501 #define BNXT_FLAG_STINGRAY              BIT(14)
 502 #define BNXT_FLAG_FW_RESET              BIT(15)
 503 #define BNXT_FLAG_FATAL_ERROR           BIT(16)
 504 #define BNXT_FLAG_FW_CAP_IF_CHANGE              BIT(17)
 505 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE   BIT(18)
 506 #define BNXT_FLAG_FW_CAP_ERROR_RECOVERY         BIT(19)
 507 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED     BIT(20)
 508 #define BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD     BIT(21)
 509 #define BNXT_FLAG_EXT_STATS_SUPPORTED           BIT(22)
 510 #define BNXT_FLAG_NEW_RM                        BIT(23)
 511 #define BNXT_FLAG_INIT_DONE                     BIT(24)
 512 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS         BIT(25)
 513 #define BNXT_FLAG_ADV_FLOW_MGMT                 BIT(26)
 514 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
 515 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
 516 #define BNXT_NPAR(bp)           ((bp)->port_partition_type)
 517 #define BNXT_MH(bp)             ((bp)->flags & BNXT_FLAG_MULTI_HOST)
 518 #define BNXT_SINGLE_PF(bp)      (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
 519 #define BNXT_USE_CHIMP_MB       0 //For non-CFA commands, everything uses Chimp.
 520 #define BNXT_USE_KONG(bp)       ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
 521 #define BNXT_VF_IS_TRUSTED(bp)  ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
 522 #define BNXT_CHIP_THOR(bp)      ((bp)->flags & BNXT_FLAG_THOR_CHIP)
 523 #define BNXT_STINGRAY(bp)       ((bp)->flags & BNXT_FLAG_STINGRAY)
 524 #define BNXT_HAS_NQ(bp)         BNXT_CHIP_THOR(bp)
 525 #define BNXT_HAS_RING_GRPS(bp)  (!BNXT_CHIP_THOR(bp))
 526
 527         uint32_t                flow_flags;
 528 #define BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN     BIT(0)
 529         pthread_mutex_t         flow_lock;
 530
 531         uint32_t                vnic_cap_flags;
 532 #define BNXT_VNIC_CAP_COS_CLASSIFY      BIT(0)
 533         unsigned int            rx_nr_rings;
 534         unsigned int            rx_cp_nr_rings;
 535         unsigned int            rx_num_qs_per_vnic;
 536         struct bnxt_rx_queue **rx_queues;
 537         const void              *rx_mem_zone;
 538         struct rx_port_stats    *hw_rx_port_stats;
 539         rte_iova_t              hw_rx_port_stats_map;
 540         struct rx_port_stats_ext    *hw_rx_port_stats_ext;
 541         rte_iova_t              hw_rx_port_stats_ext_map;
 542         uint16_t                fw_rx_port_stats_ext_size;
 543
 544         unsigned int            tx_nr_rings;
 545         unsigned int            tx_cp_nr_rings;
 546         struct bnxt_tx_queue **tx_queues;
 547         const void              *tx_mem_zone;
 548         struct tx_port_stats    *hw_tx_port_stats;
 549         rte_iova_t              hw_tx_port_stats_map;
 550         struct tx_port_stats_ext    *hw_tx_port_stats_ext;
 551         rte_iova_t              hw_tx_port_stats_ext_map;
 552         uint16_t                fw_tx_port_stats_ext_size;
 553
 554         /* Default completion ring */
 555         struct bnxt_cp_ring_info        *async_cp_ring;
 556         struct bnxt_cp_ring_info        *rxtx_nq_ring;
 557         uint32_t                max_ring_grps;
 558         struct bnxt_ring_grp_info       *grp_info;
 559
 560         unsigned int            nr_vnics;
 561
 562 #define BNXT_GET_DEFAULT_VNIC(bp)       (&(bp)->vnic_info[0])
 563         struct bnxt_vnic_info   *vnic_info;
 564         STAILQ_HEAD(, bnxt_vnic_info)   free_vnic_list;
 565
 566         struct bnxt_filter_info *filter_info;
 567         STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
 568
 569         struct bnxt_irq         *irq_tbl;
 570
 571         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 572
 573         uint16_t                        hwrm_cmd_seq;
 574         uint16_t                        kong_cmd_seq;
 575         void                            *hwrm_cmd_resp_addr;
 576         rte_iova_t                      hwrm_cmd_resp_dma_addr;
 577         void                            *hwrm_short_cmd_req_addr;
 578         rte_iova_t                      hwrm_short_cmd_req_dma_addr;
 579         rte_spinlock_t                  hwrm_lock;
 580         pthread_mutex_t                 def_cp_lock;
 581         uint16_t                        max_req_len;
 582         uint16_t                        max_resp_len;
 583         uint16_t                        hwrm_max_ext_req_len;
 584
 585          /* default command timeout value of 50ms */
 586 #define HWRM_CMD_TIMEOUT                50000
 587         /* default HWRM request timeout value */
 588         uint32_t                        hwrm_cmd_timeout;
 589
 590         struct bnxt_link_info   link_info;
 591         struct bnxt_cos_queue_info      rx_cos_queue[BNXT_COS_QUEUE_COUNT];
 592         struct bnxt_cos_queue_info      tx_cos_queue[BNXT_COS_QUEUE_COUNT];
 593         uint8_t                 tx_cosq_id[BNXT_COS_QUEUE_COUNT];
 594         uint8_t                 rx_cosq_cnt;
 595         uint8_t                 max_tc;
 596         uint8_t                 max_lltc;
 597         uint8_t                 max_q;
 598
 599         uint16_t                fw_fid;
 600         uint8_t                 dflt_mac_addr[RTE_ETHER_ADDR_LEN];
 601         uint16_t                max_rsscos_ctx;
 602         uint16_t                max_cp_rings;
 603         uint16_t                max_tx_rings;
 604         uint16_t                max_rx_rings;
 605         uint16_t                max_nq_rings;
 606         uint16_t                max_l2_ctx;
 607         uint16_t                max_rx_em_flows;
 608         uint16_t                max_vnics;
 609         uint16_t                max_stat_ctx;
 610         uint16_t                max_tpa_v2;
 611         uint16_t                first_vf_id;
 612         uint16_t                vlan;
 613 #define BNXT_OUTER_TPID_MASK    0x0000ffff
 614 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000
 615 #define BNXT_OUTER_TPID_BD_SHFT 16
 616         uint32_t                outer_tpid_bd;
 617         struct bnxt_pf_info     pf;
 618         uint8_t                 port_partition_type;
 619         uint8_t                 dev_stopped;
 620         uint8_t                 vxlan_port_cnt;
 621         uint8_t                 geneve_port_cnt;
 622         uint16_t                vxlan_port;
 623         uint16_t                geneve_port;
 624         uint16_t                vxlan_fw_dst_port_id;
 625         uint16_t                geneve_fw_dst_port_id;
 626         uint32_t                fw_ver;
 627         uint32_t                hwrm_spec_code;
 628
 629         struct bnxt_led_info    leds[BNXT_MAX_LED];
 630         uint8_t                 num_leds;
 631         struct bnxt_ptp_cfg     *ptp_cfg;
 632         uint16_t                vf_resv_strategy;
 633         struct bnxt_ctx_mem_info        *ctx;
 634
 635         uint16_t                fw_reset_min_msecs;
 636         uint16_t                fw_reset_max_msecs;
 637
 638         /* Struct to hold adapter error recovery related info */
 639         struct bnxt_error_recovery_info *recovery_info;
 640 };
 641
 642 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete);
 643 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
 644 int is_bnxt_in_error(struct bnxt *bp);
 645 uint16_t bnxt_rss_ctxts(const struct bnxt *bp);
 646
 647 int bnxt_map_fw_health_status_regs(struct bnxt *bp);
 648 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index);
 649 void bnxt_schedule_fw_health_check(struct bnxt *bp);
 650
 651 bool is_bnxt_supported(struct rte_eth_dev *dev);
 652 bool bnxt_stratus_device(struct bnxt *bp);
 653 extern const struct rte_flow_ops bnxt_flow_ops;
 654 #define bnxt_acquire_flow_lock(bp) \
 655         pthread_mutex_lock(&(bp)->flow_lock)
 656
 657 #define bnxt_release_flow_lock(bp) \
 658         pthread_mutex_unlock(&(bp)->flow_lock)
 659
 660 extern int bnxt_logtype_driver;
 661 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
 662         rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
 663                 __func__, ## args)
 664
 665 #define PMD_DRV_LOG(level, fmt, args...) \
 666         PMD_DRV_LOG_RAW(level, fmt, ## args)
 667 #endif