drivers/net/bnxt/bnxt.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _BNXT_H_
   7 #define _BNXT_H_
   8
   9 #include <inttypes.h>
  10 #include <stdbool.h>
  11 #include <sys/queue.h>
  12
  13 #include <rte_pci.h>
  14 #include <rte_bus_pci.h>
  15 #include <rte_ethdev_driver.h>
  16 #include <rte_memory.h>
  17 #include <rte_lcore.h>
  18 #include <rte_spinlock.h>
  19 #include <rte_time.h>
  20
  21 #include "bnxt_cpr.h"
  22 #include "bnxt_util.h"
  23
  24 #define BNXT_MAX_MTU            9574
  25 #define VLAN_TAG_SIZE           4
  26 #define BNXT_NUM_VLANS          2
  27 #define BNXT_MAX_PKT_LEN        (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\
  28                                  RTE_ETHER_CRC_LEN +\
  29                                  (BNXT_NUM_VLANS * VLAN_TAG_SIZE))
  30 #define BNXT_VF_RSV_NUM_RSS_CTX 1
  31 #define BNXT_VF_RSV_NUM_L2_CTX  4
  32 /* TODO: For now, do not support VMDq/RFS on VFs. */
  33 #define BNXT_VF_RSV_NUM_VNIC    1
  34 #define BNXT_MAX_LED            4
  35 #define BNXT_MIN_RING_DESC      16
  36 #define BNXT_MAX_TX_RING_DESC   4096
  37 #define BNXT_MAX_RX_RING_DESC   8192
  38 #define BNXT_DB_SIZE            0x80
  39
  40 #define TPA_MAX_AGGS            64
  41 #define TPA_MAX_AGGS_TH         1024
  42
  43 #define TPA_MAX_NUM_SEGS        32
  44 #define TPA_MAX_SEGS_TH         8 /* 32 segments in 4-segment units */
  45 #define TPA_MAX_SEGS            5 /* 32 segments in log2 units */
  46
  47 #define BNXT_TPA_MAX_AGGS(bp) \
  48         (BNXT_CHIP_THOR(bp) ? TPA_MAX_AGGS_TH : \
  49                              TPA_MAX_AGGS)
  50
  51 #define BNXT_TPA_MAX_SEGS(bp) \
  52         (BNXT_CHIP_THOR(bp) ? TPA_MAX_SEGS_TH : \
  53                               TPA_MAX_SEGS)
  54
  55 #ifdef RTE_ARCH_ARM64
  56 #define BNXT_NUM_ASYNC_CPR(bp) (BNXT_STINGRAY(bp) ? 0 : 1)
  57 #else
  58 #define BNXT_NUM_ASYNC_CPR(bp) 1
  59 #endif
  60
  61 #define BNXT_MISC_VEC_ID               RTE_INTR_VEC_ZERO_OFFSET
  62 #define BNXT_RX_VEC_START              RTE_INTR_VEC_RXTX_OFFSET
  63
  64 /* Chimp Communication Channel */
  65 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET          0x0
  66 #define GRCPF_REG_CHIMP_COMM_TRIGGER            0x100
  67 /* Kong Communication Channel */
  68 #define GRCPF_REG_KONG_CHANNEL_OFFSET           0xA00
  69 #define GRCPF_REG_KONG_COMM_TRIGGER             0xB00
  70
  71 #define BNXT_INT_LAT_TMR_MIN                    75
  72 #define BNXT_INT_LAT_TMR_MAX                    150
  73 #define BNXT_NUM_CMPL_AGGR_INT                  36
  74 #define BNXT_CMPL_AGGR_DMA_TMR                  37
  75 #define BNXT_NUM_CMPL_DMA_AGGR                  36
  76 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT       50
  77 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT       12
  78
  79 struct bnxt_led_info {
  80         uint8_t      led_id;
  81         uint8_t      led_type;
  82         uint8_t      led_group_id;
  83         uint8_t      unused;
  84         uint16_t  led_state_caps;
  85 #define BNXT_LED_ALT_BLINK_CAP(x)       ((x) &  \
  86         rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
  87
  88         uint16_t  led_color_caps;
  89 };
  90
  91 struct bnxt_led_cfg {
  92         uint8_t led_id;
  93         uint8_t led_state;
  94         uint8_t led_color;
  95         uint8_t unused;
  96         uint16_t led_blink_on;
  97         uint16_t led_blink_off;
  98         uint8_t led_group_id;
  99         uint8_t rsvd;
 100 };
 101
 102 #define BNXT_LED_DFLT_ENA                               \
 103         (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID |             \
 104          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE |          \
 105          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON |       \
 106          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF |      \
 107          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
 108
 109 #define BNXT_LED_DFLT_ENA_SHIFT         6
 110
 111 #define BNXT_LED_DFLT_ENABLES(x)                        \
 112         rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
 113
 114 enum bnxt_hw_context {
 115         HW_CONTEXT_NONE     = 0,
 116         HW_CONTEXT_IS_RSS   = 1,
 117         HW_CONTEXT_IS_COS   = 2,
 118         HW_CONTEXT_IS_LB    = 3,
 119 };
 120
 121 struct bnxt_vlan_table_entry {
 122         uint16_t                tpid;
 123         uint16_t                vid;
 124 } __attribute__((packed));
 125
 126 struct bnxt_vlan_antispoof_table_entry {
 127         uint16_t                tpid;
 128         uint16_t                vid;
 129         uint16_t                mask;
 130 } __attribute__((packed));
 131
 132 struct bnxt_child_vf_info {
 133         void                    *req_buf;
 134         struct bnxt_vlan_table_entry    *vlan_table;
 135         struct bnxt_vlan_antispoof_table_entry  *vlan_as_table;
 136         STAILQ_HEAD(, bnxt_filter_info) filter;
 137         uint32_t                func_cfg_flags;
 138         uint32_t                l2_rx_mask;
 139         uint16_t                fid;
 140         uint16_t                max_tx_rate;
 141         uint16_t                dflt_vlan;
 142         uint16_t                vlan_count;
 143         uint8_t                 mac_spoof_en;
 144         uint8_t                 vlan_spoof_en;
 145         bool                    random_mac;
 146         bool                    persist_stats;
 147 };
 148
 149 struct bnxt_pf_info {
 150 #define BNXT_FIRST_PF_FID       1
 151 #define BNXT_MAX_VFS(bp)        (bp->pf.max_vfs)
 152 #define BNXT_TOTAL_VFS(bp)      ((bp)->pf.total_vfs)
 153 #define BNXT_FIRST_VF_FID       128
 154 #define BNXT_PF_RINGS_USED(bp)  bnxt_get_num_queues(bp)
 155 #define BNXT_PF_RINGS_AVAIL(bp) (bp->pf.max_cp_rings - BNXT_PF_RINGS_USED(bp))
 156         uint16_t                port_id;
 157         uint16_t                first_vf_id;
 158         uint16_t                active_vfs;
 159         uint16_t                max_vfs;
 160         uint16_t                total_vfs; /* Total VFs possible.
 161                                             * Not necessarily enabled.
 162                                             */
 163         uint32_t                func_cfg_flags;
 164         void                    *vf_req_buf;
 165         rte_iova_t              vf_req_buf_dma_addr;
 166         uint32_t                vf_req_fwd[8];
 167         uint16_t                total_vnics;
 168         struct bnxt_child_vf_info       *vf_info;
 169 #define BNXT_EVB_MODE_NONE      0
 170 #define BNXT_EVB_MODE_VEB       1
 171 #define BNXT_EVB_MODE_VEPA      2
 172         uint8_t                 evb_mode;
 173 };
 174
 175 /* Max wait time is 10 * 100ms = 1s */
 176 #define BNXT_LINK_WAIT_CNT      10
 177 #define BNXT_LINK_WAIT_INTERVAL 100
 178 struct bnxt_link_info {
 179         uint32_t                phy_flags;
 180         uint8_t                 mac_type;
 181         uint8_t                 phy_link_status;
 182         uint8_t                 loop_back;
 183         uint8_t                 link_up;
 184         uint8_t                 duplex;
 185         uint8_t                 pause;
 186         uint8_t                 force_pause;
 187         uint8_t                 auto_pause;
 188         uint8_t                 auto_mode;
 189 #define PHY_VER_LEN             3
 190         uint8_t                 phy_ver[PHY_VER_LEN];
 191         uint16_t                link_speed;
 192         uint16_t                support_speeds;
 193         uint16_t                auto_link_speed;
 194         uint16_t                force_link_speed;
 195         uint16_t                auto_link_speed_mask;
 196         uint32_t                preemphasis;
 197         uint8_t                 phy_type;
 198         uint8_t                 media_type;
 199 };
 200
 201 #define BNXT_COS_QUEUE_COUNT    8
 202 struct bnxt_cos_queue_info {
 203         uint8_t id;
 204         uint8_t profile;
 205 };
 206
 207 struct rte_flow {
 208         STAILQ_ENTRY(rte_flow) next;
 209         struct bnxt_filter_info *filter;
 210         struct bnxt_vnic_info   *vnic;
 211 };
 212
 213 #define BNXT_PTP_FLAGS_PATH_TX          0x0
 214 #define BNXT_PTP_FLAGS_PATH_RX          0x1
 215 #define BNXT_PTP_FLAGS_CURRENT_TIME     0x2
 216
 217 struct bnxt_ptp_cfg {
 218 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT  0x400
 219 #define BNXT_GRCPF_REG_SYNC_TIME        0x480
 220 #define BNXT_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 221         struct rte_timecounter      tc;
 222         struct rte_timecounter      tx_tstamp_tc;
 223         struct rte_timecounter      rx_tstamp_tc;
 224         struct bnxt             *bp;
 225 #define BNXT_MAX_TX_TS  1
 226         uint16_t                        rxctl;
 227 #define BNXT_PTP_MSG_SYNC                       BIT(0)
 228 #define BNXT_PTP_MSG_DELAY_REQ                  BIT(1)
 229 #define BNXT_PTP_MSG_PDELAY_REQ                 BIT(2)
 230 #define BNXT_PTP_MSG_PDELAY_RESP                BIT(3)
 231 #define BNXT_PTP_MSG_FOLLOW_UP                  BIT(8)
 232 #define BNXT_PTP_MSG_DELAY_RESP                 BIT(9)
 233 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP      BIT(10)
 234 #define BNXT_PTP_MSG_ANNOUNCE                   BIT(11)
 235 #define BNXT_PTP_MSG_SIGNALING                  BIT(12)
 236 #define BNXT_PTP_MSG_MANAGEMENT                 BIT(13)
 237 #define BNXT_PTP_MSG_EVENTS             (BNXT_PTP_MSG_SYNC |            \
 238                                          BNXT_PTP_MSG_DELAY_REQ |       \
 239                                          BNXT_PTP_MSG_PDELAY_REQ |      \
 240                                          BNXT_PTP_MSG_PDELAY_RESP)
 241         uint8_t                 tx_tstamp_en:1;
 242         int                     rx_filter;
 243
 244 #define BNXT_PTP_RX_TS_L        0
 245 #define BNXT_PTP_RX_TS_H        1
 246 #define BNXT_PTP_RX_SEQ         2
 247 #define BNXT_PTP_RX_FIFO        3
 248 #define BNXT_PTP_RX_FIFO_PENDING 0x1
 249 #define BNXT_PTP_RX_FIFO_ADV    4
 250 #define BNXT_PTP_RX_REGS        5
 251
 252 #define BNXT_PTP_TX_TS_L        0
 253 #define BNXT_PTP_TX_TS_H        1
 254 #define BNXT_PTP_TX_SEQ         2
 255 #define BNXT_PTP_TX_FIFO        3
 256 #define BNXT_PTP_TX_FIFO_EMPTY   0x2
 257 #define BNXT_PTP_TX_REGS        4
 258         uint32_t                        rx_regs[BNXT_PTP_RX_REGS];
 259         uint32_t                        rx_mapped_regs[BNXT_PTP_RX_REGS];
 260         uint32_t                        tx_regs[BNXT_PTP_TX_REGS];
 261         uint32_t                        tx_mapped_regs[BNXT_PTP_TX_REGS];
 262
 263         /* On Thor, the Rx timestamp is present in the Rx completion record */
 264         uint64_t                        rx_timestamp;
 265 };
 266
 267 struct bnxt_coal {
 268         uint16_t                        num_cmpl_aggr_int;
 269         uint16_t                        num_cmpl_dma_aggr;
 270         uint16_t                        num_cmpl_dma_aggr_during_int;
 271         uint16_t                        int_lat_tmr_max;
 272         uint16_t                        int_lat_tmr_min;
 273         uint16_t                        cmpl_aggr_dma_tmr;
 274         uint16_t                        cmpl_aggr_dma_tmr_during_int;
 275 };
 276
 277 /* 64-bit doorbell */
 278 #define DBR_XID_SFT                             32
 279 #define DBR_PATH_L2                             (0x1ULL << 56)
 280 #define DBR_TYPE_SQ                             (0x0ULL << 60)
 281 #define DBR_TYPE_SRQ                            (0x2ULL << 60)
 282 #define DBR_TYPE_CQ                             (0x4ULL << 60)
 283 #define DBR_TYPE_NQ                             (0xaULL << 60)
 284 #define DBR_TYPE_NQ_ARM                         (0xbULL << 60)
 285
 286 #define BNXT_RSS_TBL_SIZE_THOR          512
 287 #define BNXT_RSS_ENTRIES_PER_CTX_THOR   64
 288 #define BNXT_MAX_RSS_CTXTS_THOR \
 289         (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR)
 290
 291 #define BNXT_MAX_TC    8
 292 #define BNXT_MAX_QUEUE 8
 293 #define BNXT_MAX_TC_Q  (BNXT_MAX_TC + 1)
 294 #define BNXT_MAX_Q     (bp->max_q + 1)
 295 #define BNXT_PAGE_SHFT 12
 296 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
 297 #define MAX_CTX_PAGES  (BNXT_PAGE_SIZE / 8)
 298
 299 #define PTU_PTE_VALID             0x1UL
 300 #define PTU_PTE_LAST              0x2UL
 301 #define PTU_PTE_NEXT_TO_LAST      0x4UL
 302
 303 struct bnxt_ring_mem_info {
 304         int                             nr_pages;
 305         int                             page_size;
 306         uint32_t                        flags;
 307 #define BNXT_RMEM_VALID_PTE_FLAG        1
 308 #define BNXT_RMEM_RING_PTE_FLAG         2
 309
 310         void                            **pg_arr;
 311         rte_iova_t                      *dma_arr;
 312         const struct rte_memzone        *mz;
 313
 314         uint64_t                        *pg_tbl;
 315         rte_iova_t                      pg_tbl_map;
 316         const struct rte_memzone        *pg_tbl_mz;
 317
 318         int                             vmem_size;
 319         void                            **vmem;
 320 };
 321
 322 struct bnxt_ctx_pg_info {
 323         uint32_t        entries;
 324         void            *ctx_pg_arr[MAX_CTX_PAGES];
 325         rte_iova_t      ctx_dma_arr[MAX_CTX_PAGES];
 326         struct bnxt_ring_mem_info ring_mem;
 327 };
 328
 329 struct bnxt_ctx_mem_info {
 330         uint32_t        qp_max_entries;
 331         uint16_t        qp_min_qp1_entries;
 332         uint16_t        qp_max_l2_entries;
 333         uint16_t        qp_entry_size;
 334         uint16_t        srq_max_l2_entries;
 335         uint32_t        srq_max_entries;
 336         uint16_t        srq_entry_size;
 337         uint16_t        cq_max_l2_entries;
 338         uint32_t        cq_max_entries;
 339         uint16_t        cq_entry_size;
 340         uint16_t        vnic_max_vnic_entries;
 341         uint16_t        vnic_max_ring_table_entries;
 342         uint16_t        vnic_entry_size;
 343         uint32_t        stat_max_entries;
 344         uint16_t        stat_entry_size;
 345         uint16_t        tqm_entry_size;
 346         uint32_t        tqm_min_entries_per_ring;
 347         uint32_t        tqm_max_entries_per_ring;
 348         uint32_t        mrav_max_entries;
 349         uint16_t        mrav_entry_size;
 350         uint16_t        tim_entry_size;
 351         uint32_t        tim_max_entries;
 352         uint8_t         tqm_entries_multiple;
 353
 354         uint32_t        flags;
 355 #define BNXT_CTX_FLAG_INITED    0x01
 356
 357         struct bnxt_ctx_pg_info qp_mem;
 358         struct bnxt_ctx_pg_info srq_mem;
 359         struct bnxt_ctx_pg_info cq_mem;
 360         struct bnxt_ctx_pg_info vnic_mem;
 361         struct bnxt_ctx_pg_info stat_mem;
 362         struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q];
 363 };
 364
 365 /* Maximum Firmware Reset bail out value in milliseconds */
 366 #define BNXT_MAX_FW_RESET_TIMEOUT       6000
 367 /* Minimum time required for the firmware readiness in milliseconds */
 368 #define BNXT_MIN_FW_READY_TIMEOUT       2000
 369 /* Frequency for the firmware readiness check in milliseconds */
 370 #define BNXT_FW_READY_WAIT_INTERVAL     100
 371
 372 #define US_PER_MS                       1000
 373 #define NS_PER_US                       1000
 374
 375 struct bnxt_error_recovery_info {
 376         /* All units in milliseconds */
 377         uint32_t        driver_polling_freq;
 378         uint32_t        master_func_wait_period;
 379         uint32_t        normal_func_wait_period;
 380         uint32_t        master_func_wait_period_after_reset;
 381         uint32_t        max_bailout_time_after_reset;
 382 #define BNXT_FW_STATUS_REG              0
 383 #define BNXT_FW_HEARTBEAT_CNT_REG       1
 384 #define BNXT_FW_RECOVERY_CNT_REG        2
 385 #define BNXT_FW_RESET_INPROG_REG        3
 386 #define BNXT_FW_STATUS_REG_CNT          4
 387         uint32_t        status_regs[BNXT_FW_STATUS_REG_CNT];
 388         uint32_t        mapped_status_regs[BNXT_FW_STATUS_REG_CNT];
 389         uint32_t        reset_inprogress_reg_mask;
 390 #define BNXT_NUM_RESET_REG      16
 391         uint8_t         reg_array_cnt;
 392         uint32_t        reset_reg[BNXT_NUM_RESET_REG];
 393         uint32_t        reset_reg_val[BNXT_NUM_RESET_REG];
 394         uint8_t         delay_after_reset[BNXT_NUM_RESET_REG];
 395 #define BNXT_FLAG_ERROR_RECOVERY_HOST   BIT(0)
 396 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1)
 397 #define BNXT_FLAG_MASTER_FUNC           BIT(2)
 398 #define BNXT_FLAG_RECOVERY_ENABLED      BIT(3)
 399         uint32_t        flags;
 400
 401         uint32_t        last_heart_beat;
 402         uint32_t        last_reset_counter;
 403 };
 404
 405 /* address space location of register */
 406 #define BNXT_FW_STATUS_REG_TYPE_MASK    3
 407 /* register is located in PCIe config space */
 408 #define BNXT_FW_STATUS_REG_TYPE_CFG     0
 409 /* register is located in GRC address space */
 410 #define BNXT_FW_STATUS_REG_TYPE_GRC     1
 411 /* register is located in BAR0  */
 412 #define BNXT_FW_STATUS_REG_TYPE_BAR0    2
 413 /* register is located in BAR1  */
 414 #define BNXT_FW_STATUS_REG_TYPE_BAR1    3
 415
 416 #define BNXT_FW_STATUS_REG_TYPE(reg)    ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK)
 417 #define BNXT_FW_STATUS_REG_OFF(reg)     ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK)
 418
 419 #define BNXT_GRCP_WINDOW_2_BASE         0x2000
 420 #define BNXT_GRCP_WINDOW_3_BASE         0x3000
 421
 422 #define BNXT_FW_STATUS_SHUTDOWN         0x100000
 423
 424 #define BNXT_HWRM_SHORT_REQ_LEN         sizeof(struct hwrm_short_input)
 425 struct bnxt {
 426         void                            *bar0;
 427
 428         struct rte_eth_dev              *eth_dev;
 429         struct rte_eth_rss_conf         rss_conf;
 430         struct rte_pci_device           *pdev;
 431         void                            *doorbell_base;
 432
 433         uint32_t                flags;
 434 #define BNXT_FLAG_REGISTERED            BIT(0)
 435 #define BNXT_FLAG_VF                    BIT(1)
 436 #define BNXT_FLAG_PORT_STATS            BIT(2)
 437 #define BNXT_FLAG_JUMBO                 BIT(3)
 438 #define BNXT_FLAG_SHORT_CMD             BIT(4)
 439 #define BNXT_FLAG_UPDATE_HASH           BIT(5)
 440 #define BNXT_FLAG_PTP_SUPPORTED         BIT(6)
 441 #define BNXT_FLAG_MULTI_HOST            BIT(7)
 442 #define BNXT_FLAG_EXT_RX_PORT_STATS     BIT(8)
 443 #define BNXT_FLAG_EXT_TX_PORT_STATS     BIT(9)
 444 #define BNXT_FLAG_KONG_MB_EN            BIT(10)
 445 #define BNXT_FLAG_TRUSTED_VF_EN         BIT(11)
 446 #define BNXT_FLAG_DFLT_VNIC_SET         BIT(12)
 447 #define BNXT_FLAG_THOR_CHIP             BIT(13)
 448 #define BNXT_FLAG_STINGRAY              BIT(14)
 449 #define BNXT_FLAG_FW_RESET              BIT(15)
 450 #define BNXT_FLAG_FATAL_ERROR           BIT(16)
 451 #define BNXT_FLAG_FW_CAP_IF_CHANGE              BIT(17)
 452 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE   BIT(18)
 453 #define BNXT_FLAG_FW_CAP_ERROR_RECOVERY         BIT(19)
 454 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED     BIT(20)
 455 #define BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD     BIT(21)
 456 #define BNXT_FLAG_EXT_STATS_SUPPORTED           BIT(22)
 457 #define BNXT_FLAG_NEW_RM                        BIT(23)
 458 #define BNXT_FLAG_INIT_DONE                     BIT(24)
 459 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS         BIT(25)
 460 #define BNXT_FLAG_ADV_FLOW_MGMT                 BIT(26)
 461 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
 462 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
 463 #define BNXT_NPAR(bp)           ((bp)->port_partition_type)
 464 #define BNXT_MH(bp)             ((bp)->flags & BNXT_FLAG_MULTI_HOST)
 465 #define BNXT_SINGLE_PF(bp)      (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
 466 #define BNXT_USE_CHIMP_MB       0 //For non-CFA commands, everything uses Chimp.
 467 #define BNXT_USE_KONG(bp)       ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
 468 #define BNXT_VF_IS_TRUSTED(bp)  ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
 469 #define BNXT_CHIP_THOR(bp)      ((bp)->flags & BNXT_FLAG_THOR_CHIP)
 470 #define BNXT_STINGRAY(bp)       ((bp)->flags & BNXT_FLAG_STINGRAY)
 471 #define BNXT_HAS_NQ(bp)         BNXT_CHIP_THOR(bp)
 472 #define BNXT_HAS_RING_GRPS(bp)  (!BNXT_CHIP_THOR(bp))
 473
 474         uint32_t                flow_flags;
 475 #define BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN     BIT(0)
 476         pthread_mutex_t         flow_lock;
 477
 478         uint32_t                vnic_cap_flags;
 479 #define BNXT_VNIC_CAP_COS_CLASSIFY      BIT(0)
 480         unsigned int            rx_nr_rings;
 481         unsigned int            rx_cp_nr_rings;
 482         unsigned int            rx_num_qs_per_vnic;
 483         struct bnxt_rx_queue **rx_queues;
 484         const void              *rx_mem_zone;
 485         struct rx_port_stats    *hw_rx_port_stats;
 486         rte_iova_t              hw_rx_port_stats_map;
 487         struct rx_port_stats_ext    *hw_rx_port_stats_ext;
 488         rte_iova_t              hw_rx_port_stats_ext_map;
 489         uint16_t                fw_rx_port_stats_ext_size;
 490
 491         unsigned int            tx_nr_rings;
 492         unsigned int            tx_cp_nr_rings;
 493         struct bnxt_tx_queue **tx_queues;
 494         const void              *tx_mem_zone;
 495         struct tx_port_stats    *hw_tx_port_stats;
 496         rte_iova_t              hw_tx_port_stats_map;
 497         struct tx_port_stats_ext    *hw_tx_port_stats_ext;
 498         rte_iova_t              hw_tx_port_stats_ext_map;
 499         uint16_t                fw_tx_port_stats_ext_size;
 500
 501         /* Default completion ring */
 502         struct bnxt_cp_ring_info        *async_cp_ring;
 503         struct bnxt_cp_ring_info        *rxtx_nq_ring;
 504         uint32_t                max_ring_grps;
 505         struct bnxt_ring_grp_info       *grp_info;
 506
 507         unsigned int            nr_vnics;
 508
 509 #define BNXT_GET_DEFAULT_VNIC(bp)       (&(bp)->vnic_info[0])
 510         struct bnxt_vnic_info   *vnic_info;
 511         STAILQ_HEAD(, bnxt_vnic_info)   free_vnic_list;
 512
 513         struct bnxt_filter_info *filter_info;
 514         STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
 515
 516         struct bnxt_irq         *irq_tbl;
 517
 518         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 519
 520         uint16_t                        hwrm_cmd_seq;
 521         uint16_t                        kong_cmd_seq;
 522         void                            *hwrm_cmd_resp_addr;
 523         rte_iova_t                      hwrm_cmd_resp_dma_addr;
 524         void                            *hwrm_short_cmd_req_addr;
 525         rte_iova_t                      hwrm_short_cmd_req_dma_addr;
 526         rte_spinlock_t                  hwrm_lock;
 527         uint16_t                        max_req_len;
 528         uint16_t                        max_resp_len;
 529         uint16_t                        hwrm_max_ext_req_len;
 530
 531          /* default command timeout value of 50ms */
 532 #define HWRM_CMD_TIMEOUT                50000
 533         /* default HWRM request timeout value */
 534         uint32_t                        hwrm_cmd_timeout;
 535
 536         struct bnxt_link_info   link_info;
 537         struct bnxt_cos_queue_info      rx_cos_queue[BNXT_COS_QUEUE_COUNT];
 538         struct bnxt_cos_queue_info      tx_cos_queue[BNXT_COS_QUEUE_COUNT];
 539         uint8_t                 tx_cosq_id[BNXT_COS_QUEUE_COUNT];
 540         uint8_t                 rx_cosq_cnt;
 541         uint8_t                 max_tc;
 542         uint8_t                 max_lltc;
 543         uint8_t                 max_q;
 544
 545         uint16_t                fw_fid;
 546         uint8_t                 dflt_mac_addr[RTE_ETHER_ADDR_LEN];
 547         uint16_t                max_rsscos_ctx;
 548         uint16_t                max_cp_rings;
 549         uint16_t                max_tx_rings;
 550         uint16_t                max_rx_rings;
 551         uint16_t                max_nq_rings;
 552         uint16_t                max_l2_ctx;
 553         uint16_t                max_rx_em_flows;
 554         uint16_t                max_vnics;
 555         uint16_t                max_stat_ctx;
 556         uint16_t                max_tpa_v2;
 557         uint16_t                first_vf_id;
 558         uint16_t                vlan;
 559 #define BNXT_OUTER_TPID_MASK    0x0000ffff
 560 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000
 561 #define BNXT_OUTER_TPID_BD_SHFT 16
 562         uint32_t                outer_tpid_bd;
 563         struct bnxt_pf_info     pf;
 564         uint8_t                 port_partition_type;
 565         uint8_t                 dev_stopped;
 566         uint8_t                 vxlan_port_cnt;
 567         uint8_t                 geneve_port_cnt;
 568         uint16_t                vxlan_port;
 569         uint16_t                geneve_port;
 570         uint16_t                vxlan_fw_dst_port_id;
 571         uint16_t                geneve_fw_dst_port_id;
 572         uint32_t                fw_ver;
 573         uint32_t                hwrm_spec_code;
 574
 575         struct bnxt_led_info    leds[BNXT_MAX_LED];
 576         uint8_t                 num_leds;
 577         struct bnxt_ptp_cfg     *ptp_cfg;
 578         uint16_t                vf_resv_strategy;
 579         struct bnxt_ctx_mem_info        *ctx;
 580
 581         uint16_t                fw_reset_min_msecs;
 582         uint16_t                fw_reset_max_msecs;
 583
 584         /* Struct to hold adapter error recovery related info */
 585         struct bnxt_error_recovery_info *recovery_info;
 586 };
 587
 588 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete);
 589 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
 590 int is_bnxt_in_error(struct bnxt *bp);
 591 uint16_t bnxt_rss_ctxts(const struct bnxt *bp);
 592
 593 int bnxt_map_fw_health_status_regs(struct bnxt *bp);
 594 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index);
 595 void bnxt_schedule_fw_health_check(struct bnxt *bp);
 596
 597 bool is_bnxt_supported(struct rte_eth_dev *dev);
 598 bool bnxt_stratus_device(struct bnxt *bp);
 599 extern const struct rte_flow_ops bnxt_flow_ops;
 600 #define bnxt_acquire_flow_lock(bp) \
 601         pthread_mutex_lock(&(bp)->flow_lock)
 602
 603 #define bnxt_release_flow_lock(bp) \
 604         pthread_mutex_unlock(&(bp)->flow_lock)
 605
 606 extern int bnxt_logtype_driver;
 607 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
 608         rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
 609                 __func__, ## args)
 610
 611 #define PMD_DRV_LOG(level, fmt, args...) \
 612         PMD_DRV_LOG_RAW(level, fmt, ## args)
 613 #endif