drivers/net/bnxt/bnxt.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _BNXT_H_
   7 #define _BNXT_H_
   8
   9 #include <inttypes.h>
  10 #include <stdbool.h>
  11 #include <sys/queue.h>
  12
  13 #include <rte_pci.h>
  14 #include <rte_bus_pci.h>
  15 #include <rte_ethdev_driver.h>
  16 #include <rte_memory.h>
  17 #include <rte_lcore.h>
  18 #include <rte_spinlock.h>
  19 #include <rte_time.h>
  20
  21 #include "bnxt_cpr.h"
  22 #include "bnxt_util.h"
  23
  24 #include "tf_core.h"
  25 #include "bnxt_ulp.h"
  26
  27 /* Vendor ID */
  28 #define PCI_VENDOR_ID_BROADCOM          0x14E4
  29
  30 /* Device IDs */
  31 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  32 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  33 #define BROADCOM_DEV_ID_STRATUS_NIC     0x1614
  34 #define BROADCOM_DEV_ID_57414_VF        0x16c1
  35 #define BROADCOM_DEV_ID_57301           0x16c8
  36 #define BROADCOM_DEV_ID_57302           0x16c9
  37 #define BROADCOM_DEV_ID_57304_PF        0x16ca
  38 #define BROADCOM_DEV_ID_57304_VF        0x16cb
  39 #define BROADCOM_DEV_ID_57417_MF        0x16cc
  40 #define BROADCOM_DEV_ID_NS2             0x16cd
  41 #define BROADCOM_DEV_ID_57311           0x16ce
  42 #define BROADCOM_DEV_ID_57312           0x16cf
  43 #define BROADCOM_DEV_ID_57402           0x16d0
  44 #define BROADCOM_DEV_ID_57404           0x16d1
  45 #define BROADCOM_DEV_ID_57406_PF        0x16d2
  46 #define BROADCOM_DEV_ID_57406_VF        0x16d3
  47 #define BROADCOM_DEV_ID_57402_MF        0x16d4
  48 #define BROADCOM_DEV_ID_57407_RJ45      0x16d5
  49 #define BROADCOM_DEV_ID_57412           0x16d6
  50 #define BROADCOM_DEV_ID_57414           0x16d7
  51 #define BROADCOM_DEV_ID_57416_RJ45      0x16d8
  52 #define BROADCOM_DEV_ID_57417_RJ45      0x16d9
  53 #define BROADCOM_DEV_ID_5741X_VF        0x16dc
  54 #define BROADCOM_DEV_ID_57412_MF        0x16de
  55 #define BROADCOM_DEV_ID_57314           0x16df
  56 #define BROADCOM_DEV_ID_57317_RJ45      0x16e0
  57 #define BROADCOM_DEV_ID_5731X_VF        0x16e1
  58 #define BROADCOM_DEV_ID_57417_SFP       0x16e2
  59 #define BROADCOM_DEV_ID_57416_SFP       0x16e3
  60 #define BROADCOM_DEV_ID_57317_SFP       0x16e4
  61 #define BROADCOM_DEV_ID_57404_MF        0x16e7
  62 #define BROADCOM_DEV_ID_57406_MF        0x16e8
  63 #define BROADCOM_DEV_ID_57407_SFP       0x16e9
  64 #define BROADCOM_DEV_ID_57407_MF        0x16ea
  65 #define BROADCOM_DEV_ID_57414_MF        0x16ec
  66 #define BROADCOM_DEV_ID_57416_MF        0x16ee
  67 #define BROADCOM_DEV_ID_57508           0x1750
  68 #define BROADCOM_DEV_ID_57504           0x1751
  69 #define BROADCOM_DEV_ID_57502           0x1752
  70 #define BROADCOM_DEV_ID_57508_MF1       0x1800
  71 #define BROADCOM_DEV_ID_57504_MF1       0x1801
  72 #define BROADCOM_DEV_ID_57502_MF1       0x1802
  73 #define BROADCOM_DEV_ID_57508_MF2       0x1803
  74 #define BROADCOM_DEV_ID_57504_MF2       0x1804
  75 #define BROADCOM_DEV_ID_57502_MF2       0x1805
  76 #define BROADCOM_DEV_ID_57500_VF1       0x1806
  77 #define BROADCOM_DEV_ID_57500_VF2       0x1807
  78 #define BROADCOM_DEV_ID_58802           0xd802
  79 #define BROADCOM_DEV_ID_58804           0xd804
  80 #define BROADCOM_DEV_ID_58808           0x16f0
  81 #define BROADCOM_DEV_ID_58802_VF        0xd800
  82
  83 #define BNXT_MAX_MTU            9574
  84 #define VLAN_TAG_SIZE           4
  85 #define BNXT_NUM_VLANS          2
  86 #define BNXT_MAX_PKT_LEN        (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\
  87                                  RTE_ETHER_CRC_LEN +\
  88                                  (BNXT_NUM_VLANS * VLAN_TAG_SIZE))
  89 /* FW adds extra 4 bytes for FCS */
  90 #define BNXT_VNIC_MRU(mtu)\
  91         ((mtu) + RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS)
  92 #define BNXT_VF_RSV_NUM_RSS_CTX 1
  93 #define BNXT_VF_RSV_NUM_L2_CTX  4
  94 /* TODO: For now, do not support VMDq/RFS on VFs. */
  95 #define BNXT_VF_RSV_NUM_VNIC    1
  96 #define BNXT_MAX_LED            4
  97 #define BNXT_MIN_RING_DESC      16
  98 #define BNXT_MAX_TX_RING_DESC   4096
  99 #define BNXT_MAX_RX_RING_DESC   8192
 100 #define BNXT_DB_SIZE            0x80
 101
 102 #define TPA_MAX_AGGS            64
 103 #define TPA_MAX_AGGS_TH         1024
 104
 105 #define TPA_MAX_NUM_SEGS        32
 106 #define TPA_MAX_SEGS_TH         8 /* 32 segments in 4-segment units */
 107 #define TPA_MAX_SEGS            5 /* 32 segments in log2 units */
 108
 109 #define BNXT_TPA_MAX_AGGS(bp) \
 110         (BNXT_CHIP_THOR(bp) ? TPA_MAX_AGGS_TH : \
 111                              TPA_MAX_AGGS)
 112
 113 #define BNXT_TPA_MAX_SEGS(bp) \
 114         (BNXT_CHIP_THOR(bp) ? TPA_MAX_SEGS_TH : \
 115                               TPA_MAX_SEGS)
 116
 117 #ifdef RTE_ARCH_ARM64
 118 #define BNXT_NUM_ASYNC_CPR(bp) (BNXT_STINGRAY(bp) ? 0 : 1)
 119 #else
 120 #define BNXT_NUM_ASYNC_CPR(bp) 1
 121 #endif
 122
 123 /* In FreeBSD OS, nic_uio driver does not support interrupts */
 124 #ifdef RTE_EXEC_ENV_FREEBSD
 125 #ifdef BNXT_NUM_ASYNC_CPR
 126 #undef BNXT_NUM_ASYNC_CPR
 127 #endif
 128 #define BNXT_NUM_ASYNC_CPR(bp)  0
 129 #endif
 130
 131 #define BNXT_MISC_VEC_ID               RTE_INTR_VEC_ZERO_OFFSET
 132 #define BNXT_RX_VEC_START              RTE_INTR_VEC_RXTX_OFFSET
 133
 134 /* Chimp Communication Channel */
 135 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET          0x0
 136 #define GRCPF_REG_CHIMP_COMM_TRIGGER            0x100
 137 /* Kong Communication Channel */
 138 #define GRCPF_REG_KONG_CHANNEL_OFFSET           0xA00
 139 #define GRCPF_REG_KONG_COMM_TRIGGER             0xB00
 140
 141 #define BNXT_INT_LAT_TMR_MIN                    75
 142 #define BNXT_INT_LAT_TMR_MAX                    150
 143 #define BNXT_NUM_CMPL_AGGR_INT                  36
 144 #define BNXT_CMPL_AGGR_DMA_TMR                  37
 145 #define BNXT_NUM_CMPL_DMA_AGGR                  36
 146 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT       50
 147 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT       12
 148
 149 struct bnxt_led_info {
 150         uint8_t      num_leds;
 151         uint8_t      led_id;
 152         uint8_t      led_type;
 153         uint8_t      led_group_id;
 154         uint8_t      unused;
 155         uint16_t  led_state_caps;
 156 #define BNXT_LED_ALT_BLINK_CAP(x)       ((x) &  \
 157         rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
 158
 159         uint16_t  led_color_caps;
 160 };
 161
 162 struct bnxt_led_cfg {
 163         uint8_t led_id;
 164         uint8_t led_state;
 165         uint8_t led_color;
 166         uint8_t unused;
 167         uint16_t led_blink_on;
 168         uint16_t led_blink_off;
 169         uint8_t led_group_id;
 170         uint8_t rsvd;
 171 };
 172
 173 #define BNXT_LED_DFLT_ENA                               \
 174         (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID |             \
 175          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE |          \
 176          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON |       \
 177          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF |      \
 178          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
 179
 180 #define BNXT_LED_DFLT_ENA_SHIFT         6
 181
 182 #define BNXT_LED_DFLT_ENABLES(x)                        \
 183         rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
 184
 185 enum bnxt_hw_context {
 186         HW_CONTEXT_NONE     = 0,
 187         HW_CONTEXT_IS_RSS   = 1,
 188         HW_CONTEXT_IS_COS   = 2,
 189         HW_CONTEXT_IS_LB    = 3,
 190 };
 191
 192 struct bnxt_vlan_table_entry {
 193         uint16_t                tpid;
 194         uint16_t                vid;
 195 } __rte_packed;
 196
 197 struct bnxt_vlan_antispoof_table_entry {
 198         uint16_t                tpid;
 199         uint16_t                vid;
 200         uint16_t                mask;
 201 } __rte_packed;
 202
 203 struct bnxt_child_vf_info {
 204         void                    *req_buf;
 205         struct bnxt_vlan_table_entry    *vlan_table;
 206         struct bnxt_vlan_antispoof_table_entry  *vlan_as_table;
 207         STAILQ_HEAD(, bnxt_filter_info) filter;
 208         uint32_t                func_cfg_flags;
 209         uint32_t                l2_rx_mask;
 210         uint16_t                fid;
 211         uint16_t                max_tx_rate;
 212         uint16_t                dflt_vlan;
 213         uint16_t                vlan_count;
 214         uint8_t                 mac_spoof_en;
 215         uint8_t                 vlan_spoof_en;
 216         bool                    random_mac;
 217         bool                    persist_stats;
 218 };
 219
 220 struct bnxt_parent_info {
 221 #define BNXT_PF_FID_INVALID     0xFFFF
 222         uint16_t                fid;
 223         uint16_t                vnic;
 224         uint16_t                port_id;
 225         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 226 };
 227
 228 struct bnxt_pf_info {
 229 #define BNXT_FIRST_PF_FID       1
 230 #define BNXT_MAX_VFS(bp)        ((bp)->pf->max_vfs)
 231 #define BNXT_MAX_VF_REPS        64
 232 #define BNXT_TOTAL_VFS(bp)      ((bp)->pf->total_vfs)
 233 #define BNXT_FIRST_VF_FID       128
 234 #define BNXT_PF_RINGS_USED(bp)  bnxt_get_num_queues(bp)
 235 #define BNXT_PF_RINGS_AVAIL(bp) ((bp)->pf->max_cp_rings - \
 236                                  BNXT_PF_RINGS_USED(bp))
 237         uint16_t                port_id;
 238         uint16_t                first_vf_id;
 239         uint16_t                active_vfs;
 240         uint16_t                max_vfs;
 241         uint16_t                total_vfs; /* Total VFs possible.
 242                                             * Not necessarily enabled.
 243                                             */
 244         uint32_t                func_cfg_flags;
 245         void                    *vf_req_buf;
 246         rte_iova_t              vf_req_buf_dma_addr;
 247         uint32_t                vf_req_fwd[8];
 248         uint16_t                total_vnics;
 249         struct bnxt_child_vf_info       *vf_info;
 250 #define BNXT_EVB_MODE_NONE      0
 251 #define BNXT_EVB_MODE_VEB       1
 252 #define BNXT_EVB_MODE_VEPA      2
 253         uint8_t                 evb_mode;
 254 };
 255
 256 /* Max wait time for link up is 10s and link down is 500ms */
 257 #define BNXT_LINK_UP_WAIT_CNT   200
 258 #define BNXT_LINK_DOWN_WAIT_CNT 10
 259 #define BNXT_LINK_WAIT_INTERVAL 50
 260 struct bnxt_link_info {
 261         uint32_t                phy_flags;
 262         uint8_t                 mac_type;
 263         uint8_t                 phy_link_status;
 264         uint8_t                 loop_back;
 265         uint8_t                 link_up;
 266         uint8_t                 duplex;
 267         uint8_t                 pause;
 268         uint8_t                 force_pause;
 269         uint8_t                 auto_pause;
 270         uint8_t                 auto_mode;
 271 #define PHY_VER_LEN             3
 272         uint8_t                 phy_ver[PHY_VER_LEN];
 273         uint16_t                link_speed;
 274         uint16_t                support_speeds;
 275         uint16_t                auto_link_speed;
 276         uint16_t                force_link_speed;
 277         uint16_t                auto_link_speed_mask;
 278         uint32_t                preemphasis;
 279         uint8_t                 phy_type;
 280         uint8_t                 media_type;
 281 };
 282
 283 #define BNXT_COS_QUEUE_COUNT    8
 284 struct bnxt_cos_queue_info {
 285         uint8_t id;
 286         uint8_t profile;
 287 };
 288
 289 struct rte_flow {
 290         STAILQ_ENTRY(rte_flow) next;
 291         struct bnxt_filter_info *filter;
 292         struct bnxt_vnic_info   *vnic;
 293 };
 294
 295 #define BNXT_PTP_FLAGS_PATH_TX          0x0
 296 #define BNXT_PTP_FLAGS_PATH_RX          0x1
 297 #define BNXT_PTP_FLAGS_CURRENT_TIME     0x2
 298
 299 struct bnxt_ptp_cfg {
 300 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT  0x400
 301 #define BNXT_GRCPF_REG_SYNC_TIME        0x480
 302 #define BNXT_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 303         struct rte_timecounter      tc;
 304         struct rte_timecounter      tx_tstamp_tc;
 305         struct rte_timecounter      rx_tstamp_tc;
 306         struct bnxt             *bp;
 307 #define BNXT_MAX_TX_TS  1
 308         uint16_t                        rxctl;
 309 #define BNXT_PTP_MSG_SYNC                       BIT(0)
 310 #define BNXT_PTP_MSG_DELAY_REQ                  BIT(1)
 311 #define BNXT_PTP_MSG_PDELAY_REQ                 BIT(2)
 312 #define BNXT_PTP_MSG_PDELAY_RESP                BIT(3)
 313 #define BNXT_PTP_MSG_FOLLOW_UP                  BIT(8)
 314 #define BNXT_PTP_MSG_DELAY_RESP                 BIT(9)
 315 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP      BIT(10)
 316 #define BNXT_PTP_MSG_ANNOUNCE                   BIT(11)
 317 #define BNXT_PTP_MSG_SIGNALING                  BIT(12)
 318 #define BNXT_PTP_MSG_MANAGEMENT                 BIT(13)
 319 #define BNXT_PTP_MSG_EVENTS             (BNXT_PTP_MSG_SYNC |            \
 320                                          BNXT_PTP_MSG_DELAY_REQ |       \
 321                                          BNXT_PTP_MSG_PDELAY_REQ |      \
 322                                          BNXT_PTP_MSG_PDELAY_RESP)
 323         uint8_t                 tx_tstamp_en:1;
 324         int                     rx_filter;
 325
 326 #define BNXT_PTP_RX_TS_L        0
 327 #define BNXT_PTP_RX_TS_H        1
 328 #define BNXT_PTP_RX_SEQ         2
 329 #define BNXT_PTP_RX_FIFO        3
 330 #define BNXT_PTP_RX_FIFO_PENDING 0x1
 331 #define BNXT_PTP_RX_FIFO_ADV    4
 332 #define BNXT_PTP_RX_REGS        5
 333
 334 #define BNXT_PTP_TX_TS_L        0
 335 #define BNXT_PTP_TX_TS_H        1
 336 #define BNXT_PTP_TX_SEQ         2
 337 #define BNXT_PTP_TX_FIFO        3
 338 #define BNXT_PTP_TX_FIFO_EMPTY   0x2
 339 #define BNXT_PTP_TX_REGS        4
 340         uint32_t                        rx_regs[BNXT_PTP_RX_REGS];
 341         uint32_t                        rx_mapped_regs[BNXT_PTP_RX_REGS];
 342         uint32_t                        tx_regs[BNXT_PTP_TX_REGS];
 343         uint32_t                        tx_mapped_regs[BNXT_PTP_TX_REGS];
 344
 345         /* On Thor, the Rx timestamp is present in the Rx completion record */
 346         uint64_t                        rx_timestamp;
 347 };
 348
 349 struct bnxt_coal {
 350         uint16_t                        num_cmpl_aggr_int;
 351         uint16_t                        num_cmpl_dma_aggr;
 352         uint16_t                        num_cmpl_dma_aggr_during_int;
 353         uint16_t                        int_lat_tmr_max;
 354         uint16_t                        int_lat_tmr_min;
 355         uint16_t                        cmpl_aggr_dma_tmr;
 356         uint16_t                        cmpl_aggr_dma_tmr_during_int;
 357 };
 358
 359 /* 64-bit doorbell */
 360 #define DBR_XID_SFT                             32
 361 #define DBR_PATH_L2                             (0x1ULL << 56)
 362 #define DBR_TYPE_SQ                             (0x0ULL << 60)
 363 #define DBR_TYPE_SRQ                            (0x2ULL << 60)
 364 #define DBR_TYPE_CQ                             (0x4ULL << 60)
 365 #define DBR_TYPE_NQ                             (0xaULL << 60)
 366 #define DBR_TYPE_NQ_ARM                         (0xbULL << 60)
 367
 368 #define BNXT_RSS_TBL_SIZE_THOR          512
 369 #define BNXT_RSS_ENTRIES_PER_CTX_THOR   64
 370 #define BNXT_MAX_RSS_CTXTS_THOR \
 371         (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR)
 372
 373 #define BNXT_MAX_TC    8
 374 #define BNXT_MAX_QUEUE 8
 375 #define BNXT_MAX_TC_Q  (BNXT_MAX_TC + 1)
 376 #define BNXT_PAGE_SHFT 12
 377 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
 378 #define MAX_CTX_PAGES  (BNXT_PAGE_SIZE / 8)
 379
 380 #define PTU_PTE_VALID             0x1UL
 381 #define PTU_PTE_LAST              0x2UL
 382 #define PTU_PTE_NEXT_TO_LAST      0x4UL
 383
 384 struct bnxt_ring_mem_info {
 385         int                             nr_pages;
 386         int                             page_size;
 387         uint32_t                        flags;
 388 #define BNXT_RMEM_VALID_PTE_FLAG        1
 389 #define BNXT_RMEM_RING_PTE_FLAG         2
 390
 391         void                            **pg_arr;
 392         rte_iova_t                      *dma_arr;
 393         const struct rte_memzone        *mz;
 394
 395         uint64_t                        *pg_tbl;
 396         rte_iova_t                      pg_tbl_map;
 397         const struct rte_memzone        *pg_tbl_mz;
 398
 399         int                             vmem_size;
 400         void                            **vmem;
 401 };
 402
 403 struct bnxt_ctx_pg_info {
 404         uint32_t        entries;
 405         void            *ctx_pg_arr[MAX_CTX_PAGES];
 406         rte_iova_t      ctx_dma_arr[MAX_CTX_PAGES];
 407         struct bnxt_ring_mem_info ring_mem;
 408 };
 409
 410 struct bnxt_ctx_mem_info {
 411         uint32_t        qp_max_entries;
 412         uint16_t        qp_min_qp1_entries;
 413         uint16_t        qp_max_l2_entries;
 414         uint16_t        qp_entry_size;
 415         uint16_t        srq_max_l2_entries;
 416         uint32_t        srq_max_entries;
 417         uint16_t        srq_entry_size;
 418         uint16_t        cq_max_l2_entries;
 419         uint32_t        cq_max_entries;
 420         uint16_t        cq_entry_size;
 421         uint16_t        vnic_max_vnic_entries;
 422         uint16_t        vnic_max_ring_table_entries;
 423         uint16_t        vnic_entry_size;
 424         uint32_t        stat_max_entries;
 425         uint16_t        stat_entry_size;
 426         uint16_t        tqm_entry_size;
 427         uint32_t        tqm_min_entries_per_ring;
 428         uint32_t        tqm_max_entries_per_ring;
 429         uint32_t        mrav_max_entries;
 430         uint16_t        mrav_entry_size;
 431         uint16_t        tim_entry_size;
 432         uint32_t        tim_max_entries;
 433         uint8_t         tqm_entries_multiple;
 434         uint8_t         tqm_fp_rings_count;
 435
 436         uint32_t        flags;
 437 #define BNXT_CTX_FLAG_INITED    0x01
 438
 439         struct bnxt_ctx_pg_info qp_mem;
 440         struct bnxt_ctx_pg_info srq_mem;
 441         struct bnxt_ctx_pg_info cq_mem;
 442         struct bnxt_ctx_pg_info vnic_mem;
 443         struct bnxt_ctx_pg_info stat_mem;
 444         struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q];
 445 };
 446
 447 struct bnxt_ctx_mem_buf_info {
 448         void            *va;
 449         rte_iova_t      dma;
 450         uint16_t        ctx_id;
 451         size_t          size;
 452 };
 453
 454 /* Maximum Firmware Reset bail out value in milliseconds */
 455 #define BNXT_MAX_FW_RESET_TIMEOUT       6000
 456 /* Minimum time required for the firmware readiness in milliseconds */
 457 #define BNXT_MIN_FW_READY_TIMEOUT       2000
 458 /* Frequency for the firmware readiness check in milliseconds */
 459 #define BNXT_FW_READY_WAIT_INTERVAL     100
 460
 461 #define US_PER_MS                       1000
 462 #define NS_PER_US                       1000
 463
 464 struct bnxt_error_recovery_info {
 465         /* All units in milliseconds */
 466         uint32_t        driver_polling_freq;
 467         uint32_t        master_func_wait_period;
 468         uint32_t        normal_func_wait_period;
 469         uint32_t        master_func_wait_period_after_reset;
 470         uint32_t        max_bailout_time_after_reset;
 471 #define BNXT_FW_STATUS_REG              0
 472 #define BNXT_FW_HEARTBEAT_CNT_REG       1
 473 #define BNXT_FW_RECOVERY_CNT_REG        2
 474 #define BNXT_FW_RESET_INPROG_REG        3
 475 #define BNXT_FW_STATUS_REG_CNT          4
 476         uint32_t        status_regs[BNXT_FW_STATUS_REG_CNT];
 477         uint32_t        mapped_status_regs[BNXT_FW_STATUS_REG_CNT];
 478         uint32_t        reset_inprogress_reg_mask;
 479 #define BNXT_NUM_RESET_REG      16
 480         uint8_t         reg_array_cnt;
 481         uint32_t        reset_reg[BNXT_NUM_RESET_REG];
 482         uint32_t        reset_reg_val[BNXT_NUM_RESET_REG];
 483         uint8_t         delay_after_reset[BNXT_NUM_RESET_REG];
 484 #define BNXT_FLAG_ERROR_RECOVERY_HOST   BIT(0)
 485 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1)
 486 #define BNXT_FLAG_MASTER_FUNC           BIT(2)
 487 #define BNXT_FLAG_RECOVERY_ENABLED      BIT(3)
 488         uint32_t        flags;
 489
 490         uint32_t        last_heart_beat;
 491         uint32_t        last_reset_counter;
 492 };
 493
 494 /* Frequency for the FUNC_DRV_IF_CHANGE retry in milliseconds */
 495 #define BNXT_IF_CHANGE_RETRY_INTERVAL   50
 496 /* Maximum retry count for FUNC_DRV_IF_CHANGE */
 497 #define BNXT_IF_CHANGE_RETRY_COUNT      40
 498
 499 struct bnxt_mark_info {
 500         uint32_t        mark_id;
 501         bool            valid;
 502 };
 503
 504 struct bnxt_rep_info {
 505         struct rte_eth_dev      *vfr_eth_dev;
 506         pthread_mutex_t         vfr_lock;
 507 };
 508
 509 /* address space location of register */
 510 #define BNXT_FW_STATUS_REG_TYPE_MASK    3
 511 /* register is located in PCIe config space */
 512 #define BNXT_FW_STATUS_REG_TYPE_CFG     0
 513 /* register is located in GRC address space */
 514 #define BNXT_FW_STATUS_REG_TYPE_GRC     1
 515 /* register is located in BAR0  */
 516 #define BNXT_FW_STATUS_REG_TYPE_BAR0    2
 517 /* register is located in BAR1  */
 518 #define BNXT_FW_STATUS_REG_TYPE_BAR1    3
 519
 520 #define BNXT_FW_STATUS_REG_TYPE(reg)    ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK)
 521 #define BNXT_FW_STATUS_REG_OFF(reg)     ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK)
 522
 523 #define BNXT_GRCP_WINDOW_2_BASE         0x2000
 524 #define BNXT_GRCP_WINDOW_3_BASE         0x3000
 525
 526 #define BNXT_GRCP_BASE_MASK             0xfffff000
 527 #define BNXT_GRCP_OFFSET_MASK           0x00000ffc
 528
 529 #define BNXT_FW_STATUS_HEALTHY          0x8000
 530 #define BNXT_FW_STATUS_SHUTDOWN         0x100000
 531
 532 #define BNXT_ETH_RSS_SUPPORT (  \
 533         ETH_RSS_IPV4 |          \
 534         ETH_RSS_NONFRAG_IPV4_TCP |      \
 535         ETH_RSS_NONFRAG_IPV4_UDP |      \
 536         ETH_RSS_IPV6 |          \
 537         ETH_RSS_NONFRAG_IPV6_TCP |      \
 538         ETH_RSS_NONFRAG_IPV6_UDP)
 539
 540 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 541                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 542                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 543                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 544                                      DEV_TX_OFFLOAD_TCP_TSO | \
 545                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 546                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 547                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 548                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 549                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 550                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 551                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 552
 553 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 554                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 555                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 556                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 557                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 558                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 559                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 560                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 561                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 562                                      DEV_RX_OFFLOAD_TCP_LRO | \
 563                                      DEV_RX_OFFLOAD_SCATTER | \
 564                                      DEV_RX_OFFLOAD_RSS_HASH)
 565
 566 #define  MAX_TABLE_SUPPORT 4
 567 #define  MAX_DIR_SUPPORT   2
 568 struct bnxt_dmabuf_info {
 569         uint32_t entry_num;
 570         int      fd[MAX_DIR_SUPPORT][MAX_TABLE_SUPPORT];
 571 };
 572
 573 #define BNXT_HWRM_SHORT_REQ_LEN         sizeof(struct hwrm_short_input)
 574
 575 struct bnxt_flow_stat_info {
 576         uint16_t                max_fc;
 577         uint16_t                flow_count;
 578         struct bnxt_ctx_mem_buf_info rx_fc_in_tbl;
 579         struct bnxt_ctx_mem_buf_info rx_fc_out_tbl;
 580         struct bnxt_ctx_mem_buf_info tx_fc_in_tbl;
 581         struct bnxt_ctx_mem_buf_info tx_fc_out_tbl;
 582 };
 583
 584 struct bnxt {
 585         void                            *bar0;
 586
 587         struct rte_eth_dev              *eth_dev;
 588         struct rte_pci_device           *pdev;
 589         void                            *doorbell_base;
 590
 591         uint32_t                flags;
 592 #define BNXT_FLAG_REGISTERED            BIT(0)
 593 #define BNXT_FLAG_VF                    BIT(1)
 594 #define BNXT_FLAG_PORT_STATS            BIT(2)
 595 #define BNXT_FLAG_JUMBO                 BIT(3)
 596 #define BNXT_FLAG_SHORT_CMD             BIT(4)
 597 #define BNXT_FLAG_UPDATE_HASH           BIT(5)
 598 #define BNXT_FLAG_PTP_SUPPORTED         BIT(6)
 599 #define BNXT_FLAG_MULTI_HOST            BIT(7)
 600 #define BNXT_FLAG_EXT_RX_PORT_STATS     BIT(8)
 601 #define BNXT_FLAG_EXT_TX_PORT_STATS     BIT(9)
 602 #define BNXT_FLAG_KONG_MB_EN            BIT(10)
 603 #define BNXT_FLAG_TRUSTED_VF_EN         BIT(11)
 604 #define BNXT_FLAG_DFLT_VNIC_SET         BIT(12)
 605 #define BNXT_FLAG_THOR_CHIP             BIT(13)
 606 #define BNXT_FLAG_STINGRAY              BIT(14)
 607 #define BNXT_FLAG_FW_RESET              BIT(15)
 608 #define BNXT_FLAG_FATAL_ERROR           BIT(16)
 609 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE   BIT(17)
 610 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED     BIT(18)
 611 #define BNXT_FLAG_EXT_STATS_SUPPORTED           BIT(19)
 612 #define BNXT_FLAG_NEW_RM                        BIT(20)
 613 #define BNXT_FLAG_NPAR_PF                       BIT(21)
 614 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS         BIT(22)
 615 #define BNXT_FLAG_FC_THREAD                     BIT(23)
 616 #define BNXT_FLAG_RX_VECTOR_PKT_MODE            BIT(24)
 617 #define BNXT_FLAG_FLOW_XSTATS_EN                BIT(25)
 618 #define BNXT_FLAG_DFLT_MAC_SET                  BIT(26)
 619 #define BNXT_FLAG_TRUFLOW_EN                    BIT(27)
 620 #define BNXT_FLAG_GFID_ENABLE                   BIT(28)
 621 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
 622 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
 623 #define BNXT_NPAR(bp)           ((bp)->flags & BNXT_FLAG_NPAR_PF)
 624 #define BNXT_MH(bp)             ((bp)->flags & BNXT_FLAG_MULTI_HOST)
 625 #define BNXT_SINGLE_PF(bp)      (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
 626 #define BNXT_USE_CHIMP_MB       0 //For non-CFA commands, everything uses Chimp.
 627 #define BNXT_USE_KONG(bp)       ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
 628 #define BNXT_VF_IS_TRUSTED(bp)  ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
 629 #define BNXT_CHIP_THOR(bp)      ((bp)->flags & BNXT_FLAG_THOR_CHIP)
 630 #define BNXT_STINGRAY(bp)       ((bp)->flags & BNXT_FLAG_STINGRAY)
 631 #define BNXT_HAS_NQ(bp)         BNXT_CHIP_THOR(bp)
 632 #define BNXT_HAS_RING_GRPS(bp)  (!BNXT_CHIP_THOR(bp))
 633 #define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN)
 634 #define BNXT_HAS_DFLT_MAC_SET(bp)      ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET)
 635 #define BNXT_TRUFLOW_EN(bp)     ((bp)->flags & BNXT_FLAG_TRUFLOW_EN)
 636 #define BNXT_GFID_ENABLED(bp)   ((bp)->flags & BNXT_FLAG_GFID_ENABLE)
 637
 638         uint32_t                fw_cap;
 639 #define BNXT_FW_CAP_HOT_RESET           BIT(0)
 640 #define BNXT_FW_CAP_IF_CHANGE           BIT(1)
 641 #define BNXT_FW_CAP_ERROR_RECOVERY      BIT(2)
 642 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD  BIT(3)
 643 #define BNXT_FW_CAP_ADV_FLOW_MGMT       BIT(5)
 644 #define BNXT_FW_CAP_ADV_FLOW_COUNTERS   BIT(6)
 645 #define BNXT_FW_CAP_HCOMM_FW_STATUS     BIT(7)
 646
 647         uint32_t                flow_flags;
 648 #define BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN     BIT(0)
 649         pthread_mutex_t         flow_lock;
 650
 651         uint32_t                vnic_cap_flags;
 652 #define BNXT_VNIC_CAP_COS_CLASSIFY      BIT(0)
 653         unsigned int            rx_nr_rings;
 654         unsigned int            rx_cp_nr_rings;
 655         unsigned int            rx_num_qs_per_vnic;
 656         struct bnxt_rx_queue **rx_queues;
 657         const void              *rx_mem_zone;
 658         struct rx_port_stats    *hw_rx_port_stats;
 659         rte_iova_t              hw_rx_port_stats_map;
 660         struct rx_port_stats_ext    *hw_rx_port_stats_ext;
 661         rte_iova_t              hw_rx_port_stats_ext_map;
 662         uint16_t                fw_rx_port_stats_ext_size;
 663
 664         unsigned int            tx_nr_rings;
 665         unsigned int            tx_cp_nr_rings;
 666         struct bnxt_tx_queue **tx_queues;
 667         const void              *tx_mem_zone;
 668         struct tx_port_stats    *hw_tx_port_stats;
 669         rte_iova_t              hw_tx_port_stats_map;
 670         struct tx_port_stats_ext    *hw_tx_port_stats_ext;
 671         rte_iova_t              hw_tx_port_stats_ext_map;
 672         uint16_t                fw_tx_port_stats_ext_size;
 673
 674         /* Default completion ring */
 675         struct bnxt_cp_ring_info        *async_cp_ring;
 676         struct bnxt_cp_ring_info        *rxtx_nq_ring;
 677         uint32_t                max_ring_grps;
 678         struct bnxt_ring_grp_info       *grp_info;
 679
 680         unsigned int            nr_vnics;
 681
 682 #define BNXT_GET_DEFAULT_VNIC(bp)       (&(bp)->vnic_info[0])
 683         struct bnxt_vnic_info   *vnic_info;
 684         STAILQ_HEAD(, bnxt_vnic_info)   free_vnic_list;
 685
 686         struct bnxt_filter_info *filter_info;
 687         STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
 688
 689         struct bnxt_irq         *irq_tbl;
 690
 691         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 692
 693         uint16_t                        chimp_cmd_seq;
 694         uint16_t                        kong_cmd_seq;
 695         void                            *hwrm_cmd_resp_addr;
 696         rte_iova_t                      hwrm_cmd_resp_dma_addr;
 697         void                            *hwrm_short_cmd_req_addr;
 698         rte_iova_t                      hwrm_short_cmd_req_dma_addr;
 699         rte_spinlock_t                  hwrm_lock;
 700         pthread_mutex_t                 def_cp_lock;
 701         uint16_t                        max_req_len;
 702         uint16_t                        max_resp_len;
 703         uint16_t                        hwrm_max_ext_req_len;
 704
 705          /* default command timeout value of 500ms */
 706 #define DFLT_HWRM_CMD_TIMEOUT           500000
 707          /* short command timeout value of 50ms */
 708 #define SHORT_HWRM_CMD_TIMEOUT          50000
 709         /* default HWRM request timeout value */
 710         uint32_t                        hwrm_cmd_timeout;
 711
 712         struct bnxt_link_info           *link_info;
 713         struct bnxt_cos_queue_info      *rx_cos_queue;
 714         struct bnxt_cos_queue_info      *tx_cos_queue;
 715         uint8_t                 tx_cosq_id[BNXT_COS_QUEUE_COUNT];
 716         uint8_t                 rx_cosq_cnt;
 717         uint8_t                 max_tc;
 718         uint8_t                 max_lltc;
 719         uint8_t                 max_q;
 720
 721         uint16_t                fw_fid;
 722         uint16_t                max_rsscos_ctx;
 723         uint16_t                max_cp_rings;
 724         uint16_t                max_tx_rings;
 725         uint16_t                max_rx_rings;
 726 #define MAX_STINGRAY_RINGS              128U
 727 /* For sake of symmetry, max Tx rings == max Rx rings, one stat ctx for each */
 728 #define BNXT_MAX_RX_RINGS(bp) \
 729         (BNXT_STINGRAY(bp) ? RTE_MIN(RTE_MIN(bp->max_rx_rings / 2U, \
 730                                              MAX_STINGRAY_RINGS), \
 731                                      bp->max_stat_ctx / 2U) : \
 732                                 RTE_MIN(bp->max_rx_rings / 2U, \
 733                                         bp->max_stat_ctx / 2U))
 734 #define BNXT_MAX_TX_RINGS(bp) \
 735         (RTE_MIN((bp)->max_tx_rings, BNXT_MAX_RX_RINGS(bp)))
 736
 737 #define BNXT_MAX_RINGS(bp) \
 738         (RTE_MIN((((bp)->max_cp_rings - BNXT_NUM_ASYNC_CPR(bp)) / 2U), \
 739                  BNXT_MAX_TX_RINGS(bp)))
 740
 741 #define BNXT_MAX_VF_REP_RINGS   8
 742
 743         uint16_t                max_nq_rings;
 744         uint16_t                max_l2_ctx;
 745         uint16_t                max_rx_em_flows;
 746         uint16_t                max_vnics;
 747         uint16_t                max_stat_ctx;
 748         uint16_t                max_tpa_v2;
 749         uint16_t                first_vf_id;
 750         uint16_t                vlan;
 751 #define BNXT_OUTER_TPID_MASK    0x0000ffff
 752 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000
 753 #define BNXT_OUTER_TPID_BD_SHFT 16
 754         uint32_t                outer_tpid_bd;
 755         struct bnxt_pf_info     *pf;
 756         struct bnxt_parent_info *parent;
 757         uint8_t                 port_cnt;
 758         uint8_t                 vxlan_port_cnt;
 759         uint8_t                 geneve_port_cnt;
 760         uint16_t                vxlan_port;
 761         uint16_t                geneve_port;
 762         uint16_t                vxlan_fw_dst_port_id;
 763         uint16_t                geneve_fw_dst_port_id;
 764         uint32_t                fw_ver;
 765         uint32_t                hwrm_spec_code;
 766
 767         struct bnxt_led_info    *leds;
 768         struct bnxt_ptp_cfg     *ptp_cfg;
 769         uint16_t                vf_resv_strategy;
 770         struct bnxt_ctx_mem_info        *ctx;
 771
 772         uint16_t                fw_reset_min_msecs;
 773         uint16_t                fw_reset_max_msecs;
 774         uint16_t                switch_domain_id;
 775         uint16_t                num_reps;
 776         struct bnxt_rep_info    *rep_info;
 777         uint16_t                *cfa_code_map;
 778         /* Struct to hold adapter error recovery related info */
 779         struct bnxt_error_recovery_info *recovery_info;
 780 #define BNXT_MARK_TABLE_SZ      (sizeof(struct bnxt_mark_info)  * 64 * 1024)
 781 /* TCAM and EM should be 16-bit only. Other modes not supported. */
 782 #define BNXT_FLOW_ID_MASK       0x0000ffff
 783         struct bnxt_mark_info   *mark_table;
 784
 785 #define BNXT_SVIF_INVALID       0xFFFF
 786         uint16_t                func_svif;
 787         uint16_t                port_svif;
 788
 789         struct tf               tfp;
 790         struct bnxt_dmabuf_info dmabuf;
 791         struct bnxt_ulp_context *ulp_ctx;
 792         struct bnxt_flow_stat_info *flow_stat;
 793         uint8_t                 flow_xstat;
 794         uint16_t                max_num_kflows;
 795 };
 796
 797 #define BNXT_FC_TIMER   1 /* Timer freq in Sec Flow Counters */
 798
 799 /**
 800  * Structure to store private data for each VF representor instance
 801  */
 802 struct bnxt_vf_representor {
 803         uint16_t                switch_domain_id;
 804         uint16_t                vf_id;
 805         uint16_t                fw_fid;
 806         uint16_t                dflt_vnic_id;
 807         uint16_t                svif;
 808         uint16_t                tx_cfa_action;
 809         uint16_t                rx_cfa_code;
 810         /* Private data store of associated PF/Trusted VF */
 811         struct rte_eth_dev      *parent_dev;
 812         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 813         uint8_t                 dflt_mac_addr[RTE_ETHER_ADDR_LEN];
 814         struct bnxt_rx_queue    **rx_queues;
 815         unsigned int            rx_nr_rings;
 816         unsigned int            tx_nr_rings;
 817         uint64_t                tx_pkts[BNXT_MAX_VF_REP_RINGS];
 818         uint64_t                tx_bytes[BNXT_MAX_VF_REP_RINGS];
 819         uint64_t                rx_pkts[BNXT_MAX_VF_REP_RINGS];
 820         uint64_t                rx_bytes[BNXT_MAX_VF_REP_RINGS];
 821         uint64_t                rx_drop_pkts[BNXT_MAX_VF_REP_RINGS];
 822         uint64_t                rx_drop_bytes[BNXT_MAX_VF_REP_RINGS];
 823 };
 824
 825 struct bnxt_vf_rep_tx_queue {
 826         struct bnxt_tx_queue *txq;
 827         struct bnxt_vf_representor *bp;
 828 };
 829
 830 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 831 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
 832                      bool exp_link_status);
 833 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
 834 int is_bnxt_in_error(struct bnxt *bp);
 835
 836 int bnxt_map_fw_health_status_regs(struct bnxt *bp);
 837 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index);
 838 void bnxt_schedule_fw_health_check(struct bnxt *bp);
 839
 840 bool is_bnxt_supported(struct rte_eth_dev *dev);
 841 bool bnxt_stratus_device(struct bnxt *bp);
 842 void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 843 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp);
 844 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
 845                         int wait_to_complete);
 846
 847 extern const struct rte_flow_ops bnxt_flow_ops;
 848
 849 #define bnxt_acquire_flow_lock(bp) \
 850         pthread_mutex_lock(&(bp)->flow_lock)
 851
 852 #define bnxt_release_flow_lock(bp) \
 853         pthread_mutex_unlock(&(bp)->flow_lock)
 854
 855 #define BNXT_VALID_VNIC_OR_RET(bp, vnic_id) do { \
 856         if ((vnic_id) >= (bp)->max_vnics) { \
 857                 rte_flow_error_set(error, \
 858                                 EINVAL, \
 859                                 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, \
 860                                 NULL, \
 861                                 "Group id is invalid!"); \
 862                 rc = -rte_errno; \
 863                 goto ret; \
 864         } \
 865 } while (0)
 866
 867 #define BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)    \
 868                 ((eth_dev)->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 869
 870 extern int bnxt_logtype_driver;
 871 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
 872         rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
 873                 __func__, ## args)
 874
 875 #define PMD_DRV_LOG(level, fmt, args...) \
 876           PMD_DRV_LOG_RAW(level, fmt, ## args)
 877
 878 extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops;
 879 int32_t bnxt_ulp_init(struct bnxt *bp);
 880 void bnxt_ulp_deinit(struct bnxt *bp);
 881
 882 uint16_t bnxt_get_vnic_id(uint16_t port);
 883 uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif);
 884 uint16_t bnxt_get_fw_func_id(uint16_t port);
 885 uint16_t bnxt_get_parif(uint16_t port);
 886 uint16_t bnxt_get_phy_port_id(uint16_t port);
 887 uint16_t bnxt_get_vport(uint16_t port);
 888 enum bnxt_ulp_intf_type
 889 bnxt_get_interface_type(uint16_t port);
 890
 891 void bnxt_cancel_fc_thread(struct bnxt *bp);
 892 void bnxt_flow_cnt_alarm_cb(void *arg);
 893 int bnxt_flow_stats_req(struct bnxt *bp);
 894 int bnxt_flow_stats_cnt(struct bnxt *bp);
 895 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp);
 896 #endif