drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29 #include "bnxt_util.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME "\n";
  34 int bnxt_logtype_driver;
  35
  36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  37
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  42 #define BROADCOM_DEV_ID_57301 0x16c8
  43 #define BROADCOM_DEV_ID_57302 0x16c9
  44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  47 #define BROADCOM_DEV_ID_NS2 0x16cd
  48 #define BROADCOM_DEV_ID_57311 0x16ce
  49 #define BROADCOM_DEV_ID_57312 0x16cf
  50 #define BROADCOM_DEV_ID_57402 0x16d0
  51 #define BROADCOM_DEV_ID_57404 0x16d1
  52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  56 #define BROADCOM_DEV_ID_57412 0x16d6
  57 #define BROADCOM_DEV_ID_57414 0x16d7
  58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  61 #define BROADCOM_DEV_ID_57412_MF 0x16de
  62 #define BROADCOM_DEV_ID_57314 0x16df
  63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  74 #define BROADCOM_DEV_ID_58802 0xd802
  75 #define BROADCOM_DEV_ID_58804 0xd804
  76 #define BROADCOM_DEV_ID_58808 0x16f0
  77 #define BROADCOM_DEV_ID_58802_VF 0xd800
  78
  79 static const struct rte_pci_id bnxt_pci_id_map[] = {
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  81                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  83                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 122         { .vendor_id = 0, /* sentinel */ },
 123 };
 124
 125 #define BNXT_ETH_RSS_SUPPORT (  \
 126         ETH_RSS_IPV4 |          \
 127         ETH_RSS_NONFRAG_IPV4_TCP |      \
 128         ETH_RSS_NONFRAG_IPV4_UDP |      \
 129         ETH_RSS_IPV6 |          \
 130         ETH_RSS_NONFRAG_IPV6_TCP |      \
 131         ETH_RSS_NONFRAG_IPV6_UDP)
 132
 133 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 134                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 135                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 136                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 137                                      DEV_TX_OFFLOAD_TCP_TSO | \
 138                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 139                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 140                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 141                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 142                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 143                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 144
 145 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 146                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 147                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 148                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 149                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 150                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 151                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 152                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 153                                      DEV_RX_OFFLOAD_TCP_LRO)
 154
 155 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 156 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 157 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 158 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 159
 160 /***********************/
 161
 162 /*
 163  * High level utility functions
 164  */
 165
 166 static void bnxt_free_mem(struct bnxt *bp)
 167 {
 168         bnxt_free_filter_mem(bp);
 169         bnxt_free_vnic_attributes(bp);
 170         bnxt_free_vnic_mem(bp);
 171
 172         bnxt_free_stats(bp);
 173         bnxt_free_tx_rings(bp);
 174         bnxt_free_rx_rings(bp);
 175 }
 176
 177 static int bnxt_alloc_mem(struct bnxt *bp)
 178 {
 179         int rc;
 180
 181         rc = bnxt_alloc_vnic_mem(bp);
 182         if (rc)
 183                 goto alloc_mem_err;
 184
 185         rc = bnxt_alloc_vnic_attributes(bp);
 186         if (rc)
 187                 goto alloc_mem_err;
 188
 189         rc = bnxt_alloc_filter_mem(bp);
 190         if (rc)
 191                 goto alloc_mem_err;
 192
 193         return 0;
 194
 195 alloc_mem_err:
 196         bnxt_free_mem(bp);
 197         return rc;
 198 }
 199
 200 static int bnxt_init_chip(struct bnxt *bp)
 201 {
 202         struct bnxt_rx_queue *rxq;
 203         struct rte_eth_link new;
 204         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 205         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 206         uint32_t intr_vector = 0;
 207         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 208         uint32_t vec = BNXT_MISC_VEC_ID;
 209         unsigned int i, j;
 210         int rc;
 211
 212         /* disable uio/vfio intr/eventfd mapping */
 213         rte_intr_disable(intr_handle);
 214
 215         if (bp->eth_dev->data->mtu > ETHER_MTU) {
 216                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 217                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 218                 bp->flags |= BNXT_FLAG_JUMBO;
 219         } else {
 220                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 221                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 222                 bp->flags &= ~BNXT_FLAG_JUMBO;
 223         }
 224
 225         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 226         if (rc) {
 227                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 228                 goto err_out;
 229         }
 230
 231         rc = bnxt_alloc_hwrm_rings(bp);
 232         if (rc) {
 233                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 234                 goto err_out;
 235         }
 236
 237         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 238         if (rc) {
 239                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 240                 goto err_out;
 241         }
 242
 243         rc = bnxt_mq_rx_configure(bp);
 244         if (rc) {
 245                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 246                 goto err_out;
 247         }
 248
 249         /* VNIC configuration */
 250         for (i = 0; i < bp->nr_vnics; i++) {
 251                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 252                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 253                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 254
 255                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 256                 if (!vnic->fw_grp_ids) {
 257                         PMD_DRV_LOG(ERR,
 258                                     "Failed to alloc %d bytes for group ids\n",
 259                                     size);
 260                         rc = -ENOMEM;
 261                         goto err_out;
 262                 }
 263                 memset(vnic->fw_grp_ids, -1, size);
 264
 265                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 266                             i, vnic, vnic->fw_grp_ids);
 267
 268                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 269                 if (rc) {
 270                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 271                                 i, rc);
 272                         goto err_out;
 273                 }
 274
 275                 /* Alloc RSS context only if RSS mode is enabled */
 276                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 277                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
 278                         if (rc) {
 279                                 PMD_DRV_LOG(ERR,
 280                                         "HWRM vnic %d ctx alloc failure rc: %x\n",
 281                                         i, rc);
 282                                 goto err_out;
 283                         }
 284                 }
 285
 286                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 287                 if (rc) {
 288                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 289                                 i, rc);
 290                         goto err_out;
 291                 }
 292
 293                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 294                 if (rc) {
 295                         PMD_DRV_LOG(ERR,
 296                                 "HWRM vnic %d filter failure rc: %x\n",
 297                                 i, rc);
 298                         goto err_out;
 299                 }
 300
 301                 for (j = 0; j < bp->rx_nr_rings; j++) {
 302                         rxq = bp->eth_dev->data->rx_queues[j];
 303
 304                         PMD_DRV_LOG(DEBUG,
 305                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 306                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 307
 308                         if (rxq->rx_deferred_start)
 309                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 310                 }
 311
 312                 rc = bnxt_vnic_rss_configure(bp, vnic);
 313                 if (rc) {
 314                         PMD_DRV_LOG(ERR,
 315                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 316                         goto err_out;
 317                 }
 318
 319                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 320
 321                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 322                     DEV_RX_OFFLOAD_TCP_LRO)
 323                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 324                 else
 325                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 326         }
 327         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 328         if (rc) {
 329                 PMD_DRV_LOG(ERR,
 330                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 331                 goto err_out;
 332         }
 333
 334         /* check and configure queue intr-vector mapping */
 335         if ((rte_intr_cap_multiple(intr_handle) ||
 336              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 337             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 338                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 339                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 340                 if (intr_vector > bp->rx_cp_nr_rings) {
 341                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 342                                         bp->rx_cp_nr_rings);
 343                         return -ENOTSUP;
 344                 }
 345                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 346                         return -1;
 347         }
 348
 349         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 350                 intr_handle->intr_vec =
 351                         rte_zmalloc("intr_vec",
 352                                     bp->eth_dev->data->nb_rx_queues *
 353                                     sizeof(int), 0);
 354                 if (intr_handle->intr_vec == NULL) {
 355                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 356                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 357                         return -ENOMEM;
 358                 }
 359                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 360                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 361                          intr_handle->intr_vec, intr_handle->nb_efd,
 362                         intr_handle->max_intr);
 363         }
 364
 365         for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 366              queue_id++) {
 367                 intr_handle->intr_vec[queue_id] = vec;
 368                 if (vec < base + intr_handle->nb_efd - 1)
 369                         vec++;
 370         }
 371
 372         /* enable uio/vfio intr/eventfd mapping */
 373         rte_intr_enable(intr_handle);
 374
 375         rc = bnxt_get_hwrm_link_config(bp, &new);
 376         if (rc) {
 377                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 378                 goto err_out;
 379         }
 380
 381         if (!bp->link_info.link_up) {
 382                 rc = bnxt_set_hwrm_link_config(bp, true);
 383                 if (rc) {
 384                         PMD_DRV_LOG(ERR,
 385                                 "HWRM link config failure rc: %x\n", rc);
 386                         goto err_out;
 387                 }
 388         }
 389         bnxt_print_link_info(bp->eth_dev);
 390
 391         return 0;
 392
 393 err_out:
 394         bnxt_free_all_hwrm_resources(bp);
 395
 396         /* Some of the error status returned by FW may not be from errno.h */
 397         if (rc > 0)
 398                 rc = -EIO;
 399
 400         return rc;
 401 }
 402
 403 static int bnxt_shutdown_nic(struct bnxt *bp)
 404 {
 405         bnxt_free_all_hwrm_resources(bp);
 406         bnxt_free_all_filters(bp);
 407         bnxt_free_all_vnics(bp);
 408         return 0;
 409 }
 410
 411 static int bnxt_init_nic(struct bnxt *bp)
 412 {
 413         int rc;
 414
 415         rc = bnxt_init_ring_grps(bp);
 416         if (rc)
 417                 return rc;
 418
 419         bnxt_init_vnics(bp);
 420         bnxt_init_filters(bp);
 421
 422         return 0;
 423 }
 424
 425 /*
 426  * Device configuration and status function
 427  */
 428
 429 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 430                                   struct rte_eth_dev_info *dev_info)
 431 {
 432         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 433         uint16_t max_vnics, i, j, vpool, vrxq;
 434         unsigned int max_rx_rings;
 435
 436         /* MAC Specifics */
 437         dev_info->max_mac_addrs = bp->max_l2_ctx;
 438         dev_info->max_hash_mac_addrs = 0;
 439
 440         /* PF/VF specifics */
 441         if (BNXT_PF(bp))
 442                 dev_info->max_vfs = bp->pdev->max_vfs;
 443         max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx);
 444         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 445         dev_info->max_rx_queues = max_rx_rings;
 446         dev_info->max_tx_queues = max_rx_rings;
 447         dev_info->reta_size = HW_HASH_INDEX_SIZE;
 448         dev_info->hash_key_size = 40;
 449         max_vnics = bp->max_vnics;
 450
 451         /* Fast path specifics */
 452         dev_info->min_rx_bufsize = 1;
 453         dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
 454                                   + VLAN_TAG_SIZE * 2;
 455
 456         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 457         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 458                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 459         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 460         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 461
 462         /* *INDENT-OFF* */
 463         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 464                 .rx_thresh = {
 465                         .pthresh = 8,
 466                         .hthresh = 8,
 467                         .wthresh = 0,
 468                 },
 469                 .rx_free_thresh = 32,
 470                 /* If no descriptors available, pkts are dropped by default */
 471                 .rx_drop_en = 1,
 472         };
 473
 474         dev_info->default_txconf = (struct rte_eth_txconf) {
 475                 .tx_thresh = {
 476                         .pthresh = 32,
 477                         .hthresh = 0,
 478                         .wthresh = 0,
 479                 },
 480                 .tx_free_thresh = 32,
 481                 .tx_rs_thresh = 32,
 482         };
 483         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 484
 485         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 486         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 487         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 488         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 489         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 490
 491         /* *INDENT-ON* */
 492
 493         /*
 494          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 495          *       need further investigation.
 496          */
 497
 498         /* VMDq resources */
 499         vpool = 64; /* ETH_64_POOLS */
 500         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 501         for (i = 0; i < 4; vpool >>= 1, i++) {
 502                 if (max_vnics > vpool) {
 503                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 504                                 if (dev_info->max_rx_queues > vrxq) {
 505                                         if (vpool > vrxq)
 506                                                 vpool = vrxq;
 507                                         goto found;
 508                                 }
 509                         }
 510                         /* Not enough resources to support VMDq */
 511                         break;
 512                 }
 513         }
 514         /* Not enough resources to support VMDq */
 515         vpool = 0;
 516         vrxq = 0;
 517 found:
 518         dev_info->max_vmdq_pools = vpool;
 519         dev_info->vmdq_queue_num = vrxq;
 520
 521         dev_info->vmdq_pool_base = 0;
 522         dev_info->vmdq_queue_base = 0;
 523 }
 524
 525 /* Configure the device based on the configuration provided */
 526 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 527 {
 528         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 529         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 530         int rc;
 531
 532         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 533         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 534         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 535         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 536
 537         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 538                 rc = bnxt_hwrm_check_vf_rings(bp);
 539                 if (rc) {
 540                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 541                         return -ENOSPC;
 542                 }
 543
 544                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 545                 if (rc) {
 546                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 547                         return -ENOSPC;
 548                 }
 549         } else {
 550                 /* legacy driver needs to get updated values */
 551                 rc = bnxt_hwrm_func_qcaps(bp);
 552                 if (rc) {
 553                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 554                         return rc;
 555                 }
 556         }
 557
 558         /* Inherit new configurations */
 559         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 560             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 561             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 562             bp->max_cp_rings ||
 563             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 564             bp->max_stat_ctx ||
 565             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps ||
 566             (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 567              bp->max_vnics < eth_dev->data->nb_rx_queues)) {
 568                 PMD_DRV_LOG(ERR,
 569                         "Insufficient resources to support requested config\n");
 570                 PMD_DRV_LOG(ERR,
 571                         "Num Queues Requested: Tx %d, Rx %d\n",
 572                         eth_dev->data->nb_tx_queues,
 573                         eth_dev->data->nb_rx_queues);
 574                 PMD_DRV_LOG(ERR,
 575                         "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 576                         bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 577                         bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 578                 return -ENOSPC;
 579         }
 580
 581         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 582         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 583
 584         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 585                 eth_dev->data->mtu =
 586                                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 587                                 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE *
 588                                 BNXT_NUM_VLANS;
 589                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 590         }
 591         return 0;
 592 }
 593
 594 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 595 {
 596         struct rte_eth_link *link = &eth_dev->data->dev_link;
 597
 598         if (link->link_status)
 599                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 600                         eth_dev->data->port_id,
 601                         (uint32_t)link->link_speed,
 602                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 603                         ("full-duplex") : ("half-duplex\n"));
 604         else
 605                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 606                         eth_dev->data->port_id);
 607 }
 608
 609 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
 610 {
 611         bnxt_print_link_info(eth_dev);
 612         return 0;
 613 }
 614
 615 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 616 {
 617         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 618         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 619         int vlan_mask = 0;
 620         int rc;
 621
 622         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 623                 PMD_DRV_LOG(ERR,
 624                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 625                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 626         }
 627         bp->dev_stopped = 0;
 628
 629         rc = bnxt_init_chip(bp);
 630         if (rc)
 631                 goto error;
 632
 633         bnxt_link_update_op(eth_dev, 1);
 634
 635         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 636                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 637         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 638                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 639         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 640         if (rc)
 641                 goto error;
 642
 643         bp->flags |= BNXT_FLAG_INIT_DONE;
 644         return 0;
 645
 646 error:
 647         bnxt_shutdown_nic(bp);
 648         bnxt_free_tx_mbufs(bp);
 649         bnxt_free_rx_mbufs(bp);
 650         return rc;
 651 }
 652
 653 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 654 {
 655         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 656         int rc = 0;
 657
 658         if (!bp->link_info.link_up)
 659                 rc = bnxt_set_hwrm_link_config(bp, true);
 660         if (!rc)
 661                 eth_dev->data->dev_link.link_status = 1;
 662
 663         bnxt_print_link_info(eth_dev);
 664         return 0;
 665 }
 666
 667 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 668 {
 669         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 670
 671         eth_dev->data->dev_link.link_status = 0;
 672         bnxt_set_hwrm_link_config(bp, false);
 673         bp->link_info.link_up = 0;
 674
 675         return 0;
 676 }
 677
 678 /* Unload the driver, release resources */
 679 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 680 {
 681         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 682
 683         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 684         if (bp->eth_dev->data->dev_started) {
 685                 /* TBD: STOP HW queues DMA */
 686                 eth_dev->data->dev_link.link_status = 0;
 687         }
 688         bnxt_set_hwrm_link_config(bp, false);
 689         bnxt_hwrm_port_clr_stats(bp);
 690         bnxt_free_tx_mbufs(bp);
 691         bnxt_free_rx_mbufs(bp);
 692         bnxt_shutdown_nic(bp);
 693         bp->dev_stopped = 1;
 694 }
 695
 696 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 697 {
 698         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 699
 700         if (bp->dev_stopped == 0)
 701                 bnxt_dev_stop_op(eth_dev);
 702
 703         if (eth_dev->data->mac_addrs != NULL) {
 704                 rte_free(eth_dev->data->mac_addrs);
 705                 eth_dev->data->mac_addrs = NULL;
 706         }
 707         if (bp->grp_info != NULL) {
 708                 rte_free(bp->grp_info);
 709                 bp->grp_info = NULL;
 710         }
 711
 712         bnxt_dev_uninit(eth_dev);
 713 }
 714
 715 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 716                                     uint32_t index)
 717 {
 718         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 719         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 720         struct bnxt_vnic_info *vnic;
 721         struct bnxt_filter_info *filter, *temp_filter;
 722         uint32_t i;
 723
 724         /*
 725          * Loop through all VNICs from the specified filter flow pools to
 726          * remove the corresponding MAC addr filter
 727          */
 728         for (i = 0; i < bp->nr_vnics; i++) {
 729                 if (!(pool_mask & (1ULL << i)))
 730                         continue;
 731
 732                 vnic = &bp->vnic_info[i];
 733                 filter = STAILQ_FIRST(&vnic->filter);
 734                 while (filter) {
 735                         temp_filter = STAILQ_NEXT(filter, next);
 736                         if (filter->mac_index == index) {
 737                                 STAILQ_REMOVE(&vnic->filter, filter,
 738                                                 bnxt_filter_info, next);
 739                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 740                                 filter->mac_index = INVALID_MAC_INDEX;
 741                                 memset(&filter->l2_addr, 0, ETHER_ADDR_LEN);
 742                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 743                                                    filter, next);
 744                         }
 745                         filter = temp_filter;
 746                 }
 747         }
 748 }
 749
 750 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 751                                 struct ether_addr *mac_addr,
 752                                 uint32_t index, uint32_t pool)
 753 {
 754         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 755         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
 756         struct bnxt_filter_info *filter;
 757
 758         if (BNXT_VF(bp)) {
 759                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
 760                 return -ENOTSUP;
 761         }
 762
 763         if (!vnic) {
 764                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
 765                 return -EINVAL;
 766         }
 767         /* Attach requested MAC address to the new l2_filter */
 768         STAILQ_FOREACH(filter, &vnic->filter, next) {
 769                 if (filter->mac_index == index) {
 770                         PMD_DRV_LOG(ERR,
 771                                 "MAC addr already existed for pool %d\n", pool);
 772                         return 0;
 773                 }
 774         }
 775         filter = bnxt_alloc_filter(bp);
 776         if (!filter) {
 777                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
 778                 return -ENODEV;
 779         }
 780         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 781         filter->mac_index = index;
 782         memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
 783         return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 784 }
 785
 786 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 787 {
 788         int rc = 0;
 789         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 790         struct rte_eth_link new;
 791         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 792
 793         memset(&new, 0, sizeof(new));
 794         do {
 795                 /* Retrieve link info from hardware */
 796                 rc = bnxt_get_hwrm_link_config(bp, &new);
 797                 if (rc) {
 798                         new.link_speed = ETH_LINK_SPEED_100M;
 799                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 800                         PMD_DRV_LOG(ERR,
 801                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 802                         goto out;
 803                 }
 804                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 805
 806                 if (!wait_to_complete)
 807                         break;
 808         } while (!new.link_status && cnt--);
 809
 810 out:
 811         /* Timed out or success */
 812         if (new.link_status != eth_dev->data->dev_link.link_status ||
 813         new.link_speed != eth_dev->data->dev_link.link_speed) {
 814                 memcpy(&eth_dev->data->dev_link, &new,
 815                         sizeof(struct rte_eth_link));
 816
 817                 _rte_eth_dev_callback_process(eth_dev,
 818                                               RTE_ETH_EVENT_INTR_LSC,
 819                                               NULL);
 820
 821                 bnxt_print_link_info(eth_dev);
 822         }
 823
 824         return rc;
 825 }
 826
 827 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
 828 {
 829         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 830         struct bnxt_vnic_info *vnic;
 831
 832         if (bp->vnic_info == NULL)
 833                 return;
 834
 835         vnic = &bp->vnic_info[0];
 836
 837         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
 838         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 839 }
 840
 841 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
 842 {
 843         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 844         struct bnxt_vnic_info *vnic;
 845
 846         if (bp->vnic_info == NULL)
 847                 return;
 848
 849         vnic = &bp->vnic_info[0];
 850
 851         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
 852         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 853 }
 854
 855 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
 856 {
 857         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 858         struct bnxt_vnic_info *vnic;
 859
 860         if (bp->vnic_info == NULL)
 861                 return;
 862
 863         vnic = &bp->vnic_info[0];
 864
 865         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
 866         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 867 }
 868
 869 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
 870 {
 871         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 872         struct bnxt_vnic_info *vnic;
 873
 874         if (bp->vnic_info == NULL)
 875                 return;
 876
 877         vnic = &bp->vnic_info[0];
 878
 879         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
 880         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 881 }
 882
 883 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
 884                             struct rte_eth_rss_reta_entry64 *reta_conf,
 885                             uint16_t reta_size)
 886 {
 887         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 888         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 889         struct bnxt_vnic_info *vnic;
 890         int i;
 891
 892         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
 893                 return -EINVAL;
 894
 895         if (reta_size != HW_HASH_INDEX_SIZE) {
 896                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
 897                         "(%d) must equal the size supported by the hardware "
 898                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 899                 return -EINVAL;
 900         }
 901         /* Update the RSS VNIC(s) */
 902         for (i = 0; i < bp->max_vnics; i++) {
 903                 vnic = &bp->vnic_info[i];
 904                 memcpy(vnic->rss_table, reta_conf, reta_size);
 905                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 906         }
 907         return 0;
 908 }
 909
 910 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
 911                               struct rte_eth_rss_reta_entry64 *reta_conf,
 912                               uint16_t reta_size)
 913 {
 914         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 915         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 916         struct rte_intr_handle *intr_handle
 917                 = &bp->pdev->intr_handle;
 918
 919         /* Retrieve from the default VNIC */
 920         if (!vnic)
 921                 return -EINVAL;
 922         if (!vnic->rss_table)
 923                 return -EINVAL;
 924
 925         if (reta_size != HW_HASH_INDEX_SIZE) {
 926                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
 927                         "(%d) must equal the size supported by the hardware "
 928                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 929                 return -EINVAL;
 930         }
 931         /* EW - need to revisit here copying from uint64_t to uint16_t */
 932         memcpy(reta_conf, vnic->rss_table, reta_size);
 933
 934         if (rte_intr_allow_others(intr_handle)) {
 935                 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
 936                         bnxt_dev_lsc_intr_setup(eth_dev);
 937         }
 938
 939         return 0;
 940 }
 941
 942 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
 943                                    struct rte_eth_rss_conf *rss_conf)
 944 {
 945         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 946         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 947         struct bnxt_vnic_info *vnic;
 948         uint16_t hash_type = 0;
 949         unsigned int i;
 950
 951         /*
 952          * If RSS enablement were different than dev_configure,
 953          * then return -EINVAL
 954          */
 955         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
 956                 if (!rss_conf->rss_hf)
 957                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
 958         } else {
 959                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
 960                         return -EINVAL;
 961         }
 962
 963         bp->flags |= BNXT_FLAG_UPDATE_HASH;
 964         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
 965
 966         if (rss_conf->rss_hf & ETH_RSS_IPV4)
 967                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 968         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
 969                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 970         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
 971                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
 972         if (rss_conf->rss_hf & ETH_RSS_IPV6)
 973                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
 974         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
 975                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
 976         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
 977                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
 978
 979         /* Update the RSS VNIC(s) */
 980         for (i = 0; i < bp->nr_vnics; i++) {
 981                 vnic = &bp->vnic_info[i];
 982                 vnic->hash_type = hash_type;
 983
 984                 /*
 985                  * Use the supplied key if the key length is
 986                  * acceptable and the rss_key is not NULL
 987                  */
 988                 if (rss_conf->rss_key &&
 989                     rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
 990                         memcpy(vnic->rss_hash_key, rss_conf->rss_key,
 991                                rss_conf->rss_key_len);
 992
 993                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 994         }
 995         return 0;
 996 }
 997
 998 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
 999                                      struct rte_eth_rss_conf *rss_conf)
1000 {
1001         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1002         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1003         int len;
1004         uint32_t hash_types;
1005
1006         /* RSS configuration is the same for all VNICs */
1007         if (vnic && vnic->rss_hash_key) {
1008                 if (rss_conf->rss_key) {
1009                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1010                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1011                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1012                 }
1013
1014                 hash_types = vnic->hash_type;
1015                 rss_conf->rss_hf = 0;
1016                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1017                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1018                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1019                 }
1020                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1021                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1022                         hash_types &=
1023                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1024                 }
1025                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1026                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1027                         hash_types &=
1028                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1029                 }
1030                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1031                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1032                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1033                 }
1034                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1035                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1036                         hash_types &=
1037                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1038                 }
1039                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1040                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1041                         hash_types &=
1042                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1043                 }
1044                 if (hash_types) {
1045                         PMD_DRV_LOG(ERR,
1046                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1047                                 vnic->hash_type);
1048                         return -ENOTSUP;
1049                 }
1050         } else {
1051                 rss_conf->rss_hf = 0;
1052         }
1053         return 0;
1054 }
1055
1056 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1057                                struct rte_eth_fc_conf *fc_conf)
1058 {
1059         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1060         struct rte_eth_link link_info;
1061         int rc;
1062
1063         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1064         if (rc)
1065                 return rc;
1066
1067         memset(fc_conf, 0, sizeof(*fc_conf));
1068         if (bp->link_info.auto_pause)
1069                 fc_conf->autoneg = 1;
1070         switch (bp->link_info.pause) {
1071         case 0:
1072                 fc_conf->mode = RTE_FC_NONE;
1073                 break;
1074         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1075                 fc_conf->mode = RTE_FC_TX_PAUSE;
1076                 break;
1077         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1078                 fc_conf->mode = RTE_FC_RX_PAUSE;
1079                 break;
1080         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1081                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1082                 fc_conf->mode = RTE_FC_FULL;
1083                 break;
1084         }
1085         return 0;
1086 }
1087
1088 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1089                                struct rte_eth_fc_conf *fc_conf)
1090 {
1091         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1092
1093         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1094                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1095                 return -ENOTSUP;
1096         }
1097
1098         switch (fc_conf->mode) {
1099         case RTE_FC_NONE:
1100                 bp->link_info.auto_pause = 0;
1101                 bp->link_info.force_pause = 0;
1102                 break;
1103         case RTE_FC_RX_PAUSE:
1104                 if (fc_conf->autoneg) {
1105                         bp->link_info.auto_pause =
1106                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1107                         bp->link_info.force_pause = 0;
1108                 } else {
1109                         bp->link_info.auto_pause = 0;
1110                         bp->link_info.force_pause =
1111                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1112                 }
1113                 break;
1114         case RTE_FC_TX_PAUSE:
1115                 if (fc_conf->autoneg) {
1116                         bp->link_info.auto_pause =
1117                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1118                         bp->link_info.force_pause = 0;
1119                 } else {
1120                         bp->link_info.auto_pause = 0;
1121                         bp->link_info.force_pause =
1122                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1123                 }
1124                 break;
1125         case RTE_FC_FULL:
1126                 if (fc_conf->autoneg) {
1127                         bp->link_info.auto_pause =
1128                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1129                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1130                         bp->link_info.force_pause = 0;
1131                 } else {
1132                         bp->link_info.auto_pause = 0;
1133                         bp->link_info.force_pause =
1134                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1135                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1136                 }
1137                 break;
1138         }
1139         return bnxt_set_hwrm_link_config(bp, true);
1140 }
1141
1142 /* Add UDP tunneling port */
1143 static int
1144 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1145                          struct rte_eth_udp_tunnel *udp_tunnel)
1146 {
1147         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1148         uint16_t tunnel_type = 0;
1149         int rc = 0;
1150
1151         switch (udp_tunnel->prot_type) {
1152         case RTE_TUNNEL_TYPE_VXLAN:
1153                 if (bp->vxlan_port_cnt) {
1154                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1155                                 udp_tunnel->udp_port);
1156                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1157                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1158                                 return -ENOSPC;
1159                         }
1160                         bp->vxlan_port_cnt++;
1161                         return 0;
1162                 }
1163                 tunnel_type =
1164                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1165                 bp->vxlan_port_cnt++;
1166                 break;
1167         case RTE_TUNNEL_TYPE_GENEVE:
1168                 if (bp->geneve_port_cnt) {
1169                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1170                                 udp_tunnel->udp_port);
1171                         if (bp->geneve_port != udp_tunnel->udp_port) {
1172                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1173                                 return -ENOSPC;
1174                         }
1175                         bp->geneve_port_cnt++;
1176                         return 0;
1177                 }
1178                 tunnel_type =
1179                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1180                 bp->geneve_port_cnt++;
1181                 break;
1182         default:
1183                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1184                 return -ENOTSUP;
1185         }
1186         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1187                                              tunnel_type);
1188         return rc;
1189 }
1190
1191 static int
1192 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1193                          struct rte_eth_udp_tunnel *udp_tunnel)
1194 {
1195         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1196         uint16_t tunnel_type = 0;
1197         uint16_t port = 0;
1198         int rc = 0;
1199
1200         switch (udp_tunnel->prot_type) {
1201         case RTE_TUNNEL_TYPE_VXLAN:
1202                 if (!bp->vxlan_port_cnt) {
1203                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1204                         return -EINVAL;
1205                 }
1206                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1207                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1208                                 udp_tunnel->udp_port, bp->vxlan_port);
1209                         return -EINVAL;
1210                 }
1211                 if (--bp->vxlan_port_cnt)
1212                         return 0;
1213
1214                 tunnel_type =
1215                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1216                 port = bp->vxlan_fw_dst_port_id;
1217                 break;
1218         case RTE_TUNNEL_TYPE_GENEVE:
1219                 if (!bp->geneve_port_cnt) {
1220                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1221                         return -EINVAL;
1222                 }
1223                 if (bp->geneve_port != udp_tunnel->udp_port) {
1224                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1225                                 udp_tunnel->udp_port, bp->geneve_port);
1226                         return -EINVAL;
1227                 }
1228                 if (--bp->geneve_port_cnt)
1229                         return 0;
1230
1231                 tunnel_type =
1232                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1233                 port = bp->geneve_fw_dst_port_id;
1234                 break;
1235         default:
1236                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1237                 return -ENOTSUP;
1238         }
1239
1240         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1241         if (!rc) {
1242                 if (tunnel_type ==
1243                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1244                         bp->vxlan_port = 0;
1245                 if (tunnel_type ==
1246                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1247                         bp->geneve_port = 0;
1248         }
1249         return rc;
1250 }
1251
1252 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1253 {
1254         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1255         struct bnxt_vnic_info *vnic;
1256         unsigned int i;
1257         int rc = 0;
1258         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1259
1260         /* Cycle through all VNICs */
1261         for (i = 0; i < bp->nr_vnics; i++) {
1262                 /*
1263                  * For each VNIC and each associated filter(s)
1264                  * if VLAN exists && VLAN matches vlan_id
1265                  *      remove the MAC+VLAN filter
1266                  *      add a new MAC only filter
1267                  * else
1268                  *      VLAN filter doesn't exist, just skip and continue
1269                  */
1270                 vnic = &bp->vnic_info[i];
1271                 filter = STAILQ_FIRST(&vnic->filter);
1272                 while (filter) {
1273                         temp_filter = STAILQ_NEXT(filter, next);
1274
1275                         if (filter->enables & chk &&
1276                             filter->l2_ovlan == vlan_id) {
1277                                 /* Must delete the filter */
1278                                 STAILQ_REMOVE(&vnic->filter, filter,
1279                                               bnxt_filter_info, next);
1280                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1281                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1282                                                    filter, next);
1283
1284                                 /*
1285                                  * Need to examine to see if the MAC
1286                                  * filter already existed or not before
1287                                  * allocating a new one
1288                                  */
1289
1290                                 new_filter = bnxt_alloc_filter(bp);
1291                                 if (!new_filter) {
1292                                         PMD_DRV_LOG(ERR,
1293                                                         "MAC/VLAN filter alloc failed\n");
1294                                         rc = -ENOMEM;
1295                                         goto exit;
1296                                 }
1297                                 STAILQ_INSERT_TAIL(&vnic->filter,
1298                                                 new_filter, next);
1299                                 /* Inherit MAC from previous filter */
1300                                 new_filter->mac_index =
1301                                         filter->mac_index;
1302                                 memcpy(new_filter->l2_addr, filter->l2_addr,
1303                                        ETHER_ADDR_LEN);
1304                                 /* MAC only filter */
1305                                 rc = bnxt_hwrm_set_l2_filter(bp,
1306                                                              vnic->fw_vnic_id,
1307                                                              new_filter);
1308                                 if (rc)
1309                                         goto exit;
1310                                 PMD_DRV_LOG(INFO,
1311                                             "Del Vlan filter for %d\n",
1312                                             vlan_id);
1313                         }
1314                         filter = temp_filter;
1315                 }
1316         }
1317 exit:
1318         return rc;
1319 }
1320
1321 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1322 {
1323         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1324         struct bnxt_vnic_info *vnic;
1325         unsigned int i;
1326         int rc = 0;
1327         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1328                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1329         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1330
1331         /* Cycle through all VNICs */
1332         for (i = 0; i < bp->nr_vnics; i++) {
1333                 /*
1334                  * For each VNIC and each associated filter(s)
1335                  * if VLAN exists:
1336                  *   if VLAN matches vlan_id
1337                  *      VLAN filter already exists, just skip and continue
1338                  *   else
1339                  *      add a new MAC+VLAN filter
1340                  * else
1341                  *   Remove the old MAC only filter
1342                  *    Add a new MAC+VLAN filter
1343                  */
1344                 vnic = &bp->vnic_info[i];
1345                 filter = STAILQ_FIRST(&vnic->filter);
1346                 while (filter) {
1347                         temp_filter = STAILQ_NEXT(filter, next);
1348
1349                         if (filter->enables & chk) {
1350                                 if (filter->l2_ivlan == vlan_id)
1351                                         goto cont;
1352                         } else {
1353                                 /* Must delete the MAC filter */
1354                                 STAILQ_REMOVE(&vnic->filter, filter,
1355                                                 bnxt_filter_info, next);
1356                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1357                                 filter->l2_ovlan = 0;
1358                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1359                                                    filter, next);
1360                         }
1361                         new_filter = bnxt_alloc_filter(bp);
1362                         if (!new_filter) {
1363                                 PMD_DRV_LOG(ERR,
1364                                                 "MAC/VLAN filter alloc failed\n");
1365                                 rc = -ENOMEM;
1366                                 goto exit;
1367                         }
1368                         STAILQ_INSERT_TAIL(&vnic->filter, new_filter, next);
1369                         /* Inherit MAC from the previous filter */
1370                         new_filter->mac_index = filter->mac_index;
1371                         memcpy(new_filter->l2_addr, filter->l2_addr,
1372                                ETHER_ADDR_LEN);
1373                         /* MAC + VLAN ID filter */
1374                         new_filter->l2_ivlan = vlan_id;
1375                         new_filter->l2_ivlan_mask = 0xF000;
1376                         new_filter->enables |= en;
1377                         rc = bnxt_hwrm_set_l2_filter(bp,
1378                                         vnic->fw_vnic_id,
1379                                         new_filter);
1380                         if (rc)
1381                                 goto exit;
1382                         PMD_DRV_LOG(INFO,
1383                                     "Added Vlan filter for %d\n", vlan_id);
1384 cont:
1385                         filter = temp_filter;
1386                 }
1387         }
1388 exit:
1389         return rc;
1390 }
1391
1392 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1393                 uint16_t vlan_id, int on)
1394 {
1395         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1396
1397         /* These operations apply to ALL existing MAC/VLAN filters */
1398         if (on)
1399                 return bnxt_add_vlan_filter(bp, vlan_id);
1400         else
1401                 return bnxt_del_vlan_filter(bp, vlan_id);
1402 }
1403
1404 static int
1405 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1406 {
1407         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1408         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1409         unsigned int i;
1410
1411         if (mask & ETH_VLAN_FILTER_MASK) {
1412                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1413                         /* Remove any VLAN filters programmed */
1414                         for (i = 0; i < 4095; i++)
1415                                 bnxt_del_vlan_filter(bp, i);
1416                 }
1417                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1418                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1419         }
1420
1421         if (mask & ETH_VLAN_STRIP_MASK) {
1422                 /* Enable or disable VLAN stripping */
1423                 for (i = 0; i < bp->nr_vnics; i++) {
1424                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1425                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1426                                 vnic->vlan_strip = true;
1427                         else
1428                                 vnic->vlan_strip = false;
1429                         bnxt_hwrm_vnic_cfg(bp, vnic);
1430                 }
1431                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1432                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1433         }
1434
1435         if (mask & ETH_VLAN_EXTEND_MASK)
1436                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1437
1438         return 0;
1439 }
1440
1441 static int
1442 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1443 {
1444         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1445         /* Default Filter is tied to VNIC 0 */
1446         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1447         struct bnxt_filter_info *filter;
1448         int rc;
1449
1450         if (BNXT_VF(bp))
1451                 return -EPERM;
1452
1453         memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1454
1455         STAILQ_FOREACH(filter, &vnic->filter, next) {
1456                 /* Default Filter is at Index 0 */
1457                 if (filter->mac_index != 0)
1458                         continue;
1459                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1460                 if (rc)
1461                         return rc;
1462                 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1463                 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1464                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1465                 filter->enables |=
1466                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1467                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1468                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1469                 if (rc)
1470                         return rc;
1471                 filter->mac_index = 0;
1472                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1473         }
1474
1475         return 0;
1476 }
1477
1478 static int
1479 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1480                           struct ether_addr *mc_addr_set,
1481                           uint32_t nb_mc_addr)
1482 {
1483         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1484         char *mc_addr_list = (char *)mc_addr_set;
1485         struct bnxt_vnic_info *vnic;
1486         uint32_t off = 0, i = 0;
1487
1488         vnic = &bp->vnic_info[0];
1489
1490         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1491                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1492                 goto allmulti;
1493         }
1494
1495         /* TODO Check for Duplicate mcast addresses */
1496         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1497         for (i = 0; i < nb_mc_addr; i++) {
1498                 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1499                 off += ETHER_ADDR_LEN;
1500         }
1501
1502         vnic->mc_addr_cnt = i;
1503
1504 allmulti:
1505         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1506 }
1507
1508 static int
1509 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1510 {
1511         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1512         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1513         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1514         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1515         int ret;
1516
1517         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1518                         fw_major, fw_minor, fw_updt);
1519
1520         ret += 1; /* add the size of '\0' */
1521         if (fw_size < (uint32_t)ret)
1522                 return ret;
1523         else
1524                 return 0;
1525 }
1526
1527 static void
1528 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1529         struct rte_eth_rxq_info *qinfo)
1530 {
1531         struct bnxt_rx_queue *rxq;
1532
1533         rxq = dev->data->rx_queues[queue_id];
1534
1535         qinfo->mp = rxq->mb_pool;
1536         qinfo->scattered_rx = dev->data->scattered_rx;
1537         qinfo->nb_desc = rxq->nb_rx_desc;
1538
1539         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1540         qinfo->conf.rx_drop_en = 0;
1541         qinfo->conf.rx_deferred_start = 0;
1542 }
1543
1544 static void
1545 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1546         struct rte_eth_txq_info *qinfo)
1547 {
1548         struct bnxt_tx_queue *txq;
1549
1550         txq = dev->data->tx_queues[queue_id];
1551
1552         qinfo->nb_desc = txq->nb_tx_desc;
1553
1554         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1555         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1556         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1557
1558         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1559         qinfo->conf.tx_rs_thresh = 0;
1560         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1561 }
1562
1563 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1564 {
1565         struct bnxt *bp = eth_dev->data->dev_private;
1566         struct rte_eth_dev_info dev_info;
1567         uint32_t rc = 0;
1568         uint32_t i;
1569
1570         bnxt_dev_info_get_op(eth_dev, &dev_info);
1571
1572         if (new_mtu < ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1573                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1574                         ETHER_MIN_MTU, BNXT_MAX_MTU);
1575                 return -EINVAL;
1576         }
1577
1578         if (new_mtu > ETHER_MTU) {
1579                 bp->flags |= BNXT_FLAG_JUMBO;
1580                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1581                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1582         } else {
1583                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1584                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1585                 bp->flags &= ~BNXT_FLAG_JUMBO;
1586         }
1587
1588         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1589                 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1590
1591         eth_dev->data->mtu = new_mtu;
1592         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1593
1594         for (i = 0; i < bp->nr_vnics; i++) {
1595                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1596                 uint16_t size = 0;
1597
1598                 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1599                                         ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1600                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1601                 if (rc)
1602                         break;
1603
1604                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1605                 size -= RTE_PKTMBUF_HEADROOM;
1606
1607                 if (size < new_mtu) {
1608                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1609                         if (rc)
1610                                 return rc;
1611                 }
1612         }
1613
1614         return rc;
1615 }
1616
1617 static int
1618 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1619 {
1620         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1621         uint16_t vlan = bp->vlan;
1622         int rc;
1623
1624         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1625                 PMD_DRV_LOG(ERR,
1626                         "PVID cannot be modified for this function\n");
1627                 return -ENOTSUP;
1628         }
1629         bp->vlan = on ? pvid : 0;
1630
1631         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1632         if (rc)
1633                 bp->vlan = vlan;
1634         return rc;
1635 }
1636
1637 static int
1638 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1639 {
1640         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1641
1642         return bnxt_hwrm_port_led_cfg(bp, true);
1643 }
1644
1645 static int
1646 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1647 {
1648         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1649
1650         return bnxt_hwrm_port_led_cfg(bp, false);
1651 }
1652
1653 static uint32_t
1654 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1655 {
1656         uint32_t desc = 0, raw_cons = 0, cons;
1657         struct bnxt_cp_ring_info *cpr;
1658         struct bnxt_rx_queue *rxq;
1659         struct rx_pkt_cmpl *rxcmp;
1660         uint16_t cmp_type;
1661         uint8_t cmp = 1;
1662         bool valid;
1663
1664         rxq = dev->data->rx_queues[rx_queue_id];
1665         cpr = rxq->cp_ring;
1666         valid = cpr->valid;
1667
1668         while (raw_cons < rxq->nb_rx_desc) {
1669                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1670                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1671
1672                 if (!CMPL_VALID(rxcmp, valid))
1673                         goto nothing_to_do;
1674                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1675                 cmp_type = CMP_TYPE(rxcmp);
1676                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1677                         cmp = (rte_le_to_cpu_32(
1678                                         ((struct rx_tpa_end_cmpl *)
1679                                          (rxcmp))->agg_bufs_v1) &
1680                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1681                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1682                         desc++;
1683                 } else if (cmp_type == 0x11) {
1684                         desc++;
1685                         cmp = (rxcmp->agg_bufs_v1 &
1686                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1687                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1688                 } else {
1689                         cmp = 1;
1690                 }
1691 nothing_to_do:
1692                 raw_cons += cmp ? cmp : 2;
1693         }
1694
1695         return desc;
1696 }
1697
1698 static int
1699 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1700 {
1701         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1702         struct bnxt_rx_ring_info *rxr;
1703         struct bnxt_cp_ring_info *cpr;
1704         struct bnxt_sw_rx_bd *rx_buf;
1705         struct rx_pkt_cmpl *rxcmp;
1706         uint32_t cons, cp_cons;
1707
1708         if (!rxq)
1709                 return -EINVAL;
1710
1711         cpr = rxq->cp_ring;
1712         rxr = rxq->rx_ring;
1713
1714         if (offset >= rxq->nb_rx_desc)
1715                 return -EINVAL;
1716
1717         cons = RING_CMP(cpr->cp_ring_struct, offset);
1718         cp_cons = cpr->cp_raw_cons;
1719         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1720
1721         if (cons > cp_cons) {
1722                 if (CMPL_VALID(rxcmp, cpr->valid))
1723                         return RTE_ETH_RX_DESC_DONE;
1724         } else {
1725                 if (CMPL_VALID(rxcmp, !cpr->valid))
1726                         return RTE_ETH_RX_DESC_DONE;
1727         }
1728         rx_buf = &rxr->rx_buf_ring[cons];
1729         if (rx_buf->mbuf == NULL)
1730                 return RTE_ETH_RX_DESC_UNAVAIL;
1731
1732
1733         return RTE_ETH_RX_DESC_AVAIL;
1734 }
1735
1736 static int
1737 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1738 {
1739         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1740         struct bnxt_tx_ring_info *txr;
1741         struct bnxt_cp_ring_info *cpr;
1742         struct bnxt_sw_tx_bd *tx_buf;
1743         struct tx_pkt_cmpl *txcmp;
1744         uint32_t cons, cp_cons;
1745
1746         if (!txq)
1747                 return -EINVAL;
1748
1749         cpr = txq->cp_ring;
1750         txr = txq->tx_ring;
1751
1752         if (offset >= txq->nb_tx_desc)
1753                 return -EINVAL;
1754
1755         cons = RING_CMP(cpr->cp_ring_struct, offset);
1756         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1757         cp_cons = cpr->cp_raw_cons;
1758
1759         if (cons > cp_cons) {
1760                 if (CMPL_VALID(txcmp, cpr->valid))
1761                         return RTE_ETH_TX_DESC_UNAVAIL;
1762         } else {
1763                 if (CMPL_VALID(txcmp, !cpr->valid))
1764                         return RTE_ETH_TX_DESC_UNAVAIL;
1765         }
1766         tx_buf = &txr->tx_buf_ring[cons];
1767         if (tx_buf->mbuf == NULL)
1768                 return RTE_ETH_TX_DESC_DONE;
1769
1770         return RTE_ETH_TX_DESC_FULL;
1771 }
1772
1773 static struct bnxt_filter_info *
1774 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1775                                 struct rte_eth_ethertype_filter *efilter,
1776                                 struct bnxt_vnic_info *vnic0,
1777                                 struct bnxt_vnic_info *vnic,
1778                                 int *ret)
1779 {
1780         struct bnxt_filter_info *mfilter = NULL;
1781         int match = 0;
1782         *ret = 0;
1783
1784         if (efilter->ether_type == ETHER_TYPE_IPv4 ||
1785                 efilter->ether_type == ETHER_TYPE_IPv6) {
1786                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1787                         " ethertype filter.", efilter->ether_type);
1788                 *ret = -EINVAL;
1789                 goto exit;
1790         }
1791         if (efilter->queue >= bp->rx_nr_rings) {
1792                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1793                 *ret = -EINVAL;
1794                 goto exit;
1795         }
1796
1797         vnic0 = &bp->vnic_info[0];
1798         vnic = &bp->vnic_info[efilter->queue];
1799         if (vnic == NULL) {
1800                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1801                 *ret = -EINVAL;
1802                 goto exit;
1803         }
1804
1805         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1806                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1807                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1808                                      mfilter->l2_addr, ETHER_ADDR_LEN) &&
1809                              mfilter->flags ==
1810                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1811                              mfilter->ethertype == efilter->ether_type)) {
1812                                 match = 1;
1813                                 break;
1814                         }
1815                 }
1816         } else {
1817                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1818                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1819                                      mfilter->l2_addr, ETHER_ADDR_LEN) &&
1820                              mfilter->ethertype == efilter->ether_type &&
1821                              mfilter->flags ==
1822                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1823                                 match = 1;
1824                                 break;
1825                         }
1826         }
1827
1828         if (match)
1829                 *ret = -EEXIST;
1830
1831 exit:
1832         return mfilter;
1833 }
1834
1835 static int
1836 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1837                         enum rte_filter_op filter_op,
1838                         void *arg)
1839 {
1840         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1841         struct rte_eth_ethertype_filter *efilter =
1842                         (struct rte_eth_ethertype_filter *)arg;
1843         struct bnxt_filter_info *bfilter, *filter1;
1844         struct bnxt_vnic_info *vnic, *vnic0;
1845         int ret;
1846
1847         if (filter_op == RTE_ETH_FILTER_NOP)
1848                 return 0;
1849
1850         if (arg == NULL) {
1851                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
1852                             filter_op);
1853                 return -EINVAL;
1854         }
1855
1856         vnic0 = &bp->vnic_info[0];
1857         vnic = &bp->vnic_info[efilter->queue];
1858
1859         switch (filter_op) {
1860         case RTE_ETH_FILTER_ADD:
1861                 bnxt_match_and_validate_ether_filter(bp, efilter,
1862                                                         vnic0, vnic, &ret);
1863                 if (ret < 0)
1864                         return ret;
1865
1866                 bfilter = bnxt_get_unused_filter(bp);
1867                 if (bfilter == NULL) {
1868                         PMD_DRV_LOG(ERR,
1869                                 "Not enough resources for a new filter.\n");
1870                         return -ENOMEM;
1871                 }
1872                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1873                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1874                        ETHER_ADDR_LEN);
1875                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1876                        ETHER_ADDR_LEN);
1877                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1878                 bfilter->ethertype = efilter->ether_type;
1879                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1880
1881                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1882                 if (filter1 == NULL) {
1883                         ret = -1;
1884                         goto cleanup;
1885                 }
1886                 bfilter->enables |=
1887                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1888                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1889
1890                 bfilter->dst_id = vnic->fw_vnic_id;
1891
1892                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1893                         bfilter->flags =
1894                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1895                 }
1896
1897                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1898                 if (ret)
1899                         goto cleanup;
1900                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1901                 break;
1902         case RTE_ETH_FILTER_DELETE:
1903                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1904                                                         vnic0, vnic, &ret);
1905                 if (ret == -EEXIST) {
1906                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1907
1908                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1909                                       next);
1910                         bnxt_free_filter(bp, filter1);
1911                 } else if (ret == 0) {
1912                         PMD_DRV_LOG(ERR, "No matching filter found\n");
1913                 }
1914                 break;
1915         default:
1916                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
1917                 ret = -EINVAL;
1918                 goto error;
1919         }
1920         return ret;
1921 cleanup:
1922         bnxt_free_filter(bp, bfilter);
1923 error:
1924         return ret;
1925 }
1926
1927 static inline int
1928 parse_ntuple_filter(struct bnxt *bp,
1929                     struct rte_eth_ntuple_filter *nfilter,
1930                     struct bnxt_filter_info *bfilter)
1931 {
1932         uint32_t en = 0;
1933
1934         if (nfilter->queue >= bp->rx_nr_rings) {
1935                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
1936                 return -EINVAL;
1937         }
1938
1939         switch (nfilter->dst_port_mask) {
1940         case UINT16_MAX:
1941                 bfilter->dst_port_mask = -1;
1942                 bfilter->dst_port = nfilter->dst_port;
1943                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1944                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1945                 break;
1946         default:
1947                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
1948                 return -EINVAL;
1949         }
1950
1951         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1952         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1953
1954         switch (nfilter->proto_mask) {
1955         case UINT8_MAX:
1956                 if (nfilter->proto == 17) /* IPPROTO_UDP */
1957                         bfilter->ip_protocol = 17;
1958                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1959                         bfilter->ip_protocol = 6;
1960                 else
1961                         return -EINVAL;
1962                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1963                 break;
1964         default:
1965                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
1966                 return -EINVAL;
1967         }
1968
1969         switch (nfilter->dst_ip_mask) {
1970         case UINT32_MAX:
1971                 bfilter->dst_ipaddr_mask[0] = -1;
1972                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
1973                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
1974                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
1975                 break;
1976         default:
1977                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
1978                 return -EINVAL;
1979         }
1980
1981         switch (nfilter->src_ip_mask) {
1982         case UINT32_MAX:
1983                 bfilter->src_ipaddr_mask[0] = -1;
1984                 bfilter->src_ipaddr[0] = nfilter->src_ip;
1985                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
1986                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
1987                 break;
1988         default:
1989                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
1990                 return -EINVAL;
1991         }
1992
1993         switch (nfilter->src_port_mask) {
1994         case UINT16_MAX:
1995                 bfilter->src_port_mask = -1;
1996                 bfilter->src_port = nfilter->src_port;
1997                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
1998                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
1999                 break;
2000         default:
2001                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2002                 return -EINVAL;
2003         }
2004
2005         //TODO Priority
2006         //nfilter->priority = (uint8_t)filter->priority;
2007
2008         bfilter->enables = en;
2009         return 0;
2010 }
2011
2012 static struct bnxt_filter_info*
2013 bnxt_match_ntuple_filter(struct bnxt *bp,
2014                          struct bnxt_filter_info *bfilter,
2015                          struct bnxt_vnic_info **mvnic)
2016 {
2017         struct bnxt_filter_info *mfilter = NULL;
2018         int i;
2019
2020         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2021                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2022                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2023                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2024                             bfilter->src_ipaddr_mask[0] ==
2025                             mfilter->src_ipaddr_mask[0] &&
2026                             bfilter->src_port == mfilter->src_port &&
2027                             bfilter->src_port_mask == mfilter->src_port_mask &&
2028                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2029                             bfilter->dst_ipaddr_mask[0] ==
2030                             mfilter->dst_ipaddr_mask[0] &&
2031                             bfilter->dst_port == mfilter->dst_port &&
2032                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2033                             bfilter->flags == mfilter->flags &&
2034                             bfilter->enables == mfilter->enables) {
2035                                 if (mvnic)
2036                                         *mvnic = vnic;
2037                                 return mfilter;
2038                         }
2039                 }
2040         }
2041         return NULL;
2042 }
2043
2044 static int
2045 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2046                        struct rte_eth_ntuple_filter *nfilter,
2047                        enum rte_filter_op filter_op)
2048 {
2049         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2050         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2051         int ret;
2052
2053         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2054                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2055                 return -EINVAL;
2056         }
2057
2058         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2059                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2060                 return -EINVAL;
2061         }
2062
2063         bfilter = bnxt_get_unused_filter(bp);
2064         if (bfilter == NULL) {
2065                 PMD_DRV_LOG(ERR,
2066                         "Not enough resources for a new filter.\n");
2067                 return -ENOMEM;
2068         }
2069         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2070         if (ret < 0)
2071                 goto free_filter;
2072
2073         vnic = &bp->vnic_info[nfilter->queue];
2074         vnic0 = &bp->vnic_info[0];
2075         filter1 = STAILQ_FIRST(&vnic0->filter);
2076         if (filter1 == NULL) {
2077                 ret = -1;
2078                 goto free_filter;
2079         }
2080
2081         bfilter->dst_id = vnic->fw_vnic_id;
2082         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2083         bfilter->enables |=
2084                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2085         bfilter->ethertype = 0x800;
2086         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2087
2088         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2089
2090         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2091             bfilter->dst_id == mfilter->dst_id) {
2092                 PMD_DRV_LOG(ERR, "filter exists.\n");
2093                 ret = -EEXIST;
2094                 goto free_filter;
2095         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2096                    bfilter->dst_id != mfilter->dst_id) {
2097                 mfilter->dst_id = vnic->fw_vnic_id;
2098                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2099                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2100                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2101                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2102                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2103                 goto free_filter;
2104         }
2105         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2106                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2107                 ret = -ENOENT;
2108                 goto free_filter;
2109         }
2110
2111         if (filter_op == RTE_ETH_FILTER_ADD) {
2112                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2113                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2114                 if (ret)
2115                         goto free_filter;
2116                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2117         } else {
2118                 if (mfilter == NULL) {
2119                         /* This should not happen. But for Coverity! */
2120                         ret = -ENOENT;
2121                         goto free_filter;
2122                 }
2123                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2124
2125                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2126                 bnxt_free_filter(bp, mfilter);
2127                 mfilter->fw_l2_filter_id = -1;
2128                 bnxt_free_filter(bp, bfilter);
2129                 bfilter->fw_l2_filter_id = -1;
2130         }
2131
2132         return 0;
2133 free_filter:
2134         bfilter->fw_l2_filter_id = -1;
2135         bnxt_free_filter(bp, bfilter);
2136         return ret;
2137 }
2138
2139 static int
2140 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2141                         enum rte_filter_op filter_op,
2142                         void *arg)
2143 {
2144         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2145         int ret;
2146
2147         if (filter_op == RTE_ETH_FILTER_NOP)
2148                 return 0;
2149
2150         if (arg == NULL) {
2151                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2152                             filter_op);
2153                 return -EINVAL;
2154         }
2155
2156         switch (filter_op) {
2157         case RTE_ETH_FILTER_ADD:
2158                 ret = bnxt_cfg_ntuple_filter(bp,
2159                         (struct rte_eth_ntuple_filter *)arg,
2160                         filter_op);
2161                 break;
2162         case RTE_ETH_FILTER_DELETE:
2163                 ret = bnxt_cfg_ntuple_filter(bp,
2164                         (struct rte_eth_ntuple_filter *)arg,
2165                         filter_op);
2166                 break;
2167         default:
2168                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2169                 ret = -EINVAL;
2170                 break;
2171         }
2172         return ret;
2173 }
2174
2175 static int
2176 bnxt_parse_fdir_filter(struct bnxt *bp,
2177                        struct rte_eth_fdir_filter *fdir,
2178                        struct bnxt_filter_info *filter)
2179 {
2180         enum rte_fdir_mode fdir_mode =
2181                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2182         struct bnxt_vnic_info *vnic0, *vnic;
2183         struct bnxt_filter_info *filter1;
2184         uint32_t en = 0;
2185         int i;
2186
2187         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2188                 return -EINVAL;
2189
2190         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2191         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2192
2193         switch (fdir->input.flow_type) {
2194         case RTE_ETH_FLOW_IPV4:
2195         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2196                 /* FALLTHROUGH */
2197                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2198                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2199                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2200                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2201                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2202                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2203                 filter->ip_addr_type =
2204                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2205                 filter->src_ipaddr_mask[0] = 0xffffffff;
2206                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2207                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2208                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2209                 filter->ethertype = 0x800;
2210                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2211                 break;
2212         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2213                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2214                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2215                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2216                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2217                 filter->dst_port_mask = 0xffff;
2218                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2219                 filter->src_port_mask = 0xffff;
2220                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2221                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2222                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2223                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2224                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2225                 filter->ip_protocol = 6;
2226                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2227                 filter->ip_addr_type =
2228                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2229                 filter->src_ipaddr_mask[0] = 0xffffffff;
2230                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2231                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2232                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2233                 filter->ethertype = 0x800;
2234                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2235                 break;
2236         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2237                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2238                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2239                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2240                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2241                 filter->dst_port_mask = 0xffff;
2242                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2243                 filter->src_port_mask = 0xffff;
2244                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2245                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2246                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2247                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2248                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2249                 filter->ip_protocol = 17;
2250                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2251                 filter->ip_addr_type =
2252                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2253                 filter->src_ipaddr_mask[0] = 0xffffffff;
2254                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2255                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2256                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2257                 filter->ethertype = 0x800;
2258                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2259                 break;
2260         case RTE_ETH_FLOW_IPV6:
2261         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2262                 /* FALLTHROUGH */
2263                 filter->ip_addr_type =
2264                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2265                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2266                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2267                 rte_memcpy(filter->src_ipaddr,
2268                            fdir->input.flow.ipv6_flow.src_ip, 16);
2269                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2270                 rte_memcpy(filter->dst_ipaddr,
2271                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2272                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2273                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2274                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2275                 memset(filter->src_ipaddr_mask, 0xff, 16);
2276                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2277                 filter->ethertype = 0x86dd;
2278                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2279                 break;
2280         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2281                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2282                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2283                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2284                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2285                 filter->dst_port_mask = 0xffff;
2286                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2287                 filter->src_port_mask = 0xffff;
2288                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2289                 filter->ip_addr_type =
2290                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2291                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2292                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2293                 rte_memcpy(filter->src_ipaddr,
2294                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2295                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2296                 rte_memcpy(filter->dst_ipaddr,
2297                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2298                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2299                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2300                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2301                 memset(filter->src_ipaddr_mask, 0xff, 16);
2302                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2303                 filter->ethertype = 0x86dd;
2304                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2305                 break;
2306         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2307                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2308                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2309                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2310                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2311                 filter->dst_port_mask = 0xffff;
2312                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2313                 filter->src_port_mask = 0xffff;
2314                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2315                 filter->ip_addr_type =
2316                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2317                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2318                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2319                 rte_memcpy(filter->src_ipaddr,
2320                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2321                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2322                 rte_memcpy(filter->dst_ipaddr,
2323                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2324                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2325                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2326                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2327                 memset(filter->src_ipaddr_mask, 0xff, 16);
2328                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2329                 filter->ethertype = 0x86dd;
2330                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2331                 break;
2332         case RTE_ETH_FLOW_L2_PAYLOAD:
2333                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2334                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2335                 break;
2336         case RTE_ETH_FLOW_VXLAN:
2337                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2338                         return -EINVAL;
2339                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2340                 filter->tunnel_type =
2341                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2342                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2343                 break;
2344         case RTE_ETH_FLOW_NVGRE:
2345                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2346                         return -EINVAL;
2347                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2348                 filter->tunnel_type =
2349                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2350                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2351                 break;
2352         case RTE_ETH_FLOW_UNKNOWN:
2353         case RTE_ETH_FLOW_RAW:
2354         case RTE_ETH_FLOW_FRAG_IPV4:
2355         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2356         case RTE_ETH_FLOW_FRAG_IPV6:
2357         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2358         case RTE_ETH_FLOW_IPV6_EX:
2359         case RTE_ETH_FLOW_IPV6_TCP_EX:
2360         case RTE_ETH_FLOW_IPV6_UDP_EX:
2361         case RTE_ETH_FLOW_GENEVE:
2362                 /* FALLTHROUGH */
2363         default:
2364                 return -EINVAL;
2365         }
2366
2367         vnic0 = &bp->vnic_info[0];
2368         vnic = &bp->vnic_info[fdir->action.rx_queue];
2369         if (vnic == NULL) {
2370                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2371                 return -EINVAL;
2372         }
2373
2374
2375         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2376                 rte_memcpy(filter->dst_macaddr,
2377                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2378                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2379         }
2380
2381         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2382                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2383                 filter1 = STAILQ_FIRST(&vnic0->filter);
2384                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2385         } else {
2386                 filter->dst_id = vnic->fw_vnic_id;
2387                 for (i = 0; i < ETHER_ADDR_LEN; i++)
2388                         if (filter->dst_macaddr[i] == 0x00)
2389                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2390                         else
2391                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2392         }
2393
2394         if (filter1 == NULL)
2395                 return -EINVAL;
2396
2397         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2398         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2399
2400         filter->enables = en;
2401
2402         return 0;
2403 }
2404
2405 static struct bnxt_filter_info *
2406 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2407                 struct bnxt_vnic_info **mvnic)
2408 {
2409         struct bnxt_filter_info *mf = NULL;
2410         int i;
2411
2412         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2413                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2414
2415                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2416                         if (mf->filter_type == nf->filter_type &&
2417                             mf->flags == nf->flags &&
2418                             mf->src_port == nf->src_port &&
2419                             mf->src_port_mask == nf->src_port_mask &&
2420                             mf->dst_port == nf->dst_port &&
2421                             mf->dst_port_mask == nf->dst_port_mask &&
2422                             mf->ip_protocol == nf->ip_protocol &&
2423                             mf->ip_addr_type == nf->ip_addr_type &&
2424                             mf->ethertype == nf->ethertype &&
2425                             mf->vni == nf->vni &&
2426                             mf->tunnel_type == nf->tunnel_type &&
2427                             mf->l2_ovlan == nf->l2_ovlan &&
2428                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2429                             mf->l2_ivlan == nf->l2_ivlan &&
2430                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2431                             !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) &&
2432                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2433                                     ETHER_ADDR_LEN) &&
2434                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2435                                     ETHER_ADDR_LEN) &&
2436                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2437                                     ETHER_ADDR_LEN) &&
2438                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2439                                     sizeof(nf->src_ipaddr)) &&
2440                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2441                                     sizeof(nf->src_ipaddr_mask)) &&
2442                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2443                                     sizeof(nf->dst_ipaddr)) &&
2444                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2445                                     sizeof(nf->dst_ipaddr_mask))) {
2446                                 if (mvnic)
2447                                         *mvnic = vnic;
2448                                 return mf;
2449                         }
2450                 }
2451         }
2452         return NULL;
2453 }
2454
2455 static int
2456 bnxt_fdir_filter(struct rte_eth_dev *dev,
2457                  enum rte_filter_op filter_op,
2458                  void *arg)
2459 {
2460         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2461         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2462         struct bnxt_filter_info *filter, *match;
2463         struct bnxt_vnic_info *vnic, *mvnic;
2464         int ret = 0, i;
2465
2466         if (filter_op == RTE_ETH_FILTER_NOP)
2467                 return 0;
2468
2469         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2470                 return -EINVAL;
2471
2472         switch (filter_op) {
2473         case RTE_ETH_FILTER_ADD:
2474         case RTE_ETH_FILTER_DELETE:
2475                 /* FALLTHROUGH */
2476                 filter = bnxt_get_unused_filter(bp);
2477                 if (filter == NULL) {
2478                         PMD_DRV_LOG(ERR,
2479                                 "Not enough resources for a new flow.\n");
2480                         return -ENOMEM;
2481                 }
2482
2483                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2484                 if (ret != 0)
2485                         goto free_filter;
2486                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2487
2488                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2489                         vnic = &bp->vnic_info[0];
2490                 else
2491                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2492
2493                 match = bnxt_match_fdir(bp, filter, &mvnic);
2494                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2495                         if (match->dst_id == vnic->fw_vnic_id) {
2496                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2497                                 ret = -EEXIST;
2498                                 goto free_filter;
2499                         } else {
2500                                 match->dst_id = vnic->fw_vnic_id;
2501                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2502                                                                   match->dst_id,
2503                                                                   match);
2504                                 STAILQ_REMOVE(&mvnic->filter, match,
2505                                               bnxt_filter_info, next);
2506                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2507                                 PMD_DRV_LOG(ERR,
2508                                         "Filter with matching pattern exist\n");
2509                                 PMD_DRV_LOG(ERR,
2510                                         "Updated it to new destination q\n");
2511                                 goto free_filter;
2512                         }
2513                 }
2514                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2515                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2516                         ret = -ENOENT;
2517                         goto free_filter;
2518                 }
2519
2520                 if (filter_op == RTE_ETH_FILTER_ADD) {
2521                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2522                                                           filter->dst_id,
2523                                                           filter);
2524                         if (ret)
2525                                 goto free_filter;
2526                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2527                 } else {
2528                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2529                         STAILQ_REMOVE(&vnic->filter, match,
2530                                       bnxt_filter_info, next);
2531                         bnxt_free_filter(bp, match);
2532                         filter->fw_l2_filter_id = -1;
2533                         bnxt_free_filter(bp, filter);
2534                 }
2535                 break;
2536         case RTE_ETH_FILTER_FLUSH:
2537                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2538                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2539
2540                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2541                                 if (filter->filter_type ==
2542                                     HWRM_CFA_NTUPLE_FILTER) {
2543                                         ret =
2544                                         bnxt_hwrm_clear_ntuple_filter(bp,
2545                                                                       filter);
2546                                         STAILQ_REMOVE(&vnic->filter, filter,
2547                                                       bnxt_filter_info, next);
2548                                 }
2549                         }
2550                 }
2551                 return ret;
2552         case RTE_ETH_FILTER_UPDATE:
2553         case RTE_ETH_FILTER_STATS:
2554         case RTE_ETH_FILTER_INFO:
2555                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2556                 break;
2557         default:
2558                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2559                 ret = -EINVAL;
2560                 break;
2561         }
2562         return ret;
2563
2564 free_filter:
2565         filter->fw_l2_filter_id = -1;
2566         bnxt_free_filter(bp, filter);
2567         return ret;
2568 }
2569
2570 static int
2571 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2572                     enum rte_filter_type filter_type,
2573                     enum rte_filter_op filter_op, void *arg)
2574 {
2575         int ret = 0;
2576
2577         switch (filter_type) {
2578         case RTE_ETH_FILTER_TUNNEL:
2579                 PMD_DRV_LOG(ERR,
2580                         "filter type: %d: To be implemented\n", filter_type);
2581                 break;
2582         case RTE_ETH_FILTER_FDIR:
2583                 ret = bnxt_fdir_filter(dev, filter_op, arg);
2584                 break;
2585         case RTE_ETH_FILTER_NTUPLE:
2586                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2587                 break;
2588         case RTE_ETH_FILTER_ETHERTYPE:
2589                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2590                 break;
2591         case RTE_ETH_FILTER_GENERIC:
2592                 if (filter_op != RTE_ETH_FILTER_GET)
2593                         return -EINVAL;
2594                 *(const void **)arg = &bnxt_flow_ops;
2595                 break;
2596         default:
2597                 PMD_DRV_LOG(ERR,
2598                         "Filter type (%d) not supported", filter_type);
2599                 ret = -EINVAL;
2600                 break;
2601         }
2602         return ret;
2603 }
2604
2605 static const uint32_t *
2606 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2607 {
2608         static const uint32_t ptypes[] = {
2609                 RTE_PTYPE_L2_ETHER_VLAN,
2610                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2611                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2612                 RTE_PTYPE_L4_ICMP,
2613                 RTE_PTYPE_L4_TCP,
2614                 RTE_PTYPE_L4_UDP,
2615                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2616                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2617                 RTE_PTYPE_INNER_L4_ICMP,
2618                 RTE_PTYPE_INNER_L4_TCP,
2619                 RTE_PTYPE_INNER_L4_UDP,
2620                 RTE_PTYPE_UNKNOWN
2621         };
2622
2623         if (dev->rx_pkt_burst == bnxt_recv_pkts)
2624                 return ptypes;
2625         return NULL;
2626 }
2627
2628 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2629                          int reg_win)
2630 {
2631         uint32_t reg_base = *reg_arr & 0xfffff000;
2632         uint32_t win_off;
2633         int i;
2634
2635         for (i = 0; i < count; i++) {
2636                 if ((reg_arr[i] & 0xfffff000) != reg_base)
2637                         return -ERANGE;
2638         }
2639         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2640         rte_cpu_to_le_32(rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off));
2641         return 0;
2642 }
2643
2644 static int bnxt_map_ptp_regs(struct bnxt *bp)
2645 {
2646         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2647         uint32_t *reg_arr;
2648         int rc, i;
2649
2650         reg_arr = ptp->rx_regs;
2651         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2652         if (rc)
2653                 return rc;
2654
2655         reg_arr = ptp->tx_regs;
2656         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2657         if (rc)
2658                 return rc;
2659
2660         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2661                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2662
2663         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2664                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2665
2666         return 0;
2667 }
2668
2669 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2670 {
2671         rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2672                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16));
2673         rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2674                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20));
2675 }
2676
2677 static uint64_t bnxt_cc_read(struct bnxt *bp)
2678 {
2679         uint64_t ns;
2680
2681         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2682                               BNXT_GRCPF_REG_SYNC_TIME));
2683         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2684                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2685         return ns;
2686 }
2687
2688 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2689 {
2690         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2691         uint32_t fifo;
2692
2693         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2694                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2695         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2696                 return -EAGAIN;
2697
2698         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2699                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2700         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2701                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2702         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2703                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2704
2705         return 0;
2706 }
2707
2708 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2709 {
2710         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2711         struct bnxt_pf_info *pf = &bp->pf;
2712         uint16_t port_id;
2713         uint32_t fifo;
2714
2715         if (!ptp)
2716                 return -ENODEV;
2717
2718         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2719                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2720         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2721                 return -EAGAIN;
2722
2723         port_id = pf->port_id;
2724         rte_cpu_to_le_32(rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2725                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]));
2726
2727         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2728                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2729         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2730 /*              bnxt_clr_rx_ts(bp);       TBD  */
2731                 return -EBUSY;
2732         }
2733
2734         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2735                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2736         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2737                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2738
2739         return 0;
2740 }
2741
2742 static int
2743 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2744 {
2745         uint64_t ns;
2746         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2747         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2748
2749         if (!ptp)
2750                 return 0;
2751
2752         ns = rte_timespec_to_ns(ts);
2753         /* Set the timecounters to a new value. */
2754         ptp->tc.nsec = ns;
2755
2756         return 0;
2757 }
2758
2759 static int
2760 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2761 {
2762         uint64_t ns, systime_cycles;
2763         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2764         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2765
2766         if (!ptp)
2767                 return 0;
2768
2769         systime_cycles = bnxt_cc_read(bp);
2770         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2771         *ts = rte_ns_to_timespec(ns);
2772
2773         return 0;
2774 }
2775 static int
2776 bnxt_timesync_enable(struct rte_eth_dev *dev)
2777 {
2778         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2779         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2780         uint32_t shift = 0;
2781
2782         if (!ptp)
2783                 return 0;
2784
2785         ptp->rx_filter = 1;
2786         ptp->tx_tstamp_en = 1;
2787         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2788
2789         if (!bnxt_hwrm_ptp_cfg(bp))
2790                 bnxt_map_ptp_regs(bp);
2791
2792         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2793         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2794         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2795
2796         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2797         ptp->tc.cc_shift = shift;
2798         ptp->tc.nsec_mask = (1ULL << shift) - 1;
2799
2800         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2801         ptp->rx_tstamp_tc.cc_shift = shift;
2802         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2803
2804         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2805         ptp->tx_tstamp_tc.cc_shift = shift;
2806         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2807
2808         return 0;
2809 }
2810
2811 static int
2812 bnxt_timesync_disable(struct rte_eth_dev *dev)
2813 {
2814         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2815         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2816
2817         if (!ptp)
2818                 return 0;
2819
2820         ptp->rx_filter = 0;
2821         ptp->tx_tstamp_en = 0;
2822         ptp->rxctl = 0;
2823
2824         bnxt_hwrm_ptp_cfg(bp);
2825
2826         bnxt_unmap_ptp_regs(bp);
2827
2828         return 0;
2829 }
2830
2831 static int
2832 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2833                                  struct timespec *timestamp,
2834                                  uint32_t flags __rte_unused)
2835 {
2836         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2837         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2838         uint64_t rx_tstamp_cycles = 0;
2839         uint64_t ns;
2840
2841         if (!ptp)
2842                 return 0;
2843
2844         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2845         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2846         *timestamp = rte_ns_to_timespec(ns);
2847         return  0;
2848 }
2849
2850 static int
2851 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2852                                  struct timespec *timestamp)
2853 {
2854         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2855         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2856         uint64_t tx_tstamp_cycles = 0;
2857         uint64_t ns;
2858
2859         if (!ptp)
2860                 return 0;
2861
2862         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2863         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2864         *timestamp = rte_ns_to_timespec(ns);
2865
2866         return 0;
2867 }
2868
2869 static int
2870 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2871 {
2872         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2873         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2874
2875         if (!ptp)
2876                 return 0;
2877
2878         ptp->tc.nsec += delta;
2879
2880         return 0;
2881 }
2882
2883 static int
2884 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2885 {
2886         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2887         int rc;
2888         uint32_t dir_entries;
2889         uint32_t entry_length;
2890
2891         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
2892                 bp->pdev->addr.domain, bp->pdev->addr.bus,
2893                 bp->pdev->addr.devid, bp->pdev->addr.function);
2894
2895         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2896         if (rc != 0)
2897                 return rc;
2898
2899         return dir_entries * entry_length;
2900 }
2901
2902 static int
2903 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2904                 struct rte_dev_eeprom_info *in_eeprom)
2905 {
2906         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2907         uint32_t index;
2908         uint32_t offset;
2909
2910         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2911                 "len = %d\n", bp->pdev->addr.domain,
2912                 bp->pdev->addr.bus, bp->pdev->addr.devid,
2913                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2914
2915         if (in_eeprom->offset == 0) /* special offset value to get directory */
2916                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2917                                                 in_eeprom->data);
2918
2919         index = in_eeprom->offset >> 24;
2920         offset = in_eeprom->offset & 0xffffff;
2921
2922         if (index != 0)
2923                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2924                                            in_eeprom->length, in_eeprom->data);
2925
2926         return 0;
2927 }
2928
2929 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2930 {
2931         switch (dir_type) {
2932         case BNX_DIR_TYPE_CHIMP_PATCH:
2933         case BNX_DIR_TYPE_BOOTCODE:
2934         case BNX_DIR_TYPE_BOOTCODE_2:
2935         case BNX_DIR_TYPE_APE_FW:
2936         case BNX_DIR_TYPE_APE_PATCH:
2937         case BNX_DIR_TYPE_KONG_FW:
2938         case BNX_DIR_TYPE_KONG_PATCH:
2939         case BNX_DIR_TYPE_BONO_FW:
2940         case BNX_DIR_TYPE_BONO_PATCH:
2941                 /* FALLTHROUGH */
2942                 return true;
2943         }
2944
2945         return false;
2946 }
2947
2948 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2949 {
2950         switch (dir_type) {
2951         case BNX_DIR_TYPE_AVS:
2952         case BNX_DIR_TYPE_EXP_ROM_MBA:
2953         case BNX_DIR_TYPE_PCIE:
2954         case BNX_DIR_TYPE_TSCF_UCODE:
2955         case BNX_DIR_TYPE_EXT_PHY:
2956         case BNX_DIR_TYPE_CCM:
2957         case BNX_DIR_TYPE_ISCSI_BOOT:
2958         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2959         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2960                 /* FALLTHROUGH */
2961                 return true;
2962         }
2963
2964         return false;
2965 }
2966
2967 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
2968 {
2969         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2970                 bnxt_dir_type_is_other_exec_format(dir_type);
2971 }
2972
2973 static int
2974 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2975                 struct rte_dev_eeprom_info *in_eeprom)
2976 {
2977         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2978         uint8_t index, dir_op;
2979         uint16_t type, ext, ordinal, attr;
2980
2981         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2982                 "len = %d\n", bp->pdev->addr.domain,
2983                 bp->pdev->addr.bus, bp->pdev->addr.devid,
2984                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2985
2986         if (!BNXT_PF(bp)) {
2987                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
2988                 return -EINVAL;
2989         }
2990
2991         type = in_eeprom->magic >> 16;
2992
2993         if (type == 0xffff) { /* special value for directory operations */
2994                 index = in_eeprom->magic & 0xff;
2995                 dir_op = in_eeprom->magic >> 8;
2996                 if (index == 0)
2997                         return -EINVAL;
2998                 switch (dir_op) {
2999                 case 0x0e: /* erase */
3000                         if (in_eeprom->offset != ~in_eeprom->magic)
3001                                 return -EINVAL;
3002                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3003                 default:
3004                         return -EINVAL;
3005                 }
3006         }
3007
3008         /* Create or re-write an NVM item: */
3009         if (bnxt_dir_type_is_executable(type) == true)
3010                 return -EOPNOTSUPP;
3011         ext = in_eeprom->magic & 0xffff;
3012         ordinal = in_eeprom->offset >> 16;
3013         attr = in_eeprom->offset & 0xffff;
3014
3015         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3016                                      in_eeprom->data, in_eeprom->length);
3017         return 0;
3018 }
3019
3020 /*
3021  * Initialization
3022  */
3023
3024 static const struct eth_dev_ops bnxt_dev_ops = {
3025         .dev_infos_get = bnxt_dev_info_get_op,
3026         .dev_close = bnxt_dev_close_op,
3027         .dev_configure = bnxt_dev_configure_op,
3028         .dev_start = bnxt_dev_start_op,
3029         .dev_stop = bnxt_dev_stop_op,
3030         .dev_set_link_up = bnxt_dev_set_link_up_op,
3031         .dev_set_link_down = bnxt_dev_set_link_down_op,
3032         .stats_get = bnxt_stats_get_op,
3033         .stats_reset = bnxt_stats_reset_op,
3034         .rx_queue_setup = bnxt_rx_queue_setup_op,
3035         .rx_queue_release = bnxt_rx_queue_release_op,
3036         .tx_queue_setup = bnxt_tx_queue_setup_op,
3037         .tx_queue_release = bnxt_tx_queue_release_op,
3038         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3039         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3040         .reta_update = bnxt_reta_update_op,
3041         .reta_query = bnxt_reta_query_op,
3042         .rss_hash_update = bnxt_rss_hash_update_op,
3043         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3044         .link_update = bnxt_link_update_op,
3045         .promiscuous_enable = bnxt_promiscuous_enable_op,
3046         .promiscuous_disable = bnxt_promiscuous_disable_op,
3047         .allmulticast_enable = bnxt_allmulticast_enable_op,
3048         .allmulticast_disable = bnxt_allmulticast_disable_op,
3049         .mac_addr_add = bnxt_mac_addr_add_op,
3050         .mac_addr_remove = bnxt_mac_addr_remove_op,
3051         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3052         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3053         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3054         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3055         .vlan_filter_set = bnxt_vlan_filter_set_op,
3056         .vlan_offload_set = bnxt_vlan_offload_set_op,
3057         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3058         .mtu_set = bnxt_mtu_set_op,
3059         .mac_addr_set = bnxt_set_default_mac_addr_op,
3060         .xstats_get = bnxt_dev_xstats_get_op,
3061         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3062         .xstats_reset = bnxt_dev_xstats_reset_op,
3063         .fw_version_get = bnxt_fw_version_get,
3064         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3065         .rxq_info_get = bnxt_rxq_info_get_op,
3066         .txq_info_get = bnxt_txq_info_get_op,
3067         .dev_led_on = bnxt_dev_led_on_op,
3068         .dev_led_off = bnxt_dev_led_off_op,
3069         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3070         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3071         .rx_queue_count = bnxt_rx_queue_count_op,
3072         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3073         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3074         .rx_queue_start = bnxt_rx_queue_start,
3075         .rx_queue_stop = bnxt_rx_queue_stop,
3076         .tx_queue_start = bnxt_tx_queue_start,
3077         .tx_queue_stop = bnxt_tx_queue_stop,
3078         .filter_ctrl = bnxt_filter_ctrl_op,
3079         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3080         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3081         .get_eeprom           = bnxt_get_eeprom_op,
3082         .set_eeprom           = bnxt_set_eeprom_op,
3083         .timesync_enable      = bnxt_timesync_enable,
3084         .timesync_disable     = bnxt_timesync_disable,
3085         .timesync_read_time   = bnxt_timesync_read_time,
3086         .timesync_write_time   = bnxt_timesync_write_time,
3087         .timesync_adjust_time = bnxt_timesync_adjust_time,
3088         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3089         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3090 };
3091
3092 static bool bnxt_vf_pciid(uint16_t id)
3093 {
3094         if (id == BROADCOM_DEV_ID_57304_VF ||
3095             id == BROADCOM_DEV_ID_57406_VF ||
3096             id == BROADCOM_DEV_ID_5731X_VF ||
3097             id == BROADCOM_DEV_ID_5741X_VF ||
3098             id == BROADCOM_DEV_ID_57414_VF ||
3099             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3100             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3101             id == BROADCOM_DEV_ID_58802_VF)
3102                 return true;
3103         return false;
3104 }
3105
3106 bool bnxt_stratus_device(struct bnxt *bp)
3107 {
3108         uint16_t id = bp->pdev->id.device_id;
3109
3110         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3111             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3112             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3113                 return true;
3114         return false;
3115 }
3116
3117 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3118 {
3119         struct bnxt *bp = eth_dev->data->dev_private;
3120         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3121         int rc;
3122
3123         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3124         if (!pci_dev->mem_resource[0].addr) {
3125                 PMD_DRV_LOG(ERR,
3126                         "Cannot find PCI device base address, aborting\n");
3127                 rc = -ENODEV;
3128                 goto init_err_disable;
3129         }
3130
3131         bp->eth_dev = eth_dev;
3132         bp->pdev = pci_dev;
3133
3134         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3135         if (!bp->bar0) {
3136                 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3137                 rc = -ENOMEM;
3138                 goto init_err_release;
3139         }
3140
3141         if (!pci_dev->mem_resource[2].addr) {
3142                 PMD_DRV_LOG(ERR,
3143                             "Cannot find PCI device BAR 2 address, aborting\n");
3144                 rc = -ENODEV;
3145                 goto init_err_release;
3146         } else {
3147                 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3148         }
3149
3150         return 0;
3151
3152 init_err_release:
3153         if (bp->bar0)
3154                 bp->bar0 = NULL;
3155         if (bp->doorbell_base)
3156                 bp->doorbell_base = NULL;
3157
3158 init_err_disable:
3159
3160         return rc;
3161 }
3162
3163
3164 #define ALLOW_FUNC(x)   \
3165         { \
3166                 typeof(x) arg = (x); \
3167                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3168                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3169         }
3170 static int
3171 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3172 {
3173         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3174         char mz_name[RTE_MEMZONE_NAMESIZE];
3175         const struct rte_memzone *mz = NULL;
3176         static int version_printed;
3177         uint32_t total_alloc_len;
3178         rte_iova_t mz_phys_addr;
3179         struct bnxt *bp;
3180         int rc;
3181
3182         if (version_printed++ == 0)
3183                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3184
3185         rte_eth_copy_pci_info(eth_dev, pci_dev);
3186
3187         bp = eth_dev->data->dev_private;
3188
3189         bp->dev_stopped = 1;
3190
3191         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3192                 goto skip_init;
3193
3194         if (bnxt_vf_pciid(pci_dev->id.device_id))
3195                 bp->flags |= BNXT_FLAG_VF;
3196
3197         rc = bnxt_init_board(eth_dev);
3198         if (rc) {
3199                 PMD_DRV_LOG(ERR,
3200                         "Board initialization failed rc: %x\n", rc);
3201                 goto error;
3202         }
3203 skip_init:
3204         eth_dev->dev_ops = &bnxt_dev_ops;
3205         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3206         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3207         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3208                 return 0;
3209
3210         if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3211                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3212                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3213                          pci_dev->addr.bus, pci_dev->addr.devid,
3214                          pci_dev->addr.function, "rx_port_stats");
3215                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3216                 mz = rte_memzone_lookup(mz_name);
3217                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3218                                         sizeof(struct rx_port_stats) +
3219                                         sizeof(struct rx_port_stats_ext) +
3220                                         512);
3221                 if (!mz) {
3222                         mz = rte_memzone_reserve(mz_name, total_alloc_len,
3223                                         SOCKET_ID_ANY,
3224                                         RTE_MEMZONE_2MB |
3225                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3226                                         RTE_MEMZONE_IOVA_CONTIG);
3227                         if (mz == NULL)
3228                                 return -ENOMEM;
3229                 }
3230                 memset(mz->addr, 0, mz->len);
3231                 mz_phys_addr = mz->iova;
3232                 if ((unsigned long)mz->addr == mz_phys_addr) {
3233                         PMD_DRV_LOG(WARNING,
3234                                 "Memzone physical address same as virtual.\n");
3235                         PMD_DRV_LOG(WARNING,
3236                                 "Using rte_mem_virt2iova()\n");
3237                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3238                         if (mz_phys_addr == 0) {
3239                                 PMD_DRV_LOG(ERR,
3240                                 "unable to map address to physical memory\n");
3241                                 return -ENOMEM;
3242                         }
3243                 }
3244
3245                 bp->rx_mem_zone = (const void *)mz;
3246                 bp->hw_rx_port_stats = mz->addr;
3247                 bp->hw_rx_port_stats_map = mz_phys_addr;
3248
3249                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3250                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3251                          pci_dev->addr.bus, pci_dev->addr.devid,
3252                          pci_dev->addr.function, "tx_port_stats");
3253                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3254                 mz = rte_memzone_lookup(mz_name);
3255                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3256                                         sizeof(struct tx_port_stats) +
3257                                         sizeof(struct tx_port_stats_ext) +
3258                                         512);
3259                 if (!mz) {
3260                         mz = rte_memzone_reserve(mz_name,
3261                                         total_alloc_len,
3262                                         SOCKET_ID_ANY,
3263                                         RTE_MEMZONE_2MB |
3264                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3265                                         RTE_MEMZONE_IOVA_CONTIG);
3266                         if (mz == NULL)
3267                                 return -ENOMEM;
3268                 }
3269                 memset(mz->addr, 0, mz->len);
3270                 mz_phys_addr = mz->iova;
3271                 if ((unsigned long)mz->addr == mz_phys_addr) {
3272                         PMD_DRV_LOG(WARNING,
3273                                 "Memzone physical address same as virtual.\n");
3274                         PMD_DRV_LOG(WARNING,
3275                                 "Using rte_mem_virt2iova()\n");
3276                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3277                         if (mz_phys_addr == 0) {
3278                                 PMD_DRV_LOG(ERR,
3279                                 "unable to map address to physical memory\n");
3280                                 return -ENOMEM;
3281                         }
3282                 }
3283
3284                 bp->tx_mem_zone = (const void *)mz;
3285                 bp->hw_tx_port_stats = mz->addr;
3286                 bp->hw_tx_port_stats_map = mz_phys_addr;
3287
3288                 bp->flags |= BNXT_FLAG_PORT_STATS;
3289
3290                 /* Display extended statistics if FW supports it */
3291                 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3292                     bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0)
3293                         goto skip_ext_stats;
3294
3295                 bp->hw_rx_port_stats_ext = (void *)
3296                         (bp->hw_rx_port_stats + sizeof(struct rx_port_stats));
3297                 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3298                         sizeof(struct rx_port_stats);
3299                 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3300
3301
3302                 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2) {
3303                         bp->hw_tx_port_stats_ext = (void *)
3304                         (bp->hw_tx_port_stats + sizeof(struct tx_port_stats));
3305                         bp->hw_tx_port_stats_ext_map =
3306                                 bp->hw_tx_port_stats_map +
3307                                 sizeof(struct tx_port_stats);
3308                         bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3309                 }
3310         }
3311
3312 skip_ext_stats:
3313         rc = bnxt_alloc_hwrm_resources(bp);
3314         if (rc) {
3315                 PMD_DRV_LOG(ERR,
3316                         "hwrm resource allocation failure rc: %x\n", rc);
3317                 goto error_free;
3318         }
3319         rc = bnxt_hwrm_ver_get(bp);
3320         if (rc)
3321                 goto error_free;
3322         rc = bnxt_hwrm_queue_qportcfg(bp);
3323         if (rc) {
3324                 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3325                 goto error_free;
3326         }
3327
3328         rc = bnxt_hwrm_func_qcfg(bp);
3329         if (rc) {
3330                 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3331                 goto error_free;
3332         }
3333
3334         /* Get the MAX capabilities for this function */
3335         rc = bnxt_hwrm_func_qcaps(bp);
3336         if (rc) {
3337                 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3338                 goto error_free;
3339         }
3340         if (bp->max_tx_rings == 0) {
3341                 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3342                 rc = -EBUSY;
3343                 goto error_free;
3344         }
3345         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3346                                         ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3347         if (eth_dev->data->mac_addrs == NULL) {
3348                 PMD_DRV_LOG(ERR,
3349                         "Failed to alloc %u bytes needed to store MAC addr tbl",
3350                         ETHER_ADDR_LEN * bp->max_l2_ctx);
3351                 rc = -ENOMEM;
3352                 goto error_free;
3353         }
3354
3355         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, ETHER_ADDR_LEN)) {
3356                 PMD_DRV_LOG(ERR,
3357                             "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3358                             bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3359                             bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3360                             bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3361                 rc = -EINVAL;
3362                 goto error_free;
3363         }
3364         /* Copy the permanent MAC from the qcap response address now. */
3365         memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3366         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
3367
3368         if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3369                 /* 1 ring is for default completion ring */
3370                 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3371                 rc = -ENOSPC;
3372                 goto error_free;
3373         }
3374
3375         bp->grp_info = rte_zmalloc("bnxt_grp_info",
3376                                 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3377         if (!bp->grp_info) {
3378                 PMD_DRV_LOG(ERR,
3379                         "Failed to alloc %zu bytes to store group info table\n",
3380                         sizeof(*bp->grp_info) * bp->max_ring_grps);
3381                 rc = -ENOMEM;
3382                 goto error_free;
3383         }
3384
3385         /* Forward all requests if firmware is new enough */
3386         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3387             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3388             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3389                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3390         } else {
3391                 PMD_DRV_LOG(WARNING,
3392                         "Firmware too old for VF mailbox functionality\n");
3393                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3394         }
3395
3396         /*
3397          * The following are used for driver cleanup.  If we disallow these,
3398          * VF drivers can't clean up cleanly.
3399          */
3400         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3401         ALLOW_FUNC(HWRM_VNIC_FREE);
3402         ALLOW_FUNC(HWRM_RING_FREE);
3403         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3404         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3405         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3406         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3407         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3408         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3409         rc = bnxt_hwrm_func_driver_register(bp);
3410         if (rc) {
3411                 PMD_DRV_LOG(ERR,
3412                         "Failed to register driver");
3413                 rc = -EBUSY;
3414                 goto error_free;
3415         }
3416
3417         PMD_DRV_LOG(INFO,
3418                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3419                 pci_dev->mem_resource[0].phys_addr,
3420                 pci_dev->mem_resource[0].addr);
3421
3422         rc = bnxt_hwrm_func_reset(bp);
3423         if (rc) {
3424                 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3425                 rc = -EIO;
3426                 goto error_free;
3427         }
3428
3429         if (BNXT_PF(bp)) {
3430                 //if (bp->pf.active_vfs) {
3431                         // TODO: Deallocate VF resources?
3432                 //}
3433                 if (bp->pdev->max_vfs) {
3434                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3435                         if (rc) {
3436                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3437                                 goto error_free;
3438                         }
3439                 } else {
3440                         rc = bnxt_hwrm_allocate_pf_only(bp);
3441                         if (rc) {
3442                                 PMD_DRV_LOG(ERR,
3443                                         "Failed to allocate PF resources\n");
3444                                 goto error_free;
3445                         }
3446                 }
3447         }
3448
3449         bnxt_hwrm_port_led_qcaps(bp);
3450
3451         rc = bnxt_setup_int(bp);
3452         if (rc)
3453                 goto error_free;
3454
3455         rc = bnxt_alloc_mem(bp);
3456         if (rc)
3457                 goto error_free_int;
3458
3459         rc = bnxt_request_int(bp);
3460         if (rc)
3461                 goto error_free_int;
3462
3463         bnxt_enable_int(bp);
3464         bnxt_init_nic(bp);
3465
3466         return 0;
3467
3468 error_free_int:
3469         bnxt_disable_int(bp);
3470         bnxt_hwrm_func_buf_unrgtr(bp);
3471         bnxt_free_int(bp);
3472         bnxt_free_mem(bp);
3473 error_free:
3474         bnxt_dev_uninit(eth_dev);
3475 error:
3476         return rc;
3477 }
3478
3479 static int
3480 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3481 {
3482         struct bnxt *bp = eth_dev->data->dev_private;
3483         int rc;
3484
3485         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3486                 return -EPERM;
3487
3488         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
3489         bnxt_disable_int(bp);
3490         bnxt_free_int(bp);
3491         bnxt_free_mem(bp);
3492         if (eth_dev->data->mac_addrs != NULL) {
3493                 rte_free(eth_dev->data->mac_addrs);
3494                 eth_dev->data->mac_addrs = NULL;
3495         }
3496         if (bp->grp_info != NULL) {
3497                 rte_free(bp->grp_info);
3498                 bp->grp_info = NULL;
3499         }
3500         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3501         bnxt_free_hwrm_resources(bp);
3502
3503         if (bp->tx_mem_zone) {
3504                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3505                 bp->tx_mem_zone = NULL;
3506         }
3507
3508         if (bp->rx_mem_zone) {
3509                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3510                 bp->rx_mem_zone = NULL;
3511         }
3512
3513         if (bp->dev_stopped == 0)
3514                 bnxt_dev_close_op(eth_dev);
3515         if (bp->pf.vf_info)
3516                 rte_free(bp->pf.vf_info);
3517         eth_dev->dev_ops = NULL;
3518         eth_dev->rx_pkt_burst = NULL;
3519         eth_dev->tx_pkt_burst = NULL;
3520
3521         return rc;
3522 }
3523
3524 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3525         struct rte_pci_device *pci_dev)
3526 {
3527         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3528                 bnxt_dev_init);
3529 }
3530
3531 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3532 {
3533         return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
3534 }
3535
3536 static struct rte_pci_driver bnxt_rte_pmd = {
3537         .id_table = bnxt_pci_id_map,
3538         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3539                 RTE_PCI_DRV_INTR_LSC,
3540         .probe = bnxt_pci_probe,
3541         .remove = bnxt_pci_remove,
3542 };
3543
3544 static bool
3545 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3546 {
3547         if (strcmp(dev->device->driver->name, drv->driver.name))
3548                 return false;
3549
3550         return true;
3551 }
3552
3553 bool is_bnxt_supported(struct rte_eth_dev *dev)
3554 {
3555         return is_device_supported(dev, &bnxt_rte_pmd);
3556 }
3557
3558 RTE_INIT(bnxt_init_log)
3559 {
3560         bnxt_logtype_driver = rte_log_register("pmd.bnxt.driver");
3561         if (bnxt_logtype_driver >= 0)
3562                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_INFO);
3563 }
3564
3565 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3566 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3567 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");