drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 /*
  37  * The set of PCI devices this driver supports
  38  */
  39 static const struct rte_pci_id bnxt_pci_id_map[] = {
  40         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  41                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  93         { .vendor_id = 0, /* sentinel */ },
  94 };
  95
  96 #define BNXT_ETH_RSS_SUPPORT (  \
  97         ETH_RSS_IPV4 |          \
  98         ETH_RSS_NONFRAG_IPV4_TCP |      \
  99         ETH_RSS_NONFRAG_IPV4_UDP |      \
 100         ETH_RSS_IPV6 |          \
 101         ETH_RSS_NONFRAG_IPV6_TCP |      \
 102         ETH_RSS_NONFRAG_IPV6_UDP)
 103
 104 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 105                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 106                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 108                                      DEV_TX_OFFLOAD_TCP_TSO | \
 109                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 110                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 114                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 115                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 116
 117 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 118                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 119                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 120                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 122                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 123                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 124                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 125                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 126                                      DEV_RX_OFFLOAD_TCP_LRO | \
 127                                      DEV_RX_OFFLOAD_SCATTER | \
 128                                      DEV_RX_OFFLOAD_RSS_HASH)
 129
 130 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
 131 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 132 static const char *const bnxt_dev_args[] = {
 133         BNXT_DEVARG_TRUFLOW,
 134         BNXT_DEVARG_FLOW_XSTAT,
 135         NULL
 136 };
 137
 138 /*
 139  * truflow == false to disable the feature
 140  * truflow == true to enable the feature
 141  */
 142 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 143
 144 /*
 145  * flow_xstat == false to disable the feature
 146  * flow_xstat == true to enable the feature
 147  */
 148 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 149
 150 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 151 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 152 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 153 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 154 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 155 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 156 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 157 static void bnxt_dev_recover(void *arg);
 158 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 159
 160 int is_bnxt_in_error(struct bnxt *bp)
 161 {
 162         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 163                 return -EIO;
 164         if (bp->flags & BNXT_FLAG_FW_RESET)
 165                 return -EBUSY;
 166
 167         return 0;
 168 }
 169
 170 /***********************/
 171
 172 /*
 173  * High level utility functions
 174  */
 175
 176 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 177 {
 178         if (!BNXT_CHIP_THOR(bp))
 179                 return 1;
 180
 181         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 182                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 183                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 184 }
 185
 186 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 187 {
 188         if (!BNXT_CHIP_THOR(bp))
 189                 return HW_HASH_INDEX_SIZE;
 190
 191         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 192 }
 193
 194 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 195 {
 196         bnxt_free_filter_mem(bp);
 197         bnxt_free_vnic_attributes(bp);
 198         bnxt_free_vnic_mem(bp);
 199
 200         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 201          * If the number of rings change across fw update,
 202          * we don't have much choice except to warn the user.
 203          */
 204         if (!reconfig) {
 205                 bnxt_free_stats(bp);
 206                 bnxt_free_tx_rings(bp);
 207                 bnxt_free_rx_rings(bp);
 208         }
 209         bnxt_free_async_cp_ring(bp);
 210         bnxt_free_rxtx_nq_ring(bp);
 211
 212         rte_free(bp->grp_info);
 213         bp->grp_info = NULL;
 214 }
 215
 216 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 217 {
 218         int rc;
 219
 220         rc = bnxt_alloc_ring_grps(bp);
 221         if (rc)
 222                 goto alloc_mem_err;
 223
 224         rc = bnxt_alloc_async_ring_struct(bp);
 225         if (rc)
 226                 goto alloc_mem_err;
 227
 228         rc = bnxt_alloc_vnic_mem(bp);
 229         if (rc)
 230                 goto alloc_mem_err;
 231
 232         rc = bnxt_alloc_vnic_attributes(bp);
 233         if (rc)
 234                 goto alloc_mem_err;
 235
 236         rc = bnxt_alloc_filter_mem(bp);
 237         if (rc)
 238                 goto alloc_mem_err;
 239
 240         rc = bnxt_alloc_async_cp_ring(bp);
 241         if (rc)
 242                 goto alloc_mem_err;
 243
 244         rc = bnxt_alloc_rxtx_nq_ring(bp);
 245         if (rc)
 246                 goto alloc_mem_err;
 247
 248         return 0;
 249
 250 alloc_mem_err:
 251         bnxt_free_mem(bp, reconfig);
 252         return rc;
 253 }
 254
 255 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 256 {
 257         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 258         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 259         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 260         struct bnxt_rx_queue *rxq;
 261         unsigned int j;
 262         int rc;
 263
 264         rc = bnxt_vnic_grp_alloc(bp, vnic);
 265         if (rc)
 266                 goto err_out;
 267
 268         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 269                     vnic_id, vnic, vnic->fw_grp_ids);
 270
 271         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 272         if (rc)
 273                 goto err_out;
 274
 275         /* Alloc RSS context only if RSS mode is enabled */
 276         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 277                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 278
 279                 rc = 0;
 280                 for (j = 0; j < nr_ctxs; j++) {
 281                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 282                         if (rc)
 283                                 break;
 284                 }
 285                 if (rc) {
 286                         PMD_DRV_LOG(ERR,
 287                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 288                                     vnic_id, j, rc);
 289                         goto err_out;
 290                 }
 291                 vnic->num_lb_ctxts = nr_ctxs;
 292         }
 293
 294         /*
 295          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 296          * setting is not available at this time, it will not be
 297          * configured correctly in the CFA.
 298          */
 299         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 300                 vnic->vlan_strip = true;
 301         else
 302                 vnic->vlan_strip = false;
 303
 304         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 305         if (rc)
 306                 goto err_out;
 307
 308         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 309         if (rc)
 310                 goto err_out;
 311
 312         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 313                 rxq = bp->eth_dev->data->rx_queues[j];
 314
 315                 PMD_DRV_LOG(DEBUG,
 316                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 317                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 318
 319                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 320                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 321                 else
 322                         vnic->rx_queue_cnt++;
 323         }
 324
 325         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 326
 327         rc = bnxt_vnic_rss_configure(bp, vnic);
 328         if (rc)
 329                 goto err_out;
 330
 331         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 332
 333         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 334                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 335         else
 336                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 337
 338         return 0;
 339 err_out:
 340         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 341                     vnic_id, rc);
 342         return rc;
 343 }
 344
 345 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 346 {
 347         int rc = 0;
 348
 349         rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_in_tbl.dma,
 350                                 &bp->rx_fc_in_tbl.ctx_id);
 351         if (rc)
 352                 return rc;
 353
 354         PMD_DRV_LOG(DEBUG,
 355                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 356                     " rx_fc_in_tbl.ctx_id = %d\n",
 357                     bp->rx_fc_in_tbl.va,
 358                     (void *)((uintptr_t)bp->rx_fc_in_tbl.dma),
 359                     bp->rx_fc_in_tbl.ctx_id);
 360
 361         rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_out_tbl.dma,
 362                                 &bp->rx_fc_out_tbl.ctx_id);
 363         if (rc)
 364                 return rc;
 365
 366         PMD_DRV_LOG(DEBUG,
 367                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 368                     " rx_fc_out_tbl.ctx_id = %d\n",
 369                     bp->rx_fc_out_tbl.va,
 370                     (void *)((uintptr_t)bp->rx_fc_out_tbl.dma),
 371                     bp->rx_fc_out_tbl.ctx_id);
 372
 373         rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_in_tbl.dma,
 374                                 &bp->tx_fc_in_tbl.ctx_id);
 375         if (rc)
 376                 return rc;
 377
 378         PMD_DRV_LOG(DEBUG,
 379                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 380                     " tx_fc_in_tbl.ctx_id = %d\n",
 381                     bp->tx_fc_in_tbl.va,
 382                     (void *)((uintptr_t)bp->tx_fc_in_tbl.dma),
 383                     bp->tx_fc_in_tbl.ctx_id);
 384
 385         rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_out_tbl.dma,
 386                                 &bp->tx_fc_out_tbl.ctx_id);
 387         if (rc)
 388                 return rc;
 389
 390         PMD_DRV_LOG(DEBUG,
 391                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 392                     " tx_fc_out_tbl.ctx_id = %d\n",
 393                     bp->tx_fc_out_tbl.va,
 394                     (void *)((uintptr_t)bp->tx_fc_out_tbl.dma),
 395                     bp->tx_fc_out_tbl.ctx_id);
 396
 397         memset(bp->rx_fc_out_tbl.va, 0, bp->rx_fc_out_tbl.size);
 398         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 399                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 400                                        bp->rx_fc_out_tbl.ctx_id,
 401                                        bp->max_fc,
 402                                        true);
 403         if (rc)
 404                 return rc;
 405
 406         memset(bp->tx_fc_out_tbl.va, 0, bp->tx_fc_out_tbl.size);
 407         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 408                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 409                                        bp->tx_fc_out_tbl.ctx_id,
 410                                        bp->max_fc,
 411                                        true);
 412
 413         return rc;
 414 }
 415
 416 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 417                                   struct bnxt_ctx_mem_buf_info *ctx)
 418 {
 419         if (!ctx)
 420                 return -EINVAL;
 421
 422         ctx->va = rte_zmalloc(type, size, 0);
 423         if (ctx->va == NULL)
 424                 return -ENOMEM;
 425         rte_mem_lock_page(ctx->va);
 426         ctx->size = size;
 427         ctx->dma = rte_mem_virt2iova(ctx->va);
 428         if (ctx->dma == RTE_BAD_IOVA)
 429                 return -ENOMEM;
 430
 431         return 0;
 432 }
 433
 434 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 435 {
 436         struct rte_pci_device *pdev = bp->pdev;
 437         char type[RTE_MEMZONE_NAMESIZE];
 438         uint16_t max_fc;
 439         int rc = 0;
 440
 441         max_fc = bp->max_fc;
 442
 443         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 444                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 445         /* 4 bytes for each counter-id */
 446         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->rx_fc_in_tbl);
 447         if (rc)
 448                 return rc;
 449
 450         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 451                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 452         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 453         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->rx_fc_out_tbl);
 454         if (rc)
 455                 return rc;
 456
 457         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 458                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 459         /* 4 bytes for each counter-id */
 460         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->tx_fc_in_tbl);
 461         if (rc)
 462                 return rc;
 463
 464         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 465                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 466         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 467         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->tx_fc_out_tbl);
 468         if (rc)
 469                 return rc;
 470
 471         rc = bnxt_register_fc_ctx_mem(bp);
 472
 473         return rc;
 474 }
 475
 476 static int bnxt_init_ctx_mem(struct bnxt *bp)
 477 {
 478         int rc = 0;
 479
 480         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 481             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
 482                 return 0;
 483
 484         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->max_fc);
 485         if (rc)
 486                 return rc;
 487
 488         rc = bnxt_init_fc_ctx_mem(bp);
 489
 490         return rc;
 491 }
 492
 493 static int bnxt_init_chip(struct bnxt *bp)
 494 {
 495         struct rte_eth_link new;
 496         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 497         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 498         uint32_t intr_vector = 0;
 499         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 500         uint32_t vec = BNXT_MISC_VEC_ID;
 501         unsigned int i, j;
 502         int rc;
 503
 504         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 505                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 506                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 507                 bp->flags |= BNXT_FLAG_JUMBO;
 508         } else {
 509                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 510                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 511                 bp->flags &= ~BNXT_FLAG_JUMBO;
 512         }
 513
 514         /* THOR does not support ring groups.
 515          * But we will use the array to save RSS context IDs.
 516          */
 517         if (BNXT_CHIP_THOR(bp))
 518                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 519
 520         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 521         if (rc) {
 522                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 523                 goto err_out;
 524         }
 525
 526         rc = bnxt_alloc_hwrm_rings(bp);
 527         if (rc) {
 528                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 529                 goto err_out;
 530         }
 531
 532         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 533         if (rc) {
 534                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 535                 goto err_out;
 536         }
 537
 538         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 539                 goto skip_cosq_cfg;
 540
 541         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 542                 if (bp->rx_cos_queue[i].id != 0xff) {
 543                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 544
 545                         if (!vnic) {
 546                                 PMD_DRV_LOG(ERR,
 547                                             "Num pools more than FW profile\n");
 548                                 rc = -EINVAL;
 549                                 goto err_out;
 550                         }
 551                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 552                         bp->rx_cosq_cnt++;
 553                 }
 554         }
 555
 556 skip_cosq_cfg:
 557         rc = bnxt_mq_rx_configure(bp);
 558         if (rc) {
 559                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 560                 goto err_out;
 561         }
 562
 563         /* VNIC configuration */
 564         for (i = 0; i < bp->nr_vnics; i++) {
 565                 rc = bnxt_setup_one_vnic(bp, i);
 566                 if (rc)
 567                         goto err_out;
 568         }
 569
 570         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 571         if (rc) {
 572                 PMD_DRV_LOG(ERR,
 573                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 574                 goto err_out;
 575         }
 576
 577         /* check and configure queue intr-vector mapping */
 578         if ((rte_intr_cap_multiple(intr_handle) ||
 579              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 580             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 581                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 582                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 583                 if (intr_vector > bp->rx_cp_nr_rings) {
 584                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 585                                         bp->rx_cp_nr_rings);
 586                         return -ENOTSUP;
 587                 }
 588                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 589                 if (rc)
 590                         return rc;
 591         }
 592
 593         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 594                 intr_handle->intr_vec =
 595                         rte_zmalloc("intr_vec",
 596                                     bp->eth_dev->data->nb_rx_queues *
 597                                     sizeof(int), 0);
 598                 if (intr_handle->intr_vec == NULL) {
 599                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 600                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 601                         rc = -ENOMEM;
 602                         goto err_disable;
 603                 }
 604                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 605                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 606                          intr_handle->intr_vec, intr_handle->nb_efd,
 607                         intr_handle->max_intr);
 608                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 609                      queue_id++) {
 610                         intr_handle->intr_vec[queue_id] =
 611                                                         vec + BNXT_RX_VEC_START;
 612                         if (vec < base + intr_handle->nb_efd - 1)
 613                                 vec++;
 614                 }
 615         }
 616
 617         /* enable uio/vfio intr/eventfd mapping */
 618         rc = rte_intr_enable(intr_handle);
 619 #ifndef RTE_EXEC_ENV_FREEBSD
 620         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 621         if (rc)
 622                 goto err_free;
 623 #endif
 624
 625         rc = bnxt_get_hwrm_link_config(bp, &new);
 626         if (rc) {
 627                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 628                 goto err_free;
 629         }
 630
 631         if (!bp->link_info.link_up) {
 632                 rc = bnxt_set_hwrm_link_config(bp, true);
 633                 if (rc) {
 634                         PMD_DRV_LOG(ERR,
 635                                 "HWRM link config failure rc: %x\n", rc);
 636                         goto err_free;
 637                 }
 638         }
 639         bnxt_print_link_info(bp->eth_dev);
 640
 641         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 642         if (!bp->mark_table)
 643                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 644
 645         return 0;
 646
 647 err_free:
 648         rte_free(intr_handle->intr_vec);
 649 err_disable:
 650         rte_intr_efd_disable(intr_handle);
 651 err_out:
 652         /* Some of the error status returned by FW may not be from errno.h */
 653         if (rc > 0)
 654                 rc = -EIO;
 655
 656         return rc;
 657 }
 658
 659 static int bnxt_shutdown_nic(struct bnxt *bp)
 660 {
 661         bnxt_free_all_hwrm_resources(bp);
 662         bnxt_free_all_filters(bp);
 663         bnxt_free_all_vnics(bp);
 664         return 0;
 665 }
 666
 667 /*
 668  * Device configuration and status function
 669  */
 670
 671 static uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 672 {
 673         uint32_t link_speed = bp->link_info.support_speeds;
 674         uint32_t speed_capa = 0;
 675
 676         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 677                 speed_capa |= ETH_LINK_SPEED_100M;
 678         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 679                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 680         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 681                 speed_capa |= ETH_LINK_SPEED_1G;
 682         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 683                 speed_capa |= ETH_LINK_SPEED_2_5G;
 684         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 685                 speed_capa |= ETH_LINK_SPEED_10G;
 686         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 687                 speed_capa |= ETH_LINK_SPEED_20G;
 688         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 689                 speed_capa |= ETH_LINK_SPEED_25G;
 690         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 691                 speed_capa |= ETH_LINK_SPEED_40G;
 692         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 693                 speed_capa |= ETH_LINK_SPEED_50G;
 694         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 695                 speed_capa |= ETH_LINK_SPEED_100G;
 696
 697         if (bp->link_info.auto_mode == HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 698                 speed_capa |= ETH_LINK_SPEED_FIXED;
 699         else
 700                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 701
 702         return speed_capa;
 703 }
 704
 705 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 706                                 struct rte_eth_dev_info *dev_info)
 707 {
 708         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 709         struct bnxt *bp = eth_dev->data->dev_private;
 710         uint16_t max_vnics, i, j, vpool, vrxq;
 711         unsigned int max_rx_rings;
 712         int rc;
 713
 714         rc = is_bnxt_in_error(bp);
 715         if (rc)
 716                 return rc;
 717
 718         /* MAC Specifics */
 719         dev_info->max_mac_addrs = bp->max_l2_ctx;
 720         dev_info->max_hash_mac_addrs = 0;
 721
 722         /* PF/VF specifics */
 723         if (BNXT_PF(bp))
 724                 dev_info->max_vfs = pdev->max_vfs;
 725
 726         max_rx_rings = BNXT_MAX_RINGS(bp);
 727         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 728         dev_info->max_rx_queues = max_rx_rings;
 729         dev_info->max_tx_queues = max_rx_rings;
 730         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 731         dev_info->hash_key_size = 40;
 732         max_vnics = bp->max_vnics;
 733
 734         /* MTU specifics */
 735         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 736         dev_info->max_mtu = BNXT_MAX_MTU;
 737
 738         /* Fast path specifics */
 739         dev_info->min_rx_bufsize = 1;
 740         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 741
 742         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 743         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 744                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 745         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 746         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 747
 748         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 749
 750         /* *INDENT-OFF* */
 751         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 752                 .rx_thresh = {
 753                         .pthresh = 8,
 754                         .hthresh = 8,
 755                         .wthresh = 0,
 756                 },
 757                 .rx_free_thresh = 32,
 758                 /* If no descriptors available, pkts are dropped by default */
 759                 .rx_drop_en = 1,
 760         };
 761
 762         dev_info->default_txconf = (struct rte_eth_txconf) {
 763                 .tx_thresh = {
 764                         .pthresh = 32,
 765                         .hthresh = 0,
 766                         .wthresh = 0,
 767                 },
 768                 .tx_free_thresh = 32,
 769                 .tx_rs_thresh = 32,
 770         };
 771         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 772
 773         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 774         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 775         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 776         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 777         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 778
 779         /* *INDENT-ON* */
 780
 781         /*
 782          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 783          *       need further investigation.
 784          */
 785
 786         /* VMDq resources */
 787         vpool = 64; /* ETH_64_POOLS */
 788         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 789         for (i = 0; i < 4; vpool >>= 1, i++) {
 790                 if (max_vnics > vpool) {
 791                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 792                                 if (dev_info->max_rx_queues > vrxq) {
 793                                         if (vpool > vrxq)
 794                                                 vpool = vrxq;
 795                                         goto found;
 796                                 }
 797                         }
 798                         /* Not enough resources to support VMDq */
 799                         break;
 800                 }
 801         }
 802         /* Not enough resources to support VMDq */
 803         vpool = 0;
 804         vrxq = 0;
 805 found:
 806         dev_info->max_vmdq_pools = vpool;
 807         dev_info->vmdq_queue_num = vrxq;
 808
 809         dev_info->vmdq_pool_base = 0;
 810         dev_info->vmdq_queue_base = 0;
 811
 812         return 0;
 813 }
 814
 815 /* Configure the device based on the configuration provided */
 816 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 817 {
 818         struct bnxt *bp = eth_dev->data->dev_private;
 819         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 820         int rc;
 821
 822         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 823         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 824         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 825         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 826
 827         rc = is_bnxt_in_error(bp);
 828         if (rc)
 829                 return rc;
 830
 831         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 832                 rc = bnxt_hwrm_check_vf_rings(bp);
 833                 if (rc) {
 834                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 835                         return -ENOSPC;
 836                 }
 837
 838                 /* If a resource has already been allocated - in this case
 839                  * it is the async completion ring, free it. Reallocate it after
 840                  * resource reservation. This will ensure the resource counts
 841                  * are calculated correctly.
 842                  */
 843
 844                 pthread_mutex_lock(&bp->def_cp_lock);
 845
 846                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 847                         bnxt_disable_int(bp);
 848                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 849                 }
 850
 851                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 852                 if (rc) {
 853                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 854                         pthread_mutex_unlock(&bp->def_cp_lock);
 855                         return -ENOSPC;
 856                 }
 857
 858                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 859                         rc = bnxt_alloc_async_cp_ring(bp);
 860                         if (rc) {
 861                                 pthread_mutex_unlock(&bp->def_cp_lock);
 862                                 return rc;
 863                         }
 864                         bnxt_enable_int(bp);
 865                 }
 866
 867                 pthread_mutex_unlock(&bp->def_cp_lock);
 868         } else {
 869                 /* legacy driver needs to get updated values */
 870                 rc = bnxt_hwrm_func_qcaps(bp);
 871                 if (rc) {
 872                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 873                         return rc;
 874                 }
 875         }
 876
 877         /* Inherit new configurations */
 878         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 879             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 880             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 881                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 882             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 883             bp->max_stat_ctx)
 884                 goto resource_error;
 885
 886         if (BNXT_HAS_RING_GRPS(bp) &&
 887             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 888                 goto resource_error;
 889
 890         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 891             bp->max_vnics < eth_dev->data->nb_rx_queues)
 892                 goto resource_error;
 893
 894         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 895         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 896
 897         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 898                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 899         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
 900
 901         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 902                 eth_dev->data->mtu =
 903                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 904                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 905                         BNXT_NUM_VLANS;
 906                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 907         }
 908         return 0;
 909
 910 resource_error:
 911         PMD_DRV_LOG(ERR,
 912                     "Insufficient resources to support requested config\n");
 913         PMD_DRV_LOG(ERR,
 914                     "Num Queues Requested: Tx %d, Rx %d\n",
 915                     eth_dev->data->nb_tx_queues,
 916                     eth_dev->data->nb_rx_queues);
 917         PMD_DRV_LOG(ERR,
 918                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 919                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 920                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 921         return -ENOSPC;
 922 }
 923
 924 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 925 {
 926         struct rte_eth_link *link = &eth_dev->data->dev_link;
 927
 928         if (link->link_status)
 929                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 930                         eth_dev->data->port_id,
 931                         (uint32_t)link->link_speed,
 932                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 933                         ("full-duplex") : ("half-duplex\n"));
 934         else
 935                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 936                         eth_dev->data->port_id);
 937 }
 938
 939 /*
 940  * Determine whether the current configuration requires support for scattered
 941  * receive; return 1 if scattered receive is required and 0 if not.
 942  */
 943 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 944 {
 945         uint16_t buf_size;
 946         int i;
 947
 948         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 949                 return 1;
 950
 951         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 952                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 953
 954                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 955                                       RTE_PKTMBUF_HEADROOM);
 956                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 957                         return 1;
 958         }
 959         return 0;
 960 }
 961
 962 static eth_rx_burst_t
 963 bnxt_receive_function(struct rte_eth_dev *eth_dev)
 964 {
 965         struct bnxt *bp = eth_dev->data->dev_private;
 966
 967 #ifdef RTE_ARCH_X86
 968 #ifndef RTE_LIBRTE_IEEE1588
 969         /*
 970          * Vector mode receive can be enabled only if scatter rx is not
 971          * in use and rx offloads are limited to VLAN stripping and
 972          * CRC stripping.
 973          */
 974         if (!eth_dev->data->scattered_rx &&
 975             !(eth_dev->data->dev_conf.rxmode.offloads &
 976               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 977                 DEV_RX_OFFLOAD_KEEP_CRC |
 978                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 979                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 980                 DEV_RX_OFFLOAD_UDP_CKSUM |
 981                 DEV_RX_OFFLOAD_TCP_CKSUM |
 982                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 983                 DEV_RX_OFFLOAD_RSS_HASH |
 984                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
 985             !bp->truflow) {
 986                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 987                             eth_dev->data->port_id);
 988                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
 989                 return bnxt_recv_pkts_vec;
 990         }
 991         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 992                     eth_dev->data->port_id);
 993         PMD_DRV_LOG(INFO,
 994                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 995                     eth_dev->data->port_id,
 996                     eth_dev->data->scattered_rx,
 997                     eth_dev->data->dev_conf.rxmode.offloads);
 998 #endif
 999 #endif
1000         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1001         return bnxt_recv_pkts;
1002 }
1003
1004 static eth_tx_burst_t
1005 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1006 {
1007 #ifdef RTE_ARCH_X86
1008 #ifndef RTE_LIBRTE_IEEE1588
1009         /*
1010          * Vector mode transmit can be enabled only if not using scatter rx
1011          * or tx offloads.
1012          */
1013         if (!eth_dev->data->scattered_rx &&
1014             !eth_dev->data->dev_conf.txmode.offloads) {
1015                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1016                             eth_dev->data->port_id);
1017                 return bnxt_xmit_pkts_vec;
1018         }
1019         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1020                     eth_dev->data->port_id);
1021         PMD_DRV_LOG(INFO,
1022                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1023                     eth_dev->data->port_id,
1024                     eth_dev->data->scattered_rx,
1025                     eth_dev->data->dev_conf.txmode.offloads);
1026 #endif
1027 #endif
1028         return bnxt_xmit_pkts;
1029 }
1030
1031 static int bnxt_handle_if_change_status(struct bnxt *bp)
1032 {
1033         int rc;
1034
1035         /* Since fw has undergone a reset and lost all contexts,
1036          * set fatal flag to not issue hwrm during cleanup
1037          */
1038         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1039         bnxt_uninit_resources(bp, true);
1040
1041         /* clear fatal flag so that re-init happens */
1042         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1043         rc = bnxt_init_resources(bp, true);
1044
1045         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1046
1047         return rc;
1048 }
1049
1050 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1051 {
1052         struct bnxt *bp = eth_dev->data->dev_private;
1053         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1054         int vlan_mask = 0;
1055         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1056
1057         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1058                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1059                 return -EINVAL;
1060         }
1061
1062         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1063                 PMD_DRV_LOG(ERR,
1064                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1065                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1066         }
1067
1068         do {
1069                 rc = bnxt_hwrm_if_change(bp, true);
1070                 if (rc == 0 || rc != -EAGAIN)
1071                         break;
1072
1073                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1074         } while (retry_cnt--);
1075
1076         if (rc)
1077                 return rc;
1078
1079         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1080                 rc = bnxt_handle_if_change_status(bp);
1081                 if (rc)
1082                         return rc;
1083         }
1084
1085         bnxt_enable_int(bp);
1086
1087         rc = bnxt_init_chip(bp);
1088         if (rc)
1089                 goto error;
1090
1091         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1092         eth_dev->data->dev_started = 1;
1093
1094         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1095
1096         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1097                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1098         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1099                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1100         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1101         if (rc)
1102                 goto error;
1103
1104         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1105         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1106
1107         pthread_mutex_lock(&bp->def_cp_lock);
1108         bnxt_schedule_fw_health_check(bp);
1109         pthread_mutex_unlock(&bp->def_cp_lock);
1110
1111         if (bp->truflow)
1112                 bnxt_ulp_init(bp);
1113
1114         return 0;
1115
1116 error:
1117         bnxt_shutdown_nic(bp);
1118         bnxt_free_tx_mbufs(bp);
1119         bnxt_free_rx_mbufs(bp);
1120         bnxt_hwrm_if_change(bp, false);
1121         eth_dev->data->dev_started = 0;
1122         return rc;
1123 }
1124
1125 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1126 {
1127         struct bnxt *bp = eth_dev->data->dev_private;
1128         int rc = 0;
1129
1130         if (!bp->link_info.link_up)
1131                 rc = bnxt_set_hwrm_link_config(bp, true);
1132         if (!rc)
1133                 eth_dev->data->dev_link.link_status = 1;
1134
1135         bnxt_print_link_info(eth_dev);
1136         return rc;
1137 }
1138
1139 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1140 {
1141         struct bnxt *bp = eth_dev->data->dev_private;
1142
1143         eth_dev->data->dev_link.link_status = 0;
1144         bnxt_set_hwrm_link_config(bp, false);
1145         bp->link_info.link_up = 0;
1146
1147         return 0;
1148 }
1149
1150 /* Unload the driver, release resources */
1151 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1152 {
1153         struct bnxt *bp = eth_dev->data->dev_private;
1154         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1155         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1156
1157         if (bp->truflow)
1158                 bnxt_ulp_deinit(bp);
1159
1160         eth_dev->data->dev_started = 0;
1161         /* Prevent crashes when queues are still in use */
1162         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1163         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1164
1165         bnxt_disable_int(bp);
1166
1167         /* disable uio/vfio intr/eventfd mapping */
1168         rte_intr_disable(intr_handle);
1169
1170         bnxt_cancel_fw_health_check(bp);
1171
1172         bnxt_dev_set_link_down_op(eth_dev);
1173
1174         /* Wait for link to be reset and the async notification to process.
1175          * During reset recovery, there is no need to wait and
1176          * VF/NPAR functions do not have privilege to change PHY config.
1177          */
1178         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1179                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1180
1181         /* Clean queue intr-vector mapping */
1182         rte_intr_efd_disable(intr_handle);
1183         if (intr_handle->intr_vec != NULL) {
1184                 rte_free(intr_handle->intr_vec);
1185                 intr_handle->intr_vec = NULL;
1186         }
1187
1188         bnxt_hwrm_port_clr_stats(bp);
1189         bnxt_free_tx_mbufs(bp);
1190         bnxt_free_rx_mbufs(bp);
1191         /* Process any remaining notifications in default completion queue */
1192         bnxt_int_handler(eth_dev);
1193         bnxt_shutdown_nic(bp);
1194         bnxt_hwrm_if_change(bp, false);
1195
1196         rte_free(bp->mark_table);
1197         bp->mark_table = NULL;
1198
1199         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1200         bp->rx_cosq_cnt = 0;
1201 }
1202
1203 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1204 {
1205         struct bnxt *bp = eth_dev->data->dev_private;
1206
1207         /* cancel the recovery handler before remove dev */
1208         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1209         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1210         bnxt_cancel_fc_thread(bp);
1211
1212         if (eth_dev->data->dev_started)
1213                 bnxt_dev_stop_op(eth_dev);
1214
1215         bnxt_uninit_resources(bp, false);
1216
1217         eth_dev->dev_ops = NULL;
1218         eth_dev->rx_pkt_burst = NULL;
1219         eth_dev->tx_pkt_burst = NULL;
1220
1221         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1222         bp->tx_mem_zone = NULL;
1223         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1224         bp->rx_mem_zone = NULL;
1225
1226         rte_free(bp->pf.vf_info);
1227         bp->pf.vf_info = NULL;
1228
1229         rte_free(bp->grp_info);
1230         bp->grp_info = NULL;
1231 }
1232
1233 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1234                                     uint32_t index)
1235 {
1236         struct bnxt *bp = eth_dev->data->dev_private;
1237         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1238         struct bnxt_vnic_info *vnic;
1239         struct bnxt_filter_info *filter, *temp_filter;
1240         uint32_t i;
1241
1242         if (is_bnxt_in_error(bp))
1243                 return;
1244
1245         /*
1246          * Loop through all VNICs from the specified filter flow pools to
1247          * remove the corresponding MAC addr filter
1248          */
1249         for (i = 0; i < bp->nr_vnics; i++) {
1250                 if (!(pool_mask & (1ULL << i)))
1251                         continue;
1252
1253                 vnic = &bp->vnic_info[i];
1254                 filter = STAILQ_FIRST(&vnic->filter);
1255                 while (filter) {
1256                         temp_filter = STAILQ_NEXT(filter, next);
1257                         if (filter->mac_index == index) {
1258                                 STAILQ_REMOVE(&vnic->filter, filter,
1259                                                 bnxt_filter_info, next);
1260                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1261                                 bnxt_free_filter(bp, filter);
1262                         }
1263                         filter = temp_filter;
1264                 }
1265         }
1266 }
1267
1268 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1269                                struct rte_ether_addr *mac_addr, uint32_t index,
1270                                uint32_t pool)
1271 {
1272         struct bnxt_filter_info *filter;
1273         int rc = 0;
1274
1275         /* Attach requested MAC address to the new l2_filter */
1276         STAILQ_FOREACH(filter, &vnic->filter, next) {
1277                 if (filter->mac_index == index) {
1278                         PMD_DRV_LOG(DEBUG,
1279                                     "MAC addr already existed for pool %d\n",
1280                                     pool);
1281                         return 0;
1282                 }
1283         }
1284
1285         filter = bnxt_alloc_filter(bp);
1286         if (!filter) {
1287                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1288                 return -ENODEV;
1289         }
1290
1291         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1292          * if the MAC that's been programmed now is a different one, then,
1293          * copy that addr to filter->l2_addr
1294          */
1295         if (mac_addr)
1296                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1297         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1298
1299         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1300         if (!rc) {
1301                 filter->mac_index = index;
1302                 if (filter->mac_index == 0)
1303                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1304                 else
1305                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1306         } else {
1307                 bnxt_free_filter(bp, filter);
1308         }
1309
1310         return rc;
1311 }
1312
1313 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1314                                 struct rte_ether_addr *mac_addr,
1315                                 uint32_t index, uint32_t pool)
1316 {
1317         struct bnxt *bp = eth_dev->data->dev_private;
1318         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1319         int rc = 0;
1320
1321         rc = is_bnxt_in_error(bp);
1322         if (rc)
1323                 return rc;
1324
1325         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1326                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1327                 return -ENOTSUP;
1328         }
1329
1330         if (!vnic) {
1331                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1332                 return -EINVAL;
1333         }
1334
1335         /* Filter settings will get applied when port is started */
1336         if (!eth_dev->data->dev_started)
1337                 return 0;
1338
1339         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1340
1341         return rc;
1342 }
1343
1344 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1345                      bool exp_link_status)
1346 {
1347         int rc = 0;
1348         struct bnxt *bp = eth_dev->data->dev_private;
1349         struct rte_eth_link new;
1350         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1351                   BNXT_LINK_DOWN_WAIT_CNT;
1352
1353         rc = is_bnxt_in_error(bp);
1354         if (rc)
1355                 return rc;
1356
1357         memset(&new, 0, sizeof(new));
1358         do {
1359                 /* Retrieve link info from hardware */
1360                 rc = bnxt_get_hwrm_link_config(bp, &new);
1361                 if (rc) {
1362                         new.link_speed = ETH_LINK_SPEED_100M;
1363                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1364                         PMD_DRV_LOG(ERR,
1365                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1366                         goto out;
1367                 }
1368
1369                 if (!wait_to_complete || new.link_status == exp_link_status)
1370                         break;
1371
1372                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1373         } while (cnt--);
1374
1375 out:
1376         /* Timed out or success */
1377         if (new.link_status != eth_dev->data->dev_link.link_status ||
1378         new.link_speed != eth_dev->data->dev_link.link_speed) {
1379                 rte_eth_linkstatus_set(eth_dev, &new);
1380
1381                 _rte_eth_dev_callback_process(eth_dev,
1382                                               RTE_ETH_EVENT_INTR_LSC,
1383                                               NULL);
1384
1385                 bnxt_print_link_info(eth_dev);
1386         }
1387
1388         return rc;
1389 }
1390
1391 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1392                                int wait_to_complete)
1393 {
1394         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1395 }
1396
1397 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1398 {
1399         struct bnxt *bp = eth_dev->data->dev_private;
1400         struct bnxt_vnic_info *vnic;
1401         uint32_t old_flags;
1402         int rc;
1403
1404         rc = is_bnxt_in_error(bp);
1405         if (rc)
1406                 return rc;
1407
1408         /* Filter settings will get applied when port is started */
1409         if (!eth_dev->data->dev_started)
1410                 return 0;
1411
1412         if (bp->vnic_info == NULL)
1413                 return 0;
1414
1415         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1416
1417         old_flags = vnic->flags;
1418         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1419         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1420         if (rc != 0)
1421                 vnic->flags = old_flags;
1422
1423         return rc;
1424 }
1425
1426 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1427 {
1428         struct bnxt *bp = eth_dev->data->dev_private;
1429         struct bnxt_vnic_info *vnic;
1430         uint32_t old_flags;
1431         int rc;
1432
1433         rc = is_bnxt_in_error(bp);
1434         if (rc)
1435                 return rc;
1436
1437         /* Filter settings will get applied when port is started */
1438         if (!eth_dev->data->dev_started)
1439                 return 0;
1440
1441         if (bp->vnic_info == NULL)
1442                 return 0;
1443
1444         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1445
1446         old_flags = vnic->flags;
1447         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1448         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1449         if (rc != 0)
1450                 vnic->flags = old_flags;
1451
1452         return rc;
1453 }
1454
1455 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1456 {
1457         struct bnxt *bp = eth_dev->data->dev_private;
1458         struct bnxt_vnic_info *vnic;
1459         uint32_t old_flags;
1460         int rc;
1461
1462         rc = is_bnxt_in_error(bp);
1463         if (rc)
1464                 return rc;
1465
1466         /* Filter settings will get applied when port is started */
1467         if (!eth_dev->data->dev_started)
1468                 return 0;
1469
1470         if (bp->vnic_info == NULL)
1471                 return 0;
1472
1473         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1474
1475         old_flags = vnic->flags;
1476         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1477         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1478         if (rc != 0)
1479                 vnic->flags = old_flags;
1480
1481         return rc;
1482 }
1483
1484 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1485 {
1486         struct bnxt *bp = eth_dev->data->dev_private;
1487         struct bnxt_vnic_info *vnic;
1488         uint32_t old_flags;
1489         int rc;
1490
1491         rc = is_bnxt_in_error(bp);
1492         if (rc)
1493                 return rc;
1494
1495         /* Filter settings will get applied when port is started */
1496         if (!eth_dev->data->dev_started)
1497                 return 0;
1498
1499         if (bp->vnic_info == NULL)
1500                 return 0;
1501
1502         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1503
1504         old_flags = vnic->flags;
1505         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1506         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1507         if (rc != 0)
1508                 vnic->flags = old_flags;
1509
1510         return rc;
1511 }
1512
1513 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1514 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1515 {
1516         if (qid >= bp->rx_nr_rings)
1517                 return NULL;
1518
1519         return bp->eth_dev->data->rx_queues[qid];
1520 }
1521
1522 /* Return rxq corresponding to a given rss table ring/group ID. */
1523 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1524 {
1525         struct bnxt_rx_queue *rxq;
1526         unsigned int i;
1527
1528         if (!BNXT_HAS_RING_GRPS(bp)) {
1529                 for (i = 0; i < bp->rx_nr_rings; i++) {
1530                         rxq = bp->eth_dev->data->rx_queues[i];
1531                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1532                                 return rxq->index;
1533                 }
1534         } else {
1535                 for (i = 0; i < bp->rx_nr_rings; i++) {
1536                         if (bp->grp_info[i].fw_grp_id == fwr)
1537                                 return i;
1538                 }
1539         }
1540
1541         return INVALID_HW_RING_ID;
1542 }
1543
1544 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1545                             struct rte_eth_rss_reta_entry64 *reta_conf,
1546                             uint16_t reta_size)
1547 {
1548         struct bnxt *bp = eth_dev->data->dev_private;
1549         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1550         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1551         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1552         uint16_t idx, sft;
1553         int i, rc;
1554
1555         rc = is_bnxt_in_error(bp);
1556         if (rc)
1557                 return rc;
1558
1559         if (!vnic->rss_table)
1560                 return -EINVAL;
1561
1562         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1563                 return -EINVAL;
1564
1565         if (reta_size != tbl_size) {
1566                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1567                         "(%d) must equal the size supported by the hardware "
1568                         "(%d)\n", reta_size, tbl_size);
1569                 return -EINVAL;
1570         }
1571
1572         for (i = 0; i < reta_size; i++) {
1573                 struct bnxt_rx_queue *rxq;
1574
1575                 idx = i / RTE_RETA_GROUP_SIZE;
1576                 sft = i % RTE_RETA_GROUP_SIZE;
1577
1578                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1579                         continue;
1580
1581                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1582                 if (!rxq) {
1583                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1584                         return -EINVAL;
1585                 }
1586
1587                 if (BNXT_CHIP_THOR(bp)) {
1588                         vnic->rss_table[i * 2] =
1589                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1590                         vnic->rss_table[i * 2 + 1] =
1591                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1592                 } else {
1593                         vnic->rss_table[i] =
1594                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1595                 }
1596         }
1597
1598         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1599         return 0;
1600 }
1601
1602 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1603                               struct rte_eth_rss_reta_entry64 *reta_conf,
1604                               uint16_t reta_size)
1605 {
1606         struct bnxt *bp = eth_dev->data->dev_private;
1607         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1608         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1609         uint16_t idx, sft, i;
1610         int rc;
1611
1612         rc = is_bnxt_in_error(bp);
1613         if (rc)
1614                 return rc;
1615
1616         /* Retrieve from the default VNIC */
1617         if (!vnic)
1618                 return -EINVAL;
1619         if (!vnic->rss_table)
1620                 return -EINVAL;
1621
1622         if (reta_size != tbl_size) {
1623                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1624                         "(%d) must equal the size supported by the hardware "
1625                         "(%d)\n", reta_size, tbl_size);
1626                 return -EINVAL;
1627         }
1628
1629         for (idx = 0, i = 0; i < reta_size; i++) {
1630                 idx = i / RTE_RETA_GROUP_SIZE;
1631                 sft = i % RTE_RETA_GROUP_SIZE;
1632
1633                 if (reta_conf[idx].mask & (1ULL << sft)) {
1634                         uint16_t qid;
1635
1636                         if (BNXT_CHIP_THOR(bp))
1637                                 qid = bnxt_rss_to_qid(bp,
1638                                                       vnic->rss_table[i * 2]);
1639                         else
1640                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1641
1642                         if (qid == INVALID_HW_RING_ID) {
1643                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1644                                 return -EINVAL;
1645                         }
1646                         reta_conf[idx].reta[sft] = qid;
1647                 }
1648         }
1649
1650         return 0;
1651 }
1652
1653 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1654                                    struct rte_eth_rss_conf *rss_conf)
1655 {
1656         struct bnxt *bp = eth_dev->data->dev_private;
1657         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1658         struct bnxt_vnic_info *vnic;
1659         int rc;
1660
1661         rc = is_bnxt_in_error(bp);
1662         if (rc)
1663                 return rc;
1664
1665         /*
1666          * If RSS enablement were different than dev_configure,
1667          * then return -EINVAL
1668          */
1669         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1670                 if (!rss_conf->rss_hf)
1671                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1672         } else {
1673                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1674                         return -EINVAL;
1675         }
1676
1677         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1678         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1679
1680         /* Update the default RSS VNIC(s) */
1681         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1682         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1683
1684         /*
1685          * If hashkey is not specified, use the previously configured
1686          * hashkey
1687          */
1688         if (!rss_conf->rss_key)
1689                 goto rss_config;
1690
1691         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1692                 PMD_DRV_LOG(ERR,
1693                             "Invalid hashkey length, should be 16 bytes\n");
1694                 return -EINVAL;
1695         }
1696         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1697
1698 rss_config:
1699         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1700         return 0;
1701 }
1702
1703 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1704                                      struct rte_eth_rss_conf *rss_conf)
1705 {
1706         struct bnxt *bp = eth_dev->data->dev_private;
1707         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1708         int len, rc;
1709         uint32_t hash_types;
1710
1711         rc = is_bnxt_in_error(bp);
1712         if (rc)
1713                 return rc;
1714
1715         /* RSS configuration is the same for all VNICs */
1716         if (vnic && vnic->rss_hash_key) {
1717                 if (rss_conf->rss_key) {
1718                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1719                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1720                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1721                 }
1722
1723                 hash_types = vnic->hash_type;
1724                 rss_conf->rss_hf = 0;
1725                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1726                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1727                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1728                 }
1729                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1730                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1731                         hash_types &=
1732                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1733                 }
1734                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1735                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1736                         hash_types &=
1737                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1738                 }
1739                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1740                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1741                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1742                 }
1743                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1744                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1745                         hash_types &=
1746                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1747                 }
1748                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1749                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1750                         hash_types &=
1751                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1752                 }
1753                 if (hash_types) {
1754                         PMD_DRV_LOG(ERR,
1755                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1756                                 vnic->hash_type);
1757                         return -ENOTSUP;
1758                 }
1759         } else {
1760                 rss_conf->rss_hf = 0;
1761         }
1762         return 0;
1763 }
1764
1765 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1766                                struct rte_eth_fc_conf *fc_conf)
1767 {
1768         struct bnxt *bp = dev->data->dev_private;
1769         struct rte_eth_link link_info;
1770         int rc;
1771
1772         rc = is_bnxt_in_error(bp);
1773         if (rc)
1774                 return rc;
1775
1776         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1777         if (rc)
1778                 return rc;
1779
1780         memset(fc_conf, 0, sizeof(*fc_conf));
1781         if (bp->link_info.auto_pause)
1782                 fc_conf->autoneg = 1;
1783         switch (bp->link_info.pause) {
1784         case 0:
1785                 fc_conf->mode = RTE_FC_NONE;
1786                 break;
1787         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1788                 fc_conf->mode = RTE_FC_TX_PAUSE;
1789                 break;
1790         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1791                 fc_conf->mode = RTE_FC_RX_PAUSE;
1792                 break;
1793         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1794                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1795                 fc_conf->mode = RTE_FC_FULL;
1796                 break;
1797         }
1798         return 0;
1799 }
1800
1801 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1802                                struct rte_eth_fc_conf *fc_conf)
1803 {
1804         struct bnxt *bp = dev->data->dev_private;
1805         int rc;
1806
1807         rc = is_bnxt_in_error(bp);
1808         if (rc)
1809                 return rc;
1810
1811         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1812                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1813                 return -ENOTSUP;
1814         }
1815
1816         switch (fc_conf->mode) {
1817         case RTE_FC_NONE:
1818                 bp->link_info.auto_pause = 0;
1819                 bp->link_info.force_pause = 0;
1820                 break;
1821         case RTE_FC_RX_PAUSE:
1822                 if (fc_conf->autoneg) {
1823                         bp->link_info.auto_pause =
1824                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1825                         bp->link_info.force_pause = 0;
1826                 } else {
1827                         bp->link_info.auto_pause = 0;
1828                         bp->link_info.force_pause =
1829                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1830                 }
1831                 break;
1832         case RTE_FC_TX_PAUSE:
1833                 if (fc_conf->autoneg) {
1834                         bp->link_info.auto_pause =
1835                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1836                         bp->link_info.force_pause = 0;
1837                 } else {
1838                         bp->link_info.auto_pause = 0;
1839                         bp->link_info.force_pause =
1840                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1841                 }
1842                 break;
1843         case RTE_FC_FULL:
1844                 if (fc_conf->autoneg) {
1845                         bp->link_info.auto_pause =
1846                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1847                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1848                         bp->link_info.force_pause = 0;
1849                 } else {
1850                         bp->link_info.auto_pause = 0;
1851                         bp->link_info.force_pause =
1852                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1853                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1854                 }
1855                 break;
1856         }
1857         return bnxt_set_hwrm_link_config(bp, true);
1858 }
1859
1860 /* Add UDP tunneling port */
1861 static int
1862 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1863                          struct rte_eth_udp_tunnel *udp_tunnel)
1864 {
1865         struct bnxt *bp = eth_dev->data->dev_private;
1866         uint16_t tunnel_type = 0;
1867         int rc = 0;
1868
1869         rc = is_bnxt_in_error(bp);
1870         if (rc)
1871                 return rc;
1872
1873         switch (udp_tunnel->prot_type) {
1874         case RTE_TUNNEL_TYPE_VXLAN:
1875                 if (bp->vxlan_port_cnt) {
1876                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1877                                 udp_tunnel->udp_port);
1878                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1879                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1880                                 return -ENOSPC;
1881                         }
1882                         bp->vxlan_port_cnt++;
1883                         return 0;
1884                 }
1885                 tunnel_type =
1886                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1887                 bp->vxlan_port_cnt++;
1888                 break;
1889         case RTE_TUNNEL_TYPE_GENEVE:
1890                 if (bp->geneve_port_cnt) {
1891                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1892                                 udp_tunnel->udp_port);
1893                         if (bp->geneve_port != udp_tunnel->udp_port) {
1894                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1895                                 return -ENOSPC;
1896                         }
1897                         bp->geneve_port_cnt++;
1898                         return 0;
1899                 }
1900                 tunnel_type =
1901                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1902                 bp->geneve_port_cnt++;
1903                 break;
1904         default:
1905                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1906                 return -ENOTSUP;
1907         }
1908         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1909                                              tunnel_type);
1910         return rc;
1911 }
1912
1913 static int
1914 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1915                          struct rte_eth_udp_tunnel *udp_tunnel)
1916 {
1917         struct bnxt *bp = eth_dev->data->dev_private;
1918         uint16_t tunnel_type = 0;
1919         uint16_t port = 0;
1920         int rc = 0;
1921
1922         rc = is_bnxt_in_error(bp);
1923         if (rc)
1924                 return rc;
1925
1926         switch (udp_tunnel->prot_type) {
1927         case RTE_TUNNEL_TYPE_VXLAN:
1928                 if (!bp->vxlan_port_cnt) {
1929                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1930                         return -EINVAL;
1931                 }
1932                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1933                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1934                                 udp_tunnel->udp_port, bp->vxlan_port);
1935                         return -EINVAL;
1936                 }
1937                 if (--bp->vxlan_port_cnt)
1938                         return 0;
1939
1940                 tunnel_type =
1941                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1942                 port = bp->vxlan_fw_dst_port_id;
1943                 break;
1944         case RTE_TUNNEL_TYPE_GENEVE:
1945                 if (!bp->geneve_port_cnt) {
1946                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1947                         return -EINVAL;
1948                 }
1949                 if (bp->geneve_port != udp_tunnel->udp_port) {
1950                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1951                                 udp_tunnel->udp_port, bp->geneve_port);
1952                         return -EINVAL;
1953                 }
1954                 if (--bp->geneve_port_cnt)
1955                         return 0;
1956
1957                 tunnel_type =
1958                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1959                 port = bp->geneve_fw_dst_port_id;
1960                 break;
1961         default:
1962                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1963                 return -ENOTSUP;
1964         }
1965
1966         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1967         if (!rc) {
1968                 if (tunnel_type ==
1969                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1970                         bp->vxlan_port = 0;
1971                 if (tunnel_type ==
1972                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1973                         bp->geneve_port = 0;
1974         }
1975         return rc;
1976 }
1977
1978 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1979 {
1980         struct bnxt_filter_info *filter;
1981         struct bnxt_vnic_info *vnic;
1982         int rc = 0;
1983         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1984
1985         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1986         filter = STAILQ_FIRST(&vnic->filter);
1987         while (filter) {
1988                 /* Search for this matching MAC+VLAN filter */
1989                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1990                         /* Delete the filter */
1991                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1992                         if (rc)
1993                                 return rc;
1994                         STAILQ_REMOVE(&vnic->filter, filter,
1995                                       bnxt_filter_info, next);
1996                         bnxt_free_filter(bp, filter);
1997                         PMD_DRV_LOG(INFO,
1998                                     "Deleted vlan filter for %d\n",
1999                                     vlan_id);
2000                         return 0;
2001                 }
2002                 filter = STAILQ_NEXT(filter, next);
2003         }
2004         return -ENOENT;
2005 }
2006
2007 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2008 {
2009         struct bnxt_filter_info *filter;
2010         struct bnxt_vnic_info *vnic;
2011         int rc = 0;
2012         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2013                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2014         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2015
2016         /* Implementation notes on the use of VNIC in this command:
2017          *
2018          * By default, these filters belong to default vnic for the function.
2019          * Once these filters are set up, only destination VNIC can be modified.
2020          * If the destination VNIC is not specified in this command,
2021          * then the HWRM shall only create an l2 context id.
2022          */
2023
2024         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2025         filter = STAILQ_FIRST(&vnic->filter);
2026         /* Check if the VLAN has already been added */
2027         while (filter) {
2028                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2029                         return -EEXIST;
2030
2031                 filter = STAILQ_NEXT(filter, next);
2032         }
2033
2034         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2035          * command to create MAC+VLAN filter with the right flags, enables set.
2036          */
2037         filter = bnxt_alloc_filter(bp);
2038         if (!filter) {
2039                 PMD_DRV_LOG(ERR,
2040                             "MAC/VLAN filter alloc failed\n");
2041                 return -ENOMEM;
2042         }
2043         /* MAC + VLAN ID filter */
2044         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2045          * untagged packets are received
2046          *
2047          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2048          * packets and only the programmed vlan's packets are received
2049          */
2050         filter->l2_ivlan = vlan_id;
2051         filter->l2_ivlan_mask = 0x0FFF;
2052         filter->enables |= en;
2053         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2054
2055         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2056         if (rc) {
2057                 /* Free the newly allocated filter as we were
2058                  * not able to create the filter in hardware.
2059                  */
2060                 bnxt_free_filter(bp, filter);
2061                 return rc;
2062         }
2063
2064         filter->mac_index = 0;
2065         /* Add this new filter to the list */
2066         if (vlan_id == 0)
2067                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2068         else
2069                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2070
2071         PMD_DRV_LOG(INFO,
2072                     "Added Vlan filter for %d\n", vlan_id);
2073         return rc;
2074 }
2075
2076 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2077                 uint16_t vlan_id, int on)
2078 {
2079         struct bnxt *bp = eth_dev->data->dev_private;
2080         int rc;
2081
2082         rc = is_bnxt_in_error(bp);
2083         if (rc)
2084                 return rc;
2085
2086         if (!eth_dev->data->dev_started) {
2087                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2088                 return -EINVAL;
2089         }
2090
2091         /* These operations apply to ALL existing MAC/VLAN filters */
2092         if (on)
2093                 return bnxt_add_vlan_filter(bp, vlan_id);
2094         else
2095                 return bnxt_del_vlan_filter(bp, vlan_id);
2096 }
2097
2098 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2099                                     struct bnxt_vnic_info *vnic)
2100 {
2101         struct bnxt_filter_info *filter;
2102         int rc;
2103
2104         filter = STAILQ_FIRST(&vnic->filter);
2105         while (filter) {
2106                 if (filter->mac_index == 0 &&
2107                     !memcmp(filter->l2_addr, bp->mac_addr,
2108                             RTE_ETHER_ADDR_LEN)) {
2109                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2110                         if (!rc) {
2111                                 STAILQ_REMOVE(&vnic->filter, filter,
2112                                               bnxt_filter_info, next);
2113                                 bnxt_free_filter(bp, filter);
2114                         }
2115                         return rc;
2116                 }
2117                 filter = STAILQ_NEXT(filter, next);
2118         }
2119         return 0;
2120 }
2121
2122 static int
2123 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2124 {
2125         struct bnxt_vnic_info *vnic;
2126         unsigned int i;
2127         int rc;
2128
2129         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2130         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2131                 /* Remove any VLAN filters programmed */
2132                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2133                         bnxt_del_vlan_filter(bp, i);
2134
2135                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2136                 if (rc)
2137                         return rc;
2138         } else {
2139                 /* Default filter will allow packets that match the
2140                  * dest mac. So, it has to be deleted, otherwise, we
2141                  * will endup receiving vlan packets for which the
2142                  * filter is not programmed, when hw-vlan-filter
2143                  * configuration is ON
2144                  */
2145                 bnxt_del_dflt_mac_filter(bp, vnic);
2146                 /* This filter will allow only untagged packets */
2147                 bnxt_add_vlan_filter(bp, 0);
2148         }
2149         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2150                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2151
2152         return 0;
2153 }
2154
2155 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2156 {
2157         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2158         unsigned int i;
2159         int rc;
2160
2161         /* Destroy vnic filters and vnic */
2162         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2163             DEV_RX_OFFLOAD_VLAN_FILTER) {
2164                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2165                         bnxt_del_vlan_filter(bp, i);
2166         }
2167         bnxt_del_dflt_mac_filter(bp, vnic);
2168
2169         rc = bnxt_hwrm_vnic_free(bp, vnic);
2170         if (rc)
2171                 return rc;
2172
2173         rte_free(vnic->fw_grp_ids);
2174         vnic->fw_grp_ids = NULL;
2175
2176         return 0;
2177 }
2178
2179 static int
2180 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2181 {
2182         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2183         int rc;
2184
2185         /* Destroy, recreate and reconfigure the default vnic */
2186         rc = bnxt_free_one_vnic(bp, 0);
2187         if (rc)
2188                 return rc;
2189
2190         /* default vnic 0 */
2191         rc = bnxt_setup_one_vnic(bp, 0);
2192         if (rc)
2193                 return rc;
2194
2195         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2196             DEV_RX_OFFLOAD_VLAN_FILTER) {
2197                 rc = bnxt_add_vlan_filter(bp, 0);
2198                 if (rc)
2199                         return rc;
2200                 rc = bnxt_restore_vlan_filters(bp);
2201                 if (rc)
2202                         return rc;
2203         } else {
2204                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2205                 if (rc)
2206                         return rc;
2207         }
2208
2209         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2210         if (rc)
2211                 return rc;
2212
2213         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2214                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2215
2216         return rc;
2217 }
2218
2219 static int
2220 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2221 {
2222         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2223         struct bnxt *bp = dev->data->dev_private;
2224         int rc;
2225
2226         rc = is_bnxt_in_error(bp);
2227         if (rc)
2228                 return rc;
2229
2230         /* Filter settings will get applied when port is started */
2231         if (!dev->data->dev_started)
2232                 return 0;
2233
2234         if (mask & ETH_VLAN_FILTER_MASK) {
2235                 /* Enable or disable VLAN filtering */
2236                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2237                 if (rc)
2238                         return rc;
2239         }
2240
2241         if (mask & ETH_VLAN_STRIP_MASK) {
2242                 /* Enable or disable VLAN stripping */
2243                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2244                 if (rc)
2245                         return rc;
2246         }
2247
2248         if (mask & ETH_VLAN_EXTEND_MASK) {
2249                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2250                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2251                 else
2252                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2253         }
2254
2255         return 0;
2256 }
2257
2258 static int
2259 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2260                       uint16_t tpid)
2261 {
2262         struct bnxt *bp = dev->data->dev_private;
2263         int qinq = dev->data->dev_conf.rxmode.offloads &
2264                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2265
2266         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2267             vlan_type != ETH_VLAN_TYPE_OUTER) {
2268                 PMD_DRV_LOG(ERR,
2269                             "Unsupported vlan type.");
2270                 return -EINVAL;
2271         }
2272         if (!qinq) {
2273                 PMD_DRV_LOG(ERR,
2274                             "QinQ not enabled. Needs to be ON as we can "
2275                             "accelerate only outer vlan\n");
2276                 return -EINVAL;
2277         }
2278
2279         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2280                 switch (tpid) {
2281                 case RTE_ETHER_TYPE_QINQ:
2282                         bp->outer_tpid_bd =
2283                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2284                                 break;
2285                 case RTE_ETHER_TYPE_VLAN:
2286                         bp->outer_tpid_bd =
2287                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2288                                 break;
2289                 case 0x9100:
2290                         bp->outer_tpid_bd =
2291                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2292                                 break;
2293                 case 0x9200:
2294                         bp->outer_tpid_bd =
2295                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2296                                 break;
2297                 case 0x9300:
2298                         bp->outer_tpid_bd =
2299                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2300                                 break;
2301                 default:
2302                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2303                         return -EINVAL;
2304                 }
2305                 bp->outer_tpid_bd |= tpid;
2306                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2307         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2308                 PMD_DRV_LOG(ERR,
2309                             "Can accelerate only outer vlan in QinQ\n");
2310                 return -EINVAL;
2311         }
2312
2313         return 0;
2314 }
2315
2316 static int
2317 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2318                              struct rte_ether_addr *addr)
2319 {
2320         struct bnxt *bp = dev->data->dev_private;
2321         /* Default Filter is tied to VNIC 0 */
2322         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2323         int rc;
2324
2325         rc = is_bnxt_in_error(bp);
2326         if (rc)
2327                 return rc;
2328
2329         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2330                 return -EPERM;
2331
2332         if (rte_is_zero_ether_addr(addr))
2333                 return -EINVAL;
2334
2335         /* Filter settings will get applied when port is started */
2336         if (!dev->data->dev_started)
2337                 return 0;
2338
2339         /* Check if the requested MAC is already added */
2340         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2341                 return 0;
2342
2343         /* Destroy filter and re-create it */
2344         bnxt_del_dflt_mac_filter(bp, vnic);
2345
2346         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2347         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2348                 /* This filter will allow only untagged packets */
2349                 rc = bnxt_add_vlan_filter(bp, 0);
2350         } else {
2351                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2352         }
2353
2354         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2355         return rc;
2356 }
2357
2358 static int
2359 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2360                           struct rte_ether_addr *mc_addr_set,
2361                           uint32_t nb_mc_addr)
2362 {
2363         struct bnxt *bp = eth_dev->data->dev_private;
2364         char *mc_addr_list = (char *)mc_addr_set;
2365         struct bnxt_vnic_info *vnic;
2366         uint32_t off = 0, i = 0;
2367         int rc;
2368
2369         rc = is_bnxt_in_error(bp);
2370         if (rc)
2371                 return rc;
2372
2373         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2374
2375         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2376                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2377                 goto allmulti;
2378         }
2379
2380         /* TODO Check for Duplicate mcast addresses */
2381         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2382         for (i = 0; i < nb_mc_addr; i++) {
2383                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2384                         RTE_ETHER_ADDR_LEN);
2385                 off += RTE_ETHER_ADDR_LEN;
2386         }
2387
2388         vnic->mc_addr_cnt = i;
2389         if (vnic->mc_addr_cnt)
2390                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2391         else
2392                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2393
2394 allmulti:
2395         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2396 }
2397
2398 static int
2399 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2400 {
2401         struct bnxt *bp = dev->data->dev_private;
2402         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2403         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2404         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2405         int ret;
2406
2407         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2408                         fw_major, fw_minor, fw_updt);
2409
2410         ret += 1; /* add the size of '\0' */
2411         if (fw_size < (uint32_t)ret)
2412                 return ret;
2413         else
2414                 return 0;
2415 }
2416
2417 static void
2418 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2419         struct rte_eth_rxq_info *qinfo)
2420 {
2421         struct bnxt *bp = dev->data->dev_private;
2422         struct bnxt_rx_queue *rxq;
2423
2424         if (is_bnxt_in_error(bp))
2425                 return;
2426
2427         rxq = dev->data->rx_queues[queue_id];
2428
2429         qinfo->mp = rxq->mb_pool;
2430         qinfo->scattered_rx = dev->data->scattered_rx;
2431         qinfo->nb_desc = rxq->nb_rx_desc;
2432
2433         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2434         qinfo->conf.rx_drop_en = 0;
2435         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2436 }
2437
2438 static void
2439 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2440         struct rte_eth_txq_info *qinfo)
2441 {
2442         struct bnxt *bp = dev->data->dev_private;
2443         struct bnxt_tx_queue *txq;
2444
2445         if (is_bnxt_in_error(bp))
2446                 return;
2447
2448         txq = dev->data->tx_queues[queue_id];
2449
2450         qinfo->nb_desc = txq->nb_tx_desc;
2451
2452         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2453         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2454         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2455
2456         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2457         qinfo->conf.tx_rs_thresh = 0;
2458         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2459 }
2460
2461 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2462 {
2463         struct bnxt *bp = eth_dev->data->dev_private;
2464         uint32_t new_pkt_size;
2465         uint32_t rc = 0;
2466         uint32_t i;
2467
2468         rc = is_bnxt_in_error(bp);
2469         if (rc)
2470                 return rc;
2471
2472         /* Exit if receive queues are not configured yet */
2473         if (!eth_dev->data->nb_rx_queues)
2474                 return rc;
2475
2476         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2477                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2478
2479 #ifdef RTE_ARCH_X86
2480         /*
2481          * If vector-mode tx/rx is active, disallow any MTU change that would
2482          * require scattered receive support.
2483          */
2484         if (eth_dev->data->dev_started &&
2485             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2486              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2487             (new_pkt_size >
2488              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2489                 PMD_DRV_LOG(ERR,
2490                             "MTU change would require scattered rx support. ");
2491                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2492                 return -EINVAL;
2493         }
2494 #endif
2495
2496         if (new_mtu > RTE_ETHER_MTU) {
2497                 bp->flags |= BNXT_FLAG_JUMBO;
2498                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2499                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2500         } else {
2501                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2502                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2503                 bp->flags &= ~BNXT_FLAG_JUMBO;
2504         }
2505
2506         /* Is there a change in mtu setting? */
2507         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2508                 return rc;
2509
2510         for (i = 0; i < bp->nr_vnics; i++) {
2511                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2512                 uint16_t size = 0;
2513
2514                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2515                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2516                 if (rc)
2517                         break;
2518
2519                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2520                 size -= RTE_PKTMBUF_HEADROOM;
2521
2522                 if (size < new_mtu) {
2523                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2524                         if (rc)
2525                                 return rc;
2526                 }
2527         }
2528
2529         if (!rc)
2530                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2531
2532         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2533
2534         return rc;
2535 }
2536
2537 static int
2538 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2539 {
2540         struct bnxt *bp = dev->data->dev_private;
2541         uint16_t vlan = bp->vlan;
2542         int rc;
2543
2544         rc = is_bnxt_in_error(bp);
2545         if (rc)
2546                 return rc;
2547
2548         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2549                 PMD_DRV_LOG(ERR,
2550                         "PVID cannot be modified for this function\n");
2551                 return -ENOTSUP;
2552         }
2553         bp->vlan = on ? pvid : 0;
2554
2555         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2556         if (rc)
2557                 bp->vlan = vlan;
2558         return rc;
2559 }
2560
2561 static int
2562 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2563 {
2564         struct bnxt *bp = dev->data->dev_private;
2565         int rc;
2566
2567         rc = is_bnxt_in_error(bp);
2568         if (rc)
2569                 return rc;
2570
2571         return bnxt_hwrm_port_led_cfg(bp, true);
2572 }
2573
2574 static int
2575 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2576 {
2577         struct bnxt *bp = dev->data->dev_private;
2578         int rc;
2579
2580         rc = is_bnxt_in_error(bp);
2581         if (rc)
2582                 return rc;
2583
2584         return bnxt_hwrm_port_led_cfg(bp, false);
2585 }
2586
2587 static uint32_t
2588 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2589 {
2590         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2591         uint32_t desc = 0, raw_cons = 0, cons;
2592         struct bnxt_cp_ring_info *cpr;
2593         struct bnxt_rx_queue *rxq;
2594         struct rx_pkt_cmpl *rxcmp;
2595         int rc;
2596
2597         rc = is_bnxt_in_error(bp);
2598         if (rc)
2599                 return rc;
2600
2601         rxq = dev->data->rx_queues[rx_queue_id];
2602         cpr = rxq->cp_ring;
2603         raw_cons = cpr->cp_raw_cons;
2604
2605         while (1) {
2606                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2607                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2608                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2609
2610                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2611                         break;
2612                 } else {
2613                         raw_cons++;
2614                         desc++;
2615                 }
2616         }
2617
2618         return desc;
2619 }
2620
2621 static int
2622 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2623 {
2624         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2625         struct bnxt_rx_ring_info *rxr;
2626         struct bnxt_cp_ring_info *cpr;
2627         struct bnxt_sw_rx_bd *rx_buf;
2628         struct rx_pkt_cmpl *rxcmp;
2629         uint32_t cons, cp_cons;
2630         int rc;
2631
2632         if (!rxq)
2633                 return -EINVAL;
2634
2635         rc = is_bnxt_in_error(rxq->bp);
2636         if (rc)
2637                 return rc;
2638
2639         cpr = rxq->cp_ring;
2640         rxr = rxq->rx_ring;
2641
2642         if (offset >= rxq->nb_rx_desc)
2643                 return -EINVAL;
2644
2645         cons = RING_CMP(cpr->cp_ring_struct, offset);
2646         cp_cons = cpr->cp_raw_cons;
2647         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2648
2649         if (cons > cp_cons) {
2650                 if (CMPL_VALID(rxcmp, cpr->valid))
2651                         return RTE_ETH_RX_DESC_DONE;
2652         } else {
2653                 if (CMPL_VALID(rxcmp, !cpr->valid))
2654                         return RTE_ETH_RX_DESC_DONE;
2655         }
2656         rx_buf = &rxr->rx_buf_ring[cons];
2657         if (rx_buf->mbuf == NULL)
2658                 return RTE_ETH_RX_DESC_UNAVAIL;
2659
2660
2661         return RTE_ETH_RX_DESC_AVAIL;
2662 }
2663
2664 static int
2665 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2666 {
2667         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2668         struct bnxt_tx_ring_info *txr;
2669         struct bnxt_cp_ring_info *cpr;
2670         struct bnxt_sw_tx_bd *tx_buf;
2671         struct tx_pkt_cmpl *txcmp;
2672         uint32_t cons, cp_cons;
2673         int rc;
2674
2675         if (!txq)
2676                 return -EINVAL;
2677
2678         rc = is_bnxt_in_error(txq->bp);
2679         if (rc)
2680                 return rc;
2681
2682         cpr = txq->cp_ring;
2683         txr = txq->tx_ring;
2684
2685         if (offset >= txq->nb_tx_desc)
2686                 return -EINVAL;
2687
2688         cons = RING_CMP(cpr->cp_ring_struct, offset);
2689         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2690         cp_cons = cpr->cp_raw_cons;
2691
2692         if (cons > cp_cons) {
2693                 if (CMPL_VALID(txcmp, cpr->valid))
2694                         return RTE_ETH_TX_DESC_UNAVAIL;
2695         } else {
2696                 if (CMPL_VALID(txcmp, !cpr->valid))
2697                         return RTE_ETH_TX_DESC_UNAVAIL;
2698         }
2699         tx_buf = &txr->tx_buf_ring[cons];
2700         if (tx_buf->mbuf == NULL)
2701                 return RTE_ETH_TX_DESC_DONE;
2702
2703         return RTE_ETH_TX_DESC_FULL;
2704 }
2705
2706 static struct bnxt_filter_info *
2707 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2708                                 struct rte_eth_ethertype_filter *efilter,
2709                                 struct bnxt_vnic_info *vnic0,
2710                                 struct bnxt_vnic_info *vnic,
2711                                 int *ret)
2712 {
2713         struct bnxt_filter_info *mfilter = NULL;
2714         int match = 0;
2715         *ret = 0;
2716
2717         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2718                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2719                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2720                         " ethertype filter.", efilter->ether_type);
2721                 *ret = -EINVAL;
2722                 goto exit;
2723         }
2724         if (efilter->queue >= bp->rx_nr_rings) {
2725                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2726                 *ret = -EINVAL;
2727                 goto exit;
2728         }
2729
2730         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2731         vnic = &bp->vnic_info[efilter->queue];
2732         if (vnic == NULL) {
2733                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2734                 *ret = -EINVAL;
2735                 goto exit;
2736         }
2737
2738         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2739                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2740                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2741                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2742                              mfilter->flags ==
2743                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2744                              mfilter->ethertype == efilter->ether_type)) {
2745                                 match = 1;
2746                                 break;
2747                         }
2748                 }
2749         } else {
2750                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2751                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2752                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2753                              mfilter->ethertype == efilter->ether_type &&
2754                              mfilter->flags ==
2755                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2756                                 match = 1;
2757                                 break;
2758                         }
2759         }
2760
2761         if (match)
2762                 *ret = -EEXIST;
2763
2764 exit:
2765         return mfilter;
2766 }
2767
2768 static int
2769 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2770                         enum rte_filter_op filter_op,
2771                         void *arg)
2772 {
2773         struct bnxt *bp = dev->data->dev_private;
2774         struct rte_eth_ethertype_filter *efilter =
2775                         (struct rte_eth_ethertype_filter *)arg;
2776         struct bnxt_filter_info *bfilter, *filter1;
2777         struct bnxt_vnic_info *vnic, *vnic0;
2778         int ret;
2779
2780         if (filter_op == RTE_ETH_FILTER_NOP)
2781                 return 0;
2782
2783         if (arg == NULL) {
2784                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2785                             filter_op);
2786                 return -EINVAL;
2787         }
2788
2789         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2790         vnic = &bp->vnic_info[efilter->queue];
2791
2792         switch (filter_op) {
2793         case RTE_ETH_FILTER_ADD:
2794                 bnxt_match_and_validate_ether_filter(bp, efilter,
2795                                                         vnic0, vnic, &ret);
2796                 if (ret < 0)
2797                         return ret;
2798
2799                 bfilter = bnxt_get_unused_filter(bp);
2800                 if (bfilter == NULL) {
2801                         PMD_DRV_LOG(ERR,
2802                                 "Not enough resources for a new filter.\n");
2803                         return -ENOMEM;
2804                 }
2805                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2806                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2807                        RTE_ETHER_ADDR_LEN);
2808                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2809                        RTE_ETHER_ADDR_LEN);
2810                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2811                 bfilter->ethertype = efilter->ether_type;
2812                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2813
2814                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2815                 if (filter1 == NULL) {
2816                         ret = -EINVAL;
2817                         goto cleanup;
2818                 }
2819                 bfilter->enables |=
2820                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2821                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2822
2823                 bfilter->dst_id = vnic->fw_vnic_id;
2824
2825                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2826                         bfilter->flags =
2827                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2828                 }
2829
2830                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2831                 if (ret)
2832                         goto cleanup;
2833                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2834                 break;
2835         case RTE_ETH_FILTER_DELETE:
2836                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2837                                                         vnic0, vnic, &ret);
2838                 if (ret == -EEXIST) {
2839                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2840
2841                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2842                                       next);
2843                         bnxt_free_filter(bp, filter1);
2844                 } else if (ret == 0) {
2845                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2846                 }
2847                 break;
2848         default:
2849                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2850                 ret = -EINVAL;
2851                 goto error;
2852         }
2853         return ret;
2854 cleanup:
2855         bnxt_free_filter(bp, bfilter);
2856 error:
2857         return ret;
2858 }
2859
2860 static inline int
2861 parse_ntuple_filter(struct bnxt *bp,
2862                     struct rte_eth_ntuple_filter *nfilter,
2863                     struct bnxt_filter_info *bfilter)
2864 {
2865         uint32_t en = 0;
2866
2867         if (nfilter->queue >= bp->rx_nr_rings) {
2868                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2869                 return -EINVAL;
2870         }
2871
2872         switch (nfilter->dst_port_mask) {
2873         case UINT16_MAX:
2874                 bfilter->dst_port_mask = -1;
2875                 bfilter->dst_port = nfilter->dst_port;
2876                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2877                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2878                 break;
2879         default:
2880                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2881                 return -EINVAL;
2882         }
2883
2884         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2885         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2886
2887         switch (nfilter->proto_mask) {
2888         case UINT8_MAX:
2889                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2890                         bfilter->ip_protocol = 17;
2891                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2892                         bfilter->ip_protocol = 6;
2893                 else
2894                         return -EINVAL;
2895                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2896                 break;
2897         default:
2898                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2899                 return -EINVAL;
2900         }
2901
2902         switch (nfilter->dst_ip_mask) {
2903         case UINT32_MAX:
2904                 bfilter->dst_ipaddr_mask[0] = -1;
2905                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2906                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2907                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2908                 break;
2909         default:
2910                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2911                 return -EINVAL;
2912         }
2913
2914         switch (nfilter->src_ip_mask) {
2915         case UINT32_MAX:
2916                 bfilter->src_ipaddr_mask[0] = -1;
2917                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2918                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2919                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2920                 break;
2921         default:
2922                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2923                 return -EINVAL;
2924         }
2925
2926         switch (nfilter->src_port_mask) {
2927         case UINT16_MAX:
2928                 bfilter->src_port_mask = -1;
2929                 bfilter->src_port = nfilter->src_port;
2930                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2931                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2932                 break;
2933         default:
2934                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2935                 return -EINVAL;
2936         }
2937
2938         bfilter->enables = en;
2939         return 0;
2940 }
2941
2942 static struct bnxt_filter_info*
2943 bnxt_match_ntuple_filter(struct bnxt *bp,
2944                          struct bnxt_filter_info *bfilter,
2945                          struct bnxt_vnic_info **mvnic)
2946 {
2947         struct bnxt_filter_info *mfilter = NULL;
2948         int i;
2949
2950         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2951                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2952                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2953                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2954                             bfilter->src_ipaddr_mask[0] ==
2955                             mfilter->src_ipaddr_mask[0] &&
2956                             bfilter->src_port == mfilter->src_port &&
2957                             bfilter->src_port_mask == mfilter->src_port_mask &&
2958                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2959                             bfilter->dst_ipaddr_mask[0] ==
2960                             mfilter->dst_ipaddr_mask[0] &&
2961                             bfilter->dst_port == mfilter->dst_port &&
2962                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2963                             bfilter->flags == mfilter->flags &&
2964                             bfilter->enables == mfilter->enables) {
2965                                 if (mvnic)
2966                                         *mvnic = vnic;
2967                                 return mfilter;
2968                         }
2969                 }
2970         }
2971         return NULL;
2972 }
2973
2974 static int
2975 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2976                        struct rte_eth_ntuple_filter *nfilter,
2977                        enum rte_filter_op filter_op)
2978 {
2979         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2980         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2981         int ret;
2982
2983         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2984                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2985                 return -EINVAL;
2986         }
2987
2988         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2989                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2990                 return -EINVAL;
2991         }
2992
2993         bfilter = bnxt_get_unused_filter(bp);
2994         if (bfilter == NULL) {
2995                 PMD_DRV_LOG(ERR,
2996                         "Not enough resources for a new filter.\n");
2997                 return -ENOMEM;
2998         }
2999         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3000         if (ret < 0)
3001                 goto free_filter;
3002
3003         vnic = &bp->vnic_info[nfilter->queue];
3004         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3005         filter1 = STAILQ_FIRST(&vnic0->filter);
3006         if (filter1 == NULL) {
3007                 ret = -EINVAL;
3008                 goto free_filter;
3009         }
3010
3011         bfilter->dst_id = vnic->fw_vnic_id;
3012         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3013         bfilter->enables |=
3014                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3015         bfilter->ethertype = 0x800;
3016         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3017
3018         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3019
3020         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3021             bfilter->dst_id == mfilter->dst_id) {
3022                 PMD_DRV_LOG(ERR, "filter exists.\n");
3023                 ret = -EEXIST;
3024                 goto free_filter;
3025         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3026                    bfilter->dst_id != mfilter->dst_id) {
3027                 mfilter->dst_id = vnic->fw_vnic_id;
3028                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3029                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3030                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3031                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3032                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3033                 goto free_filter;
3034         }
3035         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3036                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3037                 ret = -ENOENT;
3038                 goto free_filter;
3039         }
3040
3041         if (filter_op == RTE_ETH_FILTER_ADD) {
3042                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3043                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3044                 if (ret)
3045                         goto free_filter;
3046                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3047         } else {
3048                 if (mfilter == NULL) {
3049                         /* This should not happen. But for Coverity! */
3050                         ret = -ENOENT;
3051                         goto free_filter;
3052                 }
3053                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3054
3055                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3056                 bnxt_free_filter(bp, mfilter);
3057                 bnxt_free_filter(bp, bfilter);
3058         }
3059
3060         return 0;
3061 free_filter:
3062         bnxt_free_filter(bp, bfilter);
3063         return ret;
3064 }
3065
3066 static int
3067 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3068                         enum rte_filter_op filter_op,
3069                         void *arg)
3070 {
3071         struct bnxt *bp = dev->data->dev_private;
3072         int ret;
3073
3074         if (filter_op == RTE_ETH_FILTER_NOP)
3075                 return 0;
3076
3077         if (arg == NULL) {
3078                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3079                             filter_op);
3080                 return -EINVAL;
3081         }
3082
3083         switch (filter_op) {
3084         case RTE_ETH_FILTER_ADD:
3085                 ret = bnxt_cfg_ntuple_filter(bp,
3086                         (struct rte_eth_ntuple_filter *)arg,
3087                         filter_op);
3088                 break;
3089         case RTE_ETH_FILTER_DELETE:
3090                 ret = bnxt_cfg_ntuple_filter(bp,
3091                         (struct rte_eth_ntuple_filter *)arg,
3092                         filter_op);
3093                 break;
3094         default:
3095                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3096                 ret = -EINVAL;
3097                 break;
3098         }
3099         return ret;
3100 }
3101
3102 static int
3103 bnxt_parse_fdir_filter(struct bnxt *bp,
3104                        struct rte_eth_fdir_filter *fdir,
3105                        struct bnxt_filter_info *filter)
3106 {
3107         enum rte_fdir_mode fdir_mode =
3108                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3109         struct bnxt_vnic_info *vnic0, *vnic;
3110         struct bnxt_filter_info *filter1;
3111         uint32_t en = 0;
3112         int i;
3113
3114         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3115                 return -EINVAL;
3116
3117         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3118         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3119
3120         switch (fdir->input.flow_type) {
3121         case RTE_ETH_FLOW_IPV4:
3122         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3123                 /* FALLTHROUGH */
3124                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3125                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3126                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3127                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3128                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3129                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3130                 filter->ip_addr_type =
3131                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3132                 filter->src_ipaddr_mask[0] = 0xffffffff;
3133                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3134                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3135                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3136                 filter->ethertype = 0x800;
3137                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3138                 break;
3139         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3140                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3141                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3142                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3143                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3144                 filter->dst_port_mask = 0xffff;
3145                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3146                 filter->src_port_mask = 0xffff;
3147                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3148                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3149                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3150                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3151                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3152                 filter->ip_protocol = 6;
3153                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3154                 filter->ip_addr_type =
3155                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3156                 filter->src_ipaddr_mask[0] = 0xffffffff;
3157                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3158                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3159                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3160                 filter->ethertype = 0x800;
3161                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3162                 break;
3163         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3164                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3165                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3166                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3167                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3168                 filter->dst_port_mask = 0xffff;
3169                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3170                 filter->src_port_mask = 0xffff;
3171                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3172                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3173                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3174                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3175                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3176                 filter->ip_protocol = 17;
3177                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3178                 filter->ip_addr_type =
3179                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3180                 filter->src_ipaddr_mask[0] = 0xffffffff;
3181                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3182                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3183                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3184                 filter->ethertype = 0x800;
3185                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3186                 break;
3187         case RTE_ETH_FLOW_IPV6:
3188         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3189                 /* FALLTHROUGH */
3190                 filter->ip_addr_type =
3191                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3192                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3193                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3194                 rte_memcpy(filter->src_ipaddr,
3195                            fdir->input.flow.ipv6_flow.src_ip, 16);
3196                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3197                 rte_memcpy(filter->dst_ipaddr,
3198                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3199                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3200                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3201                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3202                 memset(filter->src_ipaddr_mask, 0xff, 16);
3203                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3204                 filter->ethertype = 0x86dd;
3205                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3206                 break;
3207         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3208                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3209                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3210                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3211                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3212                 filter->dst_port_mask = 0xffff;
3213                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3214                 filter->src_port_mask = 0xffff;
3215                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3216                 filter->ip_addr_type =
3217                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3218                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3219                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3220                 rte_memcpy(filter->src_ipaddr,
3221                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3222                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3223                 rte_memcpy(filter->dst_ipaddr,
3224                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3225                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3226                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3227                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3228                 memset(filter->src_ipaddr_mask, 0xff, 16);
3229                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3230                 filter->ethertype = 0x86dd;
3231                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3232                 break;
3233         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3234                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3235                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3236                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3237                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3238                 filter->dst_port_mask = 0xffff;
3239                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3240                 filter->src_port_mask = 0xffff;
3241                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3242                 filter->ip_addr_type =
3243                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3244                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3245                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3246                 rte_memcpy(filter->src_ipaddr,
3247                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3248                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3249                 rte_memcpy(filter->dst_ipaddr,
3250                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3251                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3252                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3253                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3254                 memset(filter->src_ipaddr_mask, 0xff, 16);
3255                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3256                 filter->ethertype = 0x86dd;
3257                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3258                 break;
3259         case RTE_ETH_FLOW_L2_PAYLOAD:
3260                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3261                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3262                 break;
3263         case RTE_ETH_FLOW_VXLAN:
3264                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3265                         return -EINVAL;
3266                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3267                 filter->tunnel_type =
3268                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3269                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3270                 break;
3271         case RTE_ETH_FLOW_NVGRE:
3272                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3273                         return -EINVAL;
3274                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3275                 filter->tunnel_type =
3276                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3277                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3278                 break;
3279         case RTE_ETH_FLOW_UNKNOWN:
3280         case RTE_ETH_FLOW_RAW:
3281         case RTE_ETH_FLOW_FRAG_IPV4:
3282         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3283         case RTE_ETH_FLOW_FRAG_IPV6:
3284         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3285         case RTE_ETH_FLOW_IPV6_EX:
3286         case RTE_ETH_FLOW_IPV6_TCP_EX:
3287         case RTE_ETH_FLOW_IPV6_UDP_EX:
3288         case RTE_ETH_FLOW_GENEVE:
3289                 /* FALLTHROUGH */
3290         default:
3291                 return -EINVAL;
3292         }
3293
3294         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3295         vnic = &bp->vnic_info[fdir->action.rx_queue];
3296         if (vnic == NULL) {
3297                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3298                 return -EINVAL;
3299         }
3300
3301         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3302                 rte_memcpy(filter->dst_macaddr,
3303                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3304                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3305         }
3306
3307         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3308                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3309                 filter1 = STAILQ_FIRST(&vnic0->filter);
3310                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3311         } else {
3312                 filter->dst_id = vnic->fw_vnic_id;
3313                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3314                         if (filter->dst_macaddr[i] == 0x00)
3315                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3316                         else
3317                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3318         }
3319
3320         if (filter1 == NULL)
3321                 return -EINVAL;
3322
3323         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3324         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3325
3326         filter->enables = en;
3327
3328         return 0;
3329 }
3330
3331 static struct bnxt_filter_info *
3332 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3333                 struct bnxt_vnic_info **mvnic)
3334 {
3335         struct bnxt_filter_info *mf = NULL;
3336         int i;
3337
3338         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3339                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3340
3341                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3342                         if (mf->filter_type == nf->filter_type &&
3343                             mf->flags == nf->flags &&
3344                             mf->src_port == nf->src_port &&
3345                             mf->src_port_mask == nf->src_port_mask &&
3346                             mf->dst_port == nf->dst_port &&
3347                             mf->dst_port_mask == nf->dst_port_mask &&
3348                             mf->ip_protocol == nf->ip_protocol &&
3349                             mf->ip_addr_type == nf->ip_addr_type &&
3350                             mf->ethertype == nf->ethertype &&
3351                             mf->vni == nf->vni &&
3352                             mf->tunnel_type == nf->tunnel_type &&
3353                             mf->l2_ovlan == nf->l2_ovlan &&
3354                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3355                             mf->l2_ivlan == nf->l2_ivlan &&
3356                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3357                             !memcmp(mf->l2_addr, nf->l2_addr,
3358                                     RTE_ETHER_ADDR_LEN) &&
3359                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3360                                     RTE_ETHER_ADDR_LEN) &&
3361                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3362                                     RTE_ETHER_ADDR_LEN) &&
3363                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3364                                     RTE_ETHER_ADDR_LEN) &&
3365                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3366                                     sizeof(nf->src_ipaddr)) &&
3367                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3368                                     sizeof(nf->src_ipaddr_mask)) &&
3369                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3370                                     sizeof(nf->dst_ipaddr)) &&
3371                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3372                                     sizeof(nf->dst_ipaddr_mask))) {
3373                                 if (mvnic)
3374                                         *mvnic = vnic;
3375                                 return mf;
3376                         }
3377                 }
3378         }
3379         return NULL;
3380 }
3381
3382 static int
3383 bnxt_fdir_filter(struct rte_eth_dev *dev,
3384                  enum rte_filter_op filter_op,
3385                  void *arg)
3386 {
3387         struct bnxt *bp = dev->data->dev_private;
3388         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3389         struct bnxt_filter_info *filter, *match;
3390         struct bnxt_vnic_info *vnic, *mvnic;
3391         int ret = 0, i;
3392
3393         if (filter_op == RTE_ETH_FILTER_NOP)
3394                 return 0;
3395
3396         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3397                 return -EINVAL;
3398
3399         switch (filter_op) {
3400         case RTE_ETH_FILTER_ADD:
3401         case RTE_ETH_FILTER_DELETE:
3402                 /* FALLTHROUGH */
3403                 filter = bnxt_get_unused_filter(bp);
3404                 if (filter == NULL) {
3405                         PMD_DRV_LOG(ERR,
3406                                 "Not enough resources for a new flow.\n");
3407                         return -ENOMEM;
3408                 }
3409
3410                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3411                 if (ret != 0)
3412                         goto free_filter;
3413                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3414
3415                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3416                         vnic = &bp->vnic_info[0];
3417                 else
3418                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3419
3420                 match = bnxt_match_fdir(bp, filter, &mvnic);
3421                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3422                         if (match->dst_id == vnic->fw_vnic_id) {
3423                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3424                                 ret = -EEXIST;
3425                                 goto free_filter;
3426                         } else {
3427                                 match->dst_id = vnic->fw_vnic_id;
3428                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3429                                                                   match->dst_id,
3430                                                                   match);
3431                                 STAILQ_REMOVE(&mvnic->filter, match,
3432                                               bnxt_filter_info, next);
3433                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3434                                 PMD_DRV_LOG(ERR,
3435                                         "Filter with matching pattern exist\n");
3436                                 PMD_DRV_LOG(ERR,
3437                                         "Updated it to new destination q\n");
3438                                 goto free_filter;
3439                         }
3440                 }
3441                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3442                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3443                         ret = -ENOENT;
3444                         goto free_filter;
3445                 }
3446
3447                 if (filter_op == RTE_ETH_FILTER_ADD) {
3448                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3449                                                           filter->dst_id,
3450                                                           filter);
3451                         if (ret)
3452                                 goto free_filter;
3453                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3454                 } else {
3455                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3456                         STAILQ_REMOVE(&vnic->filter, match,
3457                                       bnxt_filter_info, next);
3458                         bnxt_free_filter(bp, match);
3459                         bnxt_free_filter(bp, filter);
3460                 }
3461                 break;
3462         case RTE_ETH_FILTER_FLUSH:
3463                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3464                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3465
3466                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3467                                 if (filter->filter_type ==
3468                                     HWRM_CFA_NTUPLE_FILTER) {
3469                                         ret =
3470                                         bnxt_hwrm_clear_ntuple_filter(bp,
3471                                                                       filter);
3472                                         STAILQ_REMOVE(&vnic->filter, filter,
3473                                                       bnxt_filter_info, next);
3474                                 }
3475                         }
3476                 }
3477                 return ret;
3478         case RTE_ETH_FILTER_UPDATE:
3479         case RTE_ETH_FILTER_STATS:
3480         case RTE_ETH_FILTER_INFO:
3481                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3482                 break;
3483         default:
3484                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3485                 ret = -EINVAL;
3486                 break;
3487         }
3488         return ret;
3489
3490 free_filter:
3491         bnxt_free_filter(bp, filter);
3492         return ret;
3493 }
3494
3495 static int
3496 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3497                     enum rte_filter_type filter_type,
3498                     enum rte_filter_op filter_op, void *arg)
3499 {
3500         struct bnxt *bp = dev->data->dev_private;
3501         int ret = 0;
3502
3503         ret = is_bnxt_in_error(dev->data->dev_private);
3504         if (ret)
3505                 return ret;
3506
3507         switch (filter_type) {
3508         case RTE_ETH_FILTER_TUNNEL:
3509                 PMD_DRV_LOG(ERR,
3510                         "filter type: %d: To be implemented\n", filter_type);
3511                 break;
3512         case RTE_ETH_FILTER_FDIR:
3513                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3514                 break;
3515         case RTE_ETH_FILTER_NTUPLE:
3516                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3517                 break;
3518         case RTE_ETH_FILTER_ETHERTYPE:
3519                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3520                 break;
3521         case RTE_ETH_FILTER_GENERIC:
3522                 if (filter_op != RTE_ETH_FILTER_GET)
3523                         return -EINVAL;
3524                 if (bp->truflow)
3525                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3526                 else
3527                         *(const void **)arg = &bnxt_flow_ops;
3528                 break;
3529         default:
3530                 PMD_DRV_LOG(ERR,
3531                         "Filter type (%d) not supported", filter_type);
3532                 ret = -EINVAL;
3533                 break;
3534         }
3535         return ret;
3536 }
3537
3538 static const uint32_t *
3539 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3540 {
3541         static const uint32_t ptypes[] = {
3542                 RTE_PTYPE_L2_ETHER_VLAN,
3543                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3544                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3545                 RTE_PTYPE_L4_ICMP,
3546                 RTE_PTYPE_L4_TCP,
3547                 RTE_PTYPE_L4_UDP,
3548                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3549                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3550                 RTE_PTYPE_INNER_L4_ICMP,
3551                 RTE_PTYPE_INNER_L4_TCP,
3552                 RTE_PTYPE_INNER_L4_UDP,
3553                 RTE_PTYPE_UNKNOWN
3554         };
3555
3556         if (!dev->rx_pkt_burst)
3557                 return NULL;
3558
3559         return ptypes;
3560 }
3561
3562 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3563                          int reg_win)
3564 {
3565         uint32_t reg_base = *reg_arr & 0xfffff000;
3566         uint32_t win_off;
3567         int i;
3568
3569         for (i = 0; i < count; i++) {
3570                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3571                         return -ERANGE;
3572         }
3573         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3574         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3575         return 0;
3576 }
3577
3578 static int bnxt_map_ptp_regs(struct bnxt *bp)
3579 {
3580         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3581         uint32_t *reg_arr;
3582         int rc, i;
3583
3584         reg_arr = ptp->rx_regs;
3585         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3586         if (rc)
3587                 return rc;
3588
3589         reg_arr = ptp->tx_regs;
3590         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3591         if (rc)
3592                 return rc;
3593
3594         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3595                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3596
3597         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3598                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3599
3600         return 0;
3601 }
3602
3603 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3604 {
3605         rte_write32(0, (uint8_t *)bp->bar0 +
3606                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3607         rte_write32(0, (uint8_t *)bp->bar0 +
3608                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3609 }
3610
3611 static uint64_t bnxt_cc_read(struct bnxt *bp)
3612 {
3613         uint64_t ns;
3614
3615         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3616                               BNXT_GRCPF_REG_SYNC_TIME));
3617         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3618                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3619         return ns;
3620 }
3621
3622 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3623 {
3624         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3625         uint32_t fifo;
3626
3627         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3628                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3629         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3630                 return -EAGAIN;
3631
3632         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3633                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3634         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3635                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3636         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3637                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3638
3639         return 0;
3640 }
3641
3642 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3643 {
3644         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3645         struct bnxt_pf_info *pf = &bp->pf;
3646         uint16_t port_id;
3647         uint32_t fifo;
3648
3649         if (!ptp)
3650                 return -ENODEV;
3651
3652         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3653                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3654         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3655                 return -EAGAIN;
3656
3657         port_id = pf->port_id;
3658         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3659                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3660
3661         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3662                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3663         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3664 /*              bnxt_clr_rx_ts(bp);       TBD  */
3665                 return -EBUSY;
3666         }
3667
3668         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3669                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3670         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3671                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3672
3673         return 0;
3674 }
3675
3676 static int
3677 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3678 {
3679         uint64_t ns;
3680         struct bnxt *bp = dev->data->dev_private;
3681         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3682
3683         if (!ptp)
3684                 return 0;
3685
3686         ns = rte_timespec_to_ns(ts);
3687         /* Set the timecounters to a new value. */
3688         ptp->tc.nsec = ns;
3689
3690         return 0;
3691 }
3692
3693 static int
3694 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3695 {
3696         struct bnxt *bp = dev->data->dev_private;
3697         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3698         uint64_t ns, systime_cycles = 0;
3699         int rc = 0;
3700
3701         if (!ptp)
3702                 return 0;
3703
3704         if (BNXT_CHIP_THOR(bp))
3705                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3706                                              &systime_cycles);
3707         else
3708                 systime_cycles = bnxt_cc_read(bp);
3709
3710         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3711         *ts = rte_ns_to_timespec(ns);
3712
3713         return rc;
3714 }
3715 static int
3716 bnxt_timesync_enable(struct rte_eth_dev *dev)
3717 {
3718         struct bnxt *bp = dev->data->dev_private;
3719         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3720         uint32_t shift = 0;
3721         int rc;
3722
3723         if (!ptp)
3724                 return 0;
3725
3726         ptp->rx_filter = 1;
3727         ptp->tx_tstamp_en = 1;
3728         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3729
3730         rc = bnxt_hwrm_ptp_cfg(bp);
3731         if (rc)
3732                 return rc;
3733
3734         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3735         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3736         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3737
3738         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3739         ptp->tc.cc_shift = shift;
3740         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3741
3742         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3743         ptp->rx_tstamp_tc.cc_shift = shift;
3744         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3745
3746         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3747         ptp->tx_tstamp_tc.cc_shift = shift;
3748         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3749
3750         if (!BNXT_CHIP_THOR(bp))
3751                 bnxt_map_ptp_regs(bp);
3752
3753         return 0;
3754 }
3755
3756 static int
3757 bnxt_timesync_disable(struct rte_eth_dev *dev)
3758 {
3759         struct bnxt *bp = dev->data->dev_private;
3760         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3761
3762         if (!ptp)
3763                 return 0;
3764
3765         ptp->rx_filter = 0;
3766         ptp->tx_tstamp_en = 0;
3767         ptp->rxctl = 0;
3768
3769         bnxt_hwrm_ptp_cfg(bp);
3770
3771         if (!BNXT_CHIP_THOR(bp))
3772                 bnxt_unmap_ptp_regs(bp);
3773
3774         return 0;
3775 }
3776
3777 static int
3778 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3779                                  struct timespec *timestamp,
3780                                  uint32_t flags __rte_unused)
3781 {
3782         struct bnxt *bp = dev->data->dev_private;
3783         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3784         uint64_t rx_tstamp_cycles = 0;
3785         uint64_t ns;
3786
3787         if (!ptp)
3788                 return 0;
3789
3790         if (BNXT_CHIP_THOR(bp))
3791                 rx_tstamp_cycles = ptp->rx_timestamp;
3792         else
3793                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3794
3795         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3796         *timestamp = rte_ns_to_timespec(ns);
3797         return  0;
3798 }
3799
3800 static int
3801 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3802                                  struct timespec *timestamp)
3803 {
3804         struct bnxt *bp = dev->data->dev_private;
3805         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3806         uint64_t tx_tstamp_cycles = 0;
3807         uint64_t ns;
3808         int rc = 0;
3809
3810         if (!ptp)
3811                 return 0;
3812
3813         if (BNXT_CHIP_THOR(bp))
3814                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3815                                              &tx_tstamp_cycles);
3816         else
3817                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3818
3819         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3820         *timestamp = rte_ns_to_timespec(ns);
3821
3822         return rc;
3823 }
3824
3825 static int
3826 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3827 {
3828         struct bnxt *bp = dev->data->dev_private;
3829         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3830
3831         if (!ptp)
3832                 return 0;
3833
3834         ptp->tc.nsec += delta;
3835
3836         return 0;
3837 }
3838
3839 static int
3840 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3841 {
3842         struct bnxt *bp = dev->data->dev_private;
3843         int rc;
3844         uint32_t dir_entries;
3845         uint32_t entry_length;
3846
3847         rc = is_bnxt_in_error(bp);
3848         if (rc)
3849                 return rc;
3850
3851         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3852                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3853                     bp->pdev->addr.devid, bp->pdev->addr.function);
3854
3855         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3856         if (rc != 0)
3857                 return rc;
3858
3859         return dir_entries * entry_length;
3860 }
3861
3862 static int
3863 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3864                 struct rte_dev_eeprom_info *in_eeprom)
3865 {
3866         struct bnxt *bp = dev->data->dev_private;
3867         uint32_t index;
3868         uint32_t offset;
3869         int rc;
3870
3871         rc = is_bnxt_in_error(bp);
3872         if (rc)
3873                 return rc;
3874
3875         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3876                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3877                     bp->pdev->addr.devid, bp->pdev->addr.function,
3878                     in_eeprom->offset, in_eeprom->length);
3879
3880         if (in_eeprom->offset == 0) /* special offset value to get directory */
3881                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3882                                                 in_eeprom->data);
3883
3884         index = in_eeprom->offset >> 24;
3885         offset = in_eeprom->offset & 0xffffff;
3886
3887         if (index != 0)
3888                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3889                                            in_eeprom->length, in_eeprom->data);
3890
3891         return 0;
3892 }
3893
3894 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3895 {
3896         switch (dir_type) {
3897         case BNX_DIR_TYPE_CHIMP_PATCH:
3898         case BNX_DIR_TYPE_BOOTCODE:
3899         case BNX_DIR_TYPE_BOOTCODE_2:
3900         case BNX_DIR_TYPE_APE_FW:
3901         case BNX_DIR_TYPE_APE_PATCH:
3902         case BNX_DIR_TYPE_KONG_FW:
3903         case BNX_DIR_TYPE_KONG_PATCH:
3904         case BNX_DIR_TYPE_BONO_FW:
3905         case BNX_DIR_TYPE_BONO_PATCH:
3906                 /* FALLTHROUGH */
3907                 return true;
3908         }
3909
3910         return false;
3911 }
3912
3913 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3914 {
3915         switch (dir_type) {
3916         case BNX_DIR_TYPE_AVS:
3917         case BNX_DIR_TYPE_EXP_ROM_MBA:
3918         case BNX_DIR_TYPE_PCIE:
3919         case BNX_DIR_TYPE_TSCF_UCODE:
3920         case BNX_DIR_TYPE_EXT_PHY:
3921         case BNX_DIR_TYPE_CCM:
3922         case BNX_DIR_TYPE_ISCSI_BOOT:
3923         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3924         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3925                 /* FALLTHROUGH */
3926                 return true;
3927         }
3928
3929         return false;
3930 }
3931
3932 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3933 {
3934         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3935                 bnxt_dir_type_is_other_exec_format(dir_type);
3936 }
3937
3938 static int
3939 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3940                 struct rte_dev_eeprom_info *in_eeprom)
3941 {
3942         struct bnxt *bp = dev->data->dev_private;
3943         uint8_t index, dir_op;
3944         uint16_t type, ext, ordinal, attr;
3945         int rc;
3946
3947         rc = is_bnxt_in_error(bp);
3948         if (rc)
3949                 return rc;
3950
3951         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3952                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3953                     bp->pdev->addr.devid, bp->pdev->addr.function,
3954                     in_eeprom->offset, in_eeprom->length);
3955
3956         if (!BNXT_PF(bp)) {
3957                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3958                 return -EINVAL;
3959         }
3960
3961         type = in_eeprom->magic >> 16;
3962
3963         if (type == 0xffff) { /* special value for directory operations */
3964                 index = in_eeprom->magic & 0xff;
3965                 dir_op = in_eeprom->magic >> 8;
3966                 if (index == 0)
3967                         return -EINVAL;
3968                 switch (dir_op) {
3969                 case 0x0e: /* erase */
3970                         if (in_eeprom->offset != ~in_eeprom->magic)
3971                                 return -EINVAL;
3972                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3973                 default:
3974                         return -EINVAL;
3975                 }
3976         }
3977
3978         /* Create or re-write an NVM item: */
3979         if (bnxt_dir_type_is_executable(type) == true)
3980                 return -EOPNOTSUPP;
3981         ext = in_eeprom->magic & 0xffff;
3982         ordinal = in_eeprom->offset >> 16;
3983         attr = in_eeprom->offset & 0xffff;
3984
3985         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3986                                      in_eeprom->data, in_eeprom->length);
3987 }
3988
3989 /*
3990  * Initialization
3991  */
3992
3993 static const struct eth_dev_ops bnxt_dev_ops = {
3994         .dev_infos_get = bnxt_dev_info_get_op,
3995         .dev_close = bnxt_dev_close_op,
3996         .dev_configure = bnxt_dev_configure_op,
3997         .dev_start = bnxt_dev_start_op,
3998         .dev_stop = bnxt_dev_stop_op,
3999         .dev_set_link_up = bnxt_dev_set_link_up_op,
4000         .dev_set_link_down = bnxt_dev_set_link_down_op,
4001         .stats_get = bnxt_stats_get_op,
4002         .stats_reset = bnxt_stats_reset_op,
4003         .rx_queue_setup = bnxt_rx_queue_setup_op,
4004         .rx_queue_release = bnxt_rx_queue_release_op,
4005         .tx_queue_setup = bnxt_tx_queue_setup_op,
4006         .tx_queue_release = bnxt_tx_queue_release_op,
4007         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4008         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4009         .reta_update = bnxt_reta_update_op,
4010         .reta_query = bnxt_reta_query_op,
4011         .rss_hash_update = bnxt_rss_hash_update_op,
4012         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4013         .link_update = bnxt_link_update_op,
4014         .promiscuous_enable = bnxt_promiscuous_enable_op,
4015         .promiscuous_disable = bnxt_promiscuous_disable_op,
4016         .allmulticast_enable = bnxt_allmulticast_enable_op,
4017         .allmulticast_disable = bnxt_allmulticast_disable_op,
4018         .mac_addr_add = bnxt_mac_addr_add_op,
4019         .mac_addr_remove = bnxt_mac_addr_remove_op,
4020         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4021         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4022         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4023         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4024         .vlan_filter_set = bnxt_vlan_filter_set_op,
4025         .vlan_offload_set = bnxt_vlan_offload_set_op,
4026         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4027         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4028         .mtu_set = bnxt_mtu_set_op,
4029         .mac_addr_set = bnxt_set_default_mac_addr_op,
4030         .xstats_get = bnxt_dev_xstats_get_op,
4031         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4032         .xstats_reset = bnxt_dev_xstats_reset_op,
4033         .fw_version_get = bnxt_fw_version_get,
4034         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4035         .rxq_info_get = bnxt_rxq_info_get_op,
4036         .txq_info_get = bnxt_txq_info_get_op,
4037         .dev_led_on = bnxt_dev_led_on_op,
4038         .dev_led_off = bnxt_dev_led_off_op,
4039         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4040         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4041         .rx_queue_count = bnxt_rx_queue_count_op,
4042         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4043         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4044         .rx_queue_start = bnxt_rx_queue_start,
4045         .rx_queue_stop = bnxt_rx_queue_stop,
4046         .tx_queue_start = bnxt_tx_queue_start,
4047         .tx_queue_stop = bnxt_tx_queue_stop,
4048         .filter_ctrl = bnxt_filter_ctrl_op,
4049         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4050         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4051         .get_eeprom           = bnxt_get_eeprom_op,
4052         .set_eeprom           = bnxt_set_eeprom_op,
4053         .timesync_enable      = bnxt_timesync_enable,
4054         .timesync_disable     = bnxt_timesync_disable,
4055         .timesync_read_time   = bnxt_timesync_read_time,
4056         .timesync_write_time   = bnxt_timesync_write_time,
4057         .timesync_adjust_time = bnxt_timesync_adjust_time,
4058         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4059         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4060 };
4061
4062 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4063 {
4064         uint32_t offset;
4065
4066         /* Only pre-map the reset GRC registers using window 3 */
4067         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4068                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4069
4070         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4071
4072         return offset;
4073 }
4074
4075 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4076 {
4077         struct bnxt_error_recovery_info *info = bp->recovery_info;
4078         uint32_t reg_base = 0xffffffff;
4079         int i;
4080
4081         /* Only pre-map the monitoring GRC registers using window 2 */
4082         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4083                 uint32_t reg = info->status_regs[i];
4084
4085                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4086                         continue;
4087
4088                 if (reg_base == 0xffffffff)
4089                         reg_base = reg & 0xfffff000;
4090                 if ((reg & 0xfffff000) != reg_base)
4091                         return -ERANGE;
4092
4093                 /* Use mask 0xffc as the Lower 2 bits indicates
4094                  * address space location
4095                  */
4096                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4097                                                 (reg & 0xffc);
4098         }
4099
4100         if (reg_base == 0xffffffff)
4101                 return 0;
4102
4103         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4104                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4105
4106         return 0;
4107 }
4108
4109 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4110 {
4111         struct bnxt_error_recovery_info *info = bp->recovery_info;
4112         uint32_t delay = info->delay_after_reset[index];
4113         uint32_t val = info->reset_reg_val[index];
4114         uint32_t reg = info->reset_reg[index];
4115         uint32_t type, offset;
4116
4117         type = BNXT_FW_STATUS_REG_TYPE(reg);
4118         offset = BNXT_FW_STATUS_REG_OFF(reg);
4119
4120         switch (type) {
4121         case BNXT_FW_STATUS_REG_TYPE_CFG:
4122                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4123                 break;
4124         case BNXT_FW_STATUS_REG_TYPE_GRC:
4125                 offset = bnxt_map_reset_regs(bp, offset);
4126                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4127                 break;
4128         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4129                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4130                 break;
4131         }
4132         /* wait on a specific interval of time until core reset is complete */
4133         if (delay)
4134                 rte_delay_ms(delay);
4135 }
4136
4137 static void bnxt_dev_cleanup(struct bnxt *bp)
4138 {
4139         bnxt_set_hwrm_link_config(bp, false);
4140         bp->link_info.link_up = 0;
4141         if (bp->eth_dev->data->dev_started)
4142                 bnxt_dev_stop_op(bp->eth_dev);
4143
4144         bnxt_uninit_resources(bp, true);
4145 }
4146
4147 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4148 {
4149         struct rte_eth_dev *dev = bp->eth_dev;
4150         struct rte_vlan_filter_conf *vfc;
4151         int vidx, vbit, rc;
4152         uint16_t vlan_id;
4153
4154         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4155                 vfc = &dev->data->vlan_filter_conf;
4156                 vidx = vlan_id / 64;
4157                 vbit = vlan_id % 64;
4158
4159                 /* Each bit corresponds to a VLAN id */
4160                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4161                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4162                         if (rc)
4163                                 return rc;
4164                 }
4165         }
4166
4167         return 0;
4168 }
4169
4170 static int bnxt_restore_mac_filters(struct bnxt *bp)
4171 {
4172         struct rte_eth_dev *dev = bp->eth_dev;
4173         struct rte_eth_dev_info dev_info;
4174         struct rte_ether_addr *addr;
4175         uint64_t pool_mask;
4176         uint32_t pool = 0;
4177         uint16_t i;
4178         int rc;
4179
4180         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4181                 return 0;
4182
4183         rc = bnxt_dev_info_get_op(dev, &dev_info);
4184         if (rc)
4185                 return rc;
4186
4187         /* replay MAC address configuration */
4188         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4189                 addr = &dev->data->mac_addrs[i];
4190
4191                 /* skip zero address */
4192                 if (rte_is_zero_ether_addr(addr))
4193                         continue;
4194
4195                 pool = 0;
4196                 pool_mask = dev->data->mac_pool_sel[i];
4197
4198                 do {
4199                         if (pool_mask & 1ULL) {
4200                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4201                                 if (rc)
4202                                         return rc;
4203                         }
4204                         pool_mask >>= 1;
4205                         pool++;
4206                 } while (pool_mask);
4207         }
4208
4209         return 0;
4210 }
4211
4212 static int bnxt_restore_filters(struct bnxt *bp)
4213 {
4214         struct rte_eth_dev *dev = bp->eth_dev;
4215         int ret = 0;
4216
4217         if (dev->data->all_multicast) {
4218                 ret = bnxt_allmulticast_enable_op(dev);
4219                 if (ret)
4220                         return ret;
4221         }
4222         if (dev->data->promiscuous) {
4223                 ret = bnxt_promiscuous_enable_op(dev);
4224                 if (ret)
4225                         return ret;
4226         }
4227
4228         ret = bnxt_restore_mac_filters(bp);
4229         if (ret)
4230                 return ret;
4231
4232         ret = bnxt_restore_vlan_filters(bp);
4233         /* TODO restore other filters as well */
4234         return ret;
4235 }
4236
4237 static void bnxt_dev_recover(void *arg)
4238 {
4239         struct bnxt *bp = arg;
4240         int timeout = bp->fw_reset_max_msecs;
4241         int rc = 0;
4242
4243         /* Clear Error flag so that device re-init should happen */
4244         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4245
4246         do {
4247                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4248                 if (rc == 0)
4249                         break;
4250                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4251                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4252         } while (rc && timeout);
4253
4254         if (rc) {
4255                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4256                 goto err;
4257         }
4258
4259         rc = bnxt_init_resources(bp, true);
4260         if (rc) {
4261                 PMD_DRV_LOG(ERR,
4262                             "Failed to initialize resources after reset\n");
4263                 goto err;
4264         }
4265         /* clear reset flag as the device is initialized now */
4266         bp->flags &= ~BNXT_FLAG_FW_RESET;
4267
4268         rc = bnxt_dev_start_op(bp->eth_dev);
4269         if (rc) {
4270                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4271                 goto err_start;
4272         }
4273
4274         rc = bnxt_restore_filters(bp);
4275         if (rc)
4276                 goto err_start;
4277
4278         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4279         return;
4280 err_start:
4281         bnxt_dev_stop_op(bp->eth_dev);
4282 err:
4283         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4284         bnxt_uninit_resources(bp, false);
4285         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4286 }
4287
4288 void bnxt_dev_reset_and_resume(void *arg)
4289 {
4290         struct bnxt *bp = arg;
4291         int rc;
4292
4293         bnxt_dev_cleanup(bp);
4294
4295         bnxt_wait_for_device_shutdown(bp);
4296
4297         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4298                                bnxt_dev_recover, (void *)bp);
4299         if (rc)
4300                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4301 }
4302
4303 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4304 {
4305         struct bnxt_error_recovery_info *info = bp->recovery_info;
4306         uint32_t reg = info->status_regs[index];
4307         uint32_t type, offset, val = 0;
4308
4309         type = BNXT_FW_STATUS_REG_TYPE(reg);
4310         offset = BNXT_FW_STATUS_REG_OFF(reg);
4311
4312         switch (type) {
4313         case BNXT_FW_STATUS_REG_TYPE_CFG:
4314                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4315                 break;
4316         case BNXT_FW_STATUS_REG_TYPE_GRC:
4317                 offset = info->mapped_status_regs[index];
4318                 /* FALLTHROUGH */
4319         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4320                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4321                                        offset));
4322                 break;
4323         }
4324
4325         return val;
4326 }
4327
4328 static int bnxt_fw_reset_all(struct bnxt *bp)
4329 {
4330         struct bnxt_error_recovery_info *info = bp->recovery_info;
4331         uint32_t i;
4332         int rc = 0;
4333
4334         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4335                 /* Reset through master function driver */
4336                 for (i = 0; i < info->reg_array_cnt; i++)
4337                         bnxt_write_fw_reset_reg(bp, i);
4338                 /* Wait for time specified by FW after triggering reset */
4339                 rte_delay_ms(info->master_func_wait_period_after_reset);
4340         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4341                 /* Reset with the help of Kong processor */
4342                 rc = bnxt_hwrm_fw_reset(bp);
4343                 if (rc)
4344                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4345         }
4346
4347         return rc;
4348 }
4349
4350 static void bnxt_fw_reset_cb(void *arg)
4351 {
4352         struct bnxt *bp = arg;
4353         struct bnxt_error_recovery_info *info = bp->recovery_info;
4354         int rc = 0;
4355
4356         /* Only Master function can do FW reset */
4357         if (bnxt_is_master_func(bp) &&
4358             bnxt_is_recovery_enabled(bp)) {
4359                 rc = bnxt_fw_reset_all(bp);
4360                 if (rc) {
4361                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4362                         return;
4363                 }
4364         }
4365
4366         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4367          * EXCEPTION_FATAL_ASYNC event to all the functions
4368          * (including MASTER FUNC). After receiving this Async, all the active
4369          * drivers should treat this case as FW initiated recovery
4370          */
4371         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4372                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4373                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4374
4375                 /* To recover from error */
4376                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4377                                   (void *)bp);
4378         }
4379 }
4380
4381 /* Driver should poll FW heartbeat, reset_counter with the frequency
4382  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4383  * When the driver detects heartbeat stop or change in reset_counter,
4384  * it has to trigger a reset to recover from the error condition.
4385  * A “master PF” is the function who will have the privilege to
4386  * initiate the chimp reset. The master PF will be elected by the
4387  * firmware and will be notified through async message.
4388  */
4389 static void bnxt_check_fw_health(void *arg)
4390 {
4391         struct bnxt *bp = arg;
4392         struct bnxt_error_recovery_info *info = bp->recovery_info;
4393         uint32_t val = 0, wait_msec;
4394
4395         if (!info || !bnxt_is_recovery_enabled(bp) ||
4396             is_bnxt_in_error(bp))
4397                 return;
4398
4399         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4400         if (val == info->last_heart_beat)
4401                 goto reset;
4402
4403         info->last_heart_beat = val;
4404
4405         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4406         if (val != info->last_reset_counter)
4407                 goto reset;
4408
4409         info->last_reset_counter = val;
4410
4411         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4412                           bnxt_check_fw_health, (void *)bp);
4413
4414         return;
4415 reset:
4416         /* Stop DMA to/from device */
4417         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4418         bp->flags |= BNXT_FLAG_FW_RESET;
4419
4420         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4421
4422         if (bnxt_is_master_func(bp))
4423                 wait_msec = info->master_func_wait_period;
4424         else
4425                 wait_msec = info->normal_func_wait_period;
4426
4427         rte_eal_alarm_set(US_PER_MS * wait_msec,
4428                           bnxt_fw_reset_cb, (void *)bp);
4429 }
4430
4431 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4432 {
4433         uint32_t polling_freq;
4434
4435         if (!bnxt_is_recovery_enabled(bp))
4436                 return;
4437
4438         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4439                 return;
4440
4441         polling_freq = bp->recovery_info->driver_polling_freq;
4442
4443         rte_eal_alarm_set(US_PER_MS * polling_freq,
4444                           bnxt_check_fw_health, (void *)bp);
4445         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4446 }
4447
4448 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4449 {
4450         if (!bnxt_is_recovery_enabled(bp))
4451                 return;
4452
4453         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4454         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4455 }
4456
4457 static bool bnxt_vf_pciid(uint16_t device_id)
4458 {
4459         switch (device_id) {
4460         case BROADCOM_DEV_ID_57304_VF:
4461         case BROADCOM_DEV_ID_57406_VF:
4462         case BROADCOM_DEV_ID_5731X_VF:
4463         case BROADCOM_DEV_ID_5741X_VF:
4464         case BROADCOM_DEV_ID_57414_VF:
4465         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4466         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4467         case BROADCOM_DEV_ID_58802_VF:
4468         case BROADCOM_DEV_ID_57500_VF1:
4469         case BROADCOM_DEV_ID_57500_VF2:
4470                 /* FALLTHROUGH */
4471                 return true;
4472         default:
4473                 return false;
4474         }
4475 }
4476
4477 static bool bnxt_thor_device(uint16_t device_id)
4478 {
4479         switch (device_id) {
4480         case BROADCOM_DEV_ID_57508:
4481         case BROADCOM_DEV_ID_57504:
4482         case BROADCOM_DEV_ID_57502:
4483         case BROADCOM_DEV_ID_57508_MF1:
4484         case BROADCOM_DEV_ID_57504_MF1:
4485         case BROADCOM_DEV_ID_57502_MF1:
4486         case BROADCOM_DEV_ID_57508_MF2:
4487         case BROADCOM_DEV_ID_57504_MF2:
4488         case BROADCOM_DEV_ID_57502_MF2:
4489         case BROADCOM_DEV_ID_57500_VF1:
4490         case BROADCOM_DEV_ID_57500_VF2:
4491                 /* FALLTHROUGH */
4492                 return true;
4493         default:
4494                 return false;
4495         }
4496 }
4497
4498 bool bnxt_stratus_device(struct bnxt *bp)
4499 {
4500         uint16_t device_id = bp->pdev->id.device_id;
4501
4502         switch (device_id) {
4503         case BROADCOM_DEV_ID_STRATUS_NIC:
4504         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4505         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4506                 /* FALLTHROUGH */
4507                 return true;
4508         default:
4509                 return false;
4510         }
4511 }
4512
4513 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4514 {
4515         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4516         struct bnxt *bp = eth_dev->data->dev_private;
4517
4518         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4519         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4520         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4521         if (!bp->bar0 || !bp->doorbell_base) {
4522                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4523                 return -ENODEV;
4524         }
4525
4526         bp->eth_dev = eth_dev;
4527         bp->pdev = pci_dev;
4528
4529         return 0;
4530 }
4531
4532 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4533                                   struct bnxt_ctx_pg_info *ctx_pg,
4534                                   uint32_t mem_size,
4535                                   const char *suffix,
4536                                   uint16_t idx)
4537 {
4538         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4539         const struct rte_memzone *mz = NULL;
4540         char mz_name[RTE_MEMZONE_NAMESIZE];
4541         rte_iova_t mz_phys_addr;
4542         uint64_t valid_bits = 0;
4543         uint32_t sz;
4544         int i;
4545
4546         if (!mem_size)
4547                 return 0;
4548
4549         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4550                          BNXT_PAGE_SIZE;
4551         rmem->page_size = BNXT_PAGE_SIZE;
4552         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4553         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4554         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4555
4556         valid_bits = PTU_PTE_VALID;
4557
4558         if (rmem->nr_pages > 1) {
4559                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4560                          "bnxt_ctx_pg_tbl%s_%x_%d",
4561                          suffix, idx, bp->eth_dev->data->port_id);
4562                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4563                 mz = rte_memzone_lookup(mz_name);
4564                 if (!mz) {
4565                         mz = rte_memzone_reserve_aligned(mz_name,
4566                                                 rmem->nr_pages * 8,
4567                                                 SOCKET_ID_ANY,
4568                                                 RTE_MEMZONE_2MB |
4569                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4570                                                 RTE_MEMZONE_IOVA_CONTIG,
4571                                                 BNXT_PAGE_SIZE);
4572                         if (mz == NULL)
4573                                 return -ENOMEM;
4574                 }
4575
4576                 memset(mz->addr, 0, mz->len);
4577                 mz_phys_addr = mz->iova;
4578
4579                 rmem->pg_tbl = mz->addr;
4580                 rmem->pg_tbl_map = mz_phys_addr;
4581                 rmem->pg_tbl_mz = mz;
4582         }
4583
4584         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4585                  suffix, idx, bp->eth_dev->data->port_id);
4586         mz = rte_memzone_lookup(mz_name);
4587         if (!mz) {
4588                 mz = rte_memzone_reserve_aligned(mz_name,
4589                                                  mem_size,
4590                                                  SOCKET_ID_ANY,
4591                                                  RTE_MEMZONE_1GB |
4592                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4593                                                  RTE_MEMZONE_IOVA_CONTIG,
4594                                                  BNXT_PAGE_SIZE);
4595                 if (mz == NULL)
4596                         return -ENOMEM;
4597         }
4598
4599         memset(mz->addr, 0, mz->len);
4600         mz_phys_addr = mz->iova;
4601
4602         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4603                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4604                 rmem->dma_arr[i] = mz_phys_addr + sz;
4605
4606                 if (rmem->nr_pages > 1) {
4607                         if (i == rmem->nr_pages - 2 &&
4608                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4609                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4610                         else if (i == rmem->nr_pages - 1 &&
4611                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4612                                 valid_bits |= PTU_PTE_LAST;
4613
4614                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4615                                                            valid_bits);
4616                 }
4617         }
4618
4619         rmem->mz = mz;
4620         if (rmem->vmem_size)
4621                 rmem->vmem = (void **)mz->addr;
4622         rmem->dma_arr[0] = mz_phys_addr;
4623         return 0;
4624 }
4625
4626 static void bnxt_free_ctx_mem(struct bnxt *bp)
4627 {
4628         int i;
4629
4630         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4631                 return;
4632
4633         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4634         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4635         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4636         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4637         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4638         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4639         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4640         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4641         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4642         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4643         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4644
4645         for (i = 0; i < BNXT_MAX_Q; i++) {
4646                 if (bp->ctx->tqm_mem[i])
4647                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4648         }
4649
4650         rte_free(bp->ctx);
4651         bp->ctx = NULL;
4652 }
4653
4654 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4655
4656 #define min_t(type, x, y) ({                    \
4657         type __min1 = (x);                      \
4658         type __min2 = (y);                      \
4659         __min1 < __min2 ? __min1 : __min2; })
4660
4661 #define max_t(type, x, y) ({                    \
4662         type __max1 = (x);                      \
4663         type __max2 = (y);                      \
4664         __max1 > __max2 ? __max1 : __max2; })
4665
4666 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4667
4668 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4669 {
4670         struct bnxt_ctx_pg_info *ctx_pg;
4671         struct bnxt_ctx_mem_info *ctx;
4672         uint32_t mem_size, ena, entries;
4673         int i, rc;
4674
4675         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4676         if (rc) {
4677                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4678                 return rc;
4679         }
4680         ctx = bp->ctx;
4681         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4682                 return 0;
4683
4684         ctx_pg = &ctx->qp_mem;
4685         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4686         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4687         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4688         if (rc)
4689                 return rc;
4690
4691         ctx_pg = &ctx->srq_mem;
4692         ctx_pg->entries = ctx->srq_max_l2_entries;
4693         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4694         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4695         if (rc)
4696                 return rc;
4697
4698         ctx_pg = &ctx->cq_mem;
4699         ctx_pg->entries = ctx->cq_max_l2_entries;
4700         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4701         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4702         if (rc)
4703                 return rc;
4704
4705         ctx_pg = &ctx->vnic_mem;
4706         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4707                 ctx->vnic_max_ring_table_entries;
4708         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4709         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4710         if (rc)
4711                 return rc;
4712
4713         ctx_pg = &ctx->stat_mem;
4714         ctx_pg->entries = ctx->stat_max_entries;
4715         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4716         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4717         if (rc)
4718                 return rc;
4719
4720         entries = ctx->qp_max_l2_entries +
4721                   ctx->vnic_max_vnic_entries +
4722                   ctx->tqm_min_entries_per_ring;
4723         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4724         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4725                           ctx->tqm_max_entries_per_ring);
4726         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4727                 ctx_pg = ctx->tqm_mem[i];
4728                 /* use min tqm entries for now. */
4729                 ctx_pg->entries = entries;
4730                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4731                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4732                 if (rc)
4733                         return rc;
4734                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4735         }
4736
4737         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4738         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4739         if (rc)
4740                 PMD_DRV_LOG(ERR,
4741                             "Failed to configure context mem: rc = %d\n", rc);
4742         else
4743                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4744
4745         return rc;
4746 }
4747
4748 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4749 {
4750         struct rte_pci_device *pci_dev = bp->pdev;
4751         char mz_name[RTE_MEMZONE_NAMESIZE];
4752         const struct rte_memzone *mz = NULL;
4753         uint32_t total_alloc_len;
4754         rte_iova_t mz_phys_addr;
4755
4756         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4757                 return 0;
4758
4759         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4760                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4761                  pci_dev->addr.bus, pci_dev->addr.devid,
4762                  pci_dev->addr.function, "rx_port_stats");
4763         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4764         mz = rte_memzone_lookup(mz_name);
4765         total_alloc_len =
4766                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4767                                        sizeof(struct rx_port_stats_ext) + 512);
4768         if (!mz) {
4769                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4770                                          SOCKET_ID_ANY,
4771                                          RTE_MEMZONE_2MB |
4772                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4773                                          RTE_MEMZONE_IOVA_CONTIG);
4774                 if (mz == NULL)
4775                         return -ENOMEM;
4776         }
4777         memset(mz->addr, 0, mz->len);
4778         mz_phys_addr = mz->iova;
4779
4780         bp->rx_mem_zone = (const void *)mz;
4781         bp->hw_rx_port_stats = mz->addr;
4782         bp->hw_rx_port_stats_map = mz_phys_addr;
4783
4784         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4785                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4786                  pci_dev->addr.bus, pci_dev->addr.devid,
4787                  pci_dev->addr.function, "tx_port_stats");
4788         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4789         mz = rte_memzone_lookup(mz_name);
4790         total_alloc_len =
4791                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4792                                        sizeof(struct tx_port_stats_ext) + 512);
4793         if (!mz) {
4794                 mz = rte_memzone_reserve(mz_name,
4795                                          total_alloc_len,
4796                                          SOCKET_ID_ANY,
4797                                          RTE_MEMZONE_2MB |
4798                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4799                                          RTE_MEMZONE_IOVA_CONTIG);
4800                 if (mz == NULL)
4801                         return -ENOMEM;
4802         }
4803         memset(mz->addr, 0, mz->len);
4804         mz_phys_addr = mz->iova;
4805
4806         bp->tx_mem_zone = (const void *)mz;
4807         bp->hw_tx_port_stats = mz->addr;
4808         bp->hw_tx_port_stats_map = mz_phys_addr;
4809         bp->flags |= BNXT_FLAG_PORT_STATS;
4810
4811         /* Display extended statistics if FW supports it */
4812         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4813             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4814             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4815                 return 0;
4816
4817         bp->hw_rx_port_stats_ext = (void *)
4818                 ((uint8_t *)bp->hw_rx_port_stats +
4819                  sizeof(struct rx_port_stats));
4820         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4821                 sizeof(struct rx_port_stats);
4822         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4823
4824         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4825             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4826                 bp->hw_tx_port_stats_ext = (void *)
4827                         ((uint8_t *)bp->hw_tx_port_stats +
4828                          sizeof(struct tx_port_stats));
4829                 bp->hw_tx_port_stats_ext_map =
4830                         bp->hw_tx_port_stats_map +
4831                         sizeof(struct tx_port_stats);
4832                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4833         }
4834
4835         return 0;
4836 }
4837
4838 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4839 {
4840         struct bnxt *bp = eth_dev->data->dev_private;
4841         int rc = 0;
4842
4843         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4844                                                RTE_ETHER_ADDR_LEN *
4845                                                bp->max_l2_ctx,
4846                                                0);
4847         if (eth_dev->data->mac_addrs == NULL) {
4848                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4849                 return -ENOMEM;
4850         }
4851
4852         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4853                 if (BNXT_PF(bp))
4854                         return -EINVAL;
4855
4856                 /* Generate a random MAC address, if none was assigned by PF */
4857                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4858                 bnxt_eth_hw_addr_random(bp->mac_addr);
4859                 PMD_DRV_LOG(INFO,
4860                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4861                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4862                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4863
4864                 rc = bnxt_hwrm_set_mac(bp);
4865                 if (!rc)
4866                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4867                                RTE_ETHER_ADDR_LEN);
4868                 return rc;
4869         }
4870
4871         /* Copy the permanent MAC from the FUNC_QCAPS response */
4872         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4873         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4874
4875         return rc;
4876 }
4877
4878 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4879 {
4880         int rc = 0;
4881
4882         /* MAC is already configured in FW */
4883         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4884                 return 0;
4885
4886         /* Restore the old MAC configured */
4887         rc = bnxt_hwrm_set_mac(bp);
4888         if (rc)
4889                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4890
4891         return rc;
4892 }
4893
4894 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4895 {
4896         if (!BNXT_PF(bp))
4897                 return;
4898
4899 #define ALLOW_FUNC(x)   \
4900         { \
4901                 uint32_t arg = (x); \
4902                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4903                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4904         }
4905
4906         /* Forward all requests if firmware is new enough */
4907         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4908              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4909             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4910                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4911         } else {
4912                 PMD_DRV_LOG(WARNING,
4913                             "Firmware too old for VF mailbox functionality\n");
4914                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4915         }
4916
4917         /*
4918          * The following are used for driver cleanup. If we disallow these,
4919          * VF drivers can't clean up cleanly.
4920          */
4921         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4922         ALLOW_FUNC(HWRM_VNIC_FREE);
4923         ALLOW_FUNC(HWRM_RING_FREE);
4924         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4925         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4926         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4927         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4928         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4929         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4930 }
4931
4932 uint16_t
4933 bnxt_get_svif(uint16_t port_id, bool func_svif)
4934 {
4935         struct rte_eth_dev *eth_dev;
4936         struct bnxt *bp;
4937
4938         eth_dev = &rte_eth_devices[port_id];
4939         bp = eth_dev->data->dev_private;
4940
4941         return func_svif ? bp->func_svif : bp->port_svif;
4942 }
4943
4944 uint16_t
4945 bnxt_get_vnic_id(uint16_t port)
4946 {
4947         struct rte_eth_dev *eth_dev;
4948         struct bnxt_vnic_info *vnic;
4949         struct bnxt *bp;
4950
4951         eth_dev = &rte_eth_devices[port];
4952         bp = eth_dev->data->dev_private;
4953
4954         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4955
4956         return vnic->fw_vnic_id;
4957 }
4958
4959 uint16_t
4960 bnxt_get_fw_func_id(uint16_t port)
4961 {
4962         struct rte_eth_dev *eth_dev;
4963         struct bnxt *bp;
4964
4965         eth_dev = &rte_eth_devices[port];
4966         bp = eth_dev->data->dev_private;
4967
4968         return bp->fw_fid;
4969 }
4970
4971 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4972 {
4973         struct bnxt_error_recovery_info *info = bp->recovery_info;
4974
4975         if (info) {
4976                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4977                         memset(info, 0, sizeof(*info));
4978                 return;
4979         }
4980
4981         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4982                 return;
4983
4984         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4985                            sizeof(*info), 0);
4986         if (!info)
4987                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4988
4989         bp->recovery_info = info;
4990 }
4991
4992 static void bnxt_check_fw_status(struct bnxt *bp)
4993 {
4994         uint32_t fw_status;
4995
4996         if (!(bp->recovery_info &&
4997               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4998                 return;
4999
5000         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5001         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5002                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5003                             fw_status);
5004 }
5005
5006 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5007 {
5008         struct bnxt_error_recovery_info *info = bp->recovery_info;
5009         uint32_t status_loc;
5010         uint32_t sig_ver;
5011
5012         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5013                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5014         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5015                                    BNXT_GRCP_WINDOW_2_BASE +
5016                                    offsetof(struct hcomm_status,
5017                                             sig_ver)));
5018         /* If the signature is absent, then FW does not support this feature */
5019         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5020             HCOMM_STATUS_SIGNATURE_VAL)
5021                 return 0;
5022
5023         if (!info) {
5024                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5025                                    sizeof(*info), 0);
5026                 if (!info)
5027                         return -ENOMEM;
5028                 bp->recovery_info = info;
5029         } else {
5030                 memset(info, 0, sizeof(*info));
5031         }
5032
5033         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5034                                       BNXT_GRCP_WINDOW_2_BASE +
5035                                       offsetof(struct hcomm_status,
5036                                                fw_status_loc)));
5037
5038         /* Only pre-map the FW health status GRC register */
5039         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5040                 return 0;
5041
5042         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5043         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5044                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5045
5046         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5047                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5048
5049         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5050
5051         return 0;
5052 }
5053
5054 static int bnxt_init_fw(struct bnxt *bp)
5055 {
5056         uint16_t mtu;
5057         int rc = 0;
5058
5059         bp->fw_cap = 0;
5060
5061         rc = bnxt_map_hcomm_fw_status_reg(bp);
5062         if (rc)
5063                 return rc;
5064
5065         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5066         if (rc) {
5067                 bnxt_check_fw_status(bp);
5068                 return rc;
5069         }
5070
5071         rc = bnxt_hwrm_func_reset(bp);
5072         if (rc)
5073                 return -EIO;
5074
5075         rc = bnxt_hwrm_vnic_qcaps(bp);
5076         if (rc)
5077                 return rc;
5078
5079         rc = bnxt_hwrm_queue_qportcfg(bp);
5080         if (rc)
5081                 return rc;
5082
5083         /* Get the MAX capabilities for this function.
5084          * This function also allocates context memory for TQM rings and
5085          * informs the firmware about this allocated backing store memory.
5086          */
5087         rc = bnxt_hwrm_func_qcaps(bp);
5088         if (rc)
5089                 return rc;
5090
5091         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5092         if (rc)
5093                 return rc;
5094
5095         bnxt_hwrm_port_mac_qcfg(bp);
5096
5097         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5098         if (rc)
5099                 return rc;
5100
5101         bnxt_alloc_error_recovery_info(bp);
5102         /* Get the adapter error recovery support info */
5103         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5104         if (rc)
5105                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5106
5107         bnxt_hwrm_port_led_qcaps(bp);
5108
5109         return 0;
5110 }
5111
5112 static int
5113 bnxt_init_locks(struct bnxt *bp)
5114 {
5115         int err;
5116
5117         err = pthread_mutex_init(&bp->flow_lock, NULL);
5118         if (err) {
5119                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5120                 return err;
5121         }
5122
5123         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5124         if (err)
5125                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5126         return err;
5127 }
5128
5129 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5130 {
5131         int rc;
5132
5133         rc = bnxt_init_fw(bp);
5134         if (rc)
5135                 return rc;
5136
5137         if (!reconfig_dev) {
5138                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5139                 if (rc)
5140                         return rc;
5141         } else {
5142                 rc = bnxt_restore_dflt_mac(bp);
5143                 if (rc)
5144                         return rc;
5145         }
5146
5147         bnxt_config_vf_req_fwd(bp);
5148
5149         rc = bnxt_hwrm_func_driver_register(bp);
5150         if (rc) {
5151                 PMD_DRV_LOG(ERR, "Failed to register driver");
5152                 return -EBUSY;
5153         }
5154
5155         if (BNXT_PF(bp)) {
5156                 if (bp->pdev->max_vfs) {
5157                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5158                         if (rc) {
5159                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5160                                 return rc;
5161                         }
5162                 } else {
5163                         rc = bnxt_hwrm_allocate_pf_only(bp);
5164                         if (rc) {
5165                                 PMD_DRV_LOG(ERR,
5166                                             "Failed to allocate PF resources");
5167                                 return rc;
5168                         }
5169                 }
5170         }
5171
5172         rc = bnxt_alloc_mem(bp, reconfig_dev);
5173         if (rc)
5174                 return rc;
5175
5176         rc = bnxt_setup_int(bp);
5177         if (rc)
5178                 return rc;
5179
5180         rc = bnxt_request_int(bp);
5181         if (rc)
5182                 return rc;
5183
5184         rc = bnxt_init_ctx_mem(bp);
5185         if (rc) {
5186                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5187                 return rc;
5188         }
5189
5190         rc = bnxt_init_locks(bp);
5191         if (rc)
5192                 return rc;
5193
5194         return 0;
5195 }
5196
5197 static int
5198 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5199                           const char *value, void *opaque_arg)
5200 {
5201         struct bnxt *bp = opaque_arg;
5202         unsigned long truflow;
5203         char *end = NULL;
5204
5205         if (!value || !opaque_arg) {
5206                 PMD_DRV_LOG(ERR,
5207                             "Invalid parameter passed to truflow devargs.\n");
5208                 return -EINVAL;
5209         }
5210
5211         truflow = strtoul(value, &end, 10);
5212         if (end == NULL || *end != '\0' ||
5213             (truflow == ULONG_MAX && errno == ERANGE)) {
5214                 PMD_DRV_LOG(ERR,
5215                             "Invalid parameter passed to truflow devargs.\n");
5216                 return -EINVAL;
5217         }
5218
5219         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5220                 PMD_DRV_LOG(ERR,
5221                             "Invalid value passed to truflow devargs.\n");
5222                 return -EINVAL;
5223         }
5224
5225         bp->truflow = truflow;
5226         if (bp->truflow)
5227                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5228
5229         return 0;
5230 }
5231
5232 static int
5233 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5234                              const char *value, void *opaque_arg)
5235 {
5236         struct bnxt *bp = opaque_arg;
5237         unsigned long flow_xstat;
5238         char *end = NULL;
5239
5240         if (!value || !opaque_arg) {
5241                 PMD_DRV_LOG(ERR,
5242                             "Invalid parameter passed to flow_xstat devarg.\n");
5243                 return -EINVAL;
5244         }
5245
5246         flow_xstat = strtoul(value, &end, 10);
5247         if (end == NULL || *end != '\0' ||
5248             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5249                 PMD_DRV_LOG(ERR,
5250                             "Invalid parameter passed to flow_xstat devarg.\n");
5251                 return -EINVAL;
5252         }
5253
5254         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5255                 PMD_DRV_LOG(ERR,
5256                             "Invalid value passed to flow_xstat devarg.\n");
5257                 return -EINVAL;
5258         }
5259
5260         bp->flow_xstat = flow_xstat;
5261         if (bp->flow_xstat)
5262                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5263
5264         return 0;
5265 }
5266
5267 static void
5268 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5269 {
5270         struct rte_kvargs *kvlist;
5271
5272         if (devargs == NULL)
5273                 return;
5274
5275         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5276         if (kvlist == NULL)
5277                 return;
5278
5279         /*
5280          * Handler for "truflow" devarg.
5281          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1”
5282          */
5283         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5284                            bnxt_parse_devarg_truflow, bp);
5285
5286         /*
5287          * Handler for "flow_xstat" devarg.
5288          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1”
5289          */
5290         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5291                            bnxt_parse_devarg_flow_xstat, bp);
5292
5293         rte_kvargs_free(kvlist);
5294 }
5295
5296 static int
5297 bnxt_dev_init(struct rte_eth_dev *eth_dev)
5298 {
5299         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5300         static int version_printed;
5301         struct bnxt *bp;
5302         int rc;
5303
5304         if (version_printed++ == 0)
5305                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5306
5307         eth_dev->dev_ops = &bnxt_dev_ops;
5308         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5309         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5310
5311         /*
5312          * For secondary processes, we don't initialise any further
5313          * as primary has already done this work.
5314          */
5315         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5316                 return 0;
5317
5318         rte_eth_copy_pci_info(eth_dev, pci_dev);
5319
5320         bp = eth_dev->data->dev_private;
5321
5322         /* Parse dev arguments passed on when starting the DPDK application. */
5323         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5324
5325         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5326
5327         if (bnxt_vf_pciid(pci_dev->id.device_id))
5328                 bp->flags |= BNXT_FLAG_VF;
5329
5330         if (bnxt_thor_device(pci_dev->id.device_id))
5331                 bp->flags |= BNXT_FLAG_THOR_CHIP;
5332
5333         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5334             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5335             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5336             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5337                 bp->flags |= BNXT_FLAG_STINGRAY;
5338
5339         rc = bnxt_init_board(eth_dev);
5340         if (rc) {
5341                 PMD_DRV_LOG(ERR,
5342                             "Failed to initialize board rc: %x\n", rc);
5343                 return rc;
5344         }
5345
5346         rc = bnxt_alloc_hwrm_resources(bp);
5347         if (rc) {
5348                 PMD_DRV_LOG(ERR,
5349                             "Failed to allocate hwrm resource rc: %x\n", rc);
5350                 goto error_free;
5351         }
5352         rc = bnxt_init_resources(bp, false);
5353         if (rc)
5354                 goto error_free;
5355
5356         rc = bnxt_alloc_stats_mem(bp);
5357         if (rc)
5358                 goto error_free;
5359
5360         /* Pass the information to the rte_eth_dev_close() that it should also
5361          * release the private port resources.
5362          */
5363         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5364
5365         PMD_DRV_LOG(INFO,
5366                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5367                     pci_dev->mem_resource[0].phys_addr,
5368                     pci_dev->mem_resource[0].addr);
5369
5370         return 0;
5371
5372 error_free:
5373         bnxt_dev_uninit(eth_dev);
5374         return rc;
5375 }
5376
5377
5378 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5379 {
5380         if (!ctx)
5381                 return;
5382
5383         if (ctx->va)
5384                 rte_free(ctx->va);
5385
5386         ctx->va = NULL;
5387         ctx->dma = RTE_BAD_IOVA;
5388         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5389 }
5390
5391 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5392 {
5393         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5394                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5395                                   bp->rx_fc_out_tbl.ctx_id,
5396                                   bp->max_fc,
5397                                   false);
5398
5399         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5400                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5401                                   bp->tx_fc_out_tbl.ctx_id,
5402                                   bp->max_fc,
5403                                   false);
5404
5405         if (bp->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5406                 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_in_tbl.ctx_id);
5407         bp->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5408
5409         if (bp->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5410                 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_out_tbl.ctx_id);
5411         bp->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5412
5413         if (bp->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5414                 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_in_tbl.ctx_id);
5415         bp->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5416
5417         if (bp->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5418                 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_out_tbl.ctx_id);
5419         bp->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5420 }
5421
5422 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5423 {
5424         bnxt_unregister_fc_ctx_mem(bp);
5425
5426         bnxt_free_ctx_mem_buf(&bp->rx_fc_in_tbl);
5427         bnxt_free_ctx_mem_buf(&bp->rx_fc_out_tbl);
5428         bnxt_free_ctx_mem_buf(&bp->tx_fc_in_tbl);
5429         bnxt_free_ctx_mem_buf(&bp->tx_fc_out_tbl);
5430 }
5431
5432 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5433 {
5434         bnxt_uninit_fc_ctx_mem(bp);
5435 }
5436
5437 static void
5438 bnxt_free_error_recovery_info(struct bnxt *bp)
5439 {
5440         rte_free(bp->recovery_info);
5441         bp->recovery_info = NULL;
5442         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5443 }
5444
5445 static void
5446 bnxt_uninit_locks(struct bnxt *bp)
5447 {
5448         pthread_mutex_destroy(&bp->flow_lock);
5449         pthread_mutex_destroy(&bp->def_cp_lock);
5450 }
5451
5452 static int
5453 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5454 {
5455         int rc;
5456
5457         bnxt_free_int(bp);
5458         bnxt_free_mem(bp, reconfig_dev);
5459         bnxt_hwrm_func_buf_unrgtr(bp);
5460         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5461         bp->flags &= ~BNXT_FLAG_REGISTERED;
5462         bnxt_free_ctx_mem(bp);
5463         if (!reconfig_dev) {
5464                 bnxt_free_hwrm_resources(bp);
5465                 bnxt_free_error_recovery_info(bp);
5466         }
5467
5468         bnxt_uninit_ctx_mem(bp);
5469
5470         bnxt_uninit_locks(bp);
5471         rte_free(bp->ptp_cfg);
5472         bp->ptp_cfg = NULL;
5473         return rc;
5474 }
5475
5476 static int
5477 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5478 {
5479         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5480                 return -EPERM;
5481
5482         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5483
5484         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5485                 bnxt_dev_close_op(eth_dev);
5486
5487         return 0;
5488 }
5489
5490 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5491         struct rte_pci_device *pci_dev)
5492 {
5493         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
5494                 bnxt_dev_init);
5495 }
5496
5497 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5498 {
5499         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
5500                 return rte_eth_dev_pci_generic_remove(pci_dev,
5501                                 bnxt_dev_uninit);
5502         else
5503                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5504 }
5505
5506 static struct rte_pci_driver bnxt_rte_pmd = {
5507         .id_table = bnxt_pci_id_map,
5508         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5509         .probe = bnxt_pci_probe,
5510         .remove = bnxt_pci_remove,
5511 };
5512
5513 static bool
5514 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5515 {
5516         if (strcmp(dev->device->driver->name, drv->driver.name))
5517                 return false;
5518
5519         return true;
5520 }
5521
5522 bool is_bnxt_supported(struct rte_eth_dev *dev)
5523 {
5524         return is_device_supported(dev, &bnxt_rte_pmd);
5525 }
5526
5527 RTE_INIT(bnxt_init_log)
5528 {
5529         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
5530         if (bnxt_logtype_driver >= 0)
5531                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
5532 }
5533
5534 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5535 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5536 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");