drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 /*
  37  * The set of PCI devices this driver supports
  38  */
  39 static const struct rte_pci_id bnxt_pci_id_map[] = {
  40         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  41                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  93         { .vendor_id = 0, /* sentinel */ },
  94 };
  95
  96 #define BNXT_ETH_RSS_SUPPORT (  \
  97         ETH_RSS_IPV4 |          \
  98         ETH_RSS_NONFRAG_IPV4_TCP |      \
  99         ETH_RSS_NONFRAG_IPV4_UDP |      \
 100         ETH_RSS_IPV6 |          \
 101         ETH_RSS_NONFRAG_IPV6_TCP |      \
 102         ETH_RSS_NONFRAG_IPV6_UDP)
 103
 104 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 105                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 106                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 108                                      DEV_TX_OFFLOAD_TCP_TSO | \
 109                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 110                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 114                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 115                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 116
 117 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 118                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 119                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 120                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 122                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 123                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 124                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 125                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 126                                      DEV_RX_OFFLOAD_TCP_LRO | \
 127                                      DEV_RX_OFFLOAD_SCATTER | \
 128                                      DEV_RX_OFFLOAD_RSS_HASH)
 129
 130 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
 131 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 132 static const char *const bnxt_dev_args[] = {
 133         BNXT_DEVARG_TRUFLOW,
 134         BNXT_DEVARG_FLOW_XSTAT,
 135         NULL
 136 };
 137
 138 /*
 139  * truflow == false to disable the feature
 140  * truflow == true to enable the feature
 141  */
 142 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 143
 144 /*
 145  * flow_xstat == false to disable the feature
 146  * flow_xstat == true to enable the feature
 147  */
 148 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 149
 150 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 151 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 152 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 153 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 154 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 155 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 156 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 157 static void bnxt_dev_recover(void *arg);
 158
 159 int is_bnxt_in_error(struct bnxt *bp)
 160 {
 161         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 162                 return -EIO;
 163         if (bp->flags & BNXT_FLAG_FW_RESET)
 164                 return -EBUSY;
 165
 166         return 0;
 167 }
 168
 169 /***********************/
 170
 171 /*
 172  * High level utility functions
 173  */
 174
 175 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 176 {
 177         if (!BNXT_CHIP_THOR(bp))
 178                 return 1;
 179
 180         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 181                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 182                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 183 }
 184
 185 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 186 {
 187         if (!BNXT_CHIP_THOR(bp))
 188                 return HW_HASH_INDEX_SIZE;
 189
 190         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 191 }
 192
 193 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 194 {
 195         bnxt_free_filter_mem(bp);
 196         bnxt_free_vnic_attributes(bp);
 197         bnxt_free_vnic_mem(bp);
 198
 199         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 200          * If the number of rings change across fw update,
 201          * we don't have much choice except to warn the user.
 202          */
 203         if (!reconfig) {
 204                 bnxt_free_stats(bp);
 205                 bnxt_free_tx_rings(bp);
 206                 bnxt_free_rx_rings(bp);
 207         }
 208         bnxt_free_async_cp_ring(bp);
 209         bnxt_free_rxtx_nq_ring(bp);
 210
 211         rte_free(bp->grp_info);
 212         bp->grp_info = NULL;
 213 }
 214
 215 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 216 {
 217         int rc;
 218
 219         rc = bnxt_alloc_ring_grps(bp);
 220         if (rc)
 221                 goto alloc_mem_err;
 222
 223         rc = bnxt_alloc_async_ring_struct(bp);
 224         if (rc)
 225                 goto alloc_mem_err;
 226
 227         rc = bnxt_alloc_vnic_mem(bp);
 228         if (rc)
 229                 goto alloc_mem_err;
 230
 231         rc = bnxt_alloc_vnic_attributes(bp);
 232         if (rc)
 233                 goto alloc_mem_err;
 234
 235         rc = bnxt_alloc_filter_mem(bp);
 236         if (rc)
 237                 goto alloc_mem_err;
 238
 239         rc = bnxt_alloc_async_cp_ring(bp);
 240         if (rc)
 241                 goto alloc_mem_err;
 242
 243         rc = bnxt_alloc_rxtx_nq_ring(bp);
 244         if (rc)
 245                 goto alloc_mem_err;
 246
 247         return 0;
 248
 249 alloc_mem_err:
 250         bnxt_free_mem(bp, reconfig);
 251         return rc;
 252 }
 253
 254 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 255 {
 256         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 257         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 258         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 259         struct bnxt_rx_queue *rxq;
 260         unsigned int j;
 261         int rc;
 262
 263         rc = bnxt_vnic_grp_alloc(bp, vnic);
 264         if (rc)
 265                 goto err_out;
 266
 267         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 268                     vnic_id, vnic, vnic->fw_grp_ids);
 269
 270         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 271         if (rc)
 272                 goto err_out;
 273
 274         /* Alloc RSS context only if RSS mode is enabled */
 275         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 276                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 277
 278                 rc = 0;
 279                 for (j = 0; j < nr_ctxs; j++) {
 280                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 281                         if (rc)
 282                                 break;
 283                 }
 284                 if (rc) {
 285                         PMD_DRV_LOG(ERR,
 286                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 287                                     vnic_id, j, rc);
 288                         goto err_out;
 289                 }
 290                 vnic->num_lb_ctxts = nr_ctxs;
 291         }
 292
 293         /*
 294          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 295          * setting is not available at this time, it will not be
 296          * configured correctly in the CFA.
 297          */
 298         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 299                 vnic->vlan_strip = true;
 300         else
 301                 vnic->vlan_strip = false;
 302
 303         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 304         if (rc)
 305                 goto err_out;
 306
 307         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 308         if (rc)
 309                 goto err_out;
 310
 311         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 312                 rxq = bp->eth_dev->data->rx_queues[j];
 313
 314                 PMD_DRV_LOG(DEBUG,
 315                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 316                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 317
 318                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 319                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 320                 else
 321                         vnic->rx_queue_cnt++;
 322         }
 323
 324         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 325
 326         rc = bnxt_vnic_rss_configure(bp, vnic);
 327         if (rc)
 328                 goto err_out;
 329
 330         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 331
 332         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 333                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 334         else
 335                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 336
 337         return 0;
 338 err_out:
 339         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 340                     vnic_id, rc);
 341         return rc;
 342 }
 343
 344 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 345 {
 346         int rc = 0;
 347
 348         rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_in_tbl.dma,
 349                                 &bp->rx_fc_in_tbl.ctx_id);
 350         if (rc)
 351                 return rc;
 352
 353         PMD_DRV_LOG(DEBUG,
 354                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 355                     " rx_fc_in_tbl.ctx_id = %d\n",
 356                     bp->rx_fc_in_tbl.va,
 357                     (void *)((uintptr_t)bp->rx_fc_in_tbl.dma),
 358                     bp->rx_fc_in_tbl.ctx_id);
 359
 360         rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_out_tbl.dma,
 361                                 &bp->rx_fc_out_tbl.ctx_id);
 362         if (rc)
 363                 return rc;
 364
 365         PMD_DRV_LOG(DEBUG,
 366                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 367                     " rx_fc_out_tbl.ctx_id = %d\n",
 368                     bp->rx_fc_out_tbl.va,
 369                     (void *)((uintptr_t)bp->rx_fc_out_tbl.dma),
 370                     bp->rx_fc_out_tbl.ctx_id);
 371
 372         rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_in_tbl.dma,
 373                                 &bp->tx_fc_in_tbl.ctx_id);
 374         if (rc)
 375                 return rc;
 376
 377         PMD_DRV_LOG(DEBUG,
 378                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 379                     " tx_fc_in_tbl.ctx_id = %d\n",
 380                     bp->tx_fc_in_tbl.va,
 381                     (void *)((uintptr_t)bp->tx_fc_in_tbl.dma),
 382                     bp->tx_fc_in_tbl.ctx_id);
 383
 384         rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_out_tbl.dma,
 385                                 &bp->tx_fc_out_tbl.ctx_id);
 386         if (rc)
 387                 return rc;
 388
 389         PMD_DRV_LOG(DEBUG,
 390                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 391                     " tx_fc_out_tbl.ctx_id = %d\n",
 392                     bp->tx_fc_out_tbl.va,
 393                     (void *)((uintptr_t)bp->tx_fc_out_tbl.dma),
 394                     bp->tx_fc_out_tbl.ctx_id);
 395
 396         memset(bp->rx_fc_out_tbl.va, 0, bp->rx_fc_out_tbl.size);
 397         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 398                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 399                                        bp->rx_fc_out_tbl.ctx_id,
 400                                        bp->max_fc,
 401                                        true);
 402         if (rc)
 403                 return rc;
 404
 405         memset(bp->tx_fc_out_tbl.va, 0, bp->tx_fc_out_tbl.size);
 406         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 407                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 408                                        bp->tx_fc_out_tbl.ctx_id,
 409                                        bp->max_fc,
 410                                        true);
 411
 412         return rc;
 413 }
 414
 415 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 416                                   struct bnxt_ctx_mem_buf_info *ctx)
 417 {
 418         if (!ctx)
 419                 return -EINVAL;
 420
 421         ctx->va = rte_zmalloc(type, size, 0);
 422         if (ctx->va == NULL)
 423                 return -ENOMEM;
 424         rte_mem_lock_page(ctx->va);
 425         ctx->size = size;
 426         ctx->dma = rte_mem_virt2iova(ctx->va);
 427         if (ctx->dma == RTE_BAD_IOVA)
 428                 return -ENOMEM;
 429
 430         return 0;
 431 }
 432
 433 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 434 {
 435         struct rte_pci_device *pdev = bp->pdev;
 436         char type[RTE_MEMZONE_NAMESIZE];
 437         uint16_t max_fc;
 438         int rc = 0;
 439
 440         max_fc = bp->max_fc;
 441
 442         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 443                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 444         /* 4 bytes for each counter-id */
 445         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->rx_fc_in_tbl);
 446         if (rc)
 447                 return rc;
 448
 449         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 450                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 451         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 452         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->rx_fc_out_tbl);
 453         if (rc)
 454                 return rc;
 455
 456         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 457                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 458         /* 4 bytes for each counter-id */
 459         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->tx_fc_in_tbl);
 460         if (rc)
 461                 return rc;
 462
 463         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 464                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 465         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 466         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->tx_fc_out_tbl);
 467         if (rc)
 468                 return rc;
 469
 470         rc = bnxt_register_fc_ctx_mem(bp);
 471
 472         return rc;
 473 }
 474
 475 static int bnxt_init_ctx_mem(struct bnxt *bp)
 476 {
 477         int rc = 0;
 478
 479         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 480             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
 481                 return 0;
 482
 483         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->max_fc);
 484         if (rc)
 485                 return rc;
 486
 487         rc = bnxt_init_fc_ctx_mem(bp);
 488
 489         return rc;
 490 }
 491
 492 static int bnxt_init_chip(struct bnxt *bp)
 493 {
 494         struct rte_eth_link new;
 495         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 496         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 497         uint32_t intr_vector = 0;
 498         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 499         uint32_t vec = BNXT_MISC_VEC_ID;
 500         unsigned int i, j;
 501         int rc;
 502
 503         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 504                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 505                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 506                 bp->flags |= BNXT_FLAG_JUMBO;
 507         } else {
 508                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 509                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 510                 bp->flags &= ~BNXT_FLAG_JUMBO;
 511         }
 512
 513         /* THOR does not support ring groups.
 514          * But we will use the array to save RSS context IDs.
 515          */
 516         if (BNXT_CHIP_THOR(bp))
 517                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 518
 519         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 520         if (rc) {
 521                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 522                 goto err_out;
 523         }
 524
 525         rc = bnxt_alloc_hwrm_rings(bp);
 526         if (rc) {
 527                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 528                 goto err_out;
 529         }
 530
 531         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 532         if (rc) {
 533                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 534                 goto err_out;
 535         }
 536
 537         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 538                 goto skip_cosq_cfg;
 539
 540         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 541                 if (bp->rx_cos_queue[i].id != 0xff) {
 542                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 543
 544                         if (!vnic) {
 545                                 PMD_DRV_LOG(ERR,
 546                                             "Num pools more than FW profile\n");
 547                                 rc = -EINVAL;
 548                                 goto err_out;
 549                         }
 550                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 551                         bp->rx_cosq_cnt++;
 552                 }
 553         }
 554
 555 skip_cosq_cfg:
 556         rc = bnxt_mq_rx_configure(bp);
 557         if (rc) {
 558                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 559                 goto err_out;
 560         }
 561
 562         /* VNIC configuration */
 563         for (i = 0; i < bp->nr_vnics; i++) {
 564                 rc = bnxt_setup_one_vnic(bp, i);
 565                 if (rc)
 566                         goto err_out;
 567         }
 568
 569         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 570         if (rc) {
 571                 PMD_DRV_LOG(ERR,
 572                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 573                 goto err_out;
 574         }
 575
 576         /* check and configure queue intr-vector mapping */
 577         if ((rte_intr_cap_multiple(intr_handle) ||
 578              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 579             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 580                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 581                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 582                 if (intr_vector > bp->rx_cp_nr_rings) {
 583                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 584                                         bp->rx_cp_nr_rings);
 585                         return -ENOTSUP;
 586                 }
 587                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 588                 if (rc)
 589                         return rc;
 590         }
 591
 592         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 593                 intr_handle->intr_vec =
 594                         rte_zmalloc("intr_vec",
 595                                     bp->eth_dev->data->nb_rx_queues *
 596                                     sizeof(int), 0);
 597                 if (intr_handle->intr_vec == NULL) {
 598                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 599                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 600                         rc = -ENOMEM;
 601                         goto err_disable;
 602                 }
 603                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 604                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 605                          intr_handle->intr_vec, intr_handle->nb_efd,
 606                         intr_handle->max_intr);
 607                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 608                      queue_id++) {
 609                         intr_handle->intr_vec[queue_id] =
 610                                                         vec + BNXT_RX_VEC_START;
 611                         if (vec < base + intr_handle->nb_efd - 1)
 612                                 vec++;
 613                 }
 614         }
 615
 616         /* enable uio/vfio intr/eventfd mapping */
 617         rc = rte_intr_enable(intr_handle);
 618 #ifndef RTE_EXEC_ENV_FREEBSD
 619         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 620         if (rc)
 621                 goto err_free;
 622 #endif
 623
 624         rc = bnxt_get_hwrm_link_config(bp, &new);
 625         if (rc) {
 626                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 627                 goto err_free;
 628         }
 629
 630         if (!bp->link_info.link_up) {
 631                 rc = bnxt_set_hwrm_link_config(bp, true);
 632                 if (rc) {
 633                         PMD_DRV_LOG(ERR,
 634                                 "HWRM link config failure rc: %x\n", rc);
 635                         goto err_free;
 636                 }
 637         }
 638         bnxt_print_link_info(bp->eth_dev);
 639
 640         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 641         if (!bp->mark_table)
 642                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 643
 644         return 0;
 645
 646 err_free:
 647         rte_free(intr_handle->intr_vec);
 648 err_disable:
 649         rte_intr_efd_disable(intr_handle);
 650 err_out:
 651         /* Some of the error status returned by FW may not be from errno.h */
 652         if (rc > 0)
 653                 rc = -EIO;
 654
 655         return rc;
 656 }
 657
 658 static int bnxt_shutdown_nic(struct bnxt *bp)
 659 {
 660         bnxt_free_all_hwrm_resources(bp);
 661         bnxt_free_all_filters(bp);
 662         bnxt_free_all_vnics(bp);
 663         return 0;
 664 }
 665
 666 /*
 667  * Device configuration and status function
 668  */
 669
 670 static uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 671 {
 672         uint32_t link_speed = bp->link_info.support_speeds;
 673         uint32_t speed_capa = 0;
 674
 675         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 676                 speed_capa |= ETH_LINK_SPEED_100M;
 677         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 678                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 679         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 680                 speed_capa |= ETH_LINK_SPEED_1G;
 681         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 682                 speed_capa |= ETH_LINK_SPEED_2_5G;
 683         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 684                 speed_capa |= ETH_LINK_SPEED_10G;
 685         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 686                 speed_capa |= ETH_LINK_SPEED_20G;
 687         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 688                 speed_capa |= ETH_LINK_SPEED_25G;
 689         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 690                 speed_capa |= ETH_LINK_SPEED_40G;
 691         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 692                 speed_capa |= ETH_LINK_SPEED_50G;
 693         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 694                 speed_capa |= ETH_LINK_SPEED_100G;
 695
 696         if (bp->link_info.auto_mode == HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 697                 speed_capa |= ETH_LINK_SPEED_FIXED;
 698         else
 699                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 700
 701         return speed_capa;
 702 }
 703
 704 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 705                                 struct rte_eth_dev_info *dev_info)
 706 {
 707         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 708         struct bnxt *bp = eth_dev->data->dev_private;
 709         uint16_t max_vnics, i, j, vpool, vrxq;
 710         unsigned int max_rx_rings;
 711         int rc;
 712
 713         rc = is_bnxt_in_error(bp);
 714         if (rc)
 715                 return rc;
 716
 717         /* MAC Specifics */
 718         dev_info->max_mac_addrs = bp->max_l2_ctx;
 719         dev_info->max_hash_mac_addrs = 0;
 720
 721         /* PF/VF specifics */
 722         if (BNXT_PF(bp))
 723                 dev_info->max_vfs = pdev->max_vfs;
 724
 725         max_rx_rings = BNXT_MAX_RINGS(bp);
 726         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 727         dev_info->max_rx_queues = max_rx_rings;
 728         dev_info->max_tx_queues = max_rx_rings;
 729         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 730         dev_info->hash_key_size = 40;
 731         max_vnics = bp->max_vnics;
 732
 733         /* MTU specifics */
 734         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 735         dev_info->max_mtu = BNXT_MAX_MTU;
 736
 737         /* Fast path specifics */
 738         dev_info->min_rx_bufsize = 1;
 739         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 740
 741         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 742         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 743                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 744         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 745         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 746
 747         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 748
 749         /* *INDENT-OFF* */
 750         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 751                 .rx_thresh = {
 752                         .pthresh = 8,
 753                         .hthresh = 8,
 754                         .wthresh = 0,
 755                 },
 756                 .rx_free_thresh = 32,
 757                 /* If no descriptors available, pkts are dropped by default */
 758                 .rx_drop_en = 1,
 759         };
 760
 761         dev_info->default_txconf = (struct rte_eth_txconf) {
 762                 .tx_thresh = {
 763                         .pthresh = 32,
 764                         .hthresh = 0,
 765                         .wthresh = 0,
 766                 },
 767                 .tx_free_thresh = 32,
 768                 .tx_rs_thresh = 32,
 769         };
 770         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 771
 772         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 773         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 774         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 775         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 776         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 777
 778         /* *INDENT-ON* */
 779
 780         /*
 781          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 782          *       need further investigation.
 783          */
 784
 785         /* VMDq resources */
 786         vpool = 64; /* ETH_64_POOLS */
 787         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 788         for (i = 0; i < 4; vpool >>= 1, i++) {
 789                 if (max_vnics > vpool) {
 790                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 791                                 if (dev_info->max_rx_queues > vrxq) {
 792                                         if (vpool > vrxq)
 793                                                 vpool = vrxq;
 794                                         goto found;
 795                                 }
 796                         }
 797                         /* Not enough resources to support VMDq */
 798                         break;
 799                 }
 800         }
 801         /* Not enough resources to support VMDq */
 802         vpool = 0;
 803         vrxq = 0;
 804 found:
 805         dev_info->max_vmdq_pools = vpool;
 806         dev_info->vmdq_queue_num = vrxq;
 807
 808         dev_info->vmdq_pool_base = 0;
 809         dev_info->vmdq_queue_base = 0;
 810
 811         return 0;
 812 }
 813
 814 /* Configure the device based on the configuration provided */
 815 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 816 {
 817         struct bnxt *bp = eth_dev->data->dev_private;
 818         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 819         int rc;
 820
 821         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 822         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 823         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 824         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 825
 826         rc = is_bnxt_in_error(bp);
 827         if (rc)
 828                 return rc;
 829
 830         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 831                 rc = bnxt_hwrm_check_vf_rings(bp);
 832                 if (rc) {
 833                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 834                         return -ENOSPC;
 835                 }
 836
 837                 /* If a resource has already been allocated - in this case
 838                  * it is the async completion ring, free it. Reallocate it after
 839                  * resource reservation. This will ensure the resource counts
 840                  * are calculated correctly.
 841                  */
 842
 843                 pthread_mutex_lock(&bp->def_cp_lock);
 844
 845                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 846                         bnxt_disable_int(bp);
 847                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 848                 }
 849
 850                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 851                 if (rc) {
 852                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 853                         pthread_mutex_unlock(&bp->def_cp_lock);
 854                         return -ENOSPC;
 855                 }
 856
 857                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 858                         rc = bnxt_alloc_async_cp_ring(bp);
 859                         if (rc) {
 860                                 pthread_mutex_unlock(&bp->def_cp_lock);
 861                                 return rc;
 862                         }
 863                         bnxt_enable_int(bp);
 864                 }
 865
 866                 pthread_mutex_unlock(&bp->def_cp_lock);
 867         } else {
 868                 /* legacy driver needs to get updated values */
 869                 rc = bnxt_hwrm_func_qcaps(bp);
 870                 if (rc) {
 871                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 872                         return rc;
 873                 }
 874         }
 875
 876         /* Inherit new configurations */
 877         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 878             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 879             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 880                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 881             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 882             bp->max_stat_ctx)
 883                 goto resource_error;
 884
 885         if (BNXT_HAS_RING_GRPS(bp) &&
 886             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 887                 goto resource_error;
 888
 889         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 890             bp->max_vnics < eth_dev->data->nb_rx_queues)
 891                 goto resource_error;
 892
 893         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 894         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 895
 896         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 897                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 898         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
 899
 900         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 901                 eth_dev->data->mtu =
 902                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 903                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 904                         BNXT_NUM_VLANS;
 905                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 906         }
 907         return 0;
 908
 909 resource_error:
 910         PMD_DRV_LOG(ERR,
 911                     "Insufficient resources to support requested config\n");
 912         PMD_DRV_LOG(ERR,
 913                     "Num Queues Requested: Tx %d, Rx %d\n",
 914                     eth_dev->data->nb_tx_queues,
 915                     eth_dev->data->nb_rx_queues);
 916         PMD_DRV_LOG(ERR,
 917                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 918                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 919                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 920         return -ENOSPC;
 921 }
 922
 923 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 924 {
 925         struct rte_eth_link *link = &eth_dev->data->dev_link;
 926
 927         if (link->link_status)
 928                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 929                         eth_dev->data->port_id,
 930                         (uint32_t)link->link_speed,
 931                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 932                         ("full-duplex") : ("half-duplex\n"));
 933         else
 934                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 935                         eth_dev->data->port_id);
 936 }
 937
 938 /*
 939  * Determine whether the current configuration requires support for scattered
 940  * receive; return 1 if scattered receive is required and 0 if not.
 941  */
 942 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 943 {
 944         uint16_t buf_size;
 945         int i;
 946
 947         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 948                 return 1;
 949
 950         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 951                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 952
 953                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 954                                       RTE_PKTMBUF_HEADROOM);
 955                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 956                         return 1;
 957         }
 958         return 0;
 959 }
 960
 961 static eth_rx_burst_t
 962 bnxt_receive_function(struct rte_eth_dev *eth_dev)
 963 {
 964         struct bnxt *bp = eth_dev->data->dev_private;
 965
 966 #ifdef RTE_ARCH_X86
 967 #ifndef RTE_LIBRTE_IEEE1588
 968         /*
 969          * Vector mode receive can be enabled only if scatter rx is not
 970          * in use and rx offloads are limited to VLAN stripping and
 971          * CRC stripping.
 972          */
 973         if (!eth_dev->data->scattered_rx &&
 974             !(eth_dev->data->dev_conf.rxmode.offloads &
 975               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 976                 DEV_RX_OFFLOAD_KEEP_CRC |
 977                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 978                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 979                 DEV_RX_OFFLOAD_UDP_CKSUM |
 980                 DEV_RX_OFFLOAD_TCP_CKSUM |
 981                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 982                 DEV_RX_OFFLOAD_RSS_HASH |
 983                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
 984             !bp->truflow) {
 985                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 986                             eth_dev->data->port_id);
 987                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
 988                 return bnxt_recv_pkts_vec;
 989         }
 990         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 991                     eth_dev->data->port_id);
 992         PMD_DRV_LOG(INFO,
 993                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 994                     eth_dev->data->port_id,
 995                     eth_dev->data->scattered_rx,
 996                     eth_dev->data->dev_conf.rxmode.offloads);
 997 #endif
 998 #endif
 999         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1000         return bnxt_recv_pkts;
1001 }
1002
1003 static eth_tx_burst_t
1004 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1005 {
1006 #ifdef RTE_ARCH_X86
1007 #ifndef RTE_LIBRTE_IEEE1588
1008         /*
1009          * Vector mode transmit can be enabled only if not using scatter rx
1010          * or tx offloads.
1011          */
1012         if (!eth_dev->data->scattered_rx &&
1013             !eth_dev->data->dev_conf.txmode.offloads) {
1014                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1015                             eth_dev->data->port_id);
1016                 return bnxt_xmit_pkts_vec;
1017         }
1018         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1019                     eth_dev->data->port_id);
1020         PMD_DRV_LOG(INFO,
1021                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1022                     eth_dev->data->port_id,
1023                     eth_dev->data->scattered_rx,
1024                     eth_dev->data->dev_conf.txmode.offloads);
1025 #endif
1026 #endif
1027         return bnxt_xmit_pkts;
1028 }
1029
1030 static int bnxt_handle_if_change_status(struct bnxt *bp)
1031 {
1032         int rc;
1033
1034         /* Since fw has undergone a reset and lost all contexts,
1035          * set fatal flag to not issue hwrm during cleanup
1036          */
1037         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1038         bnxt_uninit_resources(bp, true);
1039
1040         /* clear fatal flag so that re-init happens */
1041         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1042         rc = bnxt_init_resources(bp, true);
1043
1044         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1045
1046         return rc;
1047 }
1048
1049 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1050 {
1051         struct bnxt *bp = eth_dev->data->dev_private;
1052         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1053         int vlan_mask = 0;
1054         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1055
1056         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1057                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1058                 return -EINVAL;
1059         }
1060
1061         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1062                 PMD_DRV_LOG(ERR,
1063                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1064                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1065         }
1066
1067         do {
1068                 rc = bnxt_hwrm_if_change(bp, true);
1069                 if (rc == 0 || rc != -EAGAIN)
1070                         break;
1071
1072                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1073         } while (retry_cnt--);
1074
1075         if (rc)
1076                 return rc;
1077
1078         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1079                 rc = bnxt_handle_if_change_status(bp);
1080                 if (rc)
1081                         return rc;
1082         }
1083
1084         bnxt_enable_int(bp);
1085
1086         rc = bnxt_init_chip(bp);
1087         if (rc)
1088                 goto error;
1089
1090         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1091         eth_dev->data->dev_started = 1;
1092
1093         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1094
1095         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1096                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1097         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1098                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1099         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1100         if (rc)
1101                 goto error;
1102
1103         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1104         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1105
1106         pthread_mutex_lock(&bp->def_cp_lock);
1107         bnxt_schedule_fw_health_check(bp);
1108         pthread_mutex_unlock(&bp->def_cp_lock);
1109
1110         if (bp->truflow)
1111                 bnxt_ulp_init(bp);
1112
1113         return 0;
1114
1115 error:
1116         bnxt_shutdown_nic(bp);
1117         bnxt_free_tx_mbufs(bp);
1118         bnxt_free_rx_mbufs(bp);
1119         bnxt_hwrm_if_change(bp, false);
1120         eth_dev->data->dev_started = 0;
1121         return rc;
1122 }
1123
1124 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1125 {
1126         struct bnxt *bp = eth_dev->data->dev_private;
1127         int rc = 0;
1128
1129         if (!bp->link_info.link_up)
1130                 rc = bnxt_set_hwrm_link_config(bp, true);
1131         if (!rc)
1132                 eth_dev->data->dev_link.link_status = 1;
1133
1134         bnxt_print_link_info(eth_dev);
1135         return rc;
1136 }
1137
1138 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1139 {
1140         struct bnxt *bp = eth_dev->data->dev_private;
1141
1142         eth_dev->data->dev_link.link_status = 0;
1143         bnxt_set_hwrm_link_config(bp, false);
1144         bp->link_info.link_up = 0;
1145
1146         return 0;
1147 }
1148
1149 /* Unload the driver, release resources */
1150 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1151 {
1152         struct bnxt *bp = eth_dev->data->dev_private;
1153         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1154         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1155
1156         if (bp->truflow)
1157                 bnxt_ulp_deinit(bp);
1158
1159         eth_dev->data->dev_started = 0;
1160         /* Prevent crashes when queues are still in use */
1161         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1162         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1163
1164         bnxt_disable_int(bp);
1165
1166         /* disable uio/vfio intr/eventfd mapping */
1167         rte_intr_disable(intr_handle);
1168
1169         bnxt_cancel_fw_health_check(bp);
1170
1171         bnxt_dev_set_link_down_op(eth_dev);
1172
1173         /* Wait for link to be reset and the async notification to process.
1174          * During reset recovery, there is no need to wait and
1175          * VF/NPAR functions do not have privilege to change PHY config.
1176          */
1177         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1178                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1179
1180         /* Clean queue intr-vector mapping */
1181         rte_intr_efd_disable(intr_handle);
1182         if (intr_handle->intr_vec != NULL) {
1183                 rte_free(intr_handle->intr_vec);
1184                 intr_handle->intr_vec = NULL;
1185         }
1186
1187         bnxt_hwrm_port_clr_stats(bp);
1188         bnxt_free_tx_mbufs(bp);
1189         bnxt_free_rx_mbufs(bp);
1190         /* Process any remaining notifications in default completion queue */
1191         bnxt_int_handler(eth_dev);
1192         bnxt_shutdown_nic(bp);
1193         bnxt_hwrm_if_change(bp, false);
1194
1195         rte_free(bp->mark_table);
1196         bp->mark_table = NULL;
1197
1198         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1199         bp->rx_cosq_cnt = 0;
1200 }
1201
1202 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1203 {
1204         struct bnxt *bp = eth_dev->data->dev_private;
1205
1206         /* cancel the recovery handler before remove dev */
1207         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1208         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1209         bnxt_cancel_fc_thread(bp);
1210
1211         if (eth_dev->data->dev_started)
1212                 bnxt_dev_stop_op(eth_dev);
1213
1214         bnxt_uninit_resources(bp, false);
1215
1216         eth_dev->dev_ops = NULL;
1217         eth_dev->rx_pkt_burst = NULL;
1218         eth_dev->tx_pkt_burst = NULL;
1219
1220         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1221         bp->tx_mem_zone = NULL;
1222         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1223         bp->rx_mem_zone = NULL;
1224
1225         rte_free(bp->pf.vf_info);
1226         bp->pf.vf_info = NULL;
1227
1228         rte_free(bp->grp_info);
1229         bp->grp_info = NULL;
1230 }
1231
1232 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1233                                     uint32_t index)
1234 {
1235         struct bnxt *bp = eth_dev->data->dev_private;
1236         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1237         struct bnxt_vnic_info *vnic;
1238         struct bnxt_filter_info *filter, *temp_filter;
1239         uint32_t i;
1240
1241         if (is_bnxt_in_error(bp))
1242                 return;
1243
1244         /*
1245          * Loop through all VNICs from the specified filter flow pools to
1246          * remove the corresponding MAC addr filter
1247          */
1248         for (i = 0; i < bp->nr_vnics; i++) {
1249                 if (!(pool_mask & (1ULL << i)))
1250                         continue;
1251
1252                 vnic = &bp->vnic_info[i];
1253                 filter = STAILQ_FIRST(&vnic->filter);
1254                 while (filter) {
1255                         temp_filter = STAILQ_NEXT(filter, next);
1256                         if (filter->mac_index == index) {
1257                                 STAILQ_REMOVE(&vnic->filter, filter,
1258                                                 bnxt_filter_info, next);
1259                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1260                                 bnxt_free_filter(bp, filter);
1261                         }
1262                         filter = temp_filter;
1263                 }
1264         }
1265 }
1266
1267 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1268                                struct rte_ether_addr *mac_addr, uint32_t index,
1269                                uint32_t pool)
1270 {
1271         struct bnxt_filter_info *filter;
1272         int rc = 0;
1273
1274         /* Attach requested MAC address to the new l2_filter */
1275         STAILQ_FOREACH(filter, &vnic->filter, next) {
1276                 if (filter->mac_index == index) {
1277                         PMD_DRV_LOG(DEBUG,
1278                                     "MAC addr already existed for pool %d\n",
1279                                     pool);
1280                         return 0;
1281                 }
1282         }
1283
1284         filter = bnxt_alloc_filter(bp);
1285         if (!filter) {
1286                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1287                 return -ENODEV;
1288         }
1289
1290         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1291          * if the MAC that's been programmed now is a different one, then,
1292          * copy that addr to filter->l2_addr
1293          */
1294         if (mac_addr)
1295                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1296         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1297
1298         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1299         if (!rc) {
1300                 filter->mac_index = index;
1301                 if (filter->mac_index == 0)
1302                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1303                 else
1304                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1305         } else {
1306                 bnxt_free_filter(bp, filter);
1307         }
1308
1309         return rc;
1310 }
1311
1312 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1313                                 struct rte_ether_addr *mac_addr,
1314                                 uint32_t index, uint32_t pool)
1315 {
1316         struct bnxt *bp = eth_dev->data->dev_private;
1317         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1318         int rc = 0;
1319
1320         rc = is_bnxt_in_error(bp);
1321         if (rc)
1322                 return rc;
1323
1324         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1325                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1326                 return -ENOTSUP;
1327         }
1328
1329         if (!vnic) {
1330                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1331                 return -EINVAL;
1332         }
1333
1334         /* Filter settings will get applied when port is started */
1335         if (!eth_dev->data->dev_started)
1336                 return 0;
1337
1338         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1339
1340         return rc;
1341 }
1342
1343 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1344                      bool exp_link_status)
1345 {
1346         int rc = 0;
1347         struct bnxt *bp = eth_dev->data->dev_private;
1348         struct rte_eth_link new;
1349         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1350                   BNXT_LINK_DOWN_WAIT_CNT;
1351
1352         rc = is_bnxt_in_error(bp);
1353         if (rc)
1354                 return rc;
1355
1356         memset(&new, 0, sizeof(new));
1357         do {
1358                 /* Retrieve link info from hardware */
1359                 rc = bnxt_get_hwrm_link_config(bp, &new);
1360                 if (rc) {
1361                         new.link_speed = ETH_LINK_SPEED_100M;
1362                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1363                         PMD_DRV_LOG(ERR,
1364                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1365                         goto out;
1366                 }
1367
1368                 if (!wait_to_complete || new.link_status == exp_link_status)
1369                         break;
1370
1371                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1372         } while (cnt--);
1373
1374 out:
1375         /* Timed out or success */
1376         if (new.link_status != eth_dev->data->dev_link.link_status ||
1377         new.link_speed != eth_dev->data->dev_link.link_speed) {
1378                 rte_eth_linkstatus_set(eth_dev, &new);
1379
1380                 _rte_eth_dev_callback_process(eth_dev,
1381                                               RTE_ETH_EVENT_INTR_LSC,
1382                                               NULL);
1383
1384                 bnxt_print_link_info(eth_dev);
1385         }
1386
1387         return rc;
1388 }
1389
1390 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1391                                int wait_to_complete)
1392 {
1393         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1394 }
1395
1396 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1397 {
1398         struct bnxt *bp = eth_dev->data->dev_private;
1399         struct bnxt_vnic_info *vnic;
1400         uint32_t old_flags;
1401         int rc;
1402
1403         rc = is_bnxt_in_error(bp);
1404         if (rc)
1405                 return rc;
1406
1407         /* Filter settings will get applied when port is started */
1408         if (!eth_dev->data->dev_started)
1409                 return 0;
1410
1411         if (bp->vnic_info == NULL)
1412                 return 0;
1413
1414         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1415
1416         old_flags = vnic->flags;
1417         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1418         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1419         if (rc != 0)
1420                 vnic->flags = old_flags;
1421
1422         return rc;
1423 }
1424
1425 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1426 {
1427         struct bnxt *bp = eth_dev->data->dev_private;
1428         struct bnxt_vnic_info *vnic;
1429         uint32_t old_flags;
1430         int rc;
1431
1432         rc = is_bnxt_in_error(bp);
1433         if (rc)
1434                 return rc;
1435
1436         /* Filter settings will get applied when port is started */
1437         if (!eth_dev->data->dev_started)
1438                 return 0;
1439
1440         if (bp->vnic_info == NULL)
1441                 return 0;
1442
1443         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1444
1445         old_flags = vnic->flags;
1446         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1447         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1448         if (rc != 0)
1449                 vnic->flags = old_flags;
1450
1451         return rc;
1452 }
1453
1454 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1455 {
1456         struct bnxt *bp = eth_dev->data->dev_private;
1457         struct bnxt_vnic_info *vnic;
1458         uint32_t old_flags;
1459         int rc;
1460
1461         rc = is_bnxt_in_error(bp);
1462         if (rc)
1463                 return rc;
1464
1465         /* Filter settings will get applied when port is started */
1466         if (!eth_dev->data->dev_started)
1467                 return 0;
1468
1469         if (bp->vnic_info == NULL)
1470                 return 0;
1471
1472         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1473
1474         old_flags = vnic->flags;
1475         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1476         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1477         if (rc != 0)
1478                 vnic->flags = old_flags;
1479
1480         return rc;
1481 }
1482
1483 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1484 {
1485         struct bnxt *bp = eth_dev->data->dev_private;
1486         struct bnxt_vnic_info *vnic;
1487         uint32_t old_flags;
1488         int rc;
1489
1490         rc = is_bnxt_in_error(bp);
1491         if (rc)
1492                 return rc;
1493
1494         /* Filter settings will get applied when port is started */
1495         if (!eth_dev->data->dev_started)
1496                 return 0;
1497
1498         if (bp->vnic_info == NULL)
1499                 return 0;
1500
1501         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1502
1503         old_flags = vnic->flags;
1504         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1505         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1506         if (rc != 0)
1507                 vnic->flags = old_flags;
1508
1509         return rc;
1510 }
1511
1512 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1513 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1514 {
1515         if (qid >= bp->rx_nr_rings)
1516                 return NULL;
1517
1518         return bp->eth_dev->data->rx_queues[qid];
1519 }
1520
1521 /* Return rxq corresponding to a given rss table ring/group ID. */
1522 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1523 {
1524         struct bnxt_rx_queue *rxq;
1525         unsigned int i;
1526
1527         if (!BNXT_HAS_RING_GRPS(bp)) {
1528                 for (i = 0; i < bp->rx_nr_rings; i++) {
1529                         rxq = bp->eth_dev->data->rx_queues[i];
1530                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1531                                 return rxq->index;
1532                 }
1533         } else {
1534                 for (i = 0; i < bp->rx_nr_rings; i++) {
1535                         if (bp->grp_info[i].fw_grp_id == fwr)
1536                                 return i;
1537                 }
1538         }
1539
1540         return INVALID_HW_RING_ID;
1541 }
1542
1543 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1544                             struct rte_eth_rss_reta_entry64 *reta_conf,
1545                             uint16_t reta_size)
1546 {
1547         struct bnxt *bp = eth_dev->data->dev_private;
1548         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1549         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1550         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1551         uint16_t idx, sft;
1552         int i, rc;
1553
1554         rc = is_bnxt_in_error(bp);
1555         if (rc)
1556                 return rc;
1557
1558         if (!vnic->rss_table)
1559                 return -EINVAL;
1560
1561         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1562                 return -EINVAL;
1563
1564         if (reta_size != tbl_size) {
1565                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1566                         "(%d) must equal the size supported by the hardware "
1567                         "(%d)\n", reta_size, tbl_size);
1568                 return -EINVAL;
1569         }
1570
1571         for (i = 0; i < reta_size; i++) {
1572                 struct bnxt_rx_queue *rxq;
1573
1574                 idx = i / RTE_RETA_GROUP_SIZE;
1575                 sft = i % RTE_RETA_GROUP_SIZE;
1576
1577                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1578                         continue;
1579
1580                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1581                 if (!rxq) {
1582                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1583                         return -EINVAL;
1584                 }
1585
1586                 if (BNXT_CHIP_THOR(bp)) {
1587                         vnic->rss_table[i * 2] =
1588                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1589                         vnic->rss_table[i * 2 + 1] =
1590                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1591                 } else {
1592                         vnic->rss_table[i] =
1593                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1594                 }
1595         }
1596
1597         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1598         return 0;
1599 }
1600
1601 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1602                               struct rte_eth_rss_reta_entry64 *reta_conf,
1603                               uint16_t reta_size)
1604 {
1605         struct bnxt *bp = eth_dev->data->dev_private;
1606         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1607         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1608         uint16_t idx, sft, i;
1609         int rc;
1610
1611         rc = is_bnxt_in_error(bp);
1612         if (rc)
1613                 return rc;
1614
1615         /* Retrieve from the default VNIC */
1616         if (!vnic)
1617                 return -EINVAL;
1618         if (!vnic->rss_table)
1619                 return -EINVAL;
1620
1621         if (reta_size != tbl_size) {
1622                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1623                         "(%d) must equal the size supported by the hardware "
1624                         "(%d)\n", reta_size, tbl_size);
1625                 return -EINVAL;
1626         }
1627
1628         for (idx = 0, i = 0; i < reta_size; i++) {
1629                 idx = i / RTE_RETA_GROUP_SIZE;
1630                 sft = i % RTE_RETA_GROUP_SIZE;
1631
1632                 if (reta_conf[idx].mask & (1ULL << sft)) {
1633                         uint16_t qid;
1634
1635                         if (BNXT_CHIP_THOR(bp))
1636                                 qid = bnxt_rss_to_qid(bp,
1637                                                       vnic->rss_table[i * 2]);
1638                         else
1639                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1640
1641                         if (qid == INVALID_HW_RING_ID) {
1642                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1643                                 return -EINVAL;
1644                         }
1645                         reta_conf[idx].reta[sft] = qid;
1646                 }
1647         }
1648
1649         return 0;
1650 }
1651
1652 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1653                                    struct rte_eth_rss_conf *rss_conf)
1654 {
1655         struct bnxt *bp = eth_dev->data->dev_private;
1656         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1657         struct bnxt_vnic_info *vnic;
1658         int rc;
1659
1660         rc = is_bnxt_in_error(bp);
1661         if (rc)
1662                 return rc;
1663
1664         /*
1665          * If RSS enablement were different than dev_configure,
1666          * then return -EINVAL
1667          */
1668         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1669                 if (!rss_conf->rss_hf)
1670                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1671         } else {
1672                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1673                         return -EINVAL;
1674         }
1675
1676         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1677         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1678
1679         /* Update the default RSS VNIC(s) */
1680         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1681         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1682
1683         /*
1684          * If hashkey is not specified, use the previously configured
1685          * hashkey
1686          */
1687         if (!rss_conf->rss_key)
1688                 goto rss_config;
1689
1690         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1691                 PMD_DRV_LOG(ERR,
1692                             "Invalid hashkey length, should be 16 bytes\n");
1693                 return -EINVAL;
1694         }
1695         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1696
1697 rss_config:
1698         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1699         return 0;
1700 }
1701
1702 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1703                                      struct rte_eth_rss_conf *rss_conf)
1704 {
1705         struct bnxt *bp = eth_dev->data->dev_private;
1706         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1707         int len, rc;
1708         uint32_t hash_types;
1709
1710         rc = is_bnxt_in_error(bp);
1711         if (rc)
1712                 return rc;
1713
1714         /* RSS configuration is the same for all VNICs */
1715         if (vnic && vnic->rss_hash_key) {
1716                 if (rss_conf->rss_key) {
1717                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1718                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1719                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1720                 }
1721
1722                 hash_types = vnic->hash_type;
1723                 rss_conf->rss_hf = 0;
1724                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1725                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1726                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1727                 }
1728                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1729                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1730                         hash_types &=
1731                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1732                 }
1733                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1734                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1735                         hash_types &=
1736                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1737                 }
1738                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1739                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1740                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1741                 }
1742                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1743                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1744                         hash_types &=
1745                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1746                 }
1747                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1748                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1749                         hash_types &=
1750                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1751                 }
1752                 if (hash_types) {
1753                         PMD_DRV_LOG(ERR,
1754                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1755                                 vnic->hash_type);
1756                         return -ENOTSUP;
1757                 }
1758         } else {
1759                 rss_conf->rss_hf = 0;
1760         }
1761         return 0;
1762 }
1763
1764 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1765                                struct rte_eth_fc_conf *fc_conf)
1766 {
1767         struct bnxt *bp = dev->data->dev_private;
1768         struct rte_eth_link link_info;
1769         int rc;
1770
1771         rc = is_bnxt_in_error(bp);
1772         if (rc)
1773                 return rc;
1774
1775         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1776         if (rc)
1777                 return rc;
1778
1779         memset(fc_conf, 0, sizeof(*fc_conf));
1780         if (bp->link_info.auto_pause)
1781                 fc_conf->autoneg = 1;
1782         switch (bp->link_info.pause) {
1783         case 0:
1784                 fc_conf->mode = RTE_FC_NONE;
1785                 break;
1786         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1787                 fc_conf->mode = RTE_FC_TX_PAUSE;
1788                 break;
1789         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1790                 fc_conf->mode = RTE_FC_RX_PAUSE;
1791                 break;
1792         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1793                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1794                 fc_conf->mode = RTE_FC_FULL;
1795                 break;
1796         }
1797         return 0;
1798 }
1799
1800 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1801                                struct rte_eth_fc_conf *fc_conf)
1802 {
1803         struct bnxt *bp = dev->data->dev_private;
1804         int rc;
1805
1806         rc = is_bnxt_in_error(bp);
1807         if (rc)
1808                 return rc;
1809
1810         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1811                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1812                 return -ENOTSUP;
1813         }
1814
1815         switch (fc_conf->mode) {
1816         case RTE_FC_NONE:
1817                 bp->link_info.auto_pause = 0;
1818                 bp->link_info.force_pause = 0;
1819                 break;
1820         case RTE_FC_RX_PAUSE:
1821                 if (fc_conf->autoneg) {
1822                         bp->link_info.auto_pause =
1823                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1824                         bp->link_info.force_pause = 0;
1825                 } else {
1826                         bp->link_info.auto_pause = 0;
1827                         bp->link_info.force_pause =
1828                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1829                 }
1830                 break;
1831         case RTE_FC_TX_PAUSE:
1832                 if (fc_conf->autoneg) {
1833                         bp->link_info.auto_pause =
1834                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1835                         bp->link_info.force_pause = 0;
1836                 } else {
1837                         bp->link_info.auto_pause = 0;
1838                         bp->link_info.force_pause =
1839                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1840                 }
1841                 break;
1842         case RTE_FC_FULL:
1843                 if (fc_conf->autoneg) {
1844                         bp->link_info.auto_pause =
1845                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1846                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1847                         bp->link_info.force_pause = 0;
1848                 } else {
1849                         bp->link_info.auto_pause = 0;
1850                         bp->link_info.force_pause =
1851                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1852                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1853                 }
1854                 break;
1855         }
1856         return bnxt_set_hwrm_link_config(bp, true);
1857 }
1858
1859 /* Add UDP tunneling port */
1860 static int
1861 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1862                          struct rte_eth_udp_tunnel *udp_tunnel)
1863 {
1864         struct bnxt *bp = eth_dev->data->dev_private;
1865         uint16_t tunnel_type = 0;
1866         int rc = 0;
1867
1868         rc = is_bnxt_in_error(bp);
1869         if (rc)
1870                 return rc;
1871
1872         switch (udp_tunnel->prot_type) {
1873         case RTE_TUNNEL_TYPE_VXLAN:
1874                 if (bp->vxlan_port_cnt) {
1875                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1876                                 udp_tunnel->udp_port);
1877                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1878                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1879                                 return -ENOSPC;
1880                         }
1881                         bp->vxlan_port_cnt++;
1882                         return 0;
1883                 }
1884                 tunnel_type =
1885                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1886                 bp->vxlan_port_cnt++;
1887                 break;
1888         case RTE_TUNNEL_TYPE_GENEVE:
1889                 if (bp->geneve_port_cnt) {
1890                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1891                                 udp_tunnel->udp_port);
1892                         if (bp->geneve_port != udp_tunnel->udp_port) {
1893                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1894                                 return -ENOSPC;
1895                         }
1896                         bp->geneve_port_cnt++;
1897                         return 0;
1898                 }
1899                 tunnel_type =
1900                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1901                 bp->geneve_port_cnt++;
1902                 break;
1903         default:
1904                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1905                 return -ENOTSUP;
1906         }
1907         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1908                                              tunnel_type);
1909         return rc;
1910 }
1911
1912 static int
1913 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1914                          struct rte_eth_udp_tunnel *udp_tunnel)
1915 {
1916         struct bnxt *bp = eth_dev->data->dev_private;
1917         uint16_t tunnel_type = 0;
1918         uint16_t port = 0;
1919         int rc = 0;
1920
1921         rc = is_bnxt_in_error(bp);
1922         if (rc)
1923                 return rc;
1924
1925         switch (udp_tunnel->prot_type) {
1926         case RTE_TUNNEL_TYPE_VXLAN:
1927                 if (!bp->vxlan_port_cnt) {
1928                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1929                         return -EINVAL;
1930                 }
1931                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1932                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1933                                 udp_tunnel->udp_port, bp->vxlan_port);
1934                         return -EINVAL;
1935                 }
1936                 if (--bp->vxlan_port_cnt)
1937                         return 0;
1938
1939                 tunnel_type =
1940                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1941                 port = bp->vxlan_fw_dst_port_id;
1942                 break;
1943         case RTE_TUNNEL_TYPE_GENEVE:
1944                 if (!bp->geneve_port_cnt) {
1945                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1946                         return -EINVAL;
1947                 }
1948                 if (bp->geneve_port != udp_tunnel->udp_port) {
1949                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1950                                 udp_tunnel->udp_port, bp->geneve_port);
1951                         return -EINVAL;
1952                 }
1953                 if (--bp->geneve_port_cnt)
1954                         return 0;
1955
1956                 tunnel_type =
1957                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1958                 port = bp->geneve_fw_dst_port_id;
1959                 break;
1960         default:
1961                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1962                 return -ENOTSUP;
1963         }
1964
1965         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1966         if (!rc) {
1967                 if (tunnel_type ==
1968                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1969                         bp->vxlan_port = 0;
1970                 if (tunnel_type ==
1971                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1972                         bp->geneve_port = 0;
1973         }
1974         return rc;
1975 }
1976
1977 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1978 {
1979         struct bnxt_filter_info *filter;
1980         struct bnxt_vnic_info *vnic;
1981         int rc = 0;
1982         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1983
1984         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1985         filter = STAILQ_FIRST(&vnic->filter);
1986         while (filter) {
1987                 /* Search for this matching MAC+VLAN filter */
1988                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1989                         /* Delete the filter */
1990                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1991                         if (rc)
1992                                 return rc;
1993                         STAILQ_REMOVE(&vnic->filter, filter,
1994                                       bnxt_filter_info, next);
1995                         bnxt_free_filter(bp, filter);
1996                         PMD_DRV_LOG(INFO,
1997                                     "Deleted vlan filter for %d\n",
1998                                     vlan_id);
1999                         return 0;
2000                 }
2001                 filter = STAILQ_NEXT(filter, next);
2002         }
2003         return -ENOENT;
2004 }
2005
2006 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2007 {
2008         struct bnxt_filter_info *filter;
2009         struct bnxt_vnic_info *vnic;
2010         int rc = 0;
2011         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2012                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2013         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2014
2015         /* Implementation notes on the use of VNIC in this command:
2016          *
2017          * By default, these filters belong to default vnic for the function.
2018          * Once these filters are set up, only destination VNIC can be modified.
2019          * If the destination VNIC is not specified in this command,
2020          * then the HWRM shall only create an l2 context id.
2021          */
2022
2023         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2024         filter = STAILQ_FIRST(&vnic->filter);
2025         /* Check if the VLAN has already been added */
2026         while (filter) {
2027                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2028                         return -EEXIST;
2029
2030                 filter = STAILQ_NEXT(filter, next);
2031         }
2032
2033         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2034          * command to create MAC+VLAN filter with the right flags, enables set.
2035          */
2036         filter = bnxt_alloc_filter(bp);
2037         if (!filter) {
2038                 PMD_DRV_LOG(ERR,
2039                             "MAC/VLAN filter alloc failed\n");
2040                 return -ENOMEM;
2041         }
2042         /* MAC + VLAN ID filter */
2043         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2044          * untagged packets are received
2045          *
2046          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2047          * packets and only the programmed vlan's packets are received
2048          */
2049         filter->l2_ivlan = vlan_id;
2050         filter->l2_ivlan_mask = 0x0FFF;
2051         filter->enables |= en;
2052         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2053
2054         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2055         if (rc) {
2056                 /* Free the newly allocated filter as we were
2057                  * not able to create the filter in hardware.
2058                  */
2059                 bnxt_free_filter(bp, filter);
2060                 return rc;
2061         }
2062
2063         filter->mac_index = 0;
2064         /* Add this new filter to the list */
2065         if (vlan_id == 0)
2066                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2067         else
2068                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2069
2070         PMD_DRV_LOG(INFO,
2071                     "Added Vlan filter for %d\n", vlan_id);
2072         return rc;
2073 }
2074
2075 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2076                 uint16_t vlan_id, int on)
2077 {
2078         struct bnxt *bp = eth_dev->data->dev_private;
2079         int rc;
2080
2081         rc = is_bnxt_in_error(bp);
2082         if (rc)
2083                 return rc;
2084
2085         /* These operations apply to ALL existing MAC/VLAN filters */
2086         if (on)
2087                 return bnxt_add_vlan_filter(bp, vlan_id);
2088         else
2089                 return bnxt_del_vlan_filter(bp, vlan_id);
2090 }
2091
2092 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2093                                     struct bnxt_vnic_info *vnic)
2094 {
2095         struct bnxt_filter_info *filter;
2096         int rc;
2097
2098         filter = STAILQ_FIRST(&vnic->filter);
2099         while (filter) {
2100                 if (filter->mac_index == 0 &&
2101                     !memcmp(filter->l2_addr, bp->mac_addr,
2102                             RTE_ETHER_ADDR_LEN)) {
2103                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2104                         if (!rc) {
2105                                 STAILQ_REMOVE(&vnic->filter, filter,
2106                                               bnxt_filter_info, next);
2107                                 bnxt_free_filter(bp, filter);
2108                         }
2109                         return rc;
2110                 }
2111                 filter = STAILQ_NEXT(filter, next);
2112         }
2113         return 0;
2114 }
2115
2116 static int
2117 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2118 {
2119         struct bnxt_vnic_info *vnic;
2120         unsigned int i;
2121         int rc;
2122
2123         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2124         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2125                 /* Remove any VLAN filters programmed */
2126                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2127                         bnxt_del_vlan_filter(bp, i);
2128
2129                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2130                 if (rc)
2131                         return rc;
2132         } else {
2133                 /* Default filter will allow packets that match the
2134                  * dest mac. So, it has to be deleted, otherwise, we
2135                  * will endup receiving vlan packets for which the
2136                  * filter is not programmed, when hw-vlan-filter
2137                  * configuration is ON
2138                  */
2139                 bnxt_del_dflt_mac_filter(bp, vnic);
2140                 /* This filter will allow only untagged packets */
2141                 bnxt_add_vlan_filter(bp, 0);
2142         }
2143         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2144                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2145
2146         return 0;
2147 }
2148
2149 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2150 {
2151         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2152         unsigned int i;
2153         int rc;
2154
2155         /* Destroy vnic filters and vnic */
2156         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2157             DEV_RX_OFFLOAD_VLAN_FILTER) {
2158                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2159                         bnxt_del_vlan_filter(bp, i);
2160         }
2161         bnxt_del_dflt_mac_filter(bp, vnic);
2162
2163         rc = bnxt_hwrm_vnic_free(bp, vnic);
2164         if (rc)
2165                 return rc;
2166
2167         rte_free(vnic->fw_grp_ids);
2168         vnic->fw_grp_ids = NULL;
2169
2170         return 0;
2171 }
2172
2173 static int
2174 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2175 {
2176         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2177         int rc;
2178
2179         /* Destroy, recreate and reconfigure the default vnic */
2180         rc = bnxt_free_one_vnic(bp, 0);
2181         if (rc)
2182                 return rc;
2183
2184         /* default vnic 0 */
2185         rc = bnxt_setup_one_vnic(bp, 0);
2186         if (rc)
2187                 return rc;
2188
2189         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2190             DEV_RX_OFFLOAD_VLAN_FILTER) {
2191                 rc = bnxt_add_vlan_filter(bp, 0);
2192                 if (rc)
2193                         return rc;
2194                 rc = bnxt_restore_vlan_filters(bp);
2195                 if (rc)
2196                         return rc;
2197         } else {
2198                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2199                 if (rc)
2200                         return rc;
2201         }
2202
2203         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2204         if (rc)
2205                 return rc;
2206
2207         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2208                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2209
2210         return rc;
2211 }
2212
2213 static int
2214 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2215 {
2216         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2217         struct bnxt *bp = dev->data->dev_private;
2218         int rc;
2219
2220         rc = is_bnxt_in_error(bp);
2221         if (rc)
2222                 return rc;
2223
2224         /* Filter settings will get applied when port is started */
2225         if (!dev->data->dev_started)
2226                 return 0;
2227
2228         if (mask & ETH_VLAN_FILTER_MASK) {
2229                 /* Enable or disable VLAN filtering */
2230                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2231                 if (rc)
2232                         return rc;
2233         }
2234
2235         if (mask & ETH_VLAN_STRIP_MASK) {
2236                 /* Enable or disable VLAN stripping */
2237                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2238                 if (rc)
2239                         return rc;
2240         }
2241
2242         if (mask & ETH_VLAN_EXTEND_MASK) {
2243                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2244                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2245                 else
2246                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2247         }
2248
2249         return 0;
2250 }
2251
2252 static int
2253 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2254                       uint16_t tpid)
2255 {
2256         struct bnxt *bp = dev->data->dev_private;
2257         int qinq = dev->data->dev_conf.rxmode.offloads &
2258                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2259
2260         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2261             vlan_type != ETH_VLAN_TYPE_OUTER) {
2262                 PMD_DRV_LOG(ERR,
2263                             "Unsupported vlan type.");
2264                 return -EINVAL;
2265         }
2266         if (!qinq) {
2267                 PMD_DRV_LOG(ERR,
2268                             "QinQ not enabled. Needs to be ON as we can "
2269                             "accelerate only outer vlan\n");
2270                 return -EINVAL;
2271         }
2272
2273         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2274                 switch (tpid) {
2275                 case RTE_ETHER_TYPE_QINQ:
2276                         bp->outer_tpid_bd =
2277                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2278                                 break;
2279                 case RTE_ETHER_TYPE_VLAN:
2280                         bp->outer_tpid_bd =
2281                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2282                                 break;
2283                 case 0x9100:
2284                         bp->outer_tpid_bd =
2285                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2286                                 break;
2287                 case 0x9200:
2288                         bp->outer_tpid_bd =
2289                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2290                                 break;
2291                 case 0x9300:
2292                         bp->outer_tpid_bd =
2293                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2294                                 break;
2295                 default:
2296                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2297                         return -EINVAL;
2298                 }
2299                 bp->outer_tpid_bd |= tpid;
2300                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2301         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2302                 PMD_DRV_LOG(ERR,
2303                             "Can accelerate only outer vlan in QinQ\n");
2304                 return -EINVAL;
2305         }
2306
2307         return 0;
2308 }
2309
2310 static int
2311 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2312                              struct rte_ether_addr *addr)
2313 {
2314         struct bnxt *bp = dev->data->dev_private;
2315         /* Default Filter is tied to VNIC 0 */
2316         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2317         int rc;
2318
2319         rc = is_bnxt_in_error(bp);
2320         if (rc)
2321                 return rc;
2322
2323         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2324                 return -EPERM;
2325
2326         if (rte_is_zero_ether_addr(addr))
2327                 return -EINVAL;
2328
2329         /* Filter settings will get applied when port is started */
2330         if (!dev->data->dev_started)
2331                 return 0;
2332
2333         /* Check if the requested MAC is already added */
2334         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2335                 return 0;
2336
2337         /* Destroy filter and re-create it */
2338         bnxt_del_dflt_mac_filter(bp, vnic);
2339
2340         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2341         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2342                 /* This filter will allow only untagged packets */
2343                 rc = bnxt_add_vlan_filter(bp, 0);
2344         } else {
2345                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2346         }
2347
2348         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2349         return rc;
2350 }
2351
2352 static int
2353 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2354                           struct rte_ether_addr *mc_addr_set,
2355                           uint32_t nb_mc_addr)
2356 {
2357         struct bnxt *bp = eth_dev->data->dev_private;
2358         char *mc_addr_list = (char *)mc_addr_set;
2359         struct bnxt_vnic_info *vnic;
2360         uint32_t off = 0, i = 0;
2361         int rc;
2362
2363         rc = is_bnxt_in_error(bp);
2364         if (rc)
2365                 return rc;
2366
2367         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2368
2369         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2370                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2371                 goto allmulti;
2372         }
2373
2374         /* TODO Check for Duplicate mcast addresses */
2375         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2376         for (i = 0; i < nb_mc_addr; i++) {
2377                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2378                         RTE_ETHER_ADDR_LEN);
2379                 off += RTE_ETHER_ADDR_LEN;
2380         }
2381
2382         vnic->mc_addr_cnt = i;
2383         if (vnic->mc_addr_cnt)
2384                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2385         else
2386                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2387
2388 allmulti:
2389         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2390 }
2391
2392 static int
2393 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2394 {
2395         struct bnxt *bp = dev->data->dev_private;
2396         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2397         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2398         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2399         int ret;
2400
2401         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2402                         fw_major, fw_minor, fw_updt);
2403
2404         ret += 1; /* add the size of '\0' */
2405         if (fw_size < (uint32_t)ret)
2406                 return ret;
2407         else
2408                 return 0;
2409 }
2410
2411 static void
2412 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2413         struct rte_eth_rxq_info *qinfo)
2414 {
2415         struct bnxt *bp = dev->data->dev_private;
2416         struct bnxt_rx_queue *rxq;
2417
2418         if (is_bnxt_in_error(bp))
2419                 return;
2420
2421         rxq = dev->data->rx_queues[queue_id];
2422
2423         qinfo->mp = rxq->mb_pool;
2424         qinfo->scattered_rx = dev->data->scattered_rx;
2425         qinfo->nb_desc = rxq->nb_rx_desc;
2426
2427         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2428         qinfo->conf.rx_drop_en = 0;
2429         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2430 }
2431
2432 static void
2433 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2434         struct rte_eth_txq_info *qinfo)
2435 {
2436         struct bnxt *bp = dev->data->dev_private;
2437         struct bnxt_tx_queue *txq;
2438
2439         if (is_bnxt_in_error(bp))
2440                 return;
2441
2442         txq = dev->data->tx_queues[queue_id];
2443
2444         qinfo->nb_desc = txq->nb_tx_desc;
2445
2446         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2447         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2448         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2449
2450         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2451         qinfo->conf.tx_rs_thresh = 0;
2452         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2453 }
2454
2455 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2456 {
2457         struct bnxt *bp = eth_dev->data->dev_private;
2458         uint32_t new_pkt_size;
2459         uint32_t rc = 0;
2460         uint32_t i;
2461
2462         rc = is_bnxt_in_error(bp);
2463         if (rc)
2464                 return rc;
2465
2466         /* Exit if receive queues are not configured yet */
2467         if (!eth_dev->data->nb_rx_queues)
2468                 return rc;
2469
2470         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2471                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2472
2473 #ifdef RTE_ARCH_X86
2474         /*
2475          * If vector-mode tx/rx is active, disallow any MTU change that would
2476          * require scattered receive support.
2477          */
2478         if (eth_dev->data->dev_started &&
2479             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2480              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2481             (new_pkt_size >
2482              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2483                 PMD_DRV_LOG(ERR,
2484                             "MTU change would require scattered rx support. ");
2485                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2486                 return -EINVAL;
2487         }
2488 #endif
2489
2490         if (new_mtu > RTE_ETHER_MTU) {
2491                 bp->flags |= BNXT_FLAG_JUMBO;
2492                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2493                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2494         } else {
2495                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2496                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2497                 bp->flags &= ~BNXT_FLAG_JUMBO;
2498         }
2499
2500         /* Is there a change in mtu setting? */
2501         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2502                 return rc;
2503
2504         for (i = 0; i < bp->nr_vnics; i++) {
2505                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2506                 uint16_t size = 0;
2507
2508                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2509                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2510                 if (rc)
2511                         break;
2512
2513                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2514                 size -= RTE_PKTMBUF_HEADROOM;
2515
2516                 if (size < new_mtu) {
2517                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2518                         if (rc)
2519                                 return rc;
2520                 }
2521         }
2522
2523         if (!rc)
2524                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2525
2526         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2527
2528         return rc;
2529 }
2530
2531 static int
2532 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2533 {
2534         struct bnxt *bp = dev->data->dev_private;
2535         uint16_t vlan = bp->vlan;
2536         int rc;
2537
2538         rc = is_bnxt_in_error(bp);
2539         if (rc)
2540                 return rc;
2541
2542         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2543                 PMD_DRV_LOG(ERR,
2544                         "PVID cannot be modified for this function\n");
2545                 return -ENOTSUP;
2546         }
2547         bp->vlan = on ? pvid : 0;
2548
2549         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2550         if (rc)
2551                 bp->vlan = vlan;
2552         return rc;
2553 }
2554
2555 static int
2556 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2557 {
2558         struct bnxt *bp = dev->data->dev_private;
2559         int rc;
2560
2561         rc = is_bnxt_in_error(bp);
2562         if (rc)
2563                 return rc;
2564
2565         return bnxt_hwrm_port_led_cfg(bp, true);
2566 }
2567
2568 static int
2569 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2570 {
2571         struct bnxt *bp = dev->data->dev_private;
2572         int rc;
2573
2574         rc = is_bnxt_in_error(bp);
2575         if (rc)
2576                 return rc;
2577
2578         return bnxt_hwrm_port_led_cfg(bp, false);
2579 }
2580
2581 static uint32_t
2582 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2583 {
2584         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2585         uint32_t desc = 0, raw_cons = 0, cons;
2586         struct bnxt_cp_ring_info *cpr;
2587         struct bnxt_rx_queue *rxq;
2588         struct rx_pkt_cmpl *rxcmp;
2589         int rc;
2590
2591         rc = is_bnxt_in_error(bp);
2592         if (rc)
2593                 return rc;
2594
2595         rxq = dev->data->rx_queues[rx_queue_id];
2596         cpr = rxq->cp_ring;
2597         raw_cons = cpr->cp_raw_cons;
2598
2599         while (1) {
2600                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2601                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2602                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2603
2604                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2605                         break;
2606                 } else {
2607                         raw_cons++;
2608                         desc++;
2609                 }
2610         }
2611
2612         return desc;
2613 }
2614
2615 static int
2616 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2617 {
2618         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2619         struct bnxt_rx_ring_info *rxr;
2620         struct bnxt_cp_ring_info *cpr;
2621         struct bnxt_sw_rx_bd *rx_buf;
2622         struct rx_pkt_cmpl *rxcmp;
2623         uint32_t cons, cp_cons;
2624         int rc;
2625
2626         if (!rxq)
2627                 return -EINVAL;
2628
2629         rc = is_bnxt_in_error(rxq->bp);
2630         if (rc)
2631                 return rc;
2632
2633         cpr = rxq->cp_ring;
2634         rxr = rxq->rx_ring;
2635
2636         if (offset >= rxq->nb_rx_desc)
2637                 return -EINVAL;
2638
2639         cons = RING_CMP(cpr->cp_ring_struct, offset);
2640         cp_cons = cpr->cp_raw_cons;
2641         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2642
2643         if (cons > cp_cons) {
2644                 if (CMPL_VALID(rxcmp, cpr->valid))
2645                         return RTE_ETH_RX_DESC_DONE;
2646         } else {
2647                 if (CMPL_VALID(rxcmp, !cpr->valid))
2648                         return RTE_ETH_RX_DESC_DONE;
2649         }
2650         rx_buf = &rxr->rx_buf_ring[cons];
2651         if (rx_buf->mbuf == NULL)
2652                 return RTE_ETH_RX_DESC_UNAVAIL;
2653
2654
2655         return RTE_ETH_RX_DESC_AVAIL;
2656 }
2657
2658 static int
2659 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2660 {
2661         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2662         struct bnxt_tx_ring_info *txr;
2663         struct bnxt_cp_ring_info *cpr;
2664         struct bnxt_sw_tx_bd *tx_buf;
2665         struct tx_pkt_cmpl *txcmp;
2666         uint32_t cons, cp_cons;
2667         int rc;
2668
2669         if (!txq)
2670                 return -EINVAL;
2671
2672         rc = is_bnxt_in_error(txq->bp);
2673         if (rc)
2674                 return rc;
2675
2676         cpr = txq->cp_ring;
2677         txr = txq->tx_ring;
2678
2679         if (offset >= txq->nb_tx_desc)
2680                 return -EINVAL;
2681
2682         cons = RING_CMP(cpr->cp_ring_struct, offset);
2683         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2684         cp_cons = cpr->cp_raw_cons;
2685
2686         if (cons > cp_cons) {
2687                 if (CMPL_VALID(txcmp, cpr->valid))
2688                         return RTE_ETH_TX_DESC_UNAVAIL;
2689         } else {
2690                 if (CMPL_VALID(txcmp, !cpr->valid))
2691                         return RTE_ETH_TX_DESC_UNAVAIL;
2692         }
2693         tx_buf = &txr->tx_buf_ring[cons];
2694         if (tx_buf->mbuf == NULL)
2695                 return RTE_ETH_TX_DESC_DONE;
2696
2697         return RTE_ETH_TX_DESC_FULL;
2698 }
2699
2700 static struct bnxt_filter_info *
2701 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2702                                 struct rte_eth_ethertype_filter *efilter,
2703                                 struct bnxt_vnic_info *vnic0,
2704                                 struct bnxt_vnic_info *vnic,
2705                                 int *ret)
2706 {
2707         struct bnxt_filter_info *mfilter = NULL;
2708         int match = 0;
2709         *ret = 0;
2710
2711         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2712                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2713                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2714                         " ethertype filter.", efilter->ether_type);
2715                 *ret = -EINVAL;
2716                 goto exit;
2717         }
2718         if (efilter->queue >= bp->rx_nr_rings) {
2719                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2720                 *ret = -EINVAL;
2721                 goto exit;
2722         }
2723
2724         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2725         vnic = &bp->vnic_info[efilter->queue];
2726         if (vnic == NULL) {
2727                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2728                 *ret = -EINVAL;
2729                 goto exit;
2730         }
2731
2732         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2733                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2734                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2735                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2736                              mfilter->flags ==
2737                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2738                              mfilter->ethertype == efilter->ether_type)) {
2739                                 match = 1;
2740                                 break;
2741                         }
2742                 }
2743         } else {
2744                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2745                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2746                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2747                              mfilter->ethertype == efilter->ether_type &&
2748                              mfilter->flags ==
2749                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2750                                 match = 1;
2751                                 break;
2752                         }
2753         }
2754
2755         if (match)
2756                 *ret = -EEXIST;
2757
2758 exit:
2759         return mfilter;
2760 }
2761
2762 static int
2763 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2764                         enum rte_filter_op filter_op,
2765                         void *arg)
2766 {
2767         struct bnxt *bp = dev->data->dev_private;
2768         struct rte_eth_ethertype_filter *efilter =
2769                         (struct rte_eth_ethertype_filter *)arg;
2770         struct bnxt_filter_info *bfilter, *filter1;
2771         struct bnxt_vnic_info *vnic, *vnic0;
2772         int ret;
2773
2774         if (filter_op == RTE_ETH_FILTER_NOP)
2775                 return 0;
2776
2777         if (arg == NULL) {
2778                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2779                             filter_op);
2780                 return -EINVAL;
2781         }
2782
2783         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2784         vnic = &bp->vnic_info[efilter->queue];
2785
2786         switch (filter_op) {
2787         case RTE_ETH_FILTER_ADD:
2788                 bnxt_match_and_validate_ether_filter(bp, efilter,
2789                                                         vnic0, vnic, &ret);
2790                 if (ret < 0)
2791                         return ret;
2792
2793                 bfilter = bnxt_get_unused_filter(bp);
2794                 if (bfilter == NULL) {
2795                         PMD_DRV_LOG(ERR,
2796                                 "Not enough resources for a new filter.\n");
2797                         return -ENOMEM;
2798                 }
2799                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2800                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2801                        RTE_ETHER_ADDR_LEN);
2802                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2803                        RTE_ETHER_ADDR_LEN);
2804                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2805                 bfilter->ethertype = efilter->ether_type;
2806                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2807
2808                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2809                 if (filter1 == NULL) {
2810                         ret = -EINVAL;
2811                         goto cleanup;
2812                 }
2813                 bfilter->enables |=
2814                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2815                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2816
2817                 bfilter->dst_id = vnic->fw_vnic_id;
2818
2819                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2820                         bfilter->flags =
2821                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2822                 }
2823
2824                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2825                 if (ret)
2826                         goto cleanup;
2827                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2828                 break;
2829         case RTE_ETH_FILTER_DELETE:
2830                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2831                                                         vnic0, vnic, &ret);
2832                 if (ret == -EEXIST) {
2833                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2834
2835                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2836                                       next);
2837                         bnxt_free_filter(bp, filter1);
2838                 } else if (ret == 0) {
2839                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2840                 }
2841                 break;
2842         default:
2843                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2844                 ret = -EINVAL;
2845                 goto error;
2846         }
2847         return ret;
2848 cleanup:
2849         bnxt_free_filter(bp, bfilter);
2850 error:
2851         return ret;
2852 }
2853
2854 static inline int
2855 parse_ntuple_filter(struct bnxt *bp,
2856                     struct rte_eth_ntuple_filter *nfilter,
2857                     struct bnxt_filter_info *bfilter)
2858 {
2859         uint32_t en = 0;
2860
2861         if (nfilter->queue >= bp->rx_nr_rings) {
2862                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2863                 return -EINVAL;
2864         }
2865
2866         switch (nfilter->dst_port_mask) {
2867         case UINT16_MAX:
2868                 bfilter->dst_port_mask = -1;
2869                 bfilter->dst_port = nfilter->dst_port;
2870                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2871                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2872                 break;
2873         default:
2874                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2875                 return -EINVAL;
2876         }
2877
2878         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2879         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2880
2881         switch (nfilter->proto_mask) {
2882         case UINT8_MAX:
2883                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2884                         bfilter->ip_protocol = 17;
2885                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2886                         bfilter->ip_protocol = 6;
2887                 else
2888                         return -EINVAL;
2889                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2890                 break;
2891         default:
2892                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2893                 return -EINVAL;
2894         }
2895
2896         switch (nfilter->dst_ip_mask) {
2897         case UINT32_MAX:
2898                 bfilter->dst_ipaddr_mask[0] = -1;
2899                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2900                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2901                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2902                 break;
2903         default:
2904                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2905                 return -EINVAL;
2906         }
2907
2908         switch (nfilter->src_ip_mask) {
2909         case UINT32_MAX:
2910                 bfilter->src_ipaddr_mask[0] = -1;
2911                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2912                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2913                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2914                 break;
2915         default:
2916                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2917                 return -EINVAL;
2918         }
2919
2920         switch (nfilter->src_port_mask) {
2921         case UINT16_MAX:
2922                 bfilter->src_port_mask = -1;
2923                 bfilter->src_port = nfilter->src_port;
2924                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2925                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2926                 break;
2927         default:
2928                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2929                 return -EINVAL;
2930         }
2931
2932         bfilter->enables = en;
2933         return 0;
2934 }
2935
2936 static struct bnxt_filter_info*
2937 bnxt_match_ntuple_filter(struct bnxt *bp,
2938                          struct bnxt_filter_info *bfilter,
2939                          struct bnxt_vnic_info **mvnic)
2940 {
2941         struct bnxt_filter_info *mfilter = NULL;
2942         int i;
2943
2944         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2945                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2946                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2947                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2948                             bfilter->src_ipaddr_mask[0] ==
2949                             mfilter->src_ipaddr_mask[0] &&
2950                             bfilter->src_port == mfilter->src_port &&
2951                             bfilter->src_port_mask == mfilter->src_port_mask &&
2952                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2953                             bfilter->dst_ipaddr_mask[0] ==
2954                             mfilter->dst_ipaddr_mask[0] &&
2955                             bfilter->dst_port == mfilter->dst_port &&
2956                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2957                             bfilter->flags == mfilter->flags &&
2958                             bfilter->enables == mfilter->enables) {
2959                                 if (mvnic)
2960                                         *mvnic = vnic;
2961                                 return mfilter;
2962                         }
2963                 }
2964         }
2965         return NULL;
2966 }
2967
2968 static int
2969 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2970                        struct rte_eth_ntuple_filter *nfilter,
2971                        enum rte_filter_op filter_op)
2972 {
2973         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2974         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2975         int ret;
2976
2977         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2978                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2979                 return -EINVAL;
2980         }
2981
2982         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2983                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2984                 return -EINVAL;
2985         }
2986
2987         bfilter = bnxt_get_unused_filter(bp);
2988         if (bfilter == NULL) {
2989                 PMD_DRV_LOG(ERR,
2990                         "Not enough resources for a new filter.\n");
2991                 return -ENOMEM;
2992         }
2993         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2994         if (ret < 0)
2995                 goto free_filter;
2996
2997         vnic = &bp->vnic_info[nfilter->queue];
2998         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2999         filter1 = STAILQ_FIRST(&vnic0->filter);
3000         if (filter1 == NULL) {
3001                 ret = -EINVAL;
3002                 goto free_filter;
3003         }
3004
3005         bfilter->dst_id = vnic->fw_vnic_id;
3006         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3007         bfilter->enables |=
3008                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3009         bfilter->ethertype = 0x800;
3010         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3011
3012         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3013
3014         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3015             bfilter->dst_id == mfilter->dst_id) {
3016                 PMD_DRV_LOG(ERR, "filter exists.\n");
3017                 ret = -EEXIST;
3018                 goto free_filter;
3019         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3020                    bfilter->dst_id != mfilter->dst_id) {
3021                 mfilter->dst_id = vnic->fw_vnic_id;
3022                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3023                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3024                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3025                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3026                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3027                 goto free_filter;
3028         }
3029         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3030                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3031                 ret = -ENOENT;
3032                 goto free_filter;
3033         }
3034
3035         if (filter_op == RTE_ETH_FILTER_ADD) {
3036                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3037                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3038                 if (ret)
3039                         goto free_filter;
3040                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3041         } else {
3042                 if (mfilter == NULL) {
3043                         /* This should not happen. But for Coverity! */
3044                         ret = -ENOENT;
3045                         goto free_filter;
3046                 }
3047                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3048
3049                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3050                 bnxt_free_filter(bp, mfilter);
3051                 bnxt_free_filter(bp, bfilter);
3052         }
3053
3054         return 0;
3055 free_filter:
3056         bnxt_free_filter(bp, bfilter);
3057         return ret;
3058 }
3059
3060 static int
3061 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3062                         enum rte_filter_op filter_op,
3063                         void *arg)
3064 {
3065         struct bnxt *bp = dev->data->dev_private;
3066         int ret;
3067
3068         if (filter_op == RTE_ETH_FILTER_NOP)
3069                 return 0;
3070
3071         if (arg == NULL) {
3072                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3073                             filter_op);
3074                 return -EINVAL;
3075         }
3076
3077         switch (filter_op) {
3078         case RTE_ETH_FILTER_ADD:
3079                 ret = bnxt_cfg_ntuple_filter(bp,
3080                         (struct rte_eth_ntuple_filter *)arg,
3081                         filter_op);
3082                 break;
3083         case RTE_ETH_FILTER_DELETE:
3084                 ret = bnxt_cfg_ntuple_filter(bp,
3085                         (struct rte_eth_ntuple_filter *)arg,
3086                         filter_op);
3087                 break;
3088         default:
3089                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3090                 ret = -EINVAL;
3091                 break;
3092         }
3093         return ret;
3094 }
3095
3096 static int
3097 bnxt_parse_fdir_filter(struct bnxt *bp,
3098                        struct rte_eth_fdir_filter *fdir,
3099                        struct bnxt_filter_info *filter)
3100 {
3101         enum rte_fdir_mode fdir_mode =
3102                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3103         struct bnxt_vnic_info *vnic0, *vnic;
3104         struct bnxt_filter_info *filter1;
3105         uint32_t en = 0;
3106         int i;
3107
3108         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3109                 return -EINVAL;
3110
3111         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3112         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3113
3114         switch (fdir->input.flow_type) {
3115         case RTE_ETH_FLOW_IPV4:
3116         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3117                 /* FALLTHROUGH */
3118                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3119                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3120                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3121                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3122                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3123                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3124                 filter->ip_addr_type =
3125                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3126                 filter->src_ipaddr_mask[0] = 0xffffffff;
3127                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3128                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3129                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3130                 filter->ethertype = 0x800;
3131                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3132                 break;
3133         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3134                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3135                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3136                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3137                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3138                 filter->dst_port_mask = 0xffff;
3139                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3140                 filter->src_port_mask = 0xffff;
3141                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3142                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3143                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3144                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3145                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3146                 filter->ip_protocol = 6;
3147                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3148                 filter->ip_addr_type =
3149                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3150                 filter->src_ipaddr_mask[0] = 0xffffffff;
3151                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3152                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3153                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3154                 filter->ethertype = 0x800;
3155                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3156                 break;
3157         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3158                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3159                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3160                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3161                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3162                 filter->dst_port_mask = 0xffff;
3163                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3164                 filter->src_port_mask = 0xffff;
3165                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3166                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3167                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3168                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3169                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3170                 filter->ip_protocol = 17;
3171                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3172                 filter->ip_addr_type =
3173                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3174                 filter->src_ipaddr_mask[0] = 0xffffffff;
3175                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3176                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3177                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3178                 filter->ethertype = 0x800;
3179                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3180                 break;
3181         case RTE_ETH_FLOW_IPV6:
3182         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3183                 /* FALLTHROUGH */
3184                 filter->ip_addr_type =
3185                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3186                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3187                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3188                 rte_memcpy(filter->src_ipaddr,
3189                            fdir->input.flow.ipv6_flow.src_ip, 16);
3190                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3191                 rte_memcpy(filter->dst_ipaddr,
3192                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3193                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3194                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3195                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3196                 memset(filter->src_ipaddr_mask, 0xff, 16);
3197                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3198                 filter->ethertype = 0x86dd;
3199                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3200                 break;
3201         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3202                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3203                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3204                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3205                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3206                 filter->dst_port_mask = 0xffff;
3207                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3208                 filter->src_port_mask = 0xffff;
3209                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3210                 filter->ip_addr_type =
3211                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3212                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3213                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3214                 rte_memcpy(filter->src_ipaddr,
3215                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3216                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3217                 rte_memcpy(filter->dst_ipaddr,
3218                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3219                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3220                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3221                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3222                 memset(filter->src_ipaddr_mask, 0xff, 16);
3223                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3224                 filter->ethertype = 0x86dd;
3225                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3226                 break;
3227         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3228                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3229                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3230                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3231                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3232                 filter->dst_port_mask = 0xffff;
3233                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3234                 filter->src_port_mask = 0xffff;
3235                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3236                 filter->ip_addr_type =
3237                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3238                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3239                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3240                 rte_memcpy(filter->src_ipaddr,
3241                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3242                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3243                 rte_memcpy(filter->dst_ipaddr,
3244                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3245                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3246                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3247                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3248                 memset(filter->src_ipaddr_mask, 0xff, 16);
3249                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3250                 filter->ethertype = 0x86dd;
3251                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3252                 break;
3253         case RTE_ETH_FLOW_L2_PAYLOAD:
3254                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3255                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3256                 break;
3257         case RTE_ETH_FLOW_VXLAN:
3258                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3259                         return -EINVAL;
3260                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3261                 filter->tunnel_type =
3262                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3263                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3264                 break;
3265         case RTE_ETH_FLOW_NVGRE:
3266                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3267                         return -EINVAL;
3268                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3269                 filter->tunnel_type =
3270                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3271                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3272                 break;
3273         case RTE_ETH_FLOW_UNKNOWN:
3274         case RTE_ETH_FLOW_RAW:
3275         case RTE_ETH_FLOW_FRAG_IPV4:
3276         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3277         case RTE_ETH_FLOW_FRAG_IPV6:
3278         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3279         case RTE_ETH_FLOW_IPV6_EX:
3280         case RTE_ETH_FLOW_IPV6_TCP_EX:
3281         case RTE_ETH_FLOW_IPV6_UDP_EX:
3282         case RTE_ETH_FLOW_GENEVE:
3283                 /* FALLTHROUGH */
3284         default:
3285                 return -EINVAL;
3286         }
3287
3288         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3289         vnic = &bp->vnic_info[fdir->action.rx_queue];
3290         if (vnic == NULL) {
3291                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3292                 return -EINVAL;
3293         }
3294
3295         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3296                 rte_memcpy(filter->dst_macaddr,
3297                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3298                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3299         }
3300
3301         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3302                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3303                 filter1 = STAILQ_FIRST(&vnic0->filter);
3304                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3305         } else {
3306                 filter->dst_id = vnic->fw_vnic_id;
3307                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3308                         if (filter->dst_macaddr[i] == 0x00)
3309                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3310                         else
3311                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3312         }
3313
3314         if (filter1 == NULL)
3315                 return -EINVAL;
3316
3317         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3318         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3319
3320         filter->enables = en;
3321
3322         return 0;
3323 }
3324
3325 static struct bnxt_filter_info *
3326 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3327                 struct bnxt_vnic_info **mvnic)
3328 {
3329         struct bnxt_filter_info *mf = NULL;
3330         int i;
3331
3332         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3333                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3334
3335                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3336                         if (mf->filter_type == nf->filter_type &&
3337                             mf->flags == nf->flags &&
3338                             mf->src_port == nf->src_port &&
3339                             mf->src_port_mask == nf->src_port_mask &&
3340                             mf->dst_port == nf->dst_port &&
3341                             mf->dst_port_mask == nf->dst_port_mask &&
3342                             mf->ip_protocol == nf->ip_protocol &&
3343                             mf->ip_addr_type == nf->ip_addr_type &&
3344                             mf->ethertype == nf->ethertype &&
3345                             mf->vni == nf->vni &&
3346                             mf->tunnel_type == nf->tunnel_type &&
3347                             mf->l2_ovlan == nf->l2_ovlan &&
3348                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3349                             mf->l2_ivlan == nf->l2_ivlan &&
3350                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3351                             !memcmp(mf->l2_addr, nf->l2_addr,
3352                                     RTE_ETHER_ADDR_LEN) &&
3353                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3354                                     RTE_ETHER_ADDR_LEN) &&
3355                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3356                                     RTE_ETHER_ADDR_LEN) &&
3357                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3358                                     RTE_ETHER_ADDR_LEN) &&
3359                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3360                                     sizeof(nf->src_ipaddr)) &&
3361                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3362                                     sizeof(nf->src_ipaddr_mask)) &&
3363                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3364                                     sizeof(nf->dst_ipaddr)) &&
3365                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3366                                     sizeof(nf->dst_ipaddr_mask))) {
3367                                 if (mvnic)
3368                                         *mvnic = vnic;
3369                                 return mf;
3370                         }
3371                 }
3372         }
3373         return NULL;
3374 }
3375
3376 static int
3377 bnxt_fdir_filter(struct rte_eth_dev *dev,
3378                  enum rte_filter_op filter_op,
3379                  void *arg)
3380 {
3381         struct bnxt *bp = dev->data->dev_private;
3382         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3383         struct bnxt_filter_info *filter, *match;
3384         struct bnxt_vnic_info *vnic, *mvnic;
3385         int ret = 0, i;
3386
3387         if (filter_op == RTE_ETH_FILTER_NOP)
3388                 return 0;
3389
3390         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3391                 return -EINVAL;
3392
3393         switch (filter_op) {
3394         case RTE_ETH_FILTER_ADD:
3395         case RTE_ETH_FILTER_DELETE:
3396                 /* FALLTHROUGH */
3397                 filter = bnxt_get_unused_filter(bp);
3398                 if (filter == NULL) {
3399                         PMD_DRV_LOG(ERR,
3400                                 "Not enough resources for a new flow.\n");
3401                         return -ENOMEM;
3402                 }
3403
3404                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3405                 if (ret != 0)
3406                         goto free_filter;
3407                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3408
3409                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3410                         vnic = &bp->vnic_info[0];
3411                 else
3412                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3413
3414                 match = bnxt_match_fdir(bp, filter, &mvnic);
3415                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3416                         if (match->dst_id == vnic->fw_vnic_id) {
3417                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3418                                 ret = -EEXIST;
3419                                 goto free_filter;
3420                         } else {
3421                                 match->dst_id = vnic->fw_vnic_id;
3422                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3423                                                                   match->dst_id,
3424                                                                   match);
3425                                 STAILQ_REMOVE(&mvnic->filter, match,
3426                                               bnxt_filter_info, next);
3427                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3428                                 PMD_DRV_LOG(ERR,
3429                                         "Filter with matching pattern exist\n");
3430                                 PMD_DRV_LOG(ERR,
3431                                         "Updated it to new destination q\n");
3432                                 goto free_filter;
3433                         }
3434                 }
3435                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3436                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3437                         ret = -ENOENT;
3438                         goto free_filter;
3439                 }
3440
3441                 if (filter_op == RTE_ETH_FILTER_ADD) {
3442                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3443                                                           filter->dst_id,
3444                                                           filter);
3445                         if (ret)
3446                                 goto free_filter;
3447                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3448                 } else {
3449                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3450                         STAILQ_REMOVE(&vnic->filter, match,
3451                                       bnxt_filter_info, next);
3452                         bnxt_free_filter(bp, match);
3453                         bnxt_free_filter(bp, filter);
3454                 }
3455                 break;
3456         case RTE_ETH_FILTER_FLUSH:
3457                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3458                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3459
3460                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3461                                 if (filter->filter_type ==
3462                                     HWRM_CFA_NTUPLE_FILTER) {
3463                                         ret =
3464                                         bnxt_hwrm_clear_ntuple_filter(bp,
3465                                                                       filter);
3466                                         STAILQ_REMOVE(&vnic->filter, filter,
3467                                                       bnxt_filter_info, next);
3468                                 }
3469                         }
3470                 }
3471                 return ret;
3472         case RTE_ETH_FILTER_UPDATE:
3473         case RTE_ETH_FILTER_STATS:
3474         case RTE_ETH_FILTER_INFO:
3475                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3476                 break;
3477         default:
3478                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3479                 ret = -EINVAL;
3480                 break;
3481         }
3482         return ret;
3483
3484 free_filter:
3485         bnxt_free_filter(bp, filter);
3486         return ret;
3487 }
3488
3489 static int
3490 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3491                     enum rte_filter_type filter_type,
3492                     enum rte_filter_op filter_op, void *arg)
3493 {
3494         struct bnxt *bp = dev->data->dev_private;
3495         int ret = 0;
3496
3497         ret = is_bnxt_in_error(dev->data->dev_private);
3498         if (ret)
3499                 return ret;
3500
3501         switch (filter_type) {
3502         case RTE_ETH_FILTER_TUNNEL:
3503                 PMD_DRV_LOG(ERR,
3504                         "filter type: %d: To be implemented\n", filter_type);
3505                 break;
3506         case RTE_ETH_FILTER_FDIR:
3507                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3508                 break;
3509         case RTE_ETH_FILTER_NTUPLE:
3510                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3511                 break;
3512         case RTE_ETH_FILTER_ETHERTYPE:
3513                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3514                 break;
3515         case RTE_ETH_FILTER_GENERIC:
3516                 if (filter_op != RTE_ETH_FILTER_GET)
3517                         return -EINVAL;
3518                 if (bp->truflow)
3519                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3520                 else
3521                         *(const void **)arg = &bnxt_flow_ops;
3522                 break;
3523         default:
3524                 PMD_DRV_LOG(ERR,
3525                         "Filter type (%d) not supported", filter_type);
3526                 ret = -EINVAL;
3527                 break;
3528         }
3529         return ret;
3530 }
3531
3532 static const uint32_t *
3533 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3534 {
3535         static const uint32_t ptypes[] = {
3536                 RTE_PTYPE_L2_ETHER_VLAN,
3537                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3538                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3539                 RTE_PTYPE_L4_ICMP,
3540                 RTE_PTYPE_L4_TCP,
3541                 RTE_PTYPE_L4_UDP,
3542                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3543                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3544                 RTE_PTYPE_INNER_L4_ICMP,
3545                 RTE_PTYPE_INNER_L4_TCP,
3546                 RTE_PTYPE_INNER_L4_UDP,
3547                 RTE_PTYPE_UNKNOWN
3548         };
3549
3550         if (!dev->rx_pkt_burst)
3551                 return NULL;
3552
3553         return ptypes;
3554 }
3555
3556 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3557                          int reg_win)
3558 {
3559         uint32_t reg_base = *reg_arr & 0xfffff000;
3560         uint32_t win_off;
3561         int i;
3562
3563         for (i = 0; i < count; i++) {
3564                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3565                         return -ERANGE;
3566         }
3567         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3568         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3569         return 0;
3570 }
3571
3572 static int bnxt_map_ptp_regs(struct bnxt *bp)
3573 {
3574         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3575         uint32_t *reg_arr;
3576         int rc, i;
3577
3578         reg_arr = ptp->rx_regs;
3579         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3580         if (rc)
3581                 return rc;
3582
3583         reg_arr = ptp->tx_regs;
3584         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3585         if (rc)
3586                 return rc;
3587
3588         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3589                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3590
3591         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3592                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3593
3594         return 0;
3595 }
3596
3597 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3598 {
3599         rte_write32(0, (uint8_t *)bp->bar0 +
3600                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3601         rte_write32(0, (uint8_t *)bp->bar0 +
3602                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3603 }
3604
3605 static uint64_t bnxt_cc_read(struct bnxt *bp)
3606 {
3607         uint64_t ns;
3608
3609         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3610                               BNXT_GRCPF_REG_SYNC_TIME));
3611         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3612                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3613         return ns;
3614 }
3615
3616 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3617 {
3618         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3619         uint32_t fifo;
3620
3621         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3622                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3623         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3624                 return -EAGAIN;
3625
3626         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3627                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3628         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3629                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3630         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3631                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3632
3633         return 0;
3634 }
3635
3636 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3637 {
3638         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3639         struct bnxt_pf_info *pf = &bp->pf;
3640         uint16_t port_id;
3641         uint32_t fifo;
3642
3643         if (!ptp)
3644                 return -ENODEV;
3645
3646         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3647                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3648         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3649                 return -EAGAIN;
3650
3651         port_id = pf->port_id;
3652         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3653                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3654
3655         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3656                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3657         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3658 /*              bnxt_clr_rx_ts(bp);       TBD  */
3659                 return -EBUSY;
3660         }
3661
3662         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3663                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3664         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3665                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3666
3667         return 0;
3668 }
3669
3670 static int
3671 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3672 {
3673         uint64_t ns;
3674         struct bnxt *bp = dev->data->dev_private;
3675         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3676
3677         if (!ptp)
3678                 return 0;
3679
3680         ns = rte_timespec_to_ns(ts);
3681         /* Set the timecounters to a new value. */
3682         ptp->tc.nsec = ns;
3683
3684         return 0;
3685 }
3686
3687 static int
3688 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3689 {
3690         struct bnxt *bp = dev->data->dev_private;
3691         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3692         uint64_t ns, systime_cycles = 0;
3693         int rc = 0;
3694
3695         if (!ptp)
3696                 return 0;
3697
3698         if (BNXT_CHIP_THOR(bp))
3699                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3700                                              &systime_cycles);
3701         else
3702                 systime_cycles = bnxt_cc_read(bp);
3703
3704         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3705         *ts = rte_ns_to_timespec(ns);
3706
3707         return rc;
3708 }
3709 static int
3710 bnxt_timesync_enable(struct rte_eth_dev *dev)
3711 {
3712         struct bnxt *bp = dev->data->dev_private;
3713         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3714         uint32_t shift = 0;
3715         int rc;
3716
3717         if (!ptp)
3718                 return 0;
3719
3720         ptp->rx_filter = 1;
3721         ptp->tx_tstamp_en = 1;
3722         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3723
3724         rc = bnxt_hwrm_ptp_cfg(bp);
3725         if (rc)
3726                 return rc;
3727
3728         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3729         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3730         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3731
3732         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3733         ptp->tc.cc_shift = shift;
3734         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3735
3736         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3737         ptp->rx_tstamp_tc.cc_shift = shift;
3738         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3739
3740         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3741         ptp->tx_tstamp_tc.cc_shift = shift;
3742         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3743
3744         if (!BNXT_CHIP_THOR(bp))
3745                 bnxt_map_ptp_regs(bp);
3746
3747         return 0;
3748 }
3749
3750 static int
3751 bnxt_timesync_disable(struct rte_eth_dev *dev)
3752 {
3753         struct bnxt *bp = dev->data->dev_private;
3754         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3755
3756         if (!ptp)
3757                 return 0;
3758
3759         ptp->rx_filter = 0;
3760         ptp->tx_tstamp_en = 0;
3761         ptp->rxctl = 0;
3762
3763         bnxt_hwrm_ptp_cfg(bp);
3764
3765         if (!BNXT_CHIP_THOR(bp))
3766                 bnxt_unmap_ptp_regs(bp);
3767
3768         return 0;
3769 }
3770
3771 static int
3772 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3773                                  struct timespec *timestamp,
3774                                  uint32_t flags __rte_unused)
3775 {
3776         struct bnxt *bp = dev->data->dev_private;
3777         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3778         uint64_t rx_tstamp_cycles = 0;
3779         uint64_t ns;
3780
3781         if (!ptp)
3782                 return 0;
3783
3784         if (BNXT_CHIP_THOR(bp))
3785                 rx_tstamp_cycles = ptp->rx_timestamp;
3786         else
3787                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3788
3789         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3790         *timestamp = rte_ns_to_timespec(ns);
3791         return  0;
3792 }
3793
3794 static int
3795 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3796                                  struct timespec *timestamp)
3797 {
3798         struct bnxt *bp = dev->data->dev_private;
3799         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3800         uint64_t tx_tstamp_cycles = 0;
3801         uint64_t ns;
3802         int rc = 0;
3803
3804         if (!ptp)
3805                 return 0;
3806
3807         if (BNXT_CHIP_THOR(bp))
3808                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3809                                              &tx_tstamp_cycles);
3810         else
3811                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3812
3813         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3814         *timestamp = rte_ns_to_timespec(ns);
3815
3816         return rc;
3817 }
3818
3819 static int
3820 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3821 {
3822         struct bnxt *bp = dev->data->dev_private;
3823         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3824
3825         if (!ptp)
3826                 return 0;
3827
3828         ptp->tc.nsec += delta;
3829
3830         return 0;
3831 }
3832
3833 static int
3834 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3835 {
3836         struct bnxt *bp = dev->data->dev_private;
3837         int rc;
3838         uint32_t dir_entries;
3839         uint32_t entry_length;
3840
3841         rc = is_bnxt_in_error(bp);
3842         if (rc)
3843                 return rc;
3844
3845         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3846                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3847                     bp->pdev->addr.devid, bp->pdev->addr.function);
3848
3849         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3850         if (rc != 0)
3851                 return rc;
3852
3853         return dir_entries * entry_length;
3854 }
3855
3856 static int
3857 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3858                 struct rte_dev_eeprom_info *in_eeprom)
3859 {
3860         struct bnxt *bp = dev->data->dev_private;
3861         uint32_t index;
3862         uint32_t offset;
3863         int rc;
3864
3865         rc = is_bnxt_in_error(bp);
3866         if (rc)
3867                 return rc;
3868
3869         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3870                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3871                     bp->pdev->addr.devid, bp->pdev->addr.function,
3872                     in_eeprom->offset, in_eeprom->length);
3873
3874         if (in_eeprom->offset == 0) /* special offset value to get directory */
3875                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3876                                                 in_eeprom->data);
3877
3878         index = in_eeprom->offset >> 24;
3879         offset = in_eeprom->offset & 0xffffff;
3880
3881         if (index != 0)
3882                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3883                                            in_eeprom->length, in_eeprom->data);
3884
3885         return 0;
3886 }
3887
3888 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3889 {
3890         switch (dir_type) {
3891         case BNX_DIR_TYPE_CHIMP_PATCH:
3892         case BNX_DIR_TYPE_BOOTCODE:
3893         case BNX_DIR_TYPE_BOOTCODE_2:
3894         case BNX_DIR_TYPE_APE_FW:
3895         case BNX_DIR_TYPE_APE_PATCH:
3896         case BNX_DIR_TYPE_KONG_FW:
3897         case BNX_DIR_TYPE_KONG_PATCH:
3898         case BNX_DIR_TYPE_BONO_FW:
3899         case BNX_DIR_TYPE_BONO_PATCH:
3900                 /* FALLTHROUGH */
3901                 return true;
3902         }
3903
3904         return false;
3905 }
3906
3907 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3908 {
3909         switch (dir_type) {
3910         case BNX_DIR_TYPE_AVS:
3911         case BNX_DIR_TYPE_EXP_ROM_MBA:
3912         case BNX_DIR_TYPE_PCIE:
3913         case BNX_DIR_TYPE_TSCF_UCODE:
3914         case BNX_DIR_TYPE_EXT_PHY:
3915         case BNX_DIR_TYPE_CCM:
3916         case BNX_DIR_TYPE_ISCSI_BOOT:
3917         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3918         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3919                 /* FALLTHROUGH */
3920                 return true;
3921         }
3922
3923         return false;
3924 }
3925
3926 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3927 {
3928         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3929                 bnxt_dir_type_is_other_exec_format(dir_type);
3930 }
3931
3932 static int
3933 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3934                 struct rte_dev_eeprom_info *in_eeprom)
3935 {
3936         struct bnxt *bp = dev->data->dev_private;
3937         uint8_t index, dir_op;
3938         uint16_t type, ext, ordinal, attr;
3939         int rc;
3940
3941         rc = is_bnxt_in_error(bp);
3942         if (rc)
3943                 return rc;
3944
3945         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3946                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3947                     bp->pdev->addr.devid, bp->pdev->addr.function,
3948                     in_eeprom->offset, in_eeprom->length);
3949
3950         if (!BNXT_PF(bp)) {
3951                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3952                 return -EINVAL;
3953         }
3954
3955         type = in_eeprom->magic >> 16;
3956
3957         if (type == 0xffff) { /* special value for directory operations */
3958                 index = in_eeprom->magic & 0xff;
3959                 dir_op = in_eeprom->magic >> 8;
3960                 if (index == 0)
3961                         return -EINVAL;
3962                 switch (dir_op) {
3963                 case 0x0e: /* erase */
3964                         if (in_eeprom->offset != ~in_eeprom->magic)
3965                                 return -EINVAL;
3966                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3967                 default:
3968                         return -EINVAL;
3969                 }
3970         }
3971
3972         /* Create or re-write an NVM item: */
3973         if (bnxt_dir_type_is_executable(type) == true)
3974                 return -EOPNOTSUPP;
3975         ext = in_eeprom->magic & 0xffff;
3976         ordinal = in_eeprom->offset >> 16;
3977         attr = in_eeprom->offset & 0xffff;
3978
3979         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3980                                      in_eeprom->data, in_eeprom->length);
3981 }
3982
3983 /*
3984  * Initialization
3985  */
3986
3987 static const struct eth_dev_ops bnxt_dev_ops = {
3988         .dev_infos_get = bnxt_dev_info_get_op,
3989         .dev_close = bnxt_dev_close_op,
3990         .dev_configure = bnxt_dev_configure_op,
3991         .dev_start = bnxt_dev_start_op,
3992         .dev_stop = bnxt_dev_stop_op,
3993         .dev_set_link_up = bnxt_dev_set_link_up_op,
3994         .dev_set_link_down = bnxt_dev_set_link_down_op,
3995         .stats_get = bnxt_stats_get_op,
3996         .stats_reset = bnxt_stats_reset_op,
3997         .rx_queue_setup = bnxt_rx_queue_setup_op,
3998         .rx_queue_release = bnxt_rx_queue_release_op,
3999         .tx_queue_setup = bnxt_tx_queue_setup_op,
4000         .tx_queue_release = bnxt_tx_queue_release_op,
4001         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4002         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4003         .reta_update = bnxt_reta_update_op,
4004         .reta_query = bnxt_reta_query_op,
4005         .rss_hash_update = bnxt_rss_hash_update_op,
4006         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4007         .link_update = bnxt_link_update_op,
4008         .promiscuous_enable = bnxt_promiscuous_enable_op,
4009         .promiscuous_disable = bnxt_promiscuous_disable_op,
4010         .allmulticast_enable = bnxt_allmulticast_enable_op,
4011         .allmulticast_disable = bnxt_allmulticast_disable_op,
4012         .mac_addr_add = bnxt_mac_addr_add_op,
4013         .mac_addr_remove = bnxt_mac_addr_remove_op,
4014         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4015         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4016         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4017         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4018         .vlan_filter_set = bnxt_vlan_filter_set_op,
4019         .vlan_offload_set = bnxt_vlan_offload_set_op,
4020         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4021         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4022         .mtu_set = bnxt_mtu_set_op,
4023         .mac_addr_set = bnxt_set_default_mac_addr_op,
4024         .xstats_get = bnxt_dev_xstats_get_op,
4025         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4026         .xstats_reset = bnxt_dev_xstats_reset_op,
4027         .fw_version_get = bnxt_fw_version_get,
4028         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4029         .rxq_info_get = bnxt_rxq_info_get_op,
4030         .txq_info_get = bnxt_txq_info_get_op,
4031         .dev_led_on = bnxt_dev_led_on_op,
4032         .dev_led_off = bnxt_dev_led_off_op,
4033         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4034         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4035         .rx_queue_count = bnxt_rx_queue_count_op,
4036         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4037         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4038         .rx_queue_start = bnxt_rx_queue_start,
4039         .rx_queue_stop = bnxt_rx_queue_stop,
4040         .tx_queue_start = bnxt_tx_queue_start,
4041         .tx_queue_stop = bnxt_tx_queue_stop,
4042         .filter_ctrl = bnxt_filter_ctrl_op,
4043         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4044         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4045         .get_eeprom           = bnxt_get_eeprom_op,
4046         .set_eeprom           = bnxt_set_eeprom_op,
4047         .timesync_enable      = bnxt_timesync_enable,
4048         .timesync_disable     = bnxt_timesync_disable,
4049         .timesync_read_time   = bnxt_timesync_read_time,
4050         .timesync_write_time   = bnxt_timesync_write_time,
4051         .timesync_adjust_time = bnxt_timesync_adjust_time,
4052         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4053         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4054 };
4055
4056 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4057 {
4058         uint32_t offset;
4059
4060         /* Only pre-map the reset GRC registers using window 3 */
4061         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4062                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4063
4064         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4065
4066         return offset;
4067 }
4068
4069 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4070 {
4071         struct bnxt_error_recovery_info *info = bp->recovery_info;
4072         uint32_t reg_base = 0xffffffff;
4073         int i;
4074
4075         /* Only pre-map the monitoring GRC registers using window 2 */
4076         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4077                 uint32_t reg = info->status_regs[i];
4078
4079                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4080                         continue;
4081
4082                 if (reg_base == 0xffffffff)
4083                         reg_base = reg & 0xfffff000;
4084                 if ((reg & 0xfffff000) != reg_base)
4085                         return -ERANGE;
4086
4087                 /* Use mask 0xffc as the Lower 2 bits indicates
4088                  * address space location
4089                  */
4090                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4091                                                 (reg & 0xffc);
4092         }
4093
4094         if (reg_base == 0xffffffff)
4095                 return 0;
4096
4097         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4098                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4099
4100         return 0;
4101 }
4102
4103 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4104 {
4105         struct bnxt_error_recovery_info *info = bp->recovery_info;
4106         uint32_t delay = info->delay_after_reset[index];
4107         uint32_t val = info->reset_reg_val[index];
4108         uint32_t reg = info->reset_reg[index];
4109         uint32_t type, offset;
4110
4111         type = BNXT_FW_STATUS_REG_TYPE(reg);
4112         offset = BNXT_FW_STATUS_REG_OFF(reg);
4113
4114         switch (type) {
4115         case BNXT_FW_STATUS_REG_TYPE_CFG:
4116                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4117                 break;
4118         case BNXT_FW_STATUS_REG_TYPE_GRC:
4119                 offset = bnxt_map_reset_regs(bp, offset);
4120                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4121                 break;
4122         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4123                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4124                 break;
4125         }
4126         /* wait on a specific interval of time until core reset is complete */
4127         if (delay)
4128                 rte_delay_ms(delay);
4129 }
4130
4131 static void bnxt_dev_cleanup(struct bnxt *bp)
4132 {
4133         bnxt_set_hwrm_link_config(bp, false);
4134         bp->link_info.link_up = 0;
4135         if (bp->eth_dev->data->dev_started)
4136                 bnxt_dev_stop_op(bp->eth_dev);
4137
4138         bnxt_uninit_resources(bp, true);
4139 }
4140
4141 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4142 {
4143         struct rte_eth_dev *dev = bp->eth_dev;
4144         struct rte_vlan_filter_conf *vfc;
4145         int vidx, vbit, rc;
4146         uint16_t vlan_id;
4147
4148         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4149                 vfc = &dev->data->vlan_filter_conf;
4150                 vidx = vlan_id / 64;
4151                 vbit = vlan_id % 64;
4152
4153                 /* Each bit corresponds to a VLAN id */
4154                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4155                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4156                         if (rc)
4157                                 return rc;
4158                 }
4159         }
4160
4161         return 0;
4162 }
4163
4164 static int bnxt_restore_mac_filters(struct bnxt *bp)
4165 {
4166         struct rte_eth_dev *dev = bp->eth_dev;
4167         struct rte_eth_dev_info dev_info;
4168         struct rte_ether_addr *addr;
4169         uint64_t pool_mask;
4170         uint32_t pool = 0;
4171         uint16_t i;
4172         int rc;
4173
4174         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4175                 return 0;
4176
4177         rc = bnxt_dev_info_get_op(dev, &dev_info);
4178         if (rc)
4179                 return rc;
4180
4181         /* replay MAC address configuration */
4182         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4183                 addr = &dev->data->mac_addrs[i];
4184
4185                 /* skip zero address */
4186                 if (rte_is_zero_ether_addr(addr))
4187                         continue;
4188
4189                 pool = 0;
4190                 pool_mask = dev->data->mac_pool_sel[i];
4191
4192                 do {
4193                         if (pool_mask & 1ULL) {
4194                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4195                                 if (rc)
4196                                         return rc;
4197                         }
4198                         pool_mask >>= 1;
4199                         pool++;
4200                 } while (pool_mask);
4201         }
4202
4203         return 0;
4204 }
4205
4206 static int bnxt_restore_filters(struct bnxt *bp)
4207 {
4208         struct rte_eth_dev *dev = bp->eth_dev;
4209         int ret = 0;
4210
4211         if (dev->data->all_multicast) {
4212                 ret = bnxt_allmulticast_enable_op(dev);
4213                 if (ret)
4214                         return ret;
4215         }
4216         if (dev->data->promiscuous) {
4217                 ret = bnxt_promiscuous_enable_op(dev);
4218                 if (ret)
4219                         return ret;
4220         }
4221
4222         ret = bnxt_restore_mac_filters(bp);
4223         if (ret)
4224                 return ret;
4225
4226         ret = bnxt_restore_vlan_filters(bp);
4227         /* TODO restore other filters as well */
4228         return ret;
4229 }
4230
4231 static void bnxt_dev_recover(void *arg)
4232 {
4233         struct bnxt *bp = arg;
4234         int timeout = bp->fw_reset_max_msecs;
4235         int rc = 0;
4236
4237         /* Clear Error flag so that device re-init should happen */
4238         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4239
4240         do {
4241                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4242                 if (rc == 0)
4243                         break;
4244                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4245                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4246         } while (rc && timeout);
4247
4248         if (rc) {
4249                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4250                 goto err;
4251         }
4252
4253         rc = bnxt_init_resources(bp, true);
4254         if (rc) {
4255                 PMD_DRV_LOG(ERR,
4256                             "Failed to initialize resources after reset\n");
4257                 goto err;
4258         }
4259         /* clear reset flag as the device is initialized now */
4260         bp->flags &= ~BNXT_FLAG_FW_RESET;
4261
4262         rc = bnxt_dev_start_op(bp->eth_dev);
4263         if (rc) {
4264                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4265                 goto err_start;
4266         }
4267
4268         rc = bnxt_restore_filters(bp);
4269         if (rc)
4270                 goto err_start;
4271
4272         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4273         return;
4274 err_start:
4275         bnxt_dev_stop_op(bp->eth_dev);
4276 err:
4277         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4278         bnxt_uninit_resources(bp, false);
4279         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4280 }
4281
4282 void bnxt_dev_reset_and_resume(void *arg)
4283 {
4284         struct bnxt *bp = arg;
4285         int rc;
4286
4287         bnxt_dev_cleanup(bp);
4288
4289         bnxt_wait_for_device_shutdown(bp);
4290
4291         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4292                                bnxt_dev_recover, (void *)bp);
4293         if (rc)
4294                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4295 }
4296
4297 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4298 {
4299         struct bnxt_error_recovery_info *info = bp->recovery_info;
4300         uint32_t reg = info->status_regs[index];
4301         uint32_t type, offset, val = 0;
4302
4303         type = BNXT_FW_STATUS_REG_TYPE(reg);
4304         offset = BNXT_FW_STATUS_REG_OFF(reg);
4305
4306         switch (type) {
4307         case BNXT_FW_STATUS_REG_TYPE_CFG:
4308                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4309                 break;
4310         case BNXT_FW_STATUS_REG_TYPE_GRC:
4311                 offset = info->mapped_status_regs[index];
4312                 /* FALLTHROUGH */
4313         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4314                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4315                                        offset));
4316                 break;
4317         }
4318
4319         return val;
4320 }
4321
4322 static int bnxt_fw_reset_all(struct bnxt *bp)
4323 {
4324         struct bnxt_error_recovery_info *info = bp->recovery_info;
4325         uint32_t i;
4326         int rc = 0;
4327
4328         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4329                 /* Reset through master function driver */
4330                 for (i = 0; i < info->reg_array_cnt; i++)
4331                         bnxt_write_fw_reset_reg(bp, i);
4332                 /* Wait for time specified by FW after triggering reset */
4333                 rte_delay_ms(info->master_func_wait_period_after_reset);
4334         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4335                 /* Reset with the help of Kong processor */
4336                 rc = bnxt_hwrm_fw_reset(bp);
4337                 if (rc)
4338                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4339         }
4340
4341         return rc;
4342 }
4343
4344 static void bnxt_fw_reset_cb(void *arg)
4345 {
4346         struct bnxt *bp = arg;
4347         struct bnxt_error_recovery_info *info = bp->recovery_info;
4348         int rc = 0;
4349
4350         /* Only Master function can do FW reset */
4351         if (bnxt_is_master_func(bp) &&
4352             bnxt_is_recovery_enabled(bp)) {
4353                 rc = bnxt_fw_reset_all(bp);
4354                 if (rc) {
4355                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4356                         return;
4357                 }
4358         }
4359
4360         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4361          * EXCEPTION_FATAL_ASYNC event to all the functions
4362          * (including MASTER FUNC). After receiving this Async, all the active
4363          * drivers should treat this case as FW initiated recovery
4364          */
4365         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4366                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4367                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4368
4369                 /* To recover from error */
4370                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4371                                   (void *)bp);
4372         }
4373 }
4374
4375 /* Driver should poll FW heartbeat, reset_counter with the frequency
4376  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4377  * When the driver detects heartbeat stop or change in reset_counter,
4378  * it has to trigger a reset to recover from the error condition.
4379  * A “master PF” is the function who will have the privilege to
4380  * initiate the chimp reset. The master PF will be elected by the
4381  * firmware and will be notified through async message.
4382  */
4383 static void bnxt_check_fw_health(void *arg)
4384 {
4385         struct bnxt *bp = arg;
4386         struct bnxt_error_recovery_info *info = bp->recovery_info;
4387         uint32_t val = 0, wait_msec;
4388
4389         if (!info || !bnxt_is_recovery_enabled(bp) ||
4390             is_bnxt_in_error(bp))
4391                 return;
4392
4393         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4394         if (val == info->last_heart_beat)
4395                 goto reset;
4396
4397         info->last_heart_beat = val;
4398
4399         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4400         if (val != info->last_reset_counter)
4401                 goto reset;
4402
4403         info->last_reset_counter = val;
4404
4405         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4406                           bnxt_check_fw_health, (void *)bp);
4407
4408         return;
4409 reset:
4410         /* Stop DMA to/from device */
4411         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4412         bp->flags |= BNXT_FLAG_FW_RESET;
4413
4414         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4415
4416         if (bnxt_is_master_func(bp))
4417                 wait_msec = info->master_func_wait_period;
4418         else
4419                 wait_msec = info->normal_func_wait_period;
4420
4421         rte_eal_alarm_set(US_PER_MS * wait_msec,
4422                           bnxt_fw_reset_cb, (void *)bp);
4423 }
4424
4425 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4426 {
4427         uint32_t polling_freq;
4428
4429         if (!bnxt_is_recovery_enabled(bp))
4430                 return;
4431
4432         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4433                 return;
4434
4435         polling_freq = bp->recovery_info->driver_polling_freq;
4436
4437         rte_eal_alarm_set(US_PER_MS * polling_freq,
4438                           bnxt_check_fw_health, (void *)bp);
4439         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4440 }
4441
4442 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4443 {
4444         if (!bnxt_is_recovery_enabled(bp))
4445                 return;
4446
4447         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4448         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4449 }
4450
4451 static bool bnxt_vf_pciid(uint16_t device_id)
4452 {
4453         switch (device_id) {
4454         case BROADCOM_DEV_ID_57304_VF:
4455         case BROADCOM_DEV_ID_57406_VF:
4456         case BROADCOM_DEV_ID_5731X_VF:
4457         case BROADCOM_DEV_ID_5741X_VF:
4458         case BROADCOM_DEV_ID_57414_VF:
4459         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4460         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4461         case BROADCOM_DEV_ID_58802_VF:
4462         case BROADCOM_DEV_ID_57500_VF1:
4463         case BROADCOM_DEV_ID_57500_VF2:
4464                 /* FALLTHROUGH */
4465                 return true;
4466         default:
4467                 return false;
4468         }
4469 }
4470
4471 static bool bnxt_thor_device(uint16_t device_id)
4472 {
4473         switch (device_id) {
4474         case BROADCOM_DEV_ID_57508:
4475         case BROADCOM_DEV_ID_57504:
4476         case BROADCOM_DEV_ID_57502:
4477         case BROADCOM_DEV_ID_57508_MF1:
4478         case BROADCOM_DEV_ID_57504_MF1:
4479         case BROADCOM_DEV_ID_57502_MF1:
4480         case BROADCOM_DEV_ID_57508_MF2:
4481         case BROADCOM_DEV_ID_57504_MF2:
4482         case BROADCOM_DEV_ID_57502_MF2:
4483         case BROADCOM_DEV_ID_57500_VF1:
4484         case BROADCOM_DEV_ID_57500_VF2:
4485                 /* FALLTHROUGH */
4486                 return true;
4487         default:
4488                 return false;
4489         }
4490 }
4491
4492 bool bnxt_stratus_device(struct bnxt *bp)
4493 {
4494         uint16_t device_id = bp->pdev->id.device_id;
4495
4496         switch (device_id) {
4497         case BROADCOM_DEV_ID_STRATUS_NIC:
4498         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4499         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4500                 /* FALLTHROUGH */
4501                 return true;
4502         default:
4503                 return false;
4504         }
4505 }
4506
4507 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4508 {
4509         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4510         struct bnxt *bp = eth_dev->data->dev_private;
4511
4512         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4513         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4514         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4515         if (!bp->bar0 || !bp->doorbell_base) {
4516                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4517                 return -ENODEV;
4518         }
4519
4520         bp->eth_dev = eth_dev;
4521         bp->pdev = pci_dev;
4522
4523         return 0;
4524 }
4525
4526 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4527                                   struct bnxt_ctx_pg_info *ctx_pg,
4528                                   uint32_t mem_size,
4529                                   const char *suffix,
4530                                   uint16_t idx)
4531 {
4532         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4533         const struct rte_memzone *mz = NULL;
4534         char mz_name[RTE_MEMZONE_NAMESIZE];
4535         rte_iova_t mz_phys_addr;
4536         uint64_t valid_bits = 0;
4537         uint32_t sz;
4538         int i;
4539
4540         if (!mem_size)
4541                 return 0;
4542
4543         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4544                          BNXT_PAGE_SIZE;
4545         rmem->page_size = BNXT_PAGE_SIZE;
4546         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4547         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4548         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4549
4550         valid_bits = PTU_PTE_VALID;
4551
4552         if (rmem->nr_pages > 1) {
4553                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4554                          "bnxt_ctx_pg_tbl%s_%x_%d",
4555                          suffix, idx, bp->eth_dev->data->port_id);
4556                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4557                 mz = rte_memzone_lookup(mz_name);
4558                 if (!mz) {
4559                         mz = rte_memzone_reserve_aligned(mz_name,
4560                                                 rmem->nr_pages * 8,
4561                                                 SOCKET_ID_ANY,
4562                                                 RTE_MEMZONE_2MB |
4563                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4564                                                 RTE_MEMZONE_IOVA_CONTIG,
4565                                                 BNXT_PAGE_SIZE);
4566                         if (mz == NULL)
4567                                 return -ENOMEM;
4568                 }
4569
4570                 memset(mz->addr, 0, mz->len);
4571                 mz_phys_addr = mz->iova;
4572
4573                 rmem->pg_tbl = mz->addr;
4574                 rmem->pg_tbl_map = mz_phys_addr;
4575                 rmem->pg_tbl_mz = mz;
4576         }
4577
4578         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4579                  suffix, idx, bp->eth_dev->data->port_id);
4580         mz = rte_memzone_lookup(mz_name);
4581         if (!mz) {
4582                 mz = rte_memzone_reserve_aligned(mz_name,
4583                                                  mem_size,
4584                                                  SOCKET_ID_ANY,
4585                                                  RTE_MEMZONE_1GB |
4586                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4587                                                  RTE_MEMZONE_IOVA_CONTIG,
4588                                                  BNXT_PAGE_SIZE);
4589                 if (mz == NULL)
4590                         return -ENOMEM;
4591         }
4592
4593         memset(mz->addr, 0, mz->len);
4594         mz_phys_addr = mz->iova;
4595
4596         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4597                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4598                 rmem->dma_arr[i] = mz_phys_addr + sz;
4599
4600                 if (rmem->nr_pages > 1) {
4601                         if (i == rmem->nr_pages - 2 &&
4602                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4603                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4604                         else if (i == rmem->nr_pages - 1 &&
4605                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4606                                 valid_bits |= PTU_PTE_LAST;
4607
4608                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4609                                                            valid_bits);
4610                 }
4611         }
4612
4613         rmem->mz = mz;
4614         if (rmem->vmem_size)
4615                 rmem->vmem = (void **)mz->addr;
4616         rmem->dma_arr[0] = mz_phys_addr;
4617         return 0;
4618 }
4619
4620 static void bnxt_free_ctx_mem(struct bnxt *bp)
4621 {
4622         int i;
4623
4624         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4625                 return;
4626
4627         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4628         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4629         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4630         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4631         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4632         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4633         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4634         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4635         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4636         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4637         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4638
4639         for (i = 0; i < BNXT_MAX_Q; i++) {
4640                 if (bp->ctx->tqm_mem[i])
4641                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4642         }
4643
4644         rte_free(bp->ctx);
4645         bp->ctx = NULL;
4646 }
4647
4648 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4649
4650 #define min_t(type, x, y) ({                    \
4651         type __min1 = (x);                      \
4652         type __min2 = (y);                      \
4653         __min1 < __min2 ? __min1 : __min2; })
4654
4655 #define max_t(type, x, y) ({                    \
4656         type __max1 = (x);                      \
4657         type __max2 = (y);                      \
4658         __max1 > __max2 ? __max1 : __max2; })
4659
4660 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4661
4662 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4663 {
4664         struct bnxt_ctx_pg_info *ctx_pg;
4665         struct bnxt_ctx_mem_info *ctx;
4666         uint32_t mem_size, ena, entries;
4667         int i, rc;
4668
4669         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4670         if (rc) {
4671                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4672                 return rc;
4673         }
4674         ctx = bp->ctx;
4675         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4676                 return 0;
4677
4678         ctx_pg = &ctx->qp_mem;
4679         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4680         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4681         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4682         if (rc)
4683                 return rc;
4684
4685         ctx_pg = &ctx->srq_mem;
4686         ctx_pg->entries = ctx->srq_max_l2_entries;
4687         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4688         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4689         if (rc)
4690                 return rc;
4691
4692         ctx_pg = &ctx->cq_mem;
4693         ctx_pg->entries = ctx->cq_max_l2_entries;
4694         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4695         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4696         if (rc)
4697                 return rc;
4698
4699         ctx_pg = &ctx->vnic_mem;
4700         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4701                 ctx->vnic_max_ring_table_entries;
4702         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4703         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4704         if (rc)
4705                 return rc;
4706
4707         ctx_pg = &ctx->stat_mem;
4708         ctx_pg->entries = ctx->stat_max_entries;
4709         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4710         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4711         if (rc)
4712                 return rc;
4713
4714         entries = ctx->qp_max_l2_entries +
4715                   ctx->vnic_max_vnic_entries +
4716                   ctx->tqm_min_entries_per_ring;
4717         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4718         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4719                           ctx->tqm_max_entries_per_ring);
4720         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4721                 ctx_pg = ctx->tqm_mem[i];
4722                 /* use min tqm entries for now. */
4723                 ctx_pg->entries = entries;
4724                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4725                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4726                 if (rc)
4727                         return rc;
4728                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4729         }
4730
4731         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4732         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4733         if (rc)
4734                 PMD_DRV_LOG(ERR,
4735                             "Failed to configure context mem: rc = %d\n", rc);
4736         else
4737                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4738
4739         return rc;
4740 }
4741
4742 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4743 {
4744         struct rte_pci_device *pci_dev = bp->pdev;
4745         char mz_name[RTE_MEMZONE_NAMESIZE];
4746         const struct rte_memzone *mz = NULL;
4747         uint32_t total_alloc_len;
4748         rte_iova_t mz_phys_addr;
4749
4750         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4751                 return 0;
4752
4753         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4754                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4755                  pci_dev->addr.bus, pci_dev->addr.devid,
4756                  pci_dev->addr.function, "rx_port_stats");
4757         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4758         mz = rte_memzone_lookup(mz_name);
4759         total_alloc_len =
4760                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4761                                        sizeof(struct rx_port_stats_ext) + 512);
4762         if (!mz) {
4763                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4764                                          SOCKET_ID_ANY,
4765                                          RTE_MEMZONE_2MB |
4766                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4767                                          RTE_MEMZONE_IOVA_CONTIG);
4768                 if (mz == NULL)
4769                         return -ENOMEM;
4770         }
4771         memset(mz->addr, 0, mz->len);
4772         mz_phys_addr = mz->iova;
4773
4774         bp->rx_mem_zone = (const void *)mz;
4775         bp->hw_rx_port_stats = mz->addr;
4776         bp->hw_rx_port_stats_map = mz_phys_addr;
4777
4778         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4779                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4780                  pci_dev->addr.bus, pci_dev->addr.devid,
4781                  pci_dev->addr.function, "tx_port_stats");
4782         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4783         mz = rte_memzone_lookup(mz_name);
4784         total_alloc_len =
4785                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4786                                        sizeof(struct tx_port_stats_ext) + 512);
4787         if (!mz) {
4788                 mz = rte_memzone_reserve(mz_name,
4789                                          total_alloc_len,
4790                                          SOCKET_ID_ANY,
4791                                          RTE_MEMZONE_2MB |
4792                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4793                                          RTE_MEMZONE_IOVA_CONTIG);
4794                 if (mz == NULL)
4795                         return -ENOMEM;
4796         }
4797         memset(mz->addr, 0, mz->len);
4798         mz_phys_addr = mz->iova;
4799
4800         bp->tx_mem_zone = (const void *)mz;
4801         bp->hw_tx_port_stats = mz->addr;
4802         bp->hw_tx_port_stats_map = mz_phys_addr;
4803         bp->flags |= BNXT_FLAG_PORT_STATS;
4804
4805         /* Display extended statistics if FW supports it */
4806         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4807             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4808             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4809                 return 0;
4810
4811         bp->hw_rx_port_stats_ext = (void *)
4812                 ((uint8_t *)bp->hw_rx_port_stats +
4813                  sizeof(struct rx_port_stats));
4814         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4815                 sizeof(struct rx_port_stats);
4816         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4817
4818         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4819             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4820                 bp->hw_tx_port_stats_ext = (void *)
4821                         ((uint8_t *)bp->hw_tx_port_stats +
4822                          sizeof(struct tx_port_stats));
4823                 bp->hw_tx_port_stats_ext_map =
4824                         bp->hw_tx_port_stats_map +
4825                         sizeof(struct tx_port_stats);
4826                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4827         }
4828
4829         return 0;
4830 }
4831
4832 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4833 {
4834         struct bnxt *bp = eth_dev->data->dev_private;
4835         int rc = 0;
4836
4837         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4838                                                RTE_ETHER_ADDR_LEN *
4839                                                bp->max_l2_ctx,
4840                                                0);
4841         if (eth_dev->data->mac_addrs == NULL) {
4842                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4843                 return -ENOMEM;
4844         }
4845
4846         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4847                 if (BNXT_PF(bp))
4848                         return -EINVAL;
4849
4850                 /* Generate a random MAC address, if none was assigned by PF */
4851                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4852                 bnxt_eth_hw_addr_random(bp->mac_addr);
4853                 PMD_DRV_LOG(INFO,
4854                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4855                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4856                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4857
4858                 rc = bnxt_hwrm_set_mac(bp);
4859                 if (!rc)
4860                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4861                                RTE_ETHER_ADDR_LEN);
4862                 return rc;
4863         }
4864
4865         /* Copy the permanent MAC from the FUNC_QCAPS response */
4866         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4867         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4868
4869         return rc;
4870 }
4871
4872 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4873 {
4874         int rc = 0;
4875
4876         /* MAC is already configured in FW */
4877         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4878                 return 0;
4879
4880         /* Restore the old MAC configured */
4881         rc = bnxt_hwrm_set_mac(bp);
4882         if (rc)
4883                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4884
4885         return rc;
4886 }
4887
4888 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4889 {
4890         if (!BNXT_PF(bp))
4891                 return;
4892
4893 #define ALLOW_FUNC(x)   \
4894         { \
4895                 uint32_t arg = (x); \
4896                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4897                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4898         }
4899
4900         /* Forward all requests if firmware is new enough */
4901         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4902              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4903             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4904                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4905         } else {
4906                 PMD_DRV_LOG(WARNING,
4907                             "Firmware too old for VF mailbox functionality\n");
4908                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4909         }
4910
4911         /*
4912          * The following are used for driver cleanup. If we disallow these,
4913          * VF drivers can't clean up cleanly.
4914          */
4915         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4916         ALLOW_FUNC(HWRM_VNIC_FREE);
4917         ALLOW_FUNC(HWRM_RING_FREE);
4918         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4919         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4920         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4921         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4922         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4923         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4924 }
4925
4926 uint16_t
4927 bnxt_get_svif(uint16_t port_id, bool func_svif)
4928 {
4929         struct rte_eth_dev *eth_dev;
4930         struct bnxt *bp;
4931
4932         eth_dev = &rte_eth_devices[port_id];
4933         bp = eth_dev->data->dev_private;
4934
4935         return func_svif ? bp->func_svif : bp->port_svif;
4936 }
4937
4938 uint16_t
4939 bnxt_get_vnic_id(uint16_t port)
4940 {
4941         struct rte_eth_dev *eth_dev;
4942         struct bnxt_vnic_info *vnic;
4943         struct bnxt *bp;
4944
4945         eth_dev = &rte_eth_devices[port];
4946         bp = eth_dev->data->dev_private;
4947
4948         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4949
4950         return vnic->fw_vnic_id;
4951 }
4952
4953 uint16_t
4954 bnxt_get_fw_func_id(uint16_t port)
4955 {
4956         struct rte_eth_dev *eth_dev;
4957         struct bnxt *bp;
4958
4959         eth_dev = &rte_eth_devices[port];
4960         bp = eth_dev->data->dev_private;
4961
4962         return bp->fw_fid;
4963 }
4964
4965 static int bnxt_init_fw(struct bnxt *bp)
4966 {
4967         uint16_t mtu;
4968         int rc = 0;
4969
4970         bp->fw_cap = 0;
4971
4972         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4973         if (rc)
4974                 return rc;
4975
4976         rc = bnxt_hwrm_func_reset(bp);
4977         if (rc)
4978                 return -EIO;
4979
4980         rc = bnxt_hwrm_vnic_qcaps(bp);
4981         if (rc)
4982                 return rc;
4983
4984         rc = bnxt_hwrm_queue_qportcfg(bp);
4985         if (rc)
4986                 return rc;
4987
4988         /* Get the MAX capabilities for this function.
4989          * This function also allocates context memory for TQM rings and
4990          * informs the firmware about this allocated backing store memory.
4991          */
4992         rc = bnxt_hwrm_func_qcaps(bp);
4993         if (rc)
4994                 return rc;
4995
4996         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4997         if (rc)
4998                 return rc;
4999
5000         bnxt_hwrm_port_mac_qcfg(bp);
5001
5002         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5003         if (rc)
5004                 return rc;
5005
5006         /* Get the adapter error recovery support info */
5007         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5008         if (rc)
5009                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5010
5011         bnxt_hwrm_port_led_qcaps(bp);
5012
5013         return 0;
5014 }
5015
5016 static int
5017 bnxt_init_locks(struct bnxt *bp)
5018 {
5019         int err;
5020
5021         err = pthread_mutex_init(&bp->flow_lock, NULL);
5022         if (err) {
5023                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5024                 return err;
5025         }
5026
5027         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5028         if (err)
5029                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5030         return err;
5031 }
5032
5033 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5034 {
5035         int rc;
5036
5037         rc = bnxt_init_fw(bp);
5038         if (rc)
5039                 return rc;
5040
5041         if (!reconfig_dev) {
5042                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5043                 if (rc)
5044                         return rc;
5045         } else {
5046                 rc = bnxt_restore_dflt_mac(bp);
5047                 if (rc)
5048                         return rc;
5049         }
5050
5051         bnxt_config_vf_req_fwd(bp);
5052
5053         rc = bnxt_hwrm_func_driver_register(bp);
5054         if (rc) {
5055                 PMD_DRV_LOG(ERR, "Failed to register driver");
5056                 return -EBUSY;
5057         }
5058
5059         if (BNXT_PF(bp)) {
5060                 if (bp->pdev->max_vfs) {
5061                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5062                         if (rc) {
5063                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5064                                 return rc;
5065                         }
5066                 } else {
5067                         rc = bnxt_hwrm_allocate_pf_only(bp);
5068                         if (rc) {
5069                                 PMD_DRV_LOG(ERR,
5070                                             "Failed to allocate PF resources");
5071                                 return rc;
5072                         }
5073                 }
5074         }
5075
5076         rc = bnxt_alloc_mem(bp, reconfig_dev);
5077         if (rc)
5078                 return rc;
5079
5080         rc = bnxt_setup_int(bp);
5081         if (rc)
5082                 return rc;
5083
5084         rc = bnxt_request_int(bp);
5085         if (rc)
5086                 return rc;
5087
5088         rc = bnxt_init_ctx_mem(bp);
5089         if (rc) {
5090                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5091                 return rc;
5092         }
5093
5094         rc = bnxt_init_locks(bp);
5095         if (rc)
5096                 return rc;
5097
5098         return 0;
5099 }
5100
5101 static int
5102 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5103                           const char *value, void *opaque_arg)
5104 {
5105         struct bnxt *bp = opaque_arg;
5106         unsigned long truflow;
5107         char *end = NULL;
5108
5109         if (!value || !opaque_arg) {
5110                 PMD_DRV_LOG(ERR,
5111                             "Invalid parameter passed to truflow devargs.\n");
5112                 return -EINVAL;
5113         }
5114
5115         truflow = strtoul(value, &end, 10);
5116         if (end == NULL || *end != '\0' ||
5117             (truflow == ULONG_MAX && errno == ERANGE)) {
5118                 PMD_DRV_LOG(ERR,
5119                             "Invalid parameter passed to truflow devargs.\n");
5120                 return -EINVAL;
5121         }
5122
5123         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5124                 PMD_DRV_LOG(ERR,
5125                             "Invalid value passed to truflow devargs.\n");
5126                 return -EINVAL;
5127         }
5128
5129         bp->truflow = truflow;
5130         if (bp->truflow)
5131                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5132
5133         return 0;
5134 }
5135
5136 static int
5137 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5138                              const char *value, void *opaque_arg)
5139 {
5140         struct bnxt *bp = opaque_arg;
5141         unsigned long flow_xstat;
5142         char *end = NULL;
5143
5144         if (!value || !opaque_arg) {
5145                 PMD_DRV_LOG(ERR,
5146                             "Invalid parameter passed to flow_xstat devarg.\n");
5147                 return -EINVAL;
5148         }
5149
5150         flow_xstat = strtoul(value, &end, 10);
5151         if (end == NULL || *end != '\0' ||
5152             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5153                 PMD_DRV_LOG(ERR,
5154                             "Invalid parameter passed to flow_xstat devarg.\n");
5155                 return -EINVAL;
5156         }
5157
5158         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5159                 PMD_DRV_LOG(ERR,
5160                             "Invalid value passed to flow_xstat devarg.\n");
5161                 return -EINVAL;
5162         }
5163
5164         bp->flow_xstat = flow_xstat;
5165         if (bp->flow_xstat)
5166                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5167
5168         return 0;
5169 }
5170
5171 static void
5172 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5173 {
5174         struct rte_kvargs *kvlist;
5175
5176         if (devargs == NULL)
5177                 return;
5178
5179         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5180         if (kvlist == NULL)
5181                 return;
5182
5183         /*
5184          * Handler for "truflow" devarg.
5185          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1”
5186          */
5187         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5188                            bnxt_parse_devarg_truflow, bp);
5189
5190         /*
5191          * Handler for "flow_xstat" devarg.
5192          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1”
5193          */
5194         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5195                            bnxt_parse_devarg_flow_xstat, bp);
5196
5197         rte_kvargs_free(kvlist);
5198 }
5199
5200 static int
5201 bnxt_dev_init(struct rte_eth_dev *eth_dev)
5202 {
5203         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5204         static int version_printed;
5205         struct bnxt *bp;
5206         int rc;
5207
5208         if (version_printed++ == 0)
5209                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5210
5211         eth_dev->dev_ops = &bnxt_dev_ops;
5212         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5213         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5214
5215         /*
5216          * For secondary processes, we don't initialise any further
5217          * as primary has already done this work.
5218          */
5219         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5220                 return 0;
5221
5222         rte_eth_copy_pci_info(eth_dev, pci_dev);
5223
5224         bp = eth_dev->data->dev_private;
5225
5226         /* Parse dev arguments passed on when starting the DPDK application. */
5227         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5228
5229         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5230
5231         if (bnxt_vf_pciid(pci_dev->id.device_id))
5232                 bp->flags |= BNXT_FLAG_VF;
5233
5234         if (bnxt_thor_device(pci_dev->id.device_id))
5235                 bp->flags |= BNXT_FLAG_THOR_CHIP;
5236
5237         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5238             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5239             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5240             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5241                 bp->flags |= BNXT_FLAG_STINGRAY;
5242
5243         rc = bnxt_init_board(eth_dev);
5244         if (rc) {
5245                 PMD_DRV_LOG(ERR,
5246                             "Failed to initialize board rc: %x\n", rc);
5247                 return rc;
5248         }
5249
5250         rc = bnxt_alloc_hwrm_resources(bp);
5251         if (rc) {
5252                 PMD_DRV_LOG(ERR,
5253                             "Failed to allocate hwrm resource rc: %x\n", rc);
5254                 goto error_free;
5255         }
5256         rc = bnxt_init_resources(bp, false);
5257         if (rc)
5258                 goto error_free;
5259
5260         rc = bnxt_alloc_stats_mem(bp);
5261         if (rc)
5262                 goto error_free;
5263
5264         /* Pass the information to the rte_eth_dev_close() that it should also
5265          * release the private port resources.
5266          */
5267         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5268
5269         PMD_DRV_LOG(INFO,
5270                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5271                     pci_dev->mem_resource[0].phys_addr,
5272                     pci_dev->mem_resource[0].addr);
5273
5274         return 0;
5275
5276 error_free:
5277         bnxt_dev_uninit(eth_dev);
5278         return rc;
5279 }
5280
5281
5282 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5283 {
5284         if (!ctx)
5285                 return;
5286
5287         if (ctx->va)
5288                 rte_free(ctx->va);
5289
5290         ctx->va = NULL;
5291         ctx->dma = RTE_BAD_IOVA;
5292         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5293 }
5294
5295 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5296 {
5297         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5298                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5299                                   bp->rx_fc_out_tbl.ctx_id,
5300                                   bp->max_fc,
5301                                   false);
5302
5303         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5304                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5305                                   bp->tx_fc_out_tbl.ctx_id,
5306                                   bp->max_fc,
5307                                   false);
5308
5309         if (bp->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5310                 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_in_tbl.ctx_id);
5311         bp->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5312
5313         if (bp->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5314                 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_out_tbl.ctx_id);
5315         bp->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5316
5317         if (bp->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5318                 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_in_tbl.ctx_id);
5319         bp->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5320
5321         if (bp->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5322                 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_out_tbl.ctx_id);
5323         bp->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5324 }
5325
5326 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5327 {
5328         bnxt_unregister_fc_ctx_mem(bp);
5329
5330         bnxt_free_ctx_mem_buf(&bp->rx_fc_in_tbl);
5331         bnxt_free_ctx_mem_buf(&bp->rx_fc_out_tbl);
5332         bnxt_free_ctx_mem_buf(&bp->tx_fc_in_tbl);
5333         bnxt_free_ctx_mem_buf(&bp->tx_fc_out_tbl);
5334 }
5335
5336 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5337 {
5338         bnxt_uninit_fc_ctx_mem(bp);
5339 }
5340
5341 static void
5342 bnxt_uninit_locks(struct bnxt *bp)
5343 {
5344         pthread_mutex_destroy(&bp->flow_lock);
5345         pthread_mutex_destroy(&bp->def_cp_lock);
5346 }
5347
5348 static int
5349 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5350 {
5351         int rc;
5352
5353         bnxt_free_int(bp);
5354         bnxt_free_mem(bp, reconfig_dev);
5355         bnxt_hwrm_func_buf_unrgtr(bp);
5356         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5357         bp->flags &= ~BNXT_FLAG_REGISTERED;
5358         bnxt_free_ctx_mem(bp);
5359         if (!reconfig_dev) {
5360                 bnxt_free_hwrm_resources(bp);
5361
5362                 if (bp->recovery_info != NULL) {
5363                         rte_free(bp->recovery_info);
5364                         bp->recovery_info = NULL;
5365                 }
5366         }
5367
5368         bnxt_uninit_ctx_mem(bp);
5369
5370         bnxt_uninit_locks(bp);
5371         rte_free(bp->ptp_cfg);
5372         bp->ptp_cfg = NULL;
5373         return rc;
5374 }
5375
5376 static int
5377 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5378 {
5379         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5380                 return -EPERM;
5381
5382         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5383
5384         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5385                 bnxt_dev_close_op(eth_dev);
5386
5387         return 0;
5388 }
5389
5390 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5391         struct rte_pci_device *pci_dev)
5392 {
5393         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
5394                 bnxt_dev_init);
5395 }
5396
5397 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5398 {
5399         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
5400                 return rte_eth_dev_pci_generic_remove(pci_dev,
5401                                 bnxt_dev_uninit);
5402         else
5403                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5404 }
5405
5406 static struct rte_pci_driver bnxt_rte_pmd = {
5407         .id_table = bnxt_pci_id_map,
5408         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5409         .probe = bnxt_pci_probe,
5410         .remove = bnxt_pci_remove,
5411 };
5412
5413 static bool
5414 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5415 {
5416         if (strcmp(dev->device->driver->name, drv->driver.name))
5417                 return false;
5418
5419         return true;
5420 }
5421
5422 bool is_bnxt_supported(struct rte_eth_dev *dev)
5423 {
5424         return is_device_supported(dev, &bnxt_rte_pmd);
5425 }
5426
5427 RTE_INIT(bnxt_init_log)
5428 {
5429         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
5430         if (bnxt_logtype_driver >= 0)
5431                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
5432 }
5433
5434 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5435 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5436 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");