drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31
  32 #define DRV_MODULE_NAME         "bnxt"
  33 static const char bnxt_version[] =
  34         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  35
  36 /*
  37  * The set of PCI devices this driver supports
  38  */
  39 static const struct rte_pci_id bnxt_pci_id_map[] = {
  40         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  41                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  93         { .vendor_id = 0, /* sentinel */ },
  94 };
  95
  96 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  97 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  98 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  99 static const char *const bnxt_dev_args[] = {
 100         BNXT_DEVARG_TRUFLOW,
 101         BNXT_DEVARG_FLOW_XSTAT,
 102         BNXT_DEVARG_MAX_NUM_KFLOWS,
 103         NULL
 104 };
 105
 106 /*
 107  * truflow == false to disable the feature
 108  * truflow == true to enable the feature
 109  */
 110 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 111
 112 /*
 113  * flow_xstat == false to disable the feature
 114  * flow_xstat == true to enable the feature
 115  */
 116 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 117
 118 /*
 119  * max_num_kflows must be >= 32
 120  * and must be a power-of-2 supported value
 121  * return: 1 -> invalid
 122  *         0 -> valid
 123  */
 124 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 125 {
 126         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 127                 return 1;
 128         return 0;
 129 }
 130
 131 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 132 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 133 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 134 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 135 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 136 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 137 static void bnxt_dev_recover(void *arg);
 138 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 139
 140 int is_bnxt_in_error(struct bnxt *bp)
 141 {
 142         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 143                 return -EIO;
 144         if (bp->flags & BNXT_FLAG_FW_RESET)
 145                 return -EBUSY;
 146
 147         return 0;
 148 }
 149
 150 /***********************/
 151
 152 /*
 153  * High level utility functions
 154  */
 155
 156 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 157 {
 158         if (!BNXT_CHIP_THOR(bp))
 159                 return 1;
 160
 161         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 162                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 163                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 164 }
 165
 166 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 167 {
 168         if (!BNXT_CHIP_THOR(bp))
 169                 return HW_HASH_INDEX_SIZE;
 170
 171         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 172 }
 173
 174 static void bnxt_free_pf_info(struct bnxt *bp)
 175 {
 176         rte_free(bp->pf);
 177 }
 178
 179 static void bnxt_free_link_info(struct bnxt *bp)
 180 {
 181         rte_free(bp->link_info);
 182 }
 183
 184 static void bnxt_free_leds_info(struct bnxt *bp)
 185 {
 186         rte_free(bp->leds);
 187         bp->leds = NULL;
 188 }
 189
 190 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 191 {
 192         rte_free(bp->flow_stat);
 193         bp->flow_stat = NULL;
 194 }
 195
 196 static void bnxt_free_cos_queues(struct bnxt *bp)
 197 {
 198         rte_free(bp->rx_cos_queue);
 199         rte_free(bp->tx_cos_queue);
 200 }
 201
 202 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 203 {
 204         bnxt_free_filter_mem(bp);
 205         bnxt_free_vnic_attributes(bp);
 206         bnxt_free_vnic_mem(bp);
 207
 208         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 209          * If the number of rings change across fw update,
 210          * we don't have much choice except to warn the user.
 211          */
 212         if (!reconfig) {
 213                 bnxt_free_stats(bp);
 214                 bnxt_free_tx_rings(bp);
 215                 bnxt_free_rx_rings(bp);
 216         }
 217         bnxt_free_async_cp_ring(bp);
 218         bnxt_free_rxtx_nq_ring(bp);
 219
 220         rte_free(bp->grp_info);
 221         bp->grp_info = NULL;
 222 }
 223
 224 static int bnxt_alloc_pf_info(struct bnxt *bp)
 225 {
 226         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 227         if (bp->pf == NULL)
 228                 return -ENOMEM;
 229
 230         return 0;
 231 }
 232
 233 static int bnxt_alloc_link_info(struct bnxt *bp)
 234 {
 235         bp->link_info =
 236                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 237         if (bp->link_info == NULL)
 238                 return -ENOMEM;
 239
 240         return 0;
 241 }
 242
 243 static int bnxt_alloc_leds_info(struct bnxt *bp)
 244 {
 245         bp->leds = rte_zmalloc("bnxt_leds",
 246                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 247                                0);
 248         if (bp->leds == NULL)
 249                 return -ENOMEM;
 250
 251         return 0;
 252 }
 253
 254 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 255 {
 256         bp->rx_cos_queue =
 257                 rte_zmalloc("bnxt_rx_cosq",
 258                             BNXT_COS_QUEUE_COUNT *
 259                             sizeof(struct bnxt_cos_queue_info),
 260                             0);
 261         if (bp->rx_cos_queue == NULL)
 262                 return -ENOMEM;
 263
 264         bp->tx_cos_queue =
 265                 rte_zmalloc("bnxt_tx_cosq",
 266                             BNXT_COS_QUEUE_COUNT *
 267                             sizeof(struct bnxt_cos_queue_info),
 268                             0);
 269         if (bp->tx_cos_queue == NULL)
 270                 return -ENOMEM;
 271
 272         return 0;
 273 }
 274
 275 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 276 {
 277         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 278                                     sizeof(struct bnxt_flow_stat_info), 0);
 279         if (bp->flow_stat == NULL)
 280                 return -ENOMEM;
 281
 282         return 0;
 283 }
 284
 285 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 286 {
 287         int rc;
 288
 289         rc = bnxt_alloc_ring_grps(bp);
 290         if (rc)
 291                 goto alloc_mem_err;
 292
 293         rc = bnxt_alloc_async_ring_struct(bp);
 294         if (rc)
 295                 goto alloc_mem_err;
 296
 297         rc = bnxt_alloc_vnic_mem(bp);
 298         if (rc)
 299                 goto alloc_mem_err;
 300
 301         rc = bnxt_alloc_vnic_attributes(bp);
 302         if (rc)
 303                 goto alloc_mem_err;
 304
 305         rc = bnxt_alloc_filter_mem(bp);
 306         if (rc)
 307                 goto alloc_mem_err;
 308
 309         rc = bnxt_alloc_async_cp_ring(bp);
 310         if (rc)
 311                 goto alloc_mem_err;
 312
 313         rc = bnxt_alloc_rxtx_nq_ring(bp);
 314         if (rc)
 315                 goto alloc_mem_err;
 316
 317         if (BNXT_FLOW_XSTATS_EN(bp)) {
 318                 rc = bnxt_alloc_flow_stats_info(bp);
 319                 if (rc)
 320                         goto alloc_mem_err;
 321         }
 322
 323         return 0;
 324
 325 alloc_mem_err:
 326         bnxt_free_mem(bp, reconfig);
 327         return rc;
 328 }
 329
 330 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 331 {
 332         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 333         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 334         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 335         struct bnxt_rx_queue *rxq;
 336         unsigned int j;
 337         int rc;
 338
 339         rc = bnxt_vnic_grp_alloc(bp, vnic);
 340         if (rc)
 341                 goto err_out;
 342
 343         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 344                     vnic_id, vnic, vnic->fw_grp_ids);
 345
 346         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 347         if (rc)
 348                 goto err_out;
 349
 350         /* Alloc RSS context only if RSS mode is enabled */
 351         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 352                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 353
 354                 rc = 0;
 355                 for (j = 0; j < nr_ctxs; j++) {
 356                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 357                         if (rc)
 358                                 break;
 359                 }
 360                 if (rc) {
 361                         PMD_DRV_LOG(ERR,
 362                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 363                                     vnic_id, j, rc);
 364                         goto err_out;
 365                 }
 366                 vnic->num_lb_ctxts = nr_ctxs;
 367         }
 368
 369         /*
 370          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 371          * setting is not available at this time, it will not be
 372          * configured correctly in the CFA.
 373          */
 374         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 375                 vnic->vlan_strip = true;
 376         else
 377                 vnic->vlan_strip = false;
 378
 379         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 380         if (rc)
 381                 goto err_out;
 382
 383         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 384         if (rc)
 385                 goto err_out;
 386
 387         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 388                 rxq = bp->eth_dev->data->rx_queues[j];
 389
 390                 PMD_DRV_LOG(DEBUG,
 391                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 392                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 393
 394                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 395                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 396                 else
 397                         vnic->rx_queue_cnt++;
 398         }
 399
 400         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 401
 402         rc = bnxt_vnic_rss_configure(bp, vnic);
 403         if (rc)
 404                 goto err_out;
 405
 406         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 407
 408         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 409                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 410         else
 411                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 412
 413         return 0;
 414 err_out:
 415         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 416                     vnic_id, rc);
 417         return rc;
 418 }
 419
 420 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 421 {
 422         int rc = 0;
 423
 424         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 425                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 426         if (rc)
 427                 return rc;
 428
 429         PMD_DRV_LOG(DEBUG,
 430                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 431                     " rx_fc_in_tbl.ctx_id = %d\n",
 432                     bp->flow_stat->rx_fc_in_tbl.va,
 433                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 434                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 435
 436         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 437                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 438         if (rc)
 439                 return rc;
 440
 441         PMD_DRV_LOG(DEBUG,
 442                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 443                     " rx_fc_out_tbl.ctx_id = %d\n",
 444                     bp->flow_stat->rx_fc_out_tbl.va,
 445                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 446                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 447
 448         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 449                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 450         if (rc)
 451                 return rc;
 452
 453         PMD_DRV_LOG(DEBUG,
 454                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 455                     " tx_fc_in_tbl.ctx_id = %d\n",
 456                     bp->flow_stat->tx_fc_in_tbl.va,
 457                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 458                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 459
 460         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 461                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 462         if (rc)
 463                 return rc;
 464
 465         PMD_DRV_LOG(DEBUG,
 466                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 467                     " tx_fc_out_tbl.ctx_id = %d\n",
 468                     bp->flow_stat->tx_fc_out_tbl.va,
 469                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 470                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 471
 472         memset(bp->flow_stat->rx_fc_out_tbl.va,
 473                0,
 474                bp->flow_stat->rx_fc_out_tbl.size);
 475         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 476                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 477                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 478                                        bp->flow_stat->max_fc,
 479                                        true);
 480         if (rc)
 481                 return rc;
 482
 483         memset(bp->flow_stat->tx_fc_out_tbl.va,
 484                0,
 485                bp->flow_stat->tx_fc_out_tbl.size);
 486         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 487                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 488                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 489                                        bp->flow_stat->max_fc,
 490                                        true);
 491
 492         return rc;
 493 }
 494
 495 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 496                                   struct bnxt_ctx_mem_buf_info *ctx)
 497 {
 498         if (!ctx)
 499                 return -EINVAL;
 500
 501         ctx->va = rte_zmalloc(type, size, 0);
 502         if (ctx->va == NULL)
 503                 return -ENOMEM;
 504         rte_mem_lock_page(ctx->va);
 505         ctx->size = size;
 506         ctx->dma = rte_mem_virt2iova(ctx->va);
 507         if (ctx->dma == RTE_BAD_IOVA)
 508                 return -ENOMEM;
 509
 510         return 0;
 511 }
 512
 513 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 514 {
 515         struct rte_pci_device *pdev = bp->pdev;
 516         char type[RTE_MEMZONE_NAMESIZE];
 517         uint16_t max_fc;
 518         int rc = 0;
 519
 520         max_fc = bp->flow_stat->max_fc;
 521
 522         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 523                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 524         /* 4 bytes for each counter-id */
 525         rc = bnxt_alloc_ctx_mem_buf(type,
 526                                     max_fc * 4,
 527                                     &bp->flow_stat->rx_fc_in_tbl);
 528         if (rc)
 529                 return rc;
 530
 531         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 532                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 533         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 534         rc = bnxt_alloc_ctx_mem_buf(type,
 535                                     max_fc * 16,
 536                                     &bp->flow_stat->rx_fc_out_tbl);
 537         if (rc)
 538                 return rc;
 539
 540         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 541                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 542         /* 4 bytes for each counter-id */
 543         rc = bnxt_alloc_ctx_mem_buf(type,
 544                                     max_fc * 4,
 545                                     &bp->flow_stat->tx_fc_in_tbl);
 546         if (rc)
 547                 return rc;
 548
 549         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 550                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 551         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 552         rc = bnxt_alloc_ctx_mem_buf(type,
 553                                     max_fc * 16,
 554                                     &bp->flow_stat->tx_fc_out_tbl);
 555         if (rc)
 556                 return rc;
 557
 558         rc = bnxt_register_fc_ctx_mem(bp);
 559
 560         return rc;
 561 }
 562
 563 static int bnxt_init_ctx_mem(struct bnxt *bp)
 564 {
 565         int rc = 0;
 566
 567         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 568             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 569             !BNXT_FLOW_XSTATS_EN(bp))
 570                 return 0;
 571
 572         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 573         if (rc)
 574                 return rc;
 575
 576         rc = bnxt_init_fc_ctx_mem(bp);
 577
 578         return rc;
 579 }
 580
 581 static int bnxt_init_chip(struct bnxt *bp)
 582 {
 583         struct rte_eth_link new;
 584         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 585         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 586         uint32_t intr_vector = 0;
 587         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 588         uint32_t vec = BNXT_MISC_VEC_ID;
 589         unsigned int i, j;
 590         int rc;
 591
 592         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 593                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 594                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 595                 bp->flags |= BNXT_FLAG_JUMBO;
 596         } else {
 597                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 598                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 599                 bp->flags &= ~BNXT_FLAG_JUMBO;
 600         }
 601
 602         /* THOR does not support ring groups.
 603          * But we will use the array to save RSS context IDs.
 604          */
 605         if (BNXT_CHIP_THOR(bp))
 606                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 607
 608         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 609         if (rc) {
 610                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 611                 goto err_out;
 612         }
 613
 614         rc = bnxt_alloc_hwrm_rings(bp);
 615         if (rc) {
 616                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 617                 goto err_out;
 618         }
 619
 620         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 621         if (rc) {
 622                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 623                 goto err_out;
 624         }
 625
 626         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 627                 goto skip_cosq_cfg;
 628
 629         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 630                 if (bp->rx_cos_queue[i].id != 0xff) {
 631                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 632
 633                         if (!vnic) {
 634                                 PMD_DRV_LOG(ERR,
 635                                             "Num pools more than FW profile\n");
 636                                 rc = -EINVAL;
 637                                 goto err_out;
 638                         }
 639                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 640                         bp->rx_cosq_cnt++;
 641                 }
 642         }
 643
 644 skip_cosq_cfg:
 645         rc = bnxt_mq_rx_configure(bp);
 646         if (rc) {
 647                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 648                 goto err_out;
 649         }
 650
 651         /* VNIC configuration */
 652         for (i = 0; i < bp->nr_vnics; i++) {
 653                 rc = bnxt_setup_one_vnic(bp, i);
 654                 if (rc)
 655                         goto err_out;
 656         }
 657
 658         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 659         if (rc) {
 660                 PMD_DRV_LOG(ERR,
 661                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 662                 goto err_out;
 663         }
 664
 665         /* check and configure queue intr-vector mapping */
 666         if ((rte_intr_cap_multiple(intr_handle) ||
 667              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 668             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 669                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 670                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 671                 if (intr_vector > bp->rx_cp_nr_rings) {
 672                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 673                                         bp->rx_cp_nr_rings);
 674                         return -ENOTSUP;
 675                 }
 676                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 677                 if (rc)
 678                         return rc;
 679         }
 680
 681         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 682                 intr_handle->intr_vec =
 683                         rte_zmalloc("intr_vec",
 684                                     bp->eth_dev->data->nb_rx_queues *
 685                                     sizeof(int), 0);
 686                 if (intr_handle->intr_vec == NULL) {
 687                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 688                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 689                         rc = -ENOMEM;
 690                         goto err_disable;
 691                 }
 692                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 693                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 694                          intr_handle->intr_vec, intr_handle->nb_efd,
 695                         intr_handle->max_intr);
 696                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 697                      queue_id++) {
 698                         intr_handle->intr_vec[queue_id] =
 699                                                         vec + BNXT_RX_VEC_START;
 700                         if (vec < base + intr_handle->nb_efd - 1)
 701                                 vec++;
 702                 }
 703         }
 704
 705         /* enable uio/vfio intr/eventfd mapping */
 706         rc = rte_intr_enable(intr_handle);
 707 #ifndef RTE_EXEC_ENV_FREEBSD
 708         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 709         if (rc)
 710                 goto err_free;
 711 #endif
 712
 713         rc = bnxt_get_hwrm_link_config(bp, &new);
 714         if (rc) {
 715                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 716                 goto err_free;
 717         }
 718
 719         if (!bp->link_info->link_up) {
 720                 rc = bnxt_set_hwrm_link_config(bp, true);
 721                 if (rc) {
 722                         PMD_DRV_LOG(ERR,
 723                                 "HWRM link config failure rc: %x\n", rc);
 724                         goto err_free;
 725                 }
 726         }
 727         bnxt_print_link_info(bp->eth_dev);
 728
 729         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 730         if (!bp->mark_table)
 731                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 732
 733         return 0;
 734
 735 err_free:
 736         rte_free(intr_handle->intr_vec);
 737 err_disable:
 738         rte_intr_efd_disable(intr_handle);
 739 err_out:
 740         /* Some of the error status returned by FW may not be from errno.h */
 741         if (rc > 0)
 742                 rc = -EIO;
 743
 744         return rc;
 745 }
 746
 747 static int bnxt_shutdown_nic(struct bnxt *bp)
 748 {
 749         bnxt_free_all_hwrm_resources(bp);
 750         bnxt_free_all_filters(bp);
 751         bnxt_free_all_vnics(bp);
 752         return 0;
 753 }
 754
 755 /*
 756  * Device configuration and status function
 757  */
 758
 759 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 760 {
 761         uint32_t link_speed = bp->link_info->support_speeds;
 762         uint32_t speed_capa = 0;
 763
 764         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 765                 speed_capa |= ETH_LINK_SPEED_100M;
 766         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 767                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 768         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 769                 speed_capa |= ETH_LINK_SPEED_1G;
 770         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 771                 speed_capa |= ETH_LINK_SPEED_2_5G;
 772         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 773                 speed_capa |= ETH_LINK_SPEED_10G;
 774         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 775                 speed_capa |= ETH_LINK_SPEED_20G;
 776         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 777                 speed_capa |= ETH_LINK_SPEED_25G;
 778         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 779                 speed_capa |= ETH_LINK_SPEED_40G;
 780         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 781                 speed_capa |= ETH_LINK_SPEED_50G;
 782         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 783                 speed_capa |= ETH_LINK_SPEED_100G;
 784         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
 785                 speed_capa |= ETH_LINK_SPEED_200G;
 786
 787         if (bp->link_info->auto_mode ==
 788             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 789                 speed_capa |= ETH_LINK_SPEED_FIXED;
 790         else
 791                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 792
 793         return speed_capa;
 794 }
 795
 796 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 797                                 struct rte_eth_dev_info *dev_info)
 798 {
 799         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 800         struct bnxt *bp = eth_dev->data->dev_private;
 801         uint16_t max_vnics, i, j, vpool, vrxq;
 802         unsigned int max_rx_rings;
 803         int rc;
 804
 805         rc = is_bnxt_in_error(bp);
 806         if (rc)
 807                 return rc;
 808
 809         /* MAC Specifics */
 810         dev_info->max_mac_addrs = bp->max_l2_ctx;
 811         dev_info->max_hash_mac_addrs = 0;
 812
 813         /* PF/VF specifics */
 814         if (BNXT_PF(bp))
 815                 dev_info->max_vfs = pdev->max_vfs;
 816
 817         max_rx_rings = BNXT_MAX_RINGS(bp);
 818         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 819         dev_info->max_rx_queues = max_rx_rings;
 820         dev_info->max_tx_queues = max_rx_rings;
 821         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 822         dev_info->hash_key_size = 40;
 823         max_vnics = bp->max_vnics;
 824
 825         /* MTU specifics */
 826         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 827         dev_info->max_mtu = BNXT_MAX_MTU;
 828
 829         /* Fast path specifics */
 830         dev_info->min_rx_bufsize = 1;
 831         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 832
 833         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 834         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 835                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 836         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 837         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 838
 839         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 840
 841         /* *INDENT-OFF* */
 842         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 843                 .rx_thresh = {
 844                         .pthresh = 8,
 845                         .hthresh = 8,
 846                         .wthresh = 0,
 847                 },
 848                 .rx_free_thresh = 32,
 849                 /* If no descriptors available, pkts are dropped by default */
 850                 .rx_drop_en = 1,
 851         };
 852
 853         dev_info->default_txconf = (struct rte_eth_txconf) {
 854                 .tx_thresh = {
 855                         .pthresh = 32,
 856                         .hthresh = 0,
 857                         .wthresh = 0,
 858                 },
 859                 .tx_free_thresh = 32,
 860                 .tx_rs_thresh = 32,
 861         };
 862         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 863
 864         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 865         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 866         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 867         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 868         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 869
 870         /* *INDENT-ON* */
 871
 872         /*
 873          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 874          *       need further investigation.
 875          */
 876
 877         /* VMDq resources */
 878         vpool = 64; /* ETH_64_POOLS */
 879         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 880         for (i = 0; i < 4; vpool >>= 1, i++) {
 881                 if (max_vnics > vpool) {
 882                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 883                                 if (dev_info->max_rx_queues > vrxq) {
 884                                         if (vpool > vrxq)
 885                                                 vpool = vrxq;
 886                                         goto found;
 887                                 }
 888                         }
 889                         /* Not enough resources to support VMDq */
 890                         break;
 891                 }
 892         }
 893         /* Not enough resources to support VMDq */
 894         vpool = 0;
 895         vrxq = 0;
 896 found:
 897         dev_info->max_vmdq_pools = vpool;
 898         dev_info->vmdq_queue_num = vrxq;
 899
 900         dev_info->vmdq_pool_base = 0;
 901         dev_info->vmdq_queue_base = 0;
 902
 903         return 0;
 904 }
 905
 906 /* Configure the device based on the configuration provided */
 907 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 908 {
 909         struct bnxt *bp = eth_dev->data->dev_private;
 910         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 911         int rc;
 912
 913         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 914         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 915         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 916         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 917
 918         rc = is_bnxt_in_error(bp);
 919         if (rc)
 920                 return rc;
 921
 922         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 923                 rc = bnxt_hwrm_check_vf_rings(bp);
 924                 if (rc) {
 925                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 926                         return -ENOSPC;
 927                 }
 928
 929                 /* If a resource has already been allocated - in this case
 930                  * it is the async completion ring, free it. Reallocate it after
 931                  * resource reservation. This will ensure the resource counts
 932                  * are calculated correctly.
 933                  */
 934
 935                 pthread_mutex_lock(&bp->def_cp_lock);
 936
 937                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 938                         bnxt_disable_int(bp);
 939                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 940                 }
 941
 942                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 943                 if (rc) {
 944                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 945                         pthread_mutex_unlock(&bp->def_cp_lock);
 946                         return -ENOSPC;
 947                 }
 948
 949                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 950                         rc = bnxt_alloc_async_cp_ring(bp);
 951                         if (rc) {
 952                                 pthread_mutex_unlock(&bp->def_cp_lock);
 953                                 return rc;
 954                         }
 955                         bnxt_enable_int(bp);
 956                 }
 957
 958                 pthread_mutex_unlock(&bp->def_cp_lock);
 959         } else {
 960                 /* legacy driver needs to get updated values */
 961                 rc = bnxt_hwrm_func_qcaps(bp);
 962                 if (rc) {
 963                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 964                         return rc;
 965                 }
 966         }
 967
 968         /* Inherit new configurations */
 969         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 970             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 971             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 972                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 973             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 974             bp->max_stat_ctx)
 975                 goto resource_error;
 976
 977         if (BNXT_HAS_RING_GRPS(bp) &&
 978             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 979                 goto resource_error;
 980
 981         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 982             bp->max_vnics < eth_dev->data->nb_rx_queues)
 983                 goto resource_error;
 984
 985         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 986         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 987
 988         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 989                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 990         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
 991
 992         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 993                 eth_dev->data->mtu =
 994                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 995                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 996                         BNXT_NUM_VLANS;
 997                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 998         }
 999         return 0;
1000
1001 resource_error:
1002         PMD_DRV_LOG(ERR,
1003                     "Insufficient resources to support requested config\n");
1004         PMD_DRV_LOG(ERR,
1005                     "Num Queues Requested: Tx %d, Rx %d\n",
1006                     eth_dev->data->nb_tx_queues,
1007                     eth_dev->data->nb_rx_queues);
1008         PMD_DRV_LOG(ERR,
1009                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1010                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1011                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1012         return -ENOSPC;
1013 }
1014
1015 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1016 {
1017         struct rte_eth_link *link = &eth_dev->data->dev_link;
1018
1019         if (link->link_status)
1020                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1021                         eth_dev->data->port_id,
1022                         (uint32_t)link->link_speed,
1023                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1024                         ("full-duplex") : ("half-duplex\n"));
1025         else
1026                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1027                         eth_dev->data->port_id);
1028 }
1029
1030 /*
1031  * Determine whether the current configuration requires support for scattered
1032  * receive; return 1 if scattered receive is required and 0 if not.
1033  */
1034 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1035 {
1036         uint16_t buf_size;
1037         int i;
1038
1039         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1040                 return 1;
1041
1042         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1043                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1044
1045                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1046                                       RTE_PKTMBUF_HEADROOM);
1047                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1048                         return 1;
1049         }
1050         return 0;
1051 }
1052
1053 static eth_rx_burst_t
1054 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1055 {
1056         struct bnxt *bp = eth_dev->data->dev_private;
1057
1058 #ifdef RTE_ARCH_X86
1059 #ifndef RTE_LIBRTE_IEEE1588
1060         /*
1061          * Vector mode receive can be enabled only if scatter rx is not
1062          * in use and rx offloads are limited to VLAN stripping and
1063          * CRC stripping.
1064          */
1065         if (!eth_dev->data->scattered_rx &&
1066             !(eth_dev->data->dev_conf.rxmode.offloads &
1067               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1068                 DEV_RX_OFFLOAD_KEEP_CRC |
1069                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1070                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1071                 DEV_RX_OFFLOAD_UDP_CKSUM |
1072                 DEV_RX_OFFLOAD_TCP_CKSUM |
1073                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1074                 DEV_RX_OFFLOAD_RSS_HASH |
1075                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1076             !BNXT_TRUFLOW_EN(bp)) {
1077                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1078                             eth_dev->data->port_id);
1079                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1080                 return bnxt_recv_pkts_vec;
1081         }
1082         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1083                     eth_dev->data->port_id);
1084         PMD_DRV_LOG(INFO,
1085                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1086                     eth_dev->data->port_id,
1087                     eth_dev->data->scattered_rx,
1088                     eth_dev->data->dev_conf.rxmode.offloads);
1089 #endif
1090 #endif
1091         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1092         return bnxt_recv_pkts;
1093 }
1094
1095 static eth_tx_burst_t
1096 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1097 {
1098 #ifdef RTE_ARCH_X86
1099 #ifndef RTE_LIBRTE_IEEE1588
1100         /*
1101          * Vector mode transmit can be enabled only if not using scatter rx
1102          * or tx offloads.
1103          */
1104         if (!eth_dev->data->scattered_rx &&
1105             !eth_dev->data->dev_conf.txmode.offloads) {
1106                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1107                             eth_dev->data->port_id);
1108                 return bnxt_xmit_pkts_vec;
1109         }
1110         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1111                     eth_dev->data->port_id);
1112         PMD_DRV_LOG(INFO,
1113                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1114                     eth_dev->data->port_id,
1115                     eth_dev->data->scattered_rx,
1116                     eth_dev->data->dev_conf.txmode.offloads);
1117 #endif
1118 #endif
1119         return bnxt_xmit_pkts;
1120 }
1121
1122 static int bnxt_handle_if_change_status(struct bnxt *bp)
1123 {
1124         int rc;
1125
1126         /* Since fw has undergone a reset and lost all contexts,
1127          * set fatal flag to not issue hwrm during cleanup
1128          */
1129         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1130         bnxt_uninit_resources(bp, true);
1131
1132         /* clear fatal flag so that re-init happens */
1133         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1134         rc = bnxt_init_resources(bp, true);
1135
1136         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1137
1138         return rc;
1139 }
1140
1141 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1142 {
1143         struct bnxt *bp = eth_dev->data->dev_private;
1144         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1145         int vlan_mask = 0;
1146         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1147
1148         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1149                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1150                 return -EINVAL;
1151         }
1152
1153         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1154                 PMD_DRV_LOG(ERR,
1155                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1156                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1157         }
1158
1159         do {
1160                 rc = bnxt_hwrm_if_change(bp, true);
1161                 if (rc == 0 || rc != -EAGAIN)
1162                         break;
1163
1164                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1165         } while (retry_cnt--);
1166
1167         if (rc)
1168                 return rc;
1169
1170         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1171                 rc = bnxt_handle_if_change_status(bp);
1172                 if (rc)
1173                         return rc;
1174         }
1175
1176         bnxt_enable_int(bp);
1177
1178         rc = bnxt_init_chip(bp);
1179         if (rc)
1180                 goto error;
1181
1182         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1183         eth_dev->data->dev_started = 1;
1184
1185         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1186
1187         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1188                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1189         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1190                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1191         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1192         if (rc)
1193                 goto error;
1194
1195         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1196         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1197
1198         pthread_mutex_lock(&bp->def_cp_lock);
1199         bnxt_schedule_fw_health_check(bp);
1200         pthread_mutex_unlock(&bp->def_cp_lock);
1201
1202         if (BNXT_TRUFLOW_EN(bp))
1203                 bnxt_ulp_init(bp);
1204
1205         return 0;
1206
1207 error:
1208         bnxt_shutdown_nic(bp);
1209         bnxt_free_tx_mbufs(bp);
1210         bnxt_free_rx_mbufs(bp);
1211         bnxt_hwrm_if_change(bp, false);
1212         eth_dev->data->dev_started = 0;
1213         return rc;
1214 }
1215
1216 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1217 {
1218         struct bnxt *bp = eth_dev->data->dev_private;
1219         int rc = 0;
1220
1221         if (!bp->link_info->link_up)
1222                 rc = bnxt_set_hwrm_link_config(bp, true);
1223         if (!rc)
1224                 eth_dev->data->dev_link.link_status = 1;
1225
1226         bnxt_print_link_info(eth_dev);
1227         return rc;
1228 }
1229
1230 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1231 {
1232         struct bnxt *bp = eth_dev->data->dev_private;
1233
1234         eth_dev->data->dev_link.link_status = 0;
1235         bnxt_set_hwrm_link_config(bp, false);
1236         bp->link_info->link_up = 0;
1237
1238         return 0;
1239 }
1240
1241 static void bnxt_free_switch_domain(struct bnxt *bp)
1242 {
1243         if (bp->switch_domain_id)
1244                 rte_eth_switch_domain_free(bp->switch_domain_id);
1245 }
1246
1247 /* Unload the driver, release resources */
1248 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1249 {
1250         struct bnxt *bp = eth_dev->data->dev_private;
1251         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1252         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1253
1254         if (BNXT_TRUFLOW_EN(bp))
1255                 bnxt_ulp_deinit(bp);
1256
1257         eth_dev->data->dev_started = 0;
1258         /* Prevent crashes when queues are still in use */
1259         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1260         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1261
1262         bnxt_disable_int(bp);
1263
1264         /* disable uio/vfio intr/eventfd mapping */
1265         rte_intr_disable(intr_handle);
1266
1267         bnxt_cancel_fw_health_check(bp);
1268
1269         bnxt_dev_set_link_down_op(eth_dev);
1270
1271         /* Wait for link to be reset and the async notification to process.
1272          * During reset recovery, there is no need to wait and
1273          * VF/NPAR functions do not have privilege to change PHY config.
1274          */
1275         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1276                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1277
1278         /* Clean queue intr-vector mapping */
1279         rte_intr_efd_disable(intr_handle);
1280         if (intr_handle->intr_vec != NULL) {
1281                 rte_free(intr_handle->intr_vec);
1282                 intr_handle->intr_vec = NULL;
1283         }
1284
1285         bnxt_hwrm_port_clr_stats(bp);
1286         bnxt_free_tx_mbufs(bp);
1287         bnxt_free_rx_mbufs(bp);
1288         /* Process any remaining notifications in default completion queue */
1289         bnxt_int_handler(eth_dev);
1290         bnxt_shutdown_nic(bp);
1291         bnxt_hwrm_if_change(bp, false);
1292
1293         rte_free(bp->mark_table);
1294         bp->mark_table = NULL;
1295
1296         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1297         bp->rx_cosq_cnt = 0;
1298         /* All filters are deleted on a port stop. */
1299         if (BNXT_FLOW_XSTATS_EN(bp))
1300                 bp->flow_stat->flow_count = 0;
1301 }
1302
1303 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1304 {
1305         struct bnxt *bp = eth_dev->data->dev_private;
1306
1307         /* cancel the recovery handler before remove dev */
1308         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1309         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1310         bnxt_cancel_fc_thread(bp);
1311
1312         if (eth_dev->data->dev_started)
1313                 bnxt_dev_stop_op(eth_dev);
1314
1315         bnxt_free_switch_domain(bp);
1316
1317         bnxt_uninit_resources(bp, false);
1318
1319         bnxt_free_leds_info(bp);
1320         bnxt_free_cos_queues(bp);
1321         bnxt_free_link_info(bp);
1322         bnxt_free_pf_info(bp);
1323
1324         eth_dev->dev_ops = NULL;
1325         eth_dev->rx_pkt_burst = NULL;
1326         eth_dev->tx_pkt_burst = NULL;
1327
1328         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1329         bp->tx_mem_zone = NULL;
1330         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1331         bp->rx_mem_zone = NULL;
1332
1333         rte_free(bp->pf->vf_info);
1334         bp->pf->vf_info = NULL;
1335
1336         rte_free(bp->grp_info);
1337         bp->grp_info = NULL;
1338 }
1339
1340 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1341                                     uint32_t index)
1342 {
1343         struct bnxt *bp = eth_dev->data->dev_private;
1344         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1345         struct bnxt_vnic_info *vnic;
1346         struct bnxt_filter_info *filter, *temp_filter;
1347         uint32_t i;
1348
1349         if (is_bnxt_in_error(bp))
1350                 return;
1351
1352         /*
1353          * Loop through all VNICs from the specified filter flow pools to
1354          * remove the corresponding MAC addr filter
1355          */
1356         for (i = 0; i < bp->nr_vnics; i++) {
1357                 if (!(pool_mask & (1ULL << i)))
1358                         continue;
1359
1360                 vnic = &bp->vnic_info[i];
1361                 filter = STAILQ_FIRST(&vnic->filter);
1362                 while (filter) {
1363                         temp_filter = STAILQ_NEXT(filter, next);
1364                         if (filter->mac_index == index) {
1365                                 STAILQ_REMOVE(&vnic->filter, filter,
1366                                                 bnxt_filter_info, next);
1367                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1368                                 bnxt_free_filter(bp, filter);
1369                         }
1370                         filter = temp_filter;
1371                 }
1372         }
1373 }
1374
1375 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1376                                struct rte_ether_addr *mac_addr, uint32_t index,
1377                                uint32_t pool)
1378 {
1379         struct bnxt_filter_info *filter;
1380         int rc = 0;
1381
1382         /* Attach requested MAC address to the new l2_filter */
1383         STAILQ_FOREACH(filter, &vnic->filter, next) {
1384                 if (filter->mac_index == index) {
1385                         PMD_DRV_LOG(DEBUG,
1386                                     "MAC addr already existed for pool %d\n",
1387                                     pool);
1388                         return 0;
1389                 }
1390         }
1391
1392         filter = bnxt_alloc_filter(bp);
1393         if (!filter) {
1394                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1395                 return -ENODEV;
1396         }
1397
1398         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1399          * if the MAC that's been programmed now is a different one, then,
1400          * copy that addr to filter->l2_addr
1401          */
1402         if (mac_addr)
1403                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1404         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1405
1406         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1407         if (!rc) {
1408                 filter->mac_index = index;
1409                 if (filter->mac_index == 0)
1410                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1411                 else
1412                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1413         } else {
1414                 bnxt_free_filter(bp, filter);
1415         }
1416
1417         return rc;
1418 }
1419
1420 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1421                                 struct rte_ether_addr *mac_addr,
1422                                 uint32_t index, uint32_t pool)
1423 {
1424         struct bnxt *bp = eth_dev->data->dev_private;
1425         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1426         int rc = 0;
1427
1428         rc = is_bnxt_in_error(bp);
1429         if (rc)
1430                 return rc;
1431
1432         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1433                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1434                 return -ENOTSUP;
1435         }
1436
1437         if (!vnic) {
1438                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1439                 return -EINVAL;
1440         }
1441
1442         /* Filter settings will get applied when port is started */
1443         if (!eth_dev->data->dev_started)
1444                 return 0;
1445
1446         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1447
1448         return rc;
1449 }
1450
1451 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1452                      bool exp_link_status)
1453 {
1454         int rc = 0;
1455         struct bnxt *bp = eth_dev->data->dev_private;
1456         struct rte_eth_link new;
1457         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1458                   BNXT_LINK_DOWN_WAIT_CNT;
1459
1460         rc = is_bnxt_in_error(bp);
1461         if (rc)
1462                 return rc;
1463
1464         memset(&new, 0, sizeof(new));
1465         do {
1466                 /* Retrieve link info from hardware */
1467                 rc = bnxt_get_hwrm_link_config(bp, &new);
1468                 if (rc) {
1469                         new.link_speed = ETH_LINK_SPEED_100M;
1470                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1471                         PMD_DRV_LOG(ERR,
1472                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1473                         goto out;
1474                 }
1475
1476                 if (!wait_to_complete || new.link_status == exp_link_status)
1477                         break;
1478
1479                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1480         } while (cnt--);
1481
1482 out:
1483         /* Timed out or success */
1484         if (new.link_status != eth_dev->data->dev_link.link_status ||
1485         new.link_speed != eth_dev->data->dev_link.link_speed) {
1486                 rte_eth_linkstatus_set(eth_dev, &new);
1487
1488                 _rte_eth_dev_callback_process(eth_dev,
1489                                               RTE_ETH_EVENT_INTR_LSC,
1490                                               NULL);
1491
1492                 bnxt_print_link_info(eth_dev);
1493         }
1494
1495         return rc;
1496 }
1497
1498 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1499                         int wait_to_complete)
1500 {
1501         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1502 }
1503
1504 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1505 {
1506         struct bnxt *bp = eth_dev->data->dev_private;
1507         struct bnxt_vnic_info *vnic;
1508         uint32_t old_flags;
1509         int rc;
1510
1511         rc = is_bnxt_in_error(bp);
1512         if (rc)
1513                 return rc;
1514
1515         /* Filter settings will get applied when port is started */
1516         if (!eth_dev->data->dev_started)
1517                 return 0;
1518
1519         if (bp->vnic_info == NULL)
1520                 return 0;
1521
1522         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1523
1524         old_flags = vnic->flags;
1525         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1526         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1527         if (rc != 0)
1528                 vnic->flags = old_flags;
1529
1530         return rc;
1531 }
1532
1533 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1534 {
1535         struct bnxt *bp = eth_dev->data->dev_private;
1536         struct bnxt_vnic_info *vnic;
1537         uint32_t old_flags;
1538         int rc;
1539
1540         rc = is_bnxt_in_error(bp);
1541         if (rc)
1542                 return rc;
1543
1544         /* Filter settings will get applied when port is started */
1545         if (!eth_dev->data->dev_started)
1546                 return 0;
1547
1548         if (bp->vnic_info == NULL)
1549                 return 0;
1550
1551         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1552
1553         old_flags = vnic->flags;
1554         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1555         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1556         if (rc != 0)
1557                 vnic->flags = old_flags;
1558
1559         return rc;
1560 }
1561
1562 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1563 {
1564         struct bnxt *bp = eth_dev->data->dev_private;
1565         struct bnxt_vnic_info *vnic;
1566         uint32_t old_flags;
1567         int rc;
1568
1569         rc = is_bnxt_in_error(bp);
1570         if (rc)
1571                 return rc;
1572
1573         /* Filter settings will get applied when port is started */
1574         if (!eth_dev->data->dev_started)
1575                 return 0;
1576
1577         if (bp->vnic_info == NULL)
1578                 return 0;
1579
1580         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1581
1582         old_flags = vnic->flags;
1583         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1584         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1585         if (rc != 0)
1586                 vnic->flags = old_flags;
1587
1588         return rc;
1589 }
1590
1591 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1592 {
1593         struct bnxt *bp = eth_dev->data->dev_private;
1594         struct bnxt_vnic_info *vnic;
1595         uint32_t old_flags;
1596         int rc;
1597
1598         rc = is_bnxt_in_error(bp);
1599         if (rc)
1600                 return rc;
1601
1602         /* Filter settings will get applied when port is started */
1603         if (!eth_dev->data->dev_started)
1604                 return 0;
1605
1606         if (bp->vnic_info == NULL)
1607                 return 0;
1608
1609         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1610
1611         old_flags = vnic->flags;
1612         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1613         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1614         if (rc != 0)
1615                 vnic->flags = old_flags;
1616
1617         return rc;
1618 }
1619
1620 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1621 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1622 {
1623         if (qid >= bp->rx_nr_rings)
1624                 return NULL;
1625
1626         return bp->eth_dev->data->rx_queues[qid];
1627 }
1628
1629 /* Return rxq corresponding to a given rss table ring/group ID. */
1630 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1631 {
1632         struct bnxt_rx_queue *rxq;
1633         unsigned int i;
1634
1635         if (!BNXT_HAS_RING_GRPS(bp)) {
1636                 for (i = 0; i < bp->rx_nr_rings; i++) {
1637                         rxq = bp->eth_dev->data->rx_queues[i];
1638                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1639                                 return rxq->index;
1640                 }
1641         } else {
1642                 for (i = 0; i < bp->rx_nr_rings; i++) {
1643                         if (bp->grp_info[i].fw_grp_id == fwr)
1644                                 return i;
1645                 }
1646         }
1647
1648         return INVALID_HW_RING_ID;
1649 }
1650
1651 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1652                             struct rte_eth_rss_reta_entry64 *reta_conf,
1653                             uint16_t reta_size)
1654 {
1655         struct bnxt *bp = eth_dev->data->dev_private;
1656         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1657         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1658         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1659         uint16_t idx, sft;
1660         int i, rc;
1661
1662         rc = is_bnxt_in_error(bp);
1663         if (rc)
1664                 return rc;
1665
1666         if (!vnic->rss_table)
1667                 return -EINVAL;
1668
1669         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1670                 return -EINVAL;
1671
1672         if (reta_size != tbl_size) {
1673                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1674                         "(%d) must equal the size supported by the hardware "
1675                         "(%d)\n", reta_size, tbl_size);
1676                 return -EINVAL;
1677         }
1678
1679         for (i = 0; i < reta_size; i++) {
1680                 struct bnxt_rx_queue *rxq;
1681
1682                 idx = i / RTE_RETA_GROUP_SIZE;
1683                 sft = i % RTE_RETA_GROUP_SIZE;
1684
1685                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1686                         continue;
1687
1688                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1689                 if (!rxq) {
1690                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1691                         return -EINVAL;
1692                 }
1693
1694                 if (BNXT_CHIP_THOR(bp)) {
1695                         vnic->rss_table[i * 2] =
1696                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1697                         vnic->rss_table[i * 2 + 1] =
1698                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1699                 } else {
1700                         vnic->rss_table[i] =
1701                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1702                 }
1703         }
1704
1705         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1706         return 0;
1707 }
1708
1709 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1710                               struct rte_eth_rss_reta_entry64 *reta_conf,
1711                               uint16_t reta_size)
1712 {
1713         struct bnxt *bp = eth_dev->data->dev_private;
1714         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1715         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1716         uint16_t idx, sft, i;
1717         int rc;
1718
1719         rc = is_bnxt_in_error(bp);
1720         if (rc)
1721                 return rc;
1722
1723         /* Retrieve from the default VNIC */
1724         if (!vnic)
1725                 return -EINVAL;
1726         if (!vnic->rss_table)
1727                 return -EINVAL;
1728
1729         if (reta_size != tbl_size) {
1730                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1731                         "(%d) must equal the size supported by the hardware "
1732                         "(%d)\n", reta_size, tbl_size);
1733                 return -EINVAL;
1734         }
1735
1736         for (idx = 0, i = 0; i < reta_size; i++) {
1737                 idx = i / RTE_RETA_GROUP_SIZE;
1738                 sft = i % RTE_RETA_GROUP_SIZE;
1739
1740                 if (reta_conf[idx].mask & (1ULL << sft)) {
1741                         uint16_t qid;
1742
1743                         if (BNXT_CHIP_THOR(bp))
1744                                 qid = bnxt_rss_to_qid(bp,
1745                                                       vnic->rss_table[i * 2]);
1746                         else
1747                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1748
1749                         if (qid == INVALID_HW_RING_ID) {
1750                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1751                                 return -EINVAL;
1752                         }
1753                         reta_conf[idx].reta[sft] = qid;
1754                 }
1755         }
1756
1757         return 0;
1758 }
1759
1760 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1761                                    struct rte_eth_rss_conf *rss_conf)
1762 {
1763         struct bnxt *bp = eth_dev->data->dev_private;
1764         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1765         struct bnxt_vnic_info *vnic;
1766         int rc;
1767
1768         rc = is_bnxt_in_error(bp);
1769         if (rc)
1770                 return rc;
1771
1772         /*
1773          * If RSS enablement were different than dev_configure,
1774          * then return -EINVAL
1775          */
1776         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1777                 if (!rss_conf->rss_hf)
1778                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1779         } else {
1780                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1781                         return -EINVAL;
1782         }
1783
1784         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1785         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1786                rss_conf,
1787                sizeof(*rss_conf));
1788
1789         /* Update the default RSS VNIC(s) */
1790         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1791         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1792
1793         /*
1794          * If hashkey is not specified, use the previously configured
1795          * hashkey
1796          */
1797         if (!rss_conf->rss_key)
1798                 goto rss_config;
1799
1800         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1801                 PMD_DRV_LOG(ERR,
1802                             "Invalid hashkey length, should be 16 bytes\n");
1803                 return -EINVAL;
1804         }
1805         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1806
1807 rss_config:
1808         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1809         return 0;
1810 }
1811
1812 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1813                                      struct rte_eth_rss_conf *rss_conf)
1814 {
1815         struct bnxt *bp = eth_dev->data->dev_private;
1816         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1817         int len, rc;
1818         uint32_t hash_types;
1819
1820         rc = is_bnxt_in_error(bp);
1821         if (rc)
1822                 return rc;
1823
1824         /* RSS configuration is the same for all VNICs */
1825         if (vnic && vnic->rss_hash_key) {
1826                 if (rss_conf->rss_key) {
1827                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1828                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1829                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1830                 }
1831
1832                 hash_types = vnic->hash_type;
1833                 rss_conf->rss_hf = 0;
1834                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1835                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1836                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1837                 }
1838                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1839                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1840                         hash_types &=
1841                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1842                 }
1843                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1844                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1845                         hash_types &=
1846                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1847                 }
1848                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1849                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1850                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1851                 }
1852                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1853                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1854                         hash_types &=
1855                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1856                 }
1857                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1858                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1859                         hash_types &=
1860                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1861                 }
1862                 if (hash_types) {
1863                         PMD_DRV_LOG(ERR,
1864                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1865                                 vnic->hash_type);
1866                         return -ENOTSUP;
1867                 }
1868         } else {
1869                 rss_conf->rss_hf = 0;
1870         }
1871         return 0;
1872 }
1873
1874 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1875                                struct rte_eth_fc_conf *fc_conf)
1876 {
1877         struct bnxt *bp = dev->data->dev_private;
1878         struct rte_eth_link link_info;
1879         int rc;
1880
1881         rc = is_bnxt_in_error(bp);
1882         if (rc)
1883                 return rc;
1884
1885         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1886         if (rc)
1887                 return rc;
1888
1889         memset(fc_conf, 0, sizeof(*fc_conf));
1890         if (bp->link_info->auto_pause)
1891                 fc_conf->autoneg = 1;
1892         switch (bp->link_info->pause) {
1893         case 0:
1894                 fc_conf->mode = RTE_FC_NONE;
1895                 break;
1896         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1897                 fc_conf->mode = RTE_FC_TX_PAUSE;
1898                 break;
1899         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1900                 fc_conf->mode = RTE_FC_RX_PAUSE;
1901                 break;
1902         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1903                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1904                 fc_conf->mode = RTE_FC_FULL;
1905                 break;
1906         }
1907         return 0;
1908 }
1909
1910 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1911                                struct rte_eth_fc_conf *fc_conf)
1912 {
1913         struct bnxt *bp = dev->data->dev_private;
1914         int rc;
1915
1916         rc = is_bnxt_in_error(bp);
1917         if (rc)
1918                 return rc;
1919
1920         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1921                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1922                 return -ENOTSUP;
1923         }
1924
1925         switch (fc_conf->mode) {
1926         case RTE_FC_NONE:
1927                 bp->link_info->auto_pause = 0;
1928                 bp->link_info->force_pause = 0;
1929                 break;
1930         case RTE_FC_RX_PAUSE:
1931                 if (fc_conf->autoneg) {
1932                         bp->link_info->auto_pause =
1933                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1934                         bp->link_info->force_pause = 0;
1935                 } else {
1936                         bp->link_info->auto_pause = 0;
1937                         bp->link_info->force_pause =
1938                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1939                 }
1940                 break;
1941         case RTE_FC_TX_PAUSE:
1942                 if (fc_conf->autoneg) {
1943                         bp->link_info->auto_pause =
1944                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1945                         bp->link_info->force_pause = 0;
1946                 } else {
1947                         bp->link_info->auto_pause = 0;
1948                         bp->link_info->force_pause =
1949                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1950                 }
1951                 break;
1952         case RTE_FC_FULL:
1953                 if (fc_conf->autoneg) {
1954                         bp->link_info->auto_pause =
1955                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1956                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1957                         bp->link_info->force_pause = 0;
1958                 } else {
1959                         bp->link_info->auto_pause = 0;
1960                         bp->link_info->force_pause =
1961                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1962                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1963                 }
1964                 break;
1965         }
1966         return bnxt_set_hwrm_link_config(bp, true);
1967 }
1968
1969 /* Add UDP tunneling port */
1970 static int
1971 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1972                          struct rte_eth_udp_tunnel *udp_tunnel)
1973 {
1974         struct bnxt *bp = eth_dev->data->dev_private;
1975         uint16_t tunnel_type = 0;
1976         int rc = 0;
1977
1978         rc = is_bnxt_in_error(bp);
1979         if (rc)
1980                 return rc;
1981
1982         switch (udp_tunnel->prot_type) {
1983         case RTE_TUNNEL_TYPE_VXLAN:
1984                 if (bp->vxlan_port_cnt) {
1985                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1986                                 udp_tunnel->udp_port);
1987                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1988                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1989                                 return -ENOSPC;
1990                         }
1991                         bp->vxlan_port_cnt++;
1992                         return 0;
1993                 }
1994                 tunnel_type =
1995                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1996                 bp->vxlan_port_cnt++;
1997                 break;
1998         case RTE_TUNNEL_TYPE_GENEVE:
1999                 if (bp->geneve_port_cnt) {
2000                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2001                                 udp_tunnel->udp_port);
2002                         if (bp->geneve_port != udp_tunnel->udp_port) {
2003                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2004                                 return -ENOSPC;
2005                         }
2006                         bp->geneve_port_cnt++;
2007                         return 0;
2008                 }
2009                 tunnel_type =
2010                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2011                 bp->geneve_port_cnt++;
2012                 break;
2013         default:
2014                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2015                 return -ENOTSUP;
2016         }
2017         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2018                                              tunnel_type);
2019         return rc;
2020 }
2021
2022 static int
2023 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2024                          struct rte_eth_udp_tunnel *udp_tunnel)
2025 {
2026         struct bnxt *bp = eth_dev->data->dev_private;
2027         uint16_t tunnel_type = 0;
2028         uint16_t port = 0;
2029         int rc = 0;
2030
2031         rc = is_bnxt_in_error(bp);
2032         if (rc)
2033                 return rc;
2034
2035         switch (udp_tunnel->prot_type) {
2036         case RTE_TUNNEL_TYPE_VXLAN:
2037                 if (!bp->vxlan_port_cnt) {
2038                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2039                         return -EINVAL;
2040                 }
2041                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2042                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2043                                 udp_tunnel->udp_port, bp->vxlan_port);
2044                         return -EINVAL;
2045                 }
2046                 if (--bp->vxlan_port_cnt)
2047                         return 0;
2048
2049                 tunnel_type =
2050                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2051                 port = bp->vxlan_fw_dst_port_id;
2052                 break;
2053         case RTE_TUNNEL_TYPE_GENEVE:
2054                 if (!bp->geneve_port_cnt) {
2055                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2056                         return -EINVAL;
2057                 }
2058                 if (bp->geneve_port != udp_tunnel->udp_port) {
2059                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2060                                 udp_tunnel->udp_port, bp->geneve_port);
2061                         return -EINVAL;
2062                 }
2063                 if (--bp->geneve_port_cnt)
2064                         return 0;
2065
2066                 tunnel_type =
2067                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2068                 port = bp->geneve_fw_dst_port_id;
2069                 break;
2070         default:
2071                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2072                 return -ENOTSUP;
2073         }
2074
2075         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2076         if (!rc) {
2077                 if (tunnel_type ==
2078                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2079                         bp->vxlan_port = 0;
2080                 if (tunnel_type ==
2081                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2082                         bp->geneve_port = 0;
2083         }
2084         return rc;
2085 }
2086
2087 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2088 {
2089         struct bnxt_filter_info *filter;
2090         struct bnxt_vnic_info *vnic;
2091         int rc = 0;
2092         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2093
2094         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2095         filter = STAILQ_FIRST(&vnic->filter);
2096         while (filter) {
2097                 /* Search for this matching MAC+VLAN filter */
2098                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2099                         /* Delete the filter */
2100                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2101                         if (rc)
2102                                 return rc;
2103                         STAILQ_REMOVE(&vnic->filter, filter,
2104                                       bnxt_filter_info, next);
2105                         bnxt_free_filter(bp, filter);
2106                         PMD_DRV_LOG(INFO,
2107                                     "Deleted vlan filter for %d\n",
2108                                     vlan_id);
2109                         return 0;
2110                 }
2111                 filter = STAILQ_NEXT(filter, next);
2112         }
2113         return -ENOENT;
2114 }
2115
2116 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2117 {
2118         struct bnxt_filter_info *filter;
2119         struct bnxt_vnic_info *vnic;
2120         int rc = 0;
2121         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2122                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2123         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2124
2125         /* Implementation notes on the use of VNIC in this command:
2126          *
2127          * By default, these filters belong to default vnic for the function.
2128          * Once these filters are set up, only destination VNIC can be modified.
2129          * If the destination VNIC is not specified in this command,
2130          * then the HWRM shall only create an l2 context id.
2131          */
2132
2133         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2134         filter = STAILQ_FIRST(&vnic->filter);
2135         /* Check if the VLAN has already been added */
2136         while (filter) {
2137                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2138                         return -EEXIST;
2139
2140                 filter = STAILQ_NEXT(filter, next);
2141         }
2142
2143         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2144          * command to create MAC+VLAN filter with the right flags, enables set.
2145          */
2146         filter = bnxt_alloc_filter(bp);
2147         if (!filter) {
2148                 PMD_DRV_LOG(ERR,
2149                             "MAC/VLAN filter alloc failed\n");
2150                 return -ENOMEM;
2151         }
2152         /* MAC + VLAN ID filter */
2153         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2154          * untagged packets are received
2155          *
2156          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2157          * packets and only the programmed vlan's packets are received
2158          */
2159         filter->l2_ivlan = vlan_id;
2160         filter->l2_ivlan_mask = 0x0FFF;
2161         filter->enables |= en;
2162         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2163
2164         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2165         if (rc) {
2166                 /* Free the newly allocated filter as we were
2167                  * not able to create the filter in hardware.
2168                  */
2169                 bnxt_free_filter(bp, filter);
2170                 return rc;
2171         }
2172
2173         filter->mac_index = 0;
2174         /* Add this new filter to the list */
2175         if (vlan_id == 0)
2176                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2177         else
2178                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2179
2180         PMD_DRV_LOG(INFO,
2181                     "Added Vlan filter for %d\n", vlan_id);
2182         return rc;
2183 }
2184
2185 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2186                 uint16_t vlan_id, int on)
2187 {
2188         struct bnxt *bp = eth_dev->data->dev_private;
2189         int rc;
2190
2191         rc = is_bnxt_in_error(bp);
2192         if (rc)
2193                 return rc;
2194
2195         if (!eth_dev->data->dev_started) {
2196                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2197                 return -EINVAL;
2198         }
2199
2200         /* These operations apply to ALL existing MAC/VLAN filters */
2201         if (on)
2202                 return bnxt_add_vlan_filter(bp, vlan_id);
2203         else
2204                 return bnxt_del_vlan_filter(bp, vlan_id);
2205 }
2206
2207 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2208                                     struct bnxt_vnic_info *vnic)
2209 {
2210         struct bnxt_filter_info *filter;
2211         int rc;
2212
2213         filter = STAILQ_FIRST(&vnic->filter);
2214         while (filter) {
2215                 if (filter->mac_index == 0 &&
2216                     !memcmp(filter->l2_addr, bp->mac_addr,
2217                             RTE_ETHER_ADDR_LEN)) {
2218                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2219                         if (!rc) {
2220                                 STAILQ_REMOVE(&vnic->filter, filter,
2221                                               bnxt_filter_info, next);
2222                                 bnxt_free_filter(bp, filter);
2223                         }
2224                         return rc;
2225                 }
2226                 filter = STAILQ_NEXT(filter, next);
2227         }
2228         return 0;
2229 }
2230
2231 static int
2232 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2233 {
2234         struct bnxt_vnic_info *vnic;
2235         unsigned int i;
2236         int rc;
2237
2238         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2239         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2240                 /* Remove any VLAN filters programmed */
2241                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2242                         bnxt_del_vlan_filter(bp, i);
2243
2244                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2245                 if (rc)
2246                         return rc;
2247         } else {
2248                 /* Default filter will allow packets that match the
2249                  * dest mac. So, it has to be deleted, otherwise, we
2250                  * will endup receiving vlan packets for which the
2251                  * filter is not programmed, when hw-vlan-filter
2252                  * configuration is ON
2253                  */
2254                 bnxt_del_dflt_mac_filter(bp, vnic);
2255                 /* This filter will allow only untagged packets */
2256                 bnxt_add_vlan_filter(bp, 0);
2257         }
2258         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2259                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2260
2261         return 0;
2262 }
2263
2264 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2265 {
2266         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2267         unsigned int i;
2268         int rc;
2269
2270         /* Destroy vnic filters and vnic */
2271         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2272             DEV_RX_OFFLOAD_VLAN_FILTER) {
2273                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2274                         bnxt_del_vlan_filter(bp, i);
2275         }
2276         bnxt_del_dflt_mac_filter(bp, vnic);
2277
2278         rc = bnxt_hwrm_vnic_free(bp, vnic);
2279         if (rc)
2280                 return rc;
2281
2282         rte_free(vnic->fw_grp_ids);
2283         vnic->fw_grp_ids = NULL;
2284
2285         vnic->rx_queue_cnt = 0;
2286
2287         return 0;
2288 }
2289
2290 static int
2291 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2292 {
2293         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2294         int rc;
2295
2296         /* Destroy, recreate and reconfigure the default vnic */
2297         rc = bnxt_free_one_vnic(bp, 0);
2298         if (rc)
2299                 return rc;
2300
2301         /* default vnic 0 */
2302         rc = bnxt_setup_one_vnic(bp, 0);
2303         if (rc)
2304                 return rc;
2305
2306         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2307             DEV_RX_OFFLOAD_VLAN_FILTER) {
2308                 rc = bnxt_add_vlan_filter(bp, 0);
2309                 if (rc)
2310                         return rc;
2311                 rc = bnxt_restore_vlan_filters(bp);
2312                 if (rc)
2313                         return rc;
2314         } else {
2315                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2316                 if (rc)
2317                         return rc;
2318         }
2319
2320         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2321         if (rc)
2322                 return rc;
2323
2324         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2325                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2326
2327         return rc;
2328 }
2329
2330 static int
2331 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2332 {
2333         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2334         struct bnxt *bp = dev->data->dev_private;
2335         int rc;
2336
2337         rc = is_bnxt_in_error(bp);
2338         if (rc)
2339                 return rc;
2340
2341         /* Filter settings will get applied when port is started */
2342         if (!dev->data->dev_started)
2343                 return 0;
2344
2345         if (mask & ETH_VLAN_FILTER_MASK) {
2346                 /* Enable or disable VLAN filtering */
2347                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2348                 if (rc)
2349                         return rc;
2350         }
2351
2352         if (mask & ETH_VLAN_STRIP_MASK) {
2353                 /* Enable or disable VLAN stripping */
2354                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2355                 if (rc)
2356                         return rc;
2357         }
2358
2359         if (mask & ETH_VLAN_EXTEND_MASK) {
2360                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2361                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2362                 else
2363                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2364         }
2365
2366         return 0;
2367 }
2368
2369 static int
2370 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2371                       uint16_t tpid)
2372 {
2373         struct bnxt *bp = dev->data->dev_private;
2374         int qinq = dev->data->dev_conf.rxmode.offloads &
2375                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2376
2377         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2378             vlan_type != ETH_VLAN_TYPE_OUTER) {
2379                 PMD_DRV_LOG(ERR,
2380                             "Unsupported vlan type.");
2381                 return -EINVAL;
2382         }
2383         if (!qinq) {
2384                 PMD_DRV_LOG(ERR,
2385                             "QinQ not enabled. Needs to be ON as we can "
2386                             "accelerate only outer vlan\n");
2387                 return -EINVAL;
2388         }
2389
2390         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2391                 switch (tpid) {
2392                 case RTE_ETHER_TYPE_QINQ:
2393                         bp->outer_tpid_bd =
2394                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2395                                 break;
2396                 case RTE_ETHER_TYPE_VLAN:
2397                         bp->outer_tpid_bd =
2398                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2399                                 break;
2400                 case 0x9100:
2401                         bp->outer_tpid_bd =
2402                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2403                                 break;
2404                 case 0x9200:
2405                         bp->outer_tpid_bd =
2406                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2407                                 break;
2408                 case 0x9300:
2409                         bp->outer_tpid_bd =
2410                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2411                                 break;
2412                 default:
2413                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2414                         return -EINVAL;
2415                 }
2416                 bp->outer_tpid_bd |= tpid;
2417                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2418         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2419                 PMD_DRV_LOG(ERR,
2420                             "Can accelerate only outer vlan in QinQ\n");
2421                 return -EINVAL;
2422         }
2423
2424         return 0;
2425 }
2426
2427 static int
2428 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2429                              struct rte_ether_addr *addr)
2430 {
2431         struct bnxt *bp = dev->data->dev_private;
2432         /* Default Filter is tied to VNIC 0 */
2433         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2434         int rc;
2435
2436         rc = is_bnxt_in_error(bp);
2437         if (rc)
2438                 return rc;
2439
2440         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2441                 return -EPERM;
2442
2443         if (rte_is_zero_ether_addr(addr))
2444                 return -EINVAL;
2445
2446         /* Filter settings will get applied when port is started */
2447         if (!dev->data->dev_started)
2448                 return 0;
2449
2450         /* Check if the requested MAC is already added */
2451         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2452                 return 0;
2453
2454         /* Destroy filter and re-create it */
2455         bnxt_del_dflt_mac_filter(bp, vnic);
2456
2457         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2458         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2459                 /* This filter will allow only untagged packets */
2460                 rc = bnxt_add_vlan_filter(bp, 0);
2461         } else {
2462                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2463         }
2464
2465         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2466         return rc;
2467 }
2468
2469 static int
2470 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2471                           struct rte_ether_addr *mc_addr_set,
2472                           uint32_t nb_mc_addr)
2473 {
2474         struct bnxt *bp = eth_dev->data->dev_private;
2475         char *mc_addr_list = (char *)mc_addr_set;
2476         struct bnxt_vnic_info *vnic;
2477         uint32_t off = 0, i = 0;
2478         int rc;
2479
2480         rc = is_bnxt_in_error(bp);
2481         if (rc)
2482                 return rc;
2483
2484         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2485
2486         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2487                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2488                 goto allmulti;
2489         }
2490
2491         /* TODO Check for Duplicate mcast addresses */
2492         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2493         for (i = 0; i < nb_mc_addr; i++) {
2494                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2495                         RTE_ETHER_ADDR_LEN);
2496                 off += RTE_ETHER_ADDR_LEN;
2497         }
2498
2499         vnic->mc_addr_cnt = i;
2500         if (vnic->mc_addr_cnt)
2501                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2502         else
2503                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2504
2505 allmulti:
2506         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2507 }
2508
2509 static int
2510 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2511 {
2512         struct bnxt *bp = dev->data->dev_private;
2513         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2514         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2515         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2516         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2517         int ret;
2518
2519         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2520                         fw_major, fw_minor, fw_updt, fw_rsvd);
2521
2522         ret += 1; /* add the size of '\0' */
2523         if (fw_size < (uint32_t)ret)
2524                 return ret;
2525         else
2526                 return 0;
2527 }
2528
2529 static void
2530 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2531         struct rte_eth_rxq_info *qinfo)
2532 {
2533         struct bnxt *bp = dev->data->dev_private;
2534         struct bnxt_rx_queue *rxq;
2535
2536         if (is_bnxt_in_error(bp))
2537                 return;
2538
2539         rxq = dev->data->rx_queues[queue_id];
2540
2541         qinfo->mp = rxq->mb_pool;
2542         qinfo->scattered_rx = dev->data->scattered_rx;
2543         qinfo->nb_desc = rxq->nb_rx_desc;
2544
2545         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2546         qinfo->conf.rx_drop_en = 0;
2547         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2548 }
2549
2550 static void
2551 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2552         struct rte_eth_txq_info *qinfo)
2553 {
2554         struct bnxt *bp = dev->data->dev_private;
2555         struct bnxt_tx_queue *txq;
2556
2557         if (is_bnxt_in_error(bp))
2558                 return;
2559
2560         txq = dev->data->tx_queues[queue_id];
2561
2562         qinfo->nb_desc = txq->nb_tx_desc;
2563
2564         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2565         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2566         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2567
2568         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2569         qinfo->conf.tx_rs_thresh = 0;
2570         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2571 }
2572
2573 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2574 {
2575         struct bnxt *bp = eth_dev->data->dev_private;
2576         uint32_t new_pkt_size;
2577         uint32_t rc = 0;
2578         uint32_t i;
2579
2580         rc = is_bnxt_in_error(bp);
2581         if (rc)
2582                 return rc;
2583
2584         /* Exit if receive queues are not configured yet */
2585         if (!eth_dev->data->nb_rx_queues)
2586                 return rc;
2587
2588         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2589                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2590
2591 #ifdef RTE_ARCH_X86
2592         /*
2593          * If vector-mode tx/rx is active, disallow any MTU change that would
2594          * require scattered receive support.
2595          */
2596         if (eth_dev->data->dev_started &&
2597             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2598              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2599             (new_pkt_size >
2600              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2601                 PMD_DRV_LOG(ERR,
2602                             "MTU change would require scattered rx support. ");
2603                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2604                 return -EINVAL;
2605         }
2606 #endif
2607
2608         if (new_mtu > RTE_ETHER_MTU) {
2609                 bp->flags |= BNXT_FLAG_JUMBO;
2610                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2611                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2612         } else {
2613                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2614                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2615                 bp->flags &= ~BNXT_FLAG_JUMBO;
2616         }
2617
2618         /* Is there a change in mtu setting? */
2619         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2620                 return rc;
2621
2622         for (i = 0; i < bp->nr_vnics; i++) {
2623                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2624                 uint16_t size = 0;
2625
2626                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2627                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2628                 if (rc)
2629                         break;
2630
2631                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2632                 size -= RTE_PKTMBUF_HEADROOM;
2633
2634                 if (size < new_mtu) {
2635                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2636                         if (rc)
2637                                 return rc;
2638                 }
2639         }
2640
2641         if (!rc)
2642                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2643
2644         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2645
2646         return rc;
2647 }
2648
2649 static int
2650 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2651 {
2652         struct bnxt *bp = dev->data->dev_private;
2653         uint16_t vlan = bp->vlan;
2654         int rc;
2655
2656         rc = is_bnxt_in_error(bp);
2657         if (rc)
2658                 return rc;
2659
2660         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2661                 PMD_DRV_LOG(ERR,
2662                         "PVID cannot be modified for this function\n");
2663                 return -ENOTSUP;
2664         }
2665         bp->vlan = on ? pvid : 0;
2666
2667         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2668         if (rc)
2669                 bp->vlan = vlan;
2670         return rc;
2671 }
2672
2673 static int
2674 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2675 {
2676         struct bnxt *bp = dev->data->dev_private;
2677         int rc;
2678
2679         rc = is_bnxt_in_error(bp);
2680         if (rc)
2681                 return rc;
2682
2683         return bnxt_hwrm_port_led_cfg(bp, true);
2684 }
2685
2686 static int
2687 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2688 {
2689         struct bnxt *bp = dev->data->dev_private;
2690         int rc;
2691
2692         rc = is_bnxt_in_error(bp);
2693         if (rc)
2694                 return rc;
2695
2696         return bnxt_hwrm_port_led_cfg(bp, false);
2697 }
2698
2699 static uint32_t
2700 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2701 {
2702         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2703         uint32_t desc = 0, raw_cons = 0, cons;
2704         struct bnxt_cp_ring_info *cpr;
2705         struct bnxt_rx_queue *rxq;
2706         struct rx_pkt_cmpl *rxcmp;
2707         int rc;
2708
2709         rc = is_bnxt_in_error(bp);
2710         if (rc)
2711                 return rc;
2712
2713         rxq = dev->data->rx_queues[rx_queue_id];
2714         cpr = rxq->cp_ring;
2715         raw_cons = cpr->cp_raw_cons;
2716
2717         while (1) {
2718                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2719                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2720                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2721
2722                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2723                         break;
2724                 } else {
2725                         raw_cons++;
2726                         desc++;
2727                 }
2728         }
2729
2730         return desc;
2731 }
2732
2733 static int
2734 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2735 {
2736         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2737         struct bnxt_rx_ring_info *rxr;
2738         struct bnxt_cp_ring_info *cpr;
2739         struct bnxt_sw_rx_bd *rx_buf;
2740         struct rx_pkt_cmpl *rxcmp;
2741         uint32_t cons, cp_cons;
2742         int rc;
2743
2744         if (!rxq)
2745                 return -EINVAL;
2746
2747         rc = is_bnxt_in_error(rxq->bp);
2748         if (rc)
2749                 return rc;
2750
2751         cpr = rxq->cp_ring;
2752         rxr = rxq->rx_ring;
2753
2754         if (offset >= rxq->nb_rx_desc)
2755                 return -EINVAL;
2756
2757         cons = RING_CMP(cpr->cp_ring_struct, offset);
2758         cp_cons = cpr->cp_raw_cons;
2759         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2760
2761         if (cons > cp_cons) {
2762                 if (CMPL_VALID(rxcmp, cpr->valid))
2763                         return RTE_ETH_RX_DESC_DONE;
2764         } else {
2765                 if (CMPL_VALID(rxcmp, !cpr->valid))
2766                         return RTE_ETH_RX_DESC_DONE;
2767         }
2768         rx_buf = &rxr->rx_buf_ring[cons];
2769         if (rx_buf->mbuf == NULL)
2770                 return RTE_ETH_RX_DESC_UNAVAIL;
2771
2772
2773         return RTE_ETH_RX_DESC_AVAIL;
2774 }
2775
2776 static int
2777 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2778 {
2779         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2780         struct bnxt_tx_ring_info *txr;
2781         struct bnxt_cp_ring_info *cpr;
2782         struct bnxt_sw_tx_bd *tx_buf;
2783         struct tx_pkt_cmpl *txcmp;
2784         uint32_t cons, cp_cons;
2785         int rc;
2786
2787         if (!txq)
2788                 return -EINVAL;
2789
2790         rc = is_bnxt_in_error(txq->bp);
2791         if (rc)
2792                 return rc;
2793
2794         cpr = txq->cp_ring;
2795         txr = txq->tx_ring;
2796
2797         if (offset >= txq->nb_tx_desc)
2798                 return -EINVAL;
2799
2800         cons = RING_CMP(cpr->cp_ring_struct, offset);
2801         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2802         cp_cons = cpr->cp_raw_cons;
2803
2804         if (cons > cp_cons) {
2805                 if (CMPL_VALID(txcmp, cpr->valid))
2806                         return RTE_ETH_TX_DESC_UNAVAIL;
2807         } else {
2808                 if (CMPL_VALID(txcmp, !cpr->valid))
2809                         return RTE_ETH_TX_DESC_UNAVAIL;
2810         }
2811         tx_buf = &txr->tx_buf_ring[cons];
2812         if (tx_buf->mbuf == NULL)
2813                 return RTE_ETH_TX_DESC_DONE;
2814
2815         return RTE_ETH_TX_DESC_FULL;
2816 }
2817
2818 static struct bnxt_filter_info *
2819 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2820                                 struct rte_eth_ethertype_filter *efilter,
2821                                 struct bnxt_vnic_info *vnic0,
2822                                 struct bnxt_vnic_info *vnic,
2823                                 int *ret)
2824 {
2825         struct bnxt_filter_info *mfilter = NULL;
2826         int match = 0;
2827         *ret = 0;
2828
2829         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2830                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2831                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2832                         " ethertype filter.", efilter->ether_type);
2833                 *ret = -EINVAL;
2834                 goto exit;
2835         }
2836         if (efilter->queue >= bp->rx_nr_rings) {
2837                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2838                 *ret = -EINVAL;
2839                 goto exit;
2840         }
2841
2842         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2843         vnic = &bp->vnic_info[efilter->queue];
2844         if (vnic == NULL) {
2845                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2846                 *ret = -EINVAL;
2847                 goto exit;
2848         }
2849
2850         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2851                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2852                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2853                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2854                              mfilter->flags ==
2855                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2856                              mfilter->ethertype == efilter->ether_type)) {
2857                                 match = 1;
2858                                 break;
2859                         }
2860                 }
2861         } else {
2862                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2863                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2864                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2865                              mfilter->ethertype == efilter->ether_type &&
2866                              mfilter->flags ==
2867                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2868                                 match = 1;
2869                                 break;
2870                         }
2871         }
2872
2873         if (match)
2874                 *ret = -EEXIST;
2875
2876 exit:
2877         return mfilter;
2878 }
2879
2880 static int
2881 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2882                         enum rte_filter_op filter_op,
2883                         void *arg)
2884 {
2885         struct bnxt *bp = dev->data->dev_private;
2886         struct rte_eth_ethertype_filter *efilter =
2887                         (struct rte_eth_ethertype_filter *)arg;
2888         struct bnxt_filter_info *bfilter, *filter1;
2889         struct bnxt_vnic_info *vnic, *vnic0;
2890         int ret;
2891
2892         if (filter_op == RTE_ETH_FILTER_NOP)
2893                 return 0;
2894
2895         if (arg == NULL) {
2896                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2897                             filter_op);
2898                 return -EINVAL;
2899         }
2900
2901         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2902         vnic = &bp->vnic_info[efilter->queue];
2903
2904         switch (filter_op) {
2905         case RTE_ETH_FILTER_ADD:
2906                 bnxt_match_and_validate_ether_filter(bp, efilter,
2907                                                         vnic0, vnic, &ret);
2908                 if (ret < 0)
2909                         return ret;
2910
2911                 bfilter = bnxt_get_unused_filter(bp);
2912                 if (bfilter == NULL) {
2913                         PMD_DRV_LOG(ERR,
2914                                 "Not enough resources for a new filter.\n");
2915                         return -ENOMEM;
2916                 }
2917                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2918                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2919                        RTE_ETHER_ADDR_LEN);
2920                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2921                        RTE_ETHER_ADDR_LEN);
2922                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2923                 bfilter->ethertype = efilter->ether_type;
2924                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2925
2926                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2927                 if (filter1 == NULL) {
2928                         ret = -EINVAL;
2929                         goto cleanup;
2930                 }
2931                 bfilter->enables |=
2932                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2933                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2934
2935                 bfilter->dst_id = vnic->fw_vnic_id;
2936
2937                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2938                         bfilter->flags =
2939                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2940                 }
2941
2942                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2943                 if (ret)
2944                         goto cleanup;
2945                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2946                 break;
2947         case RTE_ETH_FILTER_DELETE:
2948                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2949                                                         vnic0, vnic, &ret);
2950                 if (ret == -EEXIST) {
2951                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2952
2953                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2954                                       next);
2955                         bnxt_free_filter(bp, filter1);
2956                 } else if (ret == 0) {
2957                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2958                 }
2959                 break;
2960         default:
2961                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2962                 ret = -EINVAL;
2963                 goto error;
2964         }
2965         return ret;
2966 cleanup:
2967         bnxt_free_filter(bp, bfilter);
2968 error:
2969         return ret;
2970 }
2971
2972 static inline int
2973 parse_ntuple_filter(struct bnxt *bp,
2974                     struct rte_eth_ntuple_filter *nfilter,
2975                     struct bnxt_filter_info *bfilter)
2976 {
2977         uint32_t en = 0;
2978
2979         if (nfilter->queue >= bp->rx_nr_rings) {
2980                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2981                 return -EINVAL;
2982         }
2983
2984         switch (nfilter->dst_port_mask) {
2985         case UINT16_MAX:
2986                 bfilter->dst_port_mask = -1;
2987                 bfilter->dst_port = nfilter->dst_port;
2988                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2989                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2990                 break;
2991         default:
2992                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2993                 return -EINVAL;
2994         }
2995
2996         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2997         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2998
2999         switch (nfilter->proto_mask) {
3000         case UINT8_MAX:
3001                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3002                         bfilter->ip_protocol = 17;
3003                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3004                         bfilter->ip_protocol = 6;
3005                 else
3006                         return -EINVAL;
3007                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3008                 break;
3009         default:
3010                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3011                 return -EINVAL;
3012         }
3013
3014         switch (nfilter->dst_ip_mask) {
3015         case UINT32_MAX:
3016                 bfilter->dst_ipaddr_mask[0] = -1;
3017                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3018                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3019                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3020                 break;
3021         default:
3022                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3023                 return -EINVAL;
3024         }
3025
3026         switch (nfilter->src_ip_mask) {
3027         case UINT32_MAX:
3028                 bfilter->src_ipaddr_mask[0] = -1;
3029                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3030                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3031                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3032                 break;
3033         default:
3034                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3035                 return -EINVAL;
3036         }
3037
3038         switch (nfilter->src_port_mask) {
3039         case UINT16_MAX:
3040                 bfilter->src_port_mask = -1;
3041                 bfilter->src_port = nfilter->src_port;
3042                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3043                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3044                 break;
3045         default:
3046                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3047                 return -EINVAL;
3048         }
3049
3050         bfilter->enables = en;
3051         return 0;
3052 }
3053
3054 static struct bnxt_filter_info*
3055 bnxt_match_ntuple_filter(struct bnxt *bp,
3056                          struct bnxt_filter_info *bfilter,
3057                          struct bnxt_vnic_info **mvnic)
3058 {
3059         struct bnxt_filter_info *mfilter = NULL;
3060         int i;
3061
3062         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3063                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3064                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3065                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3066                             bfilter->src_ipaddr_mask[0] ==
3067                             mfilter->src_ipaddr_mask[0] &&
3068                             bfilter->src_port == mfilter->src_port &&
3069                             bfilter->src_port_mask == mfilter->src_port_mask &&
3070                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3071                             bfilter->dst_ipaddr_mask[0] ==
3072                             mfilter->dst_ipaddr_mask[0] &&
3073                             bfilter->dst_port == mfilter->dst_port &&
3074                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3075                             bfilter->flags == mfilter->flags &&
3076                             bfilter->enables == mfilter->enables) {
3077                                 if (mvnic)
3078                                         *mvnic = vnic;
3079                                 return mfilter;
3080                         }
3081                 }
3082         }
3083         return NULL;
3084 }
3085
3086 static int
3087 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3088                        struct rte_eth_ntuple_filter *nfilter,
3089                        enum rte_filter_op filter_op)
3090 {
3091         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3092         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3093         int ret;
3094
3095         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3096                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3097                 return -EINVAL;
3098         }
3099
3100         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3101                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3102                 return -EINVAL;
3103         }
3104
3105         bfilter = bnxt_get_unused_filter(bp);
3106         if (bfilter == NULL) {
3107                 PMD_DRV_LOG(ERR,
3108                         "Not enough resources for a new filter.\n");
3109                 return -ENOMEM;
3110         }
3111         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3112         if (ret < 0)
3113                 goto free_filter;
3114
3115         vnic = &bp->vnic_info[nfilter->queue];
3116         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3117         filter1 = STAILQ_FIRST(&vnic0->filter);
3118         if (filter1 == NULL) {
3119                 ret = -EINVAL;
3120                 goto free_filter;
3121         }
3122
3123         bfilter->dst_id = vnic->fw_vnic_id;
3124         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3125         bfilter->enables |=
3126                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3127         bfilter->ethertype = 0x800;
3128         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3129
3130         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3131
3132         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3133             bfilter->dst_id == mfilter->dst_id) {
3134                 PMD_DRV_LOG(ERR, "filter exists.\n");
3135                 ret = -EEXIST;
3136                 goto free_filter;
3137         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3138                    bfilter->dst_id != mfilter->dst_id) {
3139                 mfilter->dst_id = vnic->fw_vnic_id;
3140                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3141                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3142                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3143                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3144                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3145                 goto free_filter;
3146         }
3147         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3148                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3149                 ret = -ENOENT;
3150                 goto free_filter;
3151         }
3152
3153         if (filter_op == RTE_ETH_FILTER_ADD) {
3154                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3155                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3156                 if (ret)
3157                         goto free_filter;
3158                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3159         } else {
3160                 if (mfilter == NULL) {
3161                         /* This should not happen. But for Coverity! */
3162                         ret = -ENOENT;
3163                         goto free_filter;
3164                 }
3165                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3166
3167                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3168                 bnxt_free_filter(bp, mfilter);
3169                 bnxt_free_filter(bp, bfilter);
3170         }
3171
3172         return 0;
3173 free_filter:
3174         bnxt_free_filter(bp, bfilter);
3175         return ret;
3176 }
3177
3178 static int
3179 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3180                         enum rte_filter_op filter_op,
3181                         void *arg)
3182 {
3183         struct bnxt *bp = dev->data->dev_private;
3184         int ret;
3185
3186         if (filter_op == RTE_ETH_FILTER_NOP)
3187                 return 0;
3188
3189         if (arg == NULL) {
3190                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3191                             filter_op);
3192                 return -EINVAL;
3193         }
3194
3195         switch (filter_op) {
3196         case RTE_ETH_FILTER_ADD:
3197                 ret = bnxt_cfg_ntuple_filter(bp,
3198                         (struct rte_eth_ntuple_filter *)arg,
3199                         filter_op);
3200                 break;
3201         case RTE_ETH_FILTER_DELETE:
3202                 ret = bnxt_cfg_ntuple_filter(bp,
3203                         (struct rte_eth_ntuple_filter *)arg,
3204                         filter_op);
3205                 break;
3206         default:
3207                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3208                 ret = -EINVAL;
3209                 break;
3210         }
3211         return ret;
3212 }
3213
3214 static int
3215 bnxt_parse_fdir_filter(struct bnxt *bp,
3216                        struct rte_eth_fdir_filter *fdir,
3217                        struct bnxt_filter_info *filter)
3218 {
3219         enum rte_fdir_mode fdir_mode =
3220                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3221         struct bnxt_vnic_info *vnic0, *vnic;
3222         struct bnxt_filter_info *filter1;
3223         uint32_t en = 0;
3224         int i;
3225
3226         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3227                 return -EINVAL;
3228
3229         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3230         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3231
3232         switch (fdir->input.flow_type) {
3233         case RTE_ETH_FLOW_IPV4:
3234         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3235                 /* FALLTHROUGH */
3236                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3237                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3238                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3239                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3240                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3241                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3242                 filter->ip_addr_type =
3243                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3244                 filter->src_ipaddr_mask[0] = 0xffffffff;
3245                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3246                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3247                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3248                 filter->ethertype = 0x800;
3249                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3250                 break;
3251         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3252                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3253                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3254                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3255                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3256                 filter->dst_port_mask = 0xffff;
3257                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3258                 filter->src_port_mask = 0xffff;
3259                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3260                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3261                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3262                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3263                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3264                 filter->ip_protocol = 6;
3265                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3266                 filter->ip_addr_type =
3267                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3268                 filter->src_ipaddr_mask[0] = 0xffffffff;
3269                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3270                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3271                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3272                 filter->ethertype = 0x800;
3273                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3274                 break;
3275         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3276                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3277                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3278                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3279                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3280                 filter->dst_port_mask = 0xffff;
3281                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3282                 filter->src_port_mask = 0xffff;
3283                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3284                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3285                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3286                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3287                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3288                 filter->ip_protocol = 17;
3289                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3290                 filter->ip_addr_type =
3291                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3292                 filter->src_ipaddr_mask[0] = 0xffffffff;
3293                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3294                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3295                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3296                 filter->ethertype = 0x800;
3297                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3298                 break;
3299         case RTE_ETH_FLOW_IPV6:
3300         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3301                 /* FALLTHROUGH */
3302                 filter->ip_addr_type =
3303                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3304                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3305                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3306                 rte_memcpy(filter->src_ipaddr,
3307                            fdir->input.flow.ipv6_flow.src_ip, 16);
3308                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3309                 rte_memcpy(filter->dst_ipaddr,
3310                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3311                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3312                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3313                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3314                 memset(filter->src_ipaddr_mask, 0xff, 16);
3315                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3316                 filter->ethertype = 0x86dd;
3317                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3318                 break;
3319         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3320                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3321                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3322                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3323                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3324                 filter->dst_port_mask = 0xffff;
3325                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3326                 filter->src_port_mask = 0xffff;
3327                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3328                 filter->ip_addr_type =
3329                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3330                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3331                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3332                 rte_memcpy(filter->src_ipaddr,
3333                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3334                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3335                 rte_memcpy(filter->dst_ipaddr,
3336                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3337                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3338                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3339                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3340                 memset(filter->src_ipaddr_mask, 0xff, 16);
3341                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3342                 filter->ethertype = 0x86dd;
3343                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3344                 break;
3345         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3346                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3347                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3348                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3349                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3350                 filter->dst_port_mask = 0xffff;
3351                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3352                 filter->src_port_mask = 0xffff;
3353                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3354                 filter->ip_addr_type =
3355                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3356                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3357                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3358                 rte_memcpy(filter->src_ipaddr,
3359                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3360                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3361                 rte_memcpy(filter->dst_ipaddr,
3362                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3363                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3364                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3365                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3366                 memset(filter->src_ipaddr_mask, 0xff, 16);
3367                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3368                 filter->ethertype = 0x86dd;
3369                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3370                 break;
3371         case RTE_ETH_FLOW_L2_PAYLOAD:
3372                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3373                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3374                 break;
3375         case RTE_ETH_FLOW_VXLAN:
3376                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3377                         return -EINVAL;
3378                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3379                 filter->tunnel_type =
3380                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3381                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3382                 break;
3383         case RTE_ETH_FLOW_NVGRE:
3384                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3385                         return -EINVAL;
3386                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3387                 filter->tunnel_type =
3388                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3389                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3390                 break;
3391         case RTE_ETH_FLOW_UNKNOWN:
3392         case RTE_ETH_FLOW_RAW:
3393         case RTE_ETH_FLOW_FRAG_IPV4:
3394         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3395         case RTE_ETH_FLOW_FRAG_IPV6:
3396         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3397         case RTE_ETH_FLOW_IPV6_EX:
3398         case RTE_ETH_FLOW_IPV6_TCP_EX:
3399         case RTE_ETH_FLOW_IPV6_UDP_EX:
3400         case RTE_ETH_FLOW_GENEVE:
3401                 /* FALLTHROUGH */
3402         default:
3403                 return -EINVAL;
3404         }
3405
3406         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3407         vnic = &bp->vnic_info[fdir->action.rx_queue];
3408         if (vnic == NULL) {
3409                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3410                 return -EINVAL;
3411         }
3412
3413         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3414                 rte_memcpy(filter->dst_macaddr,
3415                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3416                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3417         }
3418
3419         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3420                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3421                 filter1 = STAILQ_FIRST(&vnic0->filter);
3422                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3423         } else {
3424                 filter->dst_id = vnic->fw_vnic_id;
3425                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3426                         if (filter->dst_macaddr[i] == 0x00)
3427                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3428                         else
3429                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3430         }
3431
3432         if (filter1 == NULL)
3433                 return -EINVAL;
3434
3435         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3436         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3437
3438         filter->enables = en;
3439
3440         return 0;
3441 }
3442
3443 static struct bnxt_filter_info *
3444 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3445                 struct bnxt_vnic_info **mvnic)
3446 {
3447         struct bnxt_filter_info *mf = NULL;
3448         int i;
3449
3450         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3451                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3452
3453                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3454                         if (mf->filter_type == nf->filter_type &&
3455                             mf->flags == nf->flags &&
3456                             mf->src_port == nf->src_port &&
3457                             mf->src_port_mask == nf->src_port_mask &&
3458                             mf->dst_port == nf->dst_port &&
3459                             mf->dst_port_mask == nf->dst_port_mask &&
3460                             mf->ip_protocol == nf->ip_protocol &&
3461                             mf->ip_addr_type == nf->ip_addr_type &&
3462                             mf->ethertype == nf->ethertype &&
3463                             mf->vni == nf->vni &&
3464                             mf->tunnel_type == nf->tunnel_type &&
3465                             mf->l2_ovlan == nf->l2_ovlan &&
3466                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3467                             mf->l2_ivlan == nf->l2_ivlan &&
3468                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3469                             !memcmp(mf->l2_addr, nf->l2_addr,
3470                                     RTE_ETHER_ADDR_LEN) &&
3471                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3472                                     RTE_ETHER_ADDR_LEN) &&
3473                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3474                                     RTE_ETHER_ADDR_LEN) &&
3475                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3476                                     RTE_ETHER_ADDR_LEN) &&
3477                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3478                                     sizeof(nf->src_ipaddr)) &&
3479                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3480                                     sizeof(nf->src_ipaddr_mask)) &&
3481                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3482                                     sizeof(nf->dst_ipaddr)) &&
3483                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3484                                     sizeof(nf->dst_ipaddr_mask))) {
3485                                 if (mvnic)
3486                                         *mvnic = vnic;
3487                                 return mf;
3488                         }
3489                 }
3490         }
3491         return NULL;
3492 }
3493
3494 static int
3495 bnxt_fdir_filter(struct rte_eth_dev *dev,
3496                  enum rte_filter_op filter_op,
3497                  void *arg)
3498 {
3499         struct bnxt *bp = dev->data->dev_private;
3500         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3501         struct bnxt_filter_info *filter, *match;
3502         struct bnxt_vnic_info *vnic, *mvnic;
3503         int ret = 0, i;
3504
3505         if (filter_op == RTE_ETH_FILTER_NOP)
3506                 return 0;
3507
3508         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3509                 return -EINVAL;
3510
3511         switch (filter_op) {
3512         case RTE_ETH_FILTER_ADD:
3513         case RTE_ETH_FILTER_DELETE:
3514                 /* FALLTHROUGH */
3515                 filter = bnxt_get_unused_filter(bp);
3516                 if (filter == NULL) {
3517                         PMD_DRV_LOG(ERR,
3518                                 "Not enough resources for a new flow.\n");
3519                         return -ENOMEM;
3520                 }
3521
3522                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3523                 if (ret != 0)
3524                         goto free_filter;
3525                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3526
3527                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3528                         vnic = &bp->vnic_info[0];
3529                 else
3530                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3531
3532                 match = bnxt_match_fdir(bp, filter, &mvnic);
3533                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3534                         if (match->dst_id == vnic->fw_vnic_id) {
3535                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3536                                 ret = -EEXIST;
3537                                 goto free_filter;
3538                         } else {
3539                                 match->dst_id = vnic->fw_vnic_id;
3540                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3541                                                                   match->dst_id,
3542                                                                   match);
3543                                 STAILQ_REMOVE(&mvnic->filter, match,
3544                                               bnxt_filter_info, next);
3545                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3546                                 PMD_DRV_LOG(ERR,
3547                                         "Filter with matching pattern exist\n");
3548                                 PMD_DRV_LOG(ERR,
3549                                         "Updated it to new destination q\n");
3550                                 goto free_filter;
3551                         }
3552                 }
3553                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3554                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3555                         ret = -ENOENT;
3556                         goto free_filter;
3557                 }
3558
3559                 if (filter_op == RTE_ETH_FILTER_ADD) {
3560                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3561                                                           filter->dst_id,
3562                                                           filter);
3563                         if (ret)
3564                                 goto free_filter;
3565                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3566                 } else {
3567                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3568                         STAILQ_REMOVE(&vnic->filter, match,
3569                                       bnxt_filter_info, next);
3570                         bnxt_free_filter(bp, match);
3571                         bnxt_free_filter(bp, filter);
3572                 }
3573                 break;
3574         case RTE_ETH_FILTER_FLUSH:
3575                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3576                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3577
3578                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3579                                 if (filter->filter_type ==
3580                                     HWRM_CFA_NTUPLE_FILTER) {
3581                                         ret =
3582                                         bnxt_hwrm_clear_ntuple_filter(bp,
3583                                                                       filter);
3584                                         STAILQ_REMOVE(&vnic->filter, filter,
3585                                                       bnxt_filter_info, next);
3586                                 }
3587                         }
3588                 }
3589                 return ret;
3590         case RTE_ETH_FILTER_UPDATE:
3591         case RTE_ETH_FILTER_STATS:
3592         case RTE_ETH_FILTER_INFO:
3593                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3594                 break;
3595         default:
3596                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3597                 ret = -EINVAL;
3598                 break;
3599         }
3600         return ret;
3601
3602 free_filter:
3603         bnxt_free_filter(bp, filter);
3604         return ret;
3605 }
3606
3607 static int
3608 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3609                     enum rte_filter_type filter_type,
3610                     enum rte_filter_op filter_op, void *arg)
3611 {
3612         struct bnxt *bp = dev->data->dev_private;
3613         int ret = 0;
3614
3615         ret = is_bnxt_in_error(dev->data->dev_private);
3616         if (ret)
3617                 return ret;
3618
3619         switch (filter_type) {
3620         case RTE_ETH_FILTER_TUNNEL:
3621                 PMD_DRV_LOG(ERR,
3622                         "filter type: %d: To be implemented\n", filter_type);
3623                 break;
3624         case RTE_ETH_FILTER_FDIR:
3625                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3626                 break;
3627         case RTE_ETH_FILTER_NTUPLE:
3628                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3629                 break;
3630         case RTE_ETH_FILTER_ETHERTYPE:
3631                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3632                 break;
3633         case RTE_ETH_FILTER_GENERIC:
3634                 if (filter_op != RTE_ETH_FILTER_GET)
3635                         return -EINVAL;
3636                 if (BNXT_TRUFLOW_EN(bp))
3637                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3638                 else
3639                         *(const void **)arg = &bnxt_flow_ops;
3640                 break;
3641         default:
3642                 PMD_DRV_LOG(ERR,
3643                         "Filter type (%d) not supported", filter_type);
3644                 ret = -EINVAL;
3645                 break;
3646         }
3647         return ret;
3648 }
3649
3650 static const uint32_t *
3651 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3652 {
3653         static const uint32_t ptypes[] = {
3654                 RTE_PTYPE_L2_ETHER_VLAN,
3655                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3656                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3657                 RTE_PTYPE_L4_ICMP,
3658                 RTE_PTYPE_L4_TCP,
3659                 RTE_PTYPE_L4_UDP,
3660                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3661                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3662                 RTE_PTYPE_INNER_L4_ICMP,
3663                 RTE_PTYPE_INNER_L4_TCP,
3664                 RTE_PTYPE_INNER_L4_UDP,
3665                 RTE_PTYPE_UNKNOWN
3666         };
3667
3668         if (!dev->rx_pkt_burst)
3669                 return NULL;
3670
3671         return ptypes;
3672 }
3673
3674 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3675                          int reg_win)
3676 {
3677         uint32_t reg_base = *reg_arr & 0xfffff000;
3678         uint32_t win_off;
3679         int i;
3680
3681         for (i = 0; i < count; i++) {
3682                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3683                         return -ERANGE;
3684         }
3685         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3686         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3687         return 0;
3688 }
3689
3690 static int bnxt_map_ptp_regs(struct bnxt *bp)
3691 {
3692         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3693         uint32_t *reg_arr;
3694         int rc, i;
3695
3696         reg_arr = ptp->rx_regs;
3697         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3698         if (rc)
3699                 return rc;
3700
3701         reg_arr = ptp->tx_regs;
3702         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3703         if (rc)
3704                 return rc;
3705
3706         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3707                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3708
3709         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3710                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3711
3712         return 0;
3713 }
3714
3715 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3716 {
3717         rte_write32(0, (uint8_t *)bp->bar0 +
3718                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3719         rte_write32(0, (uint8_t *)bp->bar0 +
3720                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3721 }
3722
3723 static uint64_t bnxt_cc_read(struct bnxt *bp)
3724 {
3725         uint64_t ns;
3726
3727         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3728                               BNXT_GRCPF_REG_SYNC_TIME));
3729         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3730                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3731         return ns;
3732 }
3733
3734 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3735 {
3736         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3737         uint32_t fifo;
3738
3739         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3740                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3741         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3742                 return -EAGAIN;
3743
3744         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3745                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3746         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3747                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3748         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3749                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3750
3751         return 0;
3752 }
3753
3754 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3755 {
3756         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3757         struct bnxt_pf_info *pf = bp->pf;
3758         uint16_t port_id;
3759         uint32_t fifo;
3760
3761         if (!ptp)
3762                 return -ENODEV;
3763
3764         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3765                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3766         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3767                 return -EAGAIN;
3768
3769         port_id = pf->port_id;
3770         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3771                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3772
3773         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3774                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3775         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3776 /*              bnxt_clr_rx_ts(bp);       TBD  */
3777                 return -EBUSY;
3778         }
3779
3780         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3781                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3782         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3783                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3784
3785         return 0;
3786 }
3787
3788 static int
3789 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3790 {
3791         uint64_t ns;
3792         struct bnxt *bp = dev->data->dev_private;
3793         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3794
3795         if (!ptp)
3796                 return 0;
3797
3798         ns = rte_timespec_to_ns(ts);
3799         /* Set the timecounters to a new value. */
3800         ptp->tc.nsec = ns;
3801
3802         return 0;
3803 }
3804
3805 static int
3806 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3807 {
3808         struct bnxt *bp = dev->data->dev_private;
3809         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3810         uint64_t ns, systime_cycles = 0;
3811         int rc = 0;
3812
3813         if (!ptp)
3814                 return 0;
3815
3816         if (BNXT_CHIP_THOR(bp))
3817                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3818                                              &systime_cycles);
3819         else
3820                 systime_cycles = bnxt_cc_read(bp);
3821
3822         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3823         *ts = rte_ns_to_timespec(ns);
3824
3825         return rc;
3826 }
3827 static int
3828 bnxt_timesync_enable(struct rte_eth_dev *dev)
3829 {
3830         struct bnxt *bp = dev->data->dev_private;
3831         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3832         uint32_t shift = 0;
3833         int rc;
3834
3835         if (!ptp)
3836                 return 0;
3837
3838         ptp->rx_filter = 1;
3839         ptp->tx_tstamp_en = 1;
3840         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3841
3842         rc = bnxt_hwrm_ptp_cfg(bp);
3843         if (rc)
3844                 return rc;
3845
3846         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3847         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3848         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3849
3850         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3851         ptp->tc.cc_shift = shift;
3852         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3853
3854         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3855         ptp->rx_tstamp_tc.cc_shift = shift;
3856         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3857
3858         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3859         ptp->tx_tstamp_tc.cc_shift = shift;
3860         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3861
3862         if (!BNXT_CHIP_THOR(bp))
3863                 bnxt_map_ptp_regs(bp);
3864
3865         return 0;
3866 }
3867
3868 static int
3869 bnxt_timesync_disable(struct rte_eth_dev *dev)
3870 {
3871         struct bnxt *bp = dev->data->dev_private;
3872         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3873
3874         if (!ptp)
3875                 return 0;
3876
3877         ptp->rx_filter = 0;
3878         ptp->tx_tstamp_en = 0;
3879         ptp->rxctl = 0;
3880
3881         bnxt_hwrm_ptp_cfg(bp);
3882
3883         if (!BNXT_CHIP_THOR(bp))
3884                 bnxt_unmap_ptp_regs(bp);
3885
3886         return 0;
3887 }
3888
3889 static int
3890 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3891                                  struct timespec *timestamp,
3892                                  uint32_t flags __rte_unused)
3893 {
3894         struct bnxt *bp = dev->data->dev_private;
3895         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3896         uint64_t rx_tstamp_cycles = 0;
3897         uint64_t ns;
3898
3899         if (!ptp)
3900                 return 0;
3901
3902         if (BNXT_CHIP_THOR(bp))
3903                 rx_tstamp_cycles = ptp->rx_timestamp;
3904         else
3905                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3906
3907         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3908         *timestamp = rte_ns_to_timespec(ns);
3909         return  0;
3910 }
3911
3912 static int
3913 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3914                                  struct timespec *timestamp)
3915 {
3916         struct bnxt *bp = dev->data->dev_private;
3917         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3918         uint64_t tx_tstamp_cycles = 0;
3919         uint64_t ns;
3920         int rc = 0;
3921
3922         if (!ptp)
3923                 return 0;
3924
3925         if (BNXT_CHIP_THOR(bp))
3926                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3927                                              &tx_tstamp_cycles);
3928         else
3929                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3930
3931         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3932         *timestamp = rte_ns_to_timespec(ns);
3933
3934         return rc;
3935 }
3936
3937 static int
3938 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3939 {
3940         struct bnxt *bp = dev->data->dev_private;
3941         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3942
3943         if (!ptp)
3944                 return 0;
3945
3946         ptp->tc.nsec += delta;
3947
3948         return 0;
3949 }
3950
3951 static int
3952 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3953 {
3954         struct bnxt *bp = dev->data->dev_private;
3955         int rc;
3956         uint32_t dir_entries;
3957         uint32_t entry_length;
3958
3959         rc = is_bnxt_in_error(bp);
3960         if (rc)
3961                 return rc;
3962
3963         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3964                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3965                     bp->pdev->addr.devid, bp->pdev->addr.function);
3966
3967         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3968         if (rc != 0)
3969                 return rc;
3970
3971         return dir_entries * entry_length;
3972 }
3973
3974 static int
3975 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3976                 struct rte_dev_eeprom_info *in_eeprom)
3977 {
3978         struct bnxt *bp = dev->data->dev_private;
3979         uint32_t index;
3980         uint32_t offset;
3981         int rc;
3982
3983         rc = is_bnxt_in_error(bp);
3984         if (rc)
3985                 return rc;
3986
3987         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3988                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3989                     bp->pdev->addr.devid, bp->pdev->addr.function,
3990                     in_eeprom->offset, in_eeprom->length);
3991
3992         if (in_eeprom->offset == 0) /* special offset value to get directory */
3993                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3994                                                 in_eeprom->data);
3995
3996         index = in_eeprom->offset >> 24;
3997         offset = in_eeprom->offset & 0xffffff;
3998
3999         if (index != 0)
4000                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4001                                            in_eeprom->length, in_eeprom->data);
4002
4003         return 0;
4004 }
4005
4006 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4007 {
4008         switch (dir_type) {
4009         case BNX_DIR_TYPE_CHIMP_PATCH:
4010         case BNX_DIR_TYPE_BOOTCODE:
4011         case BNX_DIR_TYPE_BOOTCODE_2:
4012         case BNX_DIR_TYPE_APE_FW:
4013         case BNX_DIR_TYPE_APE_PATCH:
4014         case BNX_DIR_TYPE_KONG_FW:
4015         case BNX_DIR_TYPE_KONG_PATCH:
4016         case BNX_DIR_TYPE_BONO_FW:
4017         case BNX_DIR_TYPE_BONO_PATCH:
4018                 /* FALLTHROUGH */
4019                 return true;
4020         }
4021
4022         return false;
4023 }
4024
4025 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4026 {
4027         switch (dir_type) {
4028         case BNX_DIR_TYPE_AVS:
4029         case BNX_DIR_TYPE_EXP_ROM_MBA:
4030         case BNX_DIR_TYPE_PCIE:
4031         case BNX_DIR_TYPE_TSCF_UCODE:
4032         case BNX_DIR_TYPE_EXT_PHY:
4033         case BNX_DIR_TYPE_CCM:
4034         case BNX_DIR_TYPE_ISCSI_BOOT:
4035         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4036         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4037                 /* FALLTHROUGH */
4038                 return true;
4039         }
4040
4041         return false;
4042 }
4043
4044 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4045 {
4046         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4047                 bnxt_dir_type_is_other_exec_format(dir_type);
4048 }
4049
4050 static int
4051 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4052                 struct rte_dev_eeprom_info *in_eeprom)
4053 {
4054         struct bnxt *bp = dev->data->dev_private;
4055         uint8_t index, dir_op;
4056         uint16_t type, ext, ordinal, attr;
4057         int rc;
4058
4059         rc = is_bnxt_in_error(bp);
4060         if (rc)
4061                 return rc;
4062
4063         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4064                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4065                     bp->pdev->addr.devid, bp->pdev->addr.function,
4066                     in_eeprom->offset, in_eeprom->length);
4067
4068         if (!BNXT_PF(bp)) {
4069                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4070                 return -EINVAL;
4071         }
4072
4073         type = in_eeprom->magic >> 16;
4074
4075         if (type == 0xffff) { /* special value for directory operations */
4076                 index = in_eeprom->magic & 0xff;
4077                 dir_op = in_eeprom->magic >> 8;
4078                 if (index == 0)
4079                         return -EINVAL;
4080                 switch (dir_op) {
4081                 case 0x0e: /* erase */
4082                         if (in_eeprom->offset != ~in_eeprom->magic)
4083                                 return -EINVAL;
4084                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4085                 default:
4086                         return -EINVAL;
4087                 }
4088         }
4089
4090         /* Create or re-write an NVM item: */
4091         if (bnxt_dir_type_is_executable(type) == true)
4092                 return -EOPNOTSUPP;
4093         ext = in_eeprom->magic & 0xffff;
4094         ordinal = in_eeprom->offset >> 16;
4095         attr = in_eeprom->offset & 0xffff;
4096
4097         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4098                                      in_eeprom->data, in_eeprom->length);
4099 }
4100
4101 /*
4102  * Initialization
4103  */
4104
4105 static const struct eth_dev_ops bnxt_dev_ops = {
4106         .dev_infos_get = bnxt_dev_info_get_op,
4107         .dev_close = bnxt_dev_close_op,
4108         .dev_configure = bnxt_dev_configure_op,
4109         .dev_start = bnxt_dev_start_op,
4110         .dev_stop = bnxt_dev_stop_op,
4111         .dev_set_link_up = bnxt_dev_set_link_up_op,
4112         .dev_set_link_down = bnxt_dev_set_link_down_op,
4113         .stats_get = bnxt_stats_get_op,
4114         .stats_reset = bnxt_stats_reset_op,
4115         .rx_queue_setup = bnxt_rx_queue_setup_op,
4116         .rx_queue_release = bnxt_rx_queue_release_op,
4117         .tx_queue_setup = bnxt_tx_queue_setup_op,
4118         .tx_queue_release = bnxt_tx_queue_release_op,
4119         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4120         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4121         .reta_update = bnxt_reta_update_op,
4122         .reta_query = bnxt_reta_query_op,
4123         .rss_hash_update = bnxt_rss_hash_update_op,
4124         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4125         .link_update = bnxt_link_update_op,
4126         .promiscuous_enable = bnxt_promiscuous_enable_op,
4127         .promiscuous_disable = bnxt_promiscuous_disable_op,
4128         .allmulticast_enable = bnxt_allmulticast_enable_op,
4129         .allmulticast_disable = bnxt_allmulticast_disable_op,
4130         .mac_addr_add = bnxt_mac_addr_add_op,
4131         .mac_addr_remove = bnxt_mac_addr_remove_op,
4132         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4133         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4134         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4135         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4136         .vlan_filter_set = bnxt_vlan_filter_set_op,
4137         .vlan_offload_set = bnxt_vlan_offload_set_op,
4138         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4139         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4140         .mtu_set = bnxt_mtu_set_op,
4141         .mac_addr_set = bnxt_set_default_mac_addr_op,
4142         .xstats_get = bnxt_dev_xstats_get_op,
4143         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4144         .xstats_reset = bnxt_dev_xstats_reset_op,
4145         .fw_version_get = bnxt_fw_version_get,
4146         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4147         .rxq_info_get = bnxt_rxq_info_get_op,
4148         .txq_info_get = bnxt_txq_info_get_op,
4149         .dev_led_on = bnxt_dev_led_on_op,
4150         .dev_led_off = bnxt_dev_led_off_op,
4151         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4152         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4153         .rx_queue_count = bnxt_rx_queue_count_op,
4154         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4155         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4156         .rx_queue_start = bnxt_rx_queue_start,
4157         .rx_queue_stop = bnxt_rx_queue_stop,
4158         .tx_queue_start = bnxt_tx_queue_start,
4159         .tx_queue_stop = bnxt_tx_queue_stop,
4160         .filter_ctrl = bnxt_filter_ctrl_op,
4161         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4162         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4163         .get_eeprom           = bnxt_get_eeprom_op,
4164         .set_eeprom           = bnxt_set_eeprom_op,
4165         .timesync_enable      = bnxt_timesync_enable,
4166         .timesync_disable     = bnxt_timesync_disable,
4167         .timesync_read_time   = bnxt_timesync_read_time,
4168         .timesync_write_time   = bnxt_timesync_write_time,
4169         .timesync_adjust_time = bnxt_timesync_adjust_time,
4170         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4171         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4172 };
4173
4174 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4175 {
4176         uint32_t offset;
4177
4178         /* Only pre-map the reset GRC registers using window 3 */
4179         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4180                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4181
4182         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4183
4184         return offset;
4185 }
4186
4187 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4188 {
4189         struct bnxt_error_recovery_info *info = bp->recovery_info;
4190         uint32_t reg_base = 0xffffffff;
4191         int i;
4192
4193         /* Only pre-map the monitoring GRC registers using window 2 */
4194         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4195                 uint32_t reg = info->status_regs[i];
4196
4197                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4198                         continue;
4199
4200                 if (reg_base == 0xffffffff)
4201                         reg_base = reg & 0xfffff000;
4202                 if ((reg & 0xfffff000) != reg_base)
4203                         return -ERANGE;
4204
4205                 /* Use mask 0xffc as the Lower 2 bits indicates
4206                  * address space location
4207                  */
4208                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4209                                                 (reg & 0xffc);
4210         }
4211
4212         if (reg_base == 0xffffffff)
4213                 return 0;
4214
4215         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4216                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4217
4218         return 0;
4219 }
4220
4221 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4222 {
4223         struct bnxt_error_recovery_info *info = bp->recovery_info;
4224         uint32_t delay = info->delay_after_reset[index];
4225         uint32_t val = info->reset_reg_val[index];
4226         uint32_t reg = info->reset_reg[index];
4227         uint32_t type, offset;
4228
4229         type = BNXT_FW_STATUS_REG_TYPE(reg);
4230         offset = BNXT_FW_STATUS_REG_OFF(reg);
4231
4232         switch (type) {
4233         case BNXT_FW_STATUS_REG_TYPE_CFG:
4234                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4235                 break;
4236         case BNXT_FW_STATUS_REG_TYPE_GRC:
4237                 offset = bnxt_map_reset_regs(bp, offset);
4238                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4239                 break;
4240         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4241                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4242                 break;
4243         }
4244         /* wait on a specific interval of time until core reset is complete */
4245         if (delay)
4246                 rte_delay_ms(delay);
4247 }
4248
4249 static void bnxt_dev_cleanup(struct bnxt *bp)
4250 {
4251         bnxt_set_hwrm_link_config(bp, false);
4252         bp->link_info->link_up = 0;
4253         if (bp->eth_dev->data->dev_started)
4254                 bnxt_dev_stop_op(bp->eth_dev);
4255
4256         bnxt_uninit_resources(bp, true);
4257 }
4258
4259 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4260 {
4261         struct rte_eth_dev *dev = bp->eth_dev;
4262         struct rte_vlan_filter_conf *vfc;
4263         int vidx, vbit, rc;
4264         uint16_t vlan_id;
4265
4266         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4267                 vfc = &dev->data->vlan_filter_conf;
4268                 vidx = vlan_id / 64;
4269                 vbit = vlan_id % 64;
4270
4271                 /* Each bit corresponds to a VLAN id */
4272                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4273                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4274                         if (rc)
4275                                 return rc;
4276                 }
4277         }
4278
4279         return 0;
4280 }
4281
4282 static int bnxt_restore_mac_filters(struct bnxt *bp)
4283 {
4284         struct rte_eth_dev *dev = bp->eth_dev;
4285         struct rte_eth_dev_info dev_info;
4286         struct rte_ether_addr *addr;
4287         uint64_t pool_mask;
4288         uint32_t pool = 0;
4289         uint16_t i;
4290         int rc;
4291
4292         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4293                 return 0;
4294
4295         rc = bnxt_dev_info_get_op(dev, &dev_info);
4296         if (rc)
4297                 return rc;
4298
4299         /* replay MAC address configuration */
4300         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4301                 addr = &dev->data->mac_addrs[i];
4302
4303                 /* skip zero address */
4304                 if (rte_is_zero_ether_addr(addr))
4305                         continue;
4306
4307                 pool = 0;
4308                 pool_mask = dev->data->mac_pool_sel[i];
4309
4310                 do {
4311                         if (pool_mask & 1ULL) {
4312                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4313                                 if (rc)
4314                                         return rc;
4315                         }
4316                         pool_mask >>= 1;
4317                         pool++;
4318                 } while (pool_mask);
4319         }
4320
4321         return 0;
4322 }
4323
4324 static int bnxt_restore_filters(struct bnxt *bp)
4325 {
4326         struct rte_eth_dev *dev = bp->eth_dev;
4327         int ret = 0;
4328
4329         if (dev->data->all_multicast) {
4330                 ret = bnxt_allmulticast_enable_op(dev);
4331                 if (ret)
4332                         return ret;
4333         }
4334         if (dev->data->promiscuous) {
4335                 ret = bnxt_promiscuous_enable_op(dev);
4336                 if (ret)
4337                         return ret;
4338         }
4339
4340         ret = bnxt_restore_mac_filters(bp);
4341         if (ret)
4342                 return ret;
4343
4344         ret = bnxt_restore_vlan_filters(bp);
4345         /* TODO restore other filters as well */
4346         return ret;
4347 }
4348
4349 static void bnxt_dev_recover(void *arg)
4350 {
4351         struct bnxt *bp = arg;
4352         int timeout = bp->fw_reset_max_msecs;
4353         int rc = 0;
4354
4355         /* Clear Error flag so that device re-init should happen */
4356         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4357
4358         do {
4359                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4360                 if (rc == 0)
4361                         break;
4362                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4363                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4364         } while (rc && timeout);
4365
4366         if (rc) {
4367                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4368                 goto err;
4369         }
4370
4371         rc = bnxt_init_resources(bp, true);
4372         if (rc) {
4373                 PMD_DRV_LOG(ERR,
4374                             "Failed to initialize resources after reset\n");
4375                 goto err;
4376         }
4377         /* clear reset flag as the device is initialized now */
4378         bp->flags &= ~BNXT_FLAG_FW_RESET;
4379
4380         rc = bnxt_dev_start_op(bp->eth_dev);
4381         if (rc) {
4382                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4383                 goto err_start;
4384         }
4385
4386         rc = bnxt_restore_filters(bp);
4387         if (rc)
4388                 goto err_start;
4389
4390         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4391         return;
4392 err_start:
4393         bnxt_dev_stop_op(bp->eth_dev);
4394 err:
4395         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4396         bnxt_uninit_resources(bp, false);
4397         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4398 }
4399
4400 void bnxt_dev_reset_and_resume(void *arg)
4401 {
4402         struct bnxt *bp = arg;
4403         int rc;
4404
4405         bnxt_dev_cleanup(bp);
4406
4407         bnxt_wait_for_device_shutdown(bp);
4408
4409         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4410                                bnxt_dev_recover, (void *)bp);
4411         if (rc)
4412                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4413 }
4414
4415 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4416 {
4417         struct bnxt_error_recovery_info *info = bp->recovery_info;
4418         uint32_t reg = info->status_regs[index];
4419         uint32_t type, offset, val = 0;
4420
4421         type = BNXT_FW_STATUS_REG_TYPE(reg);
4422         offset = BNXT_FW_STATUS_REG_OFF(reg);
4423
4424         switch (type) {
4425         case BNXT_FW_STATUS_REG_TYPE_CFG:
4426                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4427                 break;
4428         case BNXT_FW_STATUS_REG_TYPE_GRC:
4429                 offset = info->mapped_status_regs[index];
4430                 /* FALLTHROUGH */
4431         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4432                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4433                                        offset));
4434                 break;
4435         }
4436
4437         return val;
4438 }
4439
4440 static int bnxt_fw_reset_all(struct bnxt *bp)
4441 {
4442         struct bnxt_error_recovery_info *info = bp->recovery_info;
4443         uint32_t i;
4444         int rc = 0;
4445
4446         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4447                 /* Reset through master function driver */
4448                 for (i = 0; i < info->reg_array_cnt; i++)
4449                         bnxt_write_fw_reset_reg(bp, i);
4450                 /* Wait for time specified by FW after triggering reset */
4451                 rte_delay_ms(info->master_func_wait_period_after_reset);
4452         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4453                 /* Reset with the help of Kong processor */
4454                 rc = bnxt_hwrm_fw_reset(bp);
4455                 if (rc)
4456                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4457         }
4458
4459         return rc;
4460 }
4461
4462 static void bnxt_fw_reset_cb(void *arg)
4463 {
4464         struct bnxt *bp = arg;
4465         struct bnxt_error_recovery_info *info = bp->recovery_info;
4466         int rc = 0;
4467
4468         /* Only Master function can do FW reset */
4469         if (bnxt_is_master_func(bp) &&
4470             bnxt_is_recovery_enabled(bp)) {
4471                 rc = bnxt_fw_reset_all(bp);
4472                 if (rc) {
4473                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4474                         return;
4475                 }
4476         }
4477
4478         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4479          * EXCEPTION_FATAL_ASYNC event to all the functions
4480          * (including MASTER FUNC). After receiving this Async, all the active
4481          * drivers should treat this case as FW initiated recovery
4482          */
4483         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4484                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4485                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4486
4487                 /* To recover from error */
4488                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4489                                   (void *)bp);
4490         }
4491 }
4492
4493 /* Driver should poll FW heartbeat, reset_counter with the frequency
4494  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4495  * When the driver detects heartbeat stop or change in reset_counter,
4496  * it has to trigger a reset to recover from the error condition.
4497  * A “master PF” is the function who will have the privilege to
4498  * initiate the chimp reset. The master PF will be elected by the
4499  * firmware and will be notified through async message.
4500  */
4501 static void bnxt_check_fw_health(void *arg)
4502 {
4503         struct bnxt *bp = arg;
4504         struct bnxt_error_recovery_info *info = bp->recovery_info;
4505         uint32_t val = 0, wait_msec;
4506
4507         if (!info || !bnxt_is_recovery_enabled(bp) ||
4508             is_bnxt_in_error(bp))
4509                 return;
4510
4511         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4512         if (val == info->last_heart_beat)
4513                 goto reset;
4514
4515         info->last_heart_beat = val;
4516
4517         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4518         if (val != info->last_reset_counter)
4519                 goto reset;
4520
4521         info->last_reset_counter = val;
4522
4523         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4524                           bnxt_check_fw_health, (void *)bp);
4525
4526         return;
4527 reset:
4528         /* Stop DMA to/from device */
4529         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4530         bp->flags |= BNXT_FLAG_FW_RESET;
4531
4532         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4533
4534         if (bnxt_is_master_func(bp))
4535                 wait_msec = info->master_func_wait_period;
4536         else
4537                 wait_msec = info->normal_func_wait_period;
4538
4539         rte_eal_alarm_set(US_PER_MS * wait_msec,
4540                           bnxt_fw_reset_cb, (void *)bp);
4541 }
4542
4543 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4544 {
4545         uint32_t polling_freq;
4546
4547         if (!bnxt_is_recovery_enabled(bp))
4548                 return;
4549
4550         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4551                 return;
4552
4553         polling_freq = bp->recovery_info->driver_polling_freq;
4554
4555         rte_eal_alarm_set(US_PER_MS * polling_freq,
4556                           bnxt_check_fw_health, (void *)bp);
4557         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4558 }
4559
4560 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4561 {
4562         if (!bnxt_is_recovery_enabled(bp))
4563                 return;
4564
4565         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4566         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4567 }
4568
4569 static bool bnxt_vf_pciid(uint16_t device_id)
4570 {
4571         switch (device_id) {
4572         case BROADCOM_DEV_ID_57304_VF:
4573         case BROADCOM_DEV_ID_57406_VF:
4574         case BROADCOM_DEV_ID_5731X_VF:
4575         case BROADCOM_DEV_ID_5741X_VF:
4576         case BROADCOM_DEV_ID_57414_VF:
4577         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4578         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4579         case BROADCOM_DEV_ID_58802_VF:
4580         case BROADCOM_DEV_ID_57500_VF1:
4581         case BROADCOM_DEV_ID_57500_VF2:
4582                 /* FALLTHROUGH */
4583                 return true;
4584         default:
4585                 return false;
4586         }
4587 }
4588
4589 static bool bnxt_thor_device(uint16_t device_id)
4590 {
4591         switch (device_id) {
4592         case BROADCOM_DEV_ID_57508:
4593         case BROADCOM_DEV_ID_57504:
4594         case BROADCOM_DEV_ID_57502:
4595         case BROADCOM_DEV_ID_57508_MF1:
4596         case BROADCOM_DEV_ID_57504_MF1:
4597         case BROADCOM_DEV_ID_57502_MF1:
4598         case BROADCOM_DEV_ID_57508_MF2:
4599         case BROADCOM_DEV_ID_57504_MF2:
4600         case BROADCOM_DEV_ID_57502_MF2:
4601         case BROADCOM_DEV_ID_57500_VF1:
4602         case BROADCOM_DEV_ID_57500_VF2:
4603                 /* FALLTHROUGH */
4604                 return true;
4605         default:
4606                 return false;
4607         }
4608 }
4609
4610 bool bnxt_stratus_device(struct bnxt *bp)
4611 {
4612         uint16_t device_id = bp->pdev->id.device_id;
4613
4614         switch (device_id) {
4615         case BROADCOM_DEV_ID_STRATUS_NIC:
4616         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4617         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4618                 /* FALLTHROUGH */
4619                 return true;
4620         default:
4621                 return false;
4622         }
4623 }
4624
4625 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4626 {
4627         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4628         struct bnxt *bp = eth_dev->data->dev_private;
4629
4630         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4631         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4632         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4633         if (!bp->bar0 || !bp->doorbell_base) {
4634                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4635                 return -ENODEV;
4636         }
4637
4638         bp->eth_dev = eth_dev;
4639         bp->pdev = pci_dev;
4640
4641         return 0;
4642 }
4643
4644 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4645                                   struct bnxt_ctx_pg_info *ctx_pg,
4646                                   uint32_t mem_size,
4647                                   const char *suffix,
4648                                   uint16_t idx)
4649 {
4650         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4651         const struct rte_memzone *mz = NULL;
4652         char mz_name[RTE_MEMZONE_NAMESIZE];
4653         rte_iova_t mz_phys_addr;
4654         uint64_t valid_bits = 0;
4655         uint32_t sz;
4656         int i;
4657
4658         if (!mem_size)
4659                 return 0;
4660
4661         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4662                          BNXT_PAGE_SIZE;
4663         rmem->page_size = BNXT_PAGE_SIZE;
4664         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4665         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4666         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4667
4668         valid_bits = PTU_PTE_VALID;
4669
4670         if (rmem->nr_pages > 1) {
4671                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4672                          "bnxt_ctx_pg_tbl%s_%x_%d",
4673                          suffix, idx, bp->eth_dev->data->port_id);
4674                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4675                 mz = rte_memzone_lookup(mz_name);
4676                 if (!mz) {
4677                         mz = rte_memzone_reserve_aligned(mz_name,
4678                                                 rmem->nr_pages * 8,
4679                                                 SOCKET_ID_ANY,
4680                                                 RTE_MEMZONE_2MB |
4681                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4682                                                 RTE_MEMZONE_IOVA_CONTIG,
4683                                                 BNXT_PAGE_SIZE);
4684                         if (mz == NULL)
4685                                 return -ENOMEM;
4686                 }
4687
4688                 memset(mz->addr, 0, mz->len);
4689                 mz_phys_addr = mz->iova;
4690
4691                 rmem->pg_tbl = mz->addr;
4692                 rmem->pg_tbl_map = mz_phys_addr;
4693                 rmem->pg_tbl_mz = mz;
4694         }
4695
4696         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4697                  suffix, idx, bp->eth_dev->data->port_id);
4698         mz = rte_memzone_lookup(mz_name);
4699         if (!mz) {
4700                 mz = rte_memzone_reserve_aligned(mz_name,
4701                                                  mem_size,
4702                                                  SOCKET_ID_ANY,
4703                                                  RTE_MEMZONE_1GB |
4704                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4705                                                  RTE_MEMZONE_IOVA_CONTIG,
4706                                                  BNXT_PAGE_SIZE);
4707                 if (mz == NULL)
4708                         return -ENOMEM;
4709         }
4710
4711         memset(mz->addr, 0, mz->len);
4712         mz_phys_addr = mz->iova;
4713
4714         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4715                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4716                 rmem->dma_arr[i] = mz_phys_addr + sz;
4717
4718                 if (rmem->nr_pages > 1) {
4719                         if (i == rmem->nr_pages - 2 &&
4720                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4721                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4722                         else if (i == rmem->nr_pages - 1 &&
4723                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4724                                 valid_bits |= PTU_PTE_LAST;
4725
4726                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4727                                                            valid_bits);
4728                 }
4729         }
4730
4731         rmem->mz = mz;
4732         if (rmem->vmem_size)
4733                 rmem->vmem = (void **)mz->addr;
4734         rmem->dma_arr[0] = mz_phys_addr;
4735         return 0;
4736 }
4737
4738 static void bnxt_free_ctx_mem(struct bnxt *bp)
4739 {
4740         int i;
4741
4742         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4743                 return;
4744
4745         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4746         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4747         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4748         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4749         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4750         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4751         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4752         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4753         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4754         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4755         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4756
4757         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4758                 if (bp->ctx->tqm_mem[i])
4759                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4760         }
4761
4762         rte_free(bp->ctx);
4763         bp->ctx = NULL;
4764 }
4765
4766 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4767
4768 #define min_t(type, x, y) ({                    \
4769         type __min1 = (x);                      \
4770         type __min2 = (y);                      \
4771         __min1 < __min2 ? __min1 : __min2; })
4772
4773 #define max_t(type, x, y) ({                    \
4774         type __max1 = (x);                      \
4775         type __max2 = (y);                      \
4776         __max1 > __max2 ? __max1 : __max2; })
4777
4778 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4779
4780 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4781 {
4782         struct bnxt_ctx_pg_info *ctx_pg;
4783         struct bnxt_ctx_mem_info *ctx;
4784         uint32_t mem_size, ena, entries;
4785         uint32_t entries_sp, min;
4786         int i, rc;
4787
4788         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4789         if (rc) {
4790                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4791                 return rc;
4792         }
4793         ctx = bp->ctx;
4794         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4795                 return 0;
4796
4797         ctx_pg = &ctx->qp_mem;
4798         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4799         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4800         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4801         if (rc)
4802                 return rc;
4803
4804         ctx_pg = &ctx->srq_mem;
4805         ctx_pg->entries = ctx->srq_max_l2_entries;
4806         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4807         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4808         if (rc)
4809                 return rc;
4810
4811         ctx_pg = &ctx->cq_mem;
4812         ctx_pg->entries = ctx->cq_max_l2_entries;
4813         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4814         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4815         if (rc)
4816                 return rc;
4817
4818         ctx_pg = &ctx->vnic_mem;
4819         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4820                 ctx->vnic_max_ring_table_entries;
4821         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4822         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4823         if (rc)
4824                 return rc;
4825
4826         ctx_pg = &ctx->stat_mem;
4827         ctx_pg->entries = ctx->stat_max_entries;
4828         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4829         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4830         if (rc)
4831                 return rc;
4832
4833         min = ctx->tqm_min_entries_per_ring;
4834
4835         entries_sp = ctx->qp_max_l2_entries +
4836                      ctx->vnic_max_vnic_entries +
4837                      2 * ctx->qp_min_qp1_entries + min;
4838         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4839
4840         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4841         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4842         entries = clamp_t(uint32_t, entries, min,
4843                           ctx->tqm_max_entries_per_ring);
4844         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4845                 ctx_pg = ctx->tqm_mem[i];
4846                 ctx_pg->entries = i ? entries : entries_sp;
4847                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4848                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4849                 if (rc)
4850                         return rc;
4851                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4852         }
4853
4854         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4855         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4856         if (rc)
4857                 PMD_DRV_LOG(ERR,
4858                             "Failed to configure context mem: rc = %d\n", rc);
4859         else
4860                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4861
4862         return rc;
4863 }
4864
4865 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4866 {
4867         struct rte_pci_device *pci_dev = bp->pdev;
4868         char mz_name[RTE_MEMZONE_NAMESIZE];
4869         const struct rte_memzone *mz = NULL;
4870         uint32_t total_alloc_len;
4871         rte_iova_t mz_phys_addr;
4872
4873         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4874                 return 0;
4875
4876         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4877                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4878                  pci_dev->addr.bus, pci_dev->addr.devid,
4879                  pci_dev->addr.function, "rx_port_stats");
4880         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4881         mz = rte_memzone_lookup(mz_name);
4882         total_alloc_len =
4883                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4884                                        sizeof(struct rx_port_stats_ext) + 512);
4885         if (!mz) {
4886                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4887                                          SOCKET_ID_ANY,
4888                                          RTE_MEMZONE_2MB |
4889                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4890                                          RTE_MEMZONE_IOVA_CONTIG);
4891                 if (mz == NULL)
4892                         return -ENOMEM;
4893         }
4894         memset(mz->addr, 0, mz->len);
4895         mz_phys_addr = mz->iova;
4896
4897         bp->rx_mem_zone = (const void *)mz;
4898         bp->hw_rx_port_stats = mz->addr;
4899         bp->hw_rx_port_stats_map = mz_phys_addr;
4900
4901         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4902                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4903                  pci_dev->addr.bus, pci_dev->addr.devid,
4904                  pci_dev->addr.function, "tx_port_stats");
4905         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4906         mz = rte_memzone_lookup(mz_name);
4907         total_alloc_len =
4908                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4909                                        sizeof(struct tx_port_stats_ext) + 512);
4910         if (!mz) {
4911                 mz = rte_memzone_reserve(mz_name,
4912                                          total_alloc_len,
4913                                          SOCKET_ID_ANY,
4914                                          RTE_MEMZONE_2MB |
4915                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4916                                          RTE_MEMZONE_IOVA_CONTIG);
4917                 if (mz == NULL)
4918                         return -ENOMEM;
4919         }
4920         memset(mz->addr, 0, mz->len);
4921         mz_phys_addr = mz->iova;
4922
4923         bp->tx_mem_zone = (const void *)mz;
4924         bp->hw_tx_port_stats = mz->addr;
4925         bp->hw_tx_port_stats_map = mz_phys_addr;
4926         bp->flags |= BNXT_FLAG_PORT_STATS;
4927
4928         /* Display extended statistics if FW supports it */
4929         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4930             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4931             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4932                 return 0;
4933
4934         bp->hw_rx_port_stats_ext = (void *)
4935                 ((uint8_t *)bp->hw_rx_port_stats +
4936                  sizeof(struct rx_port_stats));
4937         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4938                 sizeof(struct rx_port_stats);
4939         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4940
4941         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4942             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4943                 bp->hw_tx_port_stats_ext = (void *)
4944                         ((uint8_t *)bp->hw_tx_port_stats +
4945                          sizeof(struct tx_port_stats));
4946                 bp->hw_tx_port_stats_ext_map =
4947                         bp->hw_tx_port_stats_map +
4948                         sizeof(struct tx_port_stats);
4949                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4950         }
4951
4952         return 0;
4953 }
4954
4955 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4956 {
4957         struct bnxt *bp = eth_dev->data->dev_private;
4958         int rc = 0;
4959
4960         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4961                                                RTE_ETHER_ADDR_LEN *
4962                                                bp->max_l2_ctx,
4963                                                0);
4964         if (eth_dev->data->mac_addrs == NULL) {
4965                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4966                 return -ENOMEM;
4967         }
4968
4969         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4970                 if (BNXT_PF(bp))
4971                         return -EINVAL;
4972
4973                 /* Generate a random MAC address, if none was assigned by PF */
4974                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4975                 bnxt_eth_hw_addr_random(bp->mac_addr);
4976                 PMD_DRV_LOG(INFO,
4977                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4978                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4979                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4980
4981                 rc = bnxt_hwrm_set_mac(bp);
4982                 if (rc)
4983                         return rc;
4984         }
4985
4986         /* Copy the permanent MAC from the FUNC_QCAPS response */
4987         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4988
4989         return rc;
4990 }
4991
4992 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4993 {
4994         int rc = 0;
4995
4996         /* MAC is already configured in FW */
4997         if (BNXT_HAS_DFLT_MAC_SET(bp))
4998                 return 0;
4999
5000         /* Restore the old MAC configured */
5001         rc = bnxt_hwrm_set_mac(bp);
5002         if (rc)
5003                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5004
5005         return rc;
5006 }
5007
5008 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5009 {
5010         if (!BNXT_PF(bp))
5011                 return;
5012
5013 #define ALLOW_FUNC(x)   \
5014         { \
5015                 uint32_t arg = (x); \
5016                 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5017                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5018         }
5019
5020         /* Forward all requests if firmware is new enough */
5021         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5022              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5023             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5024                 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5025         } else {
5026                 PMD_DRV_LOG(WARNING,
5027                             "Firmware too old for VF mailbox functionality\n");
5028                 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5029         }
5030
5031         /*
5032          * The following are used for driver cleanup. If we disallow these,
5033          * VF drivers can't clean up cleanly.
5034          */
5035         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5036         ALLOW_FUNC(HWRM_VNIC_FREE);
5037         ALLOW_FUNC(HWRM_RING_FREE);
5038         ALLOW_FUNC(HWRM_RING_GRP_FREE);
5039         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5040         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5041         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5042         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5043         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5044 }
5045
5046 uint16_t
5047 bnxt_get_svif(uint16_t port_id, bool func_svif)
5048 {
5049         struct rte_eth_dev *eth_dev;
5050         struct bnxt *bp;
5051
5052         eth_dev = &rte_eth_devices[port_id];
5053         bp = eth_dev->data->dev_private;
5054
5055         return func_svif ? bp->func_svif : bp->port_svif;
5056 }
5057
5058 uint16_t
5059 bnxt_get_vnic_id(uint16_t port)
5060 {
5061         struct rte_eth_dev *eth_dev;
5062         struct bnxt_vnic_info *vnic;
5063         struct bnxt *bp;
5064
5065         eth_dev = &rte_eth_devices[port];
5066         bp = eth_dev->data->dev_private;
5067
5068         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5069
5070         return vnic->fw_vnic_id;
5071 }
5072
5073 uint16_t
5074 bnxt_get_fw_func_id(uint16_t port)
5075 {
5076         struct rte_eth_dev *eth_dev;
5077         struct bnxt *bp;
5078
5079         eth_dev = &rte_eth_devices[port];
5080         bp = eth_dev->data->dev_private;
5081
5082         return bp->fw_fid;
5083 }
5084
5085 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5086 {
5087         struct bnxt_error_recovery_info *info = bp->recovery_info;
5088
5089         if (info) {
5090                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5091                         memset(info, 0, sizeof(*info));
5092                 return;
5093         }
5094
5095         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5096                 return;
5097
5098         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5099                            sizeof(*info), 0);
5100         if (!info)
5101                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5102
5103         bp->recovery_info = info;
5104 }
5105
5106 static void bnxt_check_fw_status(struct bnxt *bp)
5107 {
5108         uint32_t fw_status;
5109
5110         if (!(bp->recovery_info &&
5111               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5112                 return;
5113
5114         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5115         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5116                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5117                             fw_status);
5118 }
5119
5120 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5121 {
5122         struct bnxt_error_recovery_info *info = bp->recovery_info;
5123         uint32_t status_loc;
5124         uint32_t sig_ver;
5125
5126         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5127                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5128         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5129                                    BNXT_GRCP_WINDOW_2_BASE +
5130                                    offsetof(struct hcomm_status,
5131                                             sig_ver)));
5132         /* If the signature is absent, then FW does not support this feature */
5133         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5134             HCOMM_STATUS_SIGNATURE_VAL)
5135                 return 0;
5136
5137         if (!info) {
5138                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5139                                    sizeof(*info), 0);
5140                 if (!info)
5141                         return -ENOMEM;
5142                 bp->recovery_info = info;
5143         } else {
5144                 memset(info, 0, sizeof(*info));
5145         }
5146
5147         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5148                                       BNXT_GRCP_WINDOW_2_BASE +
5149                                       offsetof(struct hcomm_status,
5150                                                fw_status_loc)));
5151
5152         /* Only pre-map the FW health status GRC register */
5153         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5154                 return 0;
5155
5156         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5157         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5158                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5159
5160         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5161                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5162
5163         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5164
5165         return 0;
5166 }
5167
5168 static int bnxt_init_fw(struct bnxt *bp)
5169 {
5170         uint16_t mtu;
5171         int rc = 0;
5172
5173         bp->fw_cap = 0;
5174
5175         rc = bnxt_map_hcomm_fw_status_reg(bp);
5176         if (rc)
5177                 return rc;
5178
5179         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5180         if (rc) {
5181                 bnxt_check_fw_status(bp);
5182                 return rc;
5183         }
5184
5185         rc = bnxt_hwrm_func_reset(bp);
5186         if (rc)
5187                 return -EIO;
5188
5189         rc = bnxt_hwrm_vnic_qcaps(bp);
5190         if (rc)
5191                 return rc;
5192
5193         rc = bnxt_hwrm_queue_qportcfg(bp);
5194         if (rc)
5195                 return rc;
5196
5197         /* Get the MAX capabilities for this function.
5198          * This function also allocates context memory for TQM rings and
5199          * informs the firmware about this allocated backing store memory.
5200          */
5201         rc = bnxt_hwrm_func_qcaps(bp);
5202         if (rc)
5203                 return rc;
5204
5205         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5206         if (rc)
5207                 return rc;
5208
5209         bnxt_hwrm_port_mac_qcfg(bp);
5210
5211         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5212         if (rc)
5213                 return rc;
5214
5215         bnxt_alloc_error_recovery_info(bp);
5216         /* Get the adapter error recovery support info */
5217         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5218         if (rc)
5219                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5220
5221         bnxt_hwrm_port_led_qcaps(bp);
5222
5223         return 0;
5224 }
5225
5226 static int
5227 bnxt_init_locks(struct bnxt *bp)
5228 {
5229         int err;
5230
5231         err = pthread_mutex_init(&bp->flow_lock, NULL);
5232         if (err) {
5233                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5234                 return err;
5235         }
5236
5237         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5238         if (err)
5239                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5240         return err;
5241 }
5242
5243 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5244 {
5245         int rc;
5246
5247         rc = bnxt_init_fw(bp);
5248         if (rc)
5249                 return rc;
5250
5251         if (!reconfig_dev) {
5252                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5253                 if (rc)
5254                         return rc;
5255         } else {
5256                 rc = bnxt_restore_dflt_mac(bp);
5257                 if (rc)
5258                         return rc;
5259         }
5260
5261         bnxt_config_vf_req_fwd(bp);
5262
5263         rc = bnxt_hwrm_func_driver_register(bp);
5264         if (rc) {
5265                 PMD_DRV_LOG(ERR, "Failed to register driver");
5266                 return -EBUSY;
5267         }
5268
5269         if (BNXT_PF(bp)) {
5270                 if (bp->pdev->max_vfs) {
5271                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5272                         if (rc) {
5273                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5274                                 return rc;
5275                         }
5276                 } else {
5277                         rc = bnxt_hwrm_allocate_pf_only(bp);
5278                         if (rc) {
5279                                 PMD_DRV_LOG(ERR,
5280                                             "Failed to allocate PF resources");
5281                                 return rc;
5282                         }
5283                 }
5284         }
5285
5286         rc = bnxt_alloc_mem(bp, reconfig_dev);
5287         if (rc)
5288                 return rc;
5289
5290         rc = bnxt_setup_int(bp);
5291         if (rc)
5292                 return rc;
5293
5294         rc = bnxt_request_int(bp);
5295         if (rc)
5296                 return rc;
5297
5298         rc = bnxt_init_ctx_mem(bp);
5299         if (rc) {
5300                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5301                 return rc;
5302         }
5303
5304         rc = bnxt_init_locks(bp);
5305         if (rc)
5306                 return rc;
5307
5308         return 0;
5309 }
5310
5311 static int
5312 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5313                           const char *value, void *opaque_arg)
5314 {
5315         struct bnxt *bp = opaque_arg;
5316         unsigned long truflow;
5317         char *end = NULL;
5318
5319         if (!value || !opaque_arg) {
5320                 PMD_DRV_LOG(ERR,
5321                             "Invalid parameter passed to truflow devargs.\n");
5322                 return -EINVAL;
5323         }
5324
5325         truflow = strtoul(value, &end, 10);
5326         if (end == NULL || *end != '\0' ||
5327             (truflow == ULONG_MAX && errno == ERANGE)) {
5328                 PMD_DRV_LOG(ERR,
5329                             "Invalid parameter passed to truflow devargs.\n");
5330                 return -EINVAL;
5331         }
5332
5333         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5334                 PMD_DRV_LOG(ERR,
5335                             "Invalid value passed to truflow devargs.\n");
5336                 return -EINVAL;
5337         }
5338
5339         bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5340         if (BNXT_TRUFLOW_EN(bp))
5341                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5342
5343         return 0;
5344 }
5345
5346 static int
5347 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5348                              const char *value, void *opaque_arg)
5349 {
5350         struct bnxt *bp = opaque_arg;
5351         unsigned long flow_xstat;
5352         char *end = NULL;
5353
5354         if (!value || !opaque_arg) {
5355                 PMD_DRV_LOG(ERR,
5356                             "Invalid parameter passed to flow_xstat devarg.\n");
5357                 return -EINVAL;
5358         }
5359
5360         flow_xstat = strtoul(value, &end, 10);
5361         if (end == NULL || *end != '\0' ||
5362             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5363                 PMD_DRV_LOG(ERR,
5364                             "Invalid parameter passed to flow_xstat devarg.\n");
5365                 return -EINVAL;
5366         }
5367
5368         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5369                 PMD_DRV_LOG(ERR,
5370                             "Invalid value passed to flow_xstat devarg.\n");
5371                 return -EINVAL;
5372         }
5373
5374         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5375         if (BNXT_FLOW_XSTATS_EN(bp))
5376                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5377
5378         return 0;
5379 }
5380
5381 static int
5382 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5383                                         const char *value, void *opaque_arg)
5384 {
5385         struct bnxt *bp = opaque_arg;
5386         unsigned long max_num_kflows;
5387         char *end = NULL;
5388
5389         if (!value || !opaque_arg) {
5390                 PMD_DRV_LOG(ERR,
5391                         "Invalid parameter passed to max_num_kflows devarg.\n");
5392                 return -EINVAL;
5393         }
5394
5395         max_num_kflows = strtoul(value, &end, 10);
5396         if (end == NULL || *end != '\0' ||
5397                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5398                 PMD_DRV_LOG(ERR,
5399                         "Invalid parameter passed to max_num_kflows devarg.\n");
5400                 return -EINVAL;
5401         }
5402
5403         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5404                 PMD_DRV_LOG(ERR,
5405                         "Invalid value passed to max_num_kflows devarg.\n");
5406                 return -EINVAL;
5407         }
5408
5409         bp->max_num_kflows = max_num_kflows;
5410         if (bp->max_num_kflows)
5411                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5412                                 max_num_kflows);
5413
5414         return 0;
5415 }
5416
5417 static void
5418 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5419 {
5420         struct rte_kvargs *kvlist;
5421
5422         if (devargs == NULL)
5423                 return;
5424
5425         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5426         if (kvlist == NULL)
5427                 return;
5428
5429         /*
5430          * Handler for "truflow" devarg.
5431          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5432          */
5433         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5434                            bnxt_parse_devarg_truflow, bp);
5435
5436         /*
5437          * Handler for "flow_xstat" devarg.
5438          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5439          */
5440         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5441                            bnxt_parse_devarg_flow_xstat, bp);
5442
5443         /*
5444          * Handler for "max_num_kflows" devarg.
5445          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5446          */
5447         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5448                            bnxt_parse_devarg_max_num_kflows, bp);
5449
5450         rte_kvargs_free(kvlist);
5451 }
5452
5453 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5454 {
5455         int rc = 0;
5456
5457         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5458                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5459                 if (rc)
5460                         PMD_DRV_LOG(ERR,
5461                                     "Failed to alloc switch domain: %d\n", rc);
5462                 else
5463                         PMD_DRV_LOG(INFO,
5464                                     "Switch domain allocated %d\n",
5465                                     bp->switch_domain_id);
5466         }
5467
5468         return rc;
5469 }
5470
5471 static int
5472 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5473 {
5474         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5475         static int version_printed;
5476         struct bnxt *bp;
5477         int rc;
5478
5479         if (version_printed++ == 0)
5480                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5481
5482         eth_dev->dev_ops = &bnxt_dev_ops;
5483         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5484         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5485
5486         /*
5487          * For secondary processes, we don't initialise any further
5488          * as primary has already done this work.
5489          */
5490         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5491                 return 0;
5492
5493         rte_eth_copy_pci_info(eth_dev, pci_dev);
5494
5495         bp = eth_dev->data->dev_private;
5496
5497         /* Parse dev arguments passed on when starting the DPDK application. */
5498         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5499
5500         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5501
5502         if (bnxt_vf_pciid(pci_dev->id.device_id))
5503                 bp->flags |= BNXT_FLAG_VF;
5504
5505         if (bnxt_thor_device(pci_dev->id.device_id))
5506                 bp->flags |= BNXT_FLAG_THOR_CHIP;
5507
5508         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5509             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5510             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5511             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5512                 bp->flags |= BNXT_FLAG_STINGRAY;
5513
5514         rc = bnxt_init_board(eth_dev);
5515         if (rc) {
5516                 PMD_DRV_LOG(ERR,
5517                             "Failed to initialize board rc: %x\n", rc);
5518                 return rc;
5519         }
5520
5521         rc = bnxt_alloc_pf_info(bp);
5522         if (rc)
5523                 goto error_free;
5524
5525         rc = bnxt_alloc_link_info(bp);
5526         if (rc)
5527                 goto error_free;
5528
5529         rc = bnxt_alloc_hwrm_resources(bp);
5530         if (rc) {
5531                 PMD_DRV_LOG(ERR,
5532                             "Failed to allocate hwrm resource rc: %x\n", rc);
5533                 goto error_free;
5534         }
5535         rc = bnxt_alloc_leds_info(bp);
5536         if (rc)
5537                 goto error_free;
5538
5539         rc = bnxt_alloc_cos_queues(bp);
5540         if (rc)
5541                 goto error_free;
5542
5543         rc = bnxt_init_resources(bp, false);
5544         if (rc)
5545                 goto error_free;
5546
5547         rc = bnxt_alloc_stats_mem(bp);
5548         if (rc)
5549                 goto error_free;
5550
5551         bnxt_alloc_switch_domain(bp);
5552
5553         /* Pass the information to the rte_eth_dev_close() that it should also
5554          * release the private port resources.
5555          */
5556         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5557
5558         PMD_DRV_LOG(INFO,
5559                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5560                     pci_dev->mem_resource[0].phys_addr,
5561                     pci_dev->mem_resource[0].addr);
5562
5563         return 0;
5564
5565 error_free:
5566         bnxt_dev_uninit(eth_dev);
5567         return rc;
5568 }
5569
5570
5571 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5572 {
5573         if (!ctx)
5574                 return;
5575
5576         if (ctx->va)
5577                 rte_free(ctx->va);
5578
5579         ctx->va = NULL;
5580         ctx->dma = RTE_BAD_IOVA;
5581         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5582 }
5583
5584 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5585 {
5586         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5587                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5588                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5589                                   bp->flow_stat->max_fc,
5590                                   false);
5591
5592         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5593                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5594                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5595                                   bp->flow_stat->max_fc,
5596                                   false);
5597
5598         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5599                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5600         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5601
5602         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5603                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5604         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5605
5606         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5607                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5608         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5609
5610         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5611                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5612         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5613 }
5614
5615 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5616 {
5617         bnxt_unregister_fc_ctx_mem(bp);
5618
5619         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5620         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5621         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5622         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5623 }
5624
5625 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5626 {
5627         if (BNXT_FLOW_XSTATS_EN(bp))
5628                 bnxt_uninit_fc_ctx_mem(bp);
5629 }
5630
5631 static void
5632 bnxt_free_error_recovery_info(struct bnxt *bp)
5633 {
5634         rte_free(bp->recovery_info);
5635         bp->recovery_info = NULL;
5636         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5637 }
5638
5639 static void
5640 bnxt_uninit_locks(struct bnxt *bp)
5641 {
5642         pthread_mutex_destroy(&bp->flow_lock);
5643         pthread_mutex_destroy(&bp->def_cp_lock);
5644 }
5645
5646 static int
5647 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5648 {
5649         int rc;
5650
5651         bnxt_free_int(bp);
5652         bnxt_free_mem(bp, reconfig_dev);
5653         bnxt_hwrm_func_buf_unrgtr(bp);
5654         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5655         bp->flags &= ~BNXT_FLAG_REGISTERED;
5656         bnxt_free_ctx_mem(bp);
5657         if (!reconfig_dev) {
5658                 bnxt_free_hwrm_resources(bp);
5659                 bnxt_free_error_recovery_info(bp);
5660         }
5661
5662         bnxt_uninit_ctx_mem(bp);
5663
5664         bnxt_uninit_locks(bp);
5665         bnxt_free_flow_stats_info(bp);
5666         rte_free(bp->ptp_cfg);
5667         bp->ptp_cfg = NULL;
5668         return rc;
5669 }
5670
5671 static int
5672 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5673 {
5674         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5675                 return -EPERM;
5676
5677         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5678
5679         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5680                 bnxt_dev_close_op(eth_dev);
5681
5682         return 0;
5683 }
5684
5685 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5686 {
5687         struct bnxt *bp = eth_dev->data->dev_private;
5688         struct rte_eth_dev *vf_rep_eth_dev;
5689         int ret = 0, i;
5690
5691         if (!bp)
5692                 return -EINVAL;
5693
5694         for (i = 0; i < bp->num_reps; i++) {
5695                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5696                 if (!vf_rep_eth_dev)
5697                         continue;
5698                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit);
5699         }
5700         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5701
5702         return ret;
5703 }
5704
5705 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5706         struct rte_pci_device *pci_dev)
5707 {
5708         char name[RTE_ETH_NAME_MAX_LEN];
5709         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
5710         struct rte_eth_dev *backing_eth_dev, *vf_rep_eth_dev;
5711         uint16_t num_rep;
5712         int i, ret = 0;
5713         struct bnxt *backing_bp;
5714
5715         if (pci_dev->device.devargs) {
5716                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
5717                                             &eth_da);
5718                 if (ret)
5719                         return ret;
5720         }
5721
5722         num_rep = eth_da.nb_representor_ports;
5723         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
5724                     num_rep);
5725
5726         /* We could come here after first level of probe is already invoked
5727          * as part of an application bringup(OVS-DPDK vswitchd), so first check
5728          * for already allocated eth_dev for the backing device (PF/Trusted VF)
5729          */
5730         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5731         if (backing_eth_dev == NULL) {
5732                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
5733                                          sizeof(struct bnxt),
5734                                          eth_dev_pci_specific_init, pci_dev,
5735                                          bnxt_dev_init, NULL);
5736
5737                 if (ret || !num_rep)
5738                         return ret;
5739         }
5740
5741         if (num_rep > BNXT_MAX_VF_REPS) {
5742                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5743                             eth_da.nb_representor_ports, BNXT_MAX_VF_REPS);
5744                 ret = -EINVAL;
5745                 return ret;
5746         }
5747
5748         /* probe representor ports now */
5749         if (!backing_eth_dev)
5750                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5751         if (backing_eth_dev == NULL) {
5752                 ret = -ENODEV;
5753                 return ret;
5754         }
5755         backing_bp = backing_eth_dev->data->dev_private;
5756
5757         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5758                 PMD_DRV_LOG(ERR,
5759                             "Not a PF or trusted VF. No Representor support\n");
5760                 /* Returning an error is not an option.
5761                  * Applications are not handling this correctly
5762                  */
5763                 return ret;
5764         }
5765
5766         for (i = 0; i < eth_da.nb_representor_ports; i++) {
5767                 struct bnxt_vf_representor representor = {
5768                         .vf_id = eth_da.representor_ports[i],
5769                         .switch_domain_id = backing_bp->switch_domain_id,
5770                         .parent_priv = backing_bp
5771                 };
5772
5773                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5774                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5775                                     representor.vf_id, BNXT_MAX_VF_REPS);
5776                         continue;
5777                 }
5778
5779                 /* representor port net_bdf_port */
5780                 snprintf(name, sizeof(name), "net_%s_representor_%d",
5781                          pci_dev->device.name, eth_da.representor_ports[i]);
5782
5783                 ret = rte_eth_dev_create(&pci_dev->device, name,
5784                                          sizeof(struct bnxt_vf_representor),
5785                                          NULL, NULL,
5786                                          bnxt_vf_representor_init,
5787                                          &representor);
5788
5789                 if (!ret) {
5790                         vf_rep_eth_dev = rte_eth_dev_allocated(name);
5791                         if (!vf_rep_eth_dev) {
5792                                 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5793                                             " for VF-Rep: %s.", name);
5794                                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5795                                 ret = -ENODEV;
5796                                 return ret;
5797                         }
5798                         backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
5799                                 vf_rep_eth_dev;
5800                         backing_bp->num_reps++;
5801                 } else {
5802                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5803                                     "representor %s.", name);
5804                         bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5805                 }
5806         }
5807
5808         return ret;
5809 }
5810
5811 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5812 {
5813         struct rte_eth_dev *eth_dev;
5814
5815         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5816         if (!eth_dev)
5817                 return 0; /* Invoked typically only by OVS-DPDK, by the
5818                            * time it comes here the eth_dev is already
5819                            * deleted by rte_eth_dev_close(), so returning
5820                            * +ve value will at least help in proper cleanup
5821                            */
5822
5823         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
5824                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
5825                         return rte_eth_dev_destroy(eth_dev,
5826                                                    bnxt_vf_representor_uninit);
5827                 else
5828                         return rte_eth_dev_destroy(eth_dev,
5829                                                    bnxt_dev_uninit);
5830         } else {
5831                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5832         }
5833 }
5834
5835 static struct rte_pci_driver bnxt_rte_pmd = {
5836         .id_table = bnxt_pci_id_map,
5837         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
5838                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
5839                                                   * and OVS-DPDK
5840                                                   */
5841         .probe = bnxt_pci_probe,
5842         .remove = bnxt_pci_remove,
5843 };
5844
5845 static bool
5846 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5847 {
5848         if (strcmp(dev->device->driver->name, drv->driver.name))
5849                 return false;
5850
5851         return true;
5852 }
5853
5854 bool is_bnxt_supported(struct rte_eth_dev *dev)
5855 {
5856         return is_device_supported(dev, &bnxt_rte_pmd);
5857 }
5858
5859 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
5860 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5861 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5862 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");