drivers/net/bnxt/bnxt_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <inttypes.h>
  35 #include <stdbool.h>
  36
  37 #include <rte_dev.h>
  38 #include <rte_ethdev.h>
  39 #include <rte_ethdev_pci.h>
  40 #include <rte_malloc.h>
  41 #include <rte_cycles.h>
  42
  43 #include "bnxt.h"
  44 #include "bnxt_cpr.h"
  45 #include "bnxt_filter.h"
  46 #include "bnxt_hwrm.h"
  47 #include "bnxt_irq.h"
  48 #include "bnxt_ring.h"
  49 #include "bnxt_rxq.h"
  50 #include "bnxt_rxr.h"
  51 #include "bnxt_stats.h"
  52 #include "bnxt_txq.h"
  53 #include "bnxt_txr.h"
  54 #include "bnxt_vnic.h"
  55 #include "hsi_struct_def_dpdk.h"
  56 #include "bnxt_nvm_defs.h"
  57
  58 #define DRV_MODULE_NAME         "bnxt"
  59 static const char bnxt_version[] =
  60         "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
  61
  62 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  63
  64 #define BROADCOM_DEV_ID_STRATUS_NIC_VF 0x1609
  65 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  66 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  67 #define BROADCOM_DEV_ID_57301 0x16c8
  68 #define BROADCOM_DEV_ID_57302 0x16c9
  69 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  70 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  71 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  72 #define BROADCOM_DEV_ID_NS2 0x16cd
  73 #define BROADCOM_DEV_ID_57311 0x16ce
  74 #define BROADCOM_DEV_ID_57312 0x16cf
  75 #define BROADCOM_DEV_ID_57402 0x16d0
  76 #define BROADCOM_DEV_ID_57404 0x16d1
  77 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  78 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  79 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  80 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  81 #define BROADCOM_DEV_ID_57412 0x16d6
  82 #define BROADCOM_DEV_ID_57414 0x16d7
  83 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  84 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  85 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  86 #define BROADCOM_DEV_ID_57412_MF 0x16de
  87 #define BROADCOM_DEV_ID_57314 0x16df
  88 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  89 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  90 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  91 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  92 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  93 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  94 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  95 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  96 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  97 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  98 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  99
 100 static const struct rte_pci_id bnxt_pci_id_map[] = {
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
 102                          BROADCOM_DEV_ID_STRATUS_NIC_VF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 130         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 131         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 132         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 133         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 134         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 135         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 136         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 137         { .vendor_id = 0, /* sentinel */ },
 138 };
 139
 140 #define BNXT_ETH_RSS_SUPPORT (  \
 141         ETH_RSS_IPV4 |          \
 142         ETH_RSS_NONFRAG_IPV4_TCP |      \
 143         ETH_RSS_NONFRAG_IPV4_UDP |      \
 144         ETH_RSS_IPV6 |          \
 145         ETH_RSS_NONFRAG_IPV6_TCP |      \
 146         ETH_RSS_NONFRAG_IPV6_UDP)
 147
 148 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 149 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 150
 151 /***********************/
 152
 153 /*
 154  * High level utility functions
 155  */
 156
 157 static void bnxt_free_mem(struct bnxt *bp)
 158 {
 159         bnxt_free_filter_mem(bp);
 160         bnxt_free_vnic_attributes(bp);
 161         bnxt_free_vnic_mem(bp);
 162
 163         bnxt_free_stats(bp);
 164         bnxt_free_tx_rings(bp);
 165         bnxt_free_rx_rings(bp);
 166         bnxt_free_def_cp_ring(bp);
 167 }
 168
 169 static int bnxt_alloc_mem(struct bnxt *bp)
 170 {
 171         int rc;
 172
 173         /* Default completion ring */
 174         rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
 175         if (rc)
 176                 goto alloc_mem_err;
 177
 178         rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
 179                               bp->def_cp_ring, "def_cp");
 180         if (rc)
 181                 goto alloc_mem_err;
 182
 183         rc = bnxt_alloc_vnic_mem(bp);
 184         if (rc)
 185                 goto alloc_mem_err;
 186
 187         rc = bnxt_alloc_vnic_attributes(bp);
 188         if (rc)
 189                 goto alloc_mem_err;
 190
 191         rc = bnxt_alloc_filter_mem(bp);
 192         if (rc)
 193                 goto alloc_mem_err;
 194
 195         return 0;
 196
 197 alloc_mem_err:
 198         bnxt_free_mem(bp);
 199         return rc;
 200 }
 201
 202 static int bnxt_init_chip(struct bnxt *bp)
 203 {
 204         unsigned int i, rss_idx, fw_idx;
 205         struct rte_eth_link new;
 206         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 207         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 208         uint32_t intr_vector = 0;
 209         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 210         uint32_t vec = BNXT_MISC_VEC_ID;
 211         int rc;
 212
 213         /* disable uio/vfio intr/eventfd mapping */
 214         rte_intr_disable(intr_handle);
 215
 216         if (bp->eth_dev->data->mtu > ETHER_MTU) {
 217                 bp->eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
 218                 bp->flags |= BNXT_FLAG_JUMBO;
 219         } else {
 220                 bp->eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
 221                 bp->flags &= ~BNXT_FLAG_JUMBO;
 222         }
 223
 224         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 225         if (rc) {
 226                 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
 227                 goto err_out;
 228         }
 229
 230         rc = bnxt_alloc_hwrm_rings(bp);
 231         if (rc) {
 232                 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
 233                 goto err_out;
 234         }
 235
 236         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 237         if (rc) {
 238                 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
 239                 goto err_out;
 240         }
 241
 242         rc = bnxt_mq_rx_configure(bp);
 243         if (rc) {
 244                 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
 245                 goto err_out;
 246         }
 247
 248         /* VNIC configuration */
 249         for (i = 0; i < bp->nr_vnics; i++) {
 250                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 251
 252                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 253                 if (rc) {
 254                         RTE_LOG(ERR, PMD, "HWRM vnic %d alloc failure rc: %x\n",
 255                                 i, rc);
 256                         goto err_out;
 257                 }
 258
 259                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
 260                 if (rc) {
 261                         RTE_LOG(ERR, PMD,
 262                                 "HWRM vnic %d ctx alloc failure rc: %x\n",
 263                                 i, rc);
 264                         goto err_out;
 265                 }
 266
 267                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 268                 if (rc) {
 269                         RTE_LOG(ERR, PMD, "HWRM vnic %d cfg failure rc: %x\n",
 270                                 i, rc);
 271                         goto err_out;
 272                 }
 273
 274                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 275                 if (rc) {
 276                         RTE_LOG(ERR, PMD,
 277                                 "HWRM vnic %d filter failure rc: %x\n",
 278                                 i, rc);
 279                         goto err_out;
 280                 }
 281                 if (vnic->rss_table && vnic->hash_type) {
 282                         /*
 283                          * Fill the RSS hash & redirection table with
 284                          * ring group ids for all VNICs
 285                          */
 286                         for (rss_idx = 0, fw_idx = 0;
 287                              rss_idx < HW_HASH_INDEX_SIZE;
 288                              rss_idx++, fw_idx++) {
 289                                 if (vnic->fw_grp_ids[fw_idx] ==
 290                                     INVALID_HW_RING_ID)
 291                                         fw_idx = 0;
 292                                 vnic->rss_table[rss_idx] =
 293                                                 vnic->fw_grp_ids[fw_idx];
 294                         }
 295                         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 296                         if (rc) {
 297                                 RTE_LOG(ERR, PMD,
 298                                         "HWRM vnic %d set RSS failure rc: %x\n",
 299                                         i, rc);
 300                                 goto err_out;
 301                         }
 302                 }
 303
 304                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 305
 306                 if (bp->eth_dev->data->dev_conf.rxmode.enable_lro)
 307                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 308                 else
 309                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 310         }
 311         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 312         if (rc) {
 313                 RTE_LOG(ERR, PMD,
 314                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 315                 goto err_out;
 316         }
 317
 318         /* check and configure queue intr-vector mapping */
 319         if ((rte_intr_cap_multiple(intr_handle) ||
 320              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 321             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 322                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 323                 RTE_LOG(INFO, PMD, "%s(): intr_vector = %d\n", __func__,
 324                         intr_vector);
 325                 if (intr_vector > bp->rx_cp_nr_rings) {
 326                         RTE_LOG(ERR, PMD, "At most %d intr queues supported",
 327                                         bp->rx_cp_nr_rings);
 328                         return -ENOTSUP;
 329                 }
 330                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 331                         return -1;
 332         }
 333
 334         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 335                 intr_handle->intr_vec =
 336                         rte_zmalloc("intr_vec",
 337                                     bp->eth_dev->data->nb_rx_queues *
 338                                     sizeof(int), 0);
 339                 if (intr_handle->intr_vec == NULL) {
 340                         RTE_LOG(ERR, PMD, "Failed to allocate %d rx_queues"
 341                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 342                         return -ENOMEM;
 343                 }
 344                 RTE_LOG(DEBUG, PMD, "%s(): intr_handle->intr_vec = %p "
 345                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 346                          __func__, intr_handle->intr_vec, intr_handle->nb_efd,
 347                         intr_handle->max_intr);
 348         }
 349
 350         for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 351              queue_id++) {
 352                 intr_handle->intr_vec[queue_id] = vec;
 353                 if (vec < base + intr_handle->nb_efd - 1)
 354                         vec++;
 355         }
 356
 357         /* enable uio/vfio intr/eventfd mapping */
 358         rte_intr_enable(intr_handle);
 359
 360         rc = bnxt_get_hwrm_link_config(bp, &new);
 361         if (rc) {
 362                 RTE_LOG(ERR, PMD, "HWRM Get link config failure rc: %x\n", rc);
 363                 goto err_out;
 364         }
 365
 366         if (!bp->link_info.link_up) {
 367                 rc = bnxt_set_hwrm_link_config(bp, true);
 368                 if (rc) {
 369                         RTE_LOG(ERR, PMD,
 370                                 "HWRM link config failure rc: %x\n", rc);
 371                         goto err_out;
 372                 }
 373         }
 374         bnxt_print_link_info(bp->eth_dev);
 375
 376         return 0;
 377
 378 err_out:
 379         bnxt_free_all_hwrm_resources(bp);
 380
 381         /* Some of the error status returned by FW may not be from errno.h */
 382         if (rc > 0)
 383                 rc = -EIO;
 384
 385         return rc;
 386 }
 387
 388 static int bnxt_shutdown_nic(struct bnxt *bp)
 389 {
 390         bnxt_free_all_hwrm_resources(bp);
 391         bnxt_free_all_filters(bp);
 392         bnxt_free_all_vnics(bp);
 393         return 0;
 394 }
 395
 396 static int bnxt_init_nic(struct bnxt *bp)
 397 {
 398         int rc;
 399
 400         rc = bnxt_init_ring_grps(bp);
 401         if (rc)
 402                 return rc;
 403
 404         bnxt_init_vnics(bp);
 405         bnxt_init_filters(bp);
 406
 407         rc = bnxt_init_chip(bp);
 408         if (rc)
 409                 return rc;
 410
 411         return 0;
 412 }
 413
 414 /*
 415  * Device configuration and status function
 416  */
 417
 418 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 419                                   struct rte_eth_dev_info *dev_info)
 420 {
 421         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 422         uint16_t max_vnics, i, j, vpool, vrxq;
 423         unsigned int max_rx_rings;
 424
 425         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 426
 427         /* MAC Specifics */
 428         dev_info->max_mac_addrs = bp->max_l2_ctx;
 429         dev_info->max_hash_mac_addrs = 0;
 430
 431         /* PF/VF specifics */
 432         if (BNXT_PF(bp))
 433                 dev_info->max_vfs = bp->pdev->max_vfs;
 434         max_rx_rings = RTE_MIN(bp->max_vnics, RTE_MIN(bp->max_l2_ctx,
 435                                                 RTE_MIN(bp->max_rsscos_ctx,
 436                                                 bp->max_stat_ctx)));
 437         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 438         dev_info->max_rx_queues = max_rx_rings;
 439         dev_info->max_tx_queues = max_rx_rings;
 440         dev_info->reta_size = bp->max_rsscos_ctx;
 441         dev_info->hash_key_size = 40;
 442         max_vnics = bp->max_vnics;
 443
 444         /* Fast path specifics */
 445         dev_info->min_rx_bufsize = 1;
 446         dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
 447                                   + VLAN_TAG_SIZE;
 448         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
 449                                         DEV_RX_OFFLOAD_IPV4_CKSUM |
 450                                         DEV_RX_OFFLOAD_UDP_CKSUM |
 451                                         DEV_RX_OFFLOAD_TCP_CKSUM |
 452                                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
 453         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
 454                                         DEV_TX_OFFLOAD_IPV4_CKSUM |
 455                                         DEV_TX_OFFLOAD_TCP_CKSUM |
 456                                         DEV_TX_OFFLOAD_UDP_CKSUM |
 457                                         DEV_TX_OFFLOAD_TCP_TSO |
 458                                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 459                                         DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 460                                         DEV_TX_OFFLOAD_GRE_TNL_TSO |
 461                                         DEV_TX_OFFLOAD_IPIP_TNL_TSO |
 462                                         DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
 463
 464         /* *INDENT-OFF* */
 465         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 466                 .rx_thresh = {
 467                         .pthresh = 8,
 468                         .hthresh = 8,
 469                         .wthresh = 0,
 470                 },
 471                 .rx_free_thresh = 32,
 472                 .rx_drop_en = 0,
 473         };
 474
 475         dev_info->default_txconf = (struct rte_eth_txconf) {
 476                 .tx_thresh = {
 477                         .pthresh = 32,
 478                         .hthresh = 0,
 479                         .wthresh = 0,
 480                 },
 481                 .tx_free_thresh = 32,
 482                 .tx_rs_thresh = 32,
 483                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
 484                              ETH_TXQ_FLAGS_NOOFFLOADS,
 485         };
 486         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 487
 488         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 489
 490         /* *INDENT-ON* */
 491
 492         /*
 493          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 494          *       need further investigation.
 495          */
 496
 497         /* VMDq resources */
 498         vpool = 64; /* ETH_64_POOLS */
 499         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 500         for (i = 0; i < 4; vpool >>= 1, i++) {
 501                 if (max_vnics > vpool) {
 502                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 503                                 if (dev_info->max_rx_queues > vrxq) {
 504                                         if (vpool > vrxq)
 505                                                 vpool = vrxq;
 506                                         goto found;
 507                                 }
 508                         }
 509                         /* Not enough resources to support VMDq */
 510                         break;
 511                 }
 512         }
 513         /* Not enough resources to support VMDq */
 514         vpool = 0;
 515         vrxq = 0;
 516 found:
 517         dev_info->max_vmdq_pools = vpool;
 518         dev_info->vmdq_queue_num = vrxq;
 519
 520         dev_info->vmdq_pool_base = 0;
 521         dev_info->vmdq_queue_base = 0;
 522 }
 523
 524 /* Configure the device based on the configuration provided */
 525 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 526 {
 527         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 528
 529         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 530         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 531
 532         /* Inherit new configurations */
 533         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 534             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 535             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues + 1 >
 536             bp->max_cp_rings ||
 537             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 538             bp->max_stat_ctx ||
 539             (uint32_t)(eth_dev->data->nb_rx_queues + 1) > bp->max_ring_grps) {
 540                 RTE_LOG(ERR, PMD,
 541                         "Insufficient resources to support requested config\n");
 542                 RTE_LOG(ERR, PMD,
 543                         "Num Queues Requested: Tx %d, Rx %d\n",
 544                         eth_dev->data->nb_tx_queues,
 545                         eth_dev->data->nb_rx_queues);
 546                 RTE_LOG(ERR, PMD,
 547                         "Res available: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d\n",
 548                         bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 549                         bp->max_stat_ctx, bp->max_ring_grps);
 550                 return -ENOSPC;
 551         }
 552
 553         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 554         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 555         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 556         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 557
 558         if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
 559                 eth_dev->data->mtu =
 560                                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 561                                 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
 562         return 0;
 563 }
 564
 565 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 566 {
 567         struct rte_eth_link *link = &eth_dev->data->dev_link;
 568
 569         if (link->link_status)
 570                 RTE_LOG(INFO, PMD, "Port %d Link Up - speed %u Mbps - %s\n",
 571                         eth_dev->data->port_id,
 572                         (uint32_t)link->link_speed,
 573                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 574                         ("full-duplex") : ("half-duplex\n"));
 575         else
 576                 RTE_LOG(INFO, PMD, "Port %d Link Down\n",
 577                         eth_dev->data->port_id);
 578 }
 579
 580 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
 581 {
 582         bnxt_print_link_info(eth_dev);
 583         return 0;
 584 }
 585
 586 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 587 {
 588         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 589         int vlan_mask = 0;
 590         int rc;
 591
 592         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 593                 RTE_LOG(ERR, PMD,
 594                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 595                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 596         }
 597         bp->dev_stopped = 0;
 598
 599         rc = bnxt_init_nic(bp);
 600         if (rc)
 601                 goto error;
 602
 603         bnxt_link_update_op(eth_dev, 1);
 604
 605         if (eth_dev->data->dev_conf.rxmode.hw_vlan_filter)
 606                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 607         if (eth_dev->data->dev_conf.rxmode.hw_vlan_strip)
 608                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 609         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 610         if (rc)
 611                 goto error;
 612
 613         bp->flags |= BNXT_FLAG_INIT_DONE;
 614         return 0;
 615
 616 error:
 617         bnxt_shutdown_nic(bp);
 618         bnxt_free_tx_mbufs(bp);
 619         bnxt_free_rx_mbufs(bp);
 620         return rc;
 621 }
 622
 623 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 624 {
 625         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 626         int rc = 0;
 627
 628         if (!bp->link_info.link_up)
 629                 rc = bnxt_set_hwrm_link_config(bp, true);
 630         if (!rc)
 631                 eth_dev->data->dev_link.link_status = 1;
 632
 633         bnxt_print_link_info(eth_dev);
 634         return 0;
 635 }
 636
 637 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 638 {
 639         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 640
 641         eth_dev->data->dev_link.link_status = 0;
 642         bnxt_set_hwrm_link_config(bp, false);
 643         bp->link_info.link_up = 0;
 644
 645         return 0;
 646 }
 647
 648 /* Unload the driver, release resources */
 649 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 650 {
 651         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 652
 653         if (bp->eth_dev->data->dev_started) {
 654                 /* TBD: STOP HW queues DMA */
 655                 eth_dev->data->dev_link.link_status = 0;
 656         }
 657         bnxt_set_hwrm_link_config(bp, false);
 658         bnxt_hwrm_port_clr_stats(bp);
 659         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 660         bnxt_shutdown_nic(bp);
 661         bp->dev_stopped = 1;
 662 }
 663
 664 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 665 {
 666         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 667
 668         if (bp->dev_stopped == 0)
 669                 bnxt_dev_stop_op(eth_dev);
 670
 671         bnxt_free_tx_mbufs(bp);
 672         bnxt_free_rx_mbufs(bp);
 673         bnxt_free_mem(bp);
 674         if (eth_dev->data->mac_addrs != NULL) {
 675                 rte_free(eth_dev->data->mac_addrs);
 676                 eth_dev->data->mac_addrs = NULL;
 677         }
 678         if (bp->grp_info != NULL) {
 679                 rte_free(bp->grp_info);
 680                 bp->grp_info = NULL;
 681         }
 682 }
 683
 684 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 685                                     uint32_t index)
 686 {
 687         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 688         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 689         struct bnxt_vnic_info *vnic;
 690         struct bnxt_filter_info *filter, *temp_filter;
 691         uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS);
 692         uint32_t i;
 693
 694         /*
 695          * Loop through all VNICs from the specified filter flow pools to
 696          * remove the corresponding MAC addr filter
 697          */
 698         for (i = 0; i < pool; i++) {
 699                 if (!(pool_mask & (1ULL << i)))
 700                         continue;
 701
 702                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 703                         filter = STAILQ_FIRST(&vnic->filter);
 704                         while (filter) {
 705                                 temp_filter = STAILQ_NEXT(filter, next);
 706                                 if (filter->mac_index == index) {
 707                                         STAILQ_REMOVE(&vnic->filter, filter,
 708                                                       bnxt_filter_info, next);
 709                                         bnxt_hwrm_clear_l2_filter(bp, filter);
 710                                         filter->mac_index = INVALID_MAC_INDEX;
 711                                         memset(&filter->l2_addr, 0,
 712                                                ETHER_ADDR_LEN);
 713                                         STAILQ_INSERT_TAIL(
 714                                                         &bp->free_filter_list,
 715                                                         filter, next);
 716                                 }
 717                                 filter = temp_filter;
 718                         }
 719                 }
 720         }
 721 }
 722
 723 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 724                                 struct ether_addr *mac_addr,
 725                                 uint32_t index, uint32_t pool)
 726 {
 727         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 728         struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
 729         struct bnxt_filter_info *filter;
 730
 731         if (BNXT_VF(bp)) {
 732                 RTE_LOG(ERR, PMD, "Cannot add MAC address to a VF interface\n");
 733                 return -ENOTSUP;
 734         }
 735
 736         if (!vnic) {
 737                 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
 738                 return -EINVAL;
 739         }
 740         /* Attach requested MAC address to the new l2_filter */
 741         STAILQ_FOREACH(filter, &vnic->filter, next) {
 742                 if (filter->mac_index == index) {
 743                         RTE_LOG(ERR, PMD,
 744                                 "MAC addr already existed for pool %d\n", pool);
 745                         return -EINVAL;
 746                 }
 747         }
 748         filter = bnxt_alloc_filter(bp);
 749         if (!filter) {
 750                 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
 751                 return -ENODEV;
 752         }
 753         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 754         filter->mac_index = index;
 755         memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
 756         return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 757 }
 758
 759 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 760 {
 761         int rc = 0;
 762         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 763         struct rte_eth_link new;
 764         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 765
 766         memset(&new, 0, sizeof(new));
 767         do {
 768                 /* Retrieve link info from hardware */
 769                 rc = bnxt_get_hwrm_link_config(bp, &new);
 770                 if (rc) {
 771                         new.link_speed = ETH_LINK_SPEED_100M;
 772                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 773                         RTE_LOG(ERR, PMD,
 774                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 775                         goto out;
 776                 }
 777                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 778
 779                 if (!wait_to_complete)
 780                         break;
 781         } while (!new.link_status && cnt--);
 782
 783 out:
 784         /* Timed out or success */
 785         if (new.link_status != eth_dev->data->dev_link.link_status ||
 786         new.link_speed != eth_dev->data->dev_link.link_speed) {
 787                 memcpy(&eth_dev->data->dev_link, &new,
 788                         sizeof(struct rte_eth_link));
 789                 bnxt_print_link_info(eth_dev);
 790         }
 791
 792         return rc;
 793 }
 794
 795 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
 796 {
 797         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 798         struct bnxt_vnic_info *vnic;
 799
 800         if (bp->vnic_info == NULL)
 801                 return;
 802
 803         vnic = &bp->vnic_info[0];
 804
 805         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
 806         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 807 }
 808
 809 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
 810 {
 811         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 812         struct bnxt_vnic_info *vnic;
 813
 814         if (bp->vnic_info == NULL)
 815                 return;
 816
 817         vnic = &bp->vnic_info[0];
 818
 819         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
 820         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 821 }
 822
 823 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
 824 {
 825         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 826         struct bnxt_vnic_info *vnic;
 827
 828         if (bp->vnic_info == NULL)
 829                 return;
 830
 831         vnic = &bp->vnic_info[0];
 832
 833         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
 834         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 835 }
 836
 837 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
 838 {
 839         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 840         struct bnxt_vnic_info *vnic;
 841
 842         if (bp->vnic_info == NULL)
 843                 return;
 844
 845         vnic = &bp->vnic_info[0];
 846
 847         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
 848         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 849 }
 850
 851 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
 852                             struct rte_eth_rss_reta_entry64 *reta_conf,
 853                             uint16_t reta_size)
 854 {
 855         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 856         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 857         struct bnxt_vnic_info *vnic;
 858         int i;
 859
 860         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
 861                 return -EINVAL;
 862
 863         if (reta_size != HW_HASH_INDEX_SIZE) {
 864                 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
 865                         "(%d) must equal the size supported by the hardware "
 866                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 867                 return -EINVAL;
 868         }
 869         /* Update the RSS VNIC(s) */
 870         for (i = 0; i < MAX_FF_POOLS; i++) {
 871                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 872                         memcpy(vnic->rss_table, reta_conf, reta_size);
 873
 874                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 875                 }
 876         }
 877         return 0;
 878 }
 879
 880 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
 881                               struct rte_eth_rss_reta_entry64 *reta_conf,
 882                               uint16_t reta_size)
 883 {
 884         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 885         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 886         struct rte_intr_handle *intr_handle
 887                 = &bp->pdev->intr_handle;
 888
 889         /* Retrieve from the default VNIC */
 890         if (!vnic)
 891                 return -EINVAL;
 892         if (!vnic->rss_table)
 893                 return -EINVAL;
 894
 895         if (reta_size != HW_HASH_INDEX_SIZE) {
 896                 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
 897                         "(%d) must equal the size supported by the hardware "
 898                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 899                 return -EINVAL;
 900         }
 901         /* EW - need to revisit here copying from uint64_t to uint16_t */
 902         memcpy(reta_conf, vnic->rss_table, reta_size);
 903
 904         if (rte_intr_allow_others(intr_handle)) {
 905                 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
 906                         bnxt_dev_lsc_intr_setup(eth_dev);
 907         }
 908
 909         return 0;
 910 }
 911
 912 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
 913                                    struct rte_eth_rss_conf *rss_conf)
 914 {
 915         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 916         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 917         struct bnxt_vnic_info *vnic;
 918         uint16_t hash_type = 0;
 919         int i;
 920
 921         /*
 922          * If RSS enablement were different than dev_configure,
 923          * then return -EINVAL
 924          */
 925         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
 926                 if (!rss_conf->rss_hf)
 927                         RTE_LOG(ERR, PMD, "Hash type NONE\n");
 928         } else {
 929                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
 930                         return -EINVAL;
 931         }
 932
 933         bp->flags |= BNXT_FLAG_UPDATE_HASH;
 934         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
 935
 936         if (rss_conf->rss_hf & ETH_RSS_IPV4)
 937                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 938         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
 939                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 940         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
 941                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
 942         if (rss_conf->rss_hf & ETH_RSS_IPV6)
 943                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
 944         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
 945                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
 946         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
 947                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
 948
 949         /* Update the RSS VNIC(s) */
 950         for (i = 0; i < MAX_FF_POOLS; i++) {
 951                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 952                         vnic->hash_type = hash_type;
 953
 954                         /*
 955                          * Use the supplied key if the key length is
 956                          * acceptable and the rss_key is not NULL
 957                          */
 958                         if (rss_conf->rss_key &&
 959                             rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
 960                                 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
 961                                        rss_conf->rss_key_len);
 962
 963                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 964                 }
 965         }
 966         return 0;
 967 }
 968
 969 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
 970                                      struct rte_eth_rss_conf *rss_conf)
 971 {
 972         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 973         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 974         int len;
 975         uint32_t hash_types;
 976
 977         /* RSS configuration is the same for all VNICs */
 978         if (vnic && vnic->rss_hash_key) {
 979                 if (rss_conf->rss_key) {
 980                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
 981                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
 982                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
 983                 }
 984
 985                 hash_types = vnic->hash_type;
 986                 rss_conf->rss_hf = 0;
 987                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
 988                         rss_conf->rss_hf |= ETH_RSS_IPV4;
 989                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 990                 }
 991                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
 992                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
 993                         hash_types &=
 994                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 995                 }
 996                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
 997                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
 998                         hash_types &=
 999                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1000                 }
1001                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1002                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1003                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1004                 }
1005                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1006                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1007                         hash_types &=
1008                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1009                 }
1010                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1011                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1012                         hash_types &=
1013                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1014                 }
1015                 if (hash_types) {
1016                         RTE_LOG(ERR, PMD,
1017                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1018                                 vnic->hash_type);
1019                         return -ENOTSUP;
1020                 }
1021         } else {
1022                 rss_conf->rss_hf = 0;
1023         }
1024         return 0;
1025 }
1026
1027 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1028                                struct rte_eth_fc_conf *fc_conf)
1029 {
1030         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1031         struct rte_eth_link link_info;
1032         int rc;
1033
1034         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1035         if (rc)
1036                 return rc;
1037
1038         memset(fc_conf, 0, sizeof(*fc_conf));
1039         if (bp->link_info.auto_pause)
1040                 fc_conf->autoneg = 1;
1041         switch (bp->link_info.pause) {
1042         case 0:
1043                 fc_conf->mode = RTE_FC_NONE;
1044                 break;
1045         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1046                 fc_conf->mode = RTE_FC_TX_PAUSE;
1047                 break;
1048         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1049                 fc_conf->mode = RTE_FC_RX_PAUSE;
1050                 break;
1051         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1052                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1053                 fc_conf->mode = RTE_FC_FULL;
1054                 break;
1055         }
1056         return 0;
1057 }
1058
1059 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1060                                struct rte_eth_fc_conf *fc_conf)
1061 {
1062         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1063
1064         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1065                 RTE_LOG(ERR, PMD, "Flow Control Settings cannot be modified\n");
1066                 return -ENOTSUP;
1067         }
1068
1069         switch (fc_conf->mode) {
1070         case RTE_FC_NONE:
1071                 bp->link_info.auto_pause = 0;
1072                 bp->link_info.force_pause = 0;
1073                 break;
1074         case RTE_FC_RX_PAUSE:
1075                 if (fc_conf->autoneg) {
1076                         bp->link_info.auto_pause =
1077                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1078                         bp->link_info.force_pause = 0;
1079                 } else {
1080                         bp->link_info.auto_pause = 0;
1081                         bp->link_info.force_pause =
1082                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1083                 }
1084                 break;
1085         case RTE_FC_TX_PAUSE:
1086                 if (fc_conf->autoneg) {
1087                         bp->link_info.auto_pause =
1088                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1089                         bp->link_info.force_pause = 0;
1090                 } else {
1091                         bp->link_info.auto_pause = 0;
1092                         bp->link_info.force_pause =
1093                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1094                 }
1095                 break;
1096         case RTE_FC_FULL:
1097                 if (fc_conf->autoneg) {
1098                         bp->link_info.auto_pause =
1099                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1100                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1101                         bp->link_info.force_pause = 0;
1102                 } else {
1103                         bp->link_info.auto_pause = 0;
1104                         bp->link_info.force_pause =
1105                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1106                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1107                 }
1108                 break;
1109         }
1110         return bnxt_set_hwrm_link_config(bp, true);
1111 }
1112
1113 /* Add UDP tunneling port */
1114 static int
1115 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1116                          struct rte_eth_udp_tunnel *udp_tunnel)
1117 {
1118         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1119         uint16_t tunnel_type = 0;
1120         int rc = 0;
1121
1122         switch (udp_tunnel->prot_type) {
1123         case RTE_TUNNEL_TYPE_VXLAN:
1124                 if (bp->vxlan_port_cnt) {
1125                         RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n",
1126                                 udp_tunnel->udp_port);
1127                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1128                                 RTE_LOG(ERR, PMD, "Only one port allowed\n");
1129                                 return -ENOSPC;
1130                         }
1131                         bp->vxlan_port_cnt++;
1132                         return 0;
1133                 }
1134                 tunnel_type =
1135                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1136                 bp->vxlan_port_cnt++;
1137                 break;
1138         case RTE_TUNNEL_TYPE_GENEVE:
1139                 if (bp->geneve_port_cnt) {
1140                         RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n",
1141                                 udp_tunnel->udp_port);
1142                         if (bp->geneve_port != udp_tunnel->udp_port) {
1143                                 RTE_LOG(ERR, PMD, "Only one port allowed\n");
1144                                 return -ENOSPC;
1145                         }
1146                         bp->geneve_port_cnt++;
1147                         return 0;
1148                 }
1149                 tunnel_type =
1150                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1151                 bp->geneve_port_cnt++;
1152                 break;
1153         default:
1154                 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n");
1155                 return -ENOTSUP;
1156         }
1157         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1158                                              tunnel_type);
1159         return rc;
1160 }
1161
1162 static int
1163 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1164                          struct rte_eth_udp_tunnel *udp_tunnel)
1165 {
1166         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1167         uint16_t tunnel_type = 0;
1168         uint16_t port = 0;
1169         int rc = 0;
1170
1171         switch (udp_tunnel->prot_type) {
1172         case RTE_TUNNEL_TYPE_VXLAN:
1173                 if (!bp->vxlan_port_cnt) {
1174                         RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n");
1175                         return -EINVAL;
1176                 }
1177                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1178                         RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n",
1179                                 udp_tunnel->udp_port, bp->vxlan_port);
1180                         return -EINVAL;
1181                 }
1182                 if (--bp->vxlan_port_cnt)
1183                         return 0;
1184
1185                 tunnel_type =
1186                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1187                 port = bp->vxlan_fw_dst_port_id;
1188                 break;
1189         case RTE_TUNNEL_TYPE_GENEVE:
1190                 if (!bp->geneve_port_cnt) {
1191                         RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n");
1192                         return -EINVAL;
1193                 }
1194                 if (bp->geneve_port != udp_tunnel->udp_port) {
1195                         RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n",
1196                                 udp_tunnel->udp_port, bp->geneve_port);
1197                         return -EINVAL;
1198                 }
1199                 if (--bp->geneve_port_cnt)
1200                         return 0;
1201
1202                 tunnel_type =
1203                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1204                 port = bp->geneve_fw_dst_port_id;
1205                 break;
1206         default:
1207                 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n");
1208                 return -ENOTSUP;
1209         }
1210
1211         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1212         if (!rc) {
1213                 if (tunnel_type ==
1214                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1215                         bp->vxlan_port = 0;
1216                 if (tunnel_type ==
1217                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1218                         bp->geneve_port = 0;
1219         }
1220         return rc;
1221 }
1222
1223 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1224 {
1225         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1226         struct bnxt_vnic_info *vnic;
1227         unsigned int i;
1228         int rc = 0;
1229         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1230
1231         /* Cycle through all VNICs */
1232         for (i = 0; i < bp->nr_vnics; i++) {
1233                 /*
1234                  * For each VNIC and each associated filter(s)
1235                  * if VLAN exists && VLAN matches vlan_id
1236                  *      remove the MAC+VLAN filter
1237                  *      add a new MAC only filter
1238                  * else
1239                  *      VLAN filter doesn't exist, just skip and continue
1240                  */
1241                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1242                         filter = STAILQ_FIRST(&vnic->filter);
1243                         while (filter) {
1244                                 temp_filter = STAILQ_NEXT(filter, next);
1245
1246                                 if (filter->enables & chk &&
1247                                     filter->l2_ovlan == vlan_id) {
1248                                         /* Must delete the filter */
1249                                         STAILQ_REMOVE(&vnic->filter, filter,
1250                                                       bnxt_filter_info, next);
1251                                         bnxt_hwrm_clear_l2_filter(bp, filter);
1252                                         STAILQ_INSERT_TAIL(
1253                                                         &bp->free_filter_list,
1254                                                         filter, next);
1255
1256                                         /*
1257                                          * Need to examine to see if the MAC
1258                                          * filter already existed or not before
1259                                          * allocating a new one
1260                                          */
1261
1262                                         new_filter = bnxt_alloc_filter(bp);
1263                                         if (!new_filter) {
1264                                                 RTE_LOG(ERR, PMD,
1265                                                         "MAC/VLAN filter alloc failed\n");
1266                                                 rc = -ENOMEM;
1267                                                 goto exit;
1268                                         }
1269                                         STAILQ_INSERT_TAIL(&vnic->filter,
1270                                                            new_filter, next);
1271                                         /* Inherit MAC from previous filter */
1272                                         new_filter->mac_index =
1273                                                         filter->mac_index;
1274                                         memcpy(new_filter->l2_addr,
1275                                                filter->l2_addr, ETHER_ADDR_LEN);
1276                                         /* MAC only filter */
1277                                         rc = bnxt_hwrm_set_l2_filter(bp,
1278                                                         vnic->fw_vnic_id,
1279                                                         new_filter);
1280                                         if (rc)
1281                                                 goto exit;
1282                                         RTE_LOG(INFO, PMD,
1283                                                 "Del Vlan filter for %d\n",
1284                                                 vlan_id);
1285                                 }
1286                                 filter = temp_filter;
1287                         }
1288                 }
1289         }
1290 exit:
1291         return rc;
1292 }
1293
1294 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1295 {
1296         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1297         struct bnxt_vnic_info *vnic;
1298         unsigned int i;
1299         int rc = 0;
1300         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1301                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1302         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1303
1304         /* Cycle through all VNICs */
1305         for (i = 0; i < bp->nr_vnics; i++) {
1306                 /*
1307                  * For each VNIC and each associated filter(s)
1308                  * if VLAN exists:
1309                  *   if VLAN matches vlan_id
1310                  *      VLAN filter already exists, just skip and continue
1311                  *   else
1312                  *      add a new MAC+VLAN filter
1313                  * else
1314                  *   Remove the old MAC only filter
1315                  *    Add a new MAC+VLAN filter
1316                  */
1317                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1318                         filter = STAILQ_FIRST(&vnic->filter);
1319                         while (filter) {
1320                                 temp_filter = STAILQ_NEXT(filter, next);
1321
1322                                 if (filter->enables & chk) {
1323                                         if (filter->l2_ovlan == vlan_id)
1324                                                 goto cont;
1325                                 } else {
1326                                         /* Must delete the MAC filter */
1327                                         STAILQ_REMOVE(&vnic->filter, filter,
1328                                                       bnxt_filter_info, next);
1329                                         bnxt_hwrm_clear_l2_filter(bp, filter);
1330                                         filter->l2_ovlan = 0;
1331                                         STAILQ_INSERT_TAIL(
1332                                                         &bp->free_filter_list,
1333                                                         filter, next);
1334                                 }
1335                                 new_filter = bnxt_alloc_filter(bp);
1336                                 if (!new_filter) {
1337                                         RTE_LOG(ERR, PMD,
1338                                                 "MAC/VLAN filter alloc failed\n");
1339                                         rc = -ENOMEM;
1340                                         goto exit;
1341                                 }
1342                                 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1343                                                    next);
1344                                 /* Inherit MAC from the previous filter */
1345                                 new_filter->mac_index = filter->mac_index;
1346                                 memcpy(new_filter->l2_addr, filter->l2_addr,
1347                                        ETHER_ADDR_LEN);
1348                                 /* MAC + VLAN ID filter */
1349                                 new_filter->l2_ovlan = vlan_id;
1350                                 new_filter->l2_ovlan_mask = 0xF000;
1351                                 new_filter->enables |= en;
1352                                 rc = bnxt_hwrm_set_l2_filter(bp,
1353                                                              vnic->fw_vnic_id,
1354                                                              new_filter);
1355                                 if (rc)
1356                                         goto exit;
1357                                 RTE_LOG(INFO, PMD,
1358                                         "Added Vlan filter for %d\n", vlan_id);
1359 cont:
1360                                 filter = temp_filter;
1361                         }
1362                 }
1363         }
1364 exit:
1365         return rc;
1366 }
1367
1368 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1369                                    uint16_t vlan_id, int on)
1370 {
1371         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1372
1373         /* These operations apply to ALL existing MAC/VLAN filters */
1374         if (on)
1375                 return bnxt_add_vlan_filter(bp, vlan_id);
1376         else
1377                 return bnxt_del_vlan_filter(bp, vlan_id);
1378 }
1379
1380 static int
1381 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1382 {
1383         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1384         unsigned int i;
1385
1386         if (mask & ETH_VLAN_FILTER_MASK) {
1387                 if (!dev->data->dev_conf.rxmode.hw_vlan_filter) {
1388                         /* Remove any VLAN filters programmed */
1389                         for (i = 0; i < 4095; i++)
1390                                 bnxt_del_vlan_filter(bp, i);
1391                 }
1392                 RTE_LOG(INFO, PMD, "VLAN Filtering: %d\n",
1393                         dev->data->dev_conf.rxmode.hw_vlan_filter);
1394         }
1395
1396         if (mask & ETH_VLAN_STRIP_MASK) {
1397                 /* Enable or disable VLAN stripping */
1398                 for (i = 0; i < bp->nr_vnics; i++) {
1399                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1400                         if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1401                                 vnic->vlan_strip = true;
1402                         else
1403                                 vnic->vlan_strip = false;
1404                         bnxt_hwrm_vnic_cfg(bp, vnic);
1405                 }
1406                 RTE_LOG(INFO, PMD, "VLAN Strip Offload: %d\n",
1407                         dev->data->dev_conf.rxmode.hw_vlan_strip);
1408         }
1409
1410         if (mask & ETH_VLAN_EXTEND_MASK)
1411                 RTE_LOG(ERR, PMD, "Extend VLAN Not supported\n");
1412
1413         return 0;
1414 }
1415
1416 static void
1417 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1418 {
1419         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1420         /* Default Filter is tied to VNIC 0 */
1421         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1422         struct bnxt_filter_info *filter;
1423         int rc;
1424
1425         if (BNXT_VF(bp))
1426                 return;
1427
1428         memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1429         memcpy(&dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1430
1431         STAILQ_FOREACH(filter, &vnic->filter, next) {
1432                 /* Default Filter is at Index 0 */
1433                 if (filter->mac_index != 0)
1434                         continue;
1435                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1436                 if (rc)
1437                         break;
1438                 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1439                 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1440                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1441                 filter->enables |=
1442                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1443                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1444                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1445                 if (rc)
1446                         break;
1447                 filter->mac_index = 0;
1448                 RTE_LOG(DEBUG, PMD, "Set MAC addr\n");
1449         }
1450 }
1451
1452 static int
1453 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1454                           struct ether_addr *mc_addr_set,
1455                           uint32_t nb_mc_addr)
1456 {
1457         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1458         char *mc_addr_list = (char *)mc_addr_set;
1459         struct bnxt_vnic_info *vnic;
1460         uint32_t off = 0, i = 0;
1461
1462         vnic = &bp->vnic_info[0];
1463
1464         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1465                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1466                 goto allmulti;
1467         }
1468
1469         /* TODO Check for Duplicate mcast addresses */
1470         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1471         for (i = 0; i < nb_mc_addr; i++) {
1472                 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1473                 off += ETHER_ADDR_LEN;
1474         }
1475
1476         vnic->mc_addr_cnt = i;
1477
1478 allmulti:
1479         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1480 }
1481
1482 static int
1483 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1484 {
1485         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1486         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1487         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1488         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1489         int ret;
1490
1491         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1492                         fw_major, fw_minor, fw_updt);
1493
1494         ret += 1; /* add the size of '\0' */
1495         if (fw_size < (uint32_t)ret)
1496                 return ret;
1497         else
1498                 return 0;
1499 }
1500
1501 static void
1502 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1503         struct rte_eth_rxq_info *qinfo)
1504 {
1505         struct bnxt_rx_queue *rxq;
1506
1507         rxq = dev->data->rx_queues[queue_id];
1508
1509         qinfo->mp = rxq->mb_pool;
1510         qinfo->scattered_rx = dev->data->scattered_rx;
1511         qinfo->nb_desc = rxq->nb_rx_desc;
1512
1513         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1514         qinfo->conf.rx_drop_en = 0;
1515         qinfo->conf.rx_deferred_start = 0;
1516 }
1517
1518 static void
1519 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1520         struct rte_eth_txq_info *qinfo)
1521 {
1522         struct bnxt_tx_queue *txq;
1523
1524         txq = dev->data->tx_queues[queue_id];
1525
1526         qinfo->nb_desc = txq->nb_tx_desc;
1527
1528         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1529         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1530         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1531
1532         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1533         qinfo->conf.tx_rs_thresh = 0;
1534         qinfo->conf.txq_flags = txq->txq_flags;
1535         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1536 }
1537
1538 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1539 {
1540         struct bnxt *bp = eth_dev->data->dev_private;
1541         struct rte_eth_dev_info dev_info;
1542         uint32_t max_dev_mtu;
1543         uint32_t rc = 0;
1544         uint32_t i;
1545
1546         bnxt_dev_info_get_op(eth_dev, &dev_info);
1547         max_dev_mtu = dev_info.max_rx_pktlen -
1548                       ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1549
1550         if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1551                 RTE_LOG(ERR, PMD, "MTU requested must be within (%d, %d)\n",
1552                         ETHER_MIN_MTU, max_dev_mtu);
1553                 return -EINVAL;
1554         }
1555
1556
1557         if (new_mtu > ETHER_MTU) {
1558                 bp->flags |= BNXT_FLAG_JUMBO;
1559                 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
1560         } else {
1561                 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
1562                 bp->flags &= ~BNXT_FLAG_JUMBO;
1563         }
1564
1565         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1566                 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1567
1568         eth_dev->data->mtu = new_mtu;
1569         RTE_LOG(INFO, PMD, "New MTU is %d\n", eth_dev->data->mtu);
1570
1571         for (i = 0; i < bp->nr_vnics; i++) {
1572                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1573
1574                 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1575                                         ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1576                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1577                 if (rc)
1578                         break;
1579
1580                 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1581                 if (rc)
1582                         return rc;
1583         }
1584
1585         return rc;
1586 }
1587
1588 static int
1589 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1590 {
1591         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1592         uint16_t vlan = bp->vlan;
1593         int rc;
1594
1595         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1596                 RTE_LOG(ERR, PMD,
1597                         "PVID cannot be modified for this function\n");
1598                 return -ENOTSUP;
1599         }
1600         bp->vlan = on ? pvid : 0;
1601
1602         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1603         if (rc)
1604                 bp->vlan = vlan;
1605         return rc;
1606 }
1607
1608 static int
1609 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1610 {
1611         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1612
1613         return bnxt_hwrm_port_led_cfg(bp, true);
1614 }
1615
1616 static int
1617 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1618 {
1619         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1620
1621         return bnxt_hwrm_port_led_cfg(bp, false);
1622 }
1623
1624 static uint32_t
1625 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1626 {
1627         uint32_t desc = 0, raw_cons = 0, cons;
1628         struct bnxt_cp_ring_info *cpr;
1629         struct bnxt_rx_queue *rxq;
1630         struct rx_pkt_cmpl *rxcmp;
1631         uint16_t cmp_type;
1632         uint8_t cmp = 1;
1633         bool valid;
1634
1635         rxq = dev->data->rx_queues[rx_queue_id];
1636         cpr = rxq->cp_ring;
1637         valid = cpr->valid;
1638
1639         while (raw_cons < rxq->nb_rx_desc) {
1640                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1641                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1642
1643                 if (!CMPL_VALID(rxcmp, valid))
1644                         goto nothing_to_do;
1645                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1646                 cmp_type = CMP_TYPE(rxcmp);
1647                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1648                         cmp = (rte_le_to_cpu_32(
1649                                         ((struct rx_tpa_end_cmpl *)
1650                                          (rxcmp))->agg_bufs_v1) &
1651                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1652                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1653                         desc++;
1654                 } else if (cmp_type == 0x11) {
1655                         desc++;
1656                         cmp = (rxcmp->agg_bufs_v1 &
1657                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1658                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1659                 } else {
1660                         cmp = 1;
1661                 }
1662 nothing_to_do:
1663                 raw_cons += cmp ? cmp : 2;
1664         }
1665
1666         return desc;
1667 }
1668
1669 static int
1670 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1671 {
1672         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1673         struct bnxt_rx_ring_info *rxr;
1674         struct bnxt_cp_ring_info *cpr;
1675         struct bnxt_sw_rx_bd *rx_buf;
1676         struct rx_pkt_cmpl *rxcmp;
1677         uint32_t cons, cp_cons;
1678
1679         if (!rxq)
1680                 return -EINVAL;
1681
1682         cpr = rxq->cp_ring;
1683         rxr = rxq->rx_ring;
1684
1685         if (offset >= rxq->nb_rx_desc)
1686                 return -EINVAL;
1687
1688         cons = RING_CMP(cpr->cp_ring_struct, offset);
1689         cp_cons = cpr->cp_raw_cons;
1690         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1691
1692         if (cons > cp_cons) {
1693                 if (CMPL_VALID(rxcmp, cpr->valid))
1694                         return RTE_ETH_RX_DESC_DONE;
1695         } else {
1696                 if (CMPL_VALID(rxcmp, !cpr->valid))
1697                         return RTE_ETH_RX_DESC_DONE;
1698         }
1699         rx_buf = &rxr->rx_buf_ring[cons];
1700         if (rx_buf->mbuf == NULL)
1701                 return RTE_ETH_RX_DESC_UNAVAIL;
1702
1703
1704         return RTE_ETH_RX_DESC_AVAIL;
1705 }
1706
1707 static int
1708 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1709 {
1710         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1711         struct bnxt_tx_ring_info *txr;
1712         struct bnxt_cp_ring_info *cpr;
1713         struct bnxt_sw_tx_bd *tx_buf;
1714         struct tx_pkt_cmpl *txcmp;
1715         uint32_t cons, cp_cons;
1716
1717         if (!txq)
1718                 return -EINVAL;
1719
1720         cpr = txq->cp_ring;
1721         txr = txq->tx_ring;
1722
1723         if (offset >= txq->nb_tx_desc)
1724                 return -EINVAL;
1725
1726         cons = RING_CMP(cpr->cp_ring_struct, offset);
1727         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1728         cp_cons = cpr->cp_raw_cons;
1729
1730         if (cons > cp_cons) {
1731                 if (CMPL_VALID(txcmp, cpr->valid))
1732                         return RTE_ETH_TX_DESC_UNAVAIL;
1733         } else {
1734                 if (CMPL_VALID(txcmp, !cpr->valid))
1735                         return RTE_ETH_TX_DESC_UNAVAIL;
1736         }
1737         tx_buf = &txr->tx_buf_ring[cons];
1738         if (tx_buf->mbuf == NULL)
1739                 return RTE_ETH_TX_DESC_DONE;
1740
1741         return RTE_ETH_TX_DESC_FULL;
1742 }
1743
1744 static struct bnxt_filter_info *
1745 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1746                                 struct rte_eth_ethertype_filter *efilter,
1747                                 struct bnxt_vnic_info *vnic0,
1748                                 struct bnxt_vnic_info *vnic,
1749                                 int *ret)
1750 {
1751         struct bnxt_filter_info *mfilter = NULL;
1752         int match = 0;
1753         *ret = 0;
1754
1755         if (efilter->ether_type == ETHER_TYPE_IPv4 ||
1756                 efilter->ether_type == ETHER_TYPE_IPv6) {
1757                 RTE_LOG(ERR, PMD, "invalid ether_type(0x%04x) in"
1758                         " ethertype filter.", efilter->ether_type);
1759                 *ret = -EINVAL;
1760                 goto exit;
1761         }
1762         if (efilter->queue >= bp->rx_nr_rings) {
1763                 RTE_LOG(ERR, PMD, "Invalid queue %d\n", efilter->queue);
1764                 *ret = -EINVAL;
1765                 goto exit;
1766         }
1767
1768         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1769         vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1770         if (vnic == NULL) {
1771                 RTE_LOG(ERR, PMD, "Invalid queue %d\n", efilter->queue);
1772                 *ret = -EINVAL;
1773                 goto exit;
1774         }
1775
1776         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1777                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1778                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1779                                      mfilter->l2_addr, ETHER_ADDR_LEN) &&
1780                              mfilter->flags ==
1781                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1782                              mfilter->ethertype == efilter->ether_type)) {
1783                                 match = 1;
1784                                 break;
1785                         }
1786                 }
1787         } else {
1788                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1789                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1790                                      mfilter->l2_addr, ETHER_ADDR_LEN) &&
1791                              mfilter->ethertype == efilter->ether_type &&
1792                              mfilter->flags ==
1793                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1794                                 match = 1;
1795                                 break;
1796                         }
1797         }
1798
1799         if (match)
1800                 *ret = -EEXIST;
1801
1802 exit:
1803         return mfilter;
1804 }
1805
1806 static int
1807 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1808                         enum rte_filter_op filter_op,
1809                         void *arg)
1810 {
1811         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1812         struct rte_eth_ethertype_filter *efilter =
1813                         (struct rte_eth_ethertype_filter *)arg;
1814         struct bnxt_filter_info *bfilter, *filter1;
1815         struct bnxt_vnic_info *vnic, *vnic0;
1816         int ret;
1817
1818         if (filter_op == RTE_ETH_FILTER_NOP)
1819                 return 0;
1820
1821         if (arg == NULL) {
1822                 RTE_LOG(ERR, PMD, "arg shouldn't be NULL for operation %u.",
1823                             filter_op);
1824                 return -EINVAL;
1825         }
1826
1827         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1828         vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1829
1830         switch (filter_op) {
1831         case RTE_ETH_FILTER_ADD:
1832                 bnxt_match_and_validate_ether_filter(bp, efilter,
1833                                                         vnic0, vnic, &ret);
1834                 if (ret < 0)
1835                         return ret;
1836
1837                 bfilter = bnxt_get_unused_filter(bp);
1838                 if (bfilter == NULL) {
1839                         RTE_LOG(ERR, PMD,
1840                                 "Not enough resources for a new filter.\n");
1841                         return -ENOMEM;
1842                 }
1843                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1844                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1845                        ETHER_ADDR_LEN);
1846                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1847                        ETHER_ADDR_LEN);
1848                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1849                 bfilter->ethertype = efilter->ether_type;
1850                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1851
1852                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1853                 if (filter1 == NULL) {
1854                         ret = -1;
1855                         goto cleanup;
1856                 }
1857                 bfilter->enables |=
1858                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1859                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1860
1861                 bfilter->dst_id = vnic->fw_vnic_id;
1862
1863                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1864                         bfilter->flags =
1865                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1866                 }
1867
1868                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1869                 if (ret)
1870                         goto cleanup;
1871                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1872                 break;
1873         case RTE_ETH_FILTER_DELETE:
1874                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1875                                                         vnic0, vnic, &ret);
1876                 if (ret == -EEXIST) {
1877                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1878
1879                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1880                                       next);
1881                         bnxt_free_filter(bp, filter1);
1882                 } else if (ret == 0) {
1883                         RTE_LOG(ERR, PMD, "No matching filter found\n");
1884                 }
1885                 break;
1886         default:
1887                 RTE_LOG(ERR, PMD, "unsupported operation %u.", filter_op);
1888                 ret = -EINVAL;
1889                 goto error;
1890         }
1891         return ret;
1892 cleanup:
1893         bnxt_free_filter(bp, bfilter);
1894 error:
1895         return ret;
1896 }
1897
1898 static inline int
1899 parse_ntuple_filter(struct bnxt *bp,
1900                     struct rte_eth_ntuple_filter *nfilter,
1901                     struct bnxt_filter_info *bfilter)
1902 {
1903         uint32_t en = 0;
1904
1905         if (nfilter->queue >= bp->rx_nr_rings) {
1906                 RTE_LOG(ERR, PMD, "Invalid queue %d\n", nfilter->queue);
1907                 return -EINVAL;
1908         }
1909
1910         switch (nfilter->dst_port_mask) {
1911         case UINT16_MAX:
1912                 bfilter->dst_port_mask = -1;
1913                 bfilter->dst_port = nfilter->dst_port;
1914                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1915                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1916                 break;
1917         default:
1918                 RTE_LOG(ERR, PMD, "invalid dst_port mask.");
1919                 return -EINVAL;
1920         }
1921
1922         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1923         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1924
1925         switch (nfilter->proto_mask) {
1926         case UINT8_MAX:
1927                 if (nfilter->proto == 17) /* IPPROTO_UDP */
1928                         bfilter->ip_protocol = 17;
1929                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1930                         bfilter->ip_protocol = 6;
1931                 else
1932                         return -EINVAL;
1933                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1934                 break;
1935         default:
1936                 RTE_LOG(ERR, PMD, "invalid protocol mask.");
1937                 return -EINVAL;
1938         }
1939
1940         switch (nfilter->dst_ip_mask) {
1941         case UINT32_MAX:
1942                 bfilter->dst_ipaddr_mask[0] = -1;
1943                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
1944                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
1945                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
1946                 break;
1947         default:
1948                 RTE_LOG(ERR, PMD, "invalid dst_ip mask.");
1949                 return -EINVAL;
1950         }
1951
1952         switch (nfilter->src_ip_mask) {
1953         case UINT32_MAX:
1954                 bfilter->src_ipaddr_mask[0] = -1;
1955                 bfilter->src_ipaddr[0] = nfilter->src_ip;
1956                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
1957                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
1958                 break;
1959         default:
1960                 RTE_LOG(ERR, PMD, "invalid src_ip mask.");
1961                 return -EINVAL;
1962         }
1963
1964         switch (nfilter->src_port_mask) {
1965         case UINT16_MAX:
1966                 bfilter->src_port_mask = -1;
1967                 bfilter->src_port = nfilter->src_port;
1968                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
1969                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
1970                 break;
1971         default:
1972                 RTE_LOG(ERR, PMD, "invalid src_port mask.");
1973                 return -EINVAL;
1974         }
1975
1976         //TODO Priority
1977         //nfilter->priority = (uint8_t)filter->priority;
1978
1979         bfilter->enables = en;
1980         return 0;
1981 }
1982
1983 static struct bnxt_filter_info*
1984 bnxt_match_ntuple_filter(struct bnxt *bp,
1985                          struct bnxt_filter_info *bfilter,
1986                          struct bnxt_vnic_info **mvnic)
1987 {
1988         struct bnxt_filter_info *mfilter = NULL;
1989         int i;
1990
1991         for (i = bp->nr_vnics - 1; i >= 0; i--) {
1992                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1993                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
1994                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
1995                             bfilter->src_ipaddr_mask[0] ==
1996                             mfilter->src_ipaddr_mask[0] &&
1997                             bfilter->src_port == mfilter->src_port &&
1998                             bfilter->src_port_mask == mfilter->src_port_mask &&
1999                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2000                             bfilter->dst_ipaddr_mask[0] ==
2001                             mfilter->dst_ipaddr_mask[0] &&
2002                             bfilter->dst_port == mfilter->dst_port &&
2003                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2004                             bfilter->flags == mfilter->flags &&
2005                             bfilter->enables == mfilter->enables) {
2006                                 if (mvnic)
2007                                         *mvnic = vnic;
2008                                 return mfilter;
2009                         }
2010                 }
2011         }
2012         return NULL;
2013 }
2014
2015 static int
2016 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2017                        struct rte_eth_ntuple_filter *nfilter,
2018                        enum rte_filter_op filter_op)
2019 {
2020         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2021         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2022         int ret;
2023
2024         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2025                 RTE_LOG(ERR, PMD, "only 5tuple is supported.");
2026                 return -EINVAL;
2027         }
2028
2029         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2030                 RTE_LOG(ERR, PMD, "Ntuple filter: TCP flags not supported\n");
2031                 return -EINVAL;
2032         }
2033
2034         bfilter = bnxt_get_unused_filter(bp);
2035         if (bfilter == NULL) {
2036                 RTE_LOG(ERR, PMD,
2037                         "Not enough resources for a new filter.\n");
2038                 return -ENOMEM;
2039         }
2040         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2041         if (ret < 0)
2042                 goto free_filter;
2043
2044         vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]);
2045         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2046         filter1 = STAILQ_FIRST(&vnic0->filter);
2047         if (filter1 == NULL) {
2048                 ret = -1;
2049                 goto free_filter;
2050         }
2051
2052         bfilter->dst_id = vnic->fw_vnic_id;
2053         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2054         bfilter->enables |=
2055                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2056         bfilter->ethertype = 0x800;
2057         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2058
2059         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2060
2061         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2062             bfilter->dst_id == mfilter->dst_id) {
2063                 RTE_LOG(ERR, PMD, "filter exists.\n");
2064                 ret = -EEXIST;
2065                 goto free_filter;
2066         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2067                    bfilter->dst_id != mfilter->dst_id) {
2068                 mfilter->dst_id = vnic->fw_vnic_id;
2069                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2070                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2071                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2072                 RTE_LOG(ERR, PMD, "filter with matching pattern exists.\n");
2073                 RTE_LOG(ERR, PMD, " Updated it to the new destination queue\n");
2074                 goto free_filter;
2075         }
2076         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2077                 RTE_LOG(ERR, PMD, "filter doesn't exist.");
2078                 ret = -ENOENT;
2079                 goto free_filter;
2080         }
2081
2082         if (filter_op == RTE_ETH_FILTER_ADD) {
2083                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2084                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2085                 if (ret)
2086                         goto free_filter;
2087                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2088         } else {
2089                 if (mfilter == NULL) {
2090                         /* This should not happen. But for Coverity! */
2091                         ret = -ENOENT;
2092                         goto free_filter;
2093                 }
2094                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2095
2096                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2097                 bnxt_free_filter(bp, mfilter);
2098                 mfilter->fw_l2_filter_id = -1;
2099                 bnxt_free_filter(bp, bfilter);
2100                 bfilter->fw_l2_filter_id = -1;
2101         }
2102
2103         return 0;
2104 free_filter:
2105         bfilter->fw_l2_filter_id = -1;
2106         bnxt_free_filter(bp, bfilter);
2107         return ret;
2108 }
2109
2110 static int
2111 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2112                         enum rte_filter_op filter_op,
2113                         void *arg)
2114 {
2115         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2116         int ret;
2117
2118         if (filter_op == RTE_ETH_FILTER_NOP)
2119                 return 0;
2120
2121         if (arg == NULL) {
2122                 RTE_LOG(ERR, PMD, "arg shouldn't be NULL for operation %u.",
2123                             filter_op);
2124                 return -EINVAL;
2125         }
2126
2127         switch (filter_op) {
2128         case RTE_ETH_FILTER_ADD:
2129                 ret = bnxt_cfg_ntuple_filter(bp,
2130                         (struct rte_eth_ntuple_filter *)arg,
2131                         filter_op);
2132                 break;
2133         case RTE_ETH_FILTER_DELETE:
2134                 ret = bnxt_cfg_ntuple_filter(bp,
2135                         (struct rte_eth_ntuple_filter *)arg,
2136                         filter_op);
2137                 break;
2138         default:
2139                 RTE_LOG(ERR, PMD, "unsupported operation %u.", filter_op);
2140                 ret = -EINVAL;
2141                 break;
2142         }
2143         return ret;
2144 }
2145
2146 static int
2147 bnxt_parse_fdir_filter(struct bnxt *bp,
2148                        struct rte_eth_fdir_filter *fdir,
2149                        struct bnxt_filter_info *filter)
2150 {
2151         enum rte_fdir_mode fdir_mode =
2152                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2153         struct bnxt_vnic_info *vnic0, *vnic;
2154         struct bnxt_filter_info *filter1;
2155         uint32_t en = 0;
2156         int i;
2157
2158         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2159                 return -EINVAL;
2160
2161         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2162         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2163
2164         switch (fdir->input.flow_type) {
2165         case RTE_ETH_FLOW_IPV4:
2166         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2167                 /* FALLTHROUGH */
2168                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2169                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2170                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2171                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2172                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2173                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2174                 filter->ip_addr_type =
2175                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2176                 filter->src_ipaddr_mask[0] = 0xffffffff;
2177                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2178                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2179                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2180                 filter->ethertype = 0x800;
2181                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2182                 break;
2183         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2184                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2185                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2186                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2187                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2188                 filter->dst_port_mask = 0xffff;
2189                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2190                 filter->src_port_mask = 0xffff;
2191                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2192                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2193                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2194                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2195                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2196                 filter->ip_protocol = 6;
2197                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2198                 filter->ip_addr_type =
2199                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2200                 filter->src_ipaddr_mask[0] = 0xffffffff;
2201                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2202                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2203                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2204                 filter->ethertype = 0x800;
2205                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2206                 break;
2207         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2208                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2209                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2210                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2211                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2212                 filter->dst_port_mask = 0xffff;
2213                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2214                 filter->src_port_mask = 0xffff;
2215                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2216                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2217                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2218                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2219                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2220                 filter->ip_protocol = 17;
2221                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2222                 filter->ip_addr_type =
2223                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2224                 filter->src_ipaddr_mask[0] = 0xffffffff;
2225                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2226                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2227                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2228                 filter->ethertype = 0x800;
2229                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2230                 break;
2231         case RTE_ETH_FLOW_IPV6:
2232         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2233                 /* FALLTHROUGH */
2234                 filter->ip_addr_type =
2235                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2236                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2237                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2238                 rte_memcpy(filter->src_ipaddr,
2239                            fdir->input.flow.ipv6_flow.src_ip, 16);
2240                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2241                 rte_memcpy(filter->dst_ipaddr,
2242                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2243                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2244                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2245                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2246                 memset(filter->src_ipaddr_mask, 0xff, 16);
2247                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2248                 filter->ethertype = 0x86dd;
2249                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2250                 break;
2251         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2252                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2253                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2254                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2255                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2256                 filter->dst_port_mask = 0xffff;
2257                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2258                 filter->src_port_mask = 0xffff;
2259                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2260                 filter->ip_addr_type =
2261                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2262                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2263                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2264                 rte_memcpy(filter->src_ipaddr,
2265                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2266                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2267                 rte_memcpy(filter->dst_ipaddr,
2268                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2269                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2270                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2271                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2272                 memset(filter->src_ipaddr_mask, 0xff, 16);
2273                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2274                 filter->ethertype = 0x86dd;
2275                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2276                 break;
2277         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2278                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2279                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2280                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2281                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2282                 filter->dst_port_mask = 0xffff;
2283                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2284                 filter->src_port_mask = 0xffff;
2285                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2286                 filter->ip_addr_type =
2287                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2288                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2289                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2290                 rte_memcpy(filter->src_ipaddr,
2291                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2292                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2293                 rte_memcpy(filter->dst_ipaddr,
2294                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2295                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2296                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2297                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2298                 memset(filter->src_ipaddr_mask, 0xff, 16);
2299                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2300                 filter->ethertype = 0x86dd;
2301                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2302                 break;
2303         case RTE_ETH_FLOW_L2_PAYLOAD:
2304                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2305                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2306                 break;
2307         case RTE_ETH_FLOW_VXLAN:
2308                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2309                         return -EINVAL;
2310                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2311                 filter->tunnel_type =
2312                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2313                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2314                 break;
2315         case RTE_ETH_FLOW_NVGRE:
2316                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2317                         return -EINVAL;
2318                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2319                 filter->tunnel_type =
2320                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2321                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2322                 break;
2323         case RTE_ETH_FLOW_UNKNOWN:
2324         case RTE_ETH_FLOW_RAW:
2325         case RTE_ETH_FLOW_FRAG_IPV4:
2326         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2327         case RTE_ETH_FLOW_FRAG_IPV6:
2328         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2329         case RTE_ETH_FLOW_IPV6_EX:
2330         case RTE_ETH_FLOW_IPV6_TCP_EX:
2331         case RTE_ETH_FLOW_IPV6_UDP_EX:
2332         case RTE_ETH_FLOW_GENEVE:
2333                 /* FALLTHROUGH */
2334         default:
2335                 return -EINVAL;
2336         }
2337
2338         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2339         vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2340         if (vnic == NULL) {
2341                 RTE_LOG(ERR, PMD, "Invalid queue %d\n", fdir->action.rx_queue);
2342                 return -EINVAL;
2343         }
2344
2345
2346         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2347                 rte_memcpy(filter->dst_macaddr,
2348                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2349                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2350         }
2351
2352         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2353                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2354                 filter1 = STAILQ_FIRST(&vnic0->filter);
2355                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2356         } else {
2357                 filter->dst_id = vnic->fw_vnic_id;
2358                 for (i = 0; i < ETHER_ADDR_LEN; i++)
2359                         if (filter->dst_macaddr[i] == 0x00)
2360                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2361                         else
2362                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2363         }
2364
2365         if (filter1 == NULL)
2366                 return -EINVAL;
2367
2368         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2369         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2370
2371         filter->enables = en;
2372
2373         return 0;
2374 }
2375
2376 static struct bnxt_filter_info *
2377 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf)
2378 {
2379         struct bnxt_filter_info *mf = NULL;
2380         int i;
2381
2382         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2383                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2384
2385                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2386                         if (mf->filter_type == nf->filter_type &&
2387                             mf->flags == nf->flags &&
2388                             mf->src_port == nf->src_port &&
2389                             mf->src_port_mask == nf->src_port_mask &&
2390                             mf->dst_port == nf->dst_port &&
2391                             mf->dst_port_mask == nf->dst_port_mask &&
2392                             mf->ip_protocol == nf->ip_protocol &&
2393                             mf->ip_addr_type == nf->ip_addr_type &&
2394                             mf->ethertype == nf->ethertype &&
2395                             mf->vni == nf->vni &&
2396                             mf->tunnel_type == nf->tunnel_type &&
2397                             mf->l2_ovlan == nf->l2_ovlan &&
2398                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2399                             mf->l2_ivlan == nf->l2_ivlan &&
2400                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2401                             !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) &&
2402                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2403                                     ETHER_ADDR_LEN) &&
2404                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2405                                     ETHER_ADDR_LEN) &&
2406                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2407                                     ETHER_ADDR_LEN) &&
2408                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2409                                     sizeof(nf->src_ipaddr)) &&
2410                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2411                                     sizeof(nf->src_ipaddr_mask)) &&
2412                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2413                                     sizeof(nf->dst_ipaddr)) &&
2414                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2415                                     sizeof(nf->dst_ipaddr_mask)))
2416                                 return mf;
2417                 }
2418         }
2419         return NULL;
2420 }
2421
2422 static int
2423 bnxt_fdir_filter(struct rte_eth_dev *dev,
2424                  enum rte_filter_op filter_op,
2425                  void *arg)
2426 {
2427         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2428         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2429         struct bnxt_filter_info *filter, *match;
2430         struct bnxt_vnic_info *vnic;
2431         int ret = 0, i;
2432
2433         if (filter_op == RTE_ETH_FILTER_NOP)
2434                 return 0;
2435
2436         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2437                 return -EINVAL;
2438
2439         switch (filter_op) {
2440         case RTE_ETH_FILTER_ADD:
2441         case RTE_ETH_FILTER_DELETE:
2442                 /* FALLTHROUGH */
2443                 filter = bnxt_get_unused_filter(bp);
2444                 if (filter == NULL) {
2445                         RTE_LOG(ERR, PMD,
2446                                 "Not enough resources for a new flow.\n");
2447                         return -ENOMEM;
2448                 }
2449
2450                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2451                 if (ret != 0)
2452                         goto free_filter;
2453                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2454
2455                 match = bnxt_match_fdir(bp, filter);
2456                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2457                         RTE_LOG(ERR, PMD, "Flow already exists.\n");
2458                         ret = -EEXIST;
2459                         goto free_filter;
2460                 }
2461                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2462                         RTE_LOG(ERR, PMD, "Flow does not exist.\n");
2463                         ret = -ENOENT;
2464                         goto free_filter;
2465                 }
2466
2467                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2468                         vnic = STAILQ_FIRST(&bp->ff_pool[0]);
2469                 else
2470                         vnic =
2471                         STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2472
2473                 if (filter_op == RTE_ETH_FILTER_ADD) {
2474                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2475                                                           filter->dst_id,
2476                                                           filter);
2477                         if (ret)
2478                                 goto free_filter;
2479                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2480                 } else {
2481                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2482                         STAILQ_REMOVE(&vnic->filter, match,
2483                                       bnxt_filter_info, next);
2484                         bnxt_free_filter(bp, match);
2485                         filter->fw_l2_filter_id = -1;
2486                         bnxt_free_filter(bp, filter);
2487                 }
2488                 break;
2489         case RTE_ETH_FILTER_FLUSH:
2490                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2491                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2492
2493                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2494                                 if (filter->filter_type ==
2495                                     HWRM_CFA_NTUPLE_FILTER) {
2496                                         ret =
2497                                         bnxt_hwrm_clear_ntuple_filter(bp,
2498                                                                       filter);
2499                                         STAILQ_REMOVE(&vnic->filter, filter,
2500                                                       bnxt_filter_info, next);
2501                                 }
2502                         }
2503                 }
2504                 return ret;
2505         case RTE_ETH_FILTER_UPDATE:
2506         case RTE_ETH_FILTER_STATS:
2507         case RTE_ETH_FILTER_INFO:
2508                 /* FALLTHROUGH */
2509                 RTE_LOG(ERR, PMD, "operation %u not implemented", filter_op);
2510                 break;
2511         default:
2512                 RTE_LOG(ERR, PMD, "unknown operation %u", filter_op);
2513                 ret = -EINVAL;
2514                 break;
2515         }
2516         return ret;
2517
2518 free_filter:
2519         filter->fw_l2_filter_id = -1;
2520         bnxt_free_filter(bp, filter);
2521         return ret;
2522 }
2523
2524 static int
2525 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2526                     enum rte_filter_type filter_type,
2527                     enum rte_filter_op filter_op, void *arg)
2528 {
2529         int ret = 0;
2530
2531         switch (filter_type) {
2532         case RTE_ETH_FILTER_TUNNEL:
2533                 RTE_LOG(ERR, PMD,
2534                         "filter type: %d: To be implemented\n", filter_type);
2535                 break;
2536         case RTE_ETH_FILTER_FDIR:
2537                 ret = bnxt_fdir_filter(dev, filter_op, arg);
2538                 break;
2539         case RTE_ETH_FILTER_NTUPLE:
2540                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2541                 break;
2542         case RTE_ETH_FILTER_ETHERTYPE:
2543                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2544                 break;
2545         case RTE_ETH_FILTER_GENERIC:
2546                 if (filter_op != RTE_ETH_FILTER_GET)
2547                         return -EINVAL;
2548                 *(const void **)arg = &bnxt_flow_ops;
2549                 break;
2550         default:
2551                 RTE_LOG(ERR, PMD,
2552                         "Filter type (%d) not supported", filter_type);
2553                 ret = -EINVAL;
2554                 break;
2555         }
2556         return ret;
2557 }
2558
2559 static const uint32_t *
2560 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2561 {
2562         static const uint32_t ptypes[] = {
2563                 RTE_PTYPE_L2_ETHER_VLAN,
2564                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2565                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2566                 RTE_PTYPE_L4_ICMP,
2567                 RTE_PTYPE_L4_TCP,
2568                 RTE_PTYPE_L4_UDP,
2569                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2570                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2571                 RTE_PTYPE_INNER_L4_ICMP,
2572                 RTE_PTYPE_INNER_L4_TCP,
2573                 RTE_PTYPE_INNER_L4_UDP,
2574                 RTE_PTYPE_UNKNOWN
2575         };
2576
2577         if (dev->rx_pkt_burst == bnxt_recv_pkts)
2578                 return ptypes;
2579         return NULL;
2580 }
2581
2582 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2583                          int reg_win)
2584 {
2585         uint32_t reg_base = *reg_arr & 0xfffff000;
2586         uint32_t win_off;
2587         int i;
2588
2589         for (i = 0; i < count; i++) {
2590                 if ((reg_arr[i] & 0xfffff000) != reg_base)
2591                         return -ERANGE;
2592         }
2593         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2594         rte_cpu_to_le_32(rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off));
2595         return 0;
2596 }
2597
2598 static int bnxt_map_ptp_regs(struct bnxt *bp)
2599 {
2600         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2601         uint32_t *reg_arr;
2602         int rc, i;
2603
2604         reg_arr = ptp->rx_regs;
2605         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2606         if (rc)
2607                 return rc;
2608
2609         reg_arr = ptp->tx_regs;
2610         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2611         if (rc)
2612                 return rc;
2613
2614         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2615                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2616
2617         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2618                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2619
2620         return 0;
2621 }
2622
2623 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2624 {
2625         rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2626                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16));
2627         rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2628                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20));
2629 }
2630
2631 static uint64_t bnxt_cc_read(struct bnxt *bp)
2632 {
2633         uint64_t ns;
2634
2635         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2636                               BNXT_GRCPF_REG_SYNC_TIME));
2637         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2638                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2639         return ns;
2640 }
2641
2642 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2643 {
2644         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2645         uint32_t fifo;
2646
2647         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2648                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2649         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2650                 return -EAGAIN;
2651
2652         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2653                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2654         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2655                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2656         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2657                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2658
2659         return 0;
2660 }
2661
2662 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2663 {
2664         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2665         struct bnxt_pf_info *pf = &bp->pf;
2666         uint16_t port_id;
2667         uint32_t fifo;
2668
2669         if (!ptp)
2670                 return -ENODEV;
2671
2672         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2673                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2674         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2675                 return -EAGAIN;
2676
2677         port_id = pf->port_id;
2678         rte_cpu_to_le_32(rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2679                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]));
2680
2681         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2682                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2683         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2684 /*              bnxt_clr_rx_ts(bp);       TBD  */
2685                 return -EBUSY;
2686         }
2687
2688         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2689                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2690         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2691                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2692
2693         return 0;
2694 }
2695
2696 static int
2697 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2698 {
2699         uint64_t ns;
2700         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2701         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2702
2703         if (!ptp)
2704                 return 0;
2705
2706         ns = rte_timespec_to_ns(ts);
2707         /* Set the timecounters to a new value. */
2708         ptp->tc.nsec = ns;
2709
2710         return 0;
2711 }
2712
2713 static int
2714 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2715 {
2716         uint64_t ns, systime_cycles;
2717         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2718         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2719
2720         if (!ptp)
2721                 return 0;
2722
2723         systime_cycles = bnxt_cc_read(bp);
2724         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2725         *ts = rte_ns_to_timespec(ns);
2726
2727         return 0;
2728 }
2729 static int
2730 bnxt_timesync_enable(struct rte_eth_dev *dev)
2731 {
2732         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2733         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2734         uint32_t shift = 0;
2735
2736         if (!ptp)
2737                 return 0;
2738
2739         ptp->rx_filter = 1;
2740         ptp->tx_tstamp_en = 1;
2741         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2742
2743         if (!bnxt_hwrm_ptp_cfg(bp))
2744                 bnxt_map_ptp_regs(bp);
2745
2746         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2747         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2748         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2749
2750         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2751         ptp->tc.cc_shift = shift;
2752         ptp->tc.nsec_mask = (1ULL << shift) - 1;
2753
2754         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2755         ptp->rx_tstamp_tc.cc_shift = shift;
2756         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2757
2758         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2759         ptp->tx_tstamp_tc.cc_shift = shift;
2760         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2761
2762         return 0;
2763 }
2764
2765 static int
2766 bnxt_timesync_disable(struct rte_eth_dev *dev)
2767 {
2768         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2769         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2770
2771         if (!ptp)
2772                 return 0;
2773
2774         ptp->rx_filter = 0;
2775         ptp->tx_tstamp_en = 0;
2776         ptp->rxctl = 0;
2777
2778         bnxt_hwrm_ptp_cfg(bp);
2779
2780         bnxt_unmap_ptp_regs(bp);
2781
2782         return 0;
2783 }
2784
2785 static int
2786 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2787                                  struct timespec *timestamp,
2788                                  uint32_t flags __rte_unused)
2789 {
2790         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2791         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2792         uint64_t rx_tstamp_cycles = 0;
2793         uint64_t ns;
2794
2795         if (!ptp)
2796                 return 0;
2797
2798         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2799         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2800         *timestamp = rte_ns_to_timespec(ns);
2801         return  0;
2802 }
2803
2804 static int
2805 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2806                                  struct timespec *timestamp)
2807 {
2808         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2809         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2810         uint64_t tx_tstamp_cycles = 0;
2811         uint64_t ns;
2812
2813         if (!ptp)
2814                 return 0;
2815
2816         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2817         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2818         *timestamp = rte_ns_to_timespec(ns);
2819
2820         return 0;
2821 }
2822
2823 static int
2824 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2825 {
2826         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2827         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2828
2829         if (!ptp)
2830                 return 0;
2831
2832         ptp->tc.nsec += delta;
2833
2834         return 0;
2835 }
2836
2837 static int
2838 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2839 {
2840         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2841         int rc;
2842         uint32_t dir_entries;
2843         uint32_t entry_length;
2844
2845         RTE_LOG(INFO, PMD, "%s(): %04x:%02x:%02x:%02x\n",
2846                 __func__, bp->pdev->addr.domain, bp->pdev->addr.bus,
2847                 bp->pdev->addr.devid, bp->pdev->addr.function);
2848
2849         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2850         if (rc != 0)
2851                 return rc;
2852
2853         return dir_entries * entry_length;
2854 }
2855
2856 static int
2857 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2858                 struct rte_dev_eeprom_info *in_eeprom)
2859 {
2860         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2861         uint32_t index;
2862         uint32_t offset;
2863
2864         RTE_LOG(INFO, PMD, "%s(): %04x:%02x:%02x:%02x in_eeprom->offset = %d "
2865                 "len = %d\n", __func__, bp->pdev->addr.domain,
2866                 bp->pdev->addr.bus, bp->pdev->addr.devid,
2867                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2868
2869         if (in_eeprom->offset == 0) /* special offset value to get directory */
2870                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2871                                                 in_eeprom->data);
2872
2873         index = in_eeprom->offset >> 24;
2874         offset = in_eeprom->offset & 0xffffff;
2875
2876         if (index != 0)
2877                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2878                                            in_eeprom->length, in_eeprom->data);
2879
2880         return 0;
2881 }
2882
2883 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2884 {
2885         switch (dir_type) {
2886         case BNX_DIR_TYPE_CHIMP_PATCH:
2887         case BNX_DIR_TYPE_BOOTCODE:
2888         case BNX_DIR_TYPE_BOOTCODE_2:
2889         case BNX_DIR_TYPE_APE_FW:
2890         case BNX_DIR_TYPE_APE_PATCH:
2891         case BNX_DIR_TYPE_KONG_FW:
2892         case BNX_DIR_TYPE_KONG_PATCH:
2893         case BNX_DIR_TYPE_BONO_FW:
2894         case BNX_DIR_TYPE_BONO_PATCH:
2895                 return true;
2896         }
2897
2898         return false;
2899 }
2900
2901 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2902 {
2903         switch (dir_type) {
2904         case BNX_DIR_TYPE_AVS:
2905         case BNX_DIR_TYPE_EXP_ROM_MBA:
2906         case BNX_DIR_TYPE_PCIE:
2907         case BNX_DIR_TYPE_TSCF_UCODE:
2908         case BNX_DIR_TYPE_EXT_PHY:
2909         case BNX_DIR_TYPE_CCM:
2910         case BNX_DIR_TYPE_ISCSI_BOOT:
2911         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2912         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2913                 return true;
2914         }
2915
2916         return false;
2917 }
2918
2919 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
2920 {
2921         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2922                 bnxt_dir_type_is_other_exec_format(dir_type);
2923 }
2924
2925 static int
2926 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2927                 struct rte_dev_eeprom_info *in_eeprom)
2928 {
2929         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2930         uint8_t index, dir_op;
2931         uint16_t type, ext, ordinal, attr;
2932
2933         RTE_LOG(INFO, PMD, "%s(): %04x:%02x:%02x:%02x in_eeprom->offset = %d "
2934                 "len = %d\n", __func__, bp->pdev->addr.domain,
2935                 bp->pdev->addr.bus, bp->pdev->addr.devid,
2936                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2937
2938         if (!BNXT_PF(bp)) {
2939                 RTE_LOG(ERR, PMD, "NVM write not supported from a VF\n");
2940                 return -EINVAL;
2941         }
2942
2943         type = in_eeprom->magic >> 16;
2944
2945         if (type == 0xffff) { /* special value for directory operations */
2946                 index = in_eeprom->magic & 0xff;
2947                 dir_op = in_eeprom->magic >> 8;
2948                 if (index == 0)
2949                         return -EINVAL;
2950                 switch (dir_op) {
2951                 case 0x0e: /* erase */
2952                         if (in_eeprom->offset != ~in_eeprom->magic)
2953                                 return -EINVAL;
2954                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
2955                 default:
2956                         return -EINVAL;
2957                 }
2958         }
2959
2960         /* Create or re-write an NVM item: */
2961         if (bnxt_dir_type_is_executable(type) == true)
2962                 return -EOPNOTSUPP;
2963         ext = in_eeprom->magic & 0xffff;
2964         ordinal = in_eeprom->offset >> 16;
2965         attr = in_eeprom->offset & 0xffff;
2966
2967         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
2968                                      in_eeprom->data, in_eeprom->length);
2969         return 0;
2970 }
2971
2972 /*
2973  * Initialization
2974  */
2975
2976 static const struct eth_dev_ops bnxt_dev_ops = {
2977         .dev_infos_get = bnxt_dev_info_get_op,
2978         .dev_close = bnxt_dev_close_op,
2979         .dev_configure = bnxt_dev_configure_op,
2980         .dev_start = bnxt_dev_start_op,
2981         .dev_stop = bnxt_dev_stop_op,
2982         .dev_set_link_up = bnxt_dev_set_link_up_op,
2983         .dev_set_link_down = bnxt_dev_set_link_down_op,
2984         .stats_get = bnxt_stats_get_op,
2985         .stats_reset = bnxt_stats_reset_op,
2986         .rx_queue_setup = bnxt_rx_queue_setup_op,
2987         .rx_queue_release = bnxt_rx_queue_release_op,
2988         .tx_queue_setup = bnxt_tx_queue_setup_op,
2989         .tx_queue_release = bnxt_tx_queue_release_op,
2990         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
2991         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
2992         .reta_update = bnxt_reta_update_op,
2993         .reta_query = bnxt_reta_query_op,
2994         .rss_hash_update = bnxt_rss_hash_update_op,
2995         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
2996         .link_update = bnxt_link_update_op,
2997         .promiscuous_enable = bnxt_promiscuous_enable_op,
2998         .promiscuous_disable = bnxt_promiscuous_disable_op,
2999         .allmulticast_enable = bnxt_allmulticast_enable_op,
3000         .allmulticast_disable = bnxt_allmulticast_disable_op,
3001         .mac_addr_add = bnxt_mac_addr_add_op,
3002         .mac_addr_remove = bnxt_mac_addr_remove_op,
3003         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3004         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3005         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3006         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3007         .vlan_filter_set = bnxt_vlan_filter_set_op,
3008         .vlan_offload_set = bnxt_vlan_offload_set_op,
3009         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3010         .mtu_set = bnxt_mtu_set_op,
3011         .mac_addr_set = bnxt_set_default_mac_addr_op,
3012         .xstats_get = bnxt_dev_xstats_get_op,
3013         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3014         .xstats_reset = bnxt_dev_xstats_reset_op,
3015         .fw_version_get = bnxt_fw_version_get,
3016         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3017         .rxq_info_get = bnxt_rxq_info_get_op,
3018         .txq_info_get = bnxt_txq_info_get_op,
3019         .dev_led_on = bnxt_dev_led_on_op,
3020         .dev_led_off = bnxt_dev_led_off_op,
3021         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3022         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3023         .rx_queue_count = bnxt_rx_queue_count_op,
3024         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3025         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3026         .filter_ctrl = bnxt_filter_ctrl_op,
3027         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3028         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3029         .get_eeprom           = bnxt_get_eeprom_op,
3030         .set_eeprom           = bnxt_set_eeprom_op,
3031         .timesync_enable      = bnxt_timesync_enable,
3032         .timesync_disable     = bnxt_timesync_disable,
3033         .timesync_read_time   = bnxt_timesync_read_time,
3034         .timesync_write_time   = bnxt_timesync_write_time,
3035         .timesync_adjust_time = bnxt_timesync_adjust_time,
3036         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3037         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3038 };
3039
3040 static bool bnxt_vf_pciid(uint16_t id)
3041 {
3042         if (id == BROADCOM_DEV_ID_57304_VF ||
3043             id == BROADCOM_DEV_ID_57406_VF ||
3044             id == BROADCOM_DEV_ID_5731X_VF ||
3045             id == BROADCOM_DEV_ID_5741X_VF ||
3046             id == BROADCOM_DEV_ID_57414_VF ||
3047             id == BROADCOM_DEV_ID_STRATUS_NIC_VF)
3048                 return true;
3049         return false;
3050 }
3051
3052 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3053 {
3054         struct bnxt *bp = eth_dev->data->dev_private;
3055         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3056         int rc;
3057
3058         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3059         if (!pci_dev->mem_resource[0].addr) {
3060                 RTE_LOG(ERR, PMD,
3061                         "Cannot find PCI device base address, aborting\n");
3062                 rc = -ENODEV;
3063                 goto init_err_disable;
3064         }
3065
3066         bp->eth_dev = eth_dev;
3067         bp->pdev = pci_dev;
3068
3069         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3070         if (!bp->bar0) {
3071                 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
3072                 rc = -ENOMEM;
3073                 goto init_err_release;
3074         }
3075         return 0;
3076
3077 init_err_release:
3078         if (bp->bar0)
3079                 bp->bar0 = NULL;
3080
3081 init_err_disable:
3082
3083         return rc;
3084 }
3085
3086 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
3087
3088 #define ALLOW_FUNC(x)   \
3089         { \
3090                 typeof(x) arg = (x); \
3091                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3092                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3093         }
3094 static int
3095 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3096 {
3097         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3098         char mz_name[RTE_MEMZONE_NAMESIZE];
3099         const struct rte_memzone *mz = NULL;
3100         static int version_printed;
3101         uint32_t total_alloc_len;
3102         rte_iova_t mz_phys_addr;
3103         struct bnxt *bp;
3104         int rc;
3105
3106         if (version_printed++ == 0)
3107                 RTE_LOG(INFO, PMD, "%s\n", bnxt_version);
3108
3109         rte_eth_copy_pci_info(eth_dev, pci_dev);
3110
3111         bp = eth_dev->data->dev_private;
3112
3113         rte_atomic64_init(&bp->rx_mbuf_alloc_fail);
3114         bp->dev_stopped = 1;
3115
3116         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3117                 goto skip_init;
3118
3119         if (bnxt_vf_pciid(pci_dev->id.device_id))
3120                 bp->flags |= BNXT_FLAG_VF;
3121
3122         rc = bnxt_init_board(eth_dev);
3123         if (rc) {
3124                 RTE_LOG(ERR, PMD,
3125                         "Board initialization failed rc: %x\n", rc);
3126                 goto error;
3127         }
3128 skip_init:
3129         eth_dev->dev_ops = &bnxt_dev_ops;
3130         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3131                 return 0;
3132         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3133         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3134
3135         if (BNXT_PF(bp) && pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3136                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3137                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3138                          pci_dev->addr.bus, pci_dev->addr.devid,
3139                          pci_dev->addr.function, "rx_port_stats");
3140                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3141                 mz = rte_memzone_lookup(mz_name);
3142                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3143                                 sizeof(struct rx_port_stats) + 512);
3144                 if (!mz) {
3145                         mz = rte_memzone_reserve(mz_name, total_alloc_len,
3146                                                  SOCKET_ID_ANY,
3147                                                  RTE_MEMZONE_2MB |
3148                                                  RTE_MEMZONE_SIZE_HINT_ONLY);
3149                         if (mz == NULL)
3150                                 return -ENOMEM;
3151                 }
3152                 memset(mz->addr, 0, mz->len);
3153                 mz_phys_addr = mz->iova;
3154                 if ((unsigned long)mz->addr == mz_phys_addr) {
3155                         RTE_LOG(WARNING, PMD,
3156                                 "Memzone physical address same as virtual.\n");
3157                         RTE_LOG(WARNING, PMD,
3158                                 "Using rte_mem_virt2iova()\n");
3159                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3160                         if (mz_phys_addr == 0) {
3161                                 RTE_LOG(ERR, PMD,
3162                                 "unable to map address to physical memory\n");
3163                                 return -ENOMEM;
3164                         }
3165                 }
3166
3167                 bp->rx_mem_zone = (const void *)mz;
3168                 bp->hw_rx_port_stats = mz->addr;
3169                 bp->hw_rx_port_stats_map = mz_phys_addr;
3170
3171                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3172                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3173                          pci_dev->addr.bus, pci_dev->addr.devid,
3174                          pci_dev->addr.function, "tx_port_stats");
3175                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3176                 mz = rte_memzone_lookup(mz_name);
3177                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3178                                 sizeof(struct tx_port_stats) + 512);
3179                 if (!mz) {
3180                         mz = rte_memzone_reserve(mz_name, total_alloc_len,
3181                                                  SOCKET_ID_ANY,
3182                                                  RTE_MEMZONE_2MB |
3183                                                  RTE_MEMZONE_SIZE_HINT_ONLY);
3184                         if (mz == NULL)
3185                                 return -ENOMEM;
3186                 }
3187                 memset(mz->addr, 0, mz->len);
3188                 mz_phys_addr = mz->iova;
3189                 if ((unsigned long)mz->addr == mz_phys_addr) {
3190                         RTE_LOG(WARNING, PMD,
3191                                 "Memzone physical address same as virtual.\n");
3192                         RTE_LOG(WARNING, PMD,
3193                                 "Using rte_mem_virt2iova()\n");
3194                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3195                         if (mz_phys_addr == 0) {
3196                                 RTE_LOG(ERR, PMD,
3197                                 "unable to map address to physical memory\n");
3198                                 return -ENOMEM;
3199                         }
3200                 }
3201
3202                 bp->tx_mem_zone = (const void *)mz;
3203                 bp->hw_tx_port_stats = mz->addr;
3204                 bp->hw_tx_port_stats_map = mz_phys_addr;
3205
3206                 bp->flags |= BNXT_FLAG_PORT_STATS;
3207         }
3208
3209         rc = bnxt_alloc_hwrm_resources(bp);
3210         if (rc) {
3211                 RTE_LOG(ERR, PMD,
3212                         "hwrm resource allocation failure rc: %x\n", rc);
3213                 goto error_free;
3214         }
3215         rc = bnxt_hwrm_ver_get(bp);
3216         if (rc)
3217                 goto error_free;
3218         rc = bnxt_hwrm_queue_qportcfg(bp);
3219         if (rc) {
3220                 RTE_LOG(ERR, PMD, "hwrm queue qportcfg failed\n");
3221                 goto error_free;
3222         }
3223
3224         rc = bnxt_hwrm_func_qcfg(bp);
3225         if (rc) {
3226                 RTE_LOG(ERR, PMD, "hwrm func qcfg failed\n");
3227                 goto error_free;
3228         }
3229
3230         /* Get the MAX capabilities for this function */
3231         rc = bnxt_hwrm_func_qcaps(bp);
3232         if (rc) {
3233                 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
3234                 goto error_free;
3235         }
3236         if (bp->max_tx_rings == 0) {
3237                 RTE_LOG(ERR, PMD, "No TX rings available!\n");
3238                 rc = -EBUSY;
3239                 goto error_free;
3240         }
3241         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3242                                         ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3243         if (eth_dev->data->mac_addrs == NULL) {
3244                 RTE_LOG(ERR, PMD,
3245                         "Failed to alloc %u bytes needed to store MAC addr tbl",
3246                         ETHER_ADDR_LEN * bp->max_l2_ctx);
3247                 rc = -ENOMEM;
3248                 goto error_free;
3249         }
3250         /* Copy the permanent MAC from the qcap response address now. */
3251         memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3252         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
3253
3254         if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3255                 /* 1 ring is for default completion ring */
3256                 RTE_LOG(ERR, PMD, "Insufficient resource: Ring Group\n");
3257                 rc = -ENOSPC;
3258                 goto error_free;
3259         }
3260
3261         bp->grp_info = rte_zmalloc("bnxt_grp_info",
3262                                 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3263         if (!bp->grp_info) {
3264                 RTE_LOG(ERR, PMD,
3265                         "Failed to alloc %zu bytes to store group info table\n",
3266                         sizeof(*bp->grp_info) * bp->max_ring_grps);
3267                 rc = -ENOMEM;
3268                 goto error_free;
3269         }
3270
3271         /* Forward all requests if firmware is new enough */
3272         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3273             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3274             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3275                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3276         } else {
3277                 RTE_LOG(WARNING, PMD,
3278                         "Firmware too old for VF mailbox functionality\n");
3279                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3280         }
3281
3282         /*
3283          * The following are used for driver cleanup.  If we disallow these,
3284          * VF drivers can't clean up cleanly.
3285          */
3286         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3287         ALLOW_FUNC(HWRM_VNIC_FREE);
3288         ALLOW_FUNC(HWRM_RING_FREE);
3289         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3290         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3291         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3292         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3293         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3294         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3295         rc = bnxt_hwrm_func_driver_register(bp);
3296         if (rc) {
3297                 RTE_LOG(ERR, PMD,
3298                         "Failed to register driver");
3299                 rc = -EBUSY;
3300                 goto error_free;
3301         }
3302
3303         RTE_LOG(INFO, PMD,
3304                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3305                 pci_dev->mem_resource[0].phys_addr,
3306                 pci_dev->mem_resource[0].addr);
3307
3308         rc = bnxt_hwrm_func_reset(bp);
3309         if (rc) {
3310                 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
3311                 rc = -EIO;
3312                 goto error_free;
3313         }
3314
3315         if (BNXT_PF(bp)) {
3316                 //if (bp->pf.active_vfs) {
3317                         // TODO: Deallocate VF resources?
3318                 //}
3319                 if (bp->pdev->max_vfs) {
3320                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3321                         if (rc) {
3322                                 RTE_LOG(ERR, PMD, "Failed to allocate VFs\n");
3323                                 goto error_free;
3324                         }
3325                 } else {
3326                         rc = bnxt_hwrm_allocate_pf_only(bp);
3327                         if (rc) {
3328                                 RTE_LOG(ERR, PMD,
3329                                         "Failed to allocate PF resources\n");
3330                                 goto error_free;
3331                         }
3332                 }
3333         }
3334
3335         bnxt_hwrm_port_led_qcaps(bp);
3336
3337         rc = bnxt_setup_int(bp);
3338         if (rc)
3339                 goto error_free;
3340
3341         rc = bnxt_alloc_mem(bp);
3342         if (rc)
3343                 goto error_free_int;
3344
3345         rc = bnxt_request_int(bp);
3346         if (rc)
3347                 goto error_free_int;
3348
3349         rc = bnxt_alloc_def_cp_ring(bp);
3350         if (rc)
3351                 goto error_free_int;
3352
3353         bnxt_enable_int(bp);
3354
3355         return 0;
3356
3357 error_free_int:
3358         bnxt_disable_int(bp);
3359         bnxt_free_def_cp_ring(bp);
3360         bnxt_hwrm_func_buf_unrgtr(bp);
3361         bnxt_free_int(bp);
3362         bnxt_free_mem(bp);
3363 error_free:
3364         bnxt_dev_uninit(eth_dev);
3365 error:
3366         return rc;
3367 }
3368
3369 static int
3370 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
3371         struct bnxt *bp = eth_dev->data->dev_private;
3372         int rc;
3373
3374         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3375                 return -EPERM;
3376
3377         bnxt_disable_int(bp);
3378         bnxt_free_int(bp);
3379         bnxt_free_mem(bp);
3380         if (eth_dev->data->mac_addrs != NULL) {
3381                 rte_free(eth_dev->data->mac_addrs);
3382                 eth_dev->data->mac_addrs = NULL;
3383         }
3384         if (bp->grp_info != NULL) {
3385                 rte_free(bp->grp_info);
3386                 bp->grp_info = NULL;
3387         }
3388         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3389         bnxt_free_hwrm_resources(bp);
3390         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3391         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3392         if (bp->dev_stopped == 0)
3393                 bnxt_dev_close_op(eth_dev);
3394         if (bp->pf.vf_info)
3395                 rte_free(bp->pf.vf_info);
3396         eth_dev->dev_ops = NULL;
3397         eth_dev->rx_pkt_burst = NULL;
3398         eth_dev->tx_pkt_burst = NULL;
3399
3400         return rc;
3401 }
3402
3403 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3404         struct rte_pci_device *pci_dev)
3405 {
3406         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3407                 bnxt_dev_init);
3408 }
3409
3410 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3411 {
3412         return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
3413 }
3414
3415 static struct rte_pci_driver bnxt_rte_pmd = {
3416         .id_table = bnxt_pci_id_map,
3417         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3418                 RTE_PCI_DRV_INTR_LSC,
3419         .probe = bnxt_pci_probe,
3420         .remove = bnxt_pci_remove,
3421 };
3422
3423 static bool
3424 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3425 {
3426         if (strcmp(dev->device->driver->name, drv->driver.name))
3427                 return false;
3428
3429         return true;
3430 }
3431
3432 bool is_bnxt_supported(struct rte_eth_dev *dev)
3433 {
3434         return is_device_supported(dev, &bnxt_rte_pmd);
3435 }
3436
3437 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3438 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3439 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");