drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 /*
  37  * The set of PCI devices this driver supports
  38  */
  39 static const struct rte_pci_id bnxt_pci_id_map[] = {
  40         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  41                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  93         { .vendor_id = 0, /* sentinel */ },
  94 };
  95
  96 #define BNXT_ETH_RSS_SUPPORT (  \
  97         ETH_RSS_IPV4 |          \
  98         ETH_RSS_NONFRAG_IPV4_TCP |      \
  99         ETH_RSS_NONFRAG_IPV4_UDP |      \
 100         ETH_RSS_IPV6 |          \
 101         ETH_RSS_NONFRAG_IPV6_TCP |      \
 102         ETH_RSS_NONFRAG_IPV6_UDP)
 103
 104 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 105                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 106                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 108                                      DEV_TX_OFFLOAD_TCP_TSO | \
 109                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 110                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 114                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 115                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 116
 117 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 118                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 119                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 120                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 122                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 123                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 124                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 125                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 126                                      DEV_RX_OFFLOAD_TCP_LRO | \
 127                                      DEV_RX_OFFLOAD_SCATTER | \
 128                                      DEV_RX_OFFLOAD_RSS_HASH)
 129
 130 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
 131 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 132 static const char *const bnxt_dev_args[] = {
 133         BNXT_DEVARG_TRUFLOW,
 134         BNXT_DEVARG_FLOW_XSTAT,
 135         NULL
 136 };
 137
 138 /*
 139  * truflow == false to disable the feature
 140  * truflow == true to enable the feature
 141  */
 142 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 143
 144 /*
 145  * flow_xstat == false to disable the feature
 146  * flow_xstat == true to enable the feature
 147  */
 148 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 149
 150 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 151 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 152 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 153 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 154 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 155 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 156 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 157 static void bnxt_dev_recover(void *arg);
 158 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 159
 160 int is_bnxt_in_error(struct bnxt *bp)
 161 {
 162         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 163                 return -EIO;
 164         if (bp->flags & BNXT_FLAG_FW_RESET)
 165                 return -EBUSY;
 166
 167         return 0;
 168 }
 169
 170 /***********************/
 171
 172 /*
 173  * High level utility functions
 174  */
 175
 176 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 177 {
 178         if (!BNXT_CHIP_THOR(bp))
 179                 return 1;
 180
 181         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 182                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 183                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 184 }
 185
 186 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 187 {
 188         if (!BNXT_CHIP_THOR(bp))
 189                 return HW_HASH_INDEX_SIZE;
 190
 191         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 192 }
 193
 194 static void bnxt_free_leds_info(struct bnxt *bp)
 195 {
 196         rte_free(bp->leds);
 197         bp->leds = NULL;
 198 }
 199
 200 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 201 {
 202         bnxt_free_filter_mem(bp);
 203         bnxt_free_vnic_attributes(bp);
 204         bnxt_free_vnic_mem(bp);
 205
 206         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 207          * If the number of rings change across fw update,
 208          * we don't have much choice except to warn the user.
 209          */
 210         if (!reconfig) {
 211                 bnxt_free_stats(bp);
 212                 bnxt_free_tx_rings(bp);
 213                 bnxt_free_rx_rings(bp);
 214         }
 215         bnxt_free_async_cp_ring(bp);
 216         bnxt_free_rxtx_nq_ring(bp);
 217
 218         rte_free(bp->grp_info);
 219         bp->grp_info = NULL;
 220 }
 221
 222 static int bnxt_alloc_leds_info(struct bnxt *bp)
 223 {
 224         bp->leds = rte_zmalloc("bnxt_leds",
 225                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 226                                0);
 227         if (bp->leds == NULL)
 228                 return -ENOMEM;
 229
 230         return 0;
 231 }
 232
 233 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 234 {
 235         int rc;
 236
 237         rc = bnxt_alloc_ring_grps(bp);
 238         if (rc)
 239                 goto alloc_mem_err;
 240
 241         rc = bnxt_alloc_async_ring_struct(bp);
 242         if (rc)
 243                 goto alloc_mem_err;
 244
 245         rc = bnxt_alloc_vnic_mem(bp);
 246         if (rc)
 247                 goto alloc_mem_err;
 248
 249         rc = bnxt_alloc_vnic_attributes(bp);
 250         if (rc)
 251                 goto alloc_mem_err;
 252
 253         rc = bnxt_alloc_filter_mem(bp);
 254         if (rc)
 255                 goto alloc_mem_err;
 256
 257         rc = bnxt_alloc_async_cp_ring(bp);
 258         if (rc)
 259                 goto alloc_mem_err;
 260
 261         rc = bnxt_alloc_rxtx_nq_ring(bp);
 262         if (rc)
 263                 goto alloc_mem_err;
 264
 265         return 0;
 266
 267 alloc_mem_err:
 268         bnxt_free_mem(bp, reconfig);
 269         return rc;
 270 }
 271
 272 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 273 {
 274         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 275         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 276         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 277         struct bnxt_rx_queue *rxq;
 278         unsigned int j;
 279         int rc;
 280
 281         rc = bnxt_vnic_grp_alloc(bp, vnic);
 282         if (rc)
 283                 goto err_out;
 284
 285         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 286                     vnic_id, vnic, vnic->fw_grp_ids);
 287
 288         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 289         if (rc)
 290                 goto err_out;
 291
 292         /* Alloc RSS context only if RSS mode is enabled */
 293         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 294                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 295
 296                 rc = 0;
 297                 for (j = 0; j < nr_ctxs; j++) {
 298                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 299                         if (rc)
 300                                 break;
 301                 }
 302                 if (rc) {
 303                         PMD_DRV_LOG(ERR,
 304                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 305                                     vnic_id, j, rc);
 306                         goto err_out;
 307                 }
 308                 vnic->num_lb_ctxts = nr_ctxs;
 309         }
 310
 311         /*
 312          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 313          * setting is not available at this time, it will not be
 314          * configured correctly in the CFA.
 315          */
 316         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 317                 vnic->vlan_strip = true;
 318         else
 319                 vnic->vlan_strip = false;
 320
 321         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 322         if (rc)
 323                 goto err_out;
 324
 325         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 326         if (rc)
 327                 goto err_out;
 328
 329         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 330                 rxq = bp->eth_dev->data->rx_queues[j];
 331
 332                 PMD_DRV_LOG(DEBUG,
 333                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 334                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 335
 336                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 337                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 338                 else
 339                         vnic->rx_queue_cnt++;
 340         }
 341
 342         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 343
 344         rc = bnxt_vnic_rss_configure(bp, vnic);
 345         if (rc)
 346                 goto err_out;
 347
 348         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 349
 350         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 351                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 352         else
 353                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 354
 355         return 0;
 356 err_out:
 357         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 358                     vnic_id, rc);
 359         return rc;
 360 }
 361
 362 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 363 {
 364         int rc = 0;
 365
 366         rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_in_tbl.dma,
 367                                 &bp->rx_fc_in_tbl.ctx_id);
 368         if (rc)
 369                 return rc;
 370
 371         PMD_DRV_LOG(DEBUG,
 372                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 373                     " rx_fc_in_tbl.ctx_id = %d\n",
 374                     bp->rx_fc_in_tbl.va,
 375                     (void *)((uintptr_t)bp->rx_fc_in_tbl.dma),
 376                     bp->rx_fc_in_tbl.ctx_id);
 377
 378         rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_out_tbl.dma,
 379                                 &bp->rx_fc_out_tbl.ctx_id);
 380         if (rc)
 381                 return rc;
 382
 383         PMD_DRV_LOG(DEBUG,
 384                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 385                     " rx_fc_out_tbl.ctx_id = %d\n",
 386                     bp->rx_fc_out_tbl.va,
 387                     (void *)((uintptr_t)bp->rx_fc_out_tbl.dma),
 388                     bp->rx_fc_out_tbl.ctx_id);
 389
 390         rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_in_tbl.dma,
 391                                 &bp->tx_fc_in_tbl.ctx_id);
 392         if (rc)
 393                 return rc;
 394
 395         PMD_DRV_LOG(DEBUG,
 396                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 397                     " tx_fc_in_tbl.ctx_id = %d\n",
 398                     bp->tx_fc_in_tbl.va,
 399                     (void *)((uintptr_t)bp->tx_fc_in_tbl.dma),
 400                     bp->tx_fc_in_tbl.ctx_id);
 401
 402         rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_out_tbl.dma,
 403                                 &bp->tx_fc_out_tbl.ctx_id);
 404         if (rc)
 405                 return rc;
 406
 407         PMD_DRV_LOG(DEBUG,
 408                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 409                     " tx_fc_out_tbl.ctx_id = %d\n",
 410                     bp->tx_fc_out_tbl.va,
 411                     (void *)((uintptr_t)bp->tx_fc_out_tbl.dma),
 412                     bp->tx_fc_out_tbl.ctx_id);
 413
 414         memset(bp->rx_fc_out_tbl.va, 0, bp->rx_fc_out_tbl.size);
 415         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 416                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 417                                        bp->rx_fc_out_tbl.ctx_id,
 418                                        bp->max_fc,
 419                                        true);
 420         if (rc)
 421                 return rc;
 422
 423         memset(bp->tx_fc_out_tbl.va, 0, bp->tx_fc_out_tbl.size);
 424         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 425                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 426                                        bp->tx_fc_out_tbl.ctx_id,
 427                                        bp->max_fc,
 428                                        true);
 429
 430         return rc;
 431 }
 432
 433 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 434                                   struct bnxt_ctx_mem_buf_info *ctx)
 435 {
 436         if (!ctx)
 437                 return -EINVAL;
 438
 439         ctx->va = rte_zmalloc(type, size, 0);
 440         if (ctx->va == NULL)
 441                 return -ENOMEM;
 442         rte_mem_lock_page(ctx->va);
 443         ctx->size = size;
 444         ctx->dma = rte_mem_virt2iova(ctx->va);
 445         if (ctx->dma == RTE_BAD_IOVA)
 446                 return -ENOMEM;
 447
 448         return 0;
 449 }
 450
 451 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 452 {
 453         struct rte_pci_device *pdev = bp->pdev;
 454         char type[RTE_MEMZONE_NAMESIZE];
 455         uint16_t max_fc;
 456         int rc = 0;
 457
 458         max_fc = bp->max_fc;
 459
 460         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 461                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 462         /* 4 bytes for each counter-id */
 463         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->rx_fc_in_tbl);
 464         if (rc)
 465                 return rc;
 466
 467         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 468                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 469         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 470         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->rx_fc_out_tbl);
 471         if (rc)
 472                 return rc;
 473
 474         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 475                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 476         /* 4 bytes for each counter-id */
 477         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->tx_fc_in_tbl);
 478         if (rc)
 479                 return rc;
 480
 481         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 482                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 483         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 484         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->tx_fc_out_tbl);
 485         if (rc)
 486                 return rc;
 487
 488         rc = bnxt_register_fc_ctx_mem(bp);
 489
 490         return rc;
 491 }
 492
 493 static int bnxt_init_ctx_mem(struct bnxt *bp)
 494 {
 495         int rc = 0;
 496
 497         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 498             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
 499                 return 0;
 500
 501         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->max_fc);
 502         if (rc)
 503                 return rc;
 504
 505         rc = bnxt_init_fc_ctx_mem(bp);
 506
 507         return rc;
 508 }
 509
 510 static int bnxt_init_chip(struct bnxt *bp)
 511 {
 512         struct rte_eth_link new;
 513         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 514         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 515         uint32_t intr_vector = 0;
 516         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 517         uint32_t vec = BNXT_MISC_VEC_ID;
 518         unsigned int i, j;
 519         int rc;
 520
 521         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 522                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 523                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 524                 bp->flags |= BNXT_FLAG_JUMBO;
 525         } else {
 526                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 527                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 528                 bp->flags &= ~BNXT_FLAG_JUMBO;
 529         }
 530
 531         /* THOR does not support ring groups.
 532          * But we will use the array to save RSS context IDs.
 533          */
 534         if (BNXT_CHIP_THOR(bp))
 535                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 536
 537         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 538         if (rc) {
 539                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 540                 goto err_out;
 541         }
 542
 543         rc = bnxt_alloc_hwrm_rings(bp);
 544         if (rc) {
 545                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 546                 goto err_out;
 547         }
 548
 549         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 550         if (rc) {
 551                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 552                 goto err_out;
 553         }
 554
 555         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 556                 goto skip_cosq_cfg;
 557
 558         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 559                 if (bp->rx_cos_queue[i].id != 0xff) {
 560                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 561
 562                         if (!vnic) {
 563                                 PMD_DRV_LOG(ERR,
 564                                             "Num pools more than FW profile\n");
 565                                 rc = -EINVAL;
 566                                 goto err_out;
 567                         }
 568                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 569                         bp->rx_cosq_cnt++;
 570                 }
 571         }
 572
 573 skip_cosq_cfg:
 574         rc = bnxt_mq_rx_configure(bp);
 575         if (rc) {
 576                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 577                 goto err_out;
 578         }
 579
 580         /* VNIC configuration */
 581         for (i = 0; i < bp->nr_vnics; i++) {
 582                 rc = bnxt_setup_one_vnic(bp, i);
 583                 if (rc)
 584                         goto err_out;
 585         }
 586
 587         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 588         if (rc) {
 589                 PMD_DRV_LOG(ERR,
 590                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 591                 goto err_out;
 592         }
 593
 594         /* check and configure queue intr-vector mapping */
 595         if ((rte_intr_cap_multiple(intr_handle) ||
 596              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 597             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 598                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 599                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 600                 if (intr_vector > bp->rx_cp_nr_rings) {
 601                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 602                                         bp->rx_cp_nr_rings);
 603                         return -ENOTSUP;
 604                 }
 605                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 606                 if (rc)
 607                         return rc;
 608         }
 609
 610         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 611                 intr_handle->intr_vec =
 612                         rte_zmalloc("intr_vec",
 613                                     bp->eth_dev->data->nb_rx_queues *
 614                                     sizeof(int), 0);
 615                 if (intr_handle->intr_vec == NULL) {
 616                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 617                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 618                         rc = -ENOMEM;
 619                         goto err_disable;
 620                 }
 621                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 622                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 623                          intr_handle->intr_vec, intr_handle->nb_efd,
 624                         intr_handle->max_intr);
 625                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 626                      queue_id++) {
 627                         intr_handle->intr_vec[queue_id] =
 628                                                         vec + BNXT_RX_VEC_START;
 629                         if (vec < base + intr_handle->nb_efd - 1)
 630                                 vec++;
 631                 }
 632         }
 633
 634         /* enable uio/vfio intr/eventfd mapping */
 635         rc = rte_intr_enable(intr_handle);
 636 #ifndef RTE_EXEC_ENV_FREEBSD
 637         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 638         if (rc)
 639                 goto err_free;
 640 #endif
 641
 642         rc = bnxt_get_hwrm_link_config(bp, &new);
 643         if (rc) {
 644                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 645                 goto err_free;
 646         }
 647
 648         if (!bp->link_info.link_up) {
 649                 rc = bnxt_set_hwrm_link_config(bp, true);
 650                 if (rc) {
 651                         PMD_DRV_LOG(ERR,
 652                                 "HWRM link config failure rc: %x\n", rc);
 653                         goto err_free;
 654                 }
 655         }
 656         bnxt_print_link_info(bp->eth_dev);
 657
 658         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 659         if (!bp->mark_table)
 660                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 661
 662         return 0;
 663
 664 err_free:
 665         rte_free(intr_handle->intr_vec);
 666 err_disable:
 667         rte_intr_efd_disable(intr_handle);
 668 err_out:
 669         /* Some of the error status returned by FW may not be from errno.h */
 670         if (rc > 0)
 671                 rc = -EIO;
 672
 673         return rc;
 674 }
 675
 676 static int bnxt_shutdown_nic(struct bnxt *bp)
 677 {
 678         bnxt_free_all_hwrm_resources(bp);
 679         bnxt_free_all_filters(bp);
 680         bnxt_free_all_vnics(bp);
 681         return 0;
 682 }
 683
 684 /*
 685  * Device configuration and status function
 686  */
 687
 688 static uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 689 {
 690         uint32_t link_speed = bp->link_info.support_speeds;
 691         uint32_t speed_capa = 0;
 692
 693         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 694                 speed_capa |= ETH_LINK_SPEED_100M;
 695         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 696                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 697         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 698                 speed_capa |= ETH_LINK_SPEED_1G;
 699         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 700                 speed_capa |= ETH_LINK_SPEED_2_5G;
 701         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 702                 speed_capa |= ETH_LINK_SPEED_10G;
 703         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 704                 speed_capa |= ETH_LINK_SPEED_20G;
 705         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 706                 speed_capa |= ETH_LINK_SPEED_25G;
 707         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 708                 speed_capa |= ETH_LINK_SPEED_40G;
 709         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 710                 speed_capa |= ETH_LINK_SPEED_50G;
 711         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 712                 speed_capa |= ETH_LINK_SPEED_100G;
 713         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
 714                 speed_capa |= ETH_LINK_SPEED_200G;
 715
 716         if (bp->link_info.auto_mode == HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 717                 speed_capa |= ETH_LINK_SPEED_FIXED;
 718         else
 719                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 720
 721         return speed_capa;
 722 }
 723
 724 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 725                                 struct rte_eth_dev_info *dev_info)
 726 {
 727         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 728         struct bnxt *bp = eth_dev->data->dev_private;
 729         uint16_t max_vnics, i, j, vpool, vrxq;
 730         unsigned int max_rx_rings;
 731         int rc;
 732
 733         rc = is_bnxt_in_error(bp);
 734         if (rc)
 735                 return rc;
 736
 737         /* MAC Specifics */
 738         dev_info->max_mac_addrs = bp->max_l2_ctx;
 739         dev_info->max_hash_mac_addrs = 0;
 740
 741         /* PF/VF specifics */
 742         if (BNXT_PF(bp))
 743                 dev_info->max_vfs = pdev->max_vfs;
 744
 745         max_rx_rings = BNXT_MAX_RINGS(bp);
 746         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 747         dev_info->max_rx_queues = max_rx_rings;
 748         dev_info->max_tx_queues = max_rx_rings;
 749         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 750         dev_info->hash_key_size = 40;
 751         max_vnics = bp->max_vnics;
 752
 753         /* MTU specifics */
 754         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 755         dev_info->max_mtu = BNXT_MAX_MTU;
 756
 757         /* Fast path specifics */
 758         dev_info->min_rx_bufsize = 1;
 759         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 760
 761         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 762         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 763                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 764         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 765         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 766
 767         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 768
 769         /* *INDENT-OFF* */
 770         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 771                 .rx_thresh = {
 772                         .pthresh = 8,
 773                         .hthresh = 8,
 774                         .wthresh = 0,
 775                 },
 776                 .rx_free_thresh = 32,
 777                 /* If no descriptors available, pkts are dropped by default */
 778                 .rx_drop_en = 1,
 779         };
 780
 781         dev_info->default_txconf = (struct rte_eth_txconf) {
 782                 .tx_thresh = {
 783                         .pthresh = 32,
 784                         .hthresh = 0,
 785                         .wthresh = 0,
 786                 },
 787                 .tx_free_thresh = 32,
 788                 .tx_rs_thresh = 32,
 789         };
 790         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 791
 792         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 793         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 794         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 795         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 796         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 797
 798         /* *INDENT-ON* */
 799
 800         /*
 801          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 802          *       need further investigation.
 803          */
 804
 805         /* VMDq resources */
 806         vpool = 64; /* ETH_64_POOLS */
 807         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 808         for (i = 0; i < 4; vpool >>= 1, i++) {
 809                 if (max_vnics > vpool) {
 810                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 811                                 if (dev_info->max_rx_queues > vrxq) {
 812                                         if (vpool > vrxq)
 813                                                 vpool = vrxq;
 814                                         goto found;
 815                                 }
 816                         }
 817                         /* Not enough resources to support VMDq */
 818                         break;
 819                 }
 820         }
 821         /* Not enough resources to support VMDq */
 822         vpool = 0;
 823         vrxq = 0;
 824 found:
 825         dev_info->max_vmdq_pools = vpool;
 826         dev_info->vmdq_queue_num = vrxq;
 827
 828         dev_info->vmdq_pool_base = 0;
 829         dev_info->vmdq_queue_base = 0;
 830
 831         return 0;
 832 }
 833
 834 /* Configure the device based on the configuration provided */
 835 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 836 {
 837         struct bnxt *bp = eth_dev->data->dev_private;
 838         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 839         int rc;
 840
 841         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 842         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 843         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 844         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 845
 846         rc = is_bnxt_in_error(bp);
 847         if (rc)
 848                 return rc;
 849
 850         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 851                 rc = bnxt_hwrm_check_vf_rings(bp);
 852                 if (rc) {
 853                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 854                         return -ENOSPC;
 855                 }
 856
 857                 /* If a resource has already been allocated - in this case
 858                  * it is the async completion ring, free it. Reallocate it after
 859                  * resource reservation. This will ensure the resource counts
 860                  * are calculated correctly.
 861                  */
 862
 863                 pthread_mutex_lock(&bp->def_cp_lock);
 864
 865                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 866                         bnxt_disable_int(bp);
 867                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 868                 }
 869
 870                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 871                 if (rc) {
 872                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 873                         pthread_mutex_unlock(&bp->def_cp_lock);
 874                         return -ENOSPC;
 875                 }
 876
 877                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 878                         rc = bnxt_alloc_async_cp_ring(bp);
 879                         if (rc) {
 880                                 pthread_mutex_unlock(&bp->def_cp_lock);
 881                                 return rc;
 882                         }
 883                         bnxt_enable_int(bp);
 884                 }
 885
 886                 pthread_mutex_unlock(&bp->def_cp_lock);
 887         } else {
 888                 /* legacy driver needs to get updated values */
 889                 rc = bnxt_hwrm_func_qcaps(bp);
 890                 if (rc) {
 891                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 892                         return rc;
 893                 }
 894         }
 895
 896         /* Inherit new configurations */
 897         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 898             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 899             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 900                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 901             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 902             bp->max_stat_ctx)
 903                 goto resource_error;
 904
 905         if (BNXT_HAS_RING_GRPS(bp) &&
 906             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 907                 goto resource_error;
 908
 909         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 910             bp->max_vnics < eth_dev->data->nb_rx_queues)
 911                 goto resource_error;
 912
 913         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 914         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 915
 916         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 917                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 918         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
 919
 920         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 921                 eth_dev->data->mtu =
 922                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 923                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 924                         BNXT_NUM_VLANS;
 925                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 926         }
 927         return 0;
 928
 929 resource_error:
 930         PMD_DRV_LOG(ERR,
 931                     "Insufficient resources to support requested config\n");
 932         PMD_DRV_LOG(ERR,
 933                     "Num Queues Requested: Tx %d, Rx %d\n",
 934                     eth_dev->data->nb_tx_queues,
 935                     eth_dev->data->nb_rx_queues);
 936         PMD_DRV_LOG(ERR,
 937                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 938                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 939                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 940         return -ENOSPC;
 941 }
 942
 943 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 944 {
 945         struct rte_eth_link *link = &eth_dev->data->dev_link;
 946
 947         if (link->link_status)
 948                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 949                         eth_dev->data->port_id,
 950                         (uint32_t)link->link_speed,
 951                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 952                         ("full-duplex") : ("half-duplex\n"));
 953         else
 954                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 955                         eth_dev->data->port_id);
 956 }
 957
 958 /*
 959  * Determine whether the current configuration requires support for scattered
 960  * receive; return 1 if scattered receive is required and 0 if not.
 961  */
 962 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 963 {
 964         uint16_t buf_size;
 965         int i;
 966
 967         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 968                 return 1;
 969
 970         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 971                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 972
 973                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 974                                       RTE_PKTMBUF_HEADROOM);
 975                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 976                         return 1;
 977         }
 978         return 0;
 979 }
 980
 981 static eth_rx_burst_t
 982 bnxt_receive_function(struct rte_eth_dev *eth_dev)
 983 {
 984         struct bnxt *bp = eth_dev->data->dev_private;
 985
 986 #ifdef RTE_ARCH_X86
 987 #ifndef RTE_LIBRTE_IEEE1588
 988         /*
 989          * Vector mode receive can be enabled only if scatter rx is not
 990          * in use and rx offloads are limited to VLAN stripping and
 991          * CRC stripping.
 992          */
 993         if (!eth_dev->data->scattered_rx &&
 994             !(eth_dev->data->dev_conf.rxmode.offloads &
 995               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 996                 DEV_RX_OFFLOAD_KEEP_CRC |
 997                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 998                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 999                 DEV_RX_OFFLOAD_UDP_CKSUM |
1000                 DEV_RX_OFFLOAD_TCP_CKSUM |
1001                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1002                 DEV_RX_OFFLOAD_RSS_HASH |
1003                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1004             !bp->truflow) {
1005                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1006                             eth_dev->data->port_id);
1007                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1008                 return bnxt_recv_pkts_vec;
1009         }
1010         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1011                     eth_dev->data->port_id);
1012         PMD_DRV_LOG(INFO,
1013                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1014                     eth_dev->data->port_id,
1015                     eth_dev->data->scattered_rx,
1016                     eth_dev->data->dev_conf.rxmode.offloads);
1017 #endif
1018 #endif
1019         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1020         return bnxt_recv_pkts;
1021 }
1022
1023 static eth_tx_burst_t
1024 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1025 {
1026 #ifdef RTE_ARCH_X86
1027 #ifndef RTE_LIBRTE_IEEE1588
1028         /*
1029          * Vector mode transmit can be enabled only if not using scatter rx
1030          * or tx offloads.
1031          */
1032         if (!eth_dev->data->scattered_rx &&
1033             !eth_dev->data->dev_conf.txmode.offloads) {
1034                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1035                             eth_dev->data->port_id);
1036                 return bnxt_xmit_pkts_vec;
1037         }
1038         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1039                     eth_dev->data->port_id);
1040         PMD_DRV_LOG(INFO,
1041                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1042                     eth_dev->data->port_id,
1043                     eth_dev->data->scattered_rx,
1044                     eth_dev->data->dev_conf.txmode.offloads);
1045 #endif
1046 #endif
1047         return bnxt_xmit_pkts;
1048 }
1049
1050 static int bnxt_handle_if_change_status(struct bnxt *bp)
1051 {
1052         int rc;
1053
1054         /* Since fw has undergone a reset and lost all contexts,
1055          * set fatal flag to not issue hwrm during cleanup
1056          */
1057         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1058         bnxt_uninit_resources(bp, true);
1059
1060         /* clear fatal flag so that re-init happens */
1061         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1062         rc = bnxt_init_resources(bp, true);
1063
1064         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1065
1066         return rc;
1067 }
1068
1069 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1070 {
1071         struct bnxt *bp = eth_dev->data->dev_private;
1072         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1073         int vlan_mask = 0;
1074         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1075
1076         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1077                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1078                 return -EINVAL;
1079         }
1080
1081         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1082                 PMD_DRV_LOG(ERR,
1083                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1084                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1085         }
1086
1087         do {
1088                 rc = bnxt_hwrm_if_change(bp, true);
1089                 if (rc == 0 || rc != -EAGAIN)
1090                         break;
1091
1092                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1093         } while (retry_cnt--);
1094
1095         if (rc)
1096                 return rc;
1097
1098         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1099                 rc = bnxt_handle_if_change_status(bp);
1100                 if (rc)
1101                         return rc;
1102         }
1103
1104         bnxt_enable_int(bp);
1105
1106         rc = bnxt_init_chip(bp);
1107         if (rc)
1108                 goto error;
1109
1110         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1111         eth_dev->data->dev_started = 1;
1112
1113         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1114
1115         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1116                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1117         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1118                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1119         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1120         if (rc)
1121                 goto error;
1122
1123         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1124         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1125
1126         pthread_mutex_lock(&bp->def_cp_lock);
1127         bnxt_schedule_fw_health_check(bp);
1128         pthread_mutex_unlock(&bp->def_cp_lock);
1129
1130         if (bp->truflow)
1131                 bnxt_ulp_init(bp);
1132
1133         return 0;
1134
1135 error:
1136         bnxt_shutdown_nic(bp);
1137         bnxt_free_tx_mbufs(bp);
1138         bnxt_free_rx_mbufs(bp);
1139         bnxt_hwrm_if_change(bp, false);
1140         eth_dev->data->dev_started = 0;
1141         return rc;
1142 }
1143
1144 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1145 {
1146         struct bnxt *bp = eth_dev->data->dev_private;
1147         int rc = 0;
1148
1149         if (!bp->link_info.link_up)
1150                 rc = bnxt_set_hwrm_link_config(bp, true);
1151         if (!rc)
1152                 eth_dev->data->dev_link.link_status = 1;
1153
1154         bnxt_print_link_info(eth_dev);
1155         return rc;
1156 }
1157
1158 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1159 {
1160         struct bnxt *bp = eth_dev->data->dev_private;
1161
1162         eth_dev->data->dev_link.link_status = 0;
1163         bnxt_set_hwrm_link_config(bp, false);
1164         bp->link_info.link_up = 0;
1165
1166         return 0;
1167 }
1168
1169 /* Unload the driver, release resources */
1170 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1171 {
1172         struct bnxt *bp = eth_dev->data->dev_private;
1173         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1174         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1175
1176         if (bp->truflow)
1177                 bnxt_ulp_deinit(bp);
1178
1179         eth_dev->data->dev_started = 0;
1180         /* Prevent crashes when queues are still in use */
1181         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1182         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1183
1184         bnxt_disable_int(bp);
1185
1186         /* disable uio/vfio intr/eventfd mapping */
1187         rte_intr_disable(intr_handle);
1188
1189         bnxt_cancel_fw_health_check(bp);
1190
1191         bnxt_dev_set_link_down_op(eth_dev);
1192
1193         /* Wait for link to be reset and the async notification to process.
1194          * During reset recovery, there is no need to wait and
1195          * VF/NPAR functions do not have privilege to change PHY config.
1196          */
1197         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1198                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1199
1200         /* Clean queue intr-vector mapping */
1201         rte_intr_efd_disable(intr_handle);
1202         if (intr_handle->intr_vec != NULL) {
1203                 rte_free(intr_handle->intr_vec);
1204                 intr_handle->intr_vec = NULL;
1205         }
1206
1207         bnxt_hwrm_port_clr_stats(bp);
1208         bnxt_free_tx_mbufs(bp);
1209         bnxt_free_rx_mbufs(bp);
1210         /* Process any remaining notifications in default completion queue */
1211         bnxt_int_handler(eth_dev);
1212         bnxt_shutdown_nic(bp);
1213         bnxt_hwrm_if_change(bp, false);
1214
1215         rte_free(bp->mark_table);
1216         bp->mark_table = NULL;
1217
1218         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1219         bp->rx_cosq_cnt = 0;
1220 }
1221
1222 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1223 {
1224         struct bnxt *bp = eth_dev->data->dev_private;
1225
1226         /* cancel the recovery handler before remove dev */
1227         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1228         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1229         bnxt_cancel_fc_thread(bp);
1230
1231         if (eth_dev->data->dev_started)
1232                 bnxt_dev_stop_op(eth_dev);
1233
1234         bnxt_uninit_resources(bp, false);
1235
1236         bnxt_free_leds_info(bp);
1237
1238         eth_dev->dev_ops = NULL;
1239         eth_dev->rx_pkt_burst = NULL;
1240         eth_dev->tx_pkt_burst = NULL;
1241
1242         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1243         bp->tx_mem_zone = NULL;
1244         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1245         bp->rx_mem_zone = NULL;
1246
1247         rte_free(bp->pf.vf_info);
1248         bp->pf.vf_info = NULL;
1249
1250         rte_free(bp->grp_info);
1251         bp->grp_info = NULL;
1252 }
1253
1254 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1255                                     uint32_t index)
1256 {
1257         struct bnxt *bp = eth_dev->data->dev_private;
1258         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1259         struct bnxt_vnic_info *vnic;
1260         struct bnxt_filter_info *filter, *temp_filter;
1261         uint32_t i;
1262
1263         if (is_bnxt_in_error(bp))
1264                 return;
1265
1266         /*
1267          * Loop through all VNICs from the specified filter flow pools to
1268          * remove the corresponding MAC addr filter
1269          */
1270         for (i = 0; i < bp->nr_vnics; i++) {
1271                 if (!(pool_mask & (1ULL << i)))
1272                         continue;
1273
1274                 vnic = &bp->vnic_info[i];
1275                 filter = STAILQ_FIRST(&vnic->filter);
1276                 while (filter) {
1277                         temp_filter = STAILQ_NEXT(filter, next);
1278                         if (filter->mac_index == index) {
1279                                 STAILQ_REMOVE(&vnic->filter, filter,
1280                                                 bnxt_filter_info, next);
1281                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1282                                 bnxt_free_filter(bp, filter);
1283                         }
1284                         filter = temp_filter;
1285                 }
1286         }
1287 }
1288
1289 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1290                                struct rte_ether_addr *mac_addr, uint32_t index,
1291                                uint32_t pool)
1292 {
1293         struct bnxt_filter_info *filter;
1294         int rc = 0;
1295
1296         /* Attach requested MAC address to the new l2_filter */
1297         STAILQ_FOREACH(filter, &vnic->filter, next) {
1298                 if (filter->mac_index == index) {
1299                         PMD_DRV_LOG(DEBUG,
1300                                     "MAC addr already existed for pool %d\n",
1301                                     pool);
1302                         return 0;
1303                 }
1304         }
1305
1306         filter = bnxt_alloc_filter(bp);
1307         if (!filter) {
1308                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1309                 return -ENODEV;
1310         }
1311
1312         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1313          * if the MAC that's been programmed now is a different one, then,
1314          * copy that addr to filter->l2_addr
1315          */
1316         if (mac_addr)
1317                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1318         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1319
1320         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1321         if (!rc) {
1322                 filter->mac_index = index;
1323                 if (filter->mac_index == 0)
1324                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1325                 else
1326                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1327         } else {
1328                 bnxt_free_filter(bp, filter);
1329         }
1330
1331         return rc;
1332 }
1333
1334 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1335                                 struct rte_ether_addr *mac_addr,
1336                                 uint32_t index, uint32_t pool)
1337 {
1338         struct bnxt *bp = eth_dev->data->dev_private;
1339         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1340         int rc = 0;
1341
1342         rc = is_bnxt_in_error(bp);
1343         if (rc)
1344                 return rc;
1345
1346         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1347                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1348                 return -ENOTSUP;
1349         }
1350
1351         if (!vnic) {
1352                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1353                 return -EINVAL;
1354         }
1355
1356         /* Filter settings will get applied when port is started */
1357         if (!eth_dev->data->dev_started)
1358                 return 0;
1359
1360         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1361
1362         return rc;
1363 }
1364
1365 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1366                      bool exp_link_status)
1367 {
1368         int rc = 0;
1369         struct bnxt *bp = eth_dev->data->dev_private;
1370         struct rte_eth_link new;
1371         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1372                   BNXT_LINK_DOWN_WAIT_CNT;
1373
1374         rc = is_bnxt_in_error(bp);
1375         if (rc)
1376                 return rc;
1377
1378         memset(&new, 0, sizeof(new));
1379         do {
1380                 /* Retrieve link info from hardware */
1381                 rc = bnxt_get_hwrm_link_config(bp, &new);
1382                 if (rc) {
1383                         new.link_speed = ETH_LINK_SPEED_100M;
1384                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1385                         PMD_DRV_LOG(ERR,
1386                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1387                         goto out;
1388                 }
1389
1390                 if (!wait_to_complete || new.link_status == exp_link_status)
1391                         break;
1392
1393                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1394         } while (cnt--);
1395
1396 out:
1397         /* Timed out or success */
1398         if (new.link_status != eth_dev->data->dev_link.link_status ||
1399         new.link_speed != eth_dev->data->dev_link.link_speed) {
1400                 rte_eth_linkstatus_set(eth_dev, &new);
1401
1402                 _rte_eth_dev_callback_process(eth_dev,
1403                                               RTE_ETH_EVENT_INTR_LSC,
1404                                               NULL);
1405
1406                 bnxt_print_link_info(eth_dev);
1407         }
1408
1409         return rc;
1410 }
1411
1412 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1413                                int wait_to_complete)
1414 {
1415         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1416 }
1417
1418 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1419 {
1420         struct bnxt *bp = eth_dev->data->dev_private;
1421         struct bnxt_vnic_info *vnic;
1422         uint32_t old_flags;
1423         int rc;
1424
1425         rc = is_bnxt_in_error(bp);
1426         if (rc)
1427                 return rc;
1428
1429         /* Filter settings will get applied when port is started */
1430         if (!eth_dev->data->dev_started)
1431                 return 0;
1432
1433         if (bp->vnic_info == NULL)
1434                 return 0;
1435
1436         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1437
1438         old_flags = vnic->flags;
1439         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1440         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1441         if (rc != 0)
1442                 vnic->flags = old_flags;
1443
1444         return rc;
1445 }
1446
1447 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1448 {
1449         struct bnxt *bp = eth_dev->data->dev_private;
1450         struct bnxt_vnic_info *vnic;
1451         uint32_t old_flags;
1452         int rc;
1453
1454         rc = is_bnxt_in_error(bp);
1455         if (rc)
1456                 return rc;
1457
1458         /* Filter settings will get applied when port is started */
1459         if (!eth_dev->data->dev_started)
1460                 return 0;
1461
1462         if (bp->vnic_info == NULL)
1463                 return 0;
1464
1465         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1466
1467         old_flags = vnic->flags;
1468         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1469         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1470         if (rc != 0)
1471                 vnic->flags = old_flags;
1472
1473         return rc;
1474 }
1475
1476 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1477 {
1478         struct bnxt *bp = eth_dev->data->dev_private;
1479         struct bnxt_vnic_info *vnic;
1480         uint32_t old_flags;
1481         int rc;
1482
1483         rc = is_bnxt_in_error(bp);
1484         if (rc)
1485                 return rc;
1486
1487         /* Filter settings will get applied when port is started */
1488         if (!eth_dev->data->dev_started)
1489                 return 0;
1490
1491         if (bp->vnic_info == NULL)
1492                 return 0;
1493
1494         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1495
1496         old_flags = vnic->flags;
1497         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1498         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1499         if (rc != 0)
1500                 vnic->flags = old_flags;
1501
1502         return rc;
1503 }
1504
1505 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1506 {
1507         struct bnxt *bp = eth_dev->data->dev_private;
1508         struct bnxt_vnic_info *vnic;
1509         uint32_t old_flags;
1510         int rc;
1511
1512         rc = is_bnxt_in_error(bp);
1513         if (rc)
1514                 return rc;
1515
1516         /* Filter settings will get applied when port is started */
1517         if (!eth_dev->data->dev_started)
1518                 return 0;
1519
1520         if (bp->vnic_info == NULL)
1521                 return 0;
1522
1523         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1524
1525         old_flags = vnic->flags;
1526         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1527         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1528         if (rc != 0)
1529                 vnic->flags = old_flags;
1530
1531         return rc;
1532 }
1533
1534 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1535 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1536 {
1537         if (qid >= bp->rx_nr_rings)
1538                 return NULL;
1539
1540         return bp->eth_dev->data->rx_queues[qid];
1541 }
1542
1543 /* Return rxq corresponding to a given rss table ring/group ID. */
1544 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1545 {
1546         struct bnxt_rx_queue *rxq;
1547         unsigned int i;
1548
1549         if (!BNXT_HAS_RING_GRPS(bp)) {
1550                 for (i = 0; i < bp->rx_nr_rings; i++) {
1551                         rxq = bp->eth_dev->data->rx_queues[i];
1552                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1553                                 return rxq->index;
1554                 }
1555         } else {
1556                 for (i = 0; i < bp->rx_nr_rings; i++) {
1557                         if (bp->grp_info[i].fw_grp_id == fwr)
1558                                 return i;
1559                 }
1560         }
1561
1562         return INVALID_HW_RING_ID;
1563 }
1564
1565 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1566                             struct rte_eth_rss_reta_entry64 *reta_conf,
1567                             uint16_t reta_size)
1568 {
1569         struct bnxt *bp = eth_dev->data->dev_private;
1570         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1571         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1572         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1573         uint16_t idx, sft;
1574         int i, rc;
1575
1576         rc = is_bnxt_in_error(bp);
1577         if (rc)
1578                 return rc;
1579
1580         if (!vnic->rss_table)
1581                 return -EINVAL;
1582
1583         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1584                 return -EINVAL;
1585
1586         if (reta_size != tbl_size) {
1587                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1588                         "(%d) must equal the size supported by the hardware "
1589                         "(%d)\n", reta_size, tbl_size);
1590                 return -EINVAL;
1591         }
1592
1593         for (i = 0; i < reta_size; i++) {
1594                 struct bnxt_rx_queue *rxq;
1595
1596                 idx = i / RTE_RETA_GROUP_SIZE;
1597                 sft = i % RTE_RETA_GROUP_SIZE;
1598
1599                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1600                         continue;
1601
1602                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1603                 if (!rxq) {
1604                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1605                         return -EINVAL;
1606                 }
1607
1608                 if (BNXT_CHIP_THOR(bp)) {
1609                         vnic->rss_table[i * 2] =
1610                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1611                         vnic->rss_table[i * 2 + 1] =
1612                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1613                 } else {
1614                         vnic->rss_table[i] =
1615                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1616                 }
1617         }
1618
1619         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1620         return 0;
1621 }
1622
1623 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1624                               struct rte_eth_rss_reta_entry64 *reta_conf,
1625                               uint16_t reta_size)
1626 {
1627         struct bnxt *bp = eth_dev->data->dev_private;
1628         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1629         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1630         uint16_t idx, sft, i;
1631         int rc;
1632
1633         rc = is_bnxt_in_error(bp);
1634         if (rc)
1635                 return rc;
1636
1637         /* Retrieve from the default VNIC */
1638         if (!vnic)
1639                 return -EINVAL;
1640         if (!vnic->rss_table)
1641                 return -EINVAL;
1642
1643         if (reta_size != tbl_size) {
1644                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1645                         "(%d) must equal the size supported by the hardware "
1646                         "(%d)\n", reta_size, tbl_size);
1647                 return -EINVAL;
1648         }
1649
1650         for (idx = 0, i = 0; i < reta_size; i++) {
1651                 idx = i / RTE_RETA_GROUP_SIZE;
1652                 sft = i % RTE_RETA_GROUP_SIZE;
1653
1654                 if (reta_conf[idx].mask & (1ULL << sft)) {
1655                         uint16_t qid;
1656
1657                         if (BNXT_CHIP_THOR(bp))
1658                                 qid = bnxt_rss_to_qid(bp,
1659                                                       vnic->rss_table[i * 2]);
1660                         else
1661                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1662
1663                         if (qid == INVALID_HW_RING_ID) {
1664                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1665                                 return -EINVAL;
1666                         }
1667                         reta_conf[idx].reta[sft] = qid;
1668                 }
1669         }
1670
1671         return 0;
1672 }
1673
1674 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1675                                    struct rte_eth_rss_conf *rss_conf)
1676 {
1677         struct bnxt *bp = eth_dev->data->dev_private;
1678         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1679         struct bnxt_vnic_info *vnic;
1680         int rc;
1681
1682         rc = is_bnxt_in_error(bp);
1683         if (rc)
1684                 return rc;
1685
1686         /*
1687          * If RSS enablement were different than dev_configure,
1688          * then return -EINVAL
1689          */
1690         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1691                 if (!rss_conf->rss_hf)
1692                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1693         } else {
1694                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1695                         return -EINVAL;
1696         }
1697
1698         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1699         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1700
1701         /* Update the default RSS VNIC(s) */
1702         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1703         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1704
1705         /*
1706          * If hashkey is not specified, use the previously configured
1707          * hashkey
1708          */
1709         if (!rss_conf->rss_key)
1710                 goto rss_config;
1711
1712         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1713                 PMD_DRV_LOG(ERR,
1714                             "Invalid hashkey length, should be 16 bytes\n");
1715                 return -EINVAL;
1716         }
1717         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1718
1719 rss_config:
1720         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1721         return 0;
1722 }
1723
1724 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1725                                      struct rte_eth_rss_conf *rss_conf)
1726 {
1727         struct bnxt *bp = eth_dev->data->dev_private;
1728         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1729         int len, rc;
1730         uint32_t hash_types;
1731
1732         rc = is_bnxt_in_error(bp);
1733         if (rc)
1734                 return rc;
1735
1736         /* RSS configuration is the same for all VNICs */
1737         if (vnic && vnic->rss_hash_key) {
1738                 if (rss_conf->rss_key) {
1739                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1740                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1741                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1742                 }
1743
1744                 hash_types = vnic->hash_type;
1745                 rss_conf->rss_hf = 0;
1746                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1747                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1748                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1749                 }
1750                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1751                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1752                         hash_types &=
1753                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1754                 }
1755                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1756                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1757                         hash_types &=
1758                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1759                 }
1760                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1761                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1762                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1763                 }
1764                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1765                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1766                         hash_types &=
1767                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1768                 }
1769                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1770                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1771                         hash_types &=
1772                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1773                 }
1774                 if (hash_types) {
1775                         PMD_DRV_LOG(ERR,
1776                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1777                                 vnic->hash_type);
1778                         return -ENOTSUP;
1779                 }
1780         } else {
1781                 rss_conf->rss_hf = 0;
1782         }
1783         return 0;
1784 }
1785
1786 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1787                                struct rte_eth_fc_conf *fc_conf)
1788 {
1789         struct bnxt *bp = dev->data->dev_private;
1790         struct rte_eth_link link_info;
1791         int rc;
1792
1793         rc = is_bnxt_in_error(bp);
1794         if (rc)
1795                 return rc;
1796
1797         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1798         if (rc)
1799                 return rc;
1800
1801         memset(fc_conf, 0, sizeof(*fc_conf));
1802         if (bp->link_info.auto_pause)
1803                 fc_conf->autoneg = 1;
1804         switch (bp->link_info.pause) {
1805         case 0:
1806                 fc_conf->mode = RTE_FC_NONE;
1807                 break;
1808         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1809                 fc_conf->mode = RTE_FC_TX_PAUSE;
1810                 break;
1811         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1812                 fc_conf->mode = RTE_FC_RX_PAUSE;
1813                 break;
1814         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1815                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1816                 fc_conf->mode = RTE_FC_FULL;
1817                 break;
1818         }
1819         return 0;
1820 }
1821
1822 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1823                                struct rte_eth_fc_conf *fc_conf)
1824 {
1825         struct bnxt *bp = dev->data->dev_private;
1826         int rc;
1827
1828         rc = is_bnxt_in_error(bp);
1829         if (rc)
1830                 return rc;
1831
1832         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1833                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1834                 return -ENOTSUP;
1835         }
1836
1837         switch (fc_conf->mode) {
1838         case RTE_FC_NONE:
1839                 bp->link_info.auto_pause = 0;
1840                 bp->link_info.force_pause = 0;
1841                 break;
1842         case RTE_FC_RX_PAUSE:
1843                 if (fc_conf->autoneg) {
1844                         bp->link_info.auto_pause =
1845                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1846                         bp->link_info.force_pause = 0;
1847                 } else {
1848                         bp->link_info.auto_pause = 0;
1849                         bp->link_info.force_pause =
1850                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1851                 }
1852                 break;
1853         case RTE_FC_TX_PAUSE:
1854                 if (fc_conf->autoneg) {
1855                         bp->link_info.auto_pause =
1856                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1857                         bp->link_info.force_pause = 0;
1858                 } else {
1859                         bp->link_info.auto_pause = 0;
1860                         bp->link_info.force_pause =
1861                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1862                 }
1863                 break;
1864         case RTE_FC_FULL:
1865                 if (fc_conf->autoneg) {
1866                         bp->link_info.auto_pause =
1867                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1868                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1869                         bp->link_info.force_pause = 0;
1870                 } else {
1871                         bp->link_info.auto_pause = 0;
1872                         bp->link_info.force_pause =
1873                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1874                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1875                 }
1876                 break;
1877         }
1878         return bnxt_set_hwrm_link_config(bp, true);
1879 }
1880
1881 /* Add UDP tunneling port */
1882 static int
1883 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1884                          struct rte_eth_udp_tunnel *udp_tunnel)
1885 {
1886         struct bnxt *bp = eth_dev->data->dev_private;
1887         uint16_t tunnel_type = 0;
1888         int rc = 0;
1889
1890         rc = is_bnxt_in_error(bp);
1891         if (rc)
1892                 return rc;
1893
1894         switch (udp_tunnel->prot_type) {
1895         case RTE_TUNNEL_TYPE_VXLAN:
1896                 if (bp->vxlan_port_cnt) {
1897                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1898                                 udp_tunnel->udp_port);
1899                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1900                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1901                                 return -ENOSPC;
1902                         }
1903                         bp->vxlan_port_cnt++;
1904                         return 0;
1905                 }
1906                 tunnel_type =
1907                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1908                 bp->vxlan_port_cnt++;
1909                 break;
1910         case RTE_TUNNEL_TYPE_GENEVE:
1911                 if (bp->geneve_port_cnt) {
1912                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1913                                 udp_tunnel->udp_port);
1914                         if (bp->geneve_port != udp_tunnel->udp_port) {
1915                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1916                                 return -ENOSPC;
1917                         }
1918                         bp->geneve_port_cnt++;
1919                         return 0;
1920                 }
1921                 tunnel_type =
1922                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1923                 bp->geneve_port_cnt++;
1924                 break;
1925         default:
1926                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1927                 return -ENOTSUP;
1928         }
1929         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1930                                              tunnel_type);
1931         return rc;
1932 }
1933
1934 static int
1935 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1936                          struct rte_eth_udp_tunnel *udp_tunnel)
1937 {
1938         struct bnxt *bp = eth_dev->data->dev_private;
1939         uint16_t tunnel_type = 0;
1940         uint16_t port = 0;
1941         int rc = 0;
1942
1943         rc = is_bnxt_in_error(bp);
1944         if (rc)
1945                 return rc;
1946
1947         switch (udp_tunnel->prot_type) {
1948         case RTE_TUNNEL_TYPE_VXLAN:
1949                 if (!bp->vxlan_port_cnt) {
1950                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1951                         return -EINVAL;
1952                 }
1953                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1954                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1955                                 udp_tunnel->udp_port, bp->vxlan_port);
1956                         return -EINVAL;
1957                 }
1958                 if (--bp->vxlan_port_cnt)
1959                         return 0;
1960
1961                 tunnel_type =
1962                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1963                 port = bp->vxlan_fw_dst_port_id;
1964                 break;
1965         case RTE_TUNNEL_TYPE_GENEVE:
1966                 if (!bp->geneve_port_cnt) {
1967                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1968                         return -EINVAL;
1969                 }
1970                 if (bp->geneve_port != udp_tunnel->udp_port) {
1971                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1972                                 udp_tunnel->udp_port, bp->geneve_port);
1973                         return -EINVAL;
1974                 }
1975                 if (--bp->geneve_port_cnt)
1976                         return 0;
1977
1978                 tunnel_type =
1979                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1980                 port = bp->geneve_fw_dst_port_id;
1981                 break;
1982         default:
1983                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1984                 return -ENOTSUP;
1985         }
1986
1987         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1988         if (!rc) {
1989                 if (tunnel_type ==
1990                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1991                         bp->vxlan_port = 0;
1992                 if (tunnel_type ==
1993                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1994                         bp->geneve_port = 0;
1995         }
1996         return rc;
1997 }
1998
1999 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2000 {
2001         struct bnxt_filter_info *filter;
2002         struct bnxt_vnic_info *vnic;
2003         int rc = 0;
2004         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2005
2006         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2007         filter = STAILQ_FIRST(&vnic->filter);
2008         while (filter) {
2009                 /* Search for this matching MAC+VLAN filter */
2010                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2011                         /* Delete the filter */
2012                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2013                         if (rc)
2014                                 return rc;
2015                         STAILQ_REMOVE(&vnic->filter, filter,
2016                                       bnxt_filter_info, next);
2017                         bnxt_free_filter(bp, filter);
2018                         PMD_DRV_LOG(INFO,
2019                                     "Deleted vlan filter for %d\n",
2020                                     vlan_id);
2021                         return 0;
2022                 }
2023                 filter = STAILQ_NEXT(filter, next);
2024         }
2025         return -ENOENT;
2026 }
2027
2028 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2029 {
2030         struct bnxt_filter_info *filter;
2031         struct bnxt_vnic_info *vnic;
2032         int rc = 0;
2033         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2034                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2035         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2036
2037         /* Implementation notes on the use of VNIC in this command:
2038          *
2039          * By default, these filters belong to default vnic for the function.
2040          * Once these filters are set up, only destination VNIC can be modified.
2041          * If the destination VNIC is not specified in this command,
2042          * then the HWRM shall only create an l2 context id.
2043          */
2044
2045         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2046         filter = STAILQ_FIRST(&vnic->filter);
2047         /* Check if the VLAN has already been added */
2048         while (filter) {
2049                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2050                         return -EEXIST;
2051
2052                 filter = STAILQ_NEXT(filter, next);
2053         }
2054
2055         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2056          * command to create MAC+VLAN filter with the right flags, enables set.
2057          */
2058         filter = bnxt_alloc_filter(bp);
2059         if (!filter) {
2060                 PMD_DRV_LOG(ERR,
2061                             "MAC/VLAN filter alloc failed\n");
2062                 return -ENOMEM;
2063         }
2064         /* MAC + VLAN ID filter */
2065         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2066          * untagged packets are received
2067          *
2068          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2069          * packets and only the programmed vlan's packets are received
2070          */
2071         filter->l2_ivlan = vlan_id;
2072         filter->l2_ivlan_mask = 0x0FFF;
2073         filter->enables |= en;
2074         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2075
2076         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2077         if (rc) {
2078                 /* Free the newly allocated filter as we were
2079                  * not able to create the filter in hardware.
2080                  */
2081                 bnxt_free_filter(bp, filter);
2082                 return rc;
2083         }
2084
2085         filter->mac_index = 0;
2086         /* Add this new filter to the list */
2087         if (vlan_id == 0)
2088                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2089         else
2090                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2091
2092         PMD_DRV_LOG(INFO,
2093                     "Added Vlan filter for %d\n", vlan_id);
2094         return rc;
2095 }
2096
2097 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2098                 uint16_t vlan_id, int on)
2099 {
2100         struct bnxt *bp = eth_dev->data->dev_private;
2101         int rc;
2102
2103         rc = is_bnxt_in_error(bp);
2104         if (rc)
2105                 return rc;
2106
2107         if (!eth_dev->data->dev_started) {
2108                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2109                 return -EINVAL;
2110         }
2111
2112         /* These operations apply to ALL existing MAC/VLAN filters */
2113         if (on)
2114                 return bnxt_add_vlan_filter(bp, vlan_id);
2115         else
2116                 return bnxt_del_vlan_filter(bp, vlan_id);
2117 }
2118
2119 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2120                                     struct bnxt_vnic_info *vnic)
2121 {
2122         struct bnxt_filter_info *filter;
2123         int rc;
2124
2125         filter = STAILQ_FIRST(&vnic->filter);
2126         while (filter) {
2127                 if (filter->mac_index == 0 &&
2128                     !memcmp(filter->l2_addr, bp->mac_addr,
2129                             RTE_ETHER_ADDR_LEN)) {
2130                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2131                         if (!rc) {
2132                                 STAILQ_REMOVE(&vnic->filter, filter,
2133                                               bnxt_filter_info, next);
2134                                 bnxt_free_filter(bp, filter);
2135                         }
2136                         return rc;
2137                 }
2138                 filter = STAILQ_NEXT(filter, next);
2139         }
2140         return 0;
2141 }
2142
2143 static int
2144 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2145 {
2146         struct bnxt_vnic_info *vnic;
2147         unsigned int i;
2148         int rc;
2149
2150         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2151         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2152                 /* Remove any VLAN filters programmed */
2153                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2154                         bnxt_del_vlan_filter(bp, i);
2155
2156                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2157                 if (rc)
2158                         return rc;
2159         } else {
2160                 /* Default filter will allow packets that match the
2161                  * dest mac. So, it has to be deleted, otherwise, we
2162                  * will endup receiving vlan packets for which the
2163                  * filter is not programmed, when hw-vlan-filter
2164                  * configuration is ON
2165                  */
2166                 bnxt_del_dflt_mac_filter(bp, vnic);
2167                 /* This filter will allow only untagged packets */
2168                 bnxt_add_vlan_filter(bp, 0);
2169         }
2170         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2171                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2172
2173         return 0;
2174 }
2175
2176 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2177 {
2178         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2179         unsigned int i;
2180         int rc;
2181
2182         /* Destroy vnic filters and vnic */
2183         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2184             DEV_RX_OFFLOAD_VLAN_FILTER) {
2185                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2186                         bnxt_del_vlan_filter(bp, i);
2187         }
2188         bnxt_del_dflt_mac_filter(bp, vnic);
2189
2190         rc = bnxt_hwrm_vnic_free(bp, vnic);
2191         if (rc)
2192                 return rc;
2193
2194         rte_free(vnic->fw_grp_ids);
2195         vnic->fw_grp_ids = NULL;
2196
2197         vnic->rx_queue_cnt = 0;
2198
2199         return 0;
2200 }
2201
2202 static int
2203 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2204 {
2205         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2206         int rc;
2207
2208         /* Destroy, recreate and reconfigure the default vnic */
2209         rc = bnxt_free_one_vnic(bp, 0);
2210         if (rc)
2211                 return rc;
2212
2213         /* default vnic 0 */
2214         rc = bnxt_setup_one_vnic(bp, 0);
2215         if (rc)
2216                 return rc;
2217
2218         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2219             DEV_RX_OFFLOAD_VLAN_FILTER) {
2220                 rc = bnxt_add_vlan_filter(bp, 0);
2221                 if (rc)
2222                         return rc;
2223                 rc = bnxt_restore_vlan_filters(bp);
2224                 if (rc)
2225                         return rc;
2226         } else {
2227                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2228                 if (rc)
2229                         return rc;
2230         }
2231
2232         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2233         if (rc)
2234                 return rc;
2235
2236         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2237                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2238
2239         return rc;
2240 }
2241
2242 static int
2243 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2244 {
2245         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2246         struct bnxt *bp = dev->data->dev_private;
2247         int rc;
2248
2249         rc = is_bnxt_in_error(bp);
2250         if (rc)
2251                 return rc;
2252
2253         /* Filter settings will get applied when port is started */
2254         if (!dev->data->dev_started)
2255                 return 0;
2256
2257         if (mask & ETH_VLAN_FILTER_MASK) {
2258                 /* Enable or disable VLAN filtering */
2259                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2260                 if (rc)
2261                         return rc;
2262         }
2263
2264         if (mask & ETH_VLAN_STRIP_MASK) {
2265                 /* Enable or disable VLAN stripping */
2266                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2267                 if (rc)
2268                         return rc;
2269         }
2270
2271         if (mask & ETH_VLAN_EXTEND_MASK) {
2272                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2273                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2274                 else
2275                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2276         }
2277
2278         return 0;
2279 }
2280
2281 static int
2282 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2283                       uint16_t tpid)
2284 {
2285         struct bnxt *bp = dev->data->dev_private;
2286         int qinq = dev->data->dev_conf.rxmode.offloads &
2287                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2288
2289         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2290             vlan_type != ETH_VLAN_TYPE_OUTER) {
2291                 PMD_DRV_LOG(ERR,
2292                             "Unsupported vlan type.");
2293                 return -EINVAL;
2294         }
2295         if (!qinq) {
2296                 PMD_DRV_LOG(ERR,
2297                             "QinQ not enabled. Needs to be ON as we can "
2298                             "accelerate only outer vlan\n");
2299                 return -EINVAL;
2300         }
2301
2302         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2303                 switch (tpid) {
2304                 case RTE_ETHER_TYPE_QINQ:
2305                         bp->outer_tpid_bd =
2306                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2307                                 break;
2308                 case RTE_ETHER_TYPE_VLAN:
2309                         bp->outer_tpid_bd =
2310                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2311                                 break;
2312                 case 0x9100:
2313                         bp->outer_tpid_bd =
2314                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2315                                 break;
2316                 case 0x9200:
2317                         bp->outer_tpid_bd =
2318                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2319                                 break;
2320                 case 0x9300:
2321                         bp->outer_tpid_bd =
2322                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2323                                 break;
2324                 default:
2325                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2326                         return -EINVAL;
2327                 }
2328                 bp->outer_tpid_bd |= tpid;
2329                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2330         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2331                 PMD_DRV_LOG(ERR,
2332                             "Can accelerate only outer vlan in QinQ\n");
2333                 return -EINVAL;
2334         }
2335
2336         return 0;
2337 }
2338
2339 static int
2340 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2341                              struct rte_ether_addr *addr)
2342 {
2343         struct bnxt *bp = dev->data->dev_private;
2344         /* Default Filter is tied to VNIC 0 */
2345         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2346         int rc;
2347
2348         rc = is_bnxt_in_error(bp);
2349         if (rc)
2350                 return rc;
2351
2352         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2353                 return -EPERM;
2354
2355         if (rte_is_zero_ether_addr(addr))
2356                 return -EINVAL;
2357
2358         /* Filter settings will get applied when port is started */
2359         if (!dev->data->dev_started)
2360                 return 0;
2361
2362         /* Check if the requested MAC is already added */
2363         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2364                 return 0;
2365
2366         /* Destroy filter and re-create it */
2367         bnxt_del_dflt_mac_filter(bp, vnic);
2368
2369         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2370         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2371                 /* This filter will allow only untagged packets */
2372                 rc = bnxt_add_vlan_filter(bp, 0);
2373         } else {
2374                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2375         }
2376
2377         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2378         return rc;
2379 }
2380
2381 static int
2382 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2383                           struct rte_ether_addr *mc_addr_set,
2384                           uint32_t nb_mc_addr)
2385 {
2386         struct bnxt *bp = eth_dev->data->dev_private;
2387         char *mc_addr_list = (char *)mc_addr_set;
2388         struct bnxt_vnic_info *vnic;
2389         uint32_t off = 0, i = 0;
2390         int rc;
2391
2392         rc = is_bnxt_in_error(bp);
2393         if (rc)
2394                 return rc;
2395
2396         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2397
2398         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2399                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2400                 goto allmulti;
2401         }
2402
2403         /* TODO Check for Duplicate mcast addresses */
2404         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2405         for (i = 0; i < nb_mc_addr; i++) {
2406                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2407                         RTE_ETHER_ADDR_LEN);
2408                 off += RTE_ETHER_ADDR_LEN;
2409         }
2410
2411         vnic->mc_addr_cnt = i;
2412         if (vnic->mc_addr_cnt)
2413                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2414         else
2415                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2416
2417 allmulti:
2418         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2419 }
2420
2421 static int
2422 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2423 {
2424         struct bnxt *bp = dev->data->dev_private;
2425         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2426         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2427         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2428         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2429         int ret;
2430
2431         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2432                         fw_major, fw_minor, fw_updt, fw_rsvd);
2433
2434         ret += 1; /* add the size of '\0' */
2435         if (fw_size < (uint32_t)ret)
2436                 return ret;
2437         else
2438                 return 0;
2439 }
2440
2441 static void
2442 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2443         struct rte_eth_rxq_info *qinfo)
2444 {
2445         struct bnxt *bp = dev->data->dev_private;
2446         struct bnxt_rx_queue *rxq;
2447
2448         if (is_bnxt_in_error(bp))
2449                 return;
2450
2451         rxq = dev->data->rx_queues[queue_id];
2452
2453         qinfo->mp = rxq->mb_pool;
2454         qinfo->scattered_rx = dev->data->scattered_rx;
2455         qinfo->nb_desc = rxq->nb_rx_desc;
2456
2457         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2458         qinfo->conf.rx_drop_en = 0;
2459         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2460 }
2461
2462 static void
2463 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2464         struct rte_eth_txq_info *qinfo)
2465 {
2466         struct bnxt *bp = dev->data->dev_private;
2467         struct bnxt_tx_queue *txq;
2468
2469         if (is_bnxt_in_error(bp))
2470                 return;
2471
2472         txq = dev->data->tx_queues[queue_id];
2473
2474         qinfo->nb_desc = txq->nb_tx_desc;
2475
2476         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2477         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2478         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2479
2480         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2481         qinfo->conf.tx_rs_thresh = 0;
2482         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2483 }
2484
2485 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2486 {
2487         struct bnxt *bp = eth_dev->data->dev_private;
2488         uint32_t new_pkt_size;
2489         uint32_t rc = 0;
2490         uint32_t i;
2491
2492         rc = is_bnxt_in_error(bp);
2493         if (rc)
2494                 return rc;
2495
2496         /* Exit if receive queues are not configured yet */
2497         if (!eth_dev->data->nb_rx_queues)
2498                 return rc;
2499
2500         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2501                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2502
2503 #ifdef RTE_ARCH_X86
2504         /*
2505          * If vector-mode tx/rx is active, disallow any MTU change that would
2506          * require scattered receive support.
2507          */
2508         if (eth_dev->data->dev_started &&
2509             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2510              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2511             (new_pkt_size >
2512              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2513                 PMD_DRV_LOG(ERR,
2514                             "MTU change would require scattered rx support. ");
2515                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2516                 return -EINVAL;
2517         }
2518 #endif
2519
2520         if (new_mtu > RTE_ETHER_MTU) {
2521                 bp->flags |= BNXT_FLAG_JUMBO;
2522                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2523                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2524         } else {
2525                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2526                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2527                 bp->flags &= ~BNXT_FLAG_JUMBO;
2528         }
2529
2530         /* Is there a change in mtu setting? */
2531         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2532                 return rc;
2533
2534         for (i = 0; i < bp->nr_vnics; i++) {
2535                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2536                 uint16_t size = 0;
2537
2538                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2539                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2540                 if (rc)
2541                         break;
2542
2543                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2544                 size -= RTE_PKTMBUF_HEADROOM;
2545
2546                 if (size < new_mtu) {
2547                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2548                         if (rc)
2549                                 return rc;
2550                 }
2551         }
2552
2553         if (!rc)
2554                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2555
2556         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2557
2558         return rc;
2559 }
2560
2561 static int
2562 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2563 {
2564         struct bnxt *bp = dev->data->dev_private;
2565         uint16_t vlan = bp->vlan;
2566         int rc;
2567
2568         rc = is_bnxt_in_error(bp);
2569         if (rc)
2570                 return rc;
2571
2572         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2573                 PMD_DRV_LOG(ERR,
2574                         "PVID cannot be modified for this function\n");
2575                 return -ENOTSUP;
2576         }
2577         bp->vlan = on ? pvid : 0;
2578
2579         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2580         if (rc)
2581                 bp->vlan = vlan;
2582         return rc;
2583 }
2584
2585 static int
2586 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2587 {
2588         struct bnxt *bp = dev->data->dev_private;
2589         int rc;
2590
2591         rc = is_bnxt_in_error(bp);
2592         if (rc)
2593                 return rc;
2594
2595         return bnxt_hwrm_port_led_cfg(bp, true);
2596 }
2597
2598 static int
2599 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2600 {
2601         struct bnxt *bp = dev->data->dev_private;
2602         int rc;
2603
2604         rc = is_bnxt_in_error(bp);
2605         if (rc)
2606                 return rc;
2607
2608         return bnxt_hwrm_port_led_cfg(bp, false);
2609 }
2610
2611 static uint32_t
2612 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2613 {
2614         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2615         uint32_t desc = 0, raw_cons = 0, cons;
2616         struct bnxt_cp_ring_info *cpr;
2617         struct bnxt_rx_queue *rxq;
2618         struct rx_pkt_cmpl *rxcmp;
2619         int rc;
2620
2621         rc = is_bnxt_in_error(bp);
2622         if (rc)
2623                 return rc;
2624
2625         rxq = dev->data->rx_queues[rx_queue_id];
2626         cpr = rxq->cp_ring;
2627         raw_cons = cpr->cp_raw_cons;
2628
2629         while (1) {
2630                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2631                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2632                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2633
2634                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2635                         break;
2636                 } else {
2637                         raw_cons++;
2638                         desc++;
2639                 }
2640         }
2641
2642         return desc;
2643 }
2644
2645 static int
2646 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2647 {
2648         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2649         struct bnxt_rx_ring_info *rxr;
2650         struct bnxt_cp_ring_info *cpr;
2651         struct bnxt_sw_rx_bd *rx_buf;
2652         struct rx_pkt_cmpl *rxcmp;
2653         uint32_t cons, cp_cons;
2654         int rc;
2655
2656         if (!rxq)
2657                 return -EINVAL;
2658
2659         rc = is_bnxt_in_error(rxq->bp);
2660         if (rc)
2661                 return rc;
2662
2663         cpr = rxq->cp_ring;
2664         rxr = rxq->rx_ring;
2665
2666         if (offset >= rxq->nb_rx_desc)
2667                 return -EINVAL;
2668
2669         cons = RING_CMP(cpr->cp_ring_struct, offset);
2670         cp_cons = cpr->cp_raw_cons;
2671         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2672
2673         if (cons > cp_cons) {
2674                 if (CMPL_VALID(rxcmp, cpr->valid))
2675                         return RTE_ETH_RX_DESC_DONE;
2676         } else {
2677                 if (CMPL_VALID(rxcmp, !cpr->valid))
2678                         return RTE_ETH_RX_DESC_DONE;
2679         }
2680         rx_buf = &rxr->rx_buf_ring[cons];
2681         if (rx_buf->mbuf == NULL)
2682                 return RTE_ETH_RX_DESC_UNAVAIL;
2683
2684
2685         return RTE_ETH_RX_DESC_AVAIL;
2686 }
2687
2688 static int
2689 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2690 {
2691         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2692         struct bnxt_tx_ring_info *txr;
2693         struct bnxt_cp_ring_info *cpr;
2694         struct bnxt_sw_tx_bd *tx_buf;
2695         struct tx_pkt_cmpl *txcmp;
2696         uint32_t cons, cp_cons;
2697         int rc;
2698
2699         if (!txq)
2700                 return -EINVAL;
2701
2702         rc = is_bnxt_in_error(txq->bp);
2703         if (rc)
2704                 return rc;
2705
2706         cpr = txq->cp_ring;
2707         txr = txq->tx_ring;
2708
2709         if (offset >= txq->nb_tx_desc)
2710                 return -EINVAL;
2711
2712         cons = RING_CMP(cpr->cp_ring_struct, offset);
2713         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2714         cp_cons = cpr->cp_raw_cons;
2715
2716         if (cons > cp_cons) {
2717                 if (CMPL_VALID(txcmp, cpr->valid))
2718                         return RTE_ETH_TX_DESC_UNAVAIL;
2719         } else {
2720                 if (CMPL_VALID(txcmp, !cpr->valid))
2721                         return RTE_ETH_TX_DESC_UNAVAIL;
2722         }
2723         tx_buf = &txr->tx_buf_ring[cons];
2724         if (tx_buf->mbuf == NULL)
2725                 return RTE_ETH_TX_DESC_DONE;
2726
2727         return RTE_ETH_TX_DESC_FULL;
2728 }
2729
2730 static struct bnxt_filter_info *
2731 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2732                                 struct rte_eth_ethertype_filter *efilter,
2733                                 struct bnxt_vnic_info *vnic0,
2734                                 struct bnxt_vnic_info *vnic,
2735                                 int *ret)
2736 {
2737         struct bnxt_filter_info *mfilter = NULL;
2738         int match = 0;
2739         *ret = 0;
2740
2741         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2742                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2743                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2744                         " ethertype filter.", efilter->ether_type);
2745                 *ret = -EINVAL;
2746                 goto exit;
2747         }
2748         if (efilter->queue >= bp->rx_nr_rings) {
2749                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2750                 *ret = -EINVAL;
2751                 goto exit;
2752         }
2753
2754         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2755         vnic = &bp->vnic_info[efilter->queue];
2756         if (vnic == NULL) {
2757                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2758                 *ret = -EINVAL;
2759                 goto exit;
2760         }
2761
2762         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2763                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2764                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2765                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2766                              mfilter->flags ==
2767                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2768                              mfilter->ethertype == efilter->ether_type)) {
2769                                 match = 1;
2770                                 break;
2771                         }
2772                 }
2773         } else {
2774                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2775                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2776                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2777                              mfilter->ethertype == efilter->ether_type &&
2778                              mfilter->flags ==
2779                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2780                                 match = 1;
2781                                 break;
2782                         }
2783         }
2784
2785         if (match)
2786                 *ret = -EEXIST;
2787
2788 exit:
2789         return mfilter;
2790 }
2791
2792 static int
2793 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2794                         enum rte_filter_op filter_op,
2795                         void *arg)
2796 {
2797         struct bnxt *bp = dev->data->dev_private;
2798         struct rte_eth_ethertype_filter *efilter =
2799                         (struct rte_eth_ethertype_filter *)arg;
2800         struct bnxt_filter_info *bfilter, *filter1;
2801         struct bnxt_vnic_info *vnic, *vnic0;
2802         int ret;
2803
2804         if (filter_op == RTE_ETH_FILTER_NOP)
2805                 return 0;
2806
2807         if (arg == NULL) {
2808                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2809                             filter_op);
2810                 return -EINVAL;
2811         }
2812
2813         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2814         vnic = &bp->vnic_info[efilter->queue];
2815
2816         switch (filter_op) {
2817         case RTE_ETH_FILTER_ADD:
2818                 bnxt_match_and_validate_ether_filter(bp, efilter,
2819                                                         vnic0, vnic, &ret);
2820                 if (ret < 0)
2821                         return ret;
2822
2823                 bfilter = bnxt_get_unused_filter(bp);
2824                 if (bfilter == NULL) {
2825                         PMD_DRV_LOG(ERR,
2826                                 "Not enough resources for a new filter.\n");
2827                         return -ENOMEM;
2828                 }
2829                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2830                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2831                        RTE_ETHER_ADDR_LEN);
2832                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2833                        RTE_ETHER_ADDR_LEN);
2834                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2835                 bfilter->ethertype = efilter->ether_type;
2836                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2837
2838                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2839                 if (filter1 == NULL) {
2840                         ret = -EINVAL;
2841                         goto cleanup;
2842                 }
2843                 bfilter->enables |=
2844                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2845                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2846
2847                 bfilter->dst_id = vnic->fw_vnic_id;
2848
2849                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2850                         bfilter->flags =
2851                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2852                 }
2853
2854                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2855                 if (ret)
2856                         goto cleanup;
2857                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2858                 break;
2859         case RTE_ETH_FILTER_DELETE:
2860                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2861                                                         vnic0, vnic, &ret);
2862                 if (ret == -EEXIST) {
2863                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2864
2865                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2866                                       next);
2867                         bnxt_free_filter(bp, filter1);
2868                 } else if (ret == 0) {
2869                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2870                 }
2871                 break;
2872         default:
2873                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2874                 ret = -EINVAL;
2875                 goto error;
2876         }
2877         return ret;
2878 cleanup:
2879         bnxt_free_filter(bp, bfilter);
2880 error:
2881         return ret;
2882 }
2883
2884 static inline int
2885 parse_ntuple_filter(struct bnxt *bp,
2886                     struct rte_eth_ntuple_filter *nfilter,
2887                     struct bnxt_filter_info *bfilter)
2888 {
2889         uint32_t en = 0;
2890
2891         if (nfilter->queue >= bp->rx_nr_rings) {
2892                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2893                 return -EINVAL;
2894         }
2895
2896         switch (nfilter->dst_port_mask) {
2897         case UINT16_MAX:
2898                 bfilter->dst_port_mask = -1;
2899                 bfilter->dst_port = nfilter->dst_port;
2900                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2901                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2902                 break;
2903         default:
2904                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2905                 return -EINVAL;
2906         }
2907
2908         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2909         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2910
2911         switch (nfilter->proto_mask) {
2912         case UINT8_MAX:
2913                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2914                         bfilter->ip_protocol = 17;
2915                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2916                         bfilter->ip_protocol = 6;
2917                 else
2918                         return -EINVAL;
2919                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2920                 break;
2921         default:
2922                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2923                 return -EINVAL;
2924         }
2925
2926         switch (nfilter->dst_ip_mask) {
2927         case UINT32_MAX:
2928                 bfilter->dst_ipaddr_mask[0] = -1;
2929                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2930                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2931                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2932                 break;
2933         default:
2934                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2935                 return -EINVAL;
2936         }
2937
2938         switch (nfilter->src_ip_mask) {
2939         case UINT32_MAX:
2940                 bfilter->src_ipaddr_mask[0] = -1;
2941                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2942                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2943                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2944                 break;
2945         default:
2946                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2947                 return -EINVAL;
2948         }
2949
2950         switch (nfilter->src_port_mask) {
2951         case UINT16_MAX:
2952                 bfilter->src_port_mask = -1;
2953                 bfilter->src_port = nfilter->src_port;
2954                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2955                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2956                 break;
2957         default:
2958                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2959                 return -EINVAL;
2960         }
2961
2962         bfilter->enables = en;
2963         return 0;
2964 }
2965
2966 static struct bnxt_filter_info*
2967 bnxt_match_ntuple_filter(struct bnxt *bp,
2968                          struct bnxt_filter_info *bfilter,
2969                          struct bnxt_vnic_info **mvnic)
2970 {
2971         struct bnxt_filter_info *mfilter = NULL;
2972         int i;
2973
2974         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2975                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2976                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2977                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2978                             bfilter->src_ipaddr_mask[0] ==
2979                             mfilter->src_ipaddr_mask[0] &&
2980                             bfilter->src_port == mfilter->src_port &&
2981                             bfilter->src_port_mask == mfilter->src_port_mask &&
2982                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2983                             bfilter->dst_ipaddr_mask[0] ==
2984                             mfilter->dst_ipaddr_mask[0] &&
2985                             bfilter->dst_port == mfilter->dst_port &&
2986                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2987                             bfilter->flags == mfilter->flags &&
2988                             bfilter->enables == mfilter->enables) {
2989                                 if (mvnic)
2990                                         *mvnic = vnic;
2991                                 return mfilter;
2992                         }
2993                 }
2994         }
2995         return NULL;
2996 }
2997
2998 static int
2999 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3000                        struct rte_eth_ntuple_filter *nfilter,
3001                        enum rte_filter_op filter_op)
3002 {
3003         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3004         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3005         int ret;
3006
3007         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3008                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3009                 return -EINVAL;
3010         }
3011
3012         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3013                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3014                 return -EINVAL;
3015         }
3016
3017         bfilter = bnxt_get_unused_filter(bp);
3018         if (bfilter == NULL) {
3019                 PMD_DRV_LOG(ERR,
3020                         "Not enough resources for a new filter.\n");
3021                 return -ENOMEM;
3022         }
3023         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3024         if (ret < 0)
3025                 goto free_filter;
3026
3027         vnic = &bp->vnic_info[nfilter->queue];
3028         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3029         filter1 = STAILQ_FIRST(&vnic0->filter);
3030         if (filter1 == NULL) {
3031                 ret = -EINVAL;
3032                 goto free_filter;
3033         }
3034
3035         bfilter->dst_id = vnic->fw_vnic_id;
3036         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3037         bfilter->enables |=
3038                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3039         bfilter->ethertype = 0x800;
3040         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3041
3042         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3043
3044         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3045             bfilter->dst_id == mfilter->dst_id) {
3046                 PMD_DRV_LOG(ERR, "filter exists.\n");
3047                 ret = -EEXIST;
3048                 goto free_filter;
3049         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3050                    bfilter->dst_id != mfilter->dst_id) {
3051                 mfilter->dst_id = vnic->fw_vnic_id;
3052                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3053                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3054                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3055                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3056                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3057                 goto free_filter;
3058         }
3059         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3060                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3061                 ret = -ENOENT;
3062                 goto free_filter;
3063         }
3064
3065         if (filter_op == RTE_ETH_FILTER_ADD) {
3066                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3067                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3068                 if (ret)
3069                         goto free_filter;
3070                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3071         } else {
3072                 if (mfilter == NULL) {
3073                         /* This should not happen. But for Coverity! */
3074                         ret = -ENOENT;
3075                         goto free_filter;
3076                 }
3077                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3078
3079                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3080                 bnxt_free_filter(bp, mfilter);
3081                 bnxt_free_filter(bp, bfilter);
3082         }
3083
3084         return 0;
3085 free_filter:
3086         bnxt_free_filter(bp, bfilter);
3087         return ret;
3088 }
3089
3090 static int
3091 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3092                         enum rte_filter_op filter_op,
3093                         void *arg)
3094 {
3095         struct bnxt *bp = dev->data->dev_private;
3096         int ret;
3097
3098         if (filter_op == RTE_ETH_FILTER_NOP)
3099                 return 0;
3100
3101         if (arg == NULL) {
3102                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3103                             filter_op);
3104                 return -EINVAL;
3105         }
3106
3107         switch (filter_op) {
3108         case RTE_ETH_FILTER_ADD:
3109                 ret = bnxt_cfg_ntuple_filter(bp,
3110                         (struct rte_eth_ntuple_filter *)arg,
3111                         filter_op);
3112                 break;
3113         case RTE_ETH_FILTER_DELETE:
3114                 ret = bnxt_cfg_ntuple_filter(bp,
3115                         (struct rte_eth_ntuple_filter *)arg,
3116                         filter_op);
3117                 break;
3118         default:
3119                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3120                 ret = -EINVAL;
3121                 break;
3122         }
3123         return ret;
3124 }
3125
3126 static int
3127 bnxt_parse_fdir_filter(struct bnxt *bp,
3128                        struct rte_eth_fdir_filter *fdir,
3129                        struct bnxt_filter_info *filter)
3130 {
3131         enum rte_fdir_mode fdir_mode =
3132                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3133         struct bnxt_vnic_info *vnic0, *vnic;
3134         struct bnxt_filter_info *filter1;
3135         uint32_t en = 0;
3136         int i;
3137
3138         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3139                 return -EINVAL;
3140
3141         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3142         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3143
3144         switch (fdir->input.flow_type) {
3145         case RTE_ETH_FLOW_IPV4:
3146         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3147                 /* FALLTHROUGH */
3148                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3149                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3150                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3151                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3152                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3153                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3154                 filter->ip_addr_type =
3155                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3156                 filter->src_ipaddr_mask[0] = 0xffffffff;
3157                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3158                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3159                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3160                 filter->ethertype = 0x800;
3161                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3162                 break;
3163         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3164                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3165                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3166                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3167                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3168                 filter->dst_port_mask = 0xffff;
3169                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3170                 filter->src_port_mask = 0xffff;
3171                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3172                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3173                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3174                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3175                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3176                 filter->ip_protocol = 6;
3177                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3178                 filter->ip_addr_type =
3179                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3180                 filter->src_ipaddr_mask[0] = 0xffffffff;
3181                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3182                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3183                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3184                 filter->ethertype = 0x800;
3185                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3186                 break;
3187         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3188                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3189                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3190                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3191                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3192                 filter->dst_port_mask = 0xffff;
3193                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3194                 filter->src_port_mask = 0xffff;
3195                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3196                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3197                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3198                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3199                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3200                 filter->ip_protocol = 17;
3201                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3202                 filter->ip_addr_type =
3203                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3204                 filter->src_ipaddr_mask[0] = 0xffffffff;
3205                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3206                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3207                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3208                 filter->ethertype = 0x800;
3209                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3210                 break;
3211         case RTE_ETH_FLOW_IPV6:
3212         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3213                 /* FALLTHROUGH */
3214                 filter->ip_addr_type =
3215                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3216                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3217                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3218                 rte_memcpy(filter->src_ipaddr,
3219                            fdir->input.flow.ipv6_flow.src_ip, 16);
3220                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3221                 rte_memcpy(filter->dst_ipaddr,
3222                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3223                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3224                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3225                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3226                 memset(filter->src_ipaddr_mask, 0xff, 16);
3227                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3228                 filter->ethertype = 0x86dd;
3229                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3230                 break;
3231         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3232                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3233                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3234                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3235                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3236                 filter->dst_port_mask = 0xffff;
3237                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3238                 filter->src_port_mask = 0xffff;
3239                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3240                 filter->ip_addr_type =
3241                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3242                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3243                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3244                 rte_memcpy(filter->src_ipaddr,
3245                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3246                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3247                 rte_memcpy(filter->dst_ipaddr,
3248                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3249                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3250                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3251                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3252                 memset(filter->src_ipaddr_mask, 0xff, 16);
3253                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3254                 filter->ethertype = 0x86dd;
3255                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3256                 break;
3257         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3258                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3259                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3260                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3261                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3262                 filter->dst_port_mask = 0xffff;
3263                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3264                 filter->src_port_mask = 0xffff;
3265                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3266                 filter->ip_addr_type =
3267                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3268                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3269                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3270                 rte_memcpy(filter->src_ipaddr,
3271                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3272                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3273                 rte_memcpy(filter->dst_ipaddr,
3274                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3275                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3276                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3277                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3278                 memset(filter->src_ipaddr_mask, 0xff, 16);
3279                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3280                 filter->ethertype = 0x86dd;
3281                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3282                 break;
3283         case RTE_ETH_FLOW_L2_PAYLOAD:
3284                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3285                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3286                 break;
3287         case RTE_ETH_FLOW_VXLAN:
3288                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3289                         return -EINVAL;
3290                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3291                 filter->tunnel_type =
3292                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3293                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3294                 break;
3295         case RTE_ETH_FLOW_NVGRE:
3296                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3297                         return -EINVAL;
3298                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3299                 filter->tunnel_type =
3300                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3301                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3302                 break;
3303         case RTE_ETH_FLOW_UNKNOWN:
3304         case RTE_ETH_FLOW_RAW:
3305         case RTE_ETH_FLOW_FRAG_IPV4:
3306         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3307         case RTE_ETH_FLOW_FRAG_IPV6:
3308         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3309         case RTE_ETH_FLOW_IPV6_EX:
3310         case RTE_ETH_FLOW_IPV6_TCP_EX:
3311         case RTE_ETH_FLOW_IPV6_UDP_EX:
3312         case RTE_ETH_FLOW_GENEVE:
3313                 /* FALLTHROUGH */
3314         default:
3315                 return -EINVAL;
3316         }
3317
3318         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3319         vnic = &bp->vnic_info[fdir->action.rx_queue];
3320         if (vnic == NULL) {
3321                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3322                 return -EINVAL;
3323         }
3324
3325         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3326                 rte_memcpy(filter->dst_macaddr,
3327                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3328                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3329         }
3330
3331         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3332                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3333                 filter1 = STAILQ_FIRST(&vnic0->filter);
3334                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3335         } else {
3336                 filter->dst_id = vnic->fw_vnic_id;
3337                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3338                         if (filter->dst_macaddr[i] == 0x00)
3339                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3340                         else
3341                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3342         }
3343
3344         if (filter1 == NULL)
3345                 return -EINVAL;
3346
3347         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3348         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3349
3350         filter->enables = en;
3351
3352         return 0;
3353 }
3354
3355 static struct bnxt_filter_info *
3356 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3357                 struct bnxt_vnic_info **mvnic)
3358 {
3359         struct bnxt_filter_info *mf = NULL;
3360         int i;
3361
3362         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3363                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3364
3365                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3366                         if (mf->filter_type == nf->filter_type &&
3367                             mf->flags == nf->flags &&
3368                             mf->src_port == nf->src_port &&
3369                             mf->src_port_mask == nf->src_port_mask &&
3370                             mf->dst_port == nf->dst_port &&
3371                             mf->dst_port_mask == nf->dst_port_mask &&
3372                             mf->ip_protocol == nf->ip_protocol &&
3373                             mf->ip_addr_type == nf->ip_addr_type &&
3374                             mf->ethertype == nf->ethertype &&
3375                             mf->vni == nf->vni &&
3376                             mf->tunnel_type == nf->tunnel_type &&
3377                             mf->l2_ovlan == nf->l2_ovlan &&
3378                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3379                             mf->l2_ivlan == nf->l2_ivlan &&
3380                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3381                             !memcmp(mf->l2_addr, nf->l2_addr,
3382                                     RTE_ETHER_ADDR_LEN) &&
3383                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3384                                     RTE_ETHER_ADDR_LEN) &&
3385                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3386                                     RTE_ETHER_ADDR_LEN) &&
3387                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3388                                     RTE_ETHER_ADDR_LEN) &&
3389                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3390                                     sizeof(nf->src_ipaddr)) &&
3391                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3392                                     sizeof(nf->src_ipaddr_mask)) &&
3393                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3394                                     sizeof(nf->dst_ipaddr)) &&
3395                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3396                                     sizeof(nf->dst_ipaddr_mask))) {
3397                                 if (mvnic)
3398                                         *mvnic = vnic;
3399                                 return mf;
3400                         }
3401                 }
3402         }
3403         return NULL;
3404 }
3405
3406 static int
3407 bnxt_fdir_filter(struct rte_eth_dev *dev,
3408                  enum rte_filter_op filter_op,
3409                  void *arg)
3410 {
3411         struct bnxt *bp = dev->data->dev_private;
3412         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3413         struct bnxt_filter_info *filter, *match;
3414         struct bnxt_vnic_info *vnic, *mvnic;
3415         int ret = 0, i;
3416
3417         if (filter_op == RTE_ETH_FILTER_NOP)
3418                 return 0;
3419
3420         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3421                 return -EINVAL;
3422
3423         switch (filter_op) {
3424         case RTE_ETH_FILTER_ADD:
3425         case RTE_ETH_FILTER_DELETE:
3426                 /* FALLTHROUGH */
3427                 filter = bnxt_get_unused_filter(bp);
3428                 if (filter == NULL) {
3429                         PMD_DRV_LOG(ERR,
3430                                 "Not enough resources for a new flow.\n");
3431                         return -ENOMEM;
3432                 }
3433
3434                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3435                 if (ret != 0)
3436                         goto free_filter;
3437                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3438
3439                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3440                         vnic = &bp->vnic_info[0];
3441                 else
3442                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3443
3444                 match = bnxt_match_fdir(bp, filter, &mvnic);
3445                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3446                         if (match->dst_id == vnic->fw_vnic_id) {
3447                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3448                                 ret = -EEXIST;
3449                                 goto free_filter;
3450                         } else {
3451                                 match->dst_id = vnic->fw_vnic_id;
3452                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3453                                                                   match->dst_id,
3454                                                                   match);
3455                                 STAILQ_REMOVE(&mvnic->filter, match,
3456                                               bnxt_filter_info, next);
3457                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3458                                 PMD_DRV_LOG(ERR,
3459                                         "Filter with matching pattern exist\n");
3460                                 PMD_DRV_LOG(ERR,
3461                                         "Updated it to new destination q\n");
3462                                 goto free_filter;
3463                         }
3464                 }
3465                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3466                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3467                         ret = -ENOENT;
3468                         goto free_filter;
3469                 }
3470
3471                 if (filter_op == RTE_ETH_FILTER_ADD) {
3472                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3473                                                           filter->dst_id,
3474                                                           filter);
3475                         if (ret)
3476                                 goto free_filter;
3477                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3478                 } else {
3479                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3480                         STAILQ_REMOVE(&vnic->filter, match,
3481                                       bnxt_filter_info, next);
3482                         bnxt_free_filter(bp, match);
3483                         bnxt_free_filter(bp, filter);
3484                 }
3485                 break;
3486         case RTE_ETH_FILTER_FLUSH:
3487                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3488                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3489
3490                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3491                                 if (filter->filter_type ==
3492                                     HWRM_CFA_NTUPLE_FILTER) {
3493                                         ret =
3494                                         bnxt_hwrm_clear_ntuple_filter(bp,
3495                                                                       filter);
3496                                         STAILQ_REMOVE(&vnic->filter, filter,
3497                                                       bnxt_filter_info, next);
3498                                 }
3499                         }
3500                 }
3501                 return ret;
3502         case RTE_ETH_FILTER_UPDATE:
3503         case RTE_ETH_FILTER_STATS:
3504         case RTE_ETH_FILTER_INFO:
3505                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3506                 break;
3507         default:
3508                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3509                 ret = -EINVAL;
3510                 break;
3511         }
3512         return ret;
3513
3514 free_filter:
3515         bnxt_free_filter(bp, filter);
3516         return ret;
3517 }
3518
3519 static int
3520 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3521                     enum rte_filter_type filter_type,
3522                     enum rte_filter_op filter_op, void *arg)
3523 {
3524         struct bnxt *bp = dev->data->dev_private;
3525         int ret = 0;
3526
3527         ret = is_bnxt_in_error(dev->data->dev_private);
3528         if (ret)
3529                 return ret;
3530
3531         switch (filter_type) {
3532         case RTE_ETH_FILTER_TUNNEL:
3533                 PMD_DRV_LOG(ERR,
3534                         "filter type: %d: To be implemented\n", filter_type);
3535                 break;
3536         case RTE_ETH_FILTER_FDIR:
3537                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3538                 break;
3539         case RTE_ETH_FILTER_NTUPLE:
3540                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3541                 break;
3542         case RTE_ETH_FILTER_ETHERTYPE:
3543                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3544                 break;
3545         case RTE_ETH_FILTER_GENERIC:
3546                 if (filter_op != RTE_ETH_FILTER_GET)
3547                         return -EINVAL;
3548                 if (bp->truflow)
3549                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3550                 else
3551                         *(const void **)arg = &bnxt_flow_ops;
3552                 break;
3553         default:
3554                 PMD_DRV_LOG(ERR,
3555                         "Filter type (%d) not supported", filter_type);
3556                 ret = -EINVAL;
3557                 break;
3558         }
3559         return ret;
3560 }
3561
3562 static const uint32_t *
3563 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3564 {
3565         static const uint32_t ptypes[] = {
3566                 RTE_PTYPE_L2_ETHER_VLAN,
3567                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3568                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3569                 RTE_PTYPE_L4_ICMP,
3570                 RTE_PTYPE_L4_TCP,
3571                 RTE_PTYPE_L4_UDP,
3572                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3573                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3574                 RTE_PTYPE_INNER_L4_ICMP,
3575                 RTE_PTYPE_INNER_L4_TCP,
3576                 RTE_PTYPE_INNER_L4_UDP,
3577                 RTE_PTYPE_UNKNOWN
3578         };
3579
3580         if (!dev->rx_pkt_burst)
3581                 return NULL;
3582
3583         return ptypes;
3584 }
3585
3586 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3587                          int reg_win)
3588 {
3589         uint32_t reg_base = *reg_arr & 0xfffff000;
3590         uint32_t win_off;
3591         int i;
3592
3593         for (i = 0; i < count; i++) {
3594                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3595                         return -ERANGE;
3596         }
3597         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3598         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3599         return 0;
3600 }
3601
3602 static int bnxt_map_ptp_regs(struct bnxt *bp)
3603 {
3604         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3605         uint32_t *reg_arr;
3606         int rc, i;
3607
3608         reg_arr = ptp->rx_regs;
3609         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3610         if (rc)
3611                 return rc;
3612
3613         reg_arr = ptp->tx_regs;
3614         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3615         if (rc)
3616                 return rc;
3617
3618         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3619                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3620
3621         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3622                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3623
3624         return 0;
3625 }
3626
3627 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3628 {
3629         rte_write32(0, (uint8_t *)bp->bar0 +
3630                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3631         rte_write32(0, (uint8_t *)bp->bar0 +
3632                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3633 }
3634
3635 static uint64_t bnxt_cc_read(struct bnxt *bp)
3636 {
3637         uint64_t ns;
3638
3639         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3640                               BNXT_GRCPF_REG_SYNC_TIME));
3641         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3642                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3643         return ns;
3644 }
3645
3646 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3647 {
3648         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3649         uint32_t fifo;
3650
3651         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3652                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3653         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3654                 return -EAGAIN;
3655
3656         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3657                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3658         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3659                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3660         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3661                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3662
3663         return 0;
3664 }
3665
3666 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3667 {
3668         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3669         struct bnxt_pf_info *pf = &bp->pf;
3670         uint16_t port_id;
3671         uint32_t fifo;
3672
3673         if (!ptp)
3674                 return -ENODEV;
3675
3676         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3677                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3678         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3679                 return -EAGAIN;
3680
3681         port_id = pf->port_id;
3682         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3683                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3684
3685         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3686                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3687         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3688 /*              bnxt_clr_rx_ts(bp);       TBD  */
3689                 return -EBUSY;
3690         }
3691
3692         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3693                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3694         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3695                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3696
3697         return 0;
3698 }
3699
3700 static int
3701 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3702 {
3703         uint64_t ns;
3704         struct bnxt *bp = dev->data->dev_private;
3705         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3706
3707         if (!ptp)
3708                 return 0;
3709
3710         ns = rte_timespec_to_ns(ts);
3711         /* Set the timecounters to a new value. */
3712         ptp->tc.nsec = ns;
3713
3714         return 0;
3715 }
3716
3717 static int
3718 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3719 {
3720         struct bnxt *bp = dev->data->dev_private;
3721         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3722         uint64_t ns, systime_cycles = 0;
3723         int rc = 0;
3724
3725         if (!ptp)
3726                 return 0;
3727
3728         if (BNXT_CHIP_THOR(bp))
3729                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3730                                              &systime_cycles);
3731         else
3732                 systime_cycles = bnxt_cc_read(bp);
3733
3734         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3735         *ts = rte_ns_to_timespec(ns);
3736
3737         return rc;
3738 }
3739 static int
3740 bnxt_timesync_enable(struct rte_eth_dev *dev)
3741 {
3742         struct bnxt *bp = dev->data->dev_private;
3743         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3744         uint32_t shift = 0;
3745         int rc;
3746
3747         if (!ptp)
3748                 return 0;
3749
3750         ptp->rx_filter = 1;
3751         ptp->tx_tstamp_en = 1;
3752         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3753
3754         rc = bnxt_hwrm_ptp_cfg(bp);
3755         if (rc)
3756                 return rc;
3757
3758         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3759         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3760         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3761
3762         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3763         ptp->tc.cc_shift = shift;
3764         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3765
3766         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3767         ptp->rx_tstamp_tc.cc_shift = shift;
3768         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3769
3770         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3771         ptp->tx_tstamp_tc.cc_shift = shift;
3772         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3773
3774         if (!BNXT_CHIP_THOR(bp))
3775                 bnxt_map_ptp_regs(bp);
3776
3777         return 0;
3778 }
3779
3780 static int
3781 bnxt_timesync_disable(struct rte_eth_dev *dev)
3782 {
3783         struct bnxt *bp = dev->data->dev_private;
3784         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3785
3786         if (!ptp)
3787                 return 0;
3788
3789         ptp->rx_filter = 0;
3790         ptp->tx_tstamp_en = 0;
3791         ptp->rxctl = 0;
3792
3793         bnxt_hwrm_ptp_cfg(bp);
3794
3795         if (!BNXT_CHIP_THOR(bp))
3796                 bnxt_unmap_ptp_regs(bp);
3797
3798         return 0;
3799 }
3800
3801 static int
3802 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3803                                  struct timespec *timestamp,
3804                                  uint32_t flags __rte_unused)
3805 {
3806         struct bnxt *bp = dev->data->dev_private;
3807         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3808         uint64_t rx_tstamp_cycles = 0;
3809         uint64_t ns;
3810
3811         if (!ptp)
3812                 return 0;
3813
3814         if (BNXT_CHIP_THOR(bp))
3815                 rx_tstamp_cycles = ptp->rx_timestamp;
3816         else
3817                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3818
3819         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3820         *timestamp = rte_ns_to_timespec(ns);
3821         return  0;
3822 }
3823
3824 static int
3825 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3826                                  struct timespec *timestamp)
3827 {
3828         struct bnxt *bp = dev->data->dev_private;
3829         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3830         uint64_t tx_tstamp_cycles = 0;
3831         uint64_t ns;
3832         int rc = 0;
3833
3834         if (!ptp)
3835                 return 0;
3836
3837         if (BNXT_CHIP_THOR(bp))
3838                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3839                                              &tx_tstamp_cycles);
3840         else
3841                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3842
3843         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3844         *timestamp = rte_ns_to_timespec(ns);
3845
3846         return rc;
3847 }
3848
3849 static int
3850 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3851 {
3852         struct bnxt *bp = dev->data->dev_private;
3853         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3854
3855         if (!ptp)
3856                 return 0;
3857
3858         ptp->tc.nsec += delta;
3859
3860         return 0;
3861 }
3862
3863 static int
3864 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3865 {
3866         struct bnxt *bp = dev->data->dev_private;
3867         int rc;
3868         uint32_t dir_entries;
3869         uint32_t entry_length;
3870
3871         rc = is_bnxt_in_error(bp);
3872         if (rc)
3873                 return rc;
3874
3875         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3876                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3877                     bp->pdev->addr.devid, bp->pdev->addr.function);
3878
3879         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3880         if (rc != 0)
3881                 return rc;
3882
3883         return dir_entries * entry_length;
3884 }
3885
3886 static int
3887 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3888                 struct rte_dev_eeprom_info *in_eeprom)
3889 {
3890         struct bnxt *bp = dev->data->dev_private;
3891         uint32_t index;
3892         uint32_t offset;
3893         int rc;
3894
3895         rc = is_bnxt_in_error(bp);
3896         if (rc)
3897                 return rc;
3898
3899         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3900                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3901                     bp->pdev->addr.devid, bp->pdev->addr.function,
3902                     in_eeprom->offset, in_eeprom->length);
3903
3904         if (in_eeprom->offset == 0) /* special offset value to get directory */
3905                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3906                                                 in_eeprom->data);
3907
3908         index = in_eeprom->offset >> 24;
3909         offset = in_eeprom->offset & 0xffffff;
3910
3911         if (index != 0)
3912                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3913                                            in_eeprom->length, in_eeprom->data);
3914
3915         return 0;
3916 }
3917
3918 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3919 {
3920         switch (dir_type) {
3921         case BNX_DIR_TYPE_CHIMP_PATCH:
3922         case BNX_DIR_TYPE_BOOTCODE:
3923         case BNX_DIR_TYPE_BOOTCODE_2:
3924         case BNX_DIR_TYPE_APE_FW:
3925         case BNX_DIR_TYPE_APE_PATCH:
3926         case BNX_DIR_TYPE_KONG_FW:
3927         case BNX_DIR_TYPE_KONG_PATCH:
3928         case BNX_DIR_TYPE_BONO_FW:
3929         case BNX_DIR_TYPE_BONO_PATCH:
3930                 /* FALLTHROUGH */
3931                 return true;
3932         }
3933
3934         return false;
3935 }
3936
3937 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3938 {
3939         switch (dir_type) {
3940         case BNX_DIR_TYPE_AVS:
3941         case BNX_DIR_TYPE_EXP_ROM_MBA:
3942         case BNX_DIR_TYPE_PCIE:
3943         case BNX_DIR_TYPE_TSCF_UCODE:
3944         case BNX_DIR_TYPE_EXT_PHY:
3945         case BNX_DIR_TYPE_CCM:
3946         case BNX_DIR_TYPE_ISCSI_BOOT:
3947         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3948         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3949                 /* FALLTHROUGH */
3950                 return true;
3951         }
3952
3953         return false;
3954 }
3955
3956 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3957 {
3958         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3959                 bnxt_dir_type_is_other_exec_format(dir_type);
3960 }
3961
3962 static int
3963 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3964                 struct rte_dev_eeprom_info *in_eeprom)
3965 {
3966         struct bnxt *bp = dev->data->dev_private;
3967         uint8_t index, dir_op;
3968         uint16_t type, ext, ordinal, attr;
3969         int rc;
3970
3971         rc = is_bnxt_in_error(bp);
3972         if (rc)
3973                 return rc;
3974
3975         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3976                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3977                     bp->pdev->addr.devid, bp->pdev->addr.function,
3978                     in_eeprom->offset, in_eeprom->length);
3979
3980         if (!BNXT_PF(bp)) {
3981                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3982                 return -EINVAL;
3983         }
3984
3985         type = in_eeprom->magic >> 16;
3986
3987         if (type == 0xffff) { /* special value for directory operations */
3988                 index = in_eeprom->magic & 0xff;
3989                 dir_op = in_eeprom->magic >> 8;
3990                 if (index == 0)
3991                         return -EINVAL;
3992                 switch (dir_op) {
3993                 case 0x0e: /* erase */
3994                         if (in_eeprom->offset != ~in_eeprom->magic)
3995                                 return -EINVAL;
3996                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3997                 default:
3998                         return -EINVAL;
3999                 }
4000         }
4001
4002         /* Create or re-write an NVM item: */
4003         if (bnxt_dir_type_is_executable(type) == true)
4004                 return -EOPNOTSUPP;
4005         ext = in_eeprom->magic & 0xffff;
4006         ordinal = in_eeprom->offset >> 16;
4007         attr = in_eeprom->offset & 0xffff;
4008
4009         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4010                                      in_eeprom->data, in_eeprom->length);
4011 }
4012
4013 /*
4014  * Initialization
4015  */
4016
4017 static const struct eth_dev_ops bnxt_dev_ops = {
4018         .dev_infos_get = bnxt_dev_info_get_op,
4019         .dev_close = bnxt_dev_close_op,
4020         .dev_configure = bnxt_dev_configure_op,
4021         .dev_start = bnxt_dev_start_op,
4022         .dev_stop = bnxt_dev_stop_op,
4023         .dev_set_link_up = bnxt_dev_set_link_up_op,
4024         .dev_set_link_down = bnxt_dev_set_link_down_op,
4025         .stats_get = bnxt_stats_get_op,
4026         .stats_reset = bnxt_stats_reset_op,
4027         .rx_queue_setup = bnxt_rx_queue_setup_op,
4028         .rx_queue_release = bnxt_rx_queue_release_op,
4029         .tx_queue_setup = bnxt_tx_queue_setup_op,
4030         .tx_queue_release = bnxt_tx_queue_release_op,
4031         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4032         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4033         .reta_update = bnxt_reta_update_op,
4034         .reta_query = bnxt_reta_query_op,
4035         .rss_hash_update = bnxt_rss_hash_update_op,
4036         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4037         .link_update = bnxt_link_update_op,
4038         .promiscuous_enable = bnxt_promiscuous_enable_op,
4039         .promiscuous_disable = bnxt_promiscuous_disable_op,
4040         .allmulticast_enable = bnxt_allmulticast_enable_op,
4041         .allmulticast_disable = bnxt_allmulticast_disable_op,
4042         .mac_addr_add = bnxt_mac_addr_add_op,
4043         .mac_addr_remove = bnxt_mac_addr_remove_op,
4044         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4045         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4046         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4047         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4048         .vlan_filter_set = bnxt_vlan_filter_set_op,
4049         .vlan_offload_set = bnxt_vlan_offload_set_op,
4050         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4051         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4052         .mtu_set = bnxt_mtu_set_op,
4053         .mac_addr_set = bnxt_set_default_mac_addr_op,
4054         .xstats_get = bnxt_dev_xstats_get_op,
4055         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4056         .xstats_reset = bnxt_dev_xstats_reset_op,
4057         .fw_version_get = bnxt_fw_version_get,
4058         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4059         .rxq_info_get = bnxt_rxq_info_get_op,
4060         .txq_info_get = bnxt_txq_info_get_op,
4061         .dev_led_on = bnxt_dev_led_on_op,
4062         .dev_led_off = bnxt_dev_led_off_op,
4063         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4064         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4065         .rx_queue_count = bnxt_rx_queue_count_op,
4066         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4067         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4068         .rx_queue_start = bnxt_rx_queue_start,
4069         .rx_queue_stop = bnxt_rx_queue_stop,
4070         .tx_queue_start = bnxt_tx_queue_start,
4071         .tx_queue_stop = bnxt_tx_queue_stop,
4072         .filter_ctrl = bnxt_filter_ctrl_op,
4073         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4074         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4075         .get_eeprom           = bnxt_get_eeprom_op,
4076         .set_eeprom           = bnxt_set_eeprom_op,
4077         .timesync_enable      = bnxt_timesync_enable,
4078         .timesync_disable     = bnxt_timesync_disable,
4079         .timesync_read_time   = bnxt_timesync_read_time,
4080         .timesync_write_time   = bnxt_timesync_write_time,
4081         .timesync_adjust_time = bnxt_timesync_adjust_time,
4082         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4083         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4084 };
4085
4086 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4087 {
4088         uint32_t offset;
4089
4090         /* Only pre-map the reset GRC registers using window 3 */
4091         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4092                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4093
4094         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4095
4096         return offset;
4097 }
4098
4099 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4100 {
4101         struct bnxt_error_recovery_info *info = bp->recovery_info;
4102         uint32_t reg_base = 0xffffffff;
4103         int i;
4104
4105         /* Only pre-map the monitoring GRC registers using window 2 */
4106         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4107                 uint32_t reg = info->status_regs[i];
4108
4109                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4110                         continue;
4111
4112                 if (reg_base == 0xffffffff)
4113                         reg_base = reg & 0xfffff000;
4114                 if ((reg & 0xfffff000) != reg_base)
4115                         return -ERANGE;
4116
4117                 /* Use mask 0xffc as the Lower 2 bits indicates
4118                  * address space location
4119                  */
4120                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4121                                                 (reg & 0xffc);
4122         }
4123
4124         if (reg_base == 0xffffffff)
4125                 return 0;
4126
4127         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4128                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4129
4130         return 0;
4131 }
4132
4133 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4134 {
4135         struct bnxt_error_recovery_info *info = bp->recovery_info;
4136         uint32_t delay = info->delay_after_reset[index];
4137         uint32_t val = info->reset_reg_val[index];
4138         uint32_t reg = info->reset_reg[index];
4139         uint32_t type, offset;
4140
4141         type = BNXT_FW_STATUS_REG_TYPE(reg);
4142         offset = BNXT_FW_STATUS_REG_OFF(reg);
4143
4144         switch (type) {
4145         case BNXT_FW_STATUS_REG_TYPE_CFG:
4146                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4147                 break;
4148         case BNXT_FW_STATUS_REG_TYPE_GRC:
4149                 offset = bnxt_map_reset_regs(bp, offset);
4150                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4151                 break;
4152         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4153                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4154                 break;
4155         }
4156         /* wait on a specific interval of time until core reset is complete */
4157         if (delay)
4158                 rte_delay_ms(delay);
4159 }
4160
4161 static void bnxt_dev_cleanup(struct bnxt *bp)
4162 {
4163         bnxt_set_hwrm_link_config(bp, false);
4164         bp->link_info.link_up = 0;
4165         if (bp->eth_dev->data->dev_started)
4166                 bnxt_dev_stop_op(bp->eth_dev);
4167
4168         bnxt_uninit_resources(bp, true);
4169 }
4170
4171 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4172 {
4173         struct rte_eth_dev *dev = bp->eth_dev;
4174         struct rte_vlan_filter_conf *vfc;
4175         int vidx, vbit, rc;
4176         uint16_t vlan_id;
4177
4178         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4179                 vfc = &dev->data->vlan_filter_conf;
4180                 vidx = vlan_id / 64;
4181                 vbit = vlan_id % 64;
4182
4183                 /* Each bit corresponds to a VLAN id */
4184                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4185                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4186                         if (rc)
4187                                 return rc;
4188                 }
4189         }
4190
4191         return 0;
4192 }
4193
4194 static int bnxt_restore_mac_filters(struct bnxt *bp)
4195 {
4196         struct rte_eth_dev *dev = bp->eth_dev;
4197         struct rte_eth_dev_info dev_info;
4198         struct rte_ether_addr *addr;
4199         uint64_t pool_mask;
4200         uint32_t pool = 0;
4201         uint16_t i;
4202         int rc;
4203
4204         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4205                 return 0;
4206
4207         rc = bnxt_dev_info_get_op(dev, &dev_info);
4208         if (rc)
4209                 return rc;
4210
4211         /* replay MAC address configuration */
4212         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4213                 addr = &dev->data->mac_addrs[i];
4214
4215                 /* skip zero address */
4216                 if (rte_is_zero_ether_addr(addr))
4217                         continue;
4218
4219                 pool = 0;
4220                 pool_mask = dev->data->mac_pool_sel[i];
4221
4222                 do {
4223                         if (pool_mask & 1ULL) {
4224                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4225                                 if (rc)
4226                                         return rc;
4227                         }
4228                         pool_mask >>= 1;
4229                         pool++;
4230                 } while (pool_mask);
4231         }
4232
4233         return 0;
4234 }
4235
4236 static int bnxt_restore_filters(struct bnxt *bp)
4237 {
4238         struct rte_eth_dev *dev = bp->eth_dev;
4239         int ret = 0;
4240
4241         if (dev->data->all_multicast) {
4242                 ret = bnxt_allmulticast_enable_op(dev);
4243                 if (ret)
4244                         return ret;
4245         }
4246         if (dev->data->promiscuous) {
4247                 ret = bnxt_promiscuous_enable_op(dev);
4248                 if (ret)
4249                         return ret;
4250         }
4251
4252         ret = bnxt_restore_mac_filters(bp);
4253         if (ret)
4254                 return ret;
4255
4256         ret = bnxt_restore_vlan_filters(bp);
4257         /* TODO restore other filters as well */
4258         return ret;
4259 }
4260
4261 static void bnxt_dev_recover(void *arg)
4262 {
4263         struct bnxt *bp = arg;
4264         int timeout = bp->fw_reset_max_msecs;
4265         int rc = 0;
4266
4267         /* Clear Error flag so that device re-init should happen */
4268         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4269
4270         do {
4271                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4272                 if (rc == 0)
4273                         break;
4274                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4275                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4276         } while (rc && timeout);
4277
4278         if (rc) {
4279                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4280                 goto err;
4281         }
4282
4283         rc = bnxt_init_resources(bp, true);
4284         if (rc) {
4285                 PMD_DRV_LOG(ERR,
4286                             "Failed to initialize resources after reset\n");
4287                 goto err;
4288         }
4289         /* clear reset flag as the device is initialized now */
4290         bp->flags &= ~BNXT_FLAG_FW_RESET;
4291
4292         rc = bnxt_dev_start_op(bp->eth_dev);
4293         if (rc) {
4294                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4295                 goto err_start;
4296         }
4297
4298         rc = bnxt_restore_filters(bp);
4299         if (rc)
4300                 goto err_start;
4301
4302         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4303         return;
4304 err_start:
4305         bnxt_dev_stop_op(bp->eth_dev);
4306 err:
4307         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4308         bnxt_uninit_resources(bp, false);
4309         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4310 }
4311
4312 void bnxt_dev_reset_and_resume(void *arg)
4313 {
4314         struct bnxt *bp = arg;
4315         int rc;
4316
4317         bnxt_dev_cleanup(bp);
4318
4319         bnxt_wait_for_device_shutdown(bp);
4320
4321         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4322                                bnxt_dev_recover, (void *)bp);
4323         if (rc)
4324                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4325 }
4326
4327 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4328 {
4329         struct bnxt_error_recovery_info *info = bp->recovery_info;
4330         uint32_t reg = info->status_regs[index];
4331         uint32_t type, offset, val = 0;
4332
4333         type = BNXT_FW_STATUS_REG_TYPE(reg);
4334         offset = BNXT_FW_STATUS_REG_OFF(reg);
4335
4336         switch (type) {
4337         case BNXT_FW_STATUS_REG_TYPE_CFG:
4338                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4339                 break;
4340         case BNXT_FW_STATUS_REG_TYPE_GRC:
4341                 offset = info->mapped_status_regs[index];
4342                 /* FALLTHROUGH */
4343         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4344                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4345                                        offset));
4346                 break;
4347         }
4348
4349         return val;
4350 }
4351
4352 static int bnxt_fw_reset_all(struct bnxt *bp)
4353 {
4354         struct bnxt_error_recovery_info *info = bp->recovery_info;
4355         uint32_t i;
4356         int rc = 0;
4357
4358         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4359                 /* Reset through master function driver */
4360                 for (i = 0; i < info->reg_array_cnt; i++)
4361                         bnxt_write_fw_reset_reg(bp, i);
4362                 /* Wait for time specified by FW after triggering reset */
4363                 rte_delay_ms(info->master_func_wait_period_after_reset);
4364         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4365                 /* Reset with the help of Kong processor */
4366                 rc = bnxt_hwrm_fw_reset(bp);
4367                 if (rc)
4368                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4369         }
4370
4371         return rc;
4372 }
4373
4374 static void bnxt_fw_reset_cb(void *arg)
4375 {
4376         struct bnxt *bp = arg;
4377         struct bnxt_error_recovery_info *info = bp->recovery_info;
4378         int rc = 0;
4379
4380         /* Only Master function can do FW reset */
4381         if (bnxt_is_master_func(bp) &&
4382             bnxt_is_recovery_enabled(bp)) {
4383                 rc = bnxt_fw_reset_all(bp);
4384                 if (rc) {
4385                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4386                         return;
4387                 }
4388         }
4389
4390         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4391          * EXCEPTION_FATAL_ASYNC event to all the functions
4392          * (including MASTER FUNC). After receiving this Async, all the active
4393          * drivers should treat this case as FW initiated recovery
4394          */
4395         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4396                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4397                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4398
4399                 /* To recover from error */
4400                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4401                                   (void *)bp);
4402         }
4403 }
4404
4405 /* Driver should poll FW heartbeat, reset_counter with the frequency
4406  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4407  * When the driver detects heartbeat stop or change in reset_counter,
4408  * it has to trigger a reset to recover from the error condition.
4409  * A “master PF” is the function who will have the privilege to
4410  * initiate the chimp reset. The master PF will be elected by the
4411  * firmware and will be notified through async message.
4412  */
4413 static void bnxt_check_fw_health(void *arg)
4414 {
4415         struct bnxt *bp = arg;
4416         struct bnxt_error_recovery_info *info = bp->recovery_info;
4417         uint32_t val = 0, wait_msec;
4418
4419         if (!info || !bnxt_is_recovery_enabled(bp) ||
4420             is_bnxt_in_error(bp))
4421                 return;
4422
4423         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4424         if (val == info->last_heart_beat)
4425                 goto reset;
4426
4427         info->last_heart_beat = val;
4428
4429         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4430         if (val != info->last_reset_counter)
4431                 goto reset;
4432
4433         info->last_reset_counter = val;
4434
4435         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4436                           bnxt_check_fw_health, (void *)bp);
4437
4438         return;
4439 reset:
4440         /* Stop DMA to/from device */
4441         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4442         bp->flags |= BNXT_FLAG_FW_RESET;
4443
4444         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4445
4446         if (bnxt_is_master_func(bp))
4447                 wait_msec = info->master_func_wait_period;
4448         else
4449                 wait_msec = info->normal_func_wait_period;
4450
4451         rte_eal_alarm_set(US_PER_MS * wait_msec,
4452                           bnxt_fw_reset_cb, (void *)bp);
4453 }
4454
4455 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4456 {
4457         uint32_t polling_freq;
4458
4459         if (!bnxt_is_recovery_enabled(bp))
4460                 return;
4461
4462         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4463                 return;
4464
4465         polling_freq = bp->recovery_info->driver_polling_freq;
4466
4467         rte_eal_alarm_set(US_PER_MS * polling_freq,
4468                           bnxt_check_fw_health, (void *)bp);
4469         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4470 }
4471
4472 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4473 {
4474         if (!bnxt_is_recovery_enabled(bp))
4475                 return;
4476
4477         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4478         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4479 }
4480
4481 static bool bnxt_vf_pciid(uint16_t device_id)
4482 {
4483         switch (device_id) {
4484         case BROADCOM_DEV_ID_57304_VF:
4485         case BROADCOM_DEV_ID_57406_VF:
4486         case BROADCOM_DEV_ID_5731X_VF:
4487         case BROADCOM_DEV_ID_5741X_VF:
4488         case BROADCOM_DEV_ID_57414_VF:
4489         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4490         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4491         case BROADCOM_DEV_ID_58802_VF:
4492         case BROADCOM_DEV_ID_57500_VF1:
4493         case BROADCOM_DEV_ID_57500_VF2:
4494                 /* FALLTHROUGH */
4495                 return true;
4496         default:
4497                 return false;
4498         }
4499 }
4500
4501 static bool bnxt_thor_device(uint16_t device_id)
4502 {
4503         switch (device_id) {
4504         case BROADCOM_DEV_ID_57508:
4505         case BROADCOM_DEV_ID_57504:
4506         case BROADCOM_DEV_ID_57502:
4507         case BROADCOM_DEV_ID_57508_MF1:
4508         case BROADCOM_DEV_ID_57504_MF1:
4509         case BROADCOM_DEV_ID_57502_MF1:
4510         case BROADCOM_DEV_ID_57508_MF2:
4511         case BROADCOM_DEV_ID_57504_MF2:
4512         case BROADCOM_DEV_ID_57502_MF2:
4513         case BROADCOM_DEV_ID_57500_VF1:
4514         case BROADCOM_DEV_ID_57500_VF2:
4515                 /* FALLTHROUGH */
4516                 return true;
4517         default:
4518                 return false;
4519         }
4520 }
4521
4522 bool bnxt_stratus_device(struct bnxt *bp)
4523 {
4524         uint16_t device_id = bp->pdev->id.device_id;
4525
4526         switch (device_id) {
4527         case BROADCOM_DEV_ID_STRATUS_NIC:
4528         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4529         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4530                 /* FALLTHROUGH */
4531                 return true;
4532         default:
4533                 return false;
4534         }
4535 }
4536
4537 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4538 {
4539         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4540         struct bnxt *bp = eth_dev->data->dev_private;
4541
4542         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4543         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4544         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4545         if (!bp->bar0 || !bp->doorbell_base) {
4546                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4547                 return -ENODEV;
4548         }
4549
4550         bp->eth_dev = eth_dev;
4551         bp->pdev = pci_dev;
4552
4553         return 0;
4554 }
4555
4556 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4557                                   struct bnxt_ctx_pg_info *ctx_pg,
4558                                   uint32_t mem_size,
4559                                   const char *suffix,
4560                                   uint16_t idx)
4561 {
4562         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4563         const struct rte_memzone *mz = NULL;
4564         char mz_name[RTE_MEMZONE_NAMESIZE];
4565         rte_iova_t mz_phys_addr;
4566         uint64_t valid_bits = 0;
4567         uint32_t sz;
4568         int i;
4569
4570         if (!mem_size)
4571                 return 0;
4572
4573         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4574                          BNXT_PAGE_SIZE;
4575         rmem->page_size = BNXT_PAGE_SIZE;
4576         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4577         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4578         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4579
4580         valid_bits = PTU_PTE_VALID;
4581
4582         if (rmem->nr_pages > 1) {
4583                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4584                          "bnxt_ctx_pg_tbl%s_%x_%d",
4585                          suffix, idx, bp->eth_dev->data->port_id);
4586                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4587                 mz = rte_memzone_lookup(mz_name);
4588                 if (!mz) {
4589                         mz = rte_memzone_reserve_aligned(mz_name,
4590                                                 rmem->nr_pages * 8,
4591                                                 SOCKET_ID_ANY,
4592                                                 RTE_MEMZONE_2MB |
4593                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4594                                                 RTE_MEMZONE_IOVA_CONTIG,
4595                                                 BNXT_PAGE_SIZE);
4596                         if (mz == NULL)
4597                                 return -ENOMEM;
4598                 }
4599
4600                 memset(mz->addr, 0, mz->len);
4601                 mz_phys_addr = mz->iova;
4602
4603                 rmem->pg_tbl = mz->addr;
4604                 rmem->pg_tbl_map = mz_phys_addr;
4605                 rmem->pg_tbl_mz = mz;
4606         }
4607
4608         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4609                  suffix, idx, bp->eth_dev->data->port_id);
4610         mz = rte_memzone_lookup(mz_name);
4611         if (!mz) {
4612                 mz = rte_memzone_reserve_aligned(mz_name,
4613                                                  mem_size,
4614                                                  SOCKET_ID_ANY,
4615                                                  RTE_MEMZONE_1GB |
4616                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4617                                                  RTE_MEMZONE_IOVA_CONTIG,
4618                                                  BNXT_PAGE_SIZE);
4619                 if (mz == NULL)
4620                         return -ENOMEM;
4621         }
4622
4623         memset(mz->addr, 0, mz->len);
4624         mz_phys_addr = mz->iova;
4625
4626         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4627                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4628                 rmem->dma_arr[i] = mz_phys_addr + sz;
4629
4630                 if (rmem->nr_pages > 1) {
4631                         if (i == rmem->nr_pages - 2 &&
4632                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4633                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4634                         else if (i == rmem->nr_pages - 1 &&
4635                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4636                                 valid_bits |= PTU_PTE_LAST;
4637
4638                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4639                                                            valid_bits);
4640                 }
4641         }
4642
4643         rmem->mz = mz;
4644         if (rmem->vmem_size)
4645                 rmem->vmem = (void **)mz->addr;
4646         rmem->dma_arr[0] = mz_phys_addr;
4647         return 0;
4648 }
4649
4650 static void bnxt_free_ctx_mem(struct bnxt *bp)
4651 {
4652         int i;
4653
4654         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4655                 return;
4656
4657         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4658         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4659         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4660         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4661         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4662         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4663         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4664         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4665         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4666         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4667         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4668
4669         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4670                 if (bp->ctx->tqm_mem[i])
4671                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4672         }
4673
4674         rte_free(bp->ctx);
4675         bp->ctx = NULL;
4676 }
4677
4678 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4679
4680 #define min_t(type, x, y) ({                    \
4681         type __min1 = (x);                      \
4682         type __min2 = (y);                      \
4683         __min1 < __min2 ? __min1 : __min2; })
4684
4685 #define max_t(type, x, y) ({                    \
4686         type __max1 = (x);                      \
4687         type __max2 = (y);                      \
4688         __max1 > __max2 ? __max1 : __max2; })
4689
4690 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4691
4692 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4693 {
4694         struct bnxt_ctx_pg_info *ctx_pg;
4695         struct bnxt_ctx_mem_info *ctx;
4696         uint32_t mem_size, ena, entries;
4697         uint32_t entries_sp, min;
4698         int i, rc;
4699
4700         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4701         if (rc) {
4702                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4703                 return rc;
4704         }
4705         ctx = bp->ctx;
4706         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4707                 return 0;
4708
4709         ctx_pg = &ctx->qp_mem;
4710         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4711         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4712         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4713         if (rc)
4714                 return rc;
4715
4716         ctx_pg = &ctx->srq_mem;
4717         ctx_pg->entries = ctx->srq_max_l2_entries;
4718         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4719         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4720         if (rc)
4721                 return rc;
4722
4723         ctx_pg = &ctx->cq_mem;
4724         ctx_pg->entries = ctx->cq_max_l2_entries;
4725         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4726         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4727         if (rc)
4728                 return rc;
4729
4730         ctx_pg = &ctx->vnic_mem;
4731         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4732                 ctx->vnic_max_ring_table_entries;
4733         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4734         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4735         if (rc)
4736                 return rc;
4737
4738         ctx_pg = &ctx->stat_mem;
4739         ctx_pg->entries = ctx->stat_max_entries;
4740         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4741         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4742         if (rc)
4743                 return rc;
4744
4745         min = ctx->tqm_min_entries_per_ring;
4746
4747         entries_sp = ctx->qp_max_l2_entries +
4748                      ctx->vnic_max_vnic_entries +
4749                      2 * ctx->qp_min_qp1_entries + min;
4750         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4751
4752         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4753         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4754         entries = clamp_t(uint32_t, entries, min,
4755                           ctx->tqm_max_entries_per_ring);
4756         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4757                 ctx_pg = ctx->tqm_mem[i];
4758                 ctx_pg->entries = i ? entries : entries_sp;
4759                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4760                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4761                 if (rc)
4762                         return rc;
4763                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4764         }
4765
4766         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4767         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4768         if (rc)
4769                 PMD_DRV_LOG(ERR,
4770                             "Failed to configure context mem: rc = %d\n", rc);
4771         else
4772                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4773
4774         return rc;
4775 }
4776
4777 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4778 {
4779         struct rte_pci_device *pci_dev = bp->pdev;
4780         char mz_name[RTE_MEMZONE_NAMESIZE];
4781         const struct rte_memzone *mz = NULL;
4782         uint32_t total_alloc_len;
4783         rte_iova_t mz_phys_addr;
4784
4785         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4786                 return 0;
4787
4788         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4789                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4790                  pci_dev->addr.bus, pci_dev->addr.devid,
4791                  pci_dev->addr.function, "rx_port_stats");
4792         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4793         mz = rte_memzone_lookup(mz_name);
4794         total_alloc_len =
4795                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4796                                        sizeof(struct rx_port_stats_ext) + 512);
4797         if (!mz) {
4798                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4799                                          SOCKET_ID_ANY,
4800                                          RTE_MEMZONE_2MB |
4801                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4802                                          RTE_MEMZONE_IOVA_CONTIG);
4803                 if (mz == NULL)
4804                         return -ENOMEM;
4805         }
4806         memset(mz->addr, 0, mz->len);
4807         mz_phys_addr = mz->iova;
4808
4809         bp->rx_mem_zone = (const void *)mz;
4810         bp->hw_rx_port_stats = mz->addr;
4811         bp->hw_rx_port_stats_map = mz_phys_addr;
4812
4813         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4814                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4815                  pci_dev->addr.bus, pci_dev->addr.devid,
4816                  pci_dev->addr.function, "tx_port_stats");
4817         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4818         mz = rte_memzone_lookup(mz_name);
4819         total_alloc_len =
4820                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4821                                        sizeof(struct tx_port_stats_ext) + 512);
4822         if (!mz) {
4823                 mz = rte_memzone_reserve(mz_name,
4824                                          total_alloc_len,
4825                                          SOCKET_ID_ANY,
4826                                          RTE_MEMZONE_2MB |
4827                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4828                                          RTE_MEMZONE_IOVA_CONTIG);
4829                 if (mz == NULL)
4830                         return -ENOMEM;
4831         }
4832         memset(mz->addr, 0, mz->len);
4833         mz_phys_addr = mz->iova;
4834
4835         bp->tx_mem_zone = (const void *)mz;
4836         bp->hw_tx_port_stats = mz->addr;
4837         bp->hw_tx_port_stats_map = mz_phys_addr;
4838         bp->flags |= BNXT_FLAG_PORT_STATS;
4839
4840         /* Display extended statistics if FW supports it */
4841         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4842             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4843             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4844                 return 0;
4845
4846         bp->hw_rx_port_stats_ext = (void *)
4847                 ((uint8_t *)bp->hw_rx_port_stats +
4848                  sizeof(struct rx_port_stats));
4849         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4850                 sizeof(struct rx_port_stats);
4851         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4852
4853         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4854             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4855                 bp->hw_tx_port_stats_ext = (void *)
4856                         ((uint8_t *)bp->hw_tx_port_stats +
4857                          sizeof(struct tx_port_stats));
4858                 bp->hw_tx_port_stats_ext_map =
4859                         bp->hw_tx_port_stats_map +
4860                         sizeof(struct tx_port_stats);
4861                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4862         }
4863
4864         return 0;
4865 }
4866
4867 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4868 {
4869         struct bnxt *bp = eth_dev->data->dev_private;
4870         int rc = 0;
4871
4872         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4873                                                RTE_ETHER_ADDR_LEN *
4874                                                bp->max_l2_ctx,
4875                                                0);
4876         if (eth_dev->data->mac_addrs == NULL) {
4877                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4878                 return -ENOMEM;
4879         }
4880
4881         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4882                 if (BNXT_PF(bp))
4883                         return -EINVAL;
4884
4885                 /* Generate a random MAC address, if none was assigned by PF */
4886                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4887                 bnxt_eth_hw_addr_random(bp->mac_addr);
4888                 PMD_DRV_LOG(INFO,
4889                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4890                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4891                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4892
4893                 rc = bnxt_hwrm_set_mac(bp);
4894                 if (!rc)
4895                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4896                                RTE_ETHER_ADDR_LEN);
4897                 return rc;
4898         }
4899
4900         /* Copy the permanent MAC from the FUNC_QCAPS response */
4901         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4902         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4903
4904         return rc;
4905 }
4906
4907 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4908 {
4909         int rc = 0;
4910
4911         /* MAC is already configured in FW */
4912         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4913                 return 0;
4914
4915         /* Restore the old MAC configured */
4916         rc = bnxt_hwrm_set_mac(bp);
4917         if (rc)
4918                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4919
4920         return rc;
4921 }
4922
4923 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4924 {
4925         if (!BNXT_PF(bp))
4926                 return;
4927
4928 #define ALLOW_FUNC(x)   \
4929         { \
4930                 uint32_t arg = (x); \
4931                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4932                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4933         }
4934
4935         /* Forward all requests if firmware is new enough */
4936         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4937              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4938             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4939                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4940         } else {
4941                 PMD_DRV_LOG(WARNING,
4942                             "Firmware too old for VF mailbox functionality\n");
4943                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4944         }
4945
4946         /*
4947          * The following are used for driver cleanup. If we disallow these,
4948          * VF drivers can't clean up cleanly.
4949          */
4950         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4951         ALLOW_FUNC(HWRM_VNIC_FREE);
4952         ALLOW_FUNC(HWRM_RING_FREE);
4953         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4954         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4955         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4956         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4957         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4958         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4959 }
4960
4961 uint16_t
4962 bnxt_get_svif(uint16_t port_id, bool func_svif)
4963 {
4964         struct rte_eth_dev *eth_dev;
4965         struct bnxt *bp;
4966
4967         eth_dev = &rte_eth_devices[port_id];
4968         bp = eth_dev->data->dev_private;
4969
4970         return func_svif ? bp->func_svif : bp->port_svif;
4971 }
4972
4973 uint16_t
4974 bnxt_get_vnic_id(uint16_t port)
4975 {
4976         struct rte_eth_dev *eth_dev;
4977         struct bnxt_vnic_info *vnic;
4978         struct bnxt *bp;
4979
4980         eth_dev = &rte_eth_devices[port];
4981         bp = eth_dev->data->dev_private;
4982
4983         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4984
4985         return vnic->fw_vnic_id;
4986 }
4987
4988 uint16_t
4989 bnxt_get_fw_func_id(uint16_t port)
4990 {
4991         struct rte_eth_dev *eth_dev;
4992         struct bnxt *bp;
4993
4994         eth_dev = &rte_eth_devices[port];
4995         bp = eth_dev->data->dev_private;
4996
4997         return bp->fw_fid;
4998 }
4999
5000 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5001 {
5002         struct bnxt_error_recovery_info *info = bp->recovery_info;
5003
5004         if (info) {
5005                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5006                         memset(info, 0, sizeof(*info));
5007                 return;
5008         }
5009
5010         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5011                 return;
5012
5013         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5014                            sizeof(*info), 0);
5015         if (!info)
5016                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5017
5018         bp->recovery_info = info;
5019 }
5020
5021 static void bnxt_check_fw_status(struct bnxt *bp)
5022 {
5023         uint32_t fw_status;
5024
5025         if (!(bp->recovery_info &&
5026               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5027                 return;
5028
5029         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5030         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5031                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5032                             fw_status);
5033 }
5034
5035 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5036 {
5037         struct bnxt_error_recovery_info *info = bp->recovery_info;
5038         uint32_t status_loc;
5039         uint32_t sig_ver;
5040
5041         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5042                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5043         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5044                                    BNXT_GRCP_WINDOW_2_BASE +
5045                                    offsetof(struct hcomm_status,
5046                                             sig_ver)));
5047         /* If the signature is absent, then FW does not support this feature */
5048         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5049             HCOMM_STATUS_SIGNATURE_VAL)
5050                 return 0;
5051
5052         if (!info) {
5053                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5054                                    sizeof(*info), 0);
5055                 if (!info)
5056                         return -ENOMEM;
5057                 bp->recovery_info = info;
5058         } else {
5059                 memset(info, 0, sizeof(*info));
5060         }
5061
5062         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5063                                       BNXT_GRCP_WINDOW_2_BASE +
5064                                       offsetof(struct hcomm_status,
5065                                                fw_status_loc)));
5066
5067         /* Only pre-map the FW health status GRC register */
5068         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5069                 return 0;
5070
5071         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5072         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5073                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5074
5075         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5076                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5077
5078         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5079
5080         return 0;
5081 }
5082
5083 static int bnxt_init_fw(struct bnxt *bp)
5084 {
5085         uint16_t mtu;
5086         int rc = 0;
5087
5088         bp->fw_cap = 0;
5089
5090         rc = bnxt_map_hcomm_fw_status_reg(bp);
5091         if (rc)
5092                 return rc;
5093
5094         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5095         if (rc) {
5096                 bnxt_check_fw_status(bp);
5097                 return rc;
5098         }
5099
5100         rc = bnxt_hwrm_func_reset(bp);
5101         if (rc)
5102                 return -EIO;
5103
5104         rc = bnxt_hwrm_vnic_qcaps(bp);
5105         if (rc)
5106                 return rc;
5107
5108         rc = bnxt_hwrm_queue_qportcfg(bp);
5109         if (rc)
5110                 return rc;
5111
5112         /* Get the MAX capabilities for this function.
5113          * This function also allocates context memory for TQM rings and
5114          * informs the firmware about this allocated backing store memory.
5115          */
5116         rc = bnxt_hwrm_func_qcaps(bp);
5117         if (rc)
5118                 return rc;
5119
5120         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5121         if (rc)
5122                 return rc;
5123
5124         bnxt_hwrm_port_mac_qcfg(bp);
5125
5126         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5127         if (rc)
5128                 return rc;
5129
5130         bnxt_alloc_error_recovery_info(bp);
5131         /* Get the adapter error recovery support info */
5132         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5133         if (rc)
5134                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5135
5136         bnxt_hwrm_port_led_qcaps(bp);
5137
5138         return 0;
5139 }
5140
5141 static int
5142 bnxt_init_locks(struct bnxt *bp)
5143 {
5144         int err;
5145
5146         err = pthread_mutex_init(&bp->flow_lock, NULL);
5147         if (err) {
5148                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5149                 return err;
5150         }
5151
5152         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5153         if (err)
5154                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5155         return err;
5156 }
5157
5158 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5159 {
5160         int rc;
5161
5162         rc = bnxt_init_fw(bp);
5163         if (rc)
5164                 return rc;
5165
5166         if (!reconfig_dev) {
5167                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5168                 if (rc)
5169                         return rc;
5170         } else {
5171                 rc = bnxt_restore_dflt_mac(bp);
5172                 if (rc)
5173                         return rc;
5174         }
5175
5176         bnxt_config_vf_req_fwd(bp);
5177
5178         rc = bnxt_hwrm_func_driver_register(bp);
5179         if (rc) {
5180                 PMD_DRV_LOG(ERR, "Failed to register driver");
5181                 return -EBUSY;
5182         }
5183
5184         if (BNXT_PF(bp)) {
5185                 if (bp->pdev->max_vfs) {
5186                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5187                         if (rc) {
5188                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5189                                 return rc;
5190                         }
5191                 } else {
5192                         rc = bnxt_hwrm_allocate_pf_only(bp);
5193                         if (rc) {
5194                                 PMD_DRV_LOG(ERR,
5195                                             "Failed to allocate PF resources");
5196                                 return rc;
5197                         }
5198                 }
5199         }
5200
5201         rc = bnxt_alloc_mem(bp, reconfig_dev);
5202         if (rc)
5203                 return rc;
5204
5205         rc = bnxt_setup_int(bp);
5206         if (rc)
5207                 return rc;
5208
5209         rc = bnxt_request_int(bp);
5210         if (rc)
5211                 return rc;
5212
5213         rc = bnxt_init_ctx_mem(bp);
5214         if (rc) {
5215                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5216                 return rc;
5217         }
5218
5219         rc = bnxt_init_locks(bp);
5220         if (rc)
5221                 return rc;
5222
5223         return 0;
5224 }
5225
5226 static int
5227 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5228                           const char *value, void *opaque_arg)
5229 {
5230         struct bnxt *bp = opaque_arg;
5231         unsigned long truflow;
5232         char *end = NULL;
5233
5234         if (!value || !opaque_arg) {
5235                 PMD_DRV_LOG(ERR,
5236                             "Invalid parameter passed to truflow devargs.\n");
5237                 return -EINVAL;
5238         }
5239
5240         truflow = strtoul(value, &end, 10);
5241         if (end == NULL || *end != '\0' ||
5242             (truflow == ULONG_MAX && errno == ERANGE)) {
5243                 PMD_DRV_LOG(ERR,
5244                             "Invalid parameter passed to truflow devargs.\n");
5245                 return -EINVAL;
5246         }
5247
5248         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5249                 PMD_DRV_LOG(ERR,
5250                             "Invalid value passed to truflow devargs.\n");
5251                 return -EINVAL;
5252         }
5253
5254         bp->truflow = truflow;
5255         if (bp->truflow)
5256                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5257
5258         return 0;
5259 }
5260
5261 static int
5262 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5263                              const char *value, void *opaque_arg)
5264 {
5265         struct bnxt *bp = opaque_arg;
5266         unsigned long flow_xstat;
5267         char *end = NULL;
5268
5269         if (!value || !opaque_arg) {
5270                 PMD_DRV_LOG(ERR,
5271                             "Invalid parameter passed to flow_xstat devarg.\n");
5272                 return -EINVAL;
5273         }
5274
5275         flow_xstat = strtoul(value, &end, 10);
5276         if (end == NULL || *end != '\0' ||
5277             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5278                 PMD_DRV_LOG(ERR,
5279                             "Invalid parameter passed to flow_xstat devarg.\n");
5280                 return -EINVAL;
5281         }
5282
5283         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5284                 PMD_DRV_LOG(ERR,
5285                             "Invalid value passed to flow_xstat devarg.\n");
5286                 return -EINVAL;
5287         }
5288
5289         bp->flow_xstat = flow_xstat;
5290         if (bp->flow_xstat)
5291                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5292
5293         return 0;
5294 }
5295
5296 static void
5297 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5298 {
5299         struct rte_kvargs *kvlist;
5300
5301         if (devargs == NULL)
5302                 return;
5303
5304         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5305         if (kvlist == NULL)
5306                 return;
5307
5308         /*
5309          * Handler for "truflow" devarg.
5310          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1”
5311          */
5312         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5313                            bnxt_parse_devarg_truflow, bp);
5314
5315         /*
5316          * Handler for "flow_xstat" devarg.
5317          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1”
5318          */
5319         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5320                            bnxt_parse_devarg_flow_xstat, bp);
5321
5322         rte_kvargs_free(kvlist);
5323 }
5324
5325 static int
5326 bnxt_dev_init(struct rte_eth_dev *eth_dev)
5327 {
5328         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5329         static int version_printed;
5330         struct bnxt *bp;
5331         int rc;
5332
5333         if (version_printed++ == 0)
5334                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5335
5336         eth_dev->dev_ops = &bnxt_dev_ops;
5337         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5338         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5339
5340         /*
5341          * For secondary processes, we don't initialise any further
5342          * as primary has already done this work.
5343          */
5344         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5345                 return 0;
5346
5347         rte_eth_copy_pci_info(eth_dev, pci_dev);
5348
5349         bp = eth_dev->data->dev_private;
5350
5351         /* Parse dev arguments passed on when starting the DPDK application. */
5352         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5353
5354         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5355
5356         if (bnxt_vf_pciid(pci_dev->id.device_id))
5357                 bp->flags |= BNXT_FLAG_VF;
5358
5359         if (bnxt_thor_device(pci_dev->id.device_id))
5360                 bp->flags |= BNXT_FLAG_THOR_CHIP;
5361
5362         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5363             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5364             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5365             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5366                 bp->flags |= BNXT_FLAG_STINGRAY;
5367
5368         rc = bnxt_init_board(eth_dev);
5369         if (rc) {
5370                 PMD_DRV_LOG(ERR,
5371                             "Failed to initialize board rc: %x\n", rc);
5372                 return rc;
5373         }
5374
5375         rc = bnxt_alloc_hwrm_resources(bp);
5376         if (rc) {
5377                 PMD_DRV_LOG(ERR,
5378                             "Failed to allocate hwrm resource rc: %x\n", rc);
5379                 goto error_free;
5380         }
5381         rc = bnxt_alloc_leds_info(bp);
5382         if (rc)
5383                 goto error_free;
5384
5385         rc = bnxt_init_resources(bp, false);
5386         if (rc)
5387                 goto error_free;
5388
5389         rc = bnxt_alloc_stats_mem(bp);
5390         if (rc)
5391                 goto error_free;
5392
5393         /* Pass the information to the rte_eth_dev_close() that it should also
5394          * release the private port resources.
5395          */
5396         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5397
5398         PMD_DRV_LOG(INFO,
5399                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5400                     pci_dev->mem_resource[0].phys_addr,
5401                     pci_dev->mem_resource[0].addr);
5402
5403         return 0;
5404
5405 error_free:
5406         bnxt_dev_uninit(eth_dev);
5407         return rc;
5408 }
5409
5410
5411 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5412 {
5413         if (!ctx)
5414                 return;
5415
5416         if (ctx->va)
5417                 rte_free(ctx->va);
5418
5419         ctx->va = NULL;
5420         ctx->dma = RTE_BAD_IOVA;
5421         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5422 }
5423
5424 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5425 {
5426         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5427                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5428                                   bp->rx_fc_out_tbl.ctx_id,
5429                                   bp->max_fc,
5430                                   false);
5431
5432         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5433                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5434                                   bp->tx_fc_out_tbl.ctx_id,
5435                                   bp->max_fc,
5436                                   false);
5437
5438         if (bp->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5439                 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_in_tbl.ctx_id);
5440         bp->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5441
5442         if (bp->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5443                 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_out_tbl.ctx_id);
5444         bp->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5445
5446         if (bp->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5447                 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_in_tbl.ctx_id);
5448         bp->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5449
5450         if (bp->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5451                 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_out_tbl.ctx_id);
5452         bp->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5453 }
5454
5455 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5456 {
5457         bnxt_unregister_fc_ctx_mem(bp);
5458
5459         bnxt_free_ctx_mem_buf(&bp->rx_fc_in_tbl);
5460         bnxt_free_ctx_mem_buf(&bp->rx_fc_out_tbl);
5461         bnxt_free_ctx_mem_buf(&bp->tx_fc_in_tbl);
5462         bnxt_free_ctx_mem_buf(&bp->tx_fc_out_tbl);
5463 }
5464
5465 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5466 {
5467         bnxt_uninit_fc_ctx_mem(bp);
5468 }
5469
5470 static void
5471 bnxt_free_error_recovery_info(struct bnxt *bp)
5472 {
5473         rte_free(bp->recovery_info);
5474         bp->recovery_info = NULL;
5475         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5476 }
5477
5478 static void
5479 bnxt_uninit_locks(struct bnxt *bp)
5480 {
5481         pthread_mutex_destroy(&bp->flow_lock);
5482         pthread_mutex_destroy(&bp->def_cp_lock);
5483 }
5484
5485 static int
5486 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5487 {
5488         int rc;
5489
5490         bnxt_free_int(bp);
5491         bnxt_free_mem(bp, reconfig_dev);
5492         bnxt_hwrm_func_buf_unrgtr(bp);
5493         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5494         bp->flags &= ~BNXT_FLAG_REGISTERED;
5495         bnxt_free_ctx_mem(bp);
5496         if (!reconfig_dev) {
5497                 bnxt_free_hwrm_resources(bp);
5498                 bnxt_free_error_recovery_info(bp);
5499         }
5500
5501         bnxt_uninit_ctx_mem(bp);
5502
5503         bnxt_uninit_locks(bp);
5504         rte_free(bp->ptp_cfg);
5505         bp->ptp_cfg = NULL;
5506         return rc;
5507 }
5508
5509 static int
5510 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5511 {
5512         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5513                 return -EPERM;
5514
5515         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5516
5517         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5518                 bnxt_dev_close_op(eth_dev);
5519
5520         return 0;
5521 }
5522
5523 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5524         struct rte_pci_device *pci_dev)
5525 {
5526         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
5527                 bnxt_dev_init);
5528 }
5529
5530 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5531 {
5532         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
5533                 return rte_eth_dev_pci_generic_remove(pci_dev,
5534                                 bnxt_dev_uninit);
5535         else
5536                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5537 }
5538
5539 static struct rte_pci_driver bnxt_rte_pmd = {
5540         .id_table = bnxt_pci_id_map,
5541         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5542         .probe = bnxt_pci_probe,
5543         .remove = bnxt_pci_remove,
5544 };
5545
5546 static bool
5547 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5548 {
5549         if (strcmp(dev->device->driver->name, drv->driver.name))
5550                 return false;
5551
5552         return true;
5553 }
5554
5555 bool is_bnxt_supported(struct rte_eth_dev *dev)
5556 {
5557         return is_device_supported(dev, &bnxt_rte_pmd);
5558 }
5559
5560 RTE_INIT(bnxt_init_log)
5561 {
5562         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
5563         if (bnxt_logtype_driver >= 0)
5564                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
5565 }
5566
5567 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5568 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5569 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");