drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31 #include "bnxt_tf_common.h"
  32 #include "ulp_flow_db.h"
  33
  34 #define DRV_MODULE_NAME         "bnxt"
  35 static const char bnxt_version[] =
  36         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  37
  38 /*
  39  * The set of PCI devices this driver supports
  40  */
  41 static const struct rte_pci_id bnxt_pci_id_map[] = {
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  95         { .vendor_id = 0, /* sentinel */ },
  96 };
  97
  98 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  99 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 100 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 101 #define BNXT_DEVARG_REPRESENTOR "representor"
 102
 103 static const char *const bnxt_dev_args[] = {
 104         BNXT_DEVARG_REPRESENTOR,
 105         BNXT_DEVARG_TRUFLOW,
 106         BNXT_DEVARG_FLOW_XSTAT,
 107         BNXT_DEVARG_MAX_NUM_KFLOWS,
 108         NULL
 109 };
 110
 111 /*
 112  * truflow == false to disable the feature
 113  * truflow == true to enable the feature
 114  */
 115 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 116
 117 /*
 118  * flow_xstat == false to disable the feature
 119  * flow_xstat == true to enable the feature
 120  */
 121 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 122
 123 /*
 124  * max_num_kflows must be >= 32
 125  * and must be a power-of-2 supported value
 126  * return: 1 -> invalid
 127  *         0 -> valid
 128  */
 129 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 130 {
 131         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 132                 return 1;
 133         return 0;
 134 }
 135
 136 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 137 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 138 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 139 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 140 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 141 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 142 static void bnxt_dev_recover(void *arg);
 143 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 144 static void bnxt_free_rep_info(struct bnxt *bp);
 145
 146 int is_bnxt_in_error(struct bnxt *bp)
 147 {
 148         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 149                 return -EIO;
 150         if (bp->flags & BNXT_FLAG_FW_RESET)
 151                 return -EBUSY;
 152
 153         return 0;
 154 }
 155
 156 /***********************/
 157
 158 /*
 159  * High level utility functions
 160  */
 161
 162 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 163 {
 164         if (!BNXT_CHIP_THOR(bp))
 165                 return 1;
 166
 167         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 168                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 169                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 170 }
 171
 172 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 173 {
 174         if (!BNXT_CHIP_THOR(bp))
 175                 return HW_HASH_INDEX_SIZE;
 176
 177         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 178 }
 179
 180 static void bnxt_free_parent_info(struct bnxt *bp)
 181 {
 182         rte_free(bp->parent);
 183 }
 184
 185 static void bnxt_free_pf_info(struct bnxt *bp)
 186 {
 187         rte_free(bp->pf);
 188 }
 189
 190 static void bnxt_free_link_info(struct bnxt *bp)
 191 {
 192         rte_free(bp->link_info);
 193 }
 194
 195 static void bnxt_free_leds_info(struct bnxt *bp)
 196 {
 197         if (BNXT_VF(bp))
 198                 return;
 199
 200         rte_free(bp->leds);
 201         bp->leds = NULL;
 202 }
 203
 204 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 205 {
 206         rte_free(bp->flow_stat);
 207         bp->flow_stat = NULL;
 208 }
 209
 210 static void bnxt_free_cos_queues(struct bnxt *bp)
 211 {
 212         rte_free(bp->rx_cos_queue);
 213         rte_free(bp->tx_cos_queue);
 214 }
 215
 216 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 217 {
 218         bnxt_free_filter_mem(bp);
 219         bnxt_free_vnic_attributes(bp);
 220         bnxt_free_vnic_mem(bp);
 221
 222         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 223          * If the number of rings change across fw update,
 224          * we don't have much choice except to warn the user.
 225          */
 226         if (!reconfig) {
 227                 bnxt_free_stats(bp);
 228                 bnxt_free_tx_rings(bp);
 229                 bnxt_free_rx_rings(bp);
 230         }
 231         bnxt_free_async_cp_ring(bp);
 232         bnxt_free_rxtx_nq_ring(bp);
 233
 234         rte_free(bp->grp_info);
 235         bp->grp_info = NULL;
 236 }
 237
 238 static int bnxt_alloc_parent_info(struct bnxt *bp)
 239 {
 240         bp->parent = rte_zmalloc("bnxt_parent_info",
 241                                  sizeof(struct bnxt_parent_info), 0);
 242         if (bp->parent == NULL)
 243                 return -ENOMEM;
 244
 245         return 0;
 246 }
 247
 248 static int bnxt_alloc_pf_info(struct bnxt *bp)
 249 {
 250         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 251         if (bp->pf == NULL)
 252                 return -ENOMEM;
 253
 254         return 0;
 255 }
 256
 257 static int bnxt_alloc_link_info(struct bnxt *bp)
 258 {
 259         bp->link_info =
 260                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 261         if (bp->link_info == NULL)
 262                 return -ENOMEM;
 263
 264         return 0;
 265 }
 266
 267 static int bnxt_alloc_leds_info(struct bnxt *bp)
 268 {
 269         if (BNXT_VF(bp))
 270                 return 0;
 271
 272         bp->leds = rte_zmalloc("bnxt_leds",
 273                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 274                                0);
 275         if (bp->leds == NULL)
 276                 return -ENOMEM;
 277
 278         return 0;
 279 }
 280
 281 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 282 {
 283         bp->rx_cos_queue =
 284                 rte_zmalloc("bnxt_rx_cosq",
 285                             BNXT_COS_QUEUE_COUNT *
 286                             sizeof(struct bnxt_cos_queue_info),
 287                             0);
 288         if (bp->rx_cos_queue == NULL)
 289                 return -ENOMEM;
 290
 291         bp->tx_cos_queue =
 292                 rte_zmalloc("bnxt_tx_cosq",
 293                             BNXT_COS_QUEUE_COUNT *
 294                             sizeof(struct bnxt_cos_queue_info),
 295                             0);
 296         if (bp->tx_cos_queue == NULL)
 297                 return -ENOMEM;
 298
 299         return 0;
 300 }
 301
 302 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 303 {
 304         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 305                                     sizeof(struct bnxt_flow_stat_info), 0);
 306         if (bp->flow_stat == NULL)
 307                 return -ENOMEM;
 308
 309         return 0;
 310 }
 311
 312 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 313 {
 314         int rc;
 315
 316         rc = bnxt_alloc_ring_grps(bp);
 317         if (rc)
 318                 goto alloc_mem_err;
 319
 320         rc = bnxt_alloc_async_ring_struct(bp);
 321         if (rc)
 322                 goto alloc_mem_err;
 323
 324         rc = bnxt_alloc_vnic_mem(bp);
 325         if (rc)
 326                 goto alloc_mem_err;
 327
 328         rc = bnxt_alloc_vnic_attributes(bp);
 329         if (rc)
 330                 goto alloc_mem_err;
 331
 332         rc = bnxt_alloc_filter_mem(bp);
 333         if (rc)
 334                 goto alloc_mem_err;
 335
 336         rc = bnxt_alloc_async_cp_ring(bp);
 337         if (rc)
 338                 goto alloc_mem_err;
 339
 340         rc = bnxt_alloc_rxtx_nq_ring(bp);
 341         if (rc)
 342                 goto alloc_mem_err;
 343
 344         if (BNXT_FLOW_XSTATS_EN(bp)) {
 345                 rc = bnxt_alloc_flow_stats_info(bp);
 346                 if (rc)
 347                         goto alloc_mem_err;
 348         }
 349
 350         return 0;
 351
 352 alloc_mem_err:
 353         bnxt_free_mem(bp, reconfig);
 354         return rc;
 355 }
 356
 357 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 358 {
 359         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 360         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 361         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 362         struct bnxt_rx_queue *rxq;
 363         unsigned int j;
 364         int rc;
 365
 366         rc = bnxt_vnic_grp_alloc(bp, vnic);
 367         if (rc)
 368                 goto err_out;
 369
 370         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 371                     vnic_id, vnic, vnic->fw_grp_ids);
 372
 373         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 374         if (rc)
 375                 goto err_out;
 376
 377         /* Alloc RSS context only if RSS mode is enabled */
 378         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 379                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 380
 381                 rc = 0;
 382                 for (j = 0; j < nr_ctxs; j++) {
 383                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 384                         if (rc)
 385                                 break;
 386                 }
 387                 if (rc) {
 388                         PMD_DRV_LOG(ERR,
 389                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 390                                     vnic_id, j, rc);
 391                         goto err_out;
 392                 }
 393                 vnic->num_lb_ctxts = nr_ctxs;
 394         }
 395
 396         /*
 397          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 398          * setting is not available at this time, it will not be
 399          * configured correctly in the CFA.
 400          */
 401         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 402                 vnic->vlan_strip = true;
 403         else
 404                 vnic->vlan_strip = false;
 405
 406         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 407         if (rc)
 408                 goto err_out;
 409
 410         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 411         if (rc)
 412                 goto err_out;
 413
 414         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 415                 rxq = bp->eth_dev->data->rx_queues[j];
 416
 417                 PMD_DRV_LOG(DEBUG,
 418                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 419                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 420
 421                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 422                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 423                 else
 424                         vnic->rx_queue_cnt++;
 425         }
 426
 427         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 428
 429         rc = bnxt_vnic_rss_configure(bp, vnic);
 430         if (rc)
 431                 goto err_out;
 432
 433         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 434
 435         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 436                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 437         else
 438                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 439
 440         return 0;
 441 err_out:
 442         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 443                     vnic_id, rc);
 444         return rc;
 445 }
 446
 447 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 448 {
 449         int rc = 0;
 450
 451         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 452                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 453         if (rc)
 454                 return rc;
 455
 456         PMD_DRV_LOG(DEBUG,
 457                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 458                     " rx_fc_in_tbl.ctx_id = %d\n",
 459                     bp->flow_stat->rx_fc_in_tbl.va,
 460                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 461                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 462
 463         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 464                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 465         if (rc)
 466                 return rc;
 467
 468         PMD_DRV_LOG(DEBUG,
 469                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 470                     " rx_fc_out_tbl.ctx_id = %d\n",
 471                     bp->flow_stat->rx_fc_out_tbl.va,
 472                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 473                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 474
 475         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 476                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 477         if (rc)
 478                 return rc;
 479
 480         PMD_DRV_LOG(DEBUG,
 481                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 482                     " tx_fc_in_tbl.ctx_id = %d\n",
 483                     bp->flow_stat->tx_fc_in_tbl.va,
 484                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 485                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 486
 487         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 488                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 489         if (rc)
 490                 return rc;
 491
 492         PMD_DRV_LOG(DEBUG,
 493                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 494                     " tx_fc_out_tbl.ctx_id = %d\n",
 495                     bp->flow_stat->tx_fc_out_tbl.va,
 496                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 497                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 498
 499         memset(bp->flow_stat->rx_fc_out_tbl.va,
 500                0,
 501                bp->flow_stat->rx_fc_out_tbl.size);
 502         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 503                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 504                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 505                                        bp->flow_stat->max_fc,
 506                                        true);
 507         if (rc)
 508                 return rc;
 509
 510         memset(bp->flow_stat->tx_fc_out_tbl.va,
 511                0,
 512                bp->flow_stat->tx_fc_out_tbl.size);
 513         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 514                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 515                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 516                                        bp->flow_stat->max_fc,
 517                                        true);
 518
 519         return rc;
 520 }
 521
 522 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 523                                   struct bnxt_ctx_mem_buf_info *ctx)
 524 {
 525         if (!ctx)
 526                 return -EINVAL;
 527
 528         ctx->va = rte_zmalloc(type, size, 0);
 529         if (ctx->va == NULL)
 530                 return -ENOMEM;
 531         rte_mem_lock_page(ctx->va);
 532         ctx->size = size;
 533         ctx->dma = rte_mem_virt2iova(ctx->va);
 534         if (ctx->dma == RTE_BAD_IOVA)
 535                 return -ENOMEM;
 536
 537         return 0;
 538 }
 539
 540 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 541 {
 542         struct rte_pci_device *pdev = bp->pdev;
 543         char type[RTE_MEMZONE_NAMESIZE];
 544         uint16_t max_fc;
 545         int rc = 0;
 546
 547         max_fc = bp->flow_stat->max_fc;
 548
 549         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 550                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 551         /* 4 bytes for each counter-id */
 552         rc = bnxt_alloc_ctx_mem_buf(type,
 553                                     max_fc * 4,
 554                                     &bp->flow_stat->rx_fc_in_tbl);
 555         if (rc)
 556                 return rc;
 557
 558         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 559                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 560         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 561         rc = bnxt_alloc_ctx_mem_buf(type,
 562                                     max_fc * 16,
 563                                     &bp->flow_stat->rx_fc_out_tbl);
 564         if (rc)
 565                 return rc;
 566
 567         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 568                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 569         /* 4 bytes for each counter-id */
 570         rc = bnxt_alloc_ctx_mem_buf(type,
 571                                     max_fc * 4,
 572                                     &bp->flow_stat->tx_fc_in_tbl);
 573         if (rc)
 574                 return rc;
 575
 576         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 577                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 578         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 579         rc = bnxt_alloc_ctx_mem_buf(type,
 580                                     max_fc * 16,
 581                                     &bp->flow_stat->tx_fc_out_tbl);
 582         if (rc)
 583                 return rc;
 584
 585         rc = bnxt_register_fc_ctx_mem(bp);
 586
 587         return rc;
 588 }
 589
 590 static int bnxt_init_ctx_mem(struct bnxt *bp)
 591 {
 592         int rc = 0;
 593
 594         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 595             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 596             !BNXT_FLOW_XSTATS_EN(bp))
 597                 return 0;
 598
 599         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 600         if (rc)
 601                 return rc;
 602
 603         rc = bnxt_init_fc_ctx_mem(bp);
 604
 605         return rc;
 606 }
 607
 608 static int bnxt_init_chip(struct bnxt *bp)
 609 {
 610         struct rte_eth_link new;
 611         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 612         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 613         uint32_t intr_vector = 0;
 614         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 615         uint32_t vec = BNXT_MISC_VEC_ID;
 616         unsigned int i, j;
 617         int rc;
 618
 619         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 620                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 621                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 622                 bp->flags |= BNXT_FLAG_JUMBO;
 623         } else {
 624                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 625                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 626                 bp->flags &= ~BNXT_FLAG_JUMBO;
 627         }
 628
 629         /* THOR does not support ring groups.
 630          * But we will use the array to save RSS context IDs.
 631          */
 632         if (BNXT_CHIP_THOR(bp))
 633                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 634
 635         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 636         if (rc) {
 637                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 638                 goto err_out;
 639         }
 640
 641         rc = bnxt_alloc_hwrm_rings(bp);
 642         if (rc) {
 643                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 644                 goto err_out;
 645         }
 646
 647         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 648         if (rc) {
 649                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 650                 goto err_out;
 651         }
 652
 653         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 654                 goto skip_cosq_cfg;
 655
 656         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 657                 if (bp->rx_cos_queue[i].id != 0xff) {
 658                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 659
 660                         if (!vnic) {
 661                                 PMD_DRV_LOG(ERR,
 662                                             "Num pools more than FW profile\n");
 663                                 rc = -EINVAL;
 664                                 goto err_out;
 665                         }
 666                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 667                         bp->rx_cosq_cnt++;
 668                 }
 669         }
 670
 671 skip_cosq_cfg:
 672         rc = bnxt_mq_rx_configure(bp);
 673         if (rc) {
 674                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 675                 goto err_out;
 676         }
 677
 678         /* VNIC configuration */
 679         for (i = 0; i < bp->nr_vnics; i++) {
 680                 rc = bnxt_setup_one_vnic(bp, i);
 681                 if (rc)
 682                         goto err_out;
 683         }
 684
 685         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 686         if (rc) {
 687                 PMD_DRV_LOG(ERR,
 688                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 689                 goto err_out;
 690         }
 691
 692         /* check and configure queue intr-vector mapping */
 693         if ((rte_intr_cap_multiple(intr_handle) ||
 694              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 695             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 696                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 697                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 698                 if (intr_vector > bp->rx_cp_nr_rings) {
 699                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 700                                         bp->rx_cp_nr_rings);
 701                         return -ENOTSUP;
 702                 }
 703                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 704                 if (rc)
 705                         return rc;
 706         }
 707
 708         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 709                 intr_handle->intr_vec =
 710                         rte_zmalloc("intr_vec",
 711                                     bp->eth_dev->data->nb_rx_queues *
 712                                     sizeof(int), 0);
 713                 if (intr_handle->intr_vec == NULL) {
 714                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 715                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 716                         rc = -ENOMEM;
 717                         goto err_disable;
 718                 }
 719                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 720                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 721                          intr_handle->intr_vec, intr_handle->nb_efd,
 722                         intr_handle->max_intr);
 723                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 724                      queue_id++) {
 725                         intr_handle->intr_vec[queue_id] =
 726                                                         vec + BNXT_RX_VEC_START;
 727                         if (vec < base + intr_handle->nb_efd - 1)
 728                                 vec++;
 729                 }
 730         }
 731
 732         /* enable uio/vfio intr/eventfd mapping */
 733         rc = rte_intr_enable(intr_handle);
 734 #ifndef RTE_EXEC_ENV_FREEBSD
 735         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 736         if (rc)
 737                 goto err_free;
 738 #endif
 739
 740         rc = bnxt_get_hwrm_link_config(bp, &new);
 741         if (rc) {
 742                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 743                 goto err_free;
 744         }
 745
 746         if (!bp->link_info->link_up) {
 747                 rc = bnxt_set_hwrm_link_config(bp, true);
 748                 if (rc) {
 749                         PMD_DRV_LOG(ERR,
 750                                 "HWRM link config failure rc: %x\n", rc);
 751                         goto err_free;
 752                 }
 753         }
 754         bnxt_print_link_info(bp->eth_dev);
 755
 756         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 757         if (!bp->mark_table)
 758                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 759
 760         return 0;
 761
 762 err_free:
 763         rte_free(intr_handle->intr_vec);
 764 err_disable:
 765         rte_intr_efd_disable(intr_handle);
 766 err_out:
 767         /* Some of the error status returned by FW may not be from errno.h */
 768         if (rc > 0)
 769                 rc = -EIO;
 770
 771         return rc;
 772 }
 773
 774 static int bnxt_shutdown_nic(struct bnxt *bp)
 775 {
 776         bnxt_free_all_hwrm_resources(bp);
 777         bnxt_free_all_filters(bp);
 778         bnxt_free_all_vnics(bp);
 779         return 0;
 780 }
 781
 782 /*
 783  * Device configuration and status function
 784  */
 785
 786 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 787 {
 788         uint32_t link_speed = bp->link_info->support_speeds;
 789         uint32_t speed_capa = 0;
 790
 791         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 792                 speed_capa |= ETH_LINK_SPEED_100M;
 793         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 794                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 795         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 796                 speed_capa |= ETH_LINK_SPEED_1G;
 797         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 798                 speed_capa |= ETH_LINK_SPEED_2_5G;
 799         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 800                 speed_capa |= ETH_LINK_SPEED_10G;
 801         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 802                 speed_capa |= ETH_LINK_SPEED_20G;
 803         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 804                 speed_capa |= ETH_LINK_SPEED_25G;
 805         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 806                 speed_capa |= ETH_LINK_SPEED_40G;
 807         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 808                 speed_capa |= ETH_LINK_SPEED_50G;
 809         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 810                 speed_capa |= ETH_LINK_SPEED_100G;
 811         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
 812                 speed_capa |= ETH_LINK_SPEED_200G;
 813
 814         if (bp->link_info->auto_mode ==
 815             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 816                 speed_capa |= ETH_LINK_SPEED_FIXED;
 817         else
 818                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 819
 820         return speed_capa;
 821 }
 822
 823 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 824                                 struct rte_eth_dev_info *dev_info)
 825 {
 826         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 827         struct bnxt *bp = eth_dev->data->dev_private;
 828         uint16_t max_vnics, i, j, vpool, vrxq;
 829         unsigned int max_rx_rings;
 830         int rc;
 831
 832         rc = is_bnxt_in_error(bp);
 833         if (rc)
 834                 return rc;
 835
 836         /* MAC Specifics */
 837         dev_info->max_mac_addrs = bp->max_l2_ctx;
 838         dev_info->max_hash_mac_addrs = 0;
 839
 840         /* PF/VF specifics */
 841         if (BNXT_PF(bp))
 842                 dev_info->max_vfs = pdev->max_vfs;
 843
 844         max_rx_rings = BNXT_MAX_RINGS(bp);
 845         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 846         dev_info->max_rx_queues = max_rx_rings;
 847         dev_info->max_tx_queues = max_rx_rings;
 848         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 849         dev_info->hash_key_size = 40;
 850         max_vnics = bp->max_vnics;
 851
 852         /* MTU specifics */
 853         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 854         dev_info->max_mtu = BNXT_MAX_MTU;
 855
 856         /* Fast path specifics */
 857         dev_info->min_rx_bufsize = 1;
 858         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 859
 860         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 861         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 862                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 863         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 864         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 865
 866         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 867
 868         /* *INDENT-OFF* */
 869         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 870                 .rx_thresh = {
 871                         .pthresh = 8,
 872                         .hthresh = 8,
 873                         .wthresh = 0,
 874                 },
 875                 .rx_free_thresh = 32,
 876                 /* If no descriptors available, pkts are dropped by default */
 877                 .rx_drop_en = 1,
 878         };
 879
 880         dev_info->default_txconf = (struct rte_eth_txconf) {
 881                 .tx_thresh = {
 882                         .pthresh = 32,
 883                         .hthresh = 0,
 884                         .wthresh = 0,
 885                 },
 886                 .tx_free_thresh = 32,
 887                 .tx_rs_thresh = 32,
 888         };
 889         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 890
 891         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 892         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 893         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 894         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 895         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 896
 897         /* *INDENT-ON* */
 898
 899         /*
 900          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 901          *       need further investigation.
 902          */
 903
 904         /* VMDq resources */
 905         vpool = 64; /* ETH_64_POOLS */
 906         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 907         for (i = 0; i < 4; vpool >>= 1, i++) {
 908                 if (max_vnics > vpool) {
 909                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 910                                 if (dev_info->max_rx_queues > vrxq) {
 911                                         if (vpool > vrxq)
 912                                                 vpool = vrxq;
 913                                         goto found;
 914                                 }
 915                         }
 916                         /* Not enough resources to support VMDq */
 917                         break;
 918                 }
 919         }
 920         /* Not enough resources to support VMDq */
 921         vpool = 0;
 922         vrxq = 0;
 923 found:
 924         dev_info->max_vmdq_pools = vpool;
 925         dev_info->vmdq_queue_num = vrxq;
 926
 927         dev_info->vmdq_pool_base = 0;
 928         dev_info->vmdq_queue_base = 0;
 929
 930         return 0;
 931 }
 932
 933 /* Configure the device based on the configuration provided */
 934 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 935 {
 936         struct bnxt *bp = eth_dev->data->dev_private;
 937         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 938         int rc;
 939
 940         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 941         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 942         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 943         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 944
 945         rc = is_bnxt_in_error(bp);
 946         if (rc)
 947                 return rc;
 948
 949         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 950                 rc = bnxt_hwrm_check_vf_rings(bp);
 951                 if (rc) {
 952                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 953                         return -ENOSPC;
 954                 }
 955
 956                 /* If a resource has already been allocated - in this case
 957                  * it is the async completion ring, free it. Reallocate it after
 958                  * resource reservation. This will ensure the resource counts
 959                  * are calculated correctly.
 960                  */
 961
 962                 pthread_mutex_lock(&bp->def_cp_lock);
 963
 964                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 965                         bnxt_disable_int(bp);
 966                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 967                 }
 968
 969                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 970                 if (rc) {
 971                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 972                         pthread_mutex_unlock(&bp->def_cp_lock);
 973                         return -ENOSPC;
 974                 }
 975
 976                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 977                         rc = bnxt_alloc_async_cp_ring(bp);
 978                         if (rc) {
 979                                 pthread_mutex_unlock(&bp->def_cp_lock);
 980                                 return rc;
 981                         }
 982                         bnxt_enable_int(bp);
 983                 }
 984
 985                 pthread_mutex_unlock(&bp->def_cp_lock);
 986         } else {
 987                 /* legacy driver needs to get updated values */
 988                 rc = bnxt_hwrm_func_qcaps(bp);
 989                 if (rc) {
 990                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 991                         return rc;
 992                 }
 993         }
 994
 995         /* Inherit new configurations */
 996         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 997             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 998             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 999                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1000             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1001             bp->max_stat_ctx)
1002                 goto resource_error;
1003
1004         if (BNXT_HAS_RING_GRPS(bp) &&
1005             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1006                 goto resource_error;
1007
1008         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1009             bp->max_vnics < eth_dev->data->nb_rx_queues)
1010                 goto resource_error;
1011
1012         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1013         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1014
1015         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1016                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1017         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1018
1019         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1020                 eth_dev->data->mtu =
1021                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1022                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1023                         BNXT_NUM_VLANS;
1024                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1025         }
1026         return 0;
1027
1028 resource_error:
1029         PMD_DRV_LOG(ERR,
1030                     "Insufficient resources to support requested config\n");
1031         PMD_DRV_LOG(ERR,
1032                     "Num Queues Requested: Tx %d, Rx %d\n",
1033                     eth_dev->data->nb_tx_queues,
1034                     eth_dev->data->nb_rx_queues);
1035         PMD_DRV_LOG(ERR,
1036                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1037                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1038                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1039         return -ENOSPC;
1040 }
1041
1042 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1043 {
1044         struct rte_eth_link *link = &eth_dev->data->dev_link;
1045
1046         if (link->link_status)
1047                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1048                         eth_dev->data->port_id,
1049                         (uint32_t)link->link_speed,
1050                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1051                         ("full-duplex") : ("half-duplex\n"));
1052         else
1053                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1054                         eth_dev->data->port_id);
1055 }
1056
1057 /*
1058  * Determine whether the current configuration requires support for scattered
1059  * receive; return 1 if scattered receive is required and 0 if not.
1060  */
1061 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1062 {
1063         uint16_t buf_size;
1064         int i;
1065
1066         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1067                 return 1;
1068
1069         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1070                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1071
1072                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1073                                       RTE_PKTMBUF_HEADROOM);
1074                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1075                         return 1;
1076         }
1077         return 0;
1078 }
1079
1080 static eth_rx_burst_t
1081 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1082 {
1083         struct bnxt *bp = eth_dev->data->dev_private;
1084
1085 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1086 #ifndef RTE_LIBRTE_IEEE1588
1087         /*
1088          * Vector mode receive can be enabled only if scatter rx is not
1089          * in use and rx offloads are limited to VLAN stripping and
1090          * CRC stripping.
1091          */
1092         if (!eth_dev->data->scattered_rx &&
1093             !(eth_dev->data->dev_conf.rxmode.offloads &
1094               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1095                 DEV_RX_OFFLOAD_KEEP_CRC |
1096                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1097                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1098                 DEV_RX_OFFLOAD_UDP_CKSUM |
1099                 DEV_RX_OFFLOAD_TCP_CKSUM |
1100                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1101                 DEV_RX_OFFLOAD_RSS_HASH |
1102                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1103             !BNXT_TRUFLOW_EN(bp)) {
1104                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1105                             eth_dev->data->port_id);
1106                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1107                 return bnxt_recv_pkts_vec;
1108         }
1109         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1110                     eth_dev->data->port_id);
1111         PMD_DRV_LOG(INFO,
1112                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1113                     eth_dev->data->port_id,
1114                     eth_dev->data->scattered_rx,
1115                     eth_dev->data->dev_conf.rxmode.offloads);
1116 #endif
1117 #endif
1118         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1119         return bnxt_recv_pkts;
1120 }
1121
1122 static eth_tx_burst_t
1123 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1124 {
1125 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1126 #ifndef RTE_LIBRTE_IEEE1588
1127         struct bnxt *bp = eth_dev->data->dev_private;
1128
1129         /*
1130          * Vector mode transmit can be enabled only if not using scatter rx
1131          * or tx offloads.
1132          */
1133         if (!eth_dev->data->scattered_rx &&
1134             !eth_dev->data->dev_conf.txmode.offloads &&
1135             !BNXT_TRUFLOW_EN(bp)) {
1136                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1137                             eth_dev->data->port_id);
1138                 return bnxt_xmit_pkts_vec;
1139         }
1140         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1141                     eth_dev->data->port_id);
1142         PMD_DRV_LOG(INFO,
1143                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1144                     eth_dev->data->port_id,
1145                     eth_dev->data->scattered_rx,
1146                     eth_dev->data->dev_conf.txmode.offloads);
1147 #endif
1148 #endif
1149         return bnxt_xmit_pkts;
1150 }
1151
1152 static int bnxt_handle_if_change_status(struct bnxt *bp)
1153 {
1154         int rc;
1155
1156         /* Since fw has undergone a reset and lost all contexts,
1157          * set fatal flag to not issue hwrm during cleanup
1158          */
1159         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1160         bnxt_uninit_resources(bp, true);
1161
1162         /* clear fatal flag so that re-init happens */
1163         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1164         rc = bnxt_init_resources(bp, true);
1165
1166         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1167
1168         return rc;
1169 }
1170
1171 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1172 {
1173         struct bnxt *bp = eth_dev->data->dev_private;
1174         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1175         int vlan_mask = 0;
1176         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1177
1178         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1179                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1180                 return -EINVAL;
1181         }
1182
1183         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1184                 PMD_DRV_LOG(ERR,
1185                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1186                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1187         }
1188
1189         do {
1190                 rc = bnxt_hwrm_if_change(bp, true);
1191                 if (rc == 0 || rc != -EAGAIN)
1192                         break;
1193
1194                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1195         } while (retry_cnt--);
1196
1197         if (rc)
1198                 return rc;
1199
1200         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1201                 rc = bnxt_handle_if_change_status(bp);
1202                 if (rc)
1203                         return rc;
1204         }
1205
1206         bnxt_enable_int(bp);
1207
1208         rc = bnxt_init_chip(bp);
1209         if (rc)
1210                 goto error;
1211
1212         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1213         eth_dev->data->dev_started = 1;
1214
1215         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1216
1217         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1218                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1219         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1220                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1221         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1222         if (rc)
1223                 goto error;
1224
1225         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1226         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1227
1228         pthread_mutex_lock(&bp->def_cp_lock);
1229         bnxt_schedule_fw_health_check(bp);
1230         pthread_mutex_unlock(&bp->def_cp_lock);
1231
1232         bnxt_ulp_init(bp);
1233
1234         return 0;
1235
1236 error:
1237         bnxt_shutdown_nic(bp);
1238         bnxt_free_tx_mbufs(bp);
1239         bnxt_free_rx_mbufs(bp);
1240         bnxt_hwrm_if_change(bp, false);
1241         eth_dev->data->dev_started = 0;
1242         return rc;
1243 }
1244
1245 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1246 {
1247         struct bnxt *bp = eth_dev->data->dev_private;
1248         int rc = 0;
1249
1250         if (!bp->link_info->link_up)
1251                 rc = bnxt_set_hwrm_link_config(bp, true);
1252         if (!rc)
1253                 eth_dev->data->dev_link.link_status = 1;
1254
1255         bnxt_print_link_info(eth_dev);
1256         return rc;
1257 }
1258
1259 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1260 {
1261         struct bnxt *bp = eth_dev->data->dev_private;
1262
1263         eth_dev->data->dev_link.link_status = 0;
1264         bnxt_set_hwrm_link_config(bp, false);
1265         bp->link_info->link_up = 0;
1266
1267         return 0;
1268 }
1269
1270 static void bnxt_free_switch_domain(struct bnxt *bp)
1271 {
1272         if (bp->switch_domain_id)
1273                 rte_eth_switch_domain_free(bp->switch_domain_id);
1274 }
1275
1276 /* Unload the driver, release resources */
1277 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1278 {
1279         struct bnxt *bp = eth_dev->data->dev_private;
1280         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1281         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1282
1283         eth_dev->data->dev_started = 0;
1284         /* Prevent crashes when queues are still in use */
1285         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1286         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1287
1288         bnxt_disable_int(bp);
1289
1290         /* disable uio/vfio intr/eventfd mapping */
1291         rte_intr_disable(intr_handle);
1292
1293         bnxt_ulp_destroy_df_rules(bp, false);
1294         bnxt_ulp_deinit(bp);
1295
1296         bnxt_cancel_fw_health_check(bp);
1297
1298         bnxt_dev_set_link_down_op(eth_dev);
1299
1300         /* Wait for link to be reset and the async notification to process.
1301          * During reset recovery, there is no need to wait and
1302          * VF/NPAR functions do not have privilege to change PHY config.
1303          */
1304         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1305                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1306
1307         /* Clean queue intr-vector mapping */
1308         rte_intr_efd_disable(intr_handle);
1309         if (intr_handle->intr_vec != NULL) {
1310                 rte_free(intr_handle->intr_vec);
1311                 intr_handle->intr_vec = NULL;
1312         }
1313
1314         bnxt_hwrm_port_clr_stats(bp);
1315         bnxt_free_tx_mbufs(bp);
1316         bnxt_free_rx_mbufs(bp);
1317         /* Process any remaining notifications in default completion queue */
1318         bnxt_int_handler(eth_dev);
1319         bnxt_shutdown_nic(bp);
1320         bnxt_hwrm_if_change(bp, false);
1321
1322         rte_free(bp->mark_table);
1323         bp->mark_table = NULL;
1324
1325         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1326         bp->rx_cosq_cnt = 0;
1327         /* All filters are deleted on a port stop. */
1328         if (BNXT_FLOW_XSTATS_EN(bp))
1329                 bp->flow_stat->flow_count = 0;
1330 }
1331
1332 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1333 {
1334         struct bnxt *bp = eth_dev->data->dev_private;
1335
1336         /* cancel the recovery handler before remove dev */
1337         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1338         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1339         bnxt_cancel_fc_thread(bp);
1340
1341         if (eth_dev->data->dev_started)
1342                 bnxt_dev_stop_op(eth_dev);
1343
1344         bnxt_free_switch_domain(bp);
1345
1346         bnxt_uninit_resources(bp, false);
1347
1348         bnxt_free_leds_info(bp);
1349         bnxt_free_cos_queues(bp);
1350         bnxt_free_link_info(bp);
1351         bnxt_free_pf_info(bp);
1352         bnxt_free_parent_info(bp);
1353
1354         eth_dev->dev_ops = NULL;
1355         eth_dev->rx_pkt_burst = NULL;
1356         eth_dev->tx_pkt_burst = NULL;
1357
1358         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1359         bp->tx_mem_zone = NULL;
1360         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1361         bp->rx_mem_zone = NULL;
1362
1363         rte_free(bp->pf->vf_info);
1364         bp->pf->vf_info = NULL;
1365
1366         rte_free(bp->grp_info);
1367         bp->grp_info = NULL;
1368 }
1369
1370 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1371                                     uint32_t index)
1372 {
1373         struct bnxt *bp = eth_dev->data->dev_private;
1374         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1375         struct bnxt_vnic_info *vnic;
1376         struct bnxt_filter_info *filter, *temp_filter;
1377         uint32_t i;
1378
1379         if (is_bnxt_in_error(bp))
1380                 return;
1381
1382         /*
1383          * Loop through all VNICs from the specified filter flow pools to
1384          * remove the corresponding MAC addr filter
1385          */
1386         for (i = 0; i < bp->nr_vnics; i++) {
1387                 if (!(pool_mask & (1ULL << i)))
1388                         continue;
1389
1390                 vnic = &bp->vnic_info[i];
1391                 filter = STAILQ_FIRST(&vnic->filter);
1392                 while (filter) {
1393                         temp_filter = STAILQ_NEXT(filter, next);
1394                         if (filter->mac_index == index) {
1395                                 STAILQ_REMOVE(&vnic->filter, filter,
1396                                                 bnxt_filter_info, next);
1397                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1398                                 bnxt_free_filter(bp, filter);
1399                         }
1400                         filter = temp_filter;
1401                 }
1402         }
1403 }
1404
1405 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1406                                struct rte_ether_addr *mac_addr, uint32_t index,
1407                                uint32_t pool)
1408 {
1409         struct bnxt_filter_info *filter;
1410         int rc = 0;
1411
1412         /* Attach requested MAC address to the new l2_filter */
1413         STAILQ_FOREACH(filter, &vnic->filter, next) {
1414                 if (filter->mac_index == index) {
1415                         PMD_DRV_LOG(DEBUG,
1416                                     "MAC addr already existed for pool %d\n",
1417                                     pool);
1418                         return 0;
1419                 }
1420         }
1421
1422         filter = bnxt_alloc_filter(bp);
1423         if (!filter) {
1424                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1425                 return -ENODEV;
1426         }
1427
1428         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1429          * if the MAC that's been programmed now is a different one, then,
1430          * copy that addr to filter->l2_addr
1431          */
1432         if (mac_addr)
1433                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1434         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1435
1436         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1437         if (!rc) {
1438                 filter->mac_index = index;
1439                 if (filter->mac_index == 0)
1440                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1441                 else
1442                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1443         } else {
1444                 bnxt_free_filter(bp, filter);
1445         }
1446
1447         return rc;
1448 }
1449
1450 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1451                                 struct rte_ether_addr *mac_addr,
1452                                 uint32_t index, uint32_t pool)
1453 {
1454         struct bnxt *bp = eth_dev->data->dev_private;
1455         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1456         int rc = 0;
1457
1458         rc = is_bnxt_in_error(bp);
1459         if (rc)
1460                 return rc;
1461
1462         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1463                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1464                 return -ENOTSUP;
1465         }
1466
1467         if (!vnic) {
1468                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1469                 return -EINVAL;
1470         }
1471
1472         /* Filter settings will get applied when port is started */
1473         if (!eth_dev->data->dev_started)
1474                 return 0;
1475
1476         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1477
1478         return rc;
1479 }
1480
1481 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1482                      bool exp_link_status)
1483 {
1484         int rc = 0;
1485         struct bnxt *bp = eth_dev->data->dev_private;
1486         struct rte_eth_link new;
1487         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1488                   BNXT_LINK_DOWN_WAIT_CNT;
1489
1490         rc = is_bnxt_in_error(bp);
1491         if (rc)
1492                 return rc;
1493
1494         memset(&new, 0, sizeof(new));
1495         do {
1496                 /* Retrieve link info from hardware */
1497                 rc = bnxt_get_hwrm_link_config(bp, &new);
1498                 if (rc) {
1499                         new.link_speed = ETH_LINK_SPEED_100M;
1500                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1501                         PMD_DRV_LOG(ERR,
1502                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1503                         goto out;
1504                 }
1505
1506                 if (!wait_to_complete || new.link_status == exp_link_status)
1507                         break;
1508
1509                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1510         } while (cnt--);
1511
1512 out:
1513         /* Timed out or success */
1514         if (new.link_status != eth_dev->data->dev_link.link_status ||
1515         new.link_speed != eth_dev->data->dev_link.link_speed) {
1516                 rte_eth_linkstatus_set(eth_dev, &new);
1517
1518                 _rte_eth_dev_callback_process(eth_dev,
1519                                               RTE_ETH_EVENT_INTR_LSC,
1520                                               NULL);
1521
1522                 bnxt_print_link_info(eth_dev);
1523         }
1524
1525         return rc;
1526 }
1527
1528 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1529                         int wait_to_complete)
1530 {
1531         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1532 }
1533
1534 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1535 {
1536         struct bnxt *bp = eth_dev->data->dev_private;
1537         struct bnxt_vnic_info *vnic;
1538         uint32_t old_flags;
1539         int rc;
1540
1541         rc = is_bnxt_in_error(bp);
1542         if (rc)
1543                 return rc;
1544
1545         /* Filter settings will get applied when port is started */
1546         if (!eth_dev->data->dev_started)
1547                 return 0;
1548
1549         if (bp->vnic_info == NULL)
1550                 return 0;
1551
1552         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1553
1554         old_flags = vnic->flags;
1555         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1556         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1557         if (rc != 0)
1558                 vnic->flags = old_flags;
1559
1560         return rc;
1561 }
1562
1563 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1564 {
1565         struct bnxt *bp = eth_dev->data->dev_private;
1566         struct bnxt_vnic_info *vnic;
1567         uint32_t old_flags;
1568         int rc;
1569
1570         rc = is_bnxt_in_error(bp);
1571         if (rc)
1572                 return rc;
1573
1574         /* Filter settings will get applied when port is started */
1575         if (!eth_dev->data->dev_started)
1576                 return 0;
1577
1578         if (bp->vnic_info == NULL)
1579                 return 0;
1580
1581         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1582
1583         old_flags = vnic->flags;
1584         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1585         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1586         if (rc != 0)
1587                 vnic->flags = old_flags;
1588
1589         bnxt_ulp_create_df_rules(bp);
1590
1591         return rc;
1592 }
1593
1594 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1595 {
1596         struct bnxt *bp = eth_dev->data->dev_private;
1597         struct bnxt_vnic_info *vnic;
1598         uint32_t old_flags;
1599         int rc;
1600
1601         rc = is_bnxt_in_error(bp);
1602         if (rc)
1603                 return rc;
1604
1605         /* Filter settings will get applied when port is started */
1606         if (!eth_dev->data->dev_started)
1607                 return 0;
1608
1609         if (bp->vnic_info == NULL)
1610                 return 0;
1611
1612         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1613
1614         old_flags = vnic->flags;
1615         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1616         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1617         if (rc != 0)
1618                 vnic->flags = old_flags;
1619
1620         return rc;
1621 }
1622
1623 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1624 {
1625         struct bnxt *bp = eth_dev->data->dev_private;
1626         struct bnxt_vnic_info *vnic;
1627         uint32_t old_flags;
1628         int rc;
1629
1630         rc = is_bnxt_in_error(bp);
1631         if (rc)
1632                 return rc;
1633
1634         /* Filter settings will get applied when port is started */
1635         if (!eth_dev->data->dev_started)
1636                 return 0;
1637
1638         if (bp->vnic_info == NULL)
1639                 return 0;
1640
1641         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1642
1643         old_flags = vnic->flags;
1644         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1645         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1646         if (rc != 0)
1647                 vnic->flags = old_flags;
1648
1649         return rc;
1650 }
1651
1652 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1653 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1654 {
1655         if (qid >= bp->rx_nr_rings)
1656                 return NULL;
1657
1658         return bp->eth_dev->data->rx_queues[qid];
1659 }
1660
1661 /* Return rxq corresponding to a given rss table ring/group ID. */
1662 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1663 {
1664         struct bnxt_rx_queue *rxq;
1665         unsigned int i;
1666
1667         if (!BNXT_HAS_RING_GRPS(bp)) {
1668                 for (i = 0; i < bp->rx_nr_rings; i++) {
1669                         rxq = bp->eth_dev->data->rx_queues[i];
1670                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1671                                 return rxq->index;
1672                 }
1673         } else {
1674                 for (i = 0; i < bp->rx_nr_rings; i++) {
1675                         if (bp->grp_info[i].fw_grp_id == fwr)
1676                                 return i;
1677                 }
1678         }
1679
1680         return INVALID_HW_RING_ID;
1681 }
1682
1683 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1684                             struct rte_eth_rss_reta_entry64 *reta_conf,
1685                             uint16_t reta_size)
1686 {
1687         struct bnxt *bp = eth_dev->data->dev_private;
1688         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1689         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1690         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1691         uint16_t idx, sft;
1692         int i, rc;
1693
1694         rc = is_bnxt_in_error(bp);
1695         if (rc)
1696                 return rc;
1697
1698         if (!vnic->rss_table)
1699                 return -EINVAL;
1700
1701         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1702                 return -EINVAL;
1703
1704         if (reta_size != tbl_size) {
1705                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1706                         "(%d) must equal the size supported by the hardware "
1707                         "(%d)\n", reta_size, tbl_size);
1708                 return -EINVAL;
1709         }
1710
1711         for (i = 0; i < reta_size; i++) {
1712                 struct bnxt_rx_queue *rxq;
1713
1714                 idx = i / RTE_RETA_GROUP_SIZE;
1715                 sft = i % RTE_RETA_GROUP_SIZE;
1716
1717                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1718                         continue;
1719
1720                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1721                 if (!rxq) {
1722                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1723                         return -EINVAL;
1724                 }
1725
1726                 if (BNXT_CHIP_THOR(bp)) {
1727                         vnic->rss_table[i * 2] =
1728                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1729                         vnic->rss_table[i * 2 + 1] =
1730                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1731                 } else {
1732                         vnic->rss_table[i] =
1733                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1734                 }
1735         }
1736
1737         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1738         return 0;
1739 }
1740
1741 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1742                               struct rte_eth_rss_reta_entry64 *reta_conf,
1743                               uint16_t reta_size)
1744 {
1745         struct bnxt *bp = eth_dev->data->dev_private;
1746         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1747         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1748         uint16_t idx, sft, i;
1749         int rc;
1750
1751         rc = is_bnxt_in_error(bp);
1752         if (rc)
1753                 return rc;
1754
1755         /* Retrieve from the default VNIC */
1756         if (!vnic)
1757                 return -EINVAL;
1758         if (!vnic->rss_table)
1759                 return -EINVAL;
1760
1761         if (reta_size != tbl_size) {
1762                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1763                         "(%d) must equal the size supported by the hardware "
1764                         "(%d)\n", reta_size, tbl_size);
1765                 return -EINVAL;
1766         }
1767
1768         for (idx = 0, i = 0; i < reta_size; i++) {
1769                 idx = i / RTE_RETA_GROUP_SIZE;
1770                 sft = i % RTE_RETA_GROUP_SIZE;
1771
1772                 if (reta_conf[idx].mask & (1ULL << sft)) {
1773                         uint16_t qid;
1774
1775                         if (BNXT_CHIP_THOR(bp))
1776                                 qid = bnxt_rss_to_qid(bp,
1777                                                       vnic->rss_table[i * 2]);
1778                         else
1779                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1780
1781                         if (qid == INVALID_HW_RING_ID) {
1782                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1783                                 return -EINVAL;
1784                         }
1785                         reta_conf[idx].reta[sft] = qid;
1786                 }
1787         }
1788
1789         return 0;
1790 }
1791
1792 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1793                                    struct rte_eth_rss_conf *rss_conf)
1794 {
1795         struct bnxt *bp = eth_dev->data->dev_private;
1796         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1797         struct bnxt_vnic_info *vnic;
1798         int rc;
1799
1800         rc = is_bnxt_in_error(bp);
1801         if (rc)
1802                 return rc;
1803
1804         /*
1805          * If RSS enablement were different than dev_configure,
1806          * then return -EINVAL
1807          */
1808         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1809                 if (!rss_conf->rss_hf)
1810                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1811         } else {
1812                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1813                         return -EINVAL;
1814         }
1815
1816         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1817         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1818                rss_conf,
1819                sizeof(*rss_conf));
1820
1821         /* Update the default RSS VNIC(s) */
1822         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1823         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1824
1825         /*
1826          * If hashkey is not specified, use the previously configured
1827          * hashkey
1828          */
1829         if (!rss_conf->rss_key)
1830                 goto rss_config;
1831
1832         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1833                 PMD_DRV_LOG(ERR,
1834                             "Invalid hashkey length, should be 16 bytes\n");
1835                 return -EINVAL;
1836         }
1837         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1838
1839 rss_config:
1840         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1841         return 0;
1842 }
1843
1844 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1845                                      struct rte_eth_rss_conf *rss_conf)
1846 {
1847         struct bnxt *bp = eth_dev->data->dev_private;
1848         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1849         int len, rc;
1850         uint32_t hash_types;
1851
1852         rc = is_bnxt_in_error(bp);
1853         if (rc)
1854                 return rc;
1855
1856         /* RSS configuration is the same for all VNICs */
1857         if (vnic && vnic->rss_hash_key) {
1858                 if (rss_conf->rss_key) {
1859                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1860                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1861                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1862                 }
1863
1864                 hash_types = vnic->hash_type;
1865                 rss_conf->rss_hf = 0;
1866                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1867                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1868                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1869                 }
1870                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1871                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1872                         hash_types &=
1873                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1874                 }
1875                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1876                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1877                         hash_types &=
1878                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1879                 }
1880                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1881                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1882                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1883                 }
1884                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1885                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1886                         hash_types &=
1887                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1888                 }
1889                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1890                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1891                         hash_types &=
1892                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1893                 }
1894                 if (hash_types) {
1895                         PMD_DRV_LOG(ERR,
1896                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1897                                 vnic->hash_type);
1898                         return -ENOTSUP;
1899                 }
1900         } else {
1901                 rss_conf->rss_hf = 0;
1902         }
1903         return 0;
1904 }
1905
1906 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1907                                struct rte_eth_fc_conf *fc_conf)
1908 {
1909         struct bnxt *bp = dev->data->dev_private;
1910         struct rte_eth_link link_info;
1911         int rc;
1912
1913         rc = is_bnxt_in_error(bp);
1914         if (rc)
1915                 return rc;
1916
1917         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1918         if (rc)
1919                 return rc;
1920
1921         memset(fc_conf, 0, sizeof(*fc_conf));
1922         if (bp->link_info->auto_pause)
1923                 fc_conf->autoneg = 1;
1924         switch (bp->link_info->pause) {
1925         case 0:
1926                 fc_conf->mode = RTE_FC_NONE;
1927                 break;
1928         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1929                 fc_conf->mode = RTE_FC_TX_PAUSE;
1930                 break;
1931         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1932                 fc_conf->mode = RTE_FC_RX_PAUSE;
1933                 break;
1934         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1935                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1936                 fc_conf->mode = RTE_FC_FULL;
1937                 break;
1938         }
1939         return 0;
1940 }
1941
1942 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1943                                struct rte_eth_fc_conf *fc_conf)
1944 {
1945         struct bnxt *bp = dev->data->dev_private;
1946         int rc;
1947
1948         rc = is_bnxt_in_error(bp);
1949         if (rc)
1950                 return rc;
1951
1952         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1953                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1954                 return -ENOTSUP;
1955         }
1956
1957         switch (fc_conf->mode) {
1958         case RTE_FC_NONE:
1959                 bp->link_info->auto_pause = 0;
1960                 bp->link_info->force_pause = 0;
1961                 break;
1962         case RTE_FC_RX_PAUSE:
1963                 if (fc_conf->autoneg) {
1964                         bp->link_info->auto_pause =
1965                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1966                         bp->link_info->force_pause = 0;
1967                 } else {
1968                         bp->link_info->auto_pause = 0;
1969                         bp->link_info->force_pause =
1970                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1971                 }
1972                 break;
1973         case RTE_FC_TX_PAUSE:
1974                 if (fc_conf->autoneg) {
1975                         bp->link_info->auto_pause =
1976                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1977                         bp->link_info->force_pause = 0;
1978                 } else {
1979                         bp->link_info->auto_pause = 0;
1980                         bp->link_info->force_pause =
1981                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1982                 }
1983                 break;
1984         case RTE_FC_FULL:
1985                 if (fc_conf->autoneg) {
1986                         bp->link_info->auto_pause =
1987                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1988                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1989                         bp->link_info->force_pause = 0;
1990                 } else {
1991                         bp->link_info->auto_pause = 0;
1992                         bp->link_info->force_pause =
1993                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1994                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1995                 }
1996                 break;
1997         }
1998         return bnxt_set_hwrm_link_config(bp, true);
1999 }
2000
2001 /* Add UDP tunneling port */
2002 static int
2003 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2004                          struct rte_eth_udp_tunnel *udp_tunnel)
2005 {
2006         struct bnxt *bp = eth_dev->data->dev_private;
2007         uint16_t tunnel_type = 0;
2008         int rc = 0;
2009
2010         rc = is_bnxt_in_error(bp);
2011         if (rc)
2012                 return rc;
2013
2014         switch (udp_tunnel->prot_type) {
2015         case RTE_TUNNEL_TYPE_VXLAN:
2016                 if (bp->vxlan_port_cnt) {
2017                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2018                                 udp_tunnel->udp_port);
2019                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2020                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2021                                 return -ENOSPC;
2022                         }
2023                         bp->vxlan_port_cnt++;
2024                         return 0;
2025                 }
2026                 tunnel_type =
2027                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2028                 bp->vxlan_port_cnt++;
2029                 break;
2030         case RTE_TUNNEL_TYPE_GENEVE:
2031                 if (bp->geneve_port_cnt) {
2032                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2033                                 udp_tunnel->udp_port);
2034                         if (bp->geneve_port != udp_tunnel->udp_port) {
2035                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2036                                 return -ENOSPC;
2037                         }
2038                         bp->geneve_port_cnt++;
2039                         return 0;
2040                 }
2041                 tunnel_type =
2042                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2043                 bp->geneve_port_cnt++;
2044                 break;
2045         default:
2046                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2047                 return -ENOTSUP;
2048         }
2049         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2050                                              tunnel_type);
2051         return rc;
2052 }
2053
2054 static int
2055 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2056                          struct rte_eth_udp_tunnel *udp_tunnel)
2057 {
2058         struct bnxt *bp = eth_dev->data->dev_private;
2059         uint16_t tunnel_type = 0;
2060         uint16_t port = 0;
2061         int rc = 0;
2062
2063         rc = is_bnxt_in_error(bp);
2064         if (rc)
2065                 return rc;
2066
2067         switch (udp_tunnel->prot_type) {
2068         case RTE_TUNNEL_TYPE_VXLAN:
2069                 if (!bp->vxlan_port_cnt) {
2070                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2071                         return -EINVAL;
2072                 }
2073                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2074                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2075                                 udp_tunnel->udp_port, bp->vxlan_port);
2076                         return -EINVAL;
2077                 }
2078                 if (--bp->vxlan_port_cnt)
2079                         return 0;
2080
2081                 tunnel_type =
2082                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2083                 port = bp->vxlan_fw_dst_port_id;
2084                 break;
2085         case RTE_TUNNEL_TYPE_GENEVE:
2086                 if (!bp->geneve_port_cnt) {
2087                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2088                         return -EINVAL;
2089                 }
2090                 if (bp->geneve_port != udp_tunnel->udp_port) {
2091                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2092                                 udp_tunnel->udp_port, bp->geneve_port);
2093                         return -EINVAL;
2094                 }
2095                 if (--bp->geneve_port_cnt)
2096                         return 0;
2097
2098                 tunnel_type =
2099                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2100                 port = bp->geneve_fw_dst_port_id;
2101                 break;
2102         default:
2103                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2104                 return -ENOTSUP;
2105         }
2106
2107         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2108         if (!rc) {
2109                 if (tunnel_type ==
2110                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2111                         bp->vxlan_port = 0;
2112                 if (tunnel_type ==
2113                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2114                         bp->geneve_port = 0;
2115         }
2116         return rc;
2117 }
2118
2119 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2120 {
2121         struct bnxt_filter_info *filter;
2122         struct bnxt_vnic_info *vnic;
2123         int rc = 0;
2124         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2125
2126         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2127         filter = STAILQ_FIRST(&vnic->filter);
2128         while (filter) {
2129                 /* Search for this matching MAC+VLAN filter */
2130                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2131                         /* Delete the filter */
2132                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2133                         if (rc)
2134                                 return rc;
2135                         STAILQ_REMOVE(&vnic->filter, filter,
2136                                       bnxt_filter_info, next);
2137                         bnxt_free_filter(bp, filter);
2138                         PMD_DRV_LOG(INFO,
2139                                     "Deleted vlan filter for %d\n",
2140                                     vlan_id);
2141                         return 0;
2142                 }
2143                 filter = STAILQ_NEXT(filter, next);
2144         }
2145         return -ENOENT;
2146 }
2147
2148 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2149 {
2150         struct bnxt_filter_info *filter;
2151         struct bnxt_vnic_info *vnic;
2152         int rc = 0;
2153         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2154                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2155         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2156
2157         /* Implementation notes on the use of VNIC in this command:
2158          *
2159          * By default, these filters belong to default vnic for the function.
2160          * Once these filters are set up, only destination VNIC can be modified.
2161          * If the destination VNIC is not specified in this command,
2162          * then the HWRM shall only create an l2 context id.
2163          */
2164
2165         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2166         filter = STAILQ_FIRST(&vnic->filter);
2167         /* Check if the VLAN has already been added */
2168         while (filter) {
2169                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2170                         return -EEXIST;
2171
2172                 filter = STAILQ_NEXT(filter, next);
2173         }
2174
2175         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2176          * command to create MAC+VLAN filter with the right flags, enables set.
2177          */
2178         filter = bnxt_alloc_filter(bp);
2179         if (!filter) {
2180                 PMD_DRV_LOG(ERR,
2181                             "MAC/VLAN filter alloc failed\n");
2182                 return -ENOMEM;
2183         }
2184         /* MAC + VLAN ID filter */
2185         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2186          * untagged packets are received
2187          *
2188          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2189          * packets and only the programmed vlan's packets are received
2190          */
2191         filter->l2_ivlan = vlan_id;
2192         filter->l2_ivlan_mask = 0x0FFF;
2193         filter->enables |= en;
2194         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2195
2196         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2197         if (rc) {
2198                 /* Free the newly allocated filter as we were
2199                  * not able to create the filter in hardware.
2200                  */
2201                 bnxt_free_filter(bp, filter);
2202                 return rc;
2203         }
2204
2205         filter->mac_index = 0;
2206         /* Add this new filter to the list */
2207         if (vlan_id == 0)
2208                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2209         else
2210                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2211
2212         PMD_DRV_LOG(INFO,
2213                     "Added Vlan filter for %d\n", vlan_id);
2214         return rc;
2215 }
2216
2217 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2218                 uint16_t vlan_id, int on)
2219 {
2220         struct bnxt *bp = eth_dev->data->dev_private;
2221         int rc;
2222
2223         rc = is_bnxt_in_error(bp);
2224         if (rc)
2225                 return rc;
2226
2227         if (!eth_dev->data->dev_started) {
2228                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2229                 return -EINVAL;
2230         }
2231
2232         /* These operations apply to ALL existing MAC/VLAN filters */
2233         if (on)
2234                 return bnxt_add_vlan_filter(bp, vlan_id);
2235         else
2236                 return bnxt_del_vlan_filter(bp, vlan_id);
2237 }
2238
2239 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2240                                     struct bnxt_vnic_info *vnic)
2241 {
2242         struct bnxt_filter_info *filter;
2243         int rc;
2244
2245         filter = STAILQ_FIRST(&vnic->filter);
2246         while (filter) {
2247                 if (filter->mac_index == 0 &&
2248                     !memcmp(filter->l2_addr, bp->mac_addr,
2249                             RTE_ETHER_ADDR_LEN)) {
2250                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2251                         if (!rc) {
2252                                 STAILQ_REMOVE(&vnic->filter, filter,
2253                                               bnxt_filter_info, next);
2254                                 bnxt_free_filter(bp, filter);
2255                         }
2256                         return rc;
2257                 }
2258                 filter = STAILQ_NEXT(filter, next);
2259         }
2260         return 0;
2261 }
2262
2263 static int
2264 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2265 {
2266         struct bnxt_vnic_info *vnic;
2267         unsigned int i;
2268         int rc;
2269
2270         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2271         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2272                 /* Remove any VLAN filters programmed */
2273                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2274                         bnxt_del_vlan_filter(bp, i);
2275
2276                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2277                 if (rc)
2278                         return rc;
2279         } else {
2280                 /* Default filter will allow packets that match the
2281                  * dest mac. So, it has to be deleted, otherwise, we
2282                  * will endup receiving vlan packets for which the
2283                  * filter is not programmed, when hw-vlan-filter
2284                  * configuration is ON
2285                  */
2286                 bnxt_del_dflt_mac_filter(bp, vnic);
2287                 /* This filter will allow only untagged packets */
2288                 bnxt_add_vlan_filter(bp, 0);
2289         }
2290         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2291                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2292
2293         return 0;
2294 }
2295
2296 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2297 {
2298         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2299         unsigned int i;
2300         int rc;
2301
2302         /* Destroy vnic filters and vnic */
2303         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2304             DEV_RX_OFFLOAD_VLAN_FILTER) {
2305                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2306                         bnxt_del_vlan_filter(bp, i);
2307         }
2308         bnxt_del_dflt_mac_filter(bp, vnic);
2309
2310         rc = bnxt_hwrm_vnic_free(bp, vnic);
2311         if (rc)
2312                 return rc;
2313
2314         rte_free(vnic->fw_grp_ids);
2315         vnic->fw_grp_ids = NULL;
2316
2317         vnic->rx_queue_cnt = 0;
2318
2319         return 0;
2320 }
2321
2322 static int
2323 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2324 {
2325         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2326         int rc;
2327
2328         /* Destroy, recreate and reconfigure the default vnic */
2329         rc = bnxt_free_one_vnic(bp, 0);
2330         if (rc)
2331                 return rc;
2332
2333         /* default vnic 0 */
2334         rc = bnxt_setup_one_vnic(bp, 0);
2335         if (rc)
2336                 return rc;
2337
2338         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2339             DEV_RX_OFFLOAD_VLAN_FILTER) {
2340                 rc = bnxt_add_vlan_filter(bp, 0);
2341                 if (rc)
2342                         return rc;
2343                 rc = bnxt_restore_vlan_filters(bp);
2344                 if (rc)
2345                         return rc;
2346         } else {
2347                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2348                 if (rc)
2349                         return rc;
2350         }
2351
2352         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2353         if (rc)
2354                 return rc;
2355
2356         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2357                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2358
2359         return rc;
2360 }
2361
2362 static int
2363 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2364 {
2365         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2366         struct bnxt *bp = dev->data->dev_private;
2367         int rc;
2368
2369         rc = is_bnxt_in_error(bp);
2370         if (rc)
2371                 return rc;
2372
2373         /* Filter settings will get applied when port is started */
2374         if (!dev->data->dev_started)
2375                 return 0;
2376
2377         if (mask & ETH_VLAN_FILTER_MASK) {
2378                 /* Enable or disable VLAN filtering */
2379                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2380                 if (rc)
2381                         return rc;
2382         }
2383
2384         if (mask & ETH_VLAN_STRIP_MASK) {
2385                 /* Enable or disable VLAN stripping */
2386                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2387                 if (rc)
2388                         return rc;
2389         }
2390
2391         if (mask & ETH_VLAN_EXTEND_MASK) {
2392                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2393                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2394                 else
2395                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2396         }
2397
2398         return 0;
2399 }
2400
2401 static int
2402 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2403                       uint16_t tpid)
2404 {
2405         struct bnxt *bp = dev->data->dev_private;
2406         int qinq = dev->data->dev_conf.rxmode.offloads &
2407                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2408
2409         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2410             vlan_type != ETH_VLAN_TYPE_OUTER) {
2411                 PMD_DRV_LOG(ERR,
2412                             "Unsupported vlan type.");
2413                 return -EINVAL;
2414         }
2415         if (!qinq) {
2416                 PMD_DRV_LOG(ERR,
2417                             "QinQ not enabled. Needs to be ON as we can "
2418                             "accelerate only outer vlan\n");
2419                 return -EINVAL;
2420         }
2421
2422         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2423                 switch (tpid) {
2424                 case RTE_ETHER_TYPE_QINQ:
2425                         bp->outer_tpid_bd =
2426                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2427                                 break;
2428                 case RTE_ETHER_TYPE_VLAN:
2429                         bp->outer_tpid_bd =
2430                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2431                                 break;
2432                 case RTE_ETHER_TYPE_QINQ1:
2433                         bp->outer_tpid_bd =
2434                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2435                                 break;
2436                 case RTE_ETHER_TYPE_QINQ2:
2437                         bp->outer_tpid_bd =
2438                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2439                                 break;
2440                 case RTE_ETHER_TYPE_QINQ3:
2441                         bp->outer_tpid_bd =
2442                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2443                                 break;
2444                 default:
2445                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2446                         return -EINVAL;
2447                 }
2448                 bp->outer_tpid_bd |= tpid;
2449                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2450         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2451                 PMD_DRV_LOG(ERR,
2452                             "Can accelerate only outer vlan in QinQ\n");
2453                 return -EINVAL;
2454         }
2455
2456         return 0;
2457 }
2458
2459 static int
2460 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2461                              struct rte_ether_addr *addr)
2462 {
2463         struct bnxt *bp = dev->data->dev_private;
2464         /* Default Filter is tied to VNIC 0 */
2465         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2466         int rc;
2467
2468         rc = is_bnxt_in_error(bp);
2469         if (rc)
2470                 return rc;
2471
2472         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2473                 return -EPERM;
2474
2475         if (rte_is_zero_ether_addr(addr))
2476                 return -EINVAL;
2477
2478         /* Filter settings will get applied when port is started */
2479         if (!dev->data->dev_started)
2480                 return 0;
2481
2482         /* Check if the requested MAC is already added */
2483         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2484                 return 0;
2485
2486         /* Destroy filter and re-create it */
2487         bnxt_del_dflt_mac_filter(bp, vnic);
2488
2489         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2490         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2491                 /* This filter will allow only untagged packets */
2492                 rc = bnxt_add_vlan_filter(bp, 0);
2493         } else {
2494                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2495         }
2496
2497         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2498         return rc;
2499 }
2500
2501 static int
2502 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2503                           struct rte_ether_addr *mc_addr_set,
2504                           uint32_t nb_mc_addr)
2505 {
2506         struct bnxt *bp = eth_dev->data->dev_private;
2507         char *mc_addr_list = (char *)mc_addr_set;
2508         struct bnxt_vnic_info *vnic;
2509         uint32_t off = 0, i = 0;
2510         int rc;
2511
2512         rc = is_bnxt_in_error(bp);
2513         if (rc)
2514                 return rc;
2515
2516         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2517
2518         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2519                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2520                 goto allmulti;
2521         }
2522
2523         /* TODO Check for Duplicate mcast addresses */
2524         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2525         for (i = 0; i < nb_mc_addr; i++) {
2526                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2527                         RTE_ETHER_ADDR_LEN);
2528                 off += RTE_ETHER_ADDR_LEN;
2529         }
2530
2531         vnic->mc_addr_cnt = i;
2532         if (vnic->mc_addr_cnt)
2533                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2534         else
2535                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2536
2537 allmulti:
2538         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2539 }
2540
2541 static int
2542 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2543 {
2544         struct bnxt *bp = dev->data->dev_private;
2545         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2546         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2547         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2548         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2549         int ret;
2550
2551         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2552                         fw_major, fw_minor, fw_updt, fw_rsvd);
2553
2554         ret += 1; /* add the size of '\0' */
2555         if (fw_size < (uint32_t)ret)
2556                 return ret;
2557         else
2558                 return 0;
2559 }
2560
2561 static void
2562 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2563         struct rte_eth_rxq_info *qinfo)
2564 {
2565         struct bnxt *bp = dev->data->dev_private;
2566         struct bnxt_rx_queue *rxq;
2567
2568         if (is_bnxt_in_error(bp))
2569                 return;
2570
2571         rxq = dev->data->rx_queues[queue_id];
2572
2573         qinfo->mp = rxq->mb_pool;
2574         qinfo->scattered_rx = dev->data->scattered_rx;
2575         qinfo->nb_desc = rxq->nb_rx_desc;
2576
2577         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2578         qinfo->conf.rx_drop_en = 0;
2579         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2580 }
2581
2582 static void
2583 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2584         struct rte_eth_txq_info *qinfo)
2585 {
2586         struct bnxt *bp = dev->data->dev_private;
2587         struct bnxt_tx_queue *txq;
2588
2589         if (is_bnxt_in_error(bp))
2590                 return;
2591
2592         txq = dev->data->tx_queues[queue_id];
2593
2594         qinfo->nb_desc = txq->nb_tx_desc;
2595
2596         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2597         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2598         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2599
2600         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2601         qinfo->conf.tx_rs_thresh = 0;
2602         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2603 }
2604
2605 static int
2606 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2607                        struct rte_eth_burst_mode *mode)
2608 {
2609         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2610
2611         if (pkt_burst == bnxt_recv_pkts) {
2612                 snprintf(mode->info, sizeof(mode->info), "%s",
2613                          "Scalar");
2614                 return 0;
2615         }
2616 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2617         if (pkt_burst == bnxt_recv_pkts_vec) {
2618                 snprintf(mode->info, sizeof(mode->info), "%s",
2619                          "Vector SSE");
2620                 return 0;
2621         }
2622 #endif
2623
2624         return -EINVAL;
2625 }
2626
2627 static int
2628 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2629                        struct rte_eth_burst_mode *mode)
2630 {
2631         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2632
2633         if (pkt_burst == bnxt_xmit_pkts) {
2634                 snprintf(mode->info, sizeof(mode->info), "%s",
2635                          "Scalar");
2636                 return 0;
2637         }
2638 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2639         if (pkt_burst == bnxt_xmit_pkts_vec) {
2640                 snprintf(mode->info, sizeof(mode->info), "%s",
2641                          "Vector SSE");
2642                 return 0;
2643         }
2644 #endif
2645
2646         return -EINVAL;
2647 }
2648
2649 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2650 {
2651         struct bnxt *bp = eth_dev->data->dev_private;
2652         uint32_t new_pkt_size;
2653         uint32_t rc = 0;
2654         uint32_t i;
2655
2656         rc = is_bnxt_in_error(bp);
2657         if (rc)
2658                 return rc;
2659
2660         /* Exit if receive queues are not configured yet */
2661         if (!eth_dev->data->nb_rx_queues)
2662                 return rc;
2663
2664         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2665                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2666
2667 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2668         /*
2669          * If vector-mode tx/rx is active, disallow any MTU change that would
2670          * require scattered receive support.
2671          */
2672         if (eth_dev->data->dev_started &&
2673             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2674              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2675             (new_pkt_size >
2676              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2677                 PMD_DRV_LOG(ERR,
2678                             "MTU change would require scattered rx support. ");
2679                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2680                 return -EINVAL;
2681         }
2682 #endif
2683
2684         if (new_mtu > RTE_ETHER_MTU) {
2685                 bp->flags |= BNXT_FLAG_JUMBO;
2686                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2687                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2688         } else {
2689                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2690                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2691                 bp->flags &= ~BNXT_FLAG_JUMBO;
2692         }
2693
2694         /* Is there a change in mtu setting? */
2695         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2696                 return rc;
2697
2698         for (i = 0; i < bp->nr_vnics; i++) {
2699                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2700                 uint16_t size = 0;
2701
2702                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2703                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2704                 if (rc)
2705                         break;
2706
2707                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2708                 size -= RTE_PKTMBUF_HEADROOM;
2709
2710                 if (size < new_mtu) {
2711                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2712                         if (rc)
2713                                 return rc;
2714                 }
2715         }
2716
2717         if (!rc)
2718                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2719
2720         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2721
2722         return rc;
2723 }
2724
2725 static int
2726 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2727 {
2728         struct bnxt *bp = dev->data->dev_private;
2729         uint16_t vlan = bp->vlan;
2730         int rc;
2731
2732         rc = is_bnxt_in_error(bp);
2733         if (rc)
2734                 return rc;
2735
2736         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2737                 PMD_DRV_LOG(ERR,
2738                         "PVID cannot be modified for this function\n");
2739                 return -ENOTSUP;
2740         }
2741         bp->vlan = on ? pvid : 0;
2742
2743         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2744         if (rc)
2745                 bp->vlan = vlan;
2746         return rc;
2747 }
2748
2749 static int
2750 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2751 {
2752         struct bnxt *bp = dev->data->dev_private;
2753         int rc;
2754
2755         rc = is_bnxt_in_error(bp);
2756         if (rc)
2757                 return rc;
2758
2759         return bnxt_hwrm_port_led_cfg(bp, true);
2760 }
2761
2762 static int
2763 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2764 {
2765         struct bnxt *bp = dev->data->dev_private;
2766         int rc;
2767
2768         rc = is_bnxt_in_error(bp);
2769         if (rc)
2770                 return rc;
2771
2772         return bnxt_hwrm_port_led_cfg(bp, false);
2773 }
2774
2775 static uint32_t
2776 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2777 {
2778         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2779         uint32_t desc = 0, raw_cons = 0, cons;
2780         struct bnxt_cp_ring_info *cpr;
2781         struct bnxt_rx_queue *rxq;
2782         struct rx_pkt_cmpl *rxcmp;
2783         int rc;
2784
2785         rc = is_bnxt_in_error(bp);
2786         if (rc)
2787                 return rc;
2788
2789         rxq = dev->data->rx_queues[rx_queue_id];
2790         cpr = rxq->cp_ring;
2791         raw_cons = cpr->cp_raw_cons;
2792
2793         while (1) {
2794                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2795                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2796                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2797
2798                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2799                         break;
2800                 } else {
2801                         raw_cons++;
2802                         desc++;
2803                 }
2804         }
2805
2806         return desc;
2807 }
2808
2809 static int
2810 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2811 {
2812         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2813         struct bnxt_rx_ring_info *rxr;
2814         struct bnxt_cp_ring_info *cpr;
2815         struct bnxt_sw_rx_bd *rx_buf;
2816         struct rx_pkt_cmpl *rxcmp;
2817         uint32_t cons, cp_cons;
2818         int rc;
2819
2820         if (!rxq)
2821                 return -EINVAL;
2822
2823         rc = is_bnxt_in_error(rxq->bp);
2824         if (rc)
2825                 return rc;
2826
2827         cpr = rxq->cp_ring;
2828         rxr = rxq->rx_ring;
2829
2830         if (offset >= rxq->nb_rx_desc)
2831                 return -EINVAL;
2832
2833         cons = RING_CMP(cpr->cp_ring_struct, offset);
2834         cp_cons = cpr->cp_raw_cons;
2835         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2836
2837         if (cons > cp_cons) {
2838                 if (CMPL_VALID(rxcmp, cpr->valid))
2839                         return RTE_ETH_RX_DESC_DONE;
2840         } else {
2841                 if (CMPL_VALID(rxcmp, !cpr->valid))
2842                         return RTE_ETH_RX_DESC_DONE;
2843         }
2844         rx_buf = &rxr->rx_buf_ring[cons];
2845         if (rx_buf->mbuf == NULL)
2846                 return RTE_ETH_RX_DESC_UNAVAIL;
2847
2848
2849         return RTE_ETH_RX_DESC_AVAIL;
2850 }
2851
2852 static int
2853 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2854 {
2855         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2856         struct bnxt_tx_ring_info *txr;
2857         struct bnxt_cp_ring_info *cpr;
2858         struct bnxt_sw_tx_bd *tx_buf;
2859         struct tx_pkt_cmpl *txcmp;
2860         uint32_t cons, cp_cons;
2861         int rc;
2862
2863         if (!txq)
2864                 return -EINVAL;
2865
2866         rc = is_bnxt_in_error(txq->bp);
2867         if (rc)
2868                 return rc;
2869
2870         cpr = txq->cp_ring;
2871         txr = txq->tx_ring;
2872
2873         if (offset >= txq->nb_tx_desc)
2874                 return -EINVAL;
2875
2876         cons = RING_CMP(cpr->cp_ring_struct, offset);
2877         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2878         cp_cons = cpr->cp_raw_cons;
2879
2880         if (cons > cp_cons) {
2881                 if (CMPL_VALID(txcmp, cpr->valid))
2882                         return RTE_ETH_TX_DESC_UNAVAIL;
2883         } else {
2884                 if (CMPL_VALID(txcmp, !cpr->valid))
2885                         return RTE_ETH_TX_DESC_UNAVAIL;
2886         }
2887         tx_buf = &txr->tx_buf_ring[cons];
2888         if (tx_buf->mbuf == NULL)
2889                 return RTE_ETH_TX_DESC_DONE;
2890
2891         return RTE_ETH_TX_DESC_FULL;
2892 }
2893
2894 static struct bnxt_filter_info *
2895 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2896                                 struct rte_eth_ethertype_filter *efilter,
2897                                 struct bnxt_vnic_info *vnic0,
2898                                 struct bnxt_vnic_info *vnic,
2899                                 int *ret)
2900 {
2901         struct bnxt_filter_info *mfilter = NULL;
2902         int match = 0;
2903         *ret = 0;
2904
2905         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2906                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2907                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2908                         " ethertype filter.", efilter->ether_type);
2909                 *ret = -EINVAL;
2910                 goto exit;
2911         }
2912         if (efilter->queue >= bp->rx_nr_rings) {
2913                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2914                 *ret = -EINVAL;
2915                 goto exit;
2916         }
2917
2918         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2919         vnic = &bp->vnic_info[efilter->queue];
2920         if (vnic == NULL) {
2921                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2922                 *ret = -EINVAL;
2923                 goto exit;
2924         }
2925
2926         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2927                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2928                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2929                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2930                              mfilter->flags ==
2931                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2932                              mfilter->ethertype == efilter->ether_type)) {
2933                                 match = 1;
2934                                 break;
2935                         }
2936                 }
2937         } else {
2938                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2939                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2940                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2941                              mfilter->ethertype == efilter->ether_type &&
2942                              mfilter->flags ==
2943                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2944                                 match = 1;
2945                                 break;
2946                         }
2947         }
2948
2949         if (match)
2950                 *ret = -EEXIST;
2951
2952 exit:
2953         return mfilter;
2954 }
2955
2956 static int
2957 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2958                         enum rte_filter_op filter_op,
2959                         void *arg)
2960 {
2961         struct bnxt *bp = dev->data->dev_private;
2962         struct rte_eth_ethertype_filter *efilter =
2963                         (struct rte_eth_ethertype_filter *)arg;
2964         struct bnxt_filter_info *bfilter, *filter1;
2965         struct bnxt_vnic_info *vnic, *vnic0;
2966         int ret;
2967
2968         if (filter_op == RTE_ETH_FILTER_NOP)
2969                 return 0;
2970
2971         if (arg == NULL) {
2972                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2973                             filter_op);
2974                 return -EINVAL;
2975         }
2976
2977         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2978         vnic = &bp->vnic_info[efilter->queue];
2979
2980         switch (filter_op) {
2981         case RTE_ETH_FILTER_ADD:
2982                 bnxt_match_and_validate_ether_filter(bp, efilter,
2983                                                         vnic0, vnic, &ret);
2984                 if (ret < 0)
2985                         return ret;
2986
2987                 bfilter = bnxt_get_unused_filter(bp);
2988                 if (bfilter == NULL) {
2989                         PMD_DRV_LOG(ERR,
2990                                 "Not enough resources for a new filter.\n");
2991                         return -ENOMEM;
2992                 }
2993                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2994                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2995                        RTE_ETHER_ADDR_LEN);
2996                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2997                        RTE_ETHER_ADDR_LEN);
2998                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2999                 bfilter->ethertype = efilter->ether_type;
3000                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3001
3002                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3003                 if (filter1 == NULL) {
3004                         ret = -EINVAL;
3005                         goto cleanup;
3006                 }
3007                 bfilter->enables |=
3008                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3009                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3010
3011                 bfilter->dst_id = vnic->fw_vnic_id;
3012
3013                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3014                         bfilter->flags =
3015                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3016                 }
3017
3018                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3019                 if (ret)
3020                         goto cleanup;
3021                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3022                 break;
3023         case RTE_ETH_FILTER_DELETE:
3024                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3025                                                         vnic0, vnic, &ret);
3026                 if (ret == -EEXIST) {
3027                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3028
3029                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3030                                       next);
3031                         bnxt_free_filter(bp, filter1);
3032                 } else if (ret == 0) {
3033                         PMD_DRV_LOG(ERR, "No matching filter found\n");
3034                 }
3035                 break;
3036         default:
3037                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3038                 ret = -EINVAL;
3039                 goto error;
3040         }
3041         return ret;
3042 cleanup:
3043         bnxt_free_filter(bp, bfilter);
3044 error:
3045         return ret;
3046 }
3047
3048 static inline int
3049 parse_ntuple_filter(struct bnxt *bp,
3050                     struct rte_eth_ntuple_filter *nfilter,
3051                     struct bnxt_filter_info *bfilter)
3052 {
3053         uint32_t en = 0;
3054
3055         if (nfilter->queue >= bp->rx_nr_rings) {
3056                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3057                 return -EINVAL;
3058         }
3059
3060         switch (nfilter->dst_port_mask) {
3061         case UINT16_MAX:
3062                 bfilter->dst_port_mask = -1;
3063                 bfilter->dst_port = nfilter->dst_port;
3064                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3065                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3066                 break;
3067         default:
3068                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3069                 return -EINVAL;
3070         }
3071
3072         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3073         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3074
3075         switch (nfilter->proto_mask) {
3076         case UINT8_MAX:
3077                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3078                         bfilter->ip_protocol = 17;
3079                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3080                         bfilter->ip_protocol = 6;
3081                 else
3082                         return -EINVAL;
3083                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3084                 break;
3085         default:
3086                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3087                 return -EINVAL;
3088         }
3089
3090         switch (nfilter->dst_ip_mask) {
3091         case UINT32_MAX:
3092                 bfilter->dst_ipaddr_mask[0] = -1;
3093                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3094                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3095                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3096                 break;
3097         default:
3098                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3099                 return -EINVAL;
3100         }
3101
3102         switch (nfilter->src_ip_mask) {
3103         case UINT32_MAX:
3104                 bfilter->src_ipaddr_mask[0] = -1;
3105                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3106                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3107                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3108                 break;
3109         default:
3110                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3111                 return -EINVAL;
3112         }
3113
3114         switch (nfilter->src_port_mask) {
3115         case UINT16_MAX:
3116                 bfilter->src_port_mask = -1;
3117                 bfilter->src_port = nfilter->src_port;
3118                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3119                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3120                 break;
3121         default:
3122                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3123                 return -EINVAL;
3124         }
3125
3126         bfilter->enables = en;
3127         return 0;
3128 }
3129
3130 static struct bnxt_filter_info*
3131 bnxt_match_ntuple_filter(struct bnxt *bp,
3132                          struct bnxt_filter_info *bfilter,
3133                          struct bnxt_vnic_info **mvnic)
3134 {
3135         struct bnxt_filter_info *mfilter = NULL;
3136         int i;
3137
3138         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3139                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3140                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3141                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3142                             bfilter->src_ipaddr_mask[0] ==
3143                             mfilter->src_ipaddr_mask[0] &&
3144                             bfilter->src_port == mfilter->src_port &&
3145                             bfilter->src_port_mask == mfilter->src_port_mask &&
3146                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3147                             bfilter->dst_ipaddr_mask[0] ==
3148                             mfilter->dst_ipaddr_mask[0] &&
3149                             bfilter->dst_port == mfilter->dst_port &&
3150                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3151                             bfilter->flags == mfilter->flags &&
3152                             bfilter->enables == mfilter->enables) {
3153                                 if (mvnic)
3154                                         *mvnic = vnic;
3155                                 return mfilter;
3156                         }
3157                 }
3158         }
3159         return NULL;
3160 }
3161
3162 static int
3163 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3164                        struct rte_eth_ntuple_filter *nfilter,
3165                        enum rte_filter_op filter_op)
3166 {
3167         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3168         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3169         int ret;
3170
3171         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3172                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3173                 return -EINVAL;
3174         }
3175
3176         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3177                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3178                 return -EINVAL;
3179         }
3180
3181         bfilter = bnxt_get_unused_filter(bp);
3182         if (bfilter == NULL) {
3183                 PMD_DRV_LOG(ERR,
3184                         "Not enough resources for a new filter.\n");
3185                 return -ENOMEM;
3186         }
3187         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3188         if (ret < 0)
3189                 goto free_filter;
3190
3191         vnic = &bp->vnic_info[nfilter->queue];
3192         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3193         filter1 = STAILQ_FIRST(&vnic0->filter);
3194         if (filter1 == NULL) {
3195                 ret = -EINVAL;
3196                 goto free_filter;
3197         }
3198
3199         bfilter->dst_id = vnic->fw_vnic_id;
3200         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3201         bfilter->enables |=
3202                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3203         bfilter->ethertype = 0x800;
3204         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3205
3206         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3207
3208         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3209             bfilter->dst_id == mfilter->dst_id) {
3210                 PMD_DRV_LOG(ERR, "filter exists.\n");
3211                 ret = -EEXIST;
3212                 goto free_filter;
3213         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3214                    bfilter->dst_id != mfilter->dst_id) {
3215                 mfilter->dst_id = vnic->fw_vnic_id;
3216                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3217                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3218                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3219                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3220                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3221                 goto free_filter;
3222         }
3223         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3224                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3225                 ret = -ENOENT;
3226                 goto free_filter;
3227         }
3228
3229         if (filter_op == RTE_ETH_FILTER_ADD) {
3230                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3231                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3232                 if (ret)
3233                         goto free_filter;
3234                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3235         } else {
3236                 if (mfilter == NULL) {
3237                         /* This should not happen. But for Coverity! */
3238                         ret = -ENOENT;
3239                         goto free_filter;
3240                 }
3241                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3242
3243                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3244                 bnxt_free_filter(bp, mfilter);
3245                 bnxt_free_filter(bp, bfilter);
3246         }
3247
3248         return 0;
3249 free_filter:
3250         bnxt_free_filter(bp, bfilter);
3251         return ret;
3252 }
3253
3254 static int
3255 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3256                         enum rte_filter_op filter_op,
3257                         void *arg)
3258 {
3259         struct bnxt *bp = dev->data->dev_private;
3260         int ret;
3261
3262         if (filter_op == RTE_ETH_FILTER_NOP)
3263                 return 0;
3264
3265         if (arg == NULL) {
3266                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3267                             filter_op);
3268                 return -EINVAL;
3269         }
3270
3271         switch (filter_op) {
3272         case RTE_ETH_FILTER_ADD:
3273                 ret = bnxt_cfg_ntuple_filter(bp,
3274                         (struct rte_eth_ntuple_filter *)arg,
3275                         filter_op);
3276                 break;
3277         case RTE_ETH_FILTER_DELETE:
3278                 ret = bnxt_cfg_ntuple_filter(bp,
3279                         (struct rte_eth_ntuple_filter *)arg,
3280                         filter_op);
3281                 break;
3282         default:
3283                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3284                 ret = -EINVAL;
3285                 break;
3286         }
3287         return ret;
3288 }
3289
3290 static int
3291 bnxt_parse_fdir_filter(struct bnxt *bp,
3292                        struct rte_eth_fdir_filter *fdir,
3293                        struct bnxt_filter_info *filter)
3294 {
3295         enum rte_fdir_mode fdir_mode =
3296                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3297         struct bnxt_vnic_info *vnic0, *vnic;
3298         struct bnxt_filter_info *filter1;
3299         uint32_t en = 0;
3300         int i;
3301
3302         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3303                 return -EINVAL;
3304
3305         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3306         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3307
3308         switch (fdir->input.flow_type) {
3309         case RTE_ETH_FLOW_IPV4:
3310         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3311                 /* FALLTHROUGH */
3312                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3313                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3314                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3315                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3316                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3317                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3318                 filter->ip_addr_type =
3319                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3320                 filter->src_ipaddr_mask[0] = 0xffffffff;
3321                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3322                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3323                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3324                 filter->ethertype = 0x800;
3325                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3326                 break;
3327         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3328                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3329                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3330                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3331                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3332                 filter->dst_port_mask = 0xffff;
3333                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3334                 filter->src_port_mask = 0xffff;
3335                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3336                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3337                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3338                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3339                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3340                 filter->ip_protocol = 6;
3341                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3342                 filter->ip_addr_type =
3343                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3344                 filter->src_ipaddr_mask[0] = 0xffffffff;
3345                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3346                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3347                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3348                 filter->ethertype = 0x800;
3349                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3350                 break;
3351         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3352                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3353                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3354                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3355                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3356                 filter->dst_port_mask = 0xffff;
3357                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3358                 filter->src_port_mask = 0xffff;
3359                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3360                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3361                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3362                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3363                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3364                 filter->ip_protocol = 17;
3365                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3366                 filter->ip_addr_type =
3367                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3368                 filter->src_ipaddr_mask[0] = 0xffffffff;
3369                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3370                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3371                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3372                 filter->ethertype = 0x800;
3373                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3374                 break;
3375         case RTE_ETH_FLOW_IPV6:
3376         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3377                 /* FALLTHROUGH */
3378                 filter->ip_addr_type =
3379                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3380                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3381                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3382                 rte_memcpy(filter->src_ipaddr,
3383                            fdir->input.flow.ipv6_flow.src_ip, 16);
3384                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3385                 rte_memcpy(filter->dst_ipaddr,
3386                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3387                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3388                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3389                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3390                 memset(filter->src_ipaddr_mask, 0xff, 16);
3391                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3392                 filter->ethertype = 0x86dd;
3393                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3394                 break;
3395         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3396                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3397                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3398                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3399                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3400                 filter->dst_port_mask = 0xffff;
3401                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3402                 filter->src_port_mask = 0xffff;
3403                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3404                 filter->ip_addr_type =
3405                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3406                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3407                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3408                 rte_memcpy(filter->src_ipaddr,
3409                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3410                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3411                 rte_memcpy(filter->dst_ipaddr,
3412                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3413                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3414                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3415                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3416                 memset(filter->src_ipaddr_mask, 0xff, 16);
3417                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3418                 filter->ethertype = 0x86dd;
3419                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3420                 break;
3421         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3422                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3423                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3424                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3425                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3426                 filter->dst_port_mask = 0xffff;
3427                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3428                 filter->src_port_mask = 0xffff;
3429                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3430                 filter->ip_addr_type =
3431                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3432                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3433                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3434                 rte_memcpy(filter->src_ipaddr,
3435                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3436                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3437                 rte_memcpy(filter->dst_ipaddr,
3438                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3439                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3440                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3441                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3442                 memset(filter->src_ipaddr_mask, 0xff, 16);
3443                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3444                 filter->ethertype = 0x86dd;
3445                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3446                 break;
3447         case RTE_ETH_FLOW_L2_PAYLOAD:
3448                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3449                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3450                 break;
3451         case RTE_ETH_FLOW_VXLAN:
3452                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3453                         return -EINVAL;
3454                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3455                 filter->tunnel_type =
3456                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3457                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3458                 break;
3459         case RTE_ETH_FLOW_NVGRE:
3460                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3461                         return -EINVAL;
3462                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3463                 filter->tunnel_type =
3464                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3465                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3466                 break;
3467         case RTE_ETH_FLOW_UNKNOWN:
3468         case RTE_ETH_FLOW_RAW:
3469         case RTE_ETH_FLOW_FRAG_IPV4:
3470         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3471         case RTE_ETH_FLOW_FRAG_IPV6:
3472         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3473         case RTE_ETH_FLOW_IPV6_EX:
3474         case RTE_ETH_FLOW_IPV6_TCP_EX:
3475         case RTE_ETH_FLOW_IPV6_UDP_EX:
3476         case RTE_ETH_FLOW_GENEVE:
3477                 /* FALLTHROUGH */
3478         default:
3479                 return -EINVAL;
3480         }
3481
3482         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3483         vnic = &bp->vnic_info[fdir->action.rx_queue];
3484         if (vnic == NULL) {
3485                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3486                 return -EINVAL;
3487         }
3488
3489         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3490                 rte_memcpy(filter->dst_macaddr,
3491                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3492                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3493         }
3494
3495         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3496                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3497                 filter1 = STAILQ_FIRST(&vnic0->filter);
3498                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3499         } else {
3500                 filter->dst_id = vnic->fw_vnic_id;
3501                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3502                         if (filter->dst_macaddr[i] == 0x00)
3503                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3504                         else
3505                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3506         }
3507
3508         if (filter1 == NULL)
3509                 return -EINVAL;
3510
3511         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3512         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3513
3514         filter->enables = en;
3515
3516         return 0;
3517 }
3518
3519 static struct bnxt_filter_info *
3520 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3521                 struct bnxt_vnic_info **mvnic)
3522 {
3523         struct bnxt_filter_info *mf = NULL;
3524         int i;
3525
3526         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3527                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3528
3529                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3530                         if (mf->filter_type == nf->filter_type &&
3531                             mf->flags == nf->flags &&
3532                             mf->src_port == nf->src_port &&
3533                             mf->src_port_mask == nf->src_port_mask &&
3534                             mf->dst_port == nf->dst_port &&
3535                             mf->dst_port_mask == nf->dst_port_mask &&
3536                             mf->ip_protocol == nf->ip_protocol &&
3537                             mf->ip_addr_type == nf->ip_addr_type &&
3538                             mf->ethertype == nf->ethertype &&
3539                             mf->vni == nf->vni &&
3540                             mf->tunnel_type == nf->tunnel_type &&
3541                             mf->l2_ovlan == nf->l2_ovlan &&
3542                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3543                             mf->l2_ivlan == nf->l2_ivlan &&
3544                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3545                             !memcmp(mf->l2_addr, nf->l2_addr,
3546                                     RTE_ETHER_ADDR_LEN) &&
3547                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3548                                     RTE_ETHER_ADDR_LEN) &&
3549                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3550                                     RTE_ETHER_ADDR_LEN) &&
3551                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3552                                     RTE_ETHER_ADDR_LEN) &&
3553                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3554                                     sizeof(nf->src_ipaddr)) &&
3555                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3556                                     sizeof(nf->src_ipaddr_mask)) &&
3557                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3558                                     sizeof(nf->dst_ipaddr)) &&
3559                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3560                                     sizeof(nf->dst_ipaddr_mask))) {
3561                                 if (mvnic)
3562                                         *mvnic = vnic;
3563                                 return mf;
3564                         }
3565                 }
3566         }
3567         return NULL;
3568 }
3569
3570 static int
3571 bnxt_fdir_filter(struct rte_eth_dev *dev,
3572                  enum rte_filter_op filter_op,
3573                  void *arg)
3574 {
3575         struct bnxt *bp = dev->data->dev_private;
3576         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3577         struct bnxt_filter_info *filter, *match;
3578         struct bnxt_vnic_info *vnic, *mvnic;
3579         int ret = 0, i;
3580
3581         if (filter_op == RTE_ETH_FILTER_NOP)
3582                 return 0;
3583
3584         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3585                 return -EINVAL;
3586
3587         switch (filter_op) {
3588         case RTE_ETH_FILTER_ADD:
3589         case RTE_ETH_FILTER_DELETE:
3590                 /* FALLTHROUGH */
3591                 filter = bnxt_get_unused_filter(bp);
3592                 if (filter == NULL) {
3593                         PMD_DRV_LOG(ERR,
3594                                 "Not enough resources for a new flow.\n");
3595                         return -ENOMEM;
3596                 }
3597
3598                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3599                 if (ret != 0)
3600                         goto free_filter;
3601                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3602
3603                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3604                         vnic = &bp->vnic_info[0];
3605                 else
3606                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3607
3608                 match = bnxt_match_fdir(bp, filter, &mvnic);
3609                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3610                         if (match->dst_id == vnic->fw_vnic_id) {
3611                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3612                                 ret = -EEXIST;
3613                                 goto free_filter;
3614                         } else {
3615                                 match->dst_id = vnic->fw_vnic_id;
3616                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3617                                                                   match->dst_id,
3618                                                                   match);
3619                                 STAILQ_REMOVE(&mvnic->filter, match,
3620                                               bnxt_filter_info, next);
3621                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3622                                 PMD_DRV_LOG(ERR,
3623                                         "Filter with matching pattern exist\n");
3624                                 PMD_DRV_LOG(ERR,
3625                                         "Updated it to new destination q\n");
3626                                 goto free_filter;
3627                         }
3628                 }
3629                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3630                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3631                         ret = -ENOENT;
3632                         goto free_filter;
3633                 }
3634
3635                 if (filter_op == RTE_ETH_FILTER_ADD) {
3636                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3637                                                           filter->dst_id,
3638                                                           filter);
3639                         if (ret)
3640                                 goto free_filter;
3641                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3642                 } else {
3643                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3644                         STAILQ_REMOVE(&vnic->filter, match,
3645                                       bnxt_filter_info, next);
3646                         bnxt_free_filter(bp, match);
3647                         bnxt_free_filter(bp, filter);
3648                 }
3649                 break;
3650         case RTE_ETH_FILTER_FLUSH:
3651                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3652                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3653
3654                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3655                                 if (filter->filter_type ==
3656                                     HWRM_CFA_NTUPLE_FILTER) {
3657                                         ret =
3658                                         bnxt_hwrm_clear_ntuple_filter(bp,
3659                                                                       filter);
3660                                         STAILQ_REMOVE(&vnic->filter, filter,
3661                                                       bnxt_filter_info, next);
3662                                 }
3663                         }
3664                 }
3665                 return ret;
3666         case RTE_ETH_FILTER_UPDATE:
3667         case RTE_ETH_FILTER_STATS:
3668         case RTE_ETH_FILTER_INFO:
3669                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3670                 break;
3671         default:
3672                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3673                 ret = -EINVAL;
3674                 break;
3675         }
3676         return ret;
3677
3678 free_filter:
3679         bnxt_free_filter(bp, filter);
3680         return ret;
3681 }
3682
3683 int
3684 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3685                     enum rte_filter_type filter_type,
3686                     enum rte_filter_op filter_op, void *arg)
3687 {
3688         struct bnxt *bp = dev->data->dev_private;
3689         int ret = 0;
3690
3691         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3692                 struct bnxt_vf_representor *vfr = dev->data->dev_private;
3693                 bp = vfr->parent_dev->data->dev_private;
3694         }
3695
3696         ret = is_bnxt_in_error(bp);
3697         if (ret)
3698                 return ret;
3699
3700         switch (filter_type) {
3701         case RTE_ETH_FILTER_TUNNEL:
3702                 PMD_DRV_LOG(ERR,
3703                         "filter type: %d: To be implemented\n", filter_type);
3704                 break;
3705         case RTE_ETH_FILTER_FDIR:
3706                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3707                 break;
3708         case RTE_ETH_FILTER_NTUPLE:
3709                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3710                 break;
3711         case RTE_ETH_FILTER_ETHERTYPE:
3712                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3713                 break;
3714         case RTE_ETH_FILTER_GENERIC:
3715                 if (filter_op != RTE_ETH_FILTER_GET)
3716                         return -EINVAL;
3717                 if (BNXT_TRUFLOW_EN(bp))
3718                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3719                 else
3720                         *(const void **)arg = &bnxt_flow_ops;
3721                 break;
3722         default:
3723                 PMD_DRV_LOG(ERR,
3724                         "Filter type (%d) not supported", filter_type);
3725                 ret = -EINVAL;
3726                 break;
3727         }
3728         return ret;
3729 }
3730
3731 static const uint32_t *
3732 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3733 {
3734         static const uint32_t ptypes[] = {
3735                 RTE_PTYPE_L2_ETHER_VLAN,
3736                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3737                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3738                 RTE_PTYPE_L4_ICMP,
3739                 RTE_PTYPE_L4_TCP,
3740                 RTE_PTYPE_L4_UDP,
3741                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3742                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3743                 RTE_PTYPE_INNER_L4_ICMP,
3744                 RTE_PTYPE_INNER_L4_TCP,
3745                 RTE_PTYPE_INNER_L4_UDP,
3746                 RTE_PTYPE_UNKNOWN
3747         };
3748
3749         if (!dev->rx_pkt_burst)
3750                 return NULL;
3751
3752         return ptypes;
3753 }
3754
3755 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3756                          int reg_win)
3757 {
3758         uint32_t reg_base = *reg_arr & 0xfffff000;
3759         uint32_t win_off;
3760         int i;
3761
3762         for (i = 0; i < count; i++) {
3763                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3764                         return -ERANGE;
3765         }
3766         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3767         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3768         return 0;
3769 }
3770
3771 static int bnxt_map_ptp_regs(struct bnxt *bp)
3772 {
3773         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3774         uint32_t *reg_arr;
3775         int rc, i;
3776
3777         reg_arr = ptp->rx_regs;
3778         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3779         if (rc)
3780                 return rc;
3781
3782         reg_arr = ptp->tx_regs;
3783         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3784         if (rc)
3785                 return rc;
3786
3787         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3788                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3789
3790         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3791                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3792
3793         return 0;
3794 }
3795
3796 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3797 {
3798         rte_write32(0, (uint8_t *)bp->bar0 +
3799                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3800         rte_write32(0, (uint8_t *)bp->bar0 +
3801                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3802 }
3803
3804 static uint64_t bnxt_cc_read(struct bnxt *bp)
3805 {
3806         uint64_t ns;
3807
3808         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3809                               BNXT_GRCPF_REG_SYNC_TIME));
3810         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3811                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3812         return ns;
3813 }
3814
3815 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3816 {
3817         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3818         uint32_t fifo;
3819
3820         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3821                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3822         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3823                 return -EAGAIN;
3824
3825         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3826                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3827         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3828                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3829         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3830                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3831
3832         return 0;
3833 }
3834
3835 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3836 {
3837         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3838         struct bnxt_pf_info *pf = bp->pf;
3839         uint16_t port_id;
3840         uint32_t fifo;
3841
3842         if (!ptp)
3843                 return -ENODEV;
3844
3845         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3846                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3847         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3848                 return -EAGAIN;
3849
3850         port_id = pf->port_id;
3851         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3852                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3853
3854         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3855                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3856         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3857 /*              bnxt_clr_rx_ts(bp);       TBD  */
3858                 return -EBUSY;
3859         }
3860
3861         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3862                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3863         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3864                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3865
3866         return 0;
3867 }
3868
3869 static int
3870 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3871 {
3872         uint64_t ns;
3873         struct bnxt *bp = dev->data->dev_private;
3874         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3875
3876         if (!ptp)
3877                 return 0;
3878
3879         ns = rte_timespec_to_ns(ts);
3880         /* Set the timecounters to a new value. */
3881         ptp->tc.nsec = ns;
3882
3883         return 0;
3884 }
3885
3886 static int
3887 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3888 {
3889         struct bnxt *bp = dev->data->dev_private;
3890         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3891         uint64_t ns, systime_cycles = 0;
3892         int rc = 0;
3893
3894         if (!ptp)
3895                 return 0;
3896
3897         if (BNXT_CHIP_THOR(bp))
3898                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3899                                              &systime_cycles);
3900         else
3901                 systime_cycles = bnxt_cc_read(bp);
3902
3903         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3904         *ts = rte_ns_to_timespec(ns);
3905
3906         return rc;
3907 }
3908 static int
3909 bnxt_timesync_enable(struct rte_eth_dev *dev)
3910 {
3911         struct bnxt *bp = dev->data->dev_private;
3912         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3913         uint32_t shift = 0;
3914         int rc;
3915
3916         if (!ptp)
3917                 return 0;
3918
3919         ptp->rx_filter = 1;
3920         ptp->tx_tstamp_en = 1;
3921         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3922
3923         rc = bnxt_hwrm_ptp_cfg(bp);
3924         if (rc)
3925                 return rc;
3926
3927         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3928         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3929         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3930
3931         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3932         ptp->tc.cc_shift = shift;
3933         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3934
3935         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3936         ptp->rx_tstamp_tc.cc_shift = shift;
3937         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3938
3939         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3940         ptp->tx_tstamp_tc.cc_shift = shift;
3941         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3942
3943         if (!BNXT_CHIP_THOR(bp))
3944                 bnxt_map_ptp_regs(bp);
3945
3946         return 0;
3947 }
3948
3949 static int
3950 bnxt_timesync_disable(struct rte_eth_dev *dev)
3951 {
3952         struct bnxt *bp = dev->data->dev_private;
3953         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3954
3955         if (!ptp)
3956                 return 0;
3957
3958         ptp->rx_filter = 0;
3959         ptp->tx_tstamp_en = 0;
3960         ptp->rxctl = 0;
3961
3962         bnxt_hwrm_ptp_cfg(bp);
3963
3964         if (!BNXT_CHIP_THOR(bp))
3965                 bnxt_unmap_ptp_regs(bp);
3966
3967         return 0;
3968 }
3969
3970 static int
3971 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3972                                  struct timespec *timestamp,
3973                                  uint32_t flags __rte_unused)
3974 {
3975         struct bnxt *bp = dev->data->dev_private;
3976         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3977         uint64_t rx_tstamp_cycles = 0;
3978         uint64_t ns;
3979
3980         if (!ptp)
3981                 return 0;
3982
3983         if (BNXT_CHIP_THOR(bp))
3984                 rx_tstamp_cycles = ptp->rx_timestamp;
3985         else
3986                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3987
3988         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3989         *timestamp = rte_ns_to_timespec(ns);
3990         return  0;
3991 }
3992
3993 static int
3994 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3995                                  struct timespec *timestamp)
3996 {
3997         struct bnxt *bp = dev->data->dev_private;
3998         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3999         uint64_t tx_tstamp_cycles = 0;
4000         uint64_t ns;
4001         int rc = 0;
4002
4003         if (!ptp)
4004                 return 0;
4005
4006         if (BNXT_CHIP_THOR(bp))
4007                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4008                                              &tx_tstamp_cycles);
4009         else
4010                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4011
4012         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4013         *timestamp = rte_ns_to_timespec(ns);
4014
4015         return rc;
4016 }
4017
4018 static int
4019 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4020 {
4021         struct bnxt *bp = dev->data->dev_private;
4022         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4023
4024         if (!ptp)
4025                 return 0;
4026
4027         ptp->tc.nsec += delta;
4028
4029         return 0;
4030 }
4031
4032 static int
4033 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4034 {
4035         struct bnxt *bp = dev->data->dev_private;
4036         int rc;
4037         uint32_t dir_entries;
4038         uint32_t entry_length;
4039
4040         rc = is_bnxt_in_error(bp);
4041         if (rc)
4042                 return rc;
4043
4044         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4045                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4046                     bp->pdev->addr.devid, bp->pdev->addr.function);
4047
4048         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4049         if (rc != 0)
4050                 return rc;
4051
4052         return dir_entries * entry_length;
4053 }
4054
4055 static int
4056 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4057                 struct rte_dev_eeprom_info *in_eeprom)
4058 {
4059         struct bnxt *bp = dev->data->dev_private;
4060         uint32_t index;
4061         uint32_t offset;
4062         int rc;
4063
4064         rc = is_bnxt_in_error(bp);
4065         if (rc)
4066                 return rc;
4067
4068         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4069                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4070                     bp->pdev->addr.devid, bp->pdev->addr.function,
4071                     in_eeprom->offset, in_eeprom->length);
4072
4073         if (in_eeprom->offset == 0) /* special offset value to get directory */
4074                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4075                                                 in_eeprom->data);
4076
4077         index = in_eeprom->offset >> 24;
4078         offset = in_eeprom->offset & 0xffffff;
4079
4080         if (index != 0)
4081                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4082                                            in_eeprom->length, in_eeprom->data);
4083
4084         return 0;
4085 }
4086
4087 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4088 {
4089         switch (dir_type) {
4090         case BNX_DIR_TYPE_CHIMP_PATCH:
4091         case BNX_DIR_TYPE_BOOTCODE:
4092         case BNX_DIR_TYPE_BOOTCODE_2:
4093         case BNX_DIR_TYPE_APE_FW:
4094         case BNX_DIR_TYPE_APE_PATCH:
4095         case BNX_DIR_TYPE_KONG_FW:
4096         case BNX_DIR_TYPE_KONG_PATCH:
4097         case BNX_DIR_TYPE_BONO_FW:
4098         case BNX_DIR_TYPE_BONO_PATCH:
4099                 /* FALLTHROUGH */
4100                 return true;
4101         }
4102
4103         return false;
4104 }
4105
4106 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4107 {
4108         switch (dir_type) {
4109         case BNX_DIR_TYPE_AVS:
4110         case BNX_DIR_TYPE_EXP_ROM_MBA:
4111         case BNX_DIR_TYPE_PCIE:
4112         case BNX_DIR_TYPE_TSCF_UCODE:
4113         case BNX_DIR_TYPE_EXT_PHY:
4114         case BNX_DIR_TYPE_CCM:
4115         case BNX_DIR_TYPE_ISCSI_BOOT:
4116         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4117         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4118                 /* FALLTHROUGH */
4119                 return true;
4120         }
4121
4122         return false;
4123 }
4124
4125 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4126 {
4127         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4128                 bnxt_dir_type_is_other_exec_format(dir_type);
4129 }
4130
4131 static int
4132 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4133                 struct rte_dev_eeprom_info *in_eeprom)
4134 {
4135         struct bnxt *bp = dev->data->dev_private;
4136         uint8_t index, dir_op;
4137         uint16_t type, ext, ordinal, attr;
4138         int rc;
4139
4140         rc = is_bnxt_in_error(bp);
4141         if (rc)
4142                 return rc;
4143
4144         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4145                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4146                     bp->pdev->addr.devid, bp->pdev->addr.function,
4147                     in_eeprom->offset, in_eeprom->length);
4148
4149         if (!BNXT_PF(bp)) {
4150                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4151                 return -EINVAL;
4152         }
4153
4154         type = in_eeprom->magic >> 16;
4155
4156         if (type == 0xffff) { /* special value for directory operations */
4157                 index = in_eeprom->magic & 0xff;
4158                 dir_op = in_eeprom->magic >> 8;
4159                 if (index == 0)
4160                         return -EINVAL;
4161                 switch (dir_op) {
4162                 case 0x0e: /* erase */
4163                         if (in_eeprom->offset != ~in_eeprom->magic)
4164                                 return -EINVAL;
4165                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4166                 default:
4167                         return -EINVAL;
4168                 }
4169         }
4170
4171         /* Create or re-write an NVM item: */
4172         if (bnxt_dir_type_is_executable(type) == true)
4173                 return -EOPNOTSUPP;
4174         ext = in_eeprom->magic & 0xffff;
4175         ordinal = in_eeprom->offset >> 16;
4176         attr = in_eeprom->offset & 0xffff;
4177
4178         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4179                                      in_eeprom->data, in_eeprom->length);
4180 }
4181
4182 /*
4183  * Initialization
4184  */
4185
4186 static const struct eth_dev_ops bnxt_dev_ops = {
4187         .dev_infos_get = bnxt_dev_info_get_op,
4188         .dev_close = bnxt_dev_close_op,
4189         .dev_configure = bnxt_dev_configure_op,
4190         .dev_start = bnxt_dev_start_op,
4191         .dev_stop = bnxt_dev_stop_op,
4192         .dev_set_link_up = bnxt_dev_set_link_up_op,
4193         .dev_set_link_down = bnxt_dev_set_link_down_op,
4194         .stats_get = bnxt_stats_get_op,
4195         .stats_reset = bnxt_stats_reset_op,
4196         .rx_queue_setup = bnxt_rx_queue_setup_op,
4197         .rx_queue_release = bnxt_rx_queue_release_op,
4198         .tx_queue_setup = bnxt_tx_queue_setup_op,
4199         .tx_queue_release = bnxt_tx_queue_release_op,
4200         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4201         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4202         .reta_update = bnxt_reta_update_op,
4203         .reta_query = bnxt_reta_query_op,
4204         .rss_hash_update = bnxt_rss_hash_update_op,
4205         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4206         .link_update = bnxt_link_update_op,
4207         .promiscuous_enable = bnxt_promiscuous_enable_op,
4208         .promiscuous_disable = bnxt_promiscuous_disable_op,
4209         .allmulticast_enable = bnxt_allmulticast_enable_op,
4210         .allmulticast_disable = bnxt_allmulticast_disable_op,
4211         .mac_addr_add = bnxt_mac_addr_add_op,
4212         .mac_addr_remove = bnxt_mac_addr_remove_op,
4213         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4214         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4215         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4216         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4217         .vlan_filter_set = bnxt_vlan_filter_set_op,
4218         .vlan_offload_set = bnxt_vlan_offload_set_op,
4219         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4220         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4221         .mtu_set = bnxt_mtu_set_op,
4222         .mac_addr_set = bnxt_set_default_mac_addr_op,
4223         .xstats_get = bnxt_dev_xstats_get_op,
4224         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4225         .xstats_reset = bnxt_dev_xstats_reset_op,
4226         .fw_version_get = bnxt_fw_version_get,
4227         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4228         .rxq_info_get = bnxt_rxq_info_get_op,
4229         .txq_info_get = bnxt_txq_info_get_op,
4230         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4231         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4232         .dev_led_on = bnxt_dev_led_on_op,
4233         .dev_led_off = bnxt_dev_led_off_op,
4234         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4235         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4236         .rx_queue_count = bnxt_rx_queue_count_op,
4237         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4238         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4239         .rx_queue_start = bnxt_rx_queue_start,
4240         .rx_queue_stop = bnxt_rx_queue_stop,
4241         .tx_queue_start = bnxt_tx_queue_start,
4242         .tx_queue_stop = bnxt_tx_queue_stop,
4243         .filter_ctrl = bnxt_filter_ctrl_op,
4244         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4245         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4246         .get_eeprom           = bnxt_get_eeprom_op,
4247         .set_eeprom           = bnxt_set_eeprom_op,
4248         .timesync_enable      = bnxt_timesync_enable,
4249         .timesync_disable     = bnxt_timesync_disable,
4250         .timesync_read_time   = bnxt_timesync_read_time,
4251         .timesync_write_time   = bnxt_timesync_write_time,
4252         .timesync_adjust_time = bnxt_timesync_adjust_time,
4253         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4254         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4255 };
4256
4257 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4258 {
4259         uint32_t offset;
4260
4261         /* Only pre-map the reset GRC registers using window 3 */
4262         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4263                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4264
4265         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4266
4267         return offset;
4268 }
4269
4270 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4271 {
4272         struct bnxt_error_recovery_info *info = bp->recovery_info;
4273         uint32_t reg_base = 0xffffffff;
4274         int i;
4275
4276         /* Only pre-map the monitoring GRC registers using window 2 */
4277         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4278                 uint32_t reg = info->status_regs[i];
4279
4280                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4281                         continue;
4282
4283                 if (reg_base == 0xffffffff)
4284                         reg_base = reg & 0xfffff000;
4285                 if ((reg & 0xfffff000) != reg_base)
4286                         return -ERANGE;
4287
4288                 /* Use mask 0xffc as the Lower 2 bits indicates
4289                  * address space location
4290                  */
4291                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4292                                                 (reg & 0xffc);
4293         }
4294
4295         if (reg_base == 0xffffffff)
4296                 return 0;
4297
4298         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4299                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4300
4301         return 0;
4302 }
4303
4304 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4305 {
4306         struct bnxt_error_recovery_info *info = bp->recovery_info;
4307         uint32_t delay = info->delay_after_reset[index];
4308         uint32_t val = info->reset_reg_val[index];
4309         uint32_t reg = info->reset_reg[index];
4310         uint32_t type, offset;
4311
4312         type = BNXT_FW_STATUS_REG_TYPE(reg);
4313         offset = BNXT_FW_STATUS_REG_OFF(reg);
4314
4315         switch (type) {
4316         case BNXT_FW_STATUS_REG_TYPE_CFG:
4317                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4318                 break;
4319         case BNXT_FW_STATUS_REG_TYPE_GRC:
4320                 offset = bnxt_map_reset_regs(bp, offset);
4321                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4322                 break;
4323         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4324                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4325                 break;
4326         }
4327         /* wait on a specific interval of time until core reset is complete */
4328         if (delay)
4329                 rte_delay_ms(delay);
4330 }
4331
4332 static void bnxt_dev_cleanup(struct bnxt *bp)
4333 {
4334         bnxt_set_hwrm_link_config(bp, false);
4335         bp->link_info->link_up = 0;
4336         if (bp->eth_dev->data->dev_started)
4337                 bnxt_dev_stop_op(bp->eth_dev);
4338
4339         bnxt_uninit_resources(bp, true);
4340 }
4341
4342 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4343 {
4344         struct rte_eth_dev *dev = bp->eth_dev;
4345         struct rte_vlan_filter_conf *vfc;
4346         int vidx, vbit, rc;
4347         uint16_t vlan_id;
4348
4349         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4350                 vfc = &dev->data->vlan_filter_conf;
4351                 vidx = vlan_id / 64;
4352                 vbit = vlan_id % 64;
4353
4354                 /* Each bit corresponds to a VLAN id */
4355                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4356                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4357                         if (rc)
4358                                 return rc;
4359                 }
4360         }
4361
4362         return 0;
4363 }
4364
4365 static int bnxt_restore_mac_filters(struct bnxt *bp)
4366 {
4367         struct rte_eth_dev *dev = bp->eth_dev;
4368         struct rte_eth_dev_info dev_info;
4369         struct rte_ether_addr *addr;
4370         uint64_t pool_mask;
4371         uint32_t pool = 0;
4372         uint16_t i;
4373         int rc;
4374
4375         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4376                 return 0;
4377
4378         rc = bnxt_dev_info_get_op(dev, &dev_info);
4379         if (rc)
4380                 return rc;
4381
4382         /* replay MAC address configuration */
4383         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4384                 addr = &dev->data->mac_addrs[i];
4385
4386                 /* skip zero address */
4387                 if (rte_is_zero_ether_addr(addr))
4388                         continue;
4389
4390                 pool = 0;
4391                 pool_mask = dev->data->mac_pool_sel[i];
4392
4393                 do {
4394                         if (pool_mask & 1ULL) {
4395                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4396                                 if (rc)
4397                                         return rc;
4398                         }
4399                         pool_mask >>= 1;
4400                         pool++;
4401                 } while (pool_mask);
4402         }
4403
4404         return 0;
4405 }
4406
4407 static int bnxt_restore_filters(struct bnxt *bp)
4408 {
4409         struct rte_eth_dev *dev = bp->eth_dev;
4410         int ret = 0;
4411
4412         if (dev->data->all_multicast) {
4413                 ret = bnxt_allmulticast_enable_op(dev);
4414                 if (ret)
4415                         return ret;
4416         }
4417         if (dev->data->promiscuous) {
4418                 ret = bnxt_promiscuous_enable_op(dev);
4419                 if (ret)
4420                         return ret;
4421         }
4422
4423         ret = bnxt_restore_mac_filters(bp);
4424         if (ret)
4425                 return ret;
4426
4427         ret = bnxt_restore_vlan_filters(bp);
4428         /* TODO restore other filters as well */
4429         return ret;
4430 }
4431
4432 static void bnxt_dev_recover(void *arg)
4433 {
4434         struct bnxt *bp = arg;
4435         int timeout = bp->fw_reset_max_msecs;
4436         int rc = 0;
4437
4438         /* Clear Error flag so that device re-init should happen */
4439         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4440
4441         do {
4442                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4443                 if (rc == 0)
4444                         break;
4445                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4446                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4447         } while (rc && timeout);
4448
4449         if (rc) {
4450                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4451                 goto err;
4452         }
4453
4454         rc = bnxt_init_resources(bp, true);
4455         if (rc) {
4456                 PMD_DRV_LOG(ERR,
4457                             "Failed to initialize resources after reset\n");
4458                 goto err;
4459         }
4460         /* clear reset flag as the device is initialized now */
4461         bp->flags &= ~BNXT_FLAG_FW_RESET;
4462
4463         rc = bnxt_dev_start_op(bp->eth_dev);
4464         if (rc) {
4465                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4466                 goto err_start;
4467         }
4468
4469         rc = bnxt_restore_filters(bp);
4470         if (rc)
4471                 goto err_start;
4472
4473         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4474         return;
4475 err_start:
4476         bnxt_dev_stop_op(bp->eth_dev);
4477 err:
4478         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4479         bnxt_uninit_resources(bp, false);
4480         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4481 }
4482
4483 void bnxt_dev_reset_and_resume(void *arg)
4484 {
4485         struct bnxt *bp = arg;
4486         int rc;
4487
4488         bnxt_dev_cleanup(bp);
4489
4490         bnxt_wait_for_device_shutdown(bp);
4491
4492         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4493                                bnxt_dev_recover, (void *)bp);
4494         if (rc)
4495                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4496 }
4497
4498 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4499 {
4500         struct bnxt_error_recovery_info *info = bp->recovery_info;
4501         uint32_t reg = info->status_regs[index];
4502         uint32_t type, offset, val = 0;
4503
4504         type = BNXT_FW_STATUS_REG_TYPE(reg);
4505         offset = BNXT_FW_STATUS_REG_OFF(reg);
4506
4507         switch (type) {
4508         case BNXT_FW_STATUS_REG_TYPE_CFG:
4509                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4510                 break;
4511         case BNXT_FW_STATUS_REG_TYPE_GRC:
4512                 offset = info->mapped_status_regs[index];
4513                 /* FALLTHROUGH */
4514         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4515                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4516                                        offset));
4517                 break;
4518         }
4519
4520         return val;
4521 }
4522
4523 static int bnxt_fw_reset_all(struct bnxt *bp)
4524 {
4525         struct bnxt_error_recovery_info *info = bp->recovery_info;
4526         uint32_t i;
4527         int rc = 0;
4528
4529         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4530                 /* Reset through master function driver */
4531                 for (i = 0; i < info->reg_array_cnt; i++)
4532                         bnxt_write_fw_reset_reg(bp, i);
4533                 /* Wait for time specified by FW after triggering reset */
4534                 rte_delay_ms(info->master_func_wait_period_after_reset);
4535         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4536                 /* Reset with the help of Kong processor */
4537                 rc = bnxt_hwrm_fw_reset(bp);
4538                 if (rc)
4539                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4540         }
4541
4542         return rc;
4543 }
4544
4545 static void bnxt_fw_reset_cb(void *arg)
4546 {
4547         struct bnxt *bp = arg;
4548         struct bnxt_error_recovery_info *info = bp->recovery_info;
4549         int rc = 0;
4550
4551         /* Only Master function can do FW reset */
4552         if (bnxt_is_master_func(bp) &&
4553             bnxt_is_recovery_enabled(bp)) {
4554                 rc = bnxt_fw_reset_all(bp);
4555                 if (rc) {
4556                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4557                         return;
4558                 }
4559         }
4560
4561         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4562          * EXCEPTION_FATAL_ASYNC event to all the functions
4563          * (including MASTER FUNC). After receiving this Async, all the active
4564          * drivers should treat this case as FW initiated recovery
4565          */
4566         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4567                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4568                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4569
4570                 /* To recover from error */
4571                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4572                                   (void *)bp);
4573         }
4574 }
4575
4576 /* Driver should poll FW heartbeat, reset_counter with the frequency
4577  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4578  * When the driver detects heartbeat stop or change in reset_counter,
4579  * it has to trigger a reset to recover from the error condition.
4580  * A “master PF” is the function who will have the privilege to
4581  * initiate the chimp reset. The master PF will be elected by the
4582  * firmware and will be notified through async message.
4583  */
4584 static void bnxt_check_fw_health(void *arg)
4585 {
4586         struct bnxt *bp = arg;
4587         struct bnxt_error_recovery_info *info = bp->recovery_info;
4588         uint32_t val = 0, wait_msec;
4589
4590         if (!info || !bnxt_is_recovery_enabled(bp) ||
4591             is_bnxt_in_error(bp))
4592                 return;
4593
4594         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4595         if (val == info->last_heart_beat)
4596                 goto reset;
4597
4598         info->last_heart_beat = val;
4599
4600         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4601         if (val != info->last_reset_counter)
4602                 goto reset;
4603
4604         info->last_reset_counter = val;
4605
4606         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4607                           bnxt_check_fw_health, (void *)bp);
4608
4609         return;
4610 reset:
4611         /* Stop DMA to/from device */
4612         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4613         bp->flags |= BNXT_FLAG_FW_RESET;
4614
4615         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4616
4617         if (bnxt_is_master_func(bp))
4618                 wait_msec = info->master_func_wait_period;
4619         else
4620                 wait_msec = info->normal_func_wait_period;
4621
4622         rte_eal_alarm_set(US_PER_MS * wait_msec,
4623                           bnxt_fw_reset_cb, (void *)bp);
4624 }
4625
4626 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4627 {
4628         uint32_t polling_freq;
4629
4630         if (!bnxt_is_recovery_enabled(bp))
4631                 return;
4632
4633         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4634                 return;
4635
4636         polling_freq = bp->recovery_info->driver_polling_freq;
4637
4638         rte_eal_alarm_set(US_PER_MS * polling_freq,
4639                           bnxt_check_fw_health, (void *)bp);
4640         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4641 }
4642
4643 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4644 {
4645         if (!bnxt_is_recovery_enabled(bp))
4646                 return;
4647
4648         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4649         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4650 }
4651
4652 static bool bnxt_vf_pciid(uint16_t device_id)
4653 {
4654         switch (device_id) {
4655         case BROADCOM_DEV_ID_57304_VF:
4656         case BROADCOM_DEV_ID_57406_VF:
4657         case BROADCOM_DEV_ID_5731X_VF:
4658         case BROADCOM_DEV_ID_5741X_VF:
4659         case BROADCOM_DEV_ID_57414_VF:
4660         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4661         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4662         case BROADCOM_DEV_ID_58802_VF:
4663         case BROADCOM_DEV_ID_57500_VF1:
4664         case BROADCOM_DEV_ID_57500_VF2:
4665                 /* FALLTHROUGH */
4666                 return true;
4667         default:
4668                 return false;
4669         }
4670 }
4671
4672 static bool bnxt_thor_device(uint16_t device_id)
4673 {
4674         switch (device_id) {
4675         case BROADCOM_DEV_ID_57508:
4676         case BROADCOM_DEV_ID_57504:
4677         case BROADCOM_DEV_ID_57502:
4678         case BROADCOM_DEV_ID_57508_MF1:
4679         case BROADCOM_DEV_ID_57504_MF1:
4680         case BROADCOM_DEV_ID_57502_MF1:
4681         case BROADCOM_DEV_ID_57508_MF2:
4682         case BROADCOM_DEV_ID_57504_MF2:
4683         case BROADCOM_DEV_ID_57502_MF2:
4684         case BROADCOM_DEV_ID_57500_VF1:
4685         case BROADCOM_DEV_ID_57500_VF2:
4686                 /* FALLTHROUGH */
4687                 return true;
4688         default:
4689                 return false;
4690         }
4691 }
4692
4693 bool bnxt_stratus_device(struct bnxt *bp)
4694 {
4695         uint16_t device_id = bp->pdev->id.device_id;
4696
4697         switch (device_id) {
4698         case BROADCOM_DEV_ID_STRATUS_NIC:
4699         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4700         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4701                 /* FALLTHROUGH */
4702                 return true;
4703         default:
4704                 return false;
4705         }
4706 }
4707
4708 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4709 {
4710         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4711         struct bnxt *bp = eth_dev->data->dev_private;
4712
4713         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4714         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4715         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4716         if (!bp->bar0 || !bp->doorbell_base) {
4717                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4718                 return -ENODEV;
4719         }
4720
4721         bp->eth_dev = eth_dev;
4722         bp->pdev = pci_dev;
4723
4724         return 0;
4725 }
4726
4727 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4728                                   struct bnxt_ctx_pg_info *ctx_pg,
4729                                   uint32_t mem_size,
4730                                   const char *suffix,
4731                                   uint16_t idx)
4732 {
4733         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4734         const struct rte_memzone *mz = NULL;
4735         char mz_name[RTE_MEMZONE_NAMESIZE];
4736         rte_iova_t mz_phys_addr;
4737         uint64_t valid_bits = 0;
4738         uint32_t sz;
4739         int i;
4740
4741         if (!mem_size)
4742                 return 0;
4743
4744         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4745                          BNXT_PAGE_SIZE;
4746         rmem->page_size = BNXT_PAGE_SIZE;
4747         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4748         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4749         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4750
4751         valid_bits = PTU_PTE_VALID;
4752
4753         if (rmem->nr_pages > 1) {
4754                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4755                          "bnxt_ctx_pg_tbl%s_%x_%d",
4756                          suffix, idx, bp->eth_dev->data->port_id);
4757                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4758                 mz = rte_memzone_lookup(mz_name);
4759                 if (!mz) {
4760                         mz = rte_memzone_reserve_aligned(mz_name,
4761                                                 rmem->nr_pages * 8,
4762                                                 SOCKET_ID_ANY,
4763                                                 RTE_MEMZONE_2MB |
4764                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4765                                                 RTE_MEMZONE_IOVA_CONTIG,
4766                                                 BNXT_PAGE_SIZE);
4767                         if (mz == NULL)
4768                                 return -ENOMEM;
4769                 }
4770
4771                 memset(mz->addr, 0, mz->len);
4772                 mz_phys_addr = mz->iova;
4773
4774                 rmem->pg_tbl = mz->addr;
4775                 rmem->pg_tbl_map = mz_phys_addr;
4776                 rmem->pg_tbl_mz = mz;
4777         }
4778
4779         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4780                  suffix, idx, bp->eth_dev->data->port_id);
4781         mz = rte_memzone_lookup(mz_name);
4782         if (!mz) {
4783                 mz = rte_memzone_reserve_aligned(mz_name,
4784                                                  mem_size,
4785                                                  SOCKET_ID_ANY,
4786                                                  RTE_MEMZONE_1GB |
4787                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4788                                                  RTE_MEMZONE_IOVA_CONTIG,
4789                                                  BNXT_PAGE_SIZE);
4790                 if (mz == NULL)
4791                         return -ENOMEM;
4792         }
4793
4794         memset(mz->addr, 0, mz->len);
4795         mz_phys_addr = mz->iova;
4796
4797         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4798                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4799                 rmem->dma_arr[i] = mz_phys_addr + sz;
4800
4801                 if (rmem->nr_pages > 1) {
4802                         if (i == rmem->nr_pages - 2 &&
4803                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4804                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4805                         else if (i == rmem->nr_pages - 1 &&
4806                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4807                                 valid_bits |= PTU_PTE_LAST;
4808
4809                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4810                                                            valid_bits);
4811                 }
4812         }
4813
4814         rmem->mz = mz;
4815         if (rmem->vmem_size)
4816                 rmem->vmem = (void **)mz->addr;
4817         rmem->dma_arr[0] = mz_phys_addr;
4818         return 0;
4819 }
4820
4821 static void bnxt_free_ctx_mem(struct bnxt *bp)
4822 {
4823         int i;
4824
4825         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4826                 return;
4827
4828         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4829         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4830         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4831         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4832         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4833         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4834         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4835         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4836         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4837         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4838         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4839
4840         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4841                 if (bp->ctx->tqm_mem[i])
4842                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4843         }
4844
4845         rte_free(bp->ctx);
4846         bp->ctx = NULL;
4847 }
4848
4849 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4850
4851 #define min_t(type, x, y) ({                    \
4852         type __min1 = (x);                      \
4853         type __min2 = (y);                      \
4854         __min1 < __min2 ? __min1 : __min2; })
4855
4856 #define max_t(type, x, y) ({                    \
4857         type __max1 = (x);                      \
4858         type __max2 = (y);                      \
4859         __max1 > __max2 ? __max1 : __max2; })
4860
4861 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4862
4863 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4864 {
4865         struct bnxt_ctx_pg_info *ctx_pg;
4866         struct bnxt_ctx_mem_info *ctx;
4867         uint32_t mem_size, ena, entries;
4868         uint32_t entries_sp, min;
4869         int i, rc;
4870
4871         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4872         if (rc) {
4873                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4874                 return rc;
4875         }
4876         ctx = bp->ctx;
4877         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4878                 return 0;
4879
4880         ctx_pg = &ctx->qp_mem;
4881         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4882         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4883         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4884         if (rc)
4885                 return rc;
4886
4887         ctx_pg = &ctx->srq_mem;
4888         ctx_pg->entries = ctx->srq_max_l2_entries;
4889         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4890         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4891         if (rc)
4892                 return rc;
4893
4894         ctx_pg = &ctx->cq_mem;
4895         ctx_pg->entries = ctx->cq_max_l2_entries;
4896         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4897         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4898         if (rc)
4899                 return rc;
4900
4901         ctx_pg = &ctx->vnic_mem;
4902         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4903                 ctx->vnic_max_ring_table_entries;
4904         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4905         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4906         if (rc)
4907                 return rc;
4908
4909         ctx_pg = &ctx->stat_mem;
4910         ctx_pg->entries = ctx->stat_max_entries;
4911         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4912         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4913         if (rc)
4914                 return rc;
4915
4916         min = ctx->tqm_min_entries_per_ring;
4917
4918         entries_sp = ctx->qp_max_l2_entries +
4919                      ctx->vnic_max_vnic_entries +
4920                      2 * ctx->qp_min_qp1_entries + min;
4921         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4922
4923         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4924         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4925         entries = clamp_t(uint32_t, entries, min,
4926                           ctx->tqm_max_entries_per_ring);
4927         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4928                 ctx_pg = ctx->tqm_mem[i];
4929                 ctx_pg->entries = i ? entries : entries_sp;
4930                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4931                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4932                 if (rc)
4933                         return rc;
4934                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4935         }
4936
4937         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4938         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4939         if (rc)
4940                 PMD_DRV_LOG(ERR,
4941                             "Failed to configure context mem: rc = %d\n", rc);
4942         else
4943                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4944
4945         return rc;
4946 }
4947
4948 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4949 {
4950         struct rte_pci_device *pci_dev = bp->pdev;
4951         char mz_name[RTE_MEMZONE_NAMESIZE];
4952         const struct rte_memzone *mz = NULL;
4953         uint32_t total_alloc_len;
4954         rte_iova_t mz_phys_addr;
4955
4956         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4957                 return 0;
4958
4959         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4960                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4961                  pci_dev->addr.bus, pci_dev->addr.devid,
4962                  pci_dev->addr.function, "rx_port_stats");
4963         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4964         mz = rte_memzone_lookup(mz_name);
4965         total_alloc_len =
4966                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4967                                        sizeof(struct rx_port_stats_ext) + 512);
4968         if (!mz) {
4969                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4970                                          SOCKET_ID_ANY,
4971                                          RTE_MEMZONE_2MB |
4972                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4973                                          RTE_MEMZONE_IOVA_CONTIG);
4974                 if (mz == NULL)
4975                         return -ENOMEM;
4976         }
4977         memset(mz->addr, 0, mz->len);
4978         mz_phys_addr = mz->iova;
4979
4980         bp->rx_mem_zone = (const void *)mz;
4981         bp->hw_rx_port_stats = mz->addr;
4982         bp->hw_rx_port_stats_map = mz_phys_addr;
4983
4984         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4985                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4986                  pci_dev->addr.bus, pci_dev->addr.devid,
4987                  pci_dev->addr.function, "tx_port_stats");
4988         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4989         mz = rte_memzone_lookup(mz_name);
4990         total_alloc_len =
4991                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4992                                        sizeof(struct tx_port_stats_ext) + 512);
4993         if (!mz) {
4994                 mz = rte_memzone_reserve(mz_name,
4995                                          total_alloc_len,
4996                                          SOCKET_ID_ANY,
4997                                          RTE_MEMZONE_2MB |
4998                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4999                                          RTE_MEMZONE_IOVA_CONTIG);
5000                 if (mz == NULL)
5001                         return -ENOMEM;
5002         }
5003         memset(mz->addr, 0, mz->len);
5004         mz_phys_addr = mz->iova;
5005
5006         bp->tx_mem_zone = (const void *)mz;
5007         bp->hw_tx_port_stats = mz->addr;
5008         bp->hw_tx_port_stats_map = mz_phys_addr;
5009         bp->flags |= BNXT_FLAG_PORT_STATS;
5010
5011         /* Display extended statistics if FW supports it */
5012         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5013             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5014             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5015                 return 0;
5016
5017         bp->hw_rx_port_stats_ext = (void *)
5018                 ((uint8_t *)bp->hw_rx_port_stats +
5019                  sizeof(struct rx_port_stats));
5020         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5021                 sizeof(struct rx_port_stats);
5022         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5023
5024         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5025             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5026                 bp->hw_tx_port_stats_ext = (void *)
5027                         ((uint8_t *)bp->hw_tx_port_stats +
5028                          sizeof(struct tx_port_stats));
5029                 bp->hw_tx_port_stats_ext_map =
5030                         bp->hw_tx_port_stats_map +
5031                         sizeof(struct tx_port_stats);
5032                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5033         }
5034
5035         return 0;
5036 }
5037
5038 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5039 {
5040         struct bnxt *bp = eth_dev->data->dev_private;
5041         int rc = 0;
5042
5043         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5044                                                RTE_ETHER_ADDR_LEN *
5045                                                bp->max_l2_ctx,
5046                                                0);
5047         if (eth_dev->data->mac_addrs == NULL) {
5048                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5049                 return -ENOMEM;
5050         }
5051
5052         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5053                 if (BNXT_PF(bp))
5054                         return -EINVAL;
5055
5056                 /* Generate a random MAC address, if none was assigned by PF */
5057                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5058                 bnxt_eth_hw_addr_random(bp->mac_addr);
5059                 PMD_DRV_LOG(INFO,
5060                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5061                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5062                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5063
5064                 rc = bnxt_hwrm_set_mac(bp);
5065                 if (rc)
5066                         return rc;
5067         }
5068
5069         /* Copy the permanent MAC from the FUNC_QCAPS response */
5070         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5071
5072         return rc;
5073 }
5074
5075 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5076 {
5077         int rc = 0;
5078
5079         /* MAC is already configured in FW */
5080         if (BNXT_HAS_DFLT_MAC_SET(bp))
5081                 return 0;
5082
5083         /* Restore the old MAC configured */
5084         rc = bnxt_hwrm_set_mac(bp);
5085         if (rc)
5086                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5087
5088         return rc;
5089 }
5090
5091 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5092 {
5093         if (!BNXT_PF(bp))
5094                 return;
5095
5096 #define ALLOW_FUNC(x)   \
5097         { \
5098                 uint32_t arg = (x); \
5099                 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5100                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5101         }
5102
5103         /* Forward all requests if firmware is new enough */
5104         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5105              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5106             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5107                 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5108         } else {
5109                 PMD_DRV_LOG(WARNING,
5110                             "Firmware too old for VF mailbox functionality\n");
5111                 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5112         }
5113
5114         /*
5115          * The following are used for driver cleanup. If we disallow these,
5116          * VF drivers can't clean up cleanly.
5117          */
5118         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5119         ALLOW_FUNC(HWRM_VNIC_FREE);
5120         ALLOW_FUNC(HWRM_RING_FREE);
5121         ALLOW_FUNC(HWRM_RING_GRP_FREE);
5122         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5123         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5124         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5125         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5126         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5127 }
5128
5129 uint16_t
5130 bnxt_get_svif(uint16_t port_id, bool func_svif,
5131               enum bnxt_ulp_intf_type type)
5132 {
5133         struct rte_eth_dev *eth_dev;
5134         struct bnxt *bp;
5135
5136         eth_dev = &rte_eth_devices[port_id];
5137         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5138                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5139                 if (!vfr)
5140                         return 0;
5141
5142                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5143                         return vfr->svif;
5144
5145                 eth_dev = vfr->parent_dev;
5146         }
5147
5148         bp = eth_dev->data->dev_private;
5149
5150         return func_svif ? bp->func_svif : bp->port_svif;
5151 }
5152
5153 uint16_t
5154 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5155 {
5156         struct rte_eth_dev *eth_dev;
5157         struct bnxt_vnic_info *vnic;
5158         struct bnxt *bp;
5159
5160         eth_dev = &rte_eth_devices[port];
5161         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5162                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5163                 if (!vfr)
5164                         return 0;
5165
5166                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5167                         return vfr->dflt_vnic_id;
5168
5169                 eth_dev = vfr->parent_dev;
5170         }
5171
5172         bp = eth_dev->data->dev_private;
5173
5174         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5175
5176         return vnic->fw_vnic_id;
5177 }
5178
5179 uint16_t
5180 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5181 {
5182         struct rte_eth_dev *eth_dev;
5183         struct bnxt *bp;
5184
5185         eth_dev = &rte_eth_devices[port];
5186         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5187                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5188                 if (!vfr)
5189                         return 0;
5190
5191                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5192                         return vfr->fw_fid;
5193
5194                 eth_dev = vfr->parent_dev;
5195         }
5196
5197         bp = eth_dev->data->dev_private;
5198
5199         return bp->fw_fid;
5200 }
5201
5202 enum bnxt_ulp_intf_type
5203 bnxt_get_interface_type(uint16_t port)
5204 {
5205         struct rte_eth_dev *eth_dev;
5206         struct bnxt *bp;
5207
5208         eth_dev = &rte_eth_devices[port];
5209         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5210                 return BNXT_ULP_INTF_TYPE_VF_REP;
5211
5212         bp = eth_dev->data->dev_private;
5213         if (BNXT_PF(bp))
5214                 return BNXT_ULP_INTF_TYPE_PF;
5215         else if (BNXT_VF_IS_TRUSTED(bp))
5216                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5217         else if (BNXT_VF(bp))
5218                 return BNXT_ULP_INTF_TYPE_VF;
5219
5220         return BNXT_ULP_INTF_TYPE_INVALID;
5221 }
5222
5223 uint16_t
5224 bnxt_get_phy_port_id(uint16_t port_id)
5225 {
5226         struct bnxt_vf_representor *vfr;
5227         struct rte_eth_dev *eth_dev;
5228         struct bnxt *bp;
5229
5230         eth_dev = &rte_eth_devices[port_id];
5231         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5232                 vfr = eth_dev->data->dev_private;
5233                 if (!vfr)
5234                         return 0;
5235
5236                 eth_dev = vfr->parent_dev;
5237         }
5238
5239         bp = eth_dev->data->dev_private;
5240
5241         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5242 }
5243
5244 uint16_t
5245 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5246 {
5247         struct rte_eth_dev *eth_dev;
5248         struct bnxt *bp;
5249
5250         eth_dev = &rte_eth_devices[port_id];
5251         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5252                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5253                 if (!vfr)
5254                         return 0;
5255
5256                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5257                         return vfr->fw_fid - 1;
5258
5259                 eth_dev = vfr->parent_dev;
5260         }
5261
5262         bp = eth_dev->data->dev_private;
5263
5264         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5265 }
5266
5267 uint16_t
5268 bnxt_get_vport(uint16_t port_id)
5269 {
5270         return (1 << bnxt_get_phy_port_id(port_id));
5271 }
5272
5273 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5274 {
5275         struct bnxt_error_recovery_info *info = bp->recovery_info;
5276
5277         if (info) {
5278                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5279                         memset(info, 0, sizeof(*info));
5280                 return;
5281         }
5282
5283         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5284                 return;
5285
5286         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5287                            sizeof(*info), 0);
5288         if (!info)
5289                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5290
5291         bp->recovery_info = info;
5292 }
5293
5294 static void bnxt_check_fw_status(struct bnxt *bp)
5295 {
5296         uint32_t fw_status;
5297
5298         if (!(bp->recovery_info &&
5299               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5300                 return;
5301
5302         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5303         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5304                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5305                             fw_status);
5306 }
5307
5308 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5309 {
5310         struct bnxt_error_recovery_info *info = bp->recovery_info;
5311         uint32_t status_loc;
5312         uint32_t sig_ver;
5313
5314         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5315                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5316         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5317                                    BNXT_GRCP_WINDOW_2_BASE +
5318                                    offsetof(struct hcomm_status,
5319                                             sig_ver)));
5320         /* If the signature is absent, then FW does not support this feature */
5321         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5322             HCOMM_STATUS_SIGNATURE_VAL)
5323                 return 0;
5324
5325         if (!info) {
5326                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5327                                    sizeof(*info), 0);
5328                 if (!info)
5329                         return -ENOMEM;
5330                 bp->recovery_info = info;
5331         } else {
5332                 memset(info, 0, sizeof(*info));
5333         }
5334
5335         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5336                                       BNXT_GRCP_WINDOW_2_BASE +
5337                                       offsetof(struct hcomm_status,
5338                                                fw_status_loc)));
5339
5340         /* Only pre-map the FW health status GRC register */
5341         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5342                 return 0;
5343
5344         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5345         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5346                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5347
5348         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5349                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5350
5351         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5352
5353         return 0;
5354 }
5355
5356 static int bnxt_init_fw(struct bnxt *bp)
5357 {
5358         uint16_t mtu;
5359         int rc = 0;
5360
5361         bp->fw_cap = 0;
5362
5363         rc = bnxt_map_hcomm_fw_status_reg(bp);
5364         if (rc)
5365                 return rc;
5366
5367         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5368         if (rc) {
5369                 bnxt_check_fw_status(bp);
5370                 return rc;
5371         }
5372
5373         rc = bnxt_hwrm_func_reset(bp);
5374         if (rc)
5375                 return -EIO;
5376
5377         rc = bnxt_hwrm_vnic_qcaps(bp);
5378         if (rc)
5379                 return rc;
5380
5381         rc = bnxt_hwrm_queue_qportcfg(bp);
5382         if (rc)
5383                 return rc;
5384
5385         /* Get the MAX capabilities for this function.
5386          * This function also allocates context memory for TQM rings and
5387          * informs the firmware about this allocated backing store memory.
5388          */
5389         rc = bnxt_hwrm_func_qcaps(bp);
5390         if (rc)
5391                 return rc;
5392
5393         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5394         if (rc)
5395                 return rc;
5396
5397         bnxt_hwrm_port_mac_qcfg(bp);
5398
5399         bnxt_hwrm_parent_pf_qcfg(bp);
5400
5401         bnxt_hwrm_port_phy_qcaps(bp);
5402
5403         bnxt_alloc_error_recovery_info(bp);
5404         /* Get the adapter error recovery support info */
5405         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5406         if (rc)
5407                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5408
5409         bnxt_hwrm_port_led_qcaps(bp);
5410
5411         return 0;
5412 }
5413
5414 static int
5415 bnxt_init_locks(struct bnxt *bp)
5416 {
5417         int err;
5418
5419         err = pthread_mutex_init(&bp->flow_lock, NULL);
5420         if (err) {
5421                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5422                 return err;
5423         }
5424
5425         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5426         if (err)
5427                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5428         return err;
5429 }
5430
5431 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5432 {
5433         int rc = 0;
5434
5435         rc = bnxt_init_fw(bp);
5436         if (rc)
5437                 return rc;
5438
5439         if (!reconfig_dev) {
5440                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5441                 if (rc)
5442                         return rc;
5443         } else {
5444                 rc = bnxt_restore_dflt_mac(bp);
5445                 if (rc)
5446                         return rc;
5447         }
5448
5449         bnxt_config_vf_req_fwd(bp);
5450
5451         rc = bnxt_hwrm_func_driver_register(bp);
5452         if (rc) {
5453                 PMD_DRV_LOG(ERR, "Failed to register driver");
5454                 return -EBUSY;
5455         }
5456
5457         if (BNXT_PF(bp)) {
5458                 if (bp->pdev->max_vfs) {
5459                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5460                         if (rc) {
5461                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5462                                 return rc;
5463                         }
5464                 } else {
5465                         rc = bnxt_hwrm_allocate_pf_only(bp);
5466                         if (rc) {
5467                                 PMD_DRV_LOG(ERR,
5468                                             "Failed to allocate PF resources");
5469                                 return rc;
5470                         }
5471                 }
5472         }
5473
5474         rc = bnxt_alloc_mem(bp, reconfig_dev);
5475         if (rc)
5476                 return rc;
5477
5478         rc = bnxt_setup_int(bp);
5479         if (rc)
5480                 return rc;
5481
5482         rc = bnxt_request_int(bp);
5483         if (rc)
5484                 return rc;
5485
5486         rc = bnxt_init_ctx_mem(bp);
5487         if (rc) {
5488                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5489                 return rc;
5490         }
5491
5492         rc = bnxt_init_locks(bp);
5493         if (rc)
5494                 return rc;
5495
5496         return 0;
5497 }
5498
5499 static int
5500 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5501                           const char *value, void *opaque_arg)
5502 {
5503         struct bnxt *bp = opaque_arg;
5504         unsigned long truflow;
5505         char *end = NULL;
5506
5507         if (!value || !opaque_arg) {
5508                 PMD_DRV_LOG(ERR,
5509                             "Invalid parameter passed to truflow devargs.\n");
5510                 return -EINVAL;
5511         }
5512
5513         truflow = strtoul(value, &end, 10);
5514         if (end == NULL || *end != '\0' ||
5515             (truflow == ULONG_MAX && errno == ERANGE)) {
5516                 PMD_DRV_LOG(ERR,
5517                             "Invalid parameter passed to truflow devargs.\n");
5518                 return -EINVAL;
5519         }
5520
5521         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5522                 PMD_DRV_LOG(ERR,
5523                             "Invalid value passed to truflow devargs.\n");
5524                 return -EINVAL;
5525         }
5526
5527         bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5528         if (BNXT_TRUFLOW_EN(bp))
5529                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5530
5531         return 0;
5532 }
5533
5534 static int
5535 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5536                              const char *value, void *opaque_arg)
5537 {
5538         struct bnxt *bp = opaque_arg;
5539         unsigned long flow_xstat;
5540         char *end = NULL;
5541
5542         if (!value || !opaque_arg) {
5543                 PMD_DRV_LOG(ERR,
5544                             "Invalid parameter passed to flow_xstat devarg.\n");
5545                 return -EINVAL;
5546         }
5547
5548         flow_xstat = strtoul(value, &end, 10);
5549         if (end == NULL || *end != '\0' ||
5550             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5551                 PMD_DRV_LOG(ERR,
5552                             "Invalid parameter passed to flow_xstat devarg.\n");
5553                 return -EINVAL;
5554         }
5555
5556         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5557                 PMD_DRV_LOG(ERR,
5558                             "Invalid value passed to flow_xstat devarg.\n");
5559                 return -EINVAL;
5560         }
5561
5562         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5563         if (BNXT_FLOW_XSTATS_EN(bp))
5564                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5565
5566         return 0;
5567 }
5568
5569 static int
5570 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5571                                         const char *value, void *opaque_arg)
5572 {
5573         struct bnxt *bp = opaque_arg;
5574         unsigned long max_num_kflows;
5575         char *end = NULL;
5576
5577         if (!value || !opaque_arg) {
5578                 PMD_DRV_LOG(ERR,
5579                         "Invalid parameter passed to max_num_kflows devarg.\n");
5580                 return -EINVAL;
5581         }
5582
5583         max_num_kflows = strtoul(value, &end, 10);
5584         if (end == NULL || *end != '\0' ||
5585                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5586                 PMD_DRV_LOG(ERR,
5587                         "Invalid parameter passed to max_num_kflows devarg.\n");
5588                 return -EINVAL;
5589         }
5590
5591         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5592                 PMD_DRV_LOG(ERR,
5593                         "Invalid value passed to max_num_kflows devarg.\n");
5594                 return -EINVAL;
5595         }
5596
5597         bp->max_num_kflows = max_num_kflows;
5598         if (bp->max_num_kflows)
5599                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5600                                 max_num_kflows);
5601
5602         return 0;
5603 }
5604
5605 static void
5606 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5607 {
5608         struct rte_kvargs *kvlist;
5609
5610         if (devargs == NULL)
5611                 return;
5612
5613         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5614         if (kvlist == NULL)
5615                 return;
5616
5617         /*
5618          * Handler for "truflow" devarg.
5619          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5620          */
5621         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5622                            bnxt_parse_devarg_truflow, bp);
5623
5624         /*
5625          * Handler for "flow_xstat" devarg.
5626          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5627          */
5628         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5629                            bnxt_parse_devarg_flow_xstat, bp);
5630
5631         /*
5632          * Handler for "max_num_kflows" devarg.
5633          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5634          */
5635         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5636                            bnxt_parse_devarg_max_num_kflows, bp);
5637
5638         rte_kvargs_free(kvlist);
5639 }
5640
5641 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5642 {
5643         int rc = 0;
5644
5645         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5646                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5647                 if (rc)
5648                         PMD_DRV_LOG(ERR,
5649                                     "Failed to alloc switch domain: %d\n", rc);
5650                 else
5651                         PMD_DRV_LOG(INFO,
5652                                     "Switch domain allocated %d\n",
5653                                     bp->switch_domain_id);
5654         }
5655
5656         return rc;
5657 }
5658
5659 static int
5660 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5661 {
5662         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5663         static int version_printed;
5664         struct bnxt *bp;
5665         int rc;
5666
5667         if (version_printed++ == 0)
5668                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5669
5670         eth_dev->dev_ops = &bnxt_dev_ops;
5671         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5672         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5673
5674         /*
5675          * For secondary processes, we don't initialise any further
5676          * as primary has already done this work.
5677          */
5678         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5679                 return 0;
5680
5681         rte_eth_copy_pci_info(eth_dev, pci_dev);
5682
5683         bp = eth_dev->data->dev_private;
5684
5685         /* Parse dev arguments passed on when starting the DPDK application. */
5686         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5687
5688         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5689
5690         if (bnxt_vf_pciid(pci_dev->id.device_id))
5691                 bp->flags |= BNXT_FLAG_VF;
5692
5693         if (bnxt_thor_device(pci_dev->id.device_id))
5694                 bp->flags |= BNXT_FLAG_THOR_CHIP;
5695
5696         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5697             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5698             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5699             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5700                 bp->flags |= BNXT_FLAG_STINGRAY;
5701
5702         rc = bnxt_init_board(eth_dev);
5703         if (rc) {
5704                 PMD_DRV_LOG(ERR,
5705                             "Failed to initialize board rc: %x\n", rc);
5706                 return rc;
5707         }
5708
5709         rc = bnxt_alloc_pf_info(bp);
5710         if (rc)
5711                 goto error_free;
5712
5713         rc = bnxt_alloc_link_info(bp);
5714         if (rc)
5715                 goto error_free;
5716
5717         rc = bnxt_alloc_parent_info(bp);
5718         if (rc)
5719                 goto error_free;
5720
5721         rc = bnxt_alloc_hwrm_resources(bp);
5722         if (rc) {
5723                 PMD_DRV_LOG(ERR,
5724                             "Failed to allocate hwrm resource rc: %x\n", rc);
5725                 goto error_free;
5726         }
5727         rc = bnxt_alloc_leds_info(bp);
5728         if (rc)
5729                 goto error_free;
5730
5731         rc = bnxt_alloc_cos_queues(bp);
5732         if (rc)
5733                 goto error_free;
5734
5735         rc = bnxt_init_resources(bp, false);
5736         if (rc)
5737                 goto error_free;
5738
5739         rc = bnxt_alloc_stats_mem(bp);
5740         if (rc)
5741                 goto error_free;
5742
5743         bnxt_alloc_switch_domain(bp);
5744
5745         /* Pass the information to the rte_eth_dev_close() that it should also
5746          * release the private port resources.
5747          */
5748         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5749
5750         PMD_DRV_LOG(INFO,
5751                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5752                     pci_dev->mem_resource[0].phys_addr,
5753                     pci_dev->mem_resource[0].addr);
5754
5755         return 0;
5756
5757 error_free:
5758         bnxt_dev_uninit(eth_dev);
5759         return rc;
5760 }
5761
5762
5763 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5764 {
5765         if (!ctx)
5766                 return;
5767
5768         if (ctx->va)
5769                 rte_free(ctx->va);
5770
5771         ctx->va = NULL;
5772         ctx->dma = RTE_BAD_IOVA;
5773         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5774 }
5775
5776 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5777 {
5778         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5779                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5780                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5781                                   bp->flow_stat->max_fc,
5782                                   false);
5783
5784         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5785                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5786                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5787                                   bp->flow_stat->max_fc,
5788                                   false);
5789
5790         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5791                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5792         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5793
5794         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5795                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5796         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5797
5798         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5799                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5800         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5801
5802         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5803                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5804         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5805 }
5806
5807 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5808 {
5809         bnxt_unregister_fc_ctx_mem(bp);
5810
5811         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5812         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5813         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5814         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5815 }
5816
5817 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5818 {
5819         if (BNXT_FLOW_XSTATS_EN(bp))
5820                 bnxt_uninit_fc_ctx_mem(bp);
5821 }
5822
5823 static void
5824 bnxt_free_error_recovery_info(struct bnxt *bp)
5825 {
5826         rte_free(bp->recovery_info);
5827         bp->recovery_info = NULL;
5828         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5829 }
5830
5831 static void
5832 bnxt_uninit_locks(struct bnxt *bp)
5833 {
5834         pthread_mutex_destroy(&bp->flow_lock);
5835         pthread_mutex_destroy(&bp->def_cp_lock);
5836         if (bp->rep_info)
5837                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5838 }
5839
5840 static int
5841 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5842 {
5843         int rc;
5844
5845         bnxt_free_int(bp);
5846         bnxt_free_mem(bp, reconfig_dev);
5847         bnxt_hwrm_func_buf_unrgtr(bp);
5848         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5849         bp->flags &= ~BNXT_FLAG_REGISTERED;
5850         bnxt_free_ctx_mem(bp);
5851         if (!reconfig_dev) {
5852                 bnxt_free_hwrm_resources(bp);
5853                 bnxt_free_error_recovery_info(bp);
5854         }
5855
5856         bnxt_uninit_ctx_mem(bp);
5857
5858         bnxt_uninit_locks(bp);
5859         bnxt_free_flow_stats_info(bp);
5860         bnxt_free_rep_info(bp);
5861         rte_free(bp->ptp_cfg);
5862         bp->ptp_cfg = NULL;
5863         return rc;
5864 }
5865
5866 static int
5867 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5868 {
5869         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5870                 return -EPERM;
5871
5872         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5873
5874         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5875                 bnxt_dev_close_op(eth_dev);
5876
5877         return 0;
5878 }
5879
5880 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5881 {
5882         struct bnxt *bp = eth_dev->data->dev_private;
5883         struct rte_eth_dev *vf_rep_eth_dev;
5884         int ret = 0, i;
5885
5886         if (!bp)
5887                 return -EINVAL;
5888
5889         for (i = 0; i < bp->num_reps; i++) {
5890                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5891                 if (!vf_rep_eth_dev)
5892                         continue;
5893                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit);
5894         }
5895         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5896
5897         return ret;
5898 }
5899
5900 static void bnxt_free_rep_info(struct bnxt *bp)
5901 {
5902         rte_free(bp->rep_info);
5903         bp->rep_info = NULL;
5904         rte_free(bp->cfa_code_map);
5905         bp->cfa_code_map = NULL;
5906 }
5907
5908 static int bnxt_init_rep_info(struct bnxt *bp)
5909 {
5910         int i = 0, rc;
5911
5912         if (bp->rep_info)
5913                 return 0;
5914
5915         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5916                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5917                                    0);
5918         if (!bp->rep_info) {
5919                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5920                 return -ENOMEM;
5921         }
5922         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5923                                        sizeof(*bp->cfa_code_map) *
5924                                        BNXT_MAX_CFA_CODE, 0);
5925         if (!bp->cfa_code_map) {
5926                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5927                 bnxt_free_rep_info(bp);
5928                 return -ENOMEM;
5929         }
5930
5931         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5932                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5933
5934         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5935         if (rc) {
5936                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5937                 bnxt_free_rep_info(bp);
5938                 return rc;
5939         }
5940         return rc;
5941 }
5942
5943 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5944                                struct rte_eth_devargs eth_da,
5945                                struct rte_eth_dev *backing_eth_dev)
5946 {
5947         struct rte_eth_dev *vf_rep_eth_dev;
5948         char name[RTE_ETH_NAME_MAX_LEN];
5949         struct bnxt *backing_bp;
5950         uint16_t num_rep;
5951         int i, ret = 0;
5952
5953         num_rep = eth_da.nb_representor_ports;
5954         if (num_rep > BNXT_MAX_VF_REPS) {
5955                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5956                             num_rep, BNXT_MAX_VF_REPS);
5957                 return -EINVAL;
5958         }
5959
5960         if (num_rep > RTE_MAX_ETHPORTS) {
5961                 PMD_DRV_LOG(ERR,
5962                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5963                             num_rep, RTE_MAX_ETHPORTS);
5964                 return -EINVAL;
5965         }
5966
5967         backing_bp = backing_eth_dev->data->dev_private;
5968
5969         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5970                 PMD_DRV_LOG(ERR,
5971                             "Not a PF or trusted VF. No Representor support\n");
5972                 /* Returning an error is not an option.
5973                  * Applications are not handling this correctly
5974                  */
5975                 return 0;
5976         }
5977
5978         if (bnxt_init_rep_info(backing_bp))
5979                 return 0;
5980
5981         for (i = 0; i < num_rep; i++) {
5982                 struct bnxt_vf_representor representor = {
5983                         .vf_id = eth_da.representor_ports[i],
5984                         .switch_domain_id = backing_bp->switch_domain_id,
5985                         .parent_dev = backing_eth_dev
5986                 };
5987
5988                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5989                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5990                                     representor.vf_id, BNXT_MAX_VF_REPS);
5991                         continue;
5992                 }
5993
5994                 /* representor port net_bdf_port */
5995                 snprintf(name, sizeof(name), "net_%s_representor_%d",
5996                          pci_dev->device.name, eth_da.representor_ports[i]);
5997
5998                 ret = rte_eth_dev_create(&pci_dev->device, name,
5999                                          sizeof(struct bnxt_vf_representor),
6000                                          NULL, NULL,
6001                                          bnxt_vf_representor_init,
6002                                          &representor);
6003
6004                 if (!ret) {
6005                         vf_rep_eth_dev = rte_eth_dev_allocated(name);
6006                         if (!vf_rep_eth_dev) {
6007                                 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6008                                             " for VF-Rep: %s.", name);
6009                                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6010                                 ret = -ENODEV;
6011                                 return ret;
6012                         }
6013                         backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6014                                 vf_rep_eth_dev;
6015                         backing_bp->num_reps++;
6016                 } else {
6017                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6018                                     "representor %s.", name);
6019                         bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6020                 }
6021         }
6022
6023         return ret;
6024 }
6025
6026 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6027                           struct rte_pci_device *pci_dev)
6028 {
6029         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6030         struct rte_eth_dev *backing_eth_dev;
6031         uint16_t num_rep;
6032         int ret = 0;
6033
6034         if (pci_dev->device.devargs) {
6035                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6036                                             &eth_da);
6037                 if (ret)
6038                         return ret;
6039         }
6040
6041         num_rep = eth_da.nb_representor_ports;
6042         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6043                     num_rep);
6044
6045         /* We could come here after first level of probe is already invoked
6046          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6047          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6048          */
6049         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6050         if (backing_eth_dev == NULL) {
6051                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6052                                          sizeof(struct bnxt),
6053                                          eth_dev_pci_specific_init, pci_dev,
6054                                          bnxt_dev_init, NULL);
6055
6056                 if (ret || !num_rep)
6057                         return ret;
6058
6059                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6060         }
6061
6062         /* probe representor ports now */
6063         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
6064
6065         return ret;
6066 }
6067
6068 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6069 {
6070         struct rte_eth_dev *eth_dev;
6071
6072         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6073         if (!eth_dev)
6074                 return 0; /* Invoked typically only by OVS-DPDK, by the
6075                            * time it comes here the eth_dev is already
6076                            * deleted by rte_eth_dev_close(), so returning
6077                            * +ve value will at least help in proper cleanup
6078                            */
6079
6080         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6081                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6082                         return rte_eth_dev_destroy(eth_dev,
6083                                                    bnxt_vf_representor_uninit);
6084                 else
6085                         return rte_eth_dev_destroy(eth_dev,
6086                                                    bnxt_dev_uninit);
6087         } else {
6088                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6089         }
6090 }
6091
6092 static struct rte_pci_driver bnxt_rte_pmd = {
6093         .id_table = bnxt_pci_id_map,
6094         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6095                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6096                                                   * and OVS-DPDK
6097                                                   */
6098         .probe = bnxt_pci_probe,
6099         .remove = bnxt_pci_remove,
6100 };
6101
6102 static bool
6103 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6104 {
6105         if (strcmp(dev->device->driver->name, drv->driver.name))
6106                 return false;
6107
6108         return true;
6109 }
6110
6111 bool is_bnxt_supported(struct rte_eth_dev *dev)
6112 {
6113         return is_device_supported(dev, &bnxt_rte_pmd);
6114 }
6115
6116 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6117 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6118 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6119 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");