drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29 #include "bnxt_util.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  37
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  42 #define BROADCOM_DEV_ID_57301 0x16c8
  43 #define BROADCOM_DEV_ID_57302 0x16c9
  44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  47 #define BROADCOM_DEV_ID_NS2 0x16cd
  48 #define BROADCOM_DEV_ID_57311 0x16ce
  49 #define BROADCOM_DEV_ID_57312 0x16cf
  50 #define BROADCOM_DEV_ID_57402 0x16d0
  51 #define BROADCOM_DEV_ID_57404 0x16d1
  52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  56 #define BROADCOM_DEV_ID_57412 0x16d6
  57 #define BROADCOM_DEV_ID_57414 0x16d7
  58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  61 #define BROADCOM_DEV_ID_57412_MF 0x16de
  62 #define BROADCOM_DEV_ID_57314 0x16df
  63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  74 #define BROADCOM_DEV_ID_57508 0x1750
  75 #define BROADCOM_DEV_ID_57504 0x1751
  76 #define BROADCOM_DEV_ID_57502 0x1752
  77 #define BROADCOM_DEV_ID_57500_VF 0x1807
  78 #define BROADCOM_DEV_ID_58802 0xd802
  79 #define BROADCOM_DEV_ID_58804 0xd804
  80 #define BROADCOM_DEV_ID_58808 0x16f0
  81 #define BROADCOM_DEV_ID_58802_VF 0xd800
  82
  83 static const struct rte_pci_id bnxt_pci_id_map[] = {
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  85                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  87                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF) },
 130         { .vendor_id = 0, /* sentinel */ },
 131 };
 132
 133 #define BNXT_ETH_RSS_SUPPORT (  \
 134         ETH_RSS_IPV4 |          \
 135         ETH_RSS_NONFRAG_IPV4_TCP |      \
 136         ETH_RSS_NONFRAG_IPV4_UDP |      \
 137         ETH_RSS_IPV6 |          \
 138         ETH_RSS_NONFRAG_IPV6_TCP |      \
 139         ETH_RSS_NONFRAG_IPV6_UDP)
 140
 141 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 142                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 143                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 144                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 145                                      DEV_TX_OFFLOAD_TCP_TSO | \
 146                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 147                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 148                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 149                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 150                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 152
 153 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 154                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 155                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 156                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 157                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 158                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 159                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 160                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 161                                      DEV_RX_OFFLOAD_TCP_LRO)
 162
 163 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 164 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 165 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 166 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 167
 168 /***********************/
 169
 170 /*
 171  * High level utility functions
 172  */
 173
 174 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 175 {
 176         if (!BNXT_CHIP_THOR(bp))
 177                 return 1;
 178
 179         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 180                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 181                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 182 }
 183
 184 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 185 {
 186         if (!BNXT_CHIP_THOR(bp))
 187                 return HW_HASH_INDEX_SIZE;
 188
 189         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 190 }
 191
 192 static void bnxt_free_mem(struct bnxt *bp)
 193 {
 194         bnxt_free_filter_mem(bp);
 195         bnxt_free_vnic_attributes(bp);
 196         bnxt_free_vnic_mem(bp);
 197
 198         bnxt_free_stats(bp);
 199         bnxt_free_tx_rings(bp);
 200         bnxt_free_rx_rings(bp);
 201 }
 202
 203 static int bnxt_alloc_mem(struct bnxt *bp)
 204 {
 205         int rc;
 206
 207         rc = bnxt_alloc_vnic_mem(bp);
 208         if (rc)
 209                 goto alloc_mem_err;
 210
 211         rc = bnxt_alloc_vnic_attributes(bp);
 212         if (rc)
 213                 goto alloc_mem_err;
 214
 215         rc = bnxt_alloc_filter_mem(bp);
 216         if (rc)
 217                 goto alloc_mem_err;
 218
 219         return 0;
 220
 221 alloc_mem_err:
 222         bnxt_free_mem(bp);
 223         return rc;
 224 }
 225
 226 static int bnxt_init_chip(struct bnxt *bp)
 227 {
 228         struct bnxt_rx_queue *rxq;
 229         struct rte_eth_link new;
 230         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 231         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 232         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 233         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 234         uint32_t intr_vector = 0;
 235         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 236         uint32_t vec = BNXT_MISC_VEC_ID;
 237         unsigned int i, j;
 238         int rc;
 239
 240         /* disable uio/vfio intr/eventfd mapping */
 241         rte_intr_disable(intr_handle);
 242
 243         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 244                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 245                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 246                 bp->flags |= BNXT_FLAG_JUMBO;
 247         } else {
 248                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 249                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 250                 bp->flags &= ~BNXT_FLAG_JUMBO;
 251         }
 252
 253         /* THOR does not support ring groups.
 254          * But we will use the array to save RSS context IDs.
 255          */
 256         if (BNXT_CHIP_THOR(bp))
 257                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 258
 259         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 260         if (rc) {
 261                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 262                 goto err_out;
 263         }
 264
 265         rc = bnxt_alloc_hwrm_rings(bp);
 266         if (rc) {
 267                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 268                 goto err_out;
 269         }
 270
 271         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 272         if (rc) {
 273                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 274                 goto err_out;
 275         }
 276
 277         rc = bnxt_mq_rx_configure(bp);
 278         if (rc) {
 279                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 280                 goto err_out;
 281         }
 282
 283         /* VNIC configuration */
 284         for (i = 0; i < bp->nr_vnics; i++) {
 285                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 286                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 287                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 288
 289                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 290                 if (!vnic->fw_grp_ids) {
 291                         PMD_DRV_LOG(ERR,
 292                                     "Failed to alloc %d bytes for group ids\n",
 293                                     size);
 294                         rc = -ENOMEM;
 295                         goto err_out;
 296                 }
 297                 memset(vnic->fw_grp_ids, -1, size);
 298
 299                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 300                             i, vnic, vnic->fw_grp_ids);
 301
 302                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 303                 if (rc) {
 304                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 305                                 i, rc);
 306                         goto err_out;
 307                 }
 308
 309                 /* Alloc RSS context only if RSS mode is enabled */
 310                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 311                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 312
 313                         rc = 0;
 314                         for (j = 0; j < nr_ctxs; j++) {
 315                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 316                                 if (rc)
 317                                         break;
 318                         }
 319                         if (rc) {
 320                                 PMD_DRV_LOG(ERR,
 321                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 322                                   i, j, rc);
 323                                 goto err_out;
 324                         }
 325                         vnic->num_lb_ctxts = nr_ctxs;
 326                 }
 327
 328                 /*
 329                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 330                  * setting is not available at this time, it will not be
 331                  * configured correctly in the CFA.
 332                  */
 333                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 334                         vnic->vlan_strip = true;
 335                 else
 336                         vnic->vlan_strip = false;
 337
 338                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 339                 if (rc) {
 340                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 341                                 i, rc);
 342                         goto err_out;
 343                 }
 344
 345                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 346                 if (rc) {
 347                         PMD_DRV_LOG(ERR,
 348                                 "HWRM vnic %d filter failure rc: %x\n",
 349                                 i, rc);
 350                         goto err_out;
 351                 }
 352
 353                 for (j = 0; j < bp->rx_nr_rings; j++) {
 354                         rxq = bp->eth_dev->data->rx_queues[j];
 355
 356                         PMD_DRV_LOG(DEBUG,
 357                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 358                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 359
 360                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 361                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 362                 }
 363
 364                 rc = bnxt_vnic_rss_configure(bp, vnic);
 365                 if (rc) {
 366                         PMD_DRV_LOG(ERR,
 367                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 368                         goto err_out;
 369                 }
 370
 371                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 372
 373                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 374                     DEV_RX_OFFLOAD_TCP_LRO)
 375                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 376                 else
 377                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 378         }
 379         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 380         if (rc) {
 381                 PMD_DRV_LOG(ERR,
 382                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 383                 goto err_out;
 384         }
 385
 386         /* check and configure queue intr-vector mapping */
 387         if ((rte_intr_cap_multiple(intr_handle) ||
 388              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 389             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 390                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 391                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 392                 if (intr_vector > bp->rx_cp_nr_rings) {
 393                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 394                                         bp->rx_cp_nr_rings);
 395                         return -ENOTSUP;
 396                 }
 397                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 398                 if (rc)
 399                         return rc;
 400         }
 401
 402         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 403                 intr_handle->intr_vec =
 404                         rte_zmalloc("intr_vec",
 405                                     bp->eth_dev->data->nb_rx_queues *
 406                                     sizeof(int), 0);
 407                 if (intr_handle->intr_vec == NULL) {
 408                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 409                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 410                         rc = -ENOMEM;
 411                         goto err_disable;
 412                 }
 413                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 414                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 415                          intr_handle->intr_vec, intr_handle->nb_efd,
 416                         intr_handle->max_intr);
 417                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 418                      queue_id++) {
 419                         intr_handle->intr_vec[queue_id] = vec;
 420                         if (vec < base + intr_handle->nb_efd - 1)
 421                                 vec++;
 422                 }
 423         }
 424
 425         /* enable uio/vfio intr/eventfd mapping */
 426         rc = rte_intr_enable(intr_handle);
 427         if (rc)
 428                 goto err_free;
 429
 430         rc = bnxt_get_hwrm_link_config(bp, &new);
 431         if (rc) {
 432                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 433                 goto err_free;
 434         }
 435
 436         if (!bp->link_info.link_up) {
 437                 rc = bnxt_set_hwrm_link_config(bp, true);
 438                 if (rc) {
 439                         PMD_DRV_LOG(ERR,
 440                                 "HWRM link config failure rc: %x\n", rc);
 441                         goto err_free;
 442                 }
 443         }
 444         bnxt_print_link_info(bp->eth_dev);
 445
 446         return 0;
 447
 448 err_free:
 449         rte_free(intr_handle->intr_vec);
 450 err_disable:
 451         rte_intr_efd_disable(intr_handle);
 452 err_out:
 453         /* Some of the error status returned by FW may not be from errno.h */
 454         if (rc > 0)
 455                 rc = -EIO;
 456
 457         return rc;
 458 }
 459
 460 static int bnxt_shutdown_nic(struct bnxt *bp)
 461 {
 462         bnxt_free_all_hwrm_resources(bp);
 463         bnxt_free_all_filters(bp);
 464         bnxt_free_all_vnics(bp);
 465         return 0;
 466 }
 467
 468 static int bnxt_init_nic(struct bnxt *bp)
 469 {
 470         int rc;
 471
 472         if (BNXT_HAS_RING_GRPS(bp)) {
 473                 rc = bnxt_init_ring_grps(bp);
 474                 if (rc)
 475                         return rc;
 476         }
 477
 478         bnxt_init_vnics(bp);
 479         bnxt_init_filters(bp);
 480
 481         return 0;
 482 }
 483
 484 /*
 485  * Device configuration and status function
 486  */
 487
 488 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 489                                   struct rte_eth_dev_info *dev_info)
 490 {
 491         struct bnxt *bp = eth_dev->data->dev_private;
 492         uint16_t max_vnics, i, j, vpool, vrxq;
 493         unsigned int max_rx_rings;
 494
 495         /* MAC Specifics */
 496         dev_info->max_mac_addrs = bp->max_l2_ctx;
 497         dev_info->max_hash_mac_addrs = 0;
 498
 499         /* PF/VF specifics */
 500         if (BNXT_PF(bp))
 501                 dev_info->max_vfs = bp->pdev->max_vfs;
 502         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 503         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 504         dev_info->max_rx_queues = max_rx_rings;
 505         dev_info->max_tx_queues = max_rx_rings;
 506         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 507         dev_info->hash_key_size = 40;
 508         max_vnics = bp->max_vnics;
 509
 510         /* Fast path specifics */
 511         dev_info->min_rx_bufsize = 1;
 512         dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
 513                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
 514
 515         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 516         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 517                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 518         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 519         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 520
 521         /* *INDENT-OFF* */
 522         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 523                 .rx_thresh = {
 524                         .pthresh = 8,
 525                         .hthresh = 8,
 526                         .wthresh = 0,
 527                 },
 528                 .rx_free_thresh = 32,
 529                 /* If no descriptors available, pkts are dropped by default */
 530                 .rx_drop_en = 1,
 531         };
 532
 533         dev_info->default_txconf = (struct rte_eth_txconf) {
 534                 .tx_thresh = {
 535                         .pthresh = 32,
 536                         .hthresh = 0,
 537                         .wthresh = 0,
 538                 },
 539                 .tx_free_thresh = 32,
 540                 .tx_rs_thresh = 32,
 541         };
 542         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 543
 544         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 545         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 546         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 547         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 548         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 549
 550         /* *INDENT-ON* */
 551
 552         /*
 553          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 554          *       need further investigation.
 555          */
 556
 557         /* VMDq resources */
 558         vpool = 64; /* ETH_64_POOLS */
 559         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 560         for (i = 0; i < 4; vpool >>= 1, i++) {
 561                 if (max_vnics > vpool) {
 562                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 563                                 if (dev_info->max_rx_queues > vrxq) {
 564                                         if (vpool > vrxq)
 565                                                 vpool = vrxq;
 566                                         goto found;
 567                                 }
 568                         }
 569                         /* Not enough resources to support VMDq */
 570                         break;
 571                 }
 572         }
 573         /* Not enough resources to support VMDq */
 574         vpool = 0;
 575         vrxq = 0;
 576 found:
 577         dev_info->max_vmdq_pools = vpool;
 578         dev_info->vmdq_queue_num = vrxq;
 579
 580         dev_info->vmdq_pool_base = 0;
 581         dev_info->vmdq_queue_base = 0;
 582 }
 583
 584 /* Configure the device based on the configuration provided */
 585 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 586 {
 587         struct bnxt *bp = eth_dev->data->dev_private;
 588         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 589         int rc;
 590
 591         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 592         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 593         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 594         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 595
 596         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 597                 rc = bnxt_hwrm_check_vf_rings(bp);
 598                 if (rc) {
 599                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 600                         return -ENOSPC;
 601                 }
 602
 603                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 604                 if (rc) {
 605                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 606                         return -ENOSPC;
 607                 }
 608         } else {
 609                 /* legacy driver needs to get updated values */
 610                 rc = bnxt_hwrm_func_qcaps(bp);
 611                 if (rc) {
 612                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 613                         return rc;
 614                 }
 615         }
 616
 617         /* Inherit new configurations */
 618         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 619             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 620             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 621             bp->max_cp_rings ||
 622             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 623             bp->max_stat_ctx)
 624                 goto resource_error;
 625
 626         if (BNXT_HAS_RING_GRPS(bp) &&
 627             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 628                 goto resource_error;
 629
 630         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 631             bp->max_vnics < eth_dev->data->nb_rx_queues)
 632                 goto resource_error;
 633
 634         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 635         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 636
 637         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 638                 eth_dev->data->mtu =
 639                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 640                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 641                         BNXT_NUM_VLANS;
 642                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 643         }
 644         return 0;
 645
 646 resource_error:
 647         PMD_DRV_LOG(ERR,
 648                     "Insufficient resources to support requested config\n");
 649         PMD_DRV_LOG(ERR,
 650                     "Num Queues Requested: Tx %d, Rx %d\n",
 651                     eth_dev->data->nb_tx_queues,
 652                     eth_dev->data->nb_rx_queues);
 653         PMD_DRV_LOG(ERR,
 654                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 655                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 656                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 657         return -ENOSPC;
 658 }
 659
 660 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 661 {
 662         struct rte_eth_link *link = &eth_dev->data->dev_link;
 663
 664         if (link->link_status)
 665                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 666                         eth_dev->data->port_id,
 667                         (uint32_t)link->link_speed,
 668                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 669                         ("full-duplex") : ("half-duplex\n"));
 670         else
 671                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 672                         eth_dev->data->port_id);
 673 }
 674
 675 /*
 676  * Determine whether the current configuration requires support for scattered
 677  * receive; return 1 if scattered receive is required and 0 if not.
 678  */
 679 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 680 {
 681         uint16_t buf_size;
 682         int i;
 683
 684         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 685                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 686
 687                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 688                                       RTE_PKTMBUF_HEADROOM);
 689                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 690                         return 1;
 691         }
 692         return 0;
 693 }
 694
 695 static eth_rx_burst_t
 696 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 697 {
 698 #ifdef RTE_ARCH_X86
 699         /*
 700          * Vector mode receive can be enabled only if scatter rx is not
 701          * in use and rx offloads are limited to VLAN stripping and
 702          * CRC stripping.
 703          */
 704         if (!eth_dev->data->scattered_rx &&
 705             !(eth_dev->data->dev_conf.rxmode.offloads &
 706               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 707                 DEV_RX_OFFLOAD_KEEP_CRC |
 708                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 709                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 710                 DEV_RX_OFFLOAD_UDP_CKSUM |
 711                 DEV_RX_OFFLOAD_TCP_CKSUM |
 712                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 713                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 714                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 715                             eth_dev->data->port_id);
 716                 return bnxt_recv_pkts_vec;
 717         }
 718         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 719                     eth_dev->data->port_id);
 720         PMD_DRV_LOG(INFO,
 721                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 722                     eth_dev->data->port_id,
 723                     eth_dev->data->scattered_rx,
 724                     eth_dev->data->dev_conf.rxmode.offloads);
 725 #endif
 726         return bnxt_recv_pkts;
 727 }
 728
 729 static eth_tx_burst_t
 730 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 731 {
 732 #ifdef RTE_ARCH_X86
 733         /*
 734          * Vector mode receive can be enabled only if scatter tx is not
 735          * in use and tx offloads other than VLAN insertion are not
 736          * in use.
 737          */
 738         if (!eth_dev->data->scattered_rx &&
 739             !(eth_dev->data->dev_conf.txmode.offloads &
 740               ~DEV_TX_OFFLOAD_VLAN_INSERT)) {
 741                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 742                             eth_dev->data->port_id);
 743                 return bnxt_xmit_pkts_vec;
 744         }
 745         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 746                     eth_dev->data->port_id);
 747         PMD_DRV_LOG(INFO,
 748                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 749                     eth_dev->data->port_id,
 750                     eth_dev->data->scattered_rx,
 751                     eth_dev->data->dev_conf.txmode.offloads);
 752 #endif
 753         return bnxt_xmit_pkts;
 754 }
 755
 756 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 757 {
 758         struct bnxt *bp = eth_dev->data->dev_private;
 759         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 760         int vlan_mask = 0;
 761         int rc;
 762
 763         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 764                 PMD_DRV_LOG(ERR,
 765                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 766                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 767         }
 768
 769         rc = bnxt_init_chip(bp);
 770         if (rc)
 771                 goto error;
 772
 773         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 774
 775         bnxt_link_update_op(eth_dev, 1);
 776
 777         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 778                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 779         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 780                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 781         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 782         if (rc)
 783                 goto error;
 784
 785         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 786         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 787         bnxt_enable_int(bp);
 788         bp->flags |= BNXT_FLAG_INIT_DONE;
 789         bp->dev_stopped = 0;
 790         return 0;
 791
 792 error:
 793         bnxt_shutdown_nic(bp);
 794         bnxt_free_tx_mbufs(bp);
 795         bnxt_free_rx_mbufs(bp);
 796         return rc;
 797 }
 798
 799 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 800 {
 801         struct bnxt *bp = eth_dev->data->dev_private;
 802         int rc = 0;
 803
 804         if (!bp->link_info.link_up)
 805                 rc = bnxt_set_hwrm_link_config(bp, true);
 806         if (!rc)
 807                 eth_dev->data->dev_link.link_status = 1;
 808
 809         bnxt_print_link_info(eth_dev);
 810         return 0;
 811 }
 812
 813 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 814 {
 815         struct bnxt *bp = eth_dev->data->dev_private;
 816
 817         eth_dev->data->dev_link.link_status = 0;
 818         bnxt_set_hwrm_link_config(bp, false);
 819         bp->link_info.link_up = 0;
 820
 821         return 0;
 822 }
 823
 824 /* Unload the driver, release resources */
 825 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 826 {
 827         struct bnxt *bp = eth_dev->data->dev_private;
 828         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 829         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 830
 831         bnxt_disable_int(bp);
 832
 833         /* disable uio/vfio intr/eventfd mapping */
 834         rte_intr_disable(intr_handle);
 835
 836         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 837         if (bp->eth_dev->data->dev_started) {
 838                 /* TBD: STOP HW queues DMA */
 839                 eth_dev->data->dev_link.link_status = 0;
 840         }
 841         bnxt_set_hwrm_link_config(bp, false);
 842
 843         /* Clean queue intr-vector mapping */
 844         rte_intr_efd_disable(intr_handle);
 845         if (intr_handle->intr_vec != NULL) {
 846                 rte_free(intr_handle->intr_vec);
 847                 intr_handle->intr_vec = NULL;
 848         }
 849
 850         bnxt_hwrm_port_clr_stats(bp);
 851         bnxt_free_tx_mbufs(bp);
 852         bnxt_free_rx_mbufs(bp);
 853         bnxt_shutdown_nic(bp);
 854         bp->dev_stopped = 1;
 855 }
 856
 857 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 858 {
 859         struct bnxt *bp = eth_dev->data->dev_private;
 860
 861         if (bp->dev_stopped == 0)
 862                 bnxt_dev_stop_op(eth_dev);
 863
 864         if (eth_dev->data->mac_addrs != NULL) {
 865                 rte_free(eth_dev->data->mac_addrs);
 866                 eth_dev->data->mac_addrs = NULL;
 867         }
 868         if (bp->grp_info != NULL) {
 869                 rte_free(bp->grp_info);
 870                 bp->grp_info = NULL;
 871         }
 872
 873         bnxt_dev_uninit(eth_dev);
 874 }
 875
 876 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 877                                     uint32_t index)
 878 {
 879         struct bnxt *bp = eth_dev->data->dev_private;
 880         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 881         struct bnxt_vnic_info *vnic;
 882         struct bnxt_filter_info *filter, *temp_filter;
 883         uint32_t i;
 884
 885         /*
 886          * Loop through all VNICs from the specified filter flow pools to
 887          * remove the corresponding MAC addr filter
 888          */
 889         for (i = 0; i < bp->nr_vnics; i++) {
 890                 if (!(pool_mask & (1ULL << i)))
 891                         continue;
 892
 893                 vnic = &bp->vnic_info[i];
 894                 filter = STAILQ_FIRST(&vnic->filter);
 895                 while (filter) {
 896                         temp_filter = STAILQ_NEXT(filter, next);
 897                         if (filter->mac_index == index) {
 898                                 STAILQ_REMOVE(&vnic->filter, filter,
 899                                                 bnxt_filter_info, next);
 900                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 901                                 filter->mac_index = INVALID_MAC_INDEX;
 902                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 903                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 904                                                    filter, next);
 905                         }
 906                         filter = temp_filter;
 907                 }
 908         }
 909 }
 910
 911 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 912                                 struct rte_ether_addr *mac_addr,
 913                                 uint32_t index, uint32_t pool)
 914 {
 915         struct bnxt *bp = eth_dev->data->dev_private;
 916         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
 917         struct bnxt_filter_info *filter;
 918         int rc = 0;
 919
 920         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
 921                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
 922                 return -ENOTSUP;
 923         }
 924
 925         if (!vnic) {
 926                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
 927                 return -EINVAL;
 928         }
 929         /* Attach requested MAC address to the new l2_filter */
 930         STAILQ_FOREACH(filter, &vnic->filter, next) {
 931                 if (filter->mac_index == index) {
 932                         PMD_DRV_LOG(ERR,
 933                                 "MAC addr already existed for pool %d\n", pool);
 934                         return 0;
 935                 }
 936         }
 937         filter = bnxt_alloc_filter(bp);
 938         if (!filter) {
 939                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
 940                 return -ENODEV;
 941         }
 942
 943         filter->mac_index = index;
 944         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
 945
 946         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 947         if (!rc) {
 948                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 949         } else {
 950                 filter->mac_index = INVALID_MAC_INDEX;
 951                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 952                 bnxt_free_filter(bp, filter);
 953         }
 954
 955         return rc;
 956 }
 957
 958 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 959 {
 960         int rc = 0;
 961         struct bnxt *bp = eth_dev->data->dev_private;
 962         struct rte_eth_link new;
 963         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 964
 965         memset(&new, 0, sizeof(new));
 966         do {
 967                 /* Retrieve link info from hardware */
 968                 rc = bnxt_get_hwrm_link_config(bp, &new);
 969                 if (rc) {
 970                         new.link_speed = ETH_LINK_SPEED_100M;
 971                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 972                         PMD_DRV_LOG(ERR,
 973                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 974                         goto out;
 975                 }
 976
 977                 if (!wait_to_complete || new.link_status)
 978                         break;
 979
 980                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 981         } while (cnt--);
 982
 983 out:
 984         /* Timed out or success */
 985         if (new.link_status != eth_dev->data->dev_link.link_status ||
 986         new.link_speed != eth_dev->data->dev_link.link_speed) {
 987                 memcpy(&eth_dev->data->dev_link, &new,
 988                         sizeof(struct rte_eth_link));
 989
 990                 _rte_eth_dev_callback_process(eth_dev,
 991                                               RTE_ETH_EVENT_INTR_LSC,
 992                                               NULL);
 993
 994                 bnxt_print_link_info(eth_dev);
 995         }
 996
 997         return rc;
 998 }
 999
1000 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1001 {
1002         struct bnxt *bp = eth_dev->data->dev_private;
1003         struct bnxt_vnic_info *vnic;
1004
1005         if (bp->vnic_info == NULL)
1006                 return;
1007
1008         vnic = &bp->vnic_info[0];
1009
1010         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1011         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1012 }
1013
1014 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1015 {
1016         struct bnxt *bp = eth_dev->data->dev_private;
1017         struct bnxt_vnic_info *vnic;
1018
1019         if (bp->vnic_info == NULL)
1020                 return;
1021
1022         vnic = &bp->vnic_info[0];
1023
1024         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1025         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1026 }
1027
1028 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1029 {
1030         struct bnxt *bp = eth_dev->data->dev_private;
1031         struct bnxt_vnic_info *vnic;
1032
1033         if (bp->vnic_info == NULL)
1034                 return;
1035
1036         vnic = &bp->vnic_info[0];
1037
1038         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1039         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1040 }
1041
1042 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1043 {
1044         struct bnxt *bp = eth_dev->data->dev_private;
1045         struct bnxt_vnic_info *vnic;
1046
1047         if (bp->vnic_info == NULL)
1048                 return;
1049
1050         vnic = &bp->vnic_info[0];
1051
1052         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1053         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1054 }
1055
1056 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1057 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1058 {
1059         if (qid >= bp->rx_nr_rings)
1060                 return NULL;
1061
1062         return bp->eth_dev->data->rx_queues[qid];
1063 }
1064
1065 /* Return rxq corresponding to a given rss table ring/group ID. */
1066 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1067 {
1068         struct bnxt_rx_queue *rxq;
1069         unsigned int i;
1070
1071         if (!BNXT_HAS_RING_GRPS(bp)) {
1072                 for (i = 0; i < bp->rx_nr_rings; i++) {
1073                         rxq = bp->eth_dev->data->rx_queues[i];
1074                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1075                                 return rxq->index;
1076                 }
1077         } else {
1078                 for (i = 0; i < bp->rx_nr_rings; i++) {
1079                         if (bp->grp_info[i].fw_grp_id == fwr)
1080                                 return i;
1081                 }
1082         }
1083
1084         return INVALID_HW_RING_ID;
1085 }
1086
1087 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1088                             struct rte_eth_rss_reta_entry64 *reta_conf,
1089                             uint16_t reta_size)
1090 {
1091         struct bnxt *bp = eth_dev->data->dev_private;
1092         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1093         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1094         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1095         uint16_t idx, sft;
1096         int i;
1097
1098         if (!vnic->rss_table)
1099                 return -EINVAL;
1100
1101         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1102                 return -EINVAL;
1103
1104         if (reta_size != tbl_size) {
1105                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1106                         "(%d) must equal the size supported by the hardware "
1107                         "(%d)\n", reta_size, tbl_size);
1108                 return -EINVAL;
1109         }
1110
1111         for (i = 0; i < reta_size; i++) {
1112                 struct bnxt_rx_queue *rxq;
1113
1114                 idx = i / RTE_RETA_GROUP_SIZE;
1115                 sft = i % RTE_RETA_GROUP_SIZE;
1116
1117                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1118                         continue;
1119
1120                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1121                 if (!rxq) {
1122                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1123                         return -EINVAL;
1124                 }
1125
1126                 if (BNXT_CHIP_THOR(bp)) {
1127                         vnic->rss_table[i * 2] =
1128                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1129                         vnic->rss_table[i * 2 + 1] =
1130                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1131                 } else {
1132                         vnic->rss_table[i] =
1133                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1134                 }
1135
1136                 vnic->rss_table[i] =
1137                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1138         }
1139
1140         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1141         return 0;
1142 }
1143
1144 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1145                               struct rte_eth_rss_reta_entry64 *reta_conf,
1146                               uint16_t reta_size)
1147 {
1148         struct bnxt *bp = eth_dev->data->dev_private;
1149         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1150         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1151         uint16_t idx, sft, i;
1152
1153         /* Retrieve from the default VNIC */
1154         if (!vnic)
1155                 return -EINVAL;
1156         if (!vnic->rss_table)
1157                 return -EINVAL;
1158
1159         if (reta_size != tbl_size) {
1160                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1161                         "(%d) must equal the size supported by the hardware "
1162                         "(%d)\n", reta_size, tbl_size);
1163                 return -EINVAL;
1164         }
1165
1166         for (idx = 0, i = 0; i < reta_size; i++) {
1167                 idx = i / RTE_RETA_GROUP_SIZE;
1168                 sft = i % RTE_RETA_GROUP_SIZE;
1169
1170                 if (reta_conf[idx].mask & (1ULL << sft)) {
1171                         uint16_t qid;
1172
1173                         if (BNXT_CHIP_THOR(bp))
1174                                 qid = bnxt_rss_to_qid(bp,
1175                                                       vnic->rss_table[i * 2]);
1176                         else
1177                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1178
1179                         if (qid == INVALID_HW_RING_ID) {
1180                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1181                                 return -EINVAL;
1182                         }
1183                         reta_conf[idx].reta[sft] = qid;
1184                 }
1185         }
1186
1187         return 0;
1188 }
1189
1190 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1191                                    struct rte_eth_rss_conf *rss_conf)
1192 {
1193         struct bnxt *bp = eth_dev->data->dev_private;
1194         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1195         struct bnxt_vnic_info *vnic;
1196         uint16_t hash_type = 0;
1197         unsigned int i;
1198
1199         /*
1200          * If RSS enablement were different than dev_configure,
1201          * then return -EINVAL
1202          */
1203         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1204                 if (!rss_conf->rss_hf)
1205                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1206         } else {
1207                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1208                         return -EINVAL;
1209         }
1210
1211         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1212         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1213
1214         if (rss_conf->rss_hf & ETH_RSS_IPV4)
1215                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1216         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1217                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1218         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1219                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1220         if (rss_conf->rss_hf & ETH_RSS_IPV6)
1221                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1222         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1223                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1224         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1225                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1226
1227         /* Update the RSS VNIC(s) */
1228         for (i = 0; i < bp->nr_vnics; i++) {
1229                 vnic = &bp->vnic_info[i];
1230                 vnic->hash_type = hash_type;
1231
1232                 /*
1233                  * Use the supplied key if the key length is
1234                  * acceptable and the rss_key is not NULL
1235                  */
1236                 if (rss_conf->rss_key &&
1237                     rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1238                         memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1239                                rss_conf->rss_key_len);
1240
1241                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1242         }
1243         return 0;
1244 }
1245
1246 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1247                                      struct rte_eth_rss_conf *rss_conf)
1248 {
1249         struct bnxt *bp = eth_dev->data->dev_private;
1250         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1251         int len;
1252         uint32_t hash_types;
1253
1254         /* RSS configuration is the same for all VNICs */
1255         if (vnic && vnic->rss_hash_key) {
1256                 if (rss_conf->rss_key) {
1257                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1258                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1259                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1260                 }
1261
1262                 hash_types = vnic->hash_type;
1263                 rss_conf->rss_hf = 0;
1264                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1265                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1266                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1267                 }
1268                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1269                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1270                         hash_types &=
1271                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1272                 }
1273                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1274                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1275                         hash_types &=
1276                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1277                 }
1278                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1279                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1280                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1281                 }
1282                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1283                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1284                         hash_types &=
1285                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1286                 }
1287                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1288                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1289                         hash_types &=
1290                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1291                 }
1292                 if (hash_types) {
1293                         PMD_DRV_LOG(ERR,
1294                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1295                                 vnic->hash_type);
1296                         return -ENOTSUP;
1297                 }
1298         } else {
1299                 rss_conf->rss_hf = 0;
1300         }
1301         return 0;
1302 }
1303
1304 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1305                                struct rte_eth_fc_conf *fc_conf)
1306 {
1307         struct bnxt *bp = dev->data->dev_private;
1308         struct rte_eth_link link_info;
1309         int rc;
1310
1311         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1312         if (rc)
1313                 return rc;
1314
1315         memset(fc_conf, 0, sizeof(*fc_conf));
1316         if (bp->link_info.auto_pause)
1317                 fc_conf->autoneg = 1;
1318         switch (bp->link_info.pause) {
1319         case 0:
1320                 fc_conf->mode = RTE_FC_NONE;
1321                 break;
1322         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1323                 fc_conf->mode = RTE_FC_TX_PAUSE;
1324                 break;
1325         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1326                 fc_conf->mode = RTE_FC_RX_PAUSE;
1327                 break;
1328         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1329                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1330                 fc_conf->mode = RTE_FC_FULL;
1331                 break;
1332         }
1333         return 0;
1334 }
1335
1336 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1337                                struct rte_eth_fc_conf *fc_conf)
1338 {
1339         struct bnxt *bp = dev->data->dev_private;
1340
1341         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1342                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1343                 return -ENOTSUP;
1344         }
1345
1346         switch (fc_conf->mode) {
1347         case RTE_FC_NONE:
1348                 bp->link_info.auto_pause = 0;
1349                 bp->link_info.force_pause = 0;
1350                 break;
1351         case RTE_FC_RX_PAUSE:
1352                 if (fc_conf->autoneg) {
1353                         bp->link_info.auto_pause =
1354                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1355                         bp->link_info.force_pause = 0;
1356                 } else {
1357                         bp->link_info.auto_pause = 0;
1358                         bp->link_info.force_pause =
1359                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1360                 }
1361                 break;
1362         case RTE_FC_TX_PAUSE:
1363                 if (fc_conf->autoneg) {
1364                         bp->link_info.auto_pause =
1365                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1366                         bp->link_info.force_pause = 0;
1367                 } else {
1368                         bp->link_info.auto_pause = 0;
1369                         bp->link_info.force_pause =
1370                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1371                 }
1372                 break;
1373         case RTE_FC_FULL:
1374                 if (fc_conf->autoneg) {
1375                         bp->link_info.auto_pause =
1376                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1377                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1378                         bp->link_info.force_pause = 0;
1379                 } else {
1380                         bp->link_info.auto_pause = 0;
1381                         bp->link_info.force_pause =
1382                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1383                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1384                 }
1385                 break;
1386         }
1387         return bnxt_set_hwrm_link_config(bp, true);
1388 }
1389
1390 /* Add UDP tunneling port */
1391 static int
1392 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1393                          struct rte_eth_udp_tunnel *udp_tunnel)
1394 {
1395         struct bnxt *bp = eth_dev->data->dev_private;
1396         uint16_t tunnel_type = 0;
1397         int rc = 0;
1398
1399         switch (udp_tunnel->prot_type) {
1400         case RTE_TUNNEL_TYPE_VXLAN:
1401                 if (bp->vxlan_port_cnt) {
1402                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1403                                 udp_tunnel->udp_port);
1404                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1405                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1406                                 return -ENOSPC;
1407                         }
1408                         bp->vxlan_port_cnt++;
1409                         return 0;
1410                 }
1411                 tunnel_type =
1412                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1413                 bp->vxlan_port_cnt++;
1414                 break;
1415         case RTE_TUNNEL_TYPE_GENEVE:
1416                 if (bp->geneve_port_cnt) {
1417                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1418                                 udp_tunnel->udp_port);
1419                         if (bp->geneve_port != udp_tunnel->udp_port) {
1420                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1421                                 return -ENOSPC;
1422                         }
1423                         bp->geneve_port_cnt++;
1424                         return 0;
1425                 }
1426                 tunnel_type =
1427                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1428                 bp->geneve_port_cnt++;
1429                 break;
1430         default:
1431                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1432                 return -ENOTSUP;
1433         }
1434         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1435                                              tunnel_type);
1436         return rc;
1437 }
1438
1439 static int
1440 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1441                          struct rte_eth_udp_tunnel *udp_tunnel)
1442 {
1443         struct bnxt *bp = eth_dev->data->dev_private;
1444         uint16_t tunnel_type = 0;
1445         uint16_t port = 0;
1446         int rc = 0;
1447
1448         switch (udp_tunnel->prot_type) {
1449         case RTE_TUNNEL_TYPE_VXLAN:
1450                 if (!bp->vxlan_port_cnt) {
1451                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1452                         return -EINVAL;
1453                 }
1454                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1455                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1456                                 udp_tunnel->udp_port, bp->vxlan_port);
1457                         return -EINVAL;
1458                 }
1459                 if (--bp->vxlan_port_cnt)
1460                         return 0;
1461
1462                 tunnel_type =
1463                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1464                 port = bp->vxlan_fw_dst_port_id;
1465                 break;
1466         case RTE_TUNNEL_TYPE_GENEVE:
1467                 if (!bp->geneve_port_cnt) {
1468                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1469                         return -EINVAL;
1470                 }
1471                 if (bp->geneve_port != udp_tunnel->udp_port) {
1472                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1473                                 udp_tunnel->udp_port, bp->geneve_port);
1474                         return -EINVAL;
1475                 }
1476                 if (--bp->geneve_port_cnt)
1477                         return 0;
1478
1479                 tunnel_type =
1480                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1481                 port = bp->geneve_fw_dst_port_id;
1482                 break;
1483         default:
1484                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1485                 return -ENOTSUP;
1486         }
1487
1488         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1489         if (!rc) {
1490                 if (tunnel_type ==
1491                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1492                         bp->vxlan_port = 0;
1493                 if (tunnel_type ==
1494                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1495                         bp->geneve_port = 0;
1496         }
1497         return rc;
1498 }
1499
1500 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1501 {
1502         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1503         struct bnxt_vnic_info *vnic;
1504         unsigned int i;
1505         int rc = 0;
1506         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1507
1508         /* Cycle through all VNICs */
1509         for (i = 0; i < bp->nr_vnics; i++) {
1510                 /*
1511                  * For each VNIC and each associated filter(s)
1512                  * if VLAN exists && VLAN matches vlan_id
1513                  *      remove the MAC+VLAN filter
1514                  *      add a new MAC only filter
1515                  * else
1516                  *      VLAN filter doesn't exist, just skip and continue
1517                  */
1518                 vnic = &bp->vnic_info[i];
1519                 filter = STAILQ_FIRST(&vnic->filter);
1520                 while (filter) {
1521                         temp_filter = STAILQ_NEXT(filter, next);
1522
1523                         if (filter->enables & chk &&
1524                             filter->l2_ovlan == vlan_id) {
1525                                 /* Must delete the filter */
1526                                 STAILQ_REMOVE(&vnic->filter, filter,
1527                                               bnxt_filter_info, next);
1528                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1529                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1530                                                    filter, next);
1531
1532                                 /*
1533                                  * Need to examine to see if the MAC
1534                                  * filter already existed or not before
1535                                  * allocating a new one
1536                                  */
1537
1538                                 new_filter = bnxt_alloc_filter(bp);
1539                                 if (!new_filter) {
1540                                         PMD_DRV_LOG(ERR,
1541                                                         "MAC/VLAN filter alloc failed\n");
1542                                         rc = -ENOMEM;
1543                                         goto exit;
1544                                 }
1545                                 STAILQ_INSERT_TAIL(&vnic->filter,
1546                                                 new_filter, next);
1547                                 /* Inherit MAC from previous filter */
1548                                 new_filter->mac_index =
1549                                         filter->mac_index;
1550                                 memcpy(new_filter->l2_addr, filter->l2_addr,
1551                                        RTE_ETHER_ADDR_LEN);
1552                                 /* MAC only filter */
1553                                 rc = bnxt_hwrm_set_l2_filter(bp,
1554                                                              vnic->fw_vnic_id,
1555                                                              new_filter);
1556                                 if (rc)
1557                                         goto exit;
1558                                 PMD_DRV_LOG(INFO,
1559                                             "Del Vlan filter for %d\n",
1560                                             vlan_id);
1561                         }
1562                         filter = temp_filter;
1563                 }
1564         }
1565 exit:
1566         return rc;
1567 }
1568
1569 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1570 {
1571         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1572         struct bnxt_vnic_info *vnic;
1573         unsigned int i;
1574         int rc = 0;
1575         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1576                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1577         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1578
1579         /* Cycle through all VNICs */
1580         for (i = 0; i < bp->nr_vnics; i++) {
1581                 /*
1582                  * For each VNIC and each associated filter(s)
1583                  * if VLAN exists:
1584                  *   if VLAN matches vlan_id
1585                  *      VLAN filter already exists, just skip and continue
1586                  *   else
1587                  *      add a new MAC+VLAN filter
1588                  * else
1589                  *   Remove the old MAC only filter
1590                  *    Add a new MAC+VLAN filter
1591                  */
1592                 vnic = &bp->vnic_info[i];
1593                 filter = STAILQ_FIRST(&vnic->filter);
1594                 while (filter) {
1595                         temp_filter = STAILQ_NEXT(filter, next);
1596
1597                         if (filter->enables & chk) {
1598                                 if (filter->l2_ivlan == vlan_id)
1599                                         goto cont;
1600                         } else {
1601                                 /* Must delete the MAC filter */
1602                                 STAILQ_REMOVE(&vnic->filter, filter,
1603                                                 bnxt_filter_info, next);
1604                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1605                                 filter->l2_ovlan = 0;
1606                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1607                                                    filter, next);
1608                         }
1609                         new_filter = bnxt_alloc_filter(bp);
1610                         if (!new_filter) {
1611                                 PMD_DRV_LOG(ERR,
1612                                                 "MAC/VLAN filter alloc failed\n");
1613                                 rc = -ENOMEM;
1614                                 goto exit;
1615                         }
1616                         STAILQ_INSERT_TAIL(&vnic->filter, new_filter, next);
1617                         /* Inherit MAC from the previous filter */
1618                         new_filter->mac_index = filter->mac_index;
1619                         memcpy(new_filter->l2_addr, filter->l2_addr,
1620                                RTE_ETHER_ADDR_LEN);
1621                         /* MAC + VLAN ID filter */
1622                         new_filter->l2_ivlan = vlan_id;
1623                         new_filter->l2_ivlan_mask = 0xF000;
1624                         new_filter->enables |= en;
1625                         rc = bnxt_hwrm_set_l2_filter(bp,
1626                                         vnic->fw_vnic_id,
1627                                         new_filter);
1628                         if (rc)
1629                                 goto exit;
1630                         PMD_DRV_LOG(INFO,
1631                                     "Added Vlan filter for %d\n", vlan_id);
1632 cont:
1633                         filter = temp_filter;
1634                 }
1635         }
1636 exit:
1637         return rc;
1638 }
1639
1640 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1641                 uint16_t vlan_id, int on)
1642 {
1643         struct bnxt *bp = eth_dev->data->dev_private;
1644
1645         /* These operations apply to ALL existing MAC/VLAN filters */
1646         if (on)
1647                 return bnxt_add_vlan_filter(bp, vlan_id);
1648         else
1649                 return bnxt_del_vlan_filter(bp, vlan_id);
1650 }
1651
1652 static int
1653 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1654 {
1655         struct bnxt *bp = dev->data->dev_private;
1656         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1657         unsigned int i;
1658
1659         if (mask & ETH_VLAN_FILTER_MASK) {
1660                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1661                         /* Remove any VLAN filters programmed */
1662                         for (i = 0; i < 4095; i++)
1663                                 bnxt_del_vlan_filter(bp, i);
1664                 }
1665                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1666                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1667         }
1668
1669         if (mask & ETH_VLAN_STRIP_MASK) {
1670                 /* Enable or disable VLAN stripping */
1671                 for (i = 0; i < bp->nr_vnics; i++) {
1672                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1673                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1674                                 vnic->vlan_strip = true;
1675                         else
1676                                 vnic->vlan_strip = false;
1677                         bnxt_hwrm_vnic_cfg(bp, vnic);
1678                 }
1679                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1680                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1681         }
1682
1683         if (mask & ETH_VLAN_EXTEND_MASK)
1684                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1685
1686         return 0;
1687 }
1688
1689 static int
1690 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1691                         struct rte_ether_addr *addr)
1692 {
1693         struct bnxt *bp = dev->data->dev_private;
1694         /* Default Filter is tied to VNIC 0 */
1695         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1696         struct bnxt_filter_info *filter;
1697         int rc;
1698
1699         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1700                 return -EPERM;
1701
1702         memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1703
1704         STAILQ_FOREACH(filter, &vnic->filter, next) {
1705                 /* Default Filter is at Index 0 */
1706                 if (filter->mac_index != 0)
1707                         continue;
1708                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1709                 if (rc)
1710                         return rc;
1711                 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1712                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1713                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1714                 filter->enables |=
1715                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1716                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1717                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1718                 if (rc)
1719                         return rc;
1720                 filter->mac_index = 0;
1721                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1722         }
1723
1724         return 0;
1725 }
1726
1727 static int
1728 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1729                           struct rte_ether_addr *mc_addr_set,
1730                           uint32_t nb_mc_addr)
1731 {
1732         struct bnxt *bp = eth_dev->data->dev_private;
1733         char *mc_addr_list = (char *)mc_addr_set;
1734         struct bnxt_vnic_info *vnic;
1735         uint32_t off = 0, i = 0;
1736
1737         vnic = &bp->vnic_info[0];
1738
1739         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1740                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1741                 goto allmulti;
1742         }
1743
1744         /* TODO Check for Duplicate mcast addresses */
1745         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1746         for (i = 0; i < nb_mc_addr; i++) {
1747                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1748                         RTE_ETHER_ADDR_LEN);
1749                 off += RTE_ETHER_ADDR_LEN;
1750         }
1751
1752         vnic->mc_addr_cnt = i;
1753
1754 allmulti:
1755         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1756 }
1757
1758 static int
1759 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1760 {
1761         struct bnxt *bp = dev->data->dev_private;
1762         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1763         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1764         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1765         int ret;
1766
1767         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1768                         fw_major, fw_minor, fw_updt);
1769
1770         ret += 1; /* add the size of '\0' */
1771         if (fw_size < (uint32_t)ret)
1772                 return ret;
1773         else
1774                 return 0;
1775 }
1776
1777 static void
1778 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1779         struct rte_eth_rxq_info *qinfo)
1780 {
1781         struct bnxt_rx_queue *rxq;
1782
1783         rxq = dev->data->rx_queues[queue_id];
1784
1785         qinfo->mp = rxq->mb_pool;
1786         qinfo->scattered_rx = dev->data->scattered_rx;
1787         qinfo->nb_desc = rxq->nb_rx_desc;
1788
1789         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1790         qinfo->conf.rx_drop_en = 0;
1791         qinfo->conf.rx_deferred_start = 0;
1792 }
1793
1794 static void
1795 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1796         struct rte_eth_txq_info *qinfo)
1797 {
1798         struct bnxt_tx_queue *txq;
1799
1800         txq = dev->data->tx_queues[queue_id];
1801
1802         qinfo->nb_desc = txq->nb_tx_desc;
1803
1804         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1805         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1806         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1807
1808         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1809         qinfo->conf.tx_rs_thresh = 0;
1810         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1811 }
1812
1813 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1814 {
1815         struct bnxt *bp = eth_dev->data->dev_private;
1816         struct rte_eth_dev_info dev_info;
1817         uint32_t new_pkt_size;
1818         uint32_t rc = 0;
1819         uint32_t i;
1820
1821         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1822                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1823
1824         bnxt_dev_info_get_op(eth_dev, &dev_info);
1825
1826         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1827                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1828                         RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1829                 return -EINVAL;
1830         }
1831
1832 #ifdef RTE_ARCH_X86
1833         /*
1834          * If vector-mode tx/rx is active, disallow any MTU change that would
1835          * require scattered receive support.
1836          */
1837         if (eth_dev->data->dev_started &&
1838             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1839              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1840             (new_pkt_size >
1841              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1842                 PMD_DRV_LOG(ERR,
1843                             "MTU change would require scattered rx support. ");
1844                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1845                 return -EINVAL;
1846         }
1847 #endif
1848
1849         if (new_mtu > RTE_ETHER_MTU) {
1850                 bp->flags |= BNXT_FLAG_JUMBO;
1851                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1852                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1853         } else {
1854                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1855                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1856                 bp->flags &= ~BNXT_FLAG_JUMBO;
1857         }
1858
1859         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
1860
1861         eth_dev->data->mtu = new_mtu;
1862         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1863
1864         for (i = 0; i < bp->nr_vnics; i++) {
1865                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1866                 uint16_t size = 0;
1867
1868                 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1869                                         RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1870                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1871                 if (rc)
1872                         break;
1873
1874                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1875                 size -= RTE_PKTMBUF_HEADROOM;
1876
1877                 if (size < new_mtu) {
1878                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1879                         if (rc)
1880                                 return rc;
1881                 }
1882         }
1883
1884         return rc;
1885 }
1886
1887 static int
1888 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1889 {
1890         struct bnxt *bp = dev->data->dev_private;
1891         uint16_t vlan = bp->vlan;
1892         int rc;
1893
1894         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1895                 PMD_DRV_LOG(ERR,
1896                         "PVID cannot be modified for this function\n");
1897                 return -ENOTSUP;
1898         }
1899         bp->vlan = on ? pvid : 0;
1900
1901         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1902         if (rc)
1903                 bp->vlan = vlan;
1904         return rc;
1905 }
1906
1907 static int
1908 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1909 {
1910         struct bnxt *bp = dev->data->dev_private;
1911
1912         return bnxt_hwrm_port_led_cfg(bp, true);
1913 }
1914
1915 static int
1916 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1917 {
1918         struct bnxt *bp = dev->data->dev_private;
1919
1920         return bnxt_hwrm_port_led_cfg(bp, false);
1921 }
1922
1923 static uint32_t
1924 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1925 {
1926         uint32_t desc = 0, raw_cons = 0, cons;
1927         struct bnxt_cp_ring_info *cpr;
1928         struct bnxt_rx_queue *rxq;
1929         struct rx_pkt_cmpl *rxcmp;
1930         uint16_t cmp_type;
1931         uint8_t cmp = 1;
1932         bool valid;
1933
1934         rxq = dev->data->rx_queues[rx_queue_id];
1935         cpr = rxq->cp_ring;
1936         valid = cpr->valid;
1937
1938         while (raw_cons < rxq->nb_rx_desc) {
1939                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1940                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1941
1942                 if (!CMPL_VALID(rxcmp, valid))
1943                         goto nothing_to_do;
1944                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1945                 cmp_type = CMP_TYPE(rxcmp);
1946                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1947                         cmp = (rte_le_to_cpu_32(
1948                                         ((struct rx_tpa_end_cmpl *)
1949                                          (rxcmp))->agg_bufs_v1) &
1950                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1951                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1952                         desc++;
1953                 } else if (cmp_type == 0x11) {
1954                         desc++;
1955                         cmp = (rxcmp->agg_bufs_v1 &
1956                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1957                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1958                 } else {
1959                         cmp = 1;
1960                 }
1961 nothing_to_do:
1962                 raw_cons += cmp ? cmp : 2;
1963         }
1964
1965         return desc;
1966 }
1967
1968 static int
1969 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1970 {
1971         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1972         struct bnxt_rx_ring_info *rxr;
1973         struct bnxt_cp_ring_info *cpr;
1974         struct bnxt_sw_rx_bd *rx_buf;
1975         struct rx_pkt_cmpl *rxcmp;
1976         uint32_t cons, cp_cons;
1977
1978         if (!rxq)
1979                 return -EINVAL;
1980
1981         cpr = rxq->cp_ring;
1982         rxr = rxq->rx_ring;
1983
1984         if (offset >= rxq->nb_rx_desc)
1985                 return -EINVAL;
1986
1987         cons = RING_CMP(cpr->cp_ring_struct, offset);
1988         cp_cons = cpr->cp_raw_cons;
1989         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1990
1991         if (cons > cp_cons) {
1992                 if (CMPL_VALID(rxcmp, cpr->valid))
1993                         return RTE_ETH_RX_DESC_DONE;
1994         } else {
1995                 if (CMPL_VALID(rxcmp, !cpr->valid))
1996                         return RTE_ETH_RX_DESC_DONE;
1997         }
1998         rx_buf = &rxr->rx_buf_ring[cons];
1999         if (rx_buf->mbuf == NULL)
2000                 return RTE_ETH_RX_DESC_UNAVAIL;
2001
2002
2003         return RTE_ETH_RX_DESC_AVAIL;
2004 }
2005
2006 static int
2007 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2008 {
2009         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2010         struct bnxt_tx_ring_info *txr;
2011         struct bnxt_cp_ring_info *cpr;
2012         struct bnxt_sw_tx_bd *tx_buf;
2013         struct tx_pkt_cmpl *txcmp;
2014         uint32_t cons, cp_cons;
2015
2016         if (!txq)
2017                 return -EINVAL;
2018
2019         cpr = txq->cp_ring;
2020         txr = txq->tx_ring;
2021
2022         if (offset >= txq->nb_tx_desc)
2023                 return -EINVAL;
2024
2025         cons = RING_CMP(cpr->cp_ring_struct, offset);
2026         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2027         cp_cons = cpr->cp_raw_cons;
2028
2029         if (cons > cp_cons) {
2030                 if (CMPL_VALID(txcmp, cpr->valid))
2031                         return RTE_ETH_TX_DESC_UNAVAIL;
2032         } else {
2033                 if (CMPL_VALID(txcmp, !cpr->valid))
2034                         return RTE_ETH_TX_DESC_UNAVAIL;
2035         }
2036         tx_buf = &txr->tx_buf_ring[cons];
2037         if (tx_buf->mbuf == NULL)
2038                 return RTE_ETH_TX_DESC_DONE;
2039
2040         return RTE_ETH_TX_DESC_FULL;
2041 }
2042
2043 static struct bnxt_filter_info *
2044 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2045                                 struct rte_eth_ethertype_filter *efilter,
2046                                 struct bnxt_vnic_info *vnic0,
2047                                 struct bnxt_vnic_info *vnic,
2048                                 int *ret)
2049 {
2050         struct bnxt_filter_info *mfilter = NULL;
2051         int match = 0;
2052         *ret = 0;
2053
2054         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2055                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2056                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2057                         " ethertype filter.", efilter->ether_type);
2058                 *ret = -EINVAL;
2059                 goto exit;
2060         }
2061         if (efilter->queue >= bp->rx_nr_rings) {
2062                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2063                 *ret = -EINVAL;
2064                 goto exit;
2065         }
2066
2067         vnic0 = &bp->vnic_info[0];
2068         vnic = &bp->vnic_info[efilter->queue];
2069         if (vnic == NULL) {
2070                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2071                 *ret = -EINVAL;
2072                 goto exit;
2073         }
2074
2075         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2076                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2077                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2078                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2079                              mfilter->flags ==
2080                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2081                              mfilter->ethertype == efilter->ether_type)) {
2082                                 match = 1;
2083                                 break;
2084                         }
2085                 }
2086         } else {
2087                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2088                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2089                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2090                              mfilter->ethertype == efilter->ether_type &&
2091                              mfilter->flags ==
2092                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2093                                 match = 1;
2094                                 break;
2095                         }
2096         }
2097
2098         if (match)
2099                 *ret = -EEXIST;
2100
2101 exit:
2102         return mfilter;
2103 }
2104
2105 static int
2106 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2107                         enum rte_filter_op filter_op,
2108                         void *arg)
2109 {
2110         struct bnxt *bp = dev->data->dev_private;
2111         struct rte_eth_ethertype_filter *efilter =
2112                         (struct rte_eth_ethertype_filter *)arg;
2113         struct bnxt_filter_info *bfilter, *filter1;
2114         struct bnxt_vnic_info *vnic, *vnic0;
2115         int ret;
2116
2117         if (filter_op == RTE_ETH_FILTER_NOP)
2118                 return 0;
2119
2120         if (arg == NULL) {
2121                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2122                             filter_op);
2123                 return -EINVAL;
2124         }
2125
2126         vnic0 = &bp->vnic_info[0];
2127         vnic = &bp->vnic_info[efilter->queue];
2128
2129         switch (filter_op) {
2130         case RTE_ETH_FILTER_ADD:
2131                 bnxt_match_and_validate_ether_filter(bp, efilter,
2132                                                         vnic0, vnic, &ret);
2133                 if (ret < 0)
2134                         return ret;
2135
2136                 bfilter = bnxt_get_unused_filter(bp);
2137                 if (bfilter == NULL) {
2138                         PMD_DRV_LOG(ERR,
2139                                 "Not enough resources for a new filter.\n");
2140                         return -ENOMEM;
2141                 }
2142                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2143                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2144                        RTE_ETHER_ADDR_LEN);
2145                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2146                        RTE_ETHER_ADDR_LEN);
2147                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2148                 bfilter->ethertype = efilter->ether_type;
2149                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2150
2151                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2152                 if (filter1 == NULL) {
2153                         ret = -1;
2154                         goto cleanup;
2155                 }
2156                 bfilter->enables |=
2157                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2158                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2159
2160                 bfilter->dst_id = vnic->fw_vnic_id;
2161
2162                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2163                         bfilter->flags =
2164                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2165                 }
2166
2167                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2168                 if (ret)
2169                         goto cleanup;
2170                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2171                 break;
2172         case RTE_ETH_FILTER_DELETE:
2173                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2174                                                         vnic0, vnic, &ret);
2175                 if (ret == -EEXIST) {
2176                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2177
2178                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2179                                       next);
2180                         bnxt_free_filter(bp, filter1);
2181                 } else if (ret == 0) {
2182                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2183                 }
2184                 break;
2185         default:
2186                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2187                 ret = -EINVAL;
2188                 goto error;
2189         }
2190         return ret;
2191 cleanup:
2192         bnxt_free_filter(bp, bfilter);
2193 error:
2194         return ret;
2195 }
2196
2197 static inline int
2198 parse_ntuple_filter(struct bnxt *bp,
2199                     struct rte_eth_ntuple_filter *nfilter,
2200                     struct bnxt_filter_info *bfilter)
2201 {
2202         uint32_t en = 0;
2203
2204         if (nfilter->queue >= bp->rx_nr_rings) {
2205                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2206                 return -EINVAL;
2207         }
2208
2209         switch (nfilter->dst_port_mask) {
2210         case UINT16_MAX:
2211                 bfilter->dst_port_mask = -1;
2212                 bfilter->dst_port = nfilter->dst_port;
2213                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2214                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2215                 break;
2216         default:
2217                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2218                 return -EINVAL;
2219         }
2220
2221         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2222         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2223
2224         switch (nfilter->proto_mask) {
2225         case UINT8_MAX:
2226                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2227                         bfilter->ip_protocol = 17;
2228                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2229                         bfilter->ip_protocol = 6;
2230                 else
2231                         return -EINVAL;
2232                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2233                 break;
2234         default:
2235                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2236                 return -EINVAL;
2237         }
2238
2239         switch (nfilter->dst_ip_mask) {
2240         case UINT32_MAX:
2241                 bfilter->dst_ipaddr_mask[0] = -1;
2242                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2243                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2244                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2245                 break;
2246         default:
2247                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2248                 return -EINVAL;
2249         }
2250
2251         switch (nfilter->src_ip_mask) {
2252         case UINT32_MAX:
2253                 bfilter->src_ipaddr_mask[0] = -1;
2254                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2255                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2256                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2257                 break;
2258         default:
2259                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2260                 return -EINVAL;
2261         }
2262
2263         switch (nfilter->src_port_mask) {
2264         case UINT16_MAX:
2265                 bfilter->src_port_mask = -1;
2266                 bfilter->src_port = nfilter->src_port;
2267                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2268                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2269                 break;
2270         default:
2271                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2272                 return -EINVAL;
2273         }
2274
2275         //TODO Priority
2276         //nfilter->priority = (uint8_t)filter->priority;
2277
2278         bfilter->enables = en;
2279         return 0;
2280 }
2281
2282 static struct bnxt_filter_info*
2283 bnxt_match_ntuple_filter(struct bnxt *bp,
2284                          struct bnxt_filter_info *bfilter,
2285                          struct bnxt_vnic_info **mvnic)
2286 {
2287         struct bnxt_filter_info *mfilter = NULL;
2288         int i;
2289
2290         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2291                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2292                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2293                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2294                             bfilter->src_ipaddr_mask[0] ==
2295                             mfilter->src_ipaddr_mask[0] &&
2296                             bfilter->src_port == mfilter->src_port &&
2297                             bfilter->src_port_mask == mfilter->src_port_mask &&
2298                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2299                             bfilter->dst_ipaddr_mask[0] ==
2300                             mfilter->dst_ipaddr_mask[0] &&
2301                             bfilter->dst_port == mfilter->dst_port &&
2302                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2303                             bfilter->flags == mfilter->flags &&
2304                             bfilter->enables == mfilter->enables) {
2305                                 if (mvnic)
2306                                         *mvnic = vnic;
2307                                 return mfilter;
2308                         }
2309                 }
2310         }
2311         return NULL;
2312 }
2313
2314 static int
2315 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2316                        struct rte_eth_ntuple_filter *nfilter,
2317                        enum rte_filter_op filter_op)
2318 {
2319         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2320         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2321         int ret;
2322
2323         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2324                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2325                 return -EINVAL;
2326         }
2327
2328         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2329                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2330                 return -EINVAL;
2331         }
2332
2333         bfilter = bnxt_get_unused_filter(bp);
2334         if (bfilter == NULL) {
2335                 PMD_DRV_LOG(ERR,
2336                         "Not enough resources for a new filter.\n");
2337                 return -ENOMEM;
2338         }
2339         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2340         if (ret < 0)
2341                 goto free_filter;
2342
2343         vnic = &bp->vnic_info[nfilter->queue];
2344         vnic0 = &bp->vnic_info[0];
2345         filter1 = STAILQ_FIRST(&vnic0->filter);
2346         if (filter1 == NULL) {
2347                 ret = -1;
2348                 goto free_filter;
2349         }
2350
2351         bfilter->dst_id = vnic->fw_vnic_id;
2352         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2353         bfilter->enables |=
2354                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2355         bfilter->ethertype = 0x800;
2356         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2357
2358         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2359
2360         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2361             bfilter->dst_id == mfilter->dst_id) {
2362                 PMD_DRV_LOG(ERR, "filter exists.\n");
2363                 ret = -EEXIST;
2364                 goto free_filter;
2365         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2366                    bfilter->dst_id != mfilter->dst_id) {
2367                 mfilter->dst_id = vnic->fw_vnic_id;
2368                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2369                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2370                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2371                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2372                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2373                 goto free_filter;
2374         }
2375         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2376                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2377                 ret = -ENOENT;
2378                 goto free_filter;
2379         }
2380
2381         if (filter_op == RTE_ETH_FILTER_ADD) {
2382                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2383                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2384                 if (ret)
2385                         goto free_filter;
2386                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2387         } else {
2388                 if (mfilter == NULL) {
2389                         /* This should not happen. But for Coverity! */
2390                         ret = -ENOENT;
2391                         goto free_filter;
2392                 }
2393                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2394
2395                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2396                 bnxt_free_filter(bp, mfilter);
2397                 mfilter->fw_l2_filter_id = -1;
2398                 bnxt_free_filter(bp, bfilter);
2399                 bfilter->fw_l2_filter_id = -1;
2400         }
2401
2402         return 0;
2403 free_filter:
2404         bfilter->fw_l2_filter_id = -1;
2405         bnxt_free_filter(bp, bfilter);
2406         return ret;
2407 }
2408
2409 static int
2410 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2411                         enum rte_filter_op filter_op,
2412                         void *arg)
2413 {
2414         struct bnxt *bp = dev->data->dev_private;
2415         int ret;
2416
2417         if (filter_op == RTE_ETH_FILTER_NOP)
2418                 return 0;
2419
2420         if (arg == NULL) {
2421                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2422                             filter_op);
2423                 return -EINVAL;
2424         }
2425
2426         switch (filter_op) {
2427         case RTE_ETH_FILTER_ADD:
2428                 ret = bnxt_cfg_ntuple_filter(bp,
2429                         (struct rte_eth_ntuple_filter *)arg,
2430                         filter_op);
2431                 break;
2432         case RTE_ETH_FILTER_DELETE:
2433                 ret = bnxt_cfg_ntuple_filter(bp,
2434                         (struct rte_eth_ntuple_filter *)arg,
2435                         filter_op);
2436                 break;
2437         default:
2438                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2439                 ret = -EINVAL;
2440                 break;
2441         }
2442         return ret;
2443 }
2444
2445 static int
2446 bnxt_parse_fdir_filter(struct bnxt *bp,
2447                        struct rte_eth_fdir_filter *fdir,
2448                        struct bnxt_filter_info *filter)
2449 {
2450         enum rte_fdir_mode fdir_mode =
2451                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2452         struct bnxt_vnic_info *vnic0, *vnic;
2453         struct bnxt_filter_info *filter1;
2454         uint32_t en = 0;
2455         int i;
2456
2457         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2458                 return -EINVAL;
2459
2460         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2461         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2462
2463         switch (fdir->input.flow_type) {
2464         case RTE_ETH_FLOW_IPV4:
2465         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2466                 /* FALLTHROUGH */
2467                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2468                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2469                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2470                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2471                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2472                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2473                 filter->ip_addr_type =
2474                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2475                 filter->src_ipaddr_mask[0] = 0xffffffff;
2476                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2477                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2478                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2479                 filter->ethertype = 0x800;
2480                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2481                 break;
2482         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2483                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2484                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2485                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2486                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2487                 filter->dst_port_mask = 0xffff;
2488                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2489                 filter->src_port_mask = 0xffff;
2490                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2491                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2492                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2493                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2494                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2495                 filter->ip_protocol = 6;
2496                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2497                 filter->ip_addr_type =
2498                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2499                 filter->src_ipaddr_mask[0] = 0xffffffff;
2500                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2501                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2502                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2503                 filter->ethertype = 0x800;
2504                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2505                 break;
2506         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2507                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2508                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2509                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2510                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2511                 filter->dst_port_mask = 0xffff;
2512                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2513                 filter->src_port_mask = 0xffff;
2514                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2515                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2516                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2517                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2518                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2519                 filter->ip_protocol = 17;
2520                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2521                 filter->ip_addr_type =
2522                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2523                 filter->src_ipaddr_mask[0] = 0xffffffff;
2524                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2525                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2526                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2527                 filter->ethertype = 0x800;
2528                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2529                 break;
2530         case RTE_ETH_FLOW_IPV6:
2531         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2532                 /* FALLTHROUGH */
2533                 filter->ip_addr_type =
2534                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2535                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2536                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2537                 rte_memcpy(filter->src_ipaddr,
2538                            fdir->input.flow.ipv6_flow.src_ip, 16);
2539                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2540                 rte_memcpy(filter->dst_ipaddr,
2541                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2542                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2543                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2544                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2545                 memset(filter->src_ipaddr_mask, 0xff, 16);
2546                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2547                 filter->ethertype = 0x86dd;
2548                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2549                 break;
2550         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2551                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2552                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2553                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2554                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2555                 filter->dst_port_mask = 0xffff;
2556                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2557                 filter->src_port_mask = 0xffff;
2558                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2559                 filter->ip_addr_type =
2560                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2561                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2562                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2563                 rte_memcpy(filter->src_ipaddr,
2564                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2565                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2566                 rte_memcpy(filter->dst_ipaddr,
2567                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2568                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2569                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2570                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2571                 memset(filter->src_ipaddr_mask, 0xff, 16);
2572                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2573                 filter->ethertype = 0x86dd;
2574                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2575                 break;
2576         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2577                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2578                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2579                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2580                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2581                 filter->dst_port_mask = 0xffff;
2582                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2583                 filter->src_port_mask = 0xffff;
2584                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2585                 filter->ip_addr_type =
2586                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2587                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2588                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2589                 rte_memcpy(filter->src_ipaddr,
2590                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2591                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2592                 rte_memcpy(filter->dst_ipaddr,
2593                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2594                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2595                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2596                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2597                 memset(filter->src_ipaddr_mask, 0xff, 16);
2598                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2599                 filter->ethertype = 0x86dd;
2600                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2601                 break;
2602         case RTE_ETH_FLOW_L2_PAYLOAD:
2603                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2604                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2605                 break;
2606         case RTE_ETH_FLOW_VXLAN:
2607                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2608                         return -EINVAL;
2609                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2610                 filter->tunnel_type =
2611                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2612                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2613                 break;
2614         case RTE_ETH_FLOW_NVGRE:
2615                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2616                         return -EINVAL;
2617                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2618                 filter->tunnel_type =
2619                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2620                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2621                 break;
2622         case RTE_ETH_FLOW_UNKNOWN:
2623         case RTE_ETH_FLOW_RAW:
2624         case RTE_ETH_FLOW_FRAG_IPV4:
2625         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2626         case RTE_ETH_FLOW_FRAG_IPV6:
2627         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2628         case RTE_ETH_FLOW_IPV6_EX:
2629         case RTE_ETH_FLOW_IPV6_TCP_EX:
2630         case RTE_ETH_FLOW_IPV6_UDP_EX:
2631         case RTE_ETH_FLOW_GENEVE:
2632                 /* FALLTHROUGH */
2633         default:
2634                 return -EINVAL;
2635         }
2636
2637         vnic0 = &bp->vnic_info[0];
2638         vnic = &bp->vnic_info[fdir->action.rx_queue];
2639         if (vnic == NULL) {
2640                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2641                 return -EINVAL;
2642         }
2643
2644
2645         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2646                 rte_memcpy(filter->dst_macaddr,
2647                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2648                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2649         }
2650
2651         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2652                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2653                 filter1 = STAILQ_FIRST(&vnic0->filter);
2654                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2655         } else {
2656                 filter->dst_id = vnic->fw_vnic_id;
2657                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2658                         if (filter->dst_macaddr[i] == 0x00)
2659                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2660                         else
2661                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2662         }
2663
2664         if (filter1 == NULL)
2665                 return -EINVAL;
2666
2667         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2668         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2669
2670         filter->enables = en;
2671
2672         return 0;
2673 }
2674
2675 static struct bnxt_filter_info *
2676 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2677                 struct bnxt_vnic_info **mvnic)
2678 {
2679         struct bnxt_filter_info *mf = NULL;
2680         int i;
2681
2682         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2683                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2684
2685                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2686                         if (mf->filter_type == nf->filter_type &&
2687                             mf->flags == nf->flags &&
2688                             mf->src_port == nf->src_port &&
2689                             mf->src_port_mask == nf->src_port_mask &&
2690                             mf->dst_port == nf->dst_port &&
2691                             mf->dst_port_mask == nf->dst_port_mask &&
2692                             mf->ip_protocol == nf->ip_protocol &&
2693                             mf->ip_addr_type == nf->ip_addr_type &&
2694                             mf->ethertype == nf->ethertype &&
2695                             mf->vni == nf->vni &&
2696                             mf->tunnel_type == nf->tunnel_type &&
2697                             mf->l2_ovlan == nf->l2_ovlan &&
2698                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2699                             mf->l2_ivlan == nf->l2_ivlan &&
2700                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2701                             !memcmp(mf->l2_addr, nf->l2_addr,
2702                                     RTE_ETHER_ADDR_LEN) &&
2703                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2704                                     RTE_ETHER_ADDR_LEN) &&
2705                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2706                                     RTE_ETHER_ADDR_LEN) &&
2707                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2708                                     RTE_ETHER_ADDR_LEN) &&
2709                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2710                                     sizeof(nf->src_ipaddr)) &&
2711                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2712                                     sizeof(nf->src_ipaddr_mask)) &&
2713                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2714                                     sizeof(nf->dst_ipaddr)) &&
2715                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2716                                     sizeof(nf->dst_ipaddr_mask))) {
2717                                 if (mvnic)
2718                                         *mvnic = vnic;
2719                                 return mf;
2720                         }
2721                 }
2722         }
2723         return NULL;
2724 }
2725
2726 static int
2727 bnxt_fdir_filter(struct rte_eth_dev *dev,
2728                  enum rte_filter_op filter_op,
2729                  void *arg)
2730 {
2731         struct bnxt *bp = dev->data->dev_private;
2732         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2733         struct bnxt_filter_info *filter, *match;
2734         struct bnxt_vnic_info *vnic, *mvnic;
2735         int ret = 0, i;
2736
2737         if (filter_op == RTE_ETH_FILTER_NOP)
2738                 return 0;
2739
2740         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2741                 return -EINVAL;
2742
2743         switch (filter_op) {
2744         case RTE_ETH_FILTER_ADD:
2745         case RTE_ETH_FILTER_DELETE:
2746                 /* FALLTHROUGH */
2747                 filter = bnxt_get_unused_filter(bp);
2748                 if (filter == NULL) {
2749                         PMD_DRV_LOG(ERR,
2750                                 "Not enough resources for a new flow.\n");
2751                         return -ENOMEM;
2752                 }
2753
2754                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2755                 if (ret != 0)
2756                         goto free_filter;
2757                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2758
2759                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2760                         vnic = &bp->vnic_info[0];
2761                 else
2762                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2763
2764                 match = bnxt_match_fdir(bp, filter, &mvnic);
2765                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2766                         if (match->dst_id == vnic->fw_vnic_id) {
2767                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2768                                 ret = -EEXIST;
2769                                 goto free_filter;
2770                         } else {
2771                                 match->dst_id = vnic->fw_vnic_id;
2772                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2773                                                                   match->dst_id,
2774                                                                   match);
2775                                 STAILQ_REMOVE(&mvnic->filter, match,
2776                                               bnxt_filter_info, next);
2777                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2778                                 PMD_DRV_LOG(ERR,
2779                                         "Filter with matching pattern exist\n");
2780                                 PMD_DRV_LOG(ERR,
2781                                         "Updated it to new destination q\n");
2782                                 goto free_filter;
2783                         }
2784                 }
2785                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2786                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2787                         ret = -ENOENT;
2788                         goto free_filter;
2789                 }
2790
2791                 if (filter_op == RTE_ETH_FILTER_ADD) {
2792                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2793                                                           filter->dst_id,
2794                                                           filter);
2795                         if (ret)
2796                                 goto free_filter;
2797                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2798                 } else {
2799                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2800                         STAILQ_REMOVE(&vnic->filter, match,
2801                                       bnxt_filter_info, next);
2802                         bnxt_free_filter(bp, match);
2803                         filter->fw_l2_filter_id = -1;
2804                         bnxt_free_filter(bp, filter);
2805                 }
2806                 break;
2807         case RTE_ETH_FILTER_FLUSH:
2808                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2809                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2810
2811                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2812                                 if (filter->filter_type ==
2813                                     HWRM_CFA_NTUPLE_FILTER) {
2814                                         ret =
2815                                         bnxt_hwrm_clear_ntuple_filter(bp,
2816                                                                       filter);
2817                                         STAILQ_REMOVE(&vnic->filter, filter,
2818                                                       bnxt_filter_info, next);
2819                                 }
2820                         }
2821                 }
2822                 return ret;
2823         case RTE_ETH_FILTER_UPDATE:
2824         case RTE_ETH_FILTER_STATS:
2825         case RTE_ETH_FILTER_INFO:
2826                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2827                 break;
2828         default:
2829                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2830                 ret = -EINVAL;
2831                 break;
2832         }
2833         return ret;
2834
2835 free_filter:
2836         filter->fw_l2_filter_id = -1;
2837         bnxt_free_filter(bp, filter);
2838         return ret;
2839 }
2840
2841 static int
2842 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2843                     enum rte_filter_type filter_type,
2844                     enum rte_filter_op filter_op, void *arg)
2845 {
2846         int ret = 0;
2847
2848         switch (filter_type) {
2849         case RTE_ETH_FILTER_TUNNEL:
2850                 PMD_DRV_LOG(ERR,
2851                         "filter type: %d: To be implemented\n", filter_type);
2852                 break;
2853         case RTE_ETH_FILTER_FDIR:
2854                 ret = bnxt_fdir_filter(dev, filter_op, arg);
2855                 break;
2856         case RTE_ETH_FILTER_NTUPLE:
2857                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2858                 break;
2859         case RTE_ETH_FILTER_ETHERTYPE:
2860                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2861                 break;
2862         case RTE_ETH_FILTER_GENERIC:
2863                 if (filter_op != RTE_ETH_FILTER_GET)
2864                         return -EINVAL;
2865                 *(const void **)arg = &bnxt_flow_ops;
2866                 break;
2867         default:
2868                 PMD_DRV_LOG(ERR,
2869                         "Filter type (%d) not supported", filter_type);
2870                 ret = -EINVAL;
2871                 break;
2872         }
2873         return ret;
2874 }
2875
2876 static const uint32_t *
2877 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2878 {
2879         static const uint32_t ptypes[] = {
2880                 RTE_PTYPE_L2_ETHER_VLAN,
2881                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2882                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2883                 RTE_PTYPE_L4_ICMP,
2884                 RTE_PTYPE_L4_TCP,
2885                 RTE_PTYPE_L4_UDP,
2886                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2887                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2888                 RTE_PTYPE_INNER_L4_ICMP,
2889                 RTE_PTYPE_INNER_L4_TCP,
2890                 RTE_PTYPE_INNER_L4_UDP,
2891                 RTE_PTYPE_UNKNOWN
2892         };
2893
2894         if (!dev->rx_pkt_burst)
2895                 return NULL;
2896
2897         return ptypes;
2898 }
2899
2900 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2901                          int reg_win)
2902 {
2903         uint32_t reg_base = *reg_arr & 0xfffff000;
2904         uint32_t win_off;
2905         int i;
2906
2907         for (i = 0; i < count; i++) {
2908                 if ((reg_arr[i] & 0xfffff000) != reg_base)
2909                         return -ERANGE;
2910         }
2911         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2912         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
2913         return 0;
2914 }
2915
2916 static int bnxt_map_ptp_regs(struct bnxt *bp)
2917 {
2918         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2919         uint32_t *reg_arr;
2920         int rc, i;
2921
2922         reg_arr = ptp->rx_regs;
2923         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2924         if (rc)
2925                 return rc;
2926
2927         reg_arr = ptp->tx_regs;
2928         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2929         if (rc)
2930                 return rc;
2931
2932         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2933                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2934
2935         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2936                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2937
2938         return 0;
2939 }
2940
2941 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2942 {
2943         rte_write32(0, (uint8_t *)bp->bar0 +
2944                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
2945         rte_write32(0, (uint8_t *)bp->bar0 +
2946                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
2947 }
2948
2949 static uint64_t bnxt_cc_read(struct bnxt *bp)
2950 {
2951         uint64_t ns;
2952
2953         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2954                               BNXT_GRCPF_REG_SYNC_TIME));
2955         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2956                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2957         return ns;
2958 }
2959
2960 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2961 {
2962         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2963         uint32_t fifo;
2964
2965         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2966                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2967         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2968                 return -EAGAIN;
2969
2970         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2971                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2972         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2973                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2974         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2975                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2976
2977         return 0;
2978 }
2979
2980 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2981 {
2982         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2983         struct bnxt_pf_info *pf = &bp->pf;
2984         uint16_t port_id;
2985         uint32_t fifo;
2986
2987         if (!ptp)
2988                 return -ENODEV;
2989
2990         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2991                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2992         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2993                 return -EAGAIN;
2994
2995         port_id = pf->port_id;
2996         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2997                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
2998
2999         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3000                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3001         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3002 /*              bnxt_clr_rx_ts(bp);       TBD  */
3003                 return -EBUSY;
3004         }
3005
3006         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3007                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3008         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3009                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3010
3011         return 0;
3012 }
3013
3014 static int
3015 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3016 {
3017         uint64_t ns;
3018         struct bnxt *bp = dev->data->dev_private;
3019         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3020
3021         if (!ptp)
3022                 return 0;
3023
3024         ns = rte_timespec_to_ns(ts);
3025         /* Set the timecounters to a new value. */
3026         ptp->tc.nsec = ns;
3027
3028         return 0;
3029 }
3030
3031 static int
3032 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3033 {
3034         uint64_t ns, systime_cycles;
3035         struct bnxt *bp = dev->data->dev_private;
3036         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3037
3038         if (!ptp)
3039                 return 0;
3040
3041         systime_cycles = bnxt_cc_read(bp);
3042         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3043         *ts = rte_ns_to_timespec(ns);
3044
3045         return 0;
3046 }
3047 static int
3048 bnxt_timesync_enable(struct rte_eth_dev *dev)
3049 {
3050         struct bnxt *bp = dev->data->dev_private;
3051         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3052         uint32_t shift = 0;
3053
3054         if (!ptp)
3055                 return 0;
3056
3057         ptp->rx_filter = 1;
3058         ptp->tx_tstamp_en = 1;
3059         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3060
3061         if (!bnxt_hwrm_ptp_cfg(bp))
3062                 bnxt_map_ptp_regs(bp);
3063
3064         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3065         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3066         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3067
3068         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3069         ptp->tc.cc_shift = shift;
3070         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3071
3072         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3073         ptp->rx_tstamp_tc.cc_shift = shift;
3074         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3075
3076         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3077         ptp->tx_tstamp_tc.cc_shift = shift;
3078         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3079
3080         return 0;
3081 }
3082
3083 static int
3084 bnxt_timesync_disable(struct rte_eth_dev *dev)
3085 {
3086         struct bnxt *bp = dev->data->dev_private;
3087         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3088
3089         if (!ptp)
3090                 return 0;
3091
3092         ptp->rx_filter = 0;
3093         ptp->tx_tstamp_en = 0;
3094         ptp->rxctl = 0;
3095
3096         bnxt_hwrm_ptp_cfg(bp);
3097
3098         bnxt_unmap_ptp_regs(bp);
3099
3100         return 0;
3101 }
3102
3103 static int
3104 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3105                                  struct timespec *timestamp,
3106                                  uint32_t flags __rte_unused)
3107 {
3108         struct bnxt *bp = dev->data->dev_private;
3109         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3110         uint64_t rx_tstamp_cycles = 0;
3111         uint64_t ns;
3112
3113         if (!ptp)
3114                 return 0;
3115
3116         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3117         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3118         *timestamp = rte_ns_to_timespec(ns);
3119         return  0;
3120 }
3121
3122 static int
3123 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3124                                  struct timespec *timestamp)
3125 {
3126         struct bnxt *bp = dev->data->dev_private;
3127         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3128         uint64_t tx_tstamp_cycles = 0;
3129         uint64_t ns;
3130
3131         if (!ptp)
3132                 return 0;
3133
3134         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3135         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3136         *timestamp = rte_ns_to_timespec(ns);
3137
3138         return 0;
3139 }
3140
3141 static int
3142 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3143 {
3144         struct bnxt *bp = dev->data->dev_private;
3145         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3146
3147         if (!ptp)
3148                 return 0;
3149
3150         ptp->tc.nsec += delta;
3151
3152         return 0;
3153 }
3154
3155 static int
3156 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3157 {
3158         struct bnxt *bp = dev->data->dev_private;
3159         int rc;
3160         uint32_t dir_entries;
3161         uint32_t entry_length;
3162
3163         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3164                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3165                 bp->pdev->addr.devid, bp->pdev->addr.function);
3166
3167         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3168         if (rc != 0)
3169                 return rc;
3170
3171         return dir_entries * entry_length;
3172 }
3173
3174 static int
3175 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3176                 struct rte_dev_eeprom_info *in_eeprom)
3177 {
3178         struct bnxt *bp = dev->data->dev_private;
3179         uint32_t index;
3180         uint32_t offset;
3181
3182         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3183                 "len = %d\n", bp->pdev->addr.domain,
3184                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3185                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3186
3187         if (in_eeprom->offset == 0) /* special offset value to get directory */
3188                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3189                                                 in_eeprom->data);
3190
3191         index = in_eeprom->offset >> 24;
3192         offset = in_eeprom->offset & 0xffffff;
3193
3194         if (index != 0)
3195                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3196                                            in_eeprom->length, in_eeprom->data);
3197
3198         return 0;
3199 }
3200
3201 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3202 {
3203         switch (dir_type) {
3204         case BNX_DIR_TYPE_CHIMP_PATCH:
3205         case BNX_DIR_TYPE_BOOTCODE:
3206         case BNX_DIR_TYPE_BOOTCODE_2:
3207         case BNX_DIR_TYPE_APE_FW:
3208         case BNX_DIR_TYPE_APE_PATCH:
3209         case BNX_DIR_TYPE_KONG_FW:
3210         case BNX_DIR_TYPE_KONG_PATCH:
3211         case BNX_DIR_TYPE_BONO_FW:
3212         case BNX_DIR_TYPE_BONO_PATCH:
3213                 /* FALLTHROUGH */
3214                 return true;
3215         }
3216
3217         return false;
3218 }
3219
3220 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3221 {
3222         switch (dir_type) {
3223         case BNX_DIR_TYPE_AVS:
3224         case BNX_DIR_TYPE_EXP_ROM_MBA:
3225         case BNX_DIR_TYPE_PCIE:
3226         case BNX_DIR_TYPE_TSCF_UCODE:
3227         case BNX_DIR_TYPE_EXT_PHY:
3228         case BNX_DIR_TYPE_CCM:
3229         case BNX_DIR_TYPE_ISCSI_BOOT:
3230         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3231         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3232                 /* FALLTHROUGH */
3233                 return true;
3234         }
3235
3236         return false;
3237 }
3238
3239 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3240 {
3241         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3242                 bnxt_dir_type_is_other_exec_format(dir_type);
3243 }
3244
3245 static int
3246 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3247                 struct rte_dev_eeprom_info *in_eeprom)
3248 {
3249         struct bnxt *bp = dev->data->dev_private;
3250         uint8_t index, dir_op;
3251         uint16_t type, ext, ordinal, attr;
3252
3253         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3254                 "len = %d\n", bp->pdev->addr.domain,
3255                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3256                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3257
3258         if (!BNXT_PF(bp)) {
3259                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3260                 return -EINVAL;
3261         }
3262
3263         type = in_eeprom->magic >> 16;
3264
3265         if (type == 0xffff) { /* special value for directory operations */
3266                 index = in_eeprom->magic & 0xff;
3267                 dir_op = in_eeprom->magic >> 8;
3268                 if (index == 0)
3269                         return -EINVAL;
3270                 switch (dir_op) {
3271                 case 0x0e: /* erase */
3272                         if (in_eeprom->offset != ~in_eeprom->magic)
3273                                 return -EINVAL;
3274                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3275                 default:
3276                         return -EINVAL;
3277                 }
3278         }
3279
3280         /* Create or re-write an NVM item: */
3281         if (bnxt_dir_type_is_executable(type) == true)
3282                 return -EOPNOTSUPP;
3283         ext = in_eeprom->magic & 0xffff;
3284         ordinal = in_eeprom->offset >> 16;
3285         attr = in_eeprom->offset & 0xffff;
3286
3287         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3288                                      in_eeprom->data, in_eeprom->length);
3289         return 0;
3290 }
3291
3292 /*
3293  * Initialization
3294  */
3295
3296 static const struct eth_dev_ops bnxt_dev_ops = {
3297         .dev_infos_get = bnxt_dev_info_get_op,
3298         .dev_close = bnxt_dev_close_op,
3299         .dev_configure = bnxt_dev_configure_op,
3300         .dev_start = bnxt_dev_start_op,
3301         .dev_stop = bnxt_dev_stop_op,
3302         .dev_set_link_up = bnxt_dev_set_link_up_op,
3303         .dev_set_link_down = bnxt_dev_set_link_down_op,
3304         .stats_get = bnxt_stats_get_op,
3305         .stats_reset = bnxt_stats_reset_op,
3306         .rx_queue_setup = bnxt_rx_queue_setup_op,
3307         .rx_queue_release = bnxt_rx_queue_release_op,
3308         .tx_queue_setup = bnxt_tx_queue_setup_op,
3309         .tx_queue_release = bnxt_tx_queue_release_op,
3310         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3311         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3312         .reta_update = bnxt_reta_update_op,
3313         .reta_query = bnxt_reta_query_op,
3314         .rss_hash_update = bnxt_rss_hash_update_op,
3315         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3316         .link_update = bnxt_link_update_op,
3317         .promiscuous_enable = bnxt_promiscuous_enable_op,
3318         .promiscuous_disable = bnxt_promiscuous_disable_op,
3319         .allmulticast_enable = bnxt_allmulticast_enable_op,
3320         .allmulticast_disable = bnxt_allmulticast_disable_op,
3321         .mac_addr_add = bnxt_mac_addr_add_op,
3322         .mac_addr_remove = bnxt_mac_addr_remove_op,
3323         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3324         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3325         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3326         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3327         .vlan_filter_set = bnxt_vlan_filter_set_op,
3328         .vlan_offload_set = bnxt_vlan_offload_set_op,
3329         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3330         .mtu_set = bnxt_mtu_set_op,
3331         .mac_addr_set = bnxt_set_default_mac_addr_op,
3332         .xstats_get = bnxt_dev_xstats_get_op,
3333         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3334         .xstats_reset = bnxt_dev_xstats_reset_op,
3335         .fw_version_get = bnxt_fw_version_get,
3336         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3337         .rxq_info_get = bnxt_rxq_info_get_op,
3338         .txq_info_get = bnxt_txq_info_get_op,
3339         .dev_led_on = bnxt_dev_led_on_op,
3340         .dev_led_off = bnxt_dev_led_off_op,
3341         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3342         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3343         .rx_queue_count = bnxt_rx_queue_count_op,
3344         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3345         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3346         .rx_queue_start = bnxt_rx_queue_start,
3347         .rx_queue_stop = bnxt_rx_queue_stop,
3348         .tx_queue_start = bnxt_tx_queue_start,
3349         .tx_queue_stop = bnxt_tx_queue_stop,
3350         .filter_ctrl = bnxt_filter_ctrl_op,
3351         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3352         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3353         .get_eeprom           = bnxt_get_eeprom_op,
3354         .set_eeprom           = bnxt_set_eeprom_op,
3355         .timesync_enable      = bnxt_timesync_enable,
3356         .timesync_disable     = bnxt_timesync_disable,
3357         .timesync_read_time   = bnxt_timesync_read_time,
3358         .timesync_write_time   = bnxt_timesync_write_time,
3359         .timesync_adjust_time = bnxt_timesync_adjust_time,
3360         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3361         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3362 };
3363
3364 static bool bnxt_vf_pciid(uint16_t id)
3365 {
3366         if (id == BROADCOM_DEV_ID_57304_VF ||
3367             id == BROADCOM_DEV_ID_57406_VF ||
3368             id == BROADCOM_DEV_ID_5731X_VF ||
3369             id == BROADCOM_DEV_ID_5741X_VF ||
3370             id == BROADCOM_DEV_ID_57414_VF ||
3371             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3372             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3373             id == BROADCOM_DEV_ID_58802_VF ||
3374             id == BROADCOM_DEV_ID_57500_VF)
3375                 return true;
3376         return false;
3377 }
3378
3379 bool bnxt_stratus_device(struct bnxt *bp)
3380 {
3381         uint16_t id = bp->pdev->id.device_id;
3382
3383         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3384             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3385             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3386                 return true;
3387         return false;
3388 }
3389
3390 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3391 {
3392         struct bnxt *bp = eth_dev->data->dev_private;
3393         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3394         int rc;
3395
3396         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3397         if (!pci_dev->mem_resource[0].addr) {
3398                 PMD_DRV_LOG(ERR,
3399                         "Cannot find PCI device base address, aborting\n");
3400                 rc = -ENODEV;
3401                 goto init_err_disable;
3402         }
3403
3404         bp->eth_dev = eth_dev;
3405         bp->pdev = pci_dev;
3406
3407         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3408         if (!bp->bar0) {
3409                 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3410                 rc = -ENOMEM;
3411                 goto init_err_release;
3412         }
3413
3414         if (!pci_dev->mem_resource[2].addr) {
3415                 PMD_DRV_LOG(ERR,
3416                             "Cannot find PCI device BAR 2 address, aborting\n");
3417                 rc = -ENODEV;
3418                 goto init_err_release;
3419         } else {
3420                 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3421         }
3422
3423         return 0;
3424
3425 init_err_release:
3426         if (bp->bar0)
3427                 bp->bar0 = NULL;
3428         if (bp->doorbell_base)
3429                 bp->doorbell_base = NULL;
3430
3431 init_err_disable:
3432
3433         return rc;
3434 }
3435
3436 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3437                                   struct bnxt_ctx_pg_info *ctx_pg,
3438                                   uint32_t mem_size,
3439                                   const char *suffix,
3440                                   uint16_t idx)
3441 {
3442         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3443         const struct rte_memzone *mz = NULL;
3444         char mz_name[RTE_MEMZONE_NAMESIZE];
3445         rte_iova_t mz_phys_addr;
3446         uint64_t valid_bits = 0;
3447         uint32_t sz;
3448         int i;
3449
3450         if (!mem_size)
3451                 return 0;
3452
3453         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3454                          BNXT_PAGE_SIZE;
3455         rmem->page_size = BNXT_PAGE_SIZE;
3456         rmem->pg_arr = ctx_pg->ctx_pg_arr;
3457         rmem->dma_arr = ctx_pg->ctx_dma_arr;
3458         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3459
3460         valid_bits = PTU_PTE_VALID;
3461
3462         if (rmem->nr_pages > 1) {
3463                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_pg_tbl%s_%x",
3464                          suffix, idx);
3465                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3466                 mz = rte_memzone_lookup(mz_name);
3467                 if (!mz) {
3468                         mz = rte_memzone_reserve_aligned(mz_name,
3469                                                 rmem->nr_pages * 8,
3470                                                 SOCKET_ID_ANY,
3471                                                 RTE_MEMZONE_2MB |
3472                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
3473                                                 RTE_MEMZONE_IOVA_CONTIG,
3474                                                 BNXT_PAGE_SIZE);
3475                         if (mz == NULL)
3476                                 return -ENOMEM;
3477                 }
3478
3479                 memset(mz->addr, 0, mz->len);
3480                 mz_phys_addr = mz->iova;
3481                 if ((unsigned long)mz->addr == mz_phys_addr) {
3482                         PMD_DRV_LOG(WARNING,
3483                                 "Memzone physical address same as virtual.\n");
3484                         PMD_DRV_LOG(WARNING,
3485                                     "Using rte_mem_virt2iova()\n");
3486                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3487                         if (mz_phys_addr == RTE_BAD_IOVA) {
3488                                 PMD_DRV_LOG(ERR,
3489                                         "unable to map addr to phys memory\n");
3490                                 return -ENOMEM;
3491                         }
3492                 }
3493                 rte_mem_lock_page(((char *)mz->addr));
3494
3495                 rmem->pg_tbl = mz->addr;
3496                 rmem->pg_tbl_map = mz_phys_addr;
3497                 rmem->pg_tbl_mz = mz;
3498         }
3499
3500         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x", suffix, idx);
3501         mz = rte_memzone_lookup(mz_name);
3502         if (!mz) {
3503                 mz = rte_memzone_reserve_aligned(mz_name,
3504                                                  mem_size,
3505                                                  SOCKET_ID_ANY,
3506                                                  RTE_MEMZONE_1GB |
3507                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
3508                                                  RTE_MEMZONE_IOVA_CONTIG,
3509                                                  BNXT_PAGE_SIZE);
3510                 if (mz == NULL)
3511                         return -ENOMEM;
3512         }
3513
3514         memset(mz->addr, 0, mz->len);
3515         mz_phys_addr = mz->iova;
3516         if ((unsigned long)mz->addr == mz_phys_addr) {
3517                 PMD_DRV_LOG(WARNING,
3518                             "Memzone physical address same as virtual.\n");
3519                 PMD_DRV_LOG(WARNING,
3520                             "Using rte_mem_virt2iova()\n");
3521                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
3522                         rte_mem_lock_page(((char *)mz->addr) + sz);
3523                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3524                 if (mz_phys_addr == RTE_BAD_IOVA) {
3525                         PMD_DRV_LOG(ERR,
3526                                     "unable to map addr to phys memory\n");
3527                         return -ENOMEM;
3528                 }
3529         }
3530
3531         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
3532                 rte_mem_lock_page(((char *)mz->addr) + sz);
3533                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
3534                 rmem->dma_arr[i] = mz_phys_addr + sz;
3535
3536                 if (rmem->nr_pages > 1) {
3537                         if (i == rmem->nr_pages - 2 &&
3538                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3539                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
3540                         else if (i == rmem->nr_pages - 1 &&
3541                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3542                                 valid_bits |= PTU_PTE_LAST;
3543
3544                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
3545                                                            valid_bits);
3546                 }
3547         }
3548
3549         rmem->mz = mz;
3550         if (rmem->vmem_size)
3551                 rmem->vmem = (void **)mz->addr;
3552         rmem->dma_arr[0] = mz_phys_addr;
3553         return 0;
3554 }
3555
3556 static void bnxt_free_ctx_mem(struct bnxt *bp)
3557 {
3558         int i;
3559
3560         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
3561                 return;
3562
3563         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
3564         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
3565         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
3566         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
3567         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
3568         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
3569         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
3570         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
3571         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
3572         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
3573         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
3574
3575         for (i = 0; i < BNXT_MAX_Q; i++) {
3576                 if (bp->ctx->tqm_mem[i])
3577                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
3578         }
3579
3580         rte_free(bp->ctx);
3581         bp->ctx = NULL;
3582 }
3583
3584 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
3585
3586 #define min_t(type, x, y) ({                    \
3587         type __min1 = (x);                      \
3588         type __min2 = (y);                      \
3589         __min1 < __min2 ? __min1 : __min2; })
3590
3591 #define max_t(type, x, y) ({                    \
3592         type __max1 = (x);                      \
3593         type __max2 = (y);                      \
3594         __max1 > __max2 ? __max1 : __max2; })
3595
3596 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
3597
3598 int bnxt_alloc_ctx_mem(struct bnxt *bp)
3599 {
3600         struct bnxt_ctx_pg_info *ctx_pg;
3601         struct bnxt_ctx_mem_info *ctx;
3602         uint32_t mem_size, ena, entries;
3603         int i, rc;
3604
3605         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
3606         if (rc) {
3607                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
3608                 return rc;
3609         }
3610         ctx = bp->ctx;
3611         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
3612                 return 0;
3613
3614         ctx_pg = &ctx->qp_mem;
3615         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
3616         mem_size = ctx->qp_entry_size * ctx_pg->entries;
3617         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
3618         if (rc)
3619                 return rc;
3620
3621         ctx_pg = &ctx->srq_mem;
3622         ctx_pg->entries = ctx->srq_max_l2_entries;
3623         mem_size = ctx->srq_entry_size * ctx_pg->entries;
3624         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
3625         if (rc)
3626                 return rc;
3627
3628         ctx_pg = &ctx->cq_mem;
3629         ctx_pg->entries = ctx->cq_max_l2_entries;
3630         mem_size = ctx->cq_entry_size * ctx_pg->entries;
3631         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
3632         if (rc)
3633                 return rc;
3634
3635         ctx_pg = &ctx->vnic_mem;
3636         ctx_pg->entries = ctx->vnic_max_vnic_entries +
3637                 ctx->vnic_max_ring_table_entries;
3638         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
3639         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
3640         if (rc)
3641                 return rc;
3642
3643         ctx_pg = &ctx->stat_mem;
3644         ctx_pg->entries = ctx->stat_max_entries;
3645         mem_size = ctx->stat_entry_size * ctx_pg->entries;
3646         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
3647         if (rc)
3648                 return rc;
3649
3650         entries = ctx->qp_max_l2_entries;
3651         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
3652         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
3653                           ctx->tqm_max_entries_per_ring);
3654         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
3655                 ctx_pg = ctx->tqm_mem[i];
3656                 /* use min tqm entries for now. */
3657                 ctx_pg->entries = entries;
3658                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
3659                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
3660                 if (rc)
3661                         return rc;
3662                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
3663         }
3664
3665         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
3666         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
3667         if (rc)
3668                 PMD_DRV_LOG(ERR,
3669                             "Failed to configure context mem: rc = %d\n", rc);
3670         else
3671                 ctx->flags |= BNXT_CTX_FLAG_INITED;
3672
3673         return 0;
3674 }
3675
3676 static int bnxt_alloc_stats_mem(struct bnxt *bp)
3677 {
3678         struct rte_pci_device *pci_dev = bp->pdev;
3679         char mz_name[RTE_MEMZONE_NAMESIZE];
3680         const struct rte_memzone *mz = NULL;
3681         uint32_t total_alloc_len;
3682         rte_iova_t mz_phys_addr;
3683
3684         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
3685                 return 0;
3686
3687         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3688                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3689                  pci_dev->addr.bus, pci_dev->addr.devid,
3690                  pci_dev->addr.function, "rx_port_stats");
3691         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3692         mz = rte_memzone_lookup(mz_name);
3693         total_alloc_len =
3694                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
3695                                        sizeof(struct rx_port_stats_ext) + 512);
3696         if (!mz) {
3697                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3698                                          SOCKET_ID_ANY,
3699                                          RTE_MEMZONE_2MB |
3700                                          RTE_MEMZONE_SIZE_HINT_ONLY |
3701                                          RTE_MEMZONE_IOVA_CONTIG);
3702                 if (mz == NULL)
3703                         return -ENOMEM;
3704         }
3705         memset(mz->addr, 0, mz->len);
3706         mz_phys_addr = mz->iova;
3707         if ((unsigned long)mz->addr == mz_phys_addr) {
3708                 PMD_DRV_LOG(WARNING,
3709                             "Memzone physical address same as virtual.\n");
3710                 PMD_DRV_LOG(WARNING,
3711                             "Using rte_mem_virt2iova()\n");
3712                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3713                 if (mz_phys_addr == RTE_BAD_IOVA) {
3714                         PMD_DRV_LOG(ERR,
3715                                     "Can't map address to physical memory\n");
3716                         return -ENOMEM;
3717                 }
3718         }
3719
3720         bp->rx_mem_zone = (const void *)mz;
3721         bp->hw_rx_port_stats = mz->addr;
3722         bp->hw_rx_port_stats_map = mz_phys_addr;
3723
3724         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3725                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3726                  pci_dev->addr.bus, pci_dev->addr.devid,
3727                  pci_dev->addr.function, "tx_port_stats");
3728         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3729         mz = rte_memzone_lookup(mz_name);
3730         total_alloc_len =
3731                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
3732                                        sizeof(struct tx_port_stats_ext) + 512);
3733         if (!mz) {
3734                 mz = rte_memzone_reserve(mz_name,
3735                                          total_alloc_len,
3736                                          SOCKET_ID_ANY,
3737                                          RTE_MEMZONE_2MB |
3738                                          RTE_MEMZONE_SIZE_HINT_ONLY |
3739                                          RTE_MEMZONE_IOVA_CONTIG);
3740                 if (mz == NULL)
3741                         return -ENOMEM;
3742         }
3743         memset(mz->addr, 0, mz->len);
3744         mz_phys_addr = mz->iova;
3745         if ((unsigned long)mz->addr == mz_phys_addr) {
3746                 PMD_DRV_LOG(WARNING,
3747                             "Memzone physical address same as virtual\n");
3748                 PMD_DRV_LOG(WARNING,
3749                             "Using rte_mem_virt2iova()\n");
3750                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3751                 if (mz_phys_addr == RTE_BAD_IOVA) {
3752                         PMD_DRV_LOG(ERR,
3753                                     "Can't map address to physical memory\n");
3754                         return -ENOMEM;
3755                 }
3756         }
3757
3758         bp->tx_mem_zone = (const void *)mz;
3759         bp->hw_tx_port_stats = mz->addr;
3760         bp->hw_tx_port_stats_map = mz_phys_addr;
3761         bp->flags |= BNXT_FLAG_PORT_STATS;
3762
3763         /* Display extended statistics if FW supports it */
3764         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3765             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
3766             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
3767                 return 0;
3768
3769         bp->hw_rx_port_stats_ext = (void *)
3770                 ((uint8_t *)bp->hw_rx_port_stats +
3771                  sizeof(struct rx_port_stats));
3772         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3773                 sizeof(struct rx_port_stats);
3774         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3775
3776         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
3777             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
3778                 bp->hw_tx_port_stats_ext = (void *)
3779                         ((uint8_t *)bp->hw_tx_port_stats +
3780                          sizeof(struct tx_port_stats));
3781                 bp->hw_tx_port_stats_ext_map =
3782                         bp->hw_tx_port_stats_map +
3783                         sizeof(struct tx_port_stats);
3784                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3785         }
3786
3787         return 0;
3788 }
3789
3790 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
3791 {
3792         struct bnxt *bp = eth_dev->data->dev_private;
3793         int rc = 0;
3794
3795         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3796                                                RTE_ETHER_ADDR_LEN *
3797                                                bp->max_l2_ctx,
3798                                                0);
3799         if (eth_dev->data->mac_addrs == NULL) {
3800                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
3801                 return -ENOMEM;
3802         }
3803
3804         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
3805                 if (BNXT_PF(bp))
3806                         return -EINVAL;
3807
3808                 /* Generate a random MAC address, if none was assigned by PF */
3809                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
3810                 bnxt_eth_hw_addr_random(bp->mac_addr);
3811                 PMD_DRV_LOG(INFO,
3812                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
3813                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
3814                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
3815
3816                 rc = bnxt_hwrm_set_mac(bp);
3817                 if (!rc)
3818                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
3819                                RTE_ETHER_ADDR_LEN);
3820                 return rc;
3821         }
3822
3823         /* Copy the permanent MAC from the FUNC_QCAPS response */
3824         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
3825         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
3826
3827         return rc;
3828 }
3829
3830 #define ALLOW_FUNC(x)   \
3831         { \
3832                 uint32_t arg = (x); \
3833                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3834                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3835         }
3836 static int
3837 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3838 {
3839         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3840         static int version_printed;
3841         struct bnxt *bp;
3842         uint16_t mtu;
3843         int rc;
3844
3845         if (version_printed++ == 0)
3846                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3847
3848         rte_eth_copy_pci_info(eth_dev, pci_dev);
3849
3850         bp = eth_dev->data->dev_private;
3851
3852         bp->dev_stopped = 1;
3853
3854         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3855                 goto skip_init;
3856
3857         if (bnxt_vf_pciid(pci_dev->id.device_id))
3858                 bp->flags |= BNXT_FLAG_VF;
3859
3860         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
3861             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
3862             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
3863             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF)
3864                 bp->flags |= BNXT_FLAG_THOR_CHIP;
3865
3866         rc = bnxt_init_board(eth_dev);
3867         if (rc) {
3868                 PMD_DRV_LOG(ERR,
3869                         "Board initialization failed rc: %x\n", rc);
3870                 goto error;
3871         }
3872 skip_init:
3873         eth_dev->dev_ops = &bnxt_dev_ops;
3874         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3875         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3876         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3877                 return 0;
3878
3879         rc = bnxt_alloc_hwrm_resources(bp);
3880         if (rc) {
3881                 PMD_DRV_LOG(ERR,
3882                         "hwrm resource allocation failure rc: %x\n", rc);
3883                 goto error_free;
3884         }
3885         rc = bnxt_hwrm_ver_get(bp);
3886         if (rc)
3887                 goto error_free;
3888
3889         rc = bnxt_hwrm_func_reset(bp);
3890         if (rc) {
3891                 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3892                 rc = -EIO;
3893                 goto error_free;
3894         }
3895
3896         rc = bnxt_hwrm_queue_qportcfg(bp);
3897         if (rc) {
3898                 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3899                 goto error_free;
3900         }
3901         /* Get the MAX capabilities for this function */
3902         rc = bnxt_hwrm_func_qcaps(bp);
3903         if (rc) {
3904                 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3905                 goto error_free;
3906         }
3907
3908         rc = bnxt_alloc_stats_mem(bp);
3909         if (rc)
3910                 goto error_free;
3911
3912         if (bp->max_tx_rings == 0) {
3913                 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3914                 rc = -EBUSY;
3915                 goto error_free;
3916         }
3917
3918         rc = bnxt_setup_mac_addr(eth_dev);
3919         if (rc)
3920                 goto error_free;
3921
3922         /* THOR does not support ring groups.
3923          * But we will use the array to save RSS context IDs.
3924          */
3925         if (BNXT_CHIP_THOR(bp)) {
3926                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
3927         } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3928                 /* 1 ring is for default completion ring */
3929                 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3930                 rc = -ENOSPC;
3931                 goto error_free;
3932         }
3933
3934         if (BNXT_HAS_RING_GRPS(bp)) {
3935                 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3936                                         sizeof(*bp->grp_info) *
3937                                                 bp->max_ring_grps, 0);
3938                 if (!bp->grp_info) {
3939                         PMD_DRV_LOG(ERR,
3940                                 "Failed to alloc %zu bytes for grp info tbl.\n",
3941                                 sizeof(*bp->grp_info) * bp->max_ring_grps);
3942                         rc = -ENOMEM;
3943                         goto error_free;
3944                 }
3945         }
3946
3947         /* Forward all requests if firmware is new enough */
3948         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3949             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3950             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3951                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3952         } else {
3953                 PMD_DRV_LOG(WARNING,
3954                         "Firmware too old for VF mailbox functionality\n");
3955                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3956         }
3957
3958         /*
3959          * The following are used for driver cleanup.  If we disallow these,
3960          * VF drivers can't clean up cleanly.
3961          */
3962         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3963         ALLOW_FUNC(HWRM_VNIC_FREE);
3964         ALLOW_FUNC(HWRM_RING_FREE);
3965         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3966         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3967         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3968         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3969         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3970         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3971         rc = bnxt_hwrm_func_driver_register(bp);
3972         if (rc) {
3973                 PMD_DRV_LOG(ERR,
3974                         "Failed to register driver");
3975                 rc = -EBUSY;
3976                 goto error_free;
3977         }
3978
3979         PMD_DRV_LOG(INFO,
3980                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3981                 pci_dev->mem_resource[0].phys_addr,
3982                 pci_dev->mem_resource[0].addr);
3983
3984         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
3985         if (rc) {
3986                 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3987                 goto error_free;
3988         }
3989
3990         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
3991             mtu != eth_dev->data->mtu)
3992                 eth_dev->data->mtu = mtu;
3993
3994         if (BNXT_PF(bp)) {
3995                 //if (bp->pf.active_vfs) {
3996                         // TODO: Deallocate VF resources?
3997                 //}
3998                 if (bp->pdev->max_vfs) {
3999                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4000                         if (rc) {
4001                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4002                                 goto error_free;
4003                         }
4004                 } else {
4005                         rc = bnxt_hwrm_allocate_pf_only(bp);
4006                         if (rc) {
4007                                 PMD_DRV_LOG(ERR,
4008                                         "Failed to allocate PF resources\n");
4009                                 goto error_free;
4010                         }
4011                 }
4012         }
4013
4014         bnxt_hwrm_port_led_qcaps(bp);
4015
4016         rc = bnxt_setup_int(bp);
4017         if (rc)
4018                 goto error_free;
4019
4020         rc = bnxt_alloc_mem(bp);
4021         if (rc)
4022                 goto error_free_int;
4023
4024         rc = bnxt_request_int(bp);
4025         if (rc)
4026                 goto error_free_int;
4027
4028         bnxt_init_nic(bp);
4029
4030         return 0;
4031
4032 error_free_int:
4033         bnxt_disable_int(bp);
4034         bnxt_hwrm_func_buf_unrgtr(bp);
4035         bnxt_free_int(bp);
4036         bnxt_free_mem(bp);
4037 error_free:
4038         bnxt_dev_uninit(eth_dev);
4039 error:
4040         return rc;
4041 }
4042
4043 static int
4044 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4045 {
4046         struct bnxt *bp = eth_dev->data->dev_private;
4047         int rc;
4048
4049         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4050                 return -EPERM;
4051
4052         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4053         bnxt_disable_int(bp);
4054         bnxt_free_int(bp);
4055         bnxt_free_mem(bp);
4056         if (bp->grp_info != NULL) {
4057                 rte_free(bp->grp_info);
4058                 bp->grp_info = NULL;
4059         }
4060         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4061         bnxt_free_hwrm_resources(bp);
4062
4063         if (bp->tx_mem_zone) {
4064                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4065                 bp->tx_mem_zone = NULL;
4066         }
4067
4068         if (bp->rx_mem_zone) {
4069                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4070                 bp->rx_mem_zone = NULL;
4071         }
4072
4073         if (bp->dev_stopped == 0)
4074                 bnxt_dev_close_op(eth_dev);
4075         if (bp->pf.vf_info)
4076                 rte_free(bp->pf.vf_info);
4077         bnxt_free_ctx_mem(bp);
4078         eth_dev->dev_ops = NULL;
4079         eth_dev->rx_pkt_burst = NULL;
4080         eth_dev->tx_pkt_burst = NULL;
4081
4082         return rc;
4083 }
4084
4085 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4086         struct rte_pci_device *pci_dev)
4087 {
4088         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4089                 bnxt_dev_init);
4090 }
4091
4092 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4093 {
4094         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4095                 return rte_eth_dev_pci_generic_remove(pci_dev,
4096                                 bnxt_dev_uninit);
4097         else
4098                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4099 }
4100
4101 static struct rte_pci_driver bnxt_rte_pmd = {
4102         .id_table = bnxt_pci_id_map,
4103         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4104         .probe = bnxt_pci_probe,
4105         .remove = bnxt_pci_remove,
4106 };
4107
4108 static bool
4109 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4110 {
4111         if (strcmp(dev->device->driver->name, drv->driver.name))
4112                 return false;
4113
4114         return true;
4115 }
4116
4117 bool is_bnxt_supported(struct rte_eth_dev *dev)
4118 {
4119         return is_device_supported(dev, &bnxt_rte_pmd);
4120 }
4121
4122 RTE_INIT(bnxt_init_log)
4123 {
4124         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4125         if (bnxt_logtype_driver >= 0)
4126                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4127 }
4128
4129 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4130 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4131 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");