drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_cpr.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30 #include "bnxt_util.h"
  31
  32 #define DRV_MODULE_NAME         "bnxt"
  33 static const char bnxt_version[] =
  34         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  35 int bnxt_logtype_driver;
  36
  37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  38
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  43 #define BROADCOM_DEV_ID_57301 0x16c8
  44 #define BROADCOM_DEV_ID_57302 0x16c9
  45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  48 #define BROADCOM_DEV_ID_NS2 0x16cd
  49 #define BROADCOM_DEV_ID_57311 0x16ce
  50 #define BROADCOM_DEV_ID_57312 0x16cf
  51 #define BROADCOM_DEV_ID_57402 0x16d0
  52 #define BROADCOM_DEV_ID_57404 0x16d1
  53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  57 #define BROADCOM_DEV_ID_57412 0x16d6
  58 #define BROADCOM_DEV_ID_57414 0x16d7
  59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  62 #define BROADCOM_DEV_ID_57412_MF 0x16de
  63 #define BROADCOM_DEV_ID_57314 0x16df
  64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  75 #define BROADCOM_DEV_ID_57508 0x1750
  76 #define BROADCOM_DEV_ID_57504 0x1751
  77 #define BROADCOM_DEV_ID_57502 0x1752
  78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
  79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
  80 #define BROADCOM_DEV_ID_58802 0xd802
  81 #define BROADCOM_DEV_ID_58804 0xd804
  82 #define BROADCOM_DEV_ID_58808 0x16f0
  83 #define BROADCOM_DEV_ID_58802_VF 0xd800
  84
  85 static const struct rte_pci_id bnxt_pci_id_map[] = {
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  87                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  89                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 130         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 131         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
 132         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
 133         { .vendor_id = 0, /* sentinel */ },
 134 };
 135
 136 #define BNXT_ETH_RSS_SUPPORT (  \
 137         ETH_RSS_IPV4 |          \
 138         ETH_RSS_NONFRAG_IPV4_TCP |      \
 139         ETH_RSS_NONFRAG_IPV4_UDP |      \
 140         ETH_RSS_IPV6 |          \
 141         ETH_RSS_NONFRAG_IPV6_TCP |      \
 142         ETH_RSS_NONFRAG_IPV6_UDP)
 143
 144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 145                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 146                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 147                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 148                                      DEV_TX_OFFLOAD_TCP_TSO | \
 149                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 150                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 152                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 153                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 154                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 155
 156 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 157                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 158                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 159                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 160                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 161                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 162                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 163                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 164                                      DEV_RX_OFFLOAD_TCP_LRO)
 165
 166 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 167 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 168 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 169 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 170 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 171 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 172 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 173
 174 int is_bnxt_in_error(struct bnxt *bp)
 175 {
 176         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 177                 return -EIO;
 178         if (bp->flags & BNXT_FLAG_FW_RESET)
 179                 return -EBUSY;
 180
 181         return 0;
 182 }
 183
 184 /***********************/
 185
 186 /*
 187  * High level utility functions
 188  */
 189
 190 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 191 {
 192         if (!BNXT_CHIP_THOR(bp))
 193                 return 1;
 194
 195         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 196                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 197                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 198 }
 199
 200 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 201 {
 202         if (!BNXT_CHIP_THOR(bp))
 203                 return HW_HASH_INDEX_SIZE;
 204
 205         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 206 }
 207
 208 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 209 {
 210         bnxt_free_filter_mem(bp);
 211         bnxt_free_vnic_attributes(bp);
 212         bnxt_free_vnic_mem(bp);
 213
 214         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 215          * If the number of rings change across fw update,
 216          * we don't have much choice except to warn the user.
 217          */
 218         if (!reconfig) {
 219                 bnxt_free_stats(bp);
 220                 bnxt_free_tx_rings(bp);
 221                 bnxt_free_rx_rings(bp);
 222         }
 223         bnxt_free_async_cp_ring(bp);
 224 }
 225
 226 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 227 {
 228         int rc;
 229
 230         rc = bnxt_alloc_ring_grps(bp);
 231         if (rc)
 232                 goto alloc_mem_err;
 233
 234         rc = bnxt_alloc_async_ring_struct(bp);
 235         if (rc)
 236                 goto alloc_mem_err;
 237
 238         rc = bnxt_alloc_vnic_mem(bp);
 239         if (rc)
 240                 goto alloc_mem_err;
 241
 242         rc = bnxt_alloc_vnic_attributes(bp);
 243         if (rc)
 244                 goto alloc_mem_err;
 245
 246         rc = bnxt_alloc_filter_mem(bp);
 247         if (rc)
 248                 goto alloc_mem_err;
 249
 250         rc = bnxt_alloc_async_cp_ring(bp);
 251         if (rc)
 252                 goto alloc_mem_err;
 253
 254         return 0;
 255
 256 alloc_mem_err:
 257         bnxt_free_mem(bp, reconfig);
 258         return rc;
 259 }
 260
 261 static int bnxt_init_chip(struct bnxt *bp)
 262 {
 263         struct bnxt_rx_queue *rxq;
 264         struct rte_eth_link new;
 265         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 266         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 267         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 268         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 269         uint32_t intr_vector = 0;
 270         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 271         uint32_t vec = BNXT_MISC_VEC_ID;
 272         unsigned int i, j;
 273         int rc;
 274
 275         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 276                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 277                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 278                 bp->flags |= BNXT_FLAG_JUMBO;
 279         } else {
 280                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 281                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 282                 bp->flags &= ~BNXT_FLAG_JUMBO;
 283         }
 284
 285         /* THOR does not support ring groups.
 286          * But we will use the array to save RSS context IDs.
 287          */
 288         if (BNXT_CHIP_THOR(bp))
 289                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 290
 291         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 292         if (rc) {
 293                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 294                 goto err_out;
 295         }
 296
 297         rc = bnxt_alloc_hwrm_rings(bp);
 298         if (rc) {
 299                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 300                 goto err_out;
 301         }
 302
 303         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 304         if (rc) {
 305                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 306                 goto err_out;
 307         }
 308
 309         rc = bnxt_mq_rx_configure(bp);
 310         if (rc) {
 311                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 312                 goto err_out;
 313         }
 314
 315         /* VNIC configuration */
 316         for (i = 0; i < bp->nr_vnics; i++) {
 317                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 318                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 319                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 320
 321                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 322                 if (!vnic->fw_grp_ids) {
 323                         PMD_DRV_LOG(ERR,
 324                                     "Failed to alloc %d bytes for group ids\n",
 325                                     size);
 326                         rc = -ENOMEM;
 327                         goto err_out;
 328                 }
 329                 memset(vnic->fw_grp_ids, -1, size);
 330
 331                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 332                             i, vnic, vnic->fw_grp_ids);
 333
 334                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 335                 if (rc) {
 336                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 337                                 i, rc);
 338                         goto err_out;
 339                 }
 340
 341                 /* Alloc RSS context only if RSS mode is enabled */
 342                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 343                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 344
 345                         rc = 0;
 346                         for (j = 0; j < nr_ctxs; j++) {
 347                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 348                                 if (rc)
 349                                         break;
 350                         }
 351                         if (rc) {
 352                                 PMD_DRV_LOG(ERR,
 353                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 354                                   i, j, rc);
 355                                 goto err_out;
 356                         }
 357                         vnic->num_lb_ctxts = nr_ctxs;
 358                 }
 359
 360                 /*
 361                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 362                  * setting is not available at this time, it will not be
 363                  * configured correctly in the CFA.
 364                  */
 365                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 366                         vnic->vlan_strip = true;
 367                 else
 368                         vnic->vlan_strip = false;
 369
 370                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 371                 if (rc) {
 372                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 373                                 i, rc);
 374                         goto err_out;
 375                 }
 376
 377                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 378                 if (rc) {
 379                         PMD_DRV_LOG(ERR,
 380                                 "HWRM vnic %d filter failure rc: %x\n",
 381                                 i, rc);
 382                         goto err_out;
 383                 }
 384
 385                 for (j = 0; j < bp->rx_nr_rings; j++) {
 386                         rxq = bp->eth_dev->data->rx_queues[j];
 387
 388                         PMD_DRV_LOG(DEBUG,
 389                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 390                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 391
 392                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 393                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 394                 }
 395
 396                 rc = bnxt_vnic_rss_configure(bp, vnic);
 397                 if (rc) {
 398                         PMD_DRV_LOG(ERR,
 399                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 400                         goto err_out;
 401                 }
 402
 403                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 404
 405                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 406                     DEV_RX_OFFLOAD_TCP_LRO)
 407                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 408                 else
 409                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 410         }
 411         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 412         if (rc) {
 413                 PMD_DRV_LOG(ERR,
 414                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 415                 goto err_out;
 416         }
 417
 418         /* check and configure queue intr-vector mapping */
 419         if ((rte_intr_cap_multiple(intr_handle) ||
 420              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 421             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 422                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 423                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 424                 if (intr_vector > bp->rx_cp_nr_rings) {
 425                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 426                                         bp->rx_cp_nr_rings);
 427                         return -ENOTSUP;
 428                 }
 429                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 430                 if (rc)
 431                         return rc;
 432         }
 433
 434         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 435                 intr_handle->intr_vec =
 436                         rte_zmalloc("intr_vec",
 437                                     bp->eth_dev->data->nb_rx_queues *
 438                                     sizeof(int), 0);
 439                 if (intr_handle->intr_vec == NULL) {
 440                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 441                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 442                         rc = -ENOMEM;
 443                         goto err_disable;
 444                 }
 445                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 446                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 447                          intr_handle->intr_vec, intr_handle->nb_efd,
 448                         intr_handle->max_intr);
 449                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 450                      queue_id++) {
 451                         intr_handle->intr_vec[queue_id] =
 452                                                         vec + BNXT_RX_VEC_START;
 453                         if (vec < base + intr_handle->nb_efd - 1)
 454                                 vec++;
 455                 }
 456         }
 457
 458         /* enable uio/vfio intr/eventfd mapping */
 459         rc = rte_intr_enable(intr_handle);
 460         if (rc)
 461                 goto err_free;
 462
 463         rc = bnxt_get_hwrm_link_config(bp, &new);
 464         if (rc) {
 465                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 466                 goto err_free;
 467         }
 468
 469         if (!bp->link_info.link_up) {
 470                 rc = bnxt_set_hwrm_link_config(bp, true);
 471                 if (rc) {
 472                         PMD_DRV_LOG(ERR,
 473                                 "HWRM link config failure rc: %x\n", rc);
 474                         goto err_free;
 475                 }
 476         }
 477         bnxt_print_link_info(bp->eth_dev);
 478
 479         return 0;
 480
 481 err_free:
 482         rte_free(intr_handle->intr_vec);
 483 err_disable:
 484         rte_intr_efd_disable(intr_handle);
 485 err_out:
 486         /* Some of the error status returned by FW may not be from errno.h */
 487         if (rc > 0)
 488                 rc = -EIO;
 489
 490         return rc;
 491 }
 492
 493 static int bnxt_shutdown_nic(struct bnxt *bp)
 494 {
 495         bnxt_free_all_hwrm_resources(bp);
 496         bnxt_free_all_filters(bp);
 497         bnxt_free_all_vnics(bp);
 498         return 0;
 499 }
 500
 501 static int bnxt_init_nic(struct bnxt *bp)
 502 {
 503         int rc;
 504
 505         if (BNXT_HAS_RING_GRPS(bp)) {
 506                 rc = bnxt_init_ring_grps(bp);
 507                 if (rc)
 508                         return rc;
 509         }
 510
 511         bnxt_init_vnics(bp);
 512         bnxt_init_filters(bp);
 513
 514         return 0;
 515 }
 516
 517 /*
 518  * Device configuration and status function
 519  */
 520
 521 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 522                                 struct rte_eth_dev_info *dev_info)
 523 {
 524         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 525         struct bnxt *bp = eth_dev->data->dev_private;
 526         uint16_t max_vnics, i, j, vpool, vrxq;
 527         unsigned int max_rx_rings;
 528         int rc;
 529
 530         rc = is_bnxt_in_error(bp);
 531         if (rc)
 532                 return rc;
 533
 534         /* MAC Specifics */
 535         dev_info->max_mac_addrs = bp->max_l2_ctx;
 536         dev_info->max_hash_mac_addrs = 0;
 537
 538         /* PF/VF specifics */
 539         if (BNXT_PF(bp))
 540                 dev_info->max_vfs = pdev->max_vfs;
 541
 542         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 543         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 544         dev_info->max_rx_queues = max_rx_rings;
 545         dev_info->max_tx_queues = max_rx_rings;
 546         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 547         dev_info->hash_key_size = 40;
 548         max_vnics = bp->max_vnics;
 549
 550         /* MTU specifics */
 551         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 552         dev_info->max_mtu = BNXT_MAX_MTU;
 553
 554         /* Fast path specifics */
 555         dev_info->min_rx_bufsize = 1;
 556         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 557
 558         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 559         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 560                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 561         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 562         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 563
 564         /* *INDENT-OFF* */
 565         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 566                 .rx_thresh = {
 567                         .pthresh = 8,
 568                         .hthresh = 8,
 569                         .wthresh = 0,
 570                 },
 571                 .rx_free_thresh = 32,
 572                 /* If no descriptors available, pkts are dropped by default */
 573                 .rx_drop_en = 1,
 574         };
 575
 576         dev_info->default_txconf = (struct rte_eth_txconf) {
 577                 .tx_thresh = {
 578                         .pthresh = 32,
 579                         .hthresh = 0,
 580                         .wthresh = 0,
 581                 },
 582                 .tx_free_thresh = 32,
 583                 .tx_rs_thresh = 32,
 584         };
 585         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 586
 587         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 588         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 589         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 590         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 591         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 592
 593         /* *INDENT-ON* */
 594
 595         /*
 596          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 597          *       need further investigation.
 598          */
 599
 600         /* VMDq resources */
 601         vpool = 64; /* ETH_64_POOLS */
 602         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 603         for (i = 0; i < 4; vpool >>= 1, i++) {
 604                 if (max_vnics > vpool) {
 605                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 606                                 if (dev_info->max_rx_queues > vrxq) {
 607                                         if (vpool > vrxq)
 608                                                 vpool = vrxq;
 609                                         goto found;
 610                                 }
 611                         }
 612                         /* Not enough resources to support VMDq */
 613                         break;
 614                 }
 615         }
 616         /* Not enough resources to support VMDq */
 617         vpool = 0;
 618         vrxq = 0;
 619 found:
 620         dev_info->max_vmdq_pools = vpool;
 621         dev_info->vmdq_queue_num = vrxq;
 622
 623         dev_info->vmdq_pool_base = 0;
 624         dev_info->vmdq_queue_base = 0;
 625
 626         return 0;
 627 }
 628
 629 /* Configure the device based on the configuration provided */
 630 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 631 {
 632         struct bnxt *bp = eth_dev->data->dev_private;
 633         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 634         int rc;
 635
 636         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 637         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 638         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 639         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 640
 641         rc = is_bnxt_in_error(bp);
 642         if (rc)
 643                 return rc;
 644
 645         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 646                 rc = bnxt_hwrm_check_vf_rings(bp);
 647                 if (rc) {
 648                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 649                         return -ENOSPC;
 650                 }
 651
 652                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 653                 if (rc) {
 654                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 655                         return -ENOSPC;
 656                 }
 657         } else {
 658                 /* legacy driver needs to get updated values */
 659                 rc = bnxt_hwrm_func_qcaps(bp);
 660                 if (rc) {
 661                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 662                         return rc;
 663                 }
 664         }
 665
 666         /* Inherit new configurations */
 667         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 668             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 669             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 670                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 671             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 672             bp->max_stat_ctx)
 673                 goto resource_error;
 674
 675         if (BNXT_HAS_RING_GRPS(bp) &&
 676             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 677                 goto resource_error;
 678
 679         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 680             bp->max_vnics < eth_dev->data->nb_rx_queues)
 681                 goto resource_error;
 682
 683         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 684         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 685
 686         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 687                 eth_dev->data->mtu =
 688                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 689                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 690                         BNXT_NUM_VLANS;
 691                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 692         }
 693         return 0;
 694
 695 resource_error:
 696         PMD_DRV_LOG(ERR,
 697                     "Insufficient resources to support requested config\n");
 698         PMD_DRV_LOG(ERR,
 699                     "Num Queues Requested: Tx %d, Rx %d\n",
 700                     eth_dev->data->nb_tx_queues,
 701                     eth_dev->data->nb_rx_queues);
 702         PMD_DRV_LOG(ERR,
 703                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 704                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 705                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 706         return -ENOSPC;
 707 }
 708
 709 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 710 {
 711         struct rte_eth_link *link = &eth_dev->data->dev_link;
 712
 713         if (link->link_status)
 714                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 715                         eth_dev->data->port_id,
 716                         (uint32_t)link->link_speed,
 717                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 718                         ("full-duplex") : ("half-duplex\n"));
 719         else
 720                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 721                         eth_dev->data->port_id);
 722 }
 723
 724 /*
 725  * Determine whether the current configuration requires support for scattered
 726  * receive; return 1 if scattered receive is required and 0 if not.
 727  */
 728 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 729 {
 730         uint16_t buf_size;
 731         int i;
 732
 733         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 734                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 735
 736                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 737                                       RTE_PKTMBUF_HEADROOM);
 738                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 739                         return 1;
 740         }
 741         return 0;
 742 }
 743
 744 static eth_rx_burst_t
 745 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 746 {
 747 #ifdef RTE_ARCH_X86
 748 #ifndef RTE_LIBRTE_IEEE1588
 749         /*
 750          * Vector mode receive can be enabled only if scatter rx is not
 751          * in use and rx offloads are limited to VLAN stripping and
 752          * CRC stripping.
 753          */
 754         if (!eth_dev->data->scattered_rx &&
 755             !(eth_dev->data->dev_conf.rxmode.offloads &
 756               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 757                 DEV_RX_OFFLOAD_KEEP_CRC |
 758                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 759                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 760                 DEV_RX_OFFLOAD_UDP_CKSUM |
 761                 DEV_RX_OFFLOAD_TCP_CKSUM |
 762                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 763                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 764                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 765                             eth_dev->data->port_id);
 766                 return bnxt_recv_pkts_vec;
 767         }
 768         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 769                     eth_dev->data->port_id);
 770         PMD_DRV_LOG(INFO,
 771                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 772                     eth_dev->data->port_id,
 773                     eth_dev->data->scattered_rx,
 774                     eth_dev->data->dev_conf.rxmode.offloads);
 775 #endif
 776 #endif
 777         return bnxt_recv_pkts;
 778 }
 779
 780 static eth_tx_burst_t
 781 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 782 {
 783 #ifdef RTE_ARCH_X86
 784 #ifndef RTE_LIBRTE_IEEE1588
 785         /*
 786          * Vector mode transmit can be enabled only if not using scatter rx
 787          * or tx offloads.
 788          */
 789         if (!eth_dev->data->scattered_rx &&
 790             !eth_dev->data->dev_conf.txmode.offloads) {
 791                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 792                             eth_dev->data->port_id);
 793                 return bnxt_xmit_pkts_vec;
 794         }
 795         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 796                     eth_dev->data->port_id);
 797         PMD_DRV_LOG(INFO,
 798                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 799                     eth_dev->data->port_id,
 800                     eth_dev->data->scattered_rx,
 801                     eth_dev->data->dev_conf.txmode.offloads);
 802 #endif
 803 #endif
 804         return bnxt_xmit_pkts;
 805 }
 806
 807 static int bnxt_handle_if_change_status(struct bnxt *bp)
 808 {
 809         int rc;
 810
 811         /* Since fw has undergone a reset and lost all contexts,
 812          * set fatal flag to not issue hwrm during cleanup
 813          */
 814         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 815         bnxt_uninit_resources(bp, true);
 816
 817         /* clear fatal flag so that re-init happens */
 818         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 819         rc = bnxt_init_resources(bp, true);
 820
 821         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 822
 823         return rc;
 824 }
 825
 826 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 827 {
 828         struct bnxt *bp = eth_dev->data->dev_private;
 829         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 830         int vlan_mask = 0;
 831         int rc;
 832
 833         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 834                 PMD_DRV_LOG(ERR,
 835                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 836                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 837         }
 838
 839         bnxt_enable_int(bp);
 840         rc = bnxt_hwrm_if_change(bp, 1);
 841         if (!rc) {
 842                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 843                         rc = bnxt_handle_if_change_status(bp);
 844                         if (rc)
 845                                 return rc;
 846                 }
 847         }
 848
 849         rc = bnxt_init_chip(bp);
 850         if (rc)
 851                 goto error;
 852
 853         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 854
 855         bnxt_link_update_op(eth_dev, 1);
 856
 857         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 858                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 859         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 860                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 861         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 862         if (rc)
 863                 goto error;
 864
 865         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 866         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 867
 868         bp->flags |= BNXT_FLAG_INIT_DONE;
 869         eth_dev->data->dev_started = 1;
 870         bp->dev_stopped = 0;
 871         bnxt_schedule_fw_health_check(bp);
 872         return 0;
 873
 874 error:
 875         bnxt_hwrm_if_change(bp, 0);
 876         bnxt_shutdown_nic(bp);
 877         bnxt_free_tx_mbufs(bp);
 878         bnxt_free_rx_mbufs(bp);
 879         return rc;
 880 }
 881
 882 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 883 {
 884         struct bnxt *bp = eth_dev->data->dev_private;
 885         int rc = 0;
 886
 887         if (!bp->link_info.link_up)
 888                 rc = bnxt_set_hwrm_link_config(bp, true);
 889         if (!rc)
 890                 eth_dev->data->dev_link.link_status = 1;
 891
 892         bnxt_print_link_info(eth_dev);
 893         return 0;
 894 }
 895
 896 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 897 {
 898         struct bnxt *bp = eth_dev->data->dev_private;
 899
 900         eth_dev->data->dev_link.link_status = 0;
 901         bnxt_set_hwrm_link_config(bp, false);
 902         bp->link_info.link_up = 0;
 903
 904         return 0;
 905 }
 906
 907 /* Unload the driver, release resources */
 908 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 909 {
 910         struct bnxt *bp = eth_dev->data->dev_private;
 911         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 912         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 913
 914         eth_dev->data->dev_started = 0;
 915         /* Prevent crashes when queues are still in use */
 916         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 917         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 918
 919         bnxt_disable_int(bp);
 920
 921         /* disable uio/vfio intr/eventfd mapping */
 922         rte_intr_disable(intr_handle);
 923
 924         bnxt_cancel_fw_health_check(bp);
 925
 926         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 927         if (bp->eth_dev->data->dev_started) {
 928                 /* TBD: STOP HW queues DMA */
 929                 eth_dev->data->dev_link.link_status = 0;
 930         }
 931         bnxt_dev_set_link_down_op(eth_dev);
 932         /* Wait for link to be reset and the async notification to process. */
 933         rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
 934
 935         /* Clean queue intr-vector mapping */
 936         rte_intr_efd_disable(intr_handle);
 937         if (intr_handle->intr_vec != NULL) {
 938                 rte_free(intr_handle->intr_vec);
 939                 intr_handle->intr_vec = NULL;
 940         }
 941
 942         bnxt_hwrm_port_clr_stats(bp);
 943         bnxt_free_tx_mbufs(bp);
 944         bnxt_free_rx_mbufs(bp);
 945         /* Process any remaining notifications in default completion queue */
 946         bnxt_int_handler(eth_dev);
 947         bnxt_shutdown_nic(bp);
 948         bnxt_hwrm_if_change(bp, 0);
 949         bp->dev_stopped = 1;
 950 }
 951
 952 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 953 {
 954         struct bnxt *bp = eth_dev->data->dev_private;
 955
 956         if (bp->dev_stopped == 0)
 957                 bnxt_dev_stop_op(eth_dev);
 958
 959         if (eth_dev->data->mac_addrs != NULL) {
 960                 rte_free(eth_dev->data->mac_addrs);
 961                 eth_dev->data->mac_addrs = NULL;
 962         }
 963         if (bp->grp_info != NULL) {
 964                 rte_free(bp->grp_info);
 965                 bp->grp_info = NULL;
 966         }
 967
 968         bnxt_dev_uninit(eth_dev);
 969 }
 970
 971 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 972                                     uint32_t index)
 973 {
 974         struct bnxt *bp = eth_dev->data->dev_private;
 975         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 976         struct bnxt_vnic_info *vnic;
 977         struct bnxt_filter_info *filter, *temp_filter;
 978         uint32_t i;
 979
 980         if (is_bnxt_in_error(bp))
 981                 return;
 982
 983         /*
 984          * Loop through all VNICs from the specified filter flow pools to
 985          * remove the corresponding MAC addr filter
 986          */
 987         for (i = 0; i < bp->nr_vnics; i++) {
 988                 if (!(pool_mask & (1ULL << i)))
 989                         continue;
 990
 991                 vnic = &bp->vnic_info[i];
 992                 filter = STAILQ_FIRST(&vnic->filter);
 993                 while (filter) {
 994                         temp_filter = STAILQ_NEXT(filter, next);
 995                         if (filter->mac_index == index) {
 996                                 STAILQ_REMOVE(&vnic->filter, filter,
 997                                                 bnxt_filter_info, next);
 998                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 999                                 filter->mac_index = INVALID_MAC_INDEX;
1000                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1001                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1002                                                    filter, next);
1003                         }
1004                         filter = temp_filter;
1005                 }
1006         }
1007 }
1008
1009 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1010                                 struct rte_ether_addr *mac_addr,
1011                                 uint32_t index, uint32_t pool)
1012 {
1013         struct bnxt *bp = eth_dev->data->dev_private;
1014         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1015         struct bnxt_filter_info *filter;
1016         int rc = 0;
1017
1018         rc = is_bnxt_in_error(bp);
1019         if (rc)
1020                 return rc;
1021
1022         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1023                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1024                 return -ENOTSUP;
1025         }
1026
1027         if (!vnic) {
1028                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1029                 return -EINVAL;
1030         }
1031         /* Attach requested MAC address to the new l2_filter */
1032         STAILQ_FOREACH(filter, &vnic->filter, next) {
1033                 if (filter->mac_index == index) {
1034                         PMD_DRV_LOG(ERR,
1035                                 "MAC addr already existed for pool %d\n", pool);
1036                         return 0;
1037                 }
1038         }
1039         filter = bnxt_alloc_filter(bp);
1040         if (!filter) {
1041                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1042                 return -ENODEV;
1043         }
1044
1045         filter->mac_index = index;
1046         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1047
1048         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1049         if (!rc) {
1050                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1051         } else {
1052                 filter->mac_index = INVALID_MAC_INDEX;
1053                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1054                 bnxt_free_filter(bp, filter);
1055         }
1056
1057         return rc;
1058 }
1059
1060 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1061 {
1062         int rc = 0;
1063         struct bnxt *bp = eth_dev->data->dev_private;
1064         struct rte_eth_link new;
1065         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1066
1067         rc = is_bnxt_in_error(bp);
1068         if (rc)
1069                 return rc;
1070
1071         memset(&new, 0, sizeof(new));
1072         do {
1073                 /* Retrieve link info from hardware */
1074                 rc = bnxt_get_hwrm_link_config(bp, &new);
1075                 if (rc) {
1076                         new.link_speed = ETH_LINK_SPEED_100M;
1077                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1078                         PMD_DRV_LOG(ERR,
1079                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1080                         goto out;
1081                 }
1082
1083                 if (!wait_to_complete || new.link_status)
1084                         break;
1085
1086                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1087         } while (cnt--);
1088
1089 out:
1090         /* Timed out or success */
1091         if (new.link_status != eth_dev->data->dev_link.link_status ||
1092         new.link_speed != eth_dev->data->dev_link.link_speed) {
1093                 rte_eth_linkstatus_set(eth_dev, &new);
1094
1095                 _rte_eth_dev_callback_process(eth_dev,
1096                                               RTE_ETH_EVENT_INTR_LSC,
1097                                               NULL);
1098
1099                 bnxt_print_link_info(eth_dev);
1100         }
1101
1102         return rc;
1103 }
1104
1105 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1106 {
1107         struct bnxt *bp = eth_dev->data->dev_private;
1108         struct bnxt_vnic_info *vnic;
1109         uint32_t old_flags;
1110         int rc;
1111
1112         rc = is_bnxt_in_error(bp);
1113         if (rc)
1114                 return rc;
1115
1116         if (bp->vnic_info == NULL)
1117                 return 0;
1118
1119         vnic = &bp->vnic_info[0];
1120
1121         old_flags = vnic->flags;
1122         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1123         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1124         if (rc != 0)
1125                 vnic->flags = old_flags;
1126
1127         return rc;
1128 }
1129
1130 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1131 {
1132         struct bnxt *bp = eth_dev->data->dev_private;
1133         struct bnxt_vnic_info *vnic;
1134         uint32_t old_flags;
1135         int rc;
1136
1137         rc = is_bnxt_in_error(bp);
1138         if (rc)
1139                 return rc;
1140
1141         if (bp->vnic_info == NULL)
1142                 return 0;
1143
1144         vnic = &bp->vnic_info[0];
1145
1146         old_flags = vnic->flags;
1147         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1148         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1149         if (rc != 0)
1150                 vnic->flags = old_flags;
1151
1152         return rc;
1153 }
1154
1155 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1156 {
1157         struct bnxt *bp = eth_dev->data->dev_private;
1158         struct bnxt_vnic_info *vnic;
1159         uint32_t old_flags;
1160         int rc;
1161
1162         rc = is_bnxt_in_error(bp);
1163         if (rc)
1164                 return rc;
1165
1166         if (bp->vnic_info == NULL)
1167                 return 0;
1168
1169         vnic = &bp->vnic_info[0];
1170
1171         old_flags = vnic->flags;
1172         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1173         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1174         if (rc != 0)
1175                 vnic->flags = old_flags;
1176
1177         return rc;
1178 }
1179
1180 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1181 {
1182         struct bnxt *bp = eth_dev->data->dev_private;
1183         struct bnxt_vnic_info *vnic;
1184         uint32_t old_flags;
1185         int rc;
1186
1187         rc = is_bnxt_in_error(bp);
1188         if (rc)
1189                 return rc;
1190
1191         if (bp->vnic_info == NULL)
1192                 return 0;
1193
1194         vnic = &bp->vnic_info[0];
1195
1196         old_flags = vnic->flags;
1197         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1198         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1199         if (rc != 0)
1200                 vnic->flags = old_flags;
1201
1202         return rc;
1203 }
1204
1205 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1206 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1207 {
1208         if (qid >= bp->rx_nr_rings)
1209                 return NULL;
1210
1211         return bp->eth_dev->data->rx_queues[qid];
1212 }
1213
1214 /* Return rxq corresponding to a given rss table ring/group ID. */
1215 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1216 {
1217         struct bnxt_rx_queue *rxq;
1218         unsigned int i;
1219
1220         if (!BNXT_HAS_RING_GRPS(bp)) {
1221                 for (i = 0; i < bp->rx_nr_rings; i++) {
1222                         rxq = bp->eth_dev->data->rx_queues[i];
1223                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1224                                 return rxq->index;
1225                 }
1226         } else {
1227                 for (i = 0; i < bp->rx_nr_rings; i++) {
1228                         if (bp->grp_info[i].fw_grp_id == fwr)
1229                                 return i;
1230                 }
1231         }
1232
1233         return INVALID_HW_RING_ID;
1234 }
1235
1236 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1237                             struct rte_eth_rss_reta_entry64 *reta_conf,
1238                             uint16_t reta_size)
1239 {
1240         struct bnxt *bp = eth_dev->data->dev_private;
1241         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1242         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1243         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1244         uint16_t idx, sft;
1245         int i, rc;
1246
1247         rc = is_bnxt_in_error(bp);
1248         if (rc)
1249                 return rc;
1250
1251         if (!vnic->rss_table)
1252                 return -EINVAL;
1253
1254         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1255                 return -EINVAL;
1256
1257         if (reta_size != tbl_size) {
1258                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1259                         "(%d) must equal the size supported by the hardware "
1260                         "(%d)\n", reta_size, tbl_size);
1261                 return -EINVAL;
1262         }
1263
1264         for (i = 0; i < reta_size; i++) {
1265                 struct bnxt_rx_queue *rxq;
1266
1267                 idx = i / RTE_RETA_GROUP_SIZE;
1268                 sft = i % RTE_RETA_GROUP_SIZE;
1269
1270                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1271                         continue;
1272
1273                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1274                 if (!rxq) {
1275                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1276                         return -EINVAL;
1277                 }
1278
1279                 if (BNXT_CHIP_THOR(bp)) {
1280                         vnic->rss_table[i * 2] =
1281                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1282                         vnic->rss_table[i * 2 + 1] =
1283                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1284                 } else {
1285                         vnic->rss_table[i] =
1286                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1287                 }
1288
1289                 vnic->rss_table[i] =
1290                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1291         }
1292
1293         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1294         return 0;
1295 }
1296
1297 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1298                               struct rte_eth_rss_reta_entry64 *reta_conf,
1299                               uint16_t reta_size)
1300 {
1301         struct bnxt *bp = eth_dev->data->dev_private;
1302         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1303         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1304         uint16_t idx, sft, i;
1305         int rc;
1306
1307         rc = is_bnxt_in_error(bp);
1308         if (rc)
1309                 return rc;
1310
1311         /* Retrieve from the default VNIC */
1312         if (!vnic)
1313                 return -EINVAL;
1314         if (!vnic->rss_table)
1315                 return -EINVAL;
1316
1317         if (reta_size != tbl_size) {
1318                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1319                         "(%d) must equal the size supported by the hardware "
1320                         "(%d)\n", reta_size, tbl_size);
1321                 return -EINVAL;
1322         }
1323
1324         for (idx = 0, i = 0; i < reta_size; i++) {
1325                 idx = i / RTE_RETA_GROUP_SIZE;
1326                 sft = i % RTE_RETA_GROUP_SIZE;
1327
1328                 if (reta_conf[idx].mask & (1ULL << sft)) {
1329                         uint16_t qid;
1330
1331                         if (BNXT_CHIP_THOR(bp))
1332                                 qid = bnxt_rss_to_qid(bp,
1333                                                       vnic->rss_table[i * 2]);
1334                         else
1335                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1336
1337                         if (qid == INVALID_HW_RING_ID) {
1338                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1339                                 return -EINVAL;
1340                         }
1341                         reta_conf[idx].reta[sft] = qid;
1342                 }
1343         }
1344
1345         return 0;
1346 }
1347
1348 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1349                                    struct rte_eth_rss_conf *rss_conf)
1350 {
1351         struct bnxt *bp = eth_dev->data->dev_private;
1352         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1353         struct bnxt_vnic_info *vnic;
1354         uint16_t hash_type = 0;
1355         unsigned int i;
1356         int rc;
1357
1358         rc = is_bnxt_in_error(bp);
1359         if (rc)
1360                 return rc;
1361
1362         /*
1363          * If RSS enablement were different than dev_configure,
1364          * then return -EINVAL
1365          */
1366         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1367                 if (!rss_conf->rss_hf)
1368                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1369         } else {
1370                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1371                         return -EINVAL;
1372         }
1373
1374         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1375         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1376
1377         if (rss_conf->rss_hf & ETH_RSS_IPV4)
1378                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1379         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1380                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1381         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1382                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1383         if (rss_conf->rss_hf & ETH_RSS_IPV6)
1384                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1385         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1386                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1387         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1388                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1389
1390         /* Update the RSS VNIC(s) */
1391         for (i = 0; i < bp->nr_vnics; i++) {
1392                 vnic = &bp->vnic_info[i];
1393                 vnic->hash_type = hash_type;
1394
1395                 /*
1396                  * Use the supplied key if the key length is
1397                  * acceptable and the rss_key is not NULL
1398                  */
1399                 if (rss_conf->rss_key &&
1400                     rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1401                         memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1402                                rss_conf->rss_key_len);
1403
1404                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1405         }
1406         return 0;
1407 }
1408
1409 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1410                                      struct rte_eth_rss_conf *rss_conf)
1411 {
1412         struct bnxt *bp = eth_dev->data->dev_private;
1413         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1414         int len, rc;
1415         uint32_t hash_types;
1416
1417         rc = is_bnxt_in_error(bp);
1418         if (rc)
1419                 return rc;
1420
1421         /* RSS configuration is the same for all VNICs */
1422         if (vnic && vnic->rss_hash_key) {
1423                 if (rss_conf->rss_key) {
1424                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1425                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1426                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1427                 }
1428
1429                 hash_types = vnic->hash_type;
1430                 rss_conf->rss_hf = 0;
1431                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1432                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1433                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1434                 }
1435                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1436                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1437                         hash_types &=
1438                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1439                 }
1440                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1441                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1442                         hash_types &=
1443                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1444                 }
1445                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1446                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1447                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1448                 }
1449                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1450                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1451                         hash_types &=
1452                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1453                 }
1454                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1455                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1456                         hash_types &=
1457                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1458                 }
1459                 if (hash_types) {
1460                         PMD_DRV_LOG(ERR,
1461                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1462                                 vnic->hash_type);
1463                         return -ENOTSUP;
1464                 }
1465         } else {
1466                 rss_conf->rss_hf = 0;
1467         }
1468         return 0;
1469 }
1470
1471 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1472                                struct rte_eth_fc_conf *fc_conf)
1473 {
1474         struct bnxt *bp = dev->data->dev_private;
1475         struct rte_eth_link link_info;
1476         int rc;
1477
1478         rc = is_bnxt_in_error(bp);
1479         if (rc)
1480                 return rc;
1481
1482         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1483         if (rc)
1484                 return rc;
1485
1486         memset(fc_conf, 0, sizeof(*fc_conf));
1487         if (bp->link_info.auto_pause)
1488                 fc_conf->autoneg = 1;
1489         switch (bp->link_info.pause) {
1490         case 0:
1491                 fc_conf->mode = RTE_FC_NONE;
1492                 break;
1493         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1494                 fc_conf->mode = RTE_FC_TX_PAUSE;
1495                 break;
1496         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1497                 fc_conf->mode = RTE_FC_RX_PAUSE;
1498                 break;
1499         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1500                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1501                 fc_conf->mode = RTE_FC_FULL;
1502                 break;
1503         }
1504         return 0;
1505 }
1506
1507 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1508                                struct rte_eth_fc_conf *fc_conf)
1509 {
1510         struct bnxt *bp = dev->data->dev_private;
1511         int rc;
1512
1513         rc = is_bnxt_in_error(bp);
1514         if (rc)
1515                 return rc;
1516
1517         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1518                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1519                 return -ENOTSUP;
1520         }
1521
1522         switch (fc_conf->mode) {
1523         case RTE_FC_NONE:
1524                 bp->link_info.auto_pause = 0;
1525                 bp->link_info.force_pause = 0;
1526                 break;
1527         case RTE_FC_RX_PAUSE:
1528                 if (fc_conf->autoneg) {
1529                         bp->link_info.auto_pause =
1530                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1531                         bp->link_info.force_pause = 0;
1532                 } else {
1533                         bp->link_info.auto_pause = 0;
1534                         bp->link_info.force_pause =
1535                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1536                 }
1537                 break;
1538         case RTE_FC_TX_PAUSE:
1539                 if (fc_conf->autoneg) {
1540                         bp->link_info.auto_pause =
1541                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1542                         bp->link_info.force_pause = 0;
1543                 } else {
1544                         bp->link_info.auto_pause = 0;
1545                         bp->link_info.force_pause =
1546                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1547                 }
1548                 break;
1549         case RTE_FC_FULL:
1550                 if (fc_conf->autoneg) {
1551                         bp->link_info.auto_pause =
1552                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1553                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1554                         bp->link_info.force_pause = 0;
1555                 } else {
1556                         bp->link_info.auto_pause = 0;
1557                         bp->link_info.force_pause =
1558                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1559                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1560                 }
1561                 break;
1562         }
1563         return bnxt_set_hwrm_link_config(bp, true);
1564 }
1565
1566 /* Add UDP tunneling port */
1567 static int
1568 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1569                          struct rte_eth_udp_tunnel *udp_tunnel)
1570 {
1571         struct bnxt *bp = eth_dev->data->dev_private;
1572         uint16_t tunnel_type = 0;
1573         int rc = 0;
1574
1575         rc = is_bnxt_in_error(bp);
1576         if (rc)
1577                 return rc;
1578
1579         switch (udp_tunnel->prot_type) {
1580         case RTE_TUNNEL_TYPE_VXLAN:
1581                 if (bp->vxlan_port_cnt) {
1582                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1583                                 udp_tunnel->udp_port);
1584                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1585                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1586                                 return -ENOSPC;
1587                         }
1588                         bp->vxlan_port_cnt++;
1589                         return 0;
1590                 }
1591                 tunnel_type =
1592                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1593                 bp->vxlan_port_cnt++;
1594                 break;
1595         case RTE_TUNNEL_TYPE_GENEVE:
1596                 if (bp->geneve_port_cnt) {
1597                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1598                                 udp_tunnel->udp_port);
1599                         if (bp->geneve_port != udp_tunnel->udp_port) {
1600                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1601                                 return -ENOSPC;
1602                         }
1603                         bp->geneve_port_cnt++;
1604                         return 0;
1605                 }
1606                 tunnel_type =
1607                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1608                 bp->geneve_port_cnt++;
1609                 break;
1610         default:
1611                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1612                 return -ENOTSUP;
1613         }
1614         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1615                                              tunnel_type);
1616         return rc;
1617 }
1618
1619 static int
1620 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1621                          struct rte_eth_udp_tunnel *udp_tunnel)
1622 {
1623         struct bnxt *bp = eth_dev->data->dev_private;
1624         uint16_t tunnel_type = 0;
1625         uint16_t port = 0;
1626         int rc = 0;
1627
1628         rc = is_bnxt_in_error(bp);
1629         if (rc)
1630                 return rc;
1631
1632         switch (udp_tunnel->prot_type) {
1633         case RTE_TUNNEL_TYPE_VXLAN:
1634                 if (!bp->vxlan_port_cnt) {
1635                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1636                         return -EINVAL;
1637                 }
1638                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1639                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1640                                 udp_tunnel->udp_port, bp->vxlan_port);
1641                         return -EINVAL;
1642                 }
1643                 if (--bp->vxlan_port_cnt)
1644                         return 0;
1645
1646                 tunnel_type =
1647                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1648                 port = bp->vxlan_fw_dst_port_id;
1649                 break;
1650         case RTE_TUNNEL_TYPE_GENEVE:
1651                 if (!bp->geneve_port_cnt) {
1652                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1653                         return -EINVAL;
1654                 }
1655                 if (bp->geneve_port != udp_tunnel->udp_port) {
1656                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1657                                 udp_tunnel->udp_port, bp->geneve_port);
1658                         return -EINVAL;
1659                 }
1660                 if (--bp->geneve_port_cnt)
1661                         return 0;
1662
1663                 tunnel_type =
1664                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1665                 port = bp->geneve_fw_dst_port_id;
1666                 break;
1667         default:
1668                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1669                 return -ENOTSUP;
1670         }
1671
1672         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1673         if (!rc) {
1674                 if (tunnel_type ==
1675                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1676                         bp->vxlan_port = 0;
1677                 if (tunnel_type ==
1678                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1679                         bp->geneve_port = 0;
1680         }
1681         return rc;
1682 }
1683
1684 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1685 {
1686         struct bnxt_filter_info *filter;
1687         struct bnxt_vnic_info *vnic;
1688         int rc = 0;
1689         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1690
1691         /* if VLAN exists && VLAN matches vlan_id
1692          *      remove the MAC+VLAN filter
1693          *      add a new MAC only filter
1694          * else
1695          *      VLAN filter doesn't exist, just skip and continue
1696          */
1697         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1698         filter = STAILQ_FIRST(&vnic->filter);
1699         while (filter) {
1700                 /* Search for this matching MAC+VLAN filter */
1701                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1702                     !memcmp(filter->l2_addr,
1703                             bp->mac_addr,
1704                             RTE_ETHER_ADDR_LEN)) {
1705                         /* Delete the filter */
1706                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1707                         if (rc)
1708                                 return rc;
1709                         STAILQ_REMOVE(&vnic->filter, filter,
1710                                       bnxt_filter_info, next);
1711                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1712
1713                         PMD_DRV_LOG(INFO,
1714                                     "Del Vlan filter for %d\n",
1715                                     vlan_id);
1716                         return rc;
1717                 }
1718                 filter = STAILQ_NEXT(filter, next);
1719         }
1720         return -ENOENT;
1721 }
1722
1723 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1724 {
1725         struct bnxt_filter_info *filter;
1726         struct bnxt_vnic_info *vnic;
1727         int rc = 0;
1728         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1729                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1730         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1731
1732         /* Implementation notes on the use of VNIC in this command:
1733          *
1734          * By default, these filters belong to default vnic for the function.
1735          * Once these filters are set up, only destination VNIC can be modified.
1736          * If the destination VNIC is not specified in this command,
1737          * then the HWRM shall only create an l2 context id.
1738          */
1739
1740         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1741         filter = STAILQ_FIRST(&vnic->filter);
1742         /* Check if the VLAN has already been added */
1743         while (filter) {
1744                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1745                     !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1746                         return -EEXIST;
1747
1748                 filter = STAILQ_NEXT(filter, next);
1749         }
1750
1751         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1752          * command to create MAC+VLAN filter with the right flags, enables set.
1753          */
1754         filter = bnxt_alloc_filter(bp);
1755         if (!filter) {
1756                 PMD_DRV_LOG(ERR,
1757                             "MAC/VLAN filter alloc failed\n");
1758                 return -ENOMEM;
1759         }
1760         /* MAC + VLAN ID filter */
1761         filter->l2_ivlan = vlan_id;
1762         filter->l2_ivlan_mask = 0x0FFF;
1763         filter->enables |= en;
1764         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1765         if (rc) {
1766                 /* Free the newly allocated filter as we were
1767                  * not able to create the filter in hardware.
1768                  */
1769                 filter->fw_l2_filter_id = UINT64_MAX;
1770                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1771                 return rc;
1772         }
1773
1774         /* Add this new filter to the list */
1775         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1776         PMD_DRV_LOG(INFO,
1777                     "Added Vlan filter for %d\n", vlan_id);
1778         return rc;
1779 }
1780
1781 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1782                 uint16_t vlan_id, int on)
1783 {
1784         struct bnxt *bp = eth_dev->data->dev_private;
1785         int rc;
1786
1787         rc = is_bnxt_in_error(bp);
1788         if (rc)
1789                 return rc;
1790
1791         /* These operations apply to ALL existing MAC/VLAN filters */
1792         if (on)
1793                 return bnxt_add_vlan_filter(bp, vlan_id);
1794         else
1795                 return bnxt_del_vlan_filter(bp, vlan_id);
1796 }
1797
1798 static int
1799 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1800 {
1801         struct bnxt *bp = dev->data->dev_private;
1802         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1803         unsigned int i;
1804         int rc;
1805
1806         rc = is_bnxt_in_error(bp);
1807         if (rc)
1808                 return rc;
1809
1810         if (mask & ETH_VLAN_FILTER_MASK) {
1811                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1812                         /* Remove any VLAN filters programmed */
1813                         for (i = 0; i < 4095; i++)
1814                                 bnxt_del_vlan_filter(bp, i);
1815                 }
1816                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1817                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1818         }
1819
1820         if (mask & ETH_VLAN_STRIP_MASK) {
1821                 /* Enable or disable VLAN stripping */
1822                 for (i = 0; i < bp->nr_vnics; i++) {
1823                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1824                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1825                                 vnic->vlan_strip = true;
1826                         else
1827                                 vnic->vlan_strip = false;
1828                         bnxt_hwrm_vnic_cfg(bp, vnic);
1829                 }
1830                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1831                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1832         }
1833
1834         if (mask & ETH_VLAN_EXTEND_MASK)
1835                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1836
1837         return 0;
1838 }
1839
1840 static int
1841 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1842                         struct rte_ether_addr *addr)
1843 {
1844         struct bnxt *bp = dev->data->dev_private;
1845         /* Default Filter is tied to VNIC 0 */
1846         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1847         struct bnxt_filter_info *filter;
1848         int rc;
1849
1850         rc = is_bnxt_in_error(bp);
1851         if (rc)
1852                 return rc;
1853
1854         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1855                 return -EPERM;
1856
1857         if (rte_is_zero_ether_addr(addr))
1858                 return -EINVAL;
1859
1860         STAILQ_FOREACH(filter, &vnic->filter, next) {
1861                 /* Default Filter is at Index 0 */
1862                 if (filter->mac_index != 0)
1863                         continue;
1864
1865                 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1866                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1867                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1868                 filter->enables |=
1869                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1870                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1871
1872                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1873                 if (rc)
1874                         return rc;
1875
1876                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1877                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1878                 return 0;
1879         }
1880
1881         return 0;
1882 }
1883
1884 static int
1885 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1886                           struct rte_ether_addr *mc_addr_set,
1887                           uint32_t nb_mc_addr)
1888 {
1889         struct bnxt *bp = eth_dev->data->dev_private;
1890         char *mc_addr_list = (char *)mc_addr_set;
1891         struct bnxt_vnic_info *vnic;
1892         uint32_t off = 0, i = 0;
1893         int rc;
1894
1895         rc = is_bnxt_in_error(bp);
1896         if (rc)
1897                 return rc;
1898
1899         vnic = &bp->vnic_info[0];
1900
1901         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1902                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1903                 goto allmulti;
1904         }
1905
1906         /* TODO Check for Duplicate mcast addresses */
1907         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1908         for (i = 0; i < nb_mc_addr; i++) {
1909                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1910                         RTE_ETHER_ADDR_LEN);
1911                 off += RTE_ETHER_ADDR_LEN;
1912         }
1913
1914         vnic->mc_addr_cnt = i;
1915
1916 allmulti:
1917         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1918 }
1919
1920 static int
1921 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1922 {
1923         struct bnxt *bp = dev->data->dev_private;
1924         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1925         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1926         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1927         int ret;
1928
1929         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1930                         fw_major, fw_minor, fw_updt);
1931
1932         ret += 1; /* add the size of '\0' */
1933         if (fw_size < (uint32_t)ret)
1934                 return ret;
1935         else
1936                 return 0;
1937 }
1938
1939 static void
1940 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1941         struct rte_eth_rxq_info *qinfo)
1942 {
1943         struct bnxt_rx_queue *rxq;
1944
1945         rxq = dev->data->rx_queues[queue_id];
1946
1947         qinfo->mp = rxq->mb_pool;
1948         qinfo->scattered_rx = dev->data->scattered_rx;
1949         qinfo->nb_desc = rxq->nb_rx_desc;
1950
1951         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1952         qinfo->conf.rx_drop_en = 0;
1953         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1954 }
1955
1956 static void
1957 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1958         struct rte_eth_txq_info *qinfo)
1959 {
1960         struct bnxt_tx_queue *txq;
1961
1962         txq = dev->data->tx_queues[queue_id];
1963
1964         qinfo->nb_desc = txq->nb_tx_desc;
1965
1966         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1967         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1968         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1969
1970         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1971         qinfo->conf.tx_rs_thresh = 0;
1972         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1973 }
1974
1975 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1976 {
1977         struct bnxt *bp = eth_dev->data->dev_private;
1978         uint32_t new_pkt_size;
1979         uint32_t rc = 0;
1980         uint32_t i;
1981
1982         rc = is_bnxt_in_error(bp);
1983         if (rc)
1984                 return rc;
1985
1986         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1987                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1988
1989 #ifdef RTE_ARCH_X86
1990         /*
1991          * If vector-mode tx/rx is active, disallow any MTU change that would
1992          * require scattered receive support.
1993          */
1994         if (eth_dev->data->dev_started &&
1995             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1996              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1997             (new_pkt_size >
1998              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1999                 PMD_DRV_LOG(ERR,
2000                             "MTU change would require scattered rx support. ");
2001                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2002                 return -EINVAL;
2003         }
2004 #endif
2005
2006         if (new_mtu > RTE_ETHER_MTU) {
2007                 bp->flags |= BNXT_FLAG_JUMBO;
2008                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2009                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2010         } else {
2011                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2012                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2013                 bp->flags &= ~BNXT_FLAG_JUMBO;
2014         }
2015
2016         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2017
2018         for (i = 0; i < bp->nr_vnics; i++) {
2019                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2020                 uint16_t size = 0;
2021
2022                 vnic->mru = new_mtu + RTE_ETHER_HDR_LEN +
2023                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2024                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2025                 if (rc)
2026                         break;
2027
2028                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2029                 size -= RTE_PKTMBUF_HEADROOM;
2030
2031                 if (size < new_mtu) {
2032                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2033                         if (rc)
2034                                 return rc;
2035                 }
2036         }
2037
2038         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2039
2040         return rc;
2041 }
2042
2043 static int
2044 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2045 {
2046         struct bnxt *bp = dev->data->dev_private;
2047         uint16_t vlan = bp->vlan;
2048         int rc;
2049
2050         rc = is_bnxt_in_error(bp);
2051         if (rc)
2052                 return rc;
2053
2054         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2055                 PMD_DRV_LOG(ERR,
2056                         "PVID cannot be modified for this function\n");
2057                 return -ENOTSUP;
2058         }
2059         bp->vlan = on ? pvid : 0;
2060
2061         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2062         if (rc)
2063                 bp->vlan = vlan;
2064         return rc;
2065 }
2066
2067 static int
2068 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2069 {
2070         struct bnxt *bp = dev->data->dev_private;
2071         int rc;
2072
2073         rc = is_bnxt_in_error(bp);
2074         if (rc)
2075                 return rc;
2076
2077         return bnxt_hwrm_port_led_cfg(bp, true);
2078 }
2079
2080 static int
2081 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2082 {
2083         struct bnxt *bp = dev->data->dev_private;
2084         int rc;
2085
2086         rc = is_bnxt_in_error(bp);
2087         if (rc)
2088                 return rc;
2089
2090         return bnxt_hwrm_port_led_cfg(bp, false);
2091 }
2092
2093 static uint32_t
2094 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2095 {
2096         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2097         uint32_t desc = 0, raw_cons = 0, cons;
2098         struct bnxt_cp_ring_info *cpr;
2099         struct bnxt_rx_queue *rxq;
2100         struct rx_pkt_cmpl *rxcmp;
2101         int rc;
2102
2103         rc = is_bnxt_in_error(bp);
2104         if (rc)
2105                 return rc;
2106
2107         rxq = dev->data->rx_queues[rx_queue_id];
2108         cpr = rxq->cp_ring;
2109         raw_cons = cpr->cp_raw_cons;
2110
2111         while (1) {
2112                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2113                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2114                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2115
2116                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2117                         break;
2118                 } else {
2119                         raw_cons++;
2120                         desc++;
2121                 }
2122         }
2123
2124         return desc;
2125 }
2126
2127 static int
2128 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2129 {
2130         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2131         struct bnxt_rx_ring_info *rxr;
2132         struct bnxt_cp_ring_info *cpr;
2133         struct bnxt_sw_rx_bd *rx_buf;
2134         struct rx_pkt_cmpl *rxcmp;
2135         uint32_t cons, cp_cons;
2136         int rc;
2137
2138         if (!rxq)
2139                 return -EINVAL;
2140
2141         rc = is_bnxt_in_error(rxq->bp);
2142         if (rc)
2143                 return rc;
2144
2145         cpr = rxq->cp_ring;
2146         rxr = rxq->rx_ring;
2147
2148         if (offset >= rxq->nb_rx_desc)
2149                 return -EINVAL;
2150
2151         cons = RING_CMP(cpr->cp_ring_struct, offset);
2152         cp_cons = cpr->cp_raw_cons;
2153         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2154
2155         if (cons > cp_cons) {
2156                 if (CMPL_VALID(rxcmp, cpr->valid))
2157                         return RTE_ETH_RX_DESC_DONE;
2158         } else {
2159                 if (CMPL_VALID(rxcmp, !cpr->valid))
2160                         return RTE_ETH_RX_DESC_DONE;
2161         }
2162         rx_buf = &rxr->rx_buf_ring[cons];
2163         if (rx_buf->mbuf == NULL)
2164                 return RTE_ETH_RX_DESC_UNAVAIL;
2165
2166
2167         return RTE_ETH_RX_DESC_AVAIL;
2168 }
2169
2170 static int
2171 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2172 {
2173         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2174         struct bnxt_tx_ring_info *txr;
2175         struct bnxt_cp_ring_info *cpr;
2176         struct bnxt_sw_tx_bd *tx_buf;
2177         struct tx_pkt_cmpl *txcmp;
2178         uint32_t cons, cp_cons;
2179         int rc;
2180
2181         if (!txq)
2182                 return -EINVAL;
2183
2184         rc = is_bnxt_in_error(txq->bp);
2185         if (rc)
2186                 return rc;
2187
2188         cpr = txq->cp_ring;
2189         txr = txq->tx_ring;
2190
2191         if (offset >= txq->nb_tx_desc)
2192                 return -EINVAL;
2193
2194         cons = RING_CMP(cpr->cp_ring_struct, offset);
2195         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2196         cp_cons = cpr->cp_raw_cons;
2197
2198         if (cons > cp_cons) {
2199                 if (CMPL_VALID(txcmp, cpr->valid))
2200                         return RTE_ETH_TX_DESC_UNAVAIL;
2201         } else {
2202                 if (CMPL_VALID(txcmp, !cpr->valid))
2203                         return RTE_ETH_TX_DESC_UNAVAIL;
2204         }
2205         tx_buf = &txr->tx_buf_ring[cons];
2206         if (tx_buf->mbuf == NULL)
2207                 return RTE_ETH_TX_DESC_DONE;
2208
2209         return RTE_ETH_TX_DESC_FULL;
2210 }
2211
2212 static struct bnxt_filter_info *
2213 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2214                                 struct rte_eth_ethertype_filter *efilter,
2215                                 struct bnxt_vnic_info *vnic0,
2216                                 struct bnxt_vnic_info *vnic,
2217                                 int *ret)
2218 {
2219         struct bnxt_filter_info *mfilter = NULL;
2220         int match = 0;
2221         *ret = 0;
2222
2223         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2224                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2225                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2226                         " ethertype filter.", efilter->ether_type);
2227                 *ret = -EINVAL;
2228                 goto exit;
2229         }
2230         if (efilter->queue >= bp->rx_nr_rings) {
2231                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2232                 *ret = -EINVAL;
2233                 goto exit;
2234         }
2235
2236         vnic0 = &bp->vnic_info[0];
2237         vnic = &bp->vnic_info[efilter->queue];
2238         if (vnic == NULL) {
2239                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2240                 *ret = -EINVAL;
2241                 goto exit;
2242         }
2243
2244         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2245                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2246                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2247                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2248                              mfilter->flags ==
2249                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2250                              mfilter->ethertype == efilter->ether_type)) {
2251                                 match = 1;
2252                                 break;
2253                         }
2254                 }
2255         } else {
2256                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2257                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2258                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2259                              mfilter->ethertype == efilter->ether_type &&
2260                              mfilter->flags ==
2261                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2262                                 match = 1;
2263                                 break;
2264                         }
2265         }
2266
2267         if (match)
2268                 *ret = -EEXIST;
2269
2270 exit:
2271         return mfilter;
2272 }
2273
2274 static int
2275 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2276                         enum rte_filter_op filter_op,
2277                         void *arg)
2278 {
2279         struct bnxt *bp = dev->data->dev_private;
2280         struct rte_eth_ethertype_filter *efilter =
2281                         (struct rte_eth_ethertype_filter *)arg;
2282         struct bnxt_filter_info *bfilter, *filter1;
2283         struct bnxt_vnic_info *vnic, *vnic0;
2284         int ret;
2285
2286         if (filter_op == RTE_ETH_FILTER_NOP)
2287                 return 0;
2288
2289         if (arg == NULL) {
2290                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2291                             filter_op);
2292                 return -EINVAL;
2293         }
2294
2295         vnic0 = &bp->vnic_info[0];
2296         vnic = &bp->vnic_info[efilter->queue];
2297
2298         switch (filter_op) {
2299         case RTE_ETH_FILTER_ADD:
2300                 bnxt_match_and_validate_ether_filter(bp, efilter,
2301                                                         vnic0, vnic, &ret);
2302                 if (ret < 0)
2303                         return ret;
2304
2305                 bfilter = bnxt_get_unused_filter(bp);
2306                 if (bfilter == NULL) {
2307                         PMD_DRV_LOG(ERR,
2308                                 "Not enough resources for a new filter.\n");
2309                         return -ENOMEM;
2310                 }
2311                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2312                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2313                        RTE_ETHER_ADDR_LEN);
2314                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2315                        RTE_ETHER_ADDR_LEN);
2316                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2317                 bfilter->ethertype = efilter->ether_type;
2318                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2319
2320                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2321                 if (filter1 == NULL) {
2322                         ret = -EINVAL;
2323                         goto cleanup;
2324                 }
2325                 bfilter->enables |=
2326                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2327                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2328
2329                 bfilter->dst_id = vnic->fw_vnic_id;
2330
2331                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2332                         bfilter->flags =
2333                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2334                 }
2335
2336                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2337                 if (ret)
2338                         goto cleanup;
2339                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2340                 break;
2341         case RTE_ETH_FILTER_DELETE:
2342                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2343                                                         vnic0, vnic, &ret);
2344                 if (ret == -EEXIST) {
2345                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2346
2347                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2348                                       next);
2349                         bnxt_free_filter(bp, filter1);
2350                 } else if (ret == 0) {
2351                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2352                 }
2353                 break;
2354         default:
2355                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2356                 ret = -EINVAL;
2357                 goto error;
2358         }
2359         return ret;
2360 cleanup:
2361         bnxt_free_filter(bp, bfilter);
2362 error:
2363         return ret;
2364 }
2365
2366 static inline int
2367 parse_ntuple_filter(struct bnxt *bp,
2368                     struct rte_eth_ntuple_filter *nfilter,
2369                     struct bnxt_filter_info *bfilter)
2370 {
2371         uint32_t en = 0;
2372
2373         if (nfilter->queue >= bp->rx_nr_rings) {
2374                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2375                 return -EINVAL;
2376         }
2377
2378         switch (nfilter->dst_port_mask) {
2379         case UINT16_MAX:
2380                 bfilter->dst_port_mask = -1;
2381                 bfilter->dst_port = nfilter->dst_port;
2382                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2383                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2384                 break;
2385         default:
2386                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2387                 return -EINVAL;
2388         }
2389
2390         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2391         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2392
2393         switch (nfilter->proto_mask) {
2394         case UINT8_MAX:
2395                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2396                         bfilter->ip_protocol = 17;
2397                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2398                         bfilter->ip_protocol = 6;
2399                 else
2400                         return -EINVAL;
2401                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2402                 break;
2403         default:
2404                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2405                 return -EINVAL;
2406         }
2407
2408         switch (nfilter->dst_ip_mask) {
2409         case UINT32_MAX:
2410                 bfilter->dst_ipaddr_mask[0] = -1;
2411                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2412                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2413                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2414                 break;
2415         default:
2416                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2417                 return -EINVAL;
2418         }
2419
2420         switch (nfilter->src_ip_mask) {
2421         case UINT32_MAX:
2422                 bfilter->src_ipaddr_mask[0] = -1;
2423                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2424                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2425                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2426                 break;
2427         default:
2428                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2429                 return -EINVAL;
2430         }
2431
2432         switch (nfilter->src_port_mask) {
2433         case UINT16_MAX:
2434                 bfilter->src_port_mask = -1;
2435                 bfilter->src_port = nfilter->src_port;
2436                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2437                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2438                 break;
2439         default:
2440                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2441                 return -EINVAL;
2442         }
2443
2444         //TODO Priority
2445         //nfilter->priority = (uint8_t)filter->priority;
2446
2447         bfilter->enables = en;
2448         return 0;
2449 }
2450
2451 static struct bnxt_filter_info*
2452 bnxt_match_ntuple_filter(struct bnxt *bp,
2453                          struct bnxt_filter_info *bfilter,
2454                          struct bnxt_vnic_info **mvnic)
2455 {
2456         struct bnxt_filter_info *mfilter = NULL;
2457         int i;
2458
2459         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2460                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2461                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2462                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2463                             bfilter->src_ipaddr_mask[0] ==
2464                             mfilter->src_ipaddr_mask[0] &&
2465                             bfilter->src_port == mfilter->src_port &&
2466                             bfilter->src_port_mask == mfilter->src_port_mask &&
2467                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2468                             bfilter->dst_ipaddr_mask[0] ==
2469                             mfilter->dst_ipaddr_mask[0] &&
2470                             bfilter->dst_port == mfilter->dst_port &&
2471                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2472                             bfilter->flags == mfilter->flags &&
2473                             bfilter->enables == mfilter->enables) {
2474                                 if (mvnic)
2475                                         *mvnic = vnic;
2476                                 return mfilter;
2477                         }
2478                 }
2479         }
2480         return NULL;
2481 }
2482
2483 static int
2484 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2485                        struct rte_eth_ntuple_filter *nfilter,
2486                        enum rte_filter_op filter_op)
2487 {
2488         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2489         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2490         int ret;
2491
2492         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2493                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2494                 return -EINVAL;
2495         }
2496
2497         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2498                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2499                 return -EINVAL;
2500         }
2501
2502         bfilter = bnxt_get_unused_filter(bp);
2503         if (bfilter == NULL) {
2504                 PMD_DRV_LOG(ERR,
2505                         "Not enough resources for a new filter.\n");
2506                 return -ENOMEM;
2507         }
2508         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2509         if (ret < 0)
2510                 goto free_filter;
2511
2512         vnic = &bp->vnic_info[nfilter->queue];
2513         vnic0 = &bp->vnic_info[0];
2514         filter1 = STAILQ_FIRST(&vnic0->filter);
2515         if (filter1 == NULL) {
2516                 ret = -EINVAL;
2517                 goto free_filter;
2518         }
2519
2520         bfilter->dst_id = vnic->fw_vnic_id;
2521         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2522         bfilter->enables |=
2523                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2524         bfilter->ethertype = 0x800;
2525         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2526
2527         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2528
2529         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2530             bfilter->dst_id == mfilter->dst_id) {
2531                 PMD_DRV_LOG(ERR, "filter exists.\n");
2532                 ret = -EEXIST;
2533                 goto free_filter;
2534         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2535                    bfilter->dst_id != mfilter->dst_id) {
2536                 mfilter->dst_id = vnic->fw_vnic_id;
2537                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2538                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2539                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2540                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2541                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2542                 goto free_filter;
2543         }
2544         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2545                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2546                 ret = -ENOENT;
2547                 goto free_filter;
2548         }
2549
2550         if (filter_op == RTE_ETH_FILTER_ADD) {
2551                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2552                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2553                 if (ret)
2554                         goto free_filter;
2555                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2556         } else {
2557                 if (mfilter == NULL) {
2558                         /* This should not happen. But for Coverity! */
2559                         ret = -ENOENT;
2560                         goto free_filter;
2561                 }
2562                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2563
2564                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2565                 bnxt_free_filter(bp, mfilter);
2566                 mfilter->fw_l2_filter_id = -1;
2567                 bnxt_free_filter(bp, bfilter);
2568                 bfilter->fw_l2_filter_id = -1;
2569         }
2570
2571         return 0;
2572 free_filter:
2573         bfilter->fw_l2_filter_id = -1;
2574         bnxt_free_filter(bp, bfilter);
2575         return ret;
2576 }
2577
2578 static int
2579 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2580                         enum rte_filter_op filter_op,
2581                         void *arg)
2582 {
2583         struct bnxt *bp = dev->data->dev_private;
2584         int ret;
2585
2586         if (filter_op == RTE_ETH_FILTER_NOP)
2587                 return 0;
2588
2589         if (arg == NULL) {
2590                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2591                             filter_op);
2592                 return -EINVAL;
2593         }
2594
2595         switch (filter_op) {
2596         case RTE_ETH_FILTER_ADD:
2597                 ret = bnxt_cfg_ntuple_filter(bp,
2598                         (struct rte_eth_ntuple_filter *)arg,
2599                         filter_op);
2600                 break;
2601         case RTE_ETH_FILTER_DELETE:
2602                 ret = bnxt_cfg_ntuple_filter(bp,
2603                         (struct rte_eth_ntuple_filter *)arg,
2604                         filter_op);
2605                 break;
2606         default:
2607                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2608                 ret = -EINVAL;
2609                 break;
2610         }
2611         return ret;
2612 }
2613
2614 static int
2615 bnxt_parse_fdir_filter(struct bnxt *bp,
2616                        struct rte_eth_fdir_filter *fdir,
2617                        struct bnxt_filter_info *filter)
2618 {
2619         enum rte_fdir_mode fdir_mode =
2620                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2621         struct bnxt_vnic_info *vnic0, *vnic;
2622         struct bnxt_filter_info *filter1;
2623         uint32_t en = 0;
2624         int i;
2625
2626         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2627                 return -EINVAL;
2628
2629         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2630         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2631
2632         switch (fdir->input.flow_type) {
2633         case RTE_ETH_FLOW_IPV4:
2634         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2635                 /* FALLTHROUGH */
2636                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2637                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2638                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2639                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2640                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2641                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2642                 filter->ip_addr_type =
2643                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2644                 filter->src_ipaddr_mask[0] = 0xffffffff;
2645                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2646                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2647                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2648                 filter->ethertype = 0x800;
2649                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2650                 break;
2651         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2652                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2653                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2654                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2655                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2656                 filter->dst_port_mask = 0xffff;
2657                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2658                 filter->src_port_mask = 0xffff;
2659                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2660                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2661                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2662                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2663                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2664                 filter->ip_protocol = 6;
2665                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2666                 filter->ip_addr_type =
2667                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2668                 filter->src_ipaddr_mask[0] = 0xffffffff;
2669                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2670                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2671                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2672                 filter->ethertype = 0x800;
2673                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2674                 break;
2675         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2676                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2677                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2678                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2679                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2680                 filter->dst_port_mask = 0xffff;
2681                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2682                 filter->src_port_mask = 0xffff;
2683                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2684                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2685                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2686                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2687                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2688                 filter->ip_protocol = 17;
2689                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2690                 filter->ip_addr_type =
2691                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2692                 filter->src_ipaddr_mask[0] = 0xffffffff;
2693                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2694                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2695                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2696                 filter->ethertype = 0x800;
2697                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2698                 break;
2699         case RTE_ETH_FLOW_IPV6:
2700         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2701                 /* FALLTHROUGH */
2702                 filter->ip_addr_type =
2703                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2704                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2705                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2706                 rte_memcpy(filter->src_ipaddr,
2707                            fdir->input.flow.ipv6_flow.src_ip, 16);
2708                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2709                 rte_memcpy(filter->dst_ipaddr,
2710                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2711                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2712                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2713                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2714                 memset(filter->src_ipaddr_mask, 0xff, 16);
2715                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2716                 filter->ethertype = 0x86dd;
2717                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2718                 break;
2719         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2720                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2721                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2722                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2723                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2724                 filter->dst_port_mask = 0xffff;
2725                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2726                 filter->src_port_mask = 0xffff;
2727                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2728                 filter->ip_addr_type =
2729                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2730                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2731                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2732                 rte_memcpy(filter->src_ipaddr,
2733                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2734                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2735                 rte_memcpy(filter->dst_ipaddr,
2736                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2737                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2738                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2739                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2740                 memset(filter->src_ipaddr_mask, 0xff, 16);
2741                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2742                 filter->ethertype = 0x86dd;
2743                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2744                 break;
2745         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2746                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2747                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2748                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2749                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2750                 filter->dst_port_mask = 0xffff;
2751                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2752                 filter->src_port_mask = 0xffff;
2753                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2754                 filter->ip_addr_type =
2755                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2756                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2757                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2758                 rte_memcpy(filter->src_ipaddr,
2759                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2760                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2761                 rte_memcpy(filter->dst_ipaddr,
2762                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2763                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2764                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2765                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2766                 memset(filter->src_ipaddr_mask, 0xff, 16);
2767                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2768                 filter->ethertype = 0x86dd;
2769                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2770                 break;
2771         case RTE_ETH_FLOW_L2_PAYLOAD:
2772                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2773                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2774                 break;
2775         case RTE_ETH_FLOW_VXLAN:
2776                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2777                         return -EINVAL;
2778                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2779                 filter->tunnel_type =
2780                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2781                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2782                 break;
2783         case RTE_ETH_FLOW_NVGRE:
2784                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2785                         return -EINVAL;
2786                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2787                 filter->tunnel_type =
2788                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2789                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2790                 break;
2791         case RTE_ETH_FLOW_UNKNOWN:
2792         case RTE_ETH_FLOW_RAW:
2793         case RTE_ETH_FLOW_FRAG_IPV4:
2794         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2795         case RTE_ETH_FLOW_FRAG_IPV6:
2796         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2797         case RTE_ETH_FLOW_IPV6_EX:
2798         case RTE_ETH_FLOW_IPV6_TCP_EX:
2799         case RTE_ETH_FLOW_IPV6_UDP_EX:
2800         case RTE_ETH_FLOW_GENEVE:
2801                 /* FALLTHROUGH */
2802         default:
2803                 return -EINVAL;
2804         }
2805
2806         vnic0 = &bp->vnic_info[0];
2807         vnic = &bp->vnic_info[fdir->action.rx_queue];
2808         if (vnic == NULL) {
2809                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2810                 return -EINVAL;
2811         }
2812
2813
2814         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2815                 rte_memcpy(filter->dst_macaddr,
2816                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2817                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2818         }
2819
2820         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2821                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2822                 filter1 = STAILQ_FIRST(&vnic0->filter);
2823                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2824         } else {
2825                 filter->dst_id = vnic->fw_vnic_id;
2826                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2827                         if (filter->dst_macaddr[i] == 0x00)
2828                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2829                         else
2830                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2831         }
2832
2833         if (filter1 == NULL)
2834                 return -EINVAL;
2835
2836         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2837         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2838
2839         filter->enables = en;
2840
2841         return 0;
2842 }
2843
2844 static struct bnxt_filter_info *
2845 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2846                 struct bnxt_vnic_info **mvnic)
2847 {
2848         struct bnxt_filter_info *mf = NULL;
2849         int i;
2850
2851         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2852                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2853
2854                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2855                         if (mf->filter_type == nf->filter_type &&
2856                             mf->flags == nf->flags &&
2857                             mf->src_port == nf->src_port &&
2858                             mf->src_port_mask == nf->src_port_mask &&
2859                             mf->dst_port == nf->dst_port &&
2860                             mf->dst_port_mask == nf->dst_port_mask &&
2861                             mf->ip_protocol == nf->ip_protocol &&
2862                             mf->ip_addr_type == nf->ip_addr_type &&
2863                             mf->ethertype == nf->ethertype &&
2864                             mf->vni == nf->vni &&
2865                             mf->tunnel_type == nf->tunnel_type &&
2866                             mf->l2_ovlan == nf->l2_ovlan &&
2867                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2868                             mf->l2_ivlan == nf->l2_ivlan &&
2869                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2870                             !memcmp(mf->l2_addr, nf->l2_addr,
2871                                     RTE_ETHER_ADDR_LEN) &&
2872                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2873                                     RTE_ETHER_ADDR_LEN) &&
2874                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2875                                     RTE_ETHER_ADDR_LEN) &&
2876                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2877                                     RTE_ETHER_ADDR_LEN) &&
2878                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2879                                     sizeof(nf->src_ipaddr)) &&
2880                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2881                                     sizeof(nf->src_ipaddr_mask)) &&
2882                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2883                                     sizeof(nf->dst_ipaddr)) &&
2884                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2885                                     sizeof(nf->dst_ipaddr_mask))) {
2886                                 if (mvnic)
2887                                         *mvnic = vnic;
2888                                 return mf;
2889                         }
2890                 }
2891         }
2892         return NULL;
2893 }
2894
2895 static int
2896 bnxt_fdir_filter(struct rte_eth_dev *dev,
2897                  enum rte_filter_op filter_op,
2898                  void *arg)
2899 {
2900         struct bnxt *bp = dev->data->dev_private;
2901         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2902         struct bnxt_filter_info *filter, *match;
2903         struct bnxt_vnic_info *vnic, *mvnic;
2904         int ret = 0, i;
2905
2906         if (filter_op == RTE_ETH_FILTER_NOP)
2907                 return 0;
2908
2909         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2910                 return -EINVAL;
2911
2912         switch (filter_op) {
2913         case RTE_ETH_FILTER_ADD:
2914         case RTE_ETH_FILTER_DELETE:
2915                 /* FALLTHROUGH */
2916                 filter = bnxt_get_unused_filter(bp);
2917                 if (filter == NULL) {
2918                         PMD_DRV_LOG(ERR,
2919                                 "Not enough resources for a new flow.\n");
2920                         return -ENOMEM;
2921                 }
2922
2923                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2924                 if (ret != 0)
2925                         goto free_filter;
2926                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2927
2928                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2929                         vnic = &bp->vnic_info[0];
2930                 else
2931                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2932
2933                 match = bnxt_match_fdir(bp, filter, &mvnic);
2934                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2935                         if (match->dst_id == vnic->fw_vnic_id) {
2936                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2937                                 ret = -EEXIST;
2938                                 goto free_filter;
2939                         } else {
2940                                 match->dst_id = vnic->fw_vnic_id;
2941                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2942                                                                   match->dst_id,
2943                                                                   match);
2944                                 STAILQ_REMOVE(&mvnic->filter, match,
2945                                               bnxt_filter_info, next);
2946                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2947                                 PMD_DRV_LOG(ERR,
2948                                         "Filter with matching pattern exist\n");
2949                                 PMD_DRV_LOG(ERR,
2950                                         "Updated it to new destination q\n");
2951                                 goto free_filter;
2952                         }
2953                 }
2954                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2955                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2956                         ret = -ENOENT;
2957                         goto free_filter;
2958                 }
2959
2960                 if (filter_op == RTE_ETH_FILTER_ADD) {
2961                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2962                                                           filter->dst_id,
2963                                                           filter);
2964                         if (ret)
2965                                 goto free_filter;
2966                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2967                 } else {
2968                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2969                         STAILQ_REMOVE(&vnic->filter, match,
2970                                       bnxt_filter_info, next);
2971                         bnxt_free_filter(bp, match);
2972                         filter->fw_l2_filter_id = -1;
2973                         bnxt_free_filter(bp, filter);
2974                 }
2975                 break;
2976         case RTE_ETH_FILTER_FLUSH:
2977                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2978                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2979
2980                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2981                                 if (filter->filter_type ==
2982                                     HWRM_CFA_NTUPLE_FILTER) {
2983                                         ret =
2984                                         bnxt_hwrm_clear_ntuple_filter(bp,
2985                                                                       filter);
2986                                         STAILQ_REMOVE(&vnic->filter, filter,
2987                                                       bnxt_filter_info, next);
2988                                 }
2989                         }
2990                 }
2991                 return ret;
2992         case RTE_ETH_FILTER_UPDATE:
2993         case RTE_ETH_FILTER_STATS:
2994         case RTE_ETH_FILTER_INFO:
2995                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2996                 break;
2997         default:
2998                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2999                 ret = -EINVAL;
3000                 break;
3001         }
3002         return ret;
3003
3004 free_filter:
3005         filter->fw_l2_filter_id = -1;
3006         bnxt_free_filter(bp, filter);
3007         return ret;
3008 }
3009
3010 static int
3011 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3012                     enum rte_filter_type filter_type,
3013                     enum rte_filter_op filter_op, void *arg)
3014 {
3015         int ret = 0;
3016
3017         ret = is_bnxt_in_error(dev->data->dev_private);
3018         if (ret)
3019                 return ret;
3020
3021         switch (filter_type) {
3022         case RTE_ETH_FILTER_TUNNEL:
3023                 PMD_DRV_LOG(ERR,
3024                         "filter type: %d: To be implemented\n", filter_type);
3025                 break;
3026         case RTE_ETH_FILTER_FDIR:
3027                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3028                 break;
3029         case RTE_ETH_FILTER_NTUPLE:
3030                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3031                 break;
3032         case RTE_ETH_FILTER_ETHERTYPE:
3033                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3034                 break;
3035         case RTE_ETH_FILTER_GENERIC:
3036                 if (filter_op != RTE_ETH_FILTER_GET)
3037                         return -EINVAL;
3038                 *(const void **)arg = &bnxt_flow_ops;
3039                 break;
3040         default:
3041                 PMD_DRV_LOG(ERR,
3042                         "Filter type (%d) not supported", filter_type);
3043                 ret = -EINVAL;
3044                 break;
3045         }
3046         return ret;
3047 }
3048
3049 static const uint32_t *
3050 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3051 {
3052         static const uint32_t ptypes[] = {
3053                 RTE_PTYPE_L2_ETHER_VLAN,
3054                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3055                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3056                 RTE_PTYPE_L4_ICMP,
3057                 RTE_PTYPE_L4_TCP,
3058                 RTE_PTYPE_L4_UDP,
3059                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3060                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3061                 RTE_PTYPE_INNER_L4_ICMP,
3062                 RTE_PTYPE_INNER_L4_TCP,
3063                 RTE_PTYPE_INNER_L4_UDP,
3064                 RTE_PTYPE_UNKNOWN
3065         };
3066
3067         if (!dev->rx_pkt_burst)
3068                 return NULL;
3069
3070         return ptypes;
3071 }
3072
3073 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3074                          int reg_win)
3075 {
3076         uint32_t reg_base = *reg_arr & 0xfffff000;
3077         uint32_t win_off;
3078         int i;
3079
3080         for (i = 0; i < count; i++) {
3081                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3082                         return -ERANGE;
3083         }
3084         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3085         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3086         return 0;
3087 }
3088
3089 static int bnxt_map_ptp_regs(struct bnxt *bp)
3090 {
3091         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3092         uint32_t *reg_arr;
3093         int rc, i;
3094
3095         reg_arr = ptp->rx_regs;
3096         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3097         if (rc)
3098                 return rc;
3099
3100         reg_arr = ptp->tx_regs;
3101         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3102         if (rc)
3103                 return rc;
3104
3105         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3106                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3107
3108         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3109                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3110
3111         return 0;
3112 }
3113
3114 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3115 {
3116         rte_write32(0, (uint8_t *)bp->bar0 +
3117                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3118         rte_write32(0, (uint8_t *)bp->bar0 +
3119                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3120 }
3121
3122 static uint64_t bnxt_cc_read(struct bnxt *bp)
3123 {
3124         uint64_t ns;
3125
3126         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3127                               BNXT_GRCPF_REG_SYNC_TIME));
3128         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3129                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3130         return ns;
3131 }
3132
3133 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3134 {
3135         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3136         uint32_t fifo;
3137
3138         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3139                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3140         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3141                 return -EAGAIN;
3142
3143         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3144                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3145         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3146                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3147         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3148                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3149
3150         return 0;
3151 }
3152
3153 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3154 {
3155         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3156         struct bnxt_pf_info *pf = &bp->pf;
3157         uint16_t port_id;
3158         uint32_t fifo;
3159
3160         if (!ptp)
3161                 return -ENODEV;
3162
3163         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3164                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3165         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3166                 return -EAGAIN;
3167
3168         port_id = pf->port_id;
3169         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3170                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3171
3172         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3173                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3174         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3175 /*              bnxt_clr_rx_ts(bp);       TBD  */
3176                 return -EBUSY;
3177         }
3178
3179         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3180                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3181         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3182                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3183
3184         return 0;
3185 }
3186
3187 static int
3188 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3189 {
3190         uint64_t ns;
3191         struct bnxt *bp = dev->data->dev_private;
3192         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3193
3194         if (!ptp)
3195                 return 0;
3196
3197         ns = rte_timespec_to_ns(ts);
3198         /* Set the timecounters to a new value. */
3199         ptp->tc.nsec = ns;
3200
3201         return 0;
3202 }
3203
3204 static int
3205 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3206 {
3207         struct bnxt *bp = dev->data->dev_private;
3208         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3209         uint64_t ns, systime_cycles = 0;
3210         int rc = 0;
3211
3212         if (!ptp)
3213                 return 0;
3214
3215         if (BNXT_CHIP_THOR(bp))
3216                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3217                                              &systime_cycles);
3218         else
3219                 systime_cycles = bnxt_cc_read(bp);
3220
3221         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3222         *ts = rte_ns_to_timespec(ns);
3223
3224         return rc;
3225 }
3226 static int
3227 bnxt_timesync_enable(struct rte_eth_dev *dev)
3228 {
3229         struct bnxt *bp = dev->data->dev_private;
3230         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3231         uint32_t shift = 0;
3232         int rc;
3233
3234         if (!ptp)
3235                 return 0;
3236
3237         ptp->rx_filter = 1;
3238         ptp->tx_tstamp_en = 1;
3239         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3240
3241         rc = bnxt_hwrm_ptp_cfg(bp);
3242         if (rc)
3243                 return rc;
3244
3245         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3246         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3247         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3248
3249         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3250         ptp->tc.cc_shift = shift;
3251         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3252
3253         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3254         ptp->rx_tstamp_tc.cc_shift = shift;
3255         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3256
3257         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3258         ptp->tx_tstamp_tc.cc_shift = shift;
3259         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3260
3261         if (!BNXT_CHIP_THOR(bp))
3262                 bnxt_map_ptp_regs(bp);
3263
3264         return 0;
3265 }
3266
3267 static int
3268 bnxt_timesync_disable(struct rte_eth_dev *dev)
3269 {
3270         struct bnxt *bp = dev->data->dev_private;
3271         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3272
3273         if (!ptp)
3274                 return 0;
3275
3276         ptp->rx_filter = 0;
3277         ptp->tx_tstamp_en = 0;
3278         ptp->rxctl = 0;
3279
3280         bnxt_hwrm_ptp_cfg(bp);
3281
3282         if (!BNXT_CHIP_THOR(bp))
3283                 bnxt_unmap_ptp_regs(bp);
3284
3285         return 0;
3286 }
3287
3288 static int
3289 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3290                                  struct timespec *timestamp,
3291                                  uint32_t flags __rte_unused)
3292 {
3293         struct bnxt *bp = dev->data->dev_private;
3294         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3295         uint64_t rx_tstamp_cycles = 0;
3296         uint64_t ns;
3297
3298         if (!ptp)
3299                 return 0;
3300
3301         if (BNXT_CHIP_THOR(bp))
3302                 rx_tstamp_cycles = ptp->rx_timestamp;
3303         else
3304                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3305
3306         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3307         *timestamp = rte_ns_to_timespec(ns);
3308         return  0;
3309 }
3310
3311 static int
3312 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3313                                  struct timespec *timestamp)
3314 {
3315         struct bnxt *bp = dev->data->dev_private;
3316         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3317         uint64_t tx_tstamp_cycles = 0;
3318         uint64_t ns;
3319         int rc = 0;
3320
3321         if (!ptp)
3322                 return 0;
3323
3324         if (BNXT_CHIP_THOR(bp))
3325                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3326                                              &tx_tstamp_cycles);
3327         else
3328                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3329
3330         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3331         *timestamp = rte_ns_to_timespec(ns);
3332
3333         return rc;
3334 }
3335
3336 static int
3337 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3338 {
3339         struct bnxt *bp = dev->data->dev_private;
3340         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3341
3342         if (!ptp)
3343                 return 0;
3344
3345         ptp->tc.nsec += delta;
3346
3347         return 0;
3348 }
3349
3350 static int
3351 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3352 {
3353         struct bnxt *bp = dev->data->dev_private;
3354         int rc;
3355         uint32_t dir_entries;
3356         uint32_t entry_length;
3357
3358         rc = is_bnxt_in_error(bp);
3359         if (rc)
3360                 return rc;
3361
3362         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3363                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3364                 bp->pdev->addr.devid, bp->pdev->addr.function);
3365
3366         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3367         if (rc != 0)
3368                 return rc;
3369
3370         return dir_entries * entry_length;
3371 }
3372
3373 static int
3374 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3375                 struct rte_dev_eeprom_info *in_eeprom)
3376 {
3377         struct bnxt *bp = dev->data->dev_private;
3378         uint32_t index;
3379         uint32_t offset;
3380         int rc;
3381
3382         rc = is_bnxt_in_error(bp);
3383         if (rc)
3384                 return rc;
3385
3386         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3387                 "len = %d\n", bp->pdev->addr.domain,
3388                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3389                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3390
3391         if (in_eeprom->offset == 0) /* special offset value to get directory */
3392                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3393                                                 in_eeprom->data);
3394
3395         index = in_eeprom->offset >> 24;
3396         offset = in_eeprom->offset & 0xffffff;
3397
3398         if (index != 0)
3399                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3400                                            in_eeprom->length, in_eeprom->data);
3401
3402         return 0;
3403 }
3404
3405 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3406 {
3407         switch (dir_type) {
3408         case BNX_DIR_TYPE_CHIMP_PATCH:
3409         case BNX_DIR_TYPE_BOOTCODE:
3410         case BNX_DIR_TYPE_BOOTCODE_2:
3411         case BNX_DIR_TYPE_APE_FW:
3412         case BNX_DIR_TYPE_APE_PATCH:
3413         case BNX_DIR_TYPE_KONG_FW:
3414         case BNX_DIR_TYPE_KONG_PATCH:
3415         case BNX_DIR_TYPE_BONO_FW:
3416         case BNX_DIR_TYPE_BONO_PATCH:
3417                 /* FALLTHROUGH */
3418                 return true;
3419         }
3420
3421         return false;
3422 }
3423
3424 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3425 {
3426         switch (dir_type) {
3427         case BNX_DIR_TYPE_AVS:
3428         case BNX_DIR_TYPE_EXP_ROM_MBA:
3429         case BNX_DIR_TYPE_PCIE:
3430         case BNX_DIR_TYPE_TSCF_UCODE:
3431         case BNX_DIR_TYPE_EXT_PHY:
3432         case BNX_DIR_TYPE_CCM:
3433         case BNX_DIR_TYPE_ISCSI_BOOT:
3434         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3435         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3436                 /* FALLTHROUGH */
3437                 return true;
3438         }
3439
3440         return false;
3441 }
3442
3443 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3444 {
3445         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3446                 bnxt_dir_type_is_other_exec_format(dir_type);
3447 }
3448
3449 static int
3450 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3451                 struct rte_dev_eeprom_info *in_eeprom)
3452 {
3453         struct bnxt *bp = dev->data->dev_private;
3454         uint8_t index, dir_op;
3455         uint16_t type, ext, ordinal, attr;
3456         int rc;
3457
3458         rc = is_bnxt_in_error(bp);
3459         if (rc)
3460                 return rc;
3461
3462         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3463                 "len = %d\n", bp->pdev->addr.domain,
3464                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3465                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3466
3467         if (!BNXT_PF(bp)) {
3468                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3469                 return -EINVAL;
3470         }
3471
3472         type = in_eeprom->magic >> 16;
3473
3474         if (type == 0xffff) { /* special value for directory operations */
3475                 index = in_eeprom->magic & 0xff;
3476                 dir_op = in_eeprom->magic >> 8;
3477                 if (index == 0)
3478                         return -EINVAL;
3479                 switch (dir_op) {
3480                 case 0x0e: /* erase */
3481                         if (in_eeprom->offset != ~in_eeprom->magic)
3482                                 return -EINVAL;
3483                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3484                 default:
3485                         return -EINVAL;
3486                 }
3487         }
3488
3489         /* Create or re-write an NVM item: */
3490         if (bnxt_dir_type_is_executable(type) == true)
3491                 return -EOPNOTSUPP;
3492         ext = in_eeprom->magic & 0xffff;
3493         ordinal = in_eeprom->offset >> 16;
3494         attr = in_eeprom->offset & 0xffff;
3495
3496         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3497                                      in_eeprom->data, in_eeprom->length);
3498 }
3499
3500 /*
3501  * Initialization
3502  */
3503
3504 static const struct eth_dev_ops bnxt_dev_ops = {
3505         .dev_infos_get = bnxt_dev_info_get_op,
3506         .dev_close = bnxt_dev_close_op,
3507         .dev_configure = bnxt_dev_configure_op,
3508         .dev_start = bnxt_dev_start_op,
3509         .dev_stop = bnxt_dev_stop_op,
3510         .dev_set_link_up = bnxt_dev_set_link_up_op,
3511         .dev_set_link_down = bnxt_dev_set_link_down_op,
3512         .stats_get = bnxt_stats_get_op,
3513         .stats_reset = bnxt_stats_reset_op,
3514         .rx_queue_setup = bnxt_rx_queue_setup_op,
3515         .rx_queue_release = bnxt_rx_queue_release_op,
3516         .tx_queue_setup = bnxt_tx_queue_setup_op,
3517         .tx_queue_release = bnxt_tx_queue_release_op,
3518         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3519         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3520         .reta_update = bnxt_reta_update_op,
3521         .reta_query = bnxt_reta_query_op,
3522         .rss_hash_update = bnxt_rss_hash_update_op,
3523         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3524         .link_update = bnxt_link_update_op,
3525         .promiscuous_enable = bnxt_promiscuous_enable_op,
3526         .promiscuous_disable = bnxt_promiscuous_disable_op,
3527         .allmulticast_enable = bnxt_allmulticast_enable_op,
3528         .allmulticast_disable = bnxt_allmulticast_disable_op,
3529         .mac_addr_add = bnxt_mac_addr_add_op,
3530         .mac_addr_remove = bnxt_mac_addr_remove_op,
3531         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3532         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3533         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3534         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3535         .vlan_filter_set = bnxt_vlan_filter_set_op,
3536         .vlan_offload_set = bnxt_vlan_offload_set_op,
3537         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3538         .mtu_set = bnxt_mtu_set_op,
3539         .mac_addr_set = bnxt_set_default_mac_addr_op,
3540         .xstats_get = bnxt_dev_xstats_get_op,
3541         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3542         .xstats_reset = bnxt_dev_xstats_reset_op,
3543         .fw_version_get = bnxt_fw_version_get,
3544         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3545         .rxq_info_get = bnxt_rxq_info_get_op,
3546         .txq_info_get = bnxt_txq_info_get_op,
3547         .dev_led_on = bnxt_dev_led_on_op,
3548         .dev_led_off = bnxt_dev_led_off_op,
3549         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3550         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3551         .rx_queue_count = bnxt_rx_queue_count_op,
3552         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3553         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3554         .rx_queue_start = bnxt_rx_queue_start,
3555         .rx_queue_stop = bnxt_rx_queue_stop,
3556         .tx_queue_start = bnxt_tx_queue_start,
3557         .tx_queue_stop = bnxt_tx_queue_stop,
3558         .filter_ctrl = bnxt_filter_ctrl_op,
3559         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3560         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3561         .get_eeprom           = bnxt_get_eeprom_op,
3562         .set_eeprom           = bnxt_set_eeprom_op,
3563         .timesync_enable      = bnxt_timesync_enable,
3564         .timesync_disable     = bnxt_timesync_disable,
3565         .timesync_read_time   = bnxt_timesync_read_time,
3566         .timesync_write_time   = bnxt_timesync_write_time,
3567         .timesync_adjust_time = bnxt_timesync_adjust_time,
3568         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3569         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3570 };
3571
3572 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3573 {
3574         uint32_t offset;
3575
3576         /* Only pre-map the reset GRC registers using window 3 */
3577         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3578                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3579
3580         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3581
3582         return offset;
3583 }
3584
3585 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3586 {
3587         struct bnxt_error_recovery_info *info = bp->recovery_info;
3588         uint32_t reg_base = 0xffffffff;
3589         int i;
3590
3591         /* Only pre-map the monitoring GRC registers using window 2 */
3592         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3593                 uint32_t reg = info->status_regs[i];
3594
3595                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3596                         continue;
3597
3598                 if (reg_base == 0xffffffff)
3599                         reg_base = reg & 0xfffff000;
3600                 if ((reg & 0xfffff000) != reg_base)
3601                         return -ERANGE;
3602
3603                 /* Use mask 0xffc as the Lower 2 bits indicates
3604                  * address space location
3605                  */
3606                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3607                                                 (reg & 0xffc);
3608         }
3609
3610         if (reg_base == 0xffffffff)
3611                 return 0;
3612
3613         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3614                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3615
3616         return 0;
3617 }
3618
3619 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3620 {
3621         struct bnxt_error_recovery_info *info = bp->recovery_info;
3622         uint32_t delay = info->delay_after_reset[index];
3623         uint32_t val = info->reset_reg_val[index];
3624         uint32_t reg = info->reset_reg[index];
3625         uint32_t type, offset;
3626
3627         type = BNXT_FW_STATUS_REG_TYPE(reg);
3628         offset = BNXT_FW_STATUS_REG_OFF(reg);
3629
3630         switch (type) {
3631         case BNXT_FW_STATUS_REG_TYPE_CFG:
3632                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3633                 break;
3634         case BNXT_FW_STATUS_REG_TYPE_GRC:
3635                 offset = bnxt_map_reset_regs(bp, offset);
3636                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3637                 break;
3638         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3639                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3640                 break;
3641         }
3642         /* wait on a specific interval of time until core reset is complete */
3643         if (delay)
3644                 rte_delay_ms(delay);
3645 }
3646
3647 static void bnxt_dev_cleanup(struct bnxt *bp)
3648 {
3649         bnxt_set_hwrm_link_config(bp, false);
3650         bp->link_info.link_up = 0;
3651         if (bp->dev_stopped == 0)
3652                 bnxt_dev_stop_op(bp->eth_dev);
3653
3654         bnxt_uninit_resources(bp, true);
3655 }
3656
3657 static int bnxt_restore_filters(struct bnxt *bp)
3658 {
3659         struct rte_eth_dev *dev = bp->eth_dev;
3660         int ret = 0;
3661
3662         if (dev->data->all_multicast)
3663                 ret = bnxt_allmulticast_enable_op(dev);
3664         if (dev->data->promiscuous)
3665                 ret = bnxt_promiscuous_enable_op(dev);
3666
3667         /* TODO restore other filters as well */
3668         return ret;
3669 }
3670
3671 static void bnxt_dev_recover(void *arg)
3672 {
3673         struct bnxt *bp = arg;
3674         int timeout = bp->fw_reset_max_msecs;
3675         int rc = 0;
3676
3677         /* Clear Error flag so that device re-init should happen */
3678         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3679
3680         do {
3681                 rc = bnxt_hwrm_ver_get(bp);
3682                 if (rc == 0)
3683                         break;
3684                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3685                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3686         } while (rc && timeout);
3687
3688         if (rc) {
3689                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3690                 goto err;
3691         }
3692
3693         rc = bnxt_init_resources(bp, true);
3694         if (rc) {
3695                 PMD_DRV_LOG(ERR,
3696                             "Failed to initialize resources after reset\n");
3697                 goto err;
3698         }
3699         /* clear reset flag as the device is initialized now */
3700         bp->flags &= ~BNXT_FLAG_FW_RESET;
3701
3702         rc = bnxt_dev_start_op(bp->eth_dev);
3703         if (rc) {
3704                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3705                 goto err;
3706         }
3707
3708         rc = bnxt_restore_filters(bp);
3709         if (rc)
3710                 goto err;
3711
3712         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3713         return;
3714 err:
3715         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3716         bnxt_uninit_resources(bp, false);
3717         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3718 }
3719
3720 void bnxt_dev_reset_and_resume(void *arg)
3721 {
3722         struct bnxt *bp = arg;
3723         int rc;
3724
3725         bnxt_dev_cleanup(bp);
3726
3727         bnxt_wait_for_device_shutdown(bp);
3728
3729         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3730                                bnxt_dev_recover, (void *)bp);
3731         if (rc)
3732                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3733 }
3734
3735 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3736 {
3737         struct bnxt_error_recovery_info *info = bp->recovery_info;
3738         uint32_t reg = info->status_regs[index];
3739         uint32_t type, offset, val = 0;
3740
3741         type = BNXT_FW_STATUS_REG_TYPE(reg);
3742         offset = BNXT_FW_STATUS_REG_OFF(reg);
3743
3744         switch (type) {
3745         case BNXT_FW_STATUS_REG_TYPE_CFG:
3746                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3747                 break;
3748         case BNXT_FW_STATUS_REG_TYPE_GRC:
3749                 offset = info->mapped_status_regs[index];
3750                 /* FALLTHROUGH */
3751         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3752                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3753                                        offset));
3754                 break;
3755         }
3756
3757         return val;
3758 }
3759
3760 static int bnxt_fw_reset_all(struct bnxt *bp)
3761 {
3762         struct bnxt_error_recovery_info *info = bp->recovery_info;
3763         uint32_t i;
3764         int rc = 0;
3765
3766         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3767                 /* Reset through master function driver */
3768                 for (i = 0; i < info->reg_array_cnt; i++)
3769                         bnxt_write_fw_reset_reg(bp, i);
3770                 /* Wait for time specified by FW after triggering reset */
3771                 rte_delay_ms(info->master_func_wait_period_after_reset);
3772         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3773                 /* Reset with the help of Kong processor */
3774                 rc = bnxt_hwrm_fw_reset(bp);
3775                 if (rc)
3776                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3777         }
3778
3779         return rc;
3780 }
3781
3782 static void bnxt_fw_reset_cb(void *arg)
3783 {
3784         struct bnxt *bp = arg;
3785         struct bnxt_error_recovery_info *info = bp->recovery_info;
3786         int rc = 0;
3787
3788         /* Only Master function can do FW reset */
3789         if (bnxt_is_master_func(bp) &&
3790             bnxt_is_recovery_enabled(bp)) {
3791                 rc = bnxt_fw_reset_all(bp);
3792                 if (rc) {
3793                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3794                         return;
3795                 }
3796         }
3797
3798         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3799          * EXCEPTION_FATAL_ASYNC event to all the functions
3800          * (including MASTER FUNC). After receiving this Async, all the active
3801          * drivers should treat this case as FW initiated recovery
3802          */
3803         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3804                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3805                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3806
3807                 /* To recover from error */
3808                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3809                                   (void *)bp);
3810         }
3811 }
3812
3813 /* Driver should poll FW heartbeat, reset_counter with the frequency
3814  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3815  * When the driver detects heartbeat stop or change in reset_counter,
3816  * it has to trigger a reset to recover from the error condition.
3817  * A “master PF” is the function who will have the privilege to
3818  * initiate the chimp reset. The master PF will be elected by the
3819  * firmware and will be notified through async message.
3820  */
3821 static void bnxt_check_fw_health(void *arg)
3822 {
3823         struct bnxt *bp = arg;
3824         struct bnxt_error_recovery_info *info = bp->recovery_info;
3825         uint32_t val = 0, wait_msec;
3826
3827         if (!info || !bnxt_is_recovery_enabled(bp) ||
3828             is_bnxt_in_error(bp))
3829                 return;
3830
3831         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3832         if (val == info->last_heart_beat)
3833                 goto reset;
3834
3835         info->last_heart_beat = val;
3836
3837         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3838         if (val != info->last_reset_counter)
3839                 goto reset;
3840
3841         info->last_reset_counter = val;
3842
3843         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3844                           bnxt_check_fw_health, (void *)bp);
3845
3846         return;
3847 reset:
3848         /* Stop DMA to/from device */
3849         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3850         bp->flags |= BNXT_FLAG_FW_RESET;
3851
3852         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3853
3854         if (bnxt_is_master_func(bp))
3855                 wait_msec = info->master_func_wait_period;
3856         else
3857                 wait_msec = info->normal_func_wait_period;
3858
3859         rte_eal_alarm_set(US_PER_MS * wait_msec,
3860                           bnxt_fw_reset_cb, (void *)bp);
3861 }
3862
3863 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3864 {
3865         uint32_t polling_freq;
3866
3867         if (!bnxt_is_recovery_enabled(bp))
3868                 return;
3869
3870         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3871                 return;
3872
3873         polling_freq = bp->recovery_info->driver_polling_freq;
3874
3875         rte_eal_alarm_set(US_PER_MS * polling_freq,
3876                           bnxt_check_fw_health, (void *)bp);
3877         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3878 }
3879
3880 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3881 {
3882         if (!bnxt_is_recovery_enabled(bp))
3883                 return;
3884
3885         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3886         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3887 }
3888
3889 static bool bnxt_vf_pciid(uint16_t id)
3890 {
3891         if (id == BROADCOM_DEV_ID_57304_VF ||
3892             id == BROADCOM_DEV_ID_57406_VF ||
3893             id == BROADCOM_DEV_ID_5731X_VF ||
3894             id == BROADCOM_DEV_ID_5741X_VF ||
3895             id == BROADCOM_DEV_ID_57414_VF ||
3896             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3897             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3898             id == BROADCOM_DEV_ID_58802_VF ||
3899             id == BROADCOM_DEV_ID_57500_VF1 ||
3900             id == BROADCOM_DEV_ID_57500_VF2)
3901                 return true;
3902         return false;
3903 }
3904
3905 bool bnxt_stratus_device(struct bnxt *bp)
3906 {
3907         uint16_t id = bp->pdev->id.device_id;
3908
3909         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3910             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3911             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3912                 return true;
3913         return false;
3914 }
3915
3916 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3917 {
3918         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3919         struct bnxt *bp = eth_dev->data->dev_private;
3920
3921         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3922         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3923         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3924         if (!bp->bar0 || !bp->doorbell_base) {
3925                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3926                 return -ENODEV;
3927         }
3928
3929         bp->eth_dev = eth_dev;
3930         bp->pdev = pci_dev;
3931
3932         return 0;
3933 }
3934
3935 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3936                                   struct bnxt_ctx_pg_info *ctx_pg,
3937                                   uint32_t mem_size,
3938                                   const char *suffix,
3939                                   uint16_t idx)
3940 {
3941         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3942         const struct rte_memzone *mz = NULL;
3943         char mz_name[RTE_MEMZONE_NAMESIZE];
3944         rte_iova_t mz_phys_addr;
3945         uint64_t valid_bits = 0;
3946         uint32_t sz;
3947         int i;
3948
3949         if (!mem_size)
3950                 return 0;
3951
3952         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3953                          BNXT_PAGE_SIZE;
3954         rmem->page_size = BNXT_PAGE_SIZE;
3955         rmem->pg_arr = ctx_pg->ctx_pg_arr;
3956         rmem->dma_arr = ctx_pg->ctx_dma_arr;
3957         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3958
3959         valid_bits = PTU_PTE_VALID;
3960
3961         if (rmem->nr_pages > 1) {
3962                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3963                          "bnxt_ctx_pg_tbl%s_%x_%d",
3964                          suffix, idx, bp->eth_dev->data->port_id);
3965                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3966                 mz = rte_memzone_lookup(mz_name);
3967                 if (!mz) {
3968                         mz = rte_memzone_reserve_aligned(mz_name,
3969                                                 rmem->nr_pages * 8,
3970                                                 SOCKET_ID_ANY,
3971                                                 RTE_MEMZONE_2MB |
3972                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
3973                                                 RTE_MEMZONE_IOVA_CONTIG,
3974                                                 BNXT_PAGE_SIZE);
3975                         if (mz == NULL)
3976                                 return -ENOMEM;
3977                 }
3978
3979                 memset(mz->addr, 0, mz->len);
3980                 mz_phys_addr = mz->iova;
3981                 if ((unsigned long)mz->addr == mz_phys_addr) {
3982                         PMD_DRV_LOG(DEBUG,
3983                                     "physical address same as virtual\n");
3984                         PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
3985                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3986                         if (mz_phys_addr == RTE_BAD_IOVA) {
3987                                 PMD_DRV_LOG(ERR,
3988                                         "unable to map addr to phys memory\n");
3989                                 return -ENOMEM;
3990                         }
3991                 }
3992                 rte_mem_lock_page(((char *)mz->addr));
3993
3994                 rmem->pg_tbl = mz->addr;
3995                 rmem->pg_tbl_map = mz_phys_addr;
3996                 rmem->pg_tbl_mz = mz;
3997         }
3998
3999         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4000                  suffix, idx, bp->eth_dev->data->port_id);
4001         mz = rte_memzone_lookup(mz_name);
4002         if (!mz) {
4003                 mz = rte_memzone_reserve_aligned(mz_name,
4004                                                  mem_size,
4005                                                  SOCKET_ID_ANY,
4006                                                  RTE_MEMZONE_1GB |
4007                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4008                                                  RTE_MEMZONE_IOVA_CONTIG,
4009                                                  BNXT_PAGE_SIZE);
4010                 if (mz == NULL)
4011                         return -ENOMEM;
4012         }
4013
4014         memset(mz->addr, 0, mz->len);
4015         mz_phys_addr = mz->iova;
4016         if ((unsigned long)mz->addr == mz_phys_addr) {
4017                 PMD_DRV_LOG(DEBUG,
4018                             "Memzone physical address same as virtual.\n");
4019                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4020                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4021                         rte_mem_lock_page(((char *)mz->addr) + sz);
4022                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4023                 if (mz_phys_addr == RTE_BAD_IOVA) {
4024                         PMD_DRV_LOG(ERR,
4025                                     "unable to map addr to phys memory\n");
4026                         return -ENOMEM;
4027                 }
4028         }
4029
4030         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4031                 rte_mem_lock_page(((char *)mz->addr) + sz);
4032                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4033                 rmem->dma_arr[i] = mz_phys_addr + sz;
4034
4035                 if (rmem->nr_pages > 1) {
4036                         if (i == rmem->nr_pages - 2 &&
4037                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4038                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4039                         else if (i == rmem->nr_pages - 1 &&
4040                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4041                                 valid_bits |= PTU_PTE_LAST;
4042
4043                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4044                                                            valid_bits);
4045                 }
4046         }
4047
4048         rmem->mz = mz;
4049         if (rmem->vmem_size)
4050                 rmem->vmem = (void **)mz->addr;
4051         rmem->dma_arr[0] = mz_phys_addr;
4052         return 0;
4053 }
4054
4055 static void bnxt_free_ctx_mem(struct bnxt *bp)
4056 {
4057         int i;
4058
4059         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4060                 return;
4061
4062         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4063         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4064         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4065         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4066         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4067         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4068         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4069         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4070         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4071         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4072         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4073
4074         for (i = 0; i < BNXT_MAX_Q; i++) {
4075                 if (bp->ctx->tqm_mem[i])
4076                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4077         }
4078
4079         rte_free(bp->ctx);
4080         bp->ctx = NULL;
4081 }
4082
4083 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4084
4085 #define min_t(type, x, y) ({                    \
4086         type __min1 = (x);                      \
4087         type __min2 = (y);                      \
4088         __min1 < __min2 ? __min1 : __min2; })
4089
4090 #define max_t(type, x, y) ({                    \
4091         type __max1 = (x);                      \
4092         type __max2 = (y);                      \
4093         __max1 > __max2 ? __max1 : __max2; })
4094
4095 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4096
4097 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4098 {
4099         struct bnxt_ctx_pg_info *ctx_pg;
4100         struct bnxt_ctx_mem_info *ctx;
4101         uint32_t mem_size, ena, entries;
4102         int i, rc;
4103
4104         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4105         if (rc) {
4106                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4107                 return rc;
4108         }
4109         ctx = bp->ctx;
4110         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4111                 return 0;
4112
4113         ctx_pg = &ctx->qp_mem;
4114         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4115         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4116         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4117         if (rc)
4118                 return rc;
4119
4120         ctx_pg = &ctx->srq_mem;
4121         ctx_pg->entries = ctx->srq_max_l2_entries;
4122         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4123         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4124         if (rc)
4125                 return rc;
4126
4127         ctx_pg = &ctx->cq_mem;
4128         ctx_pg->entries = ctx->cq_max_l2_entries;
4129         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4130         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4131         if (rc)
4132                 return rc;
4133
4134         ctx_pg = &ctx->vnic_mem;
4135         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4136                 ctx->vnic_max_ring_table_entries;
4137         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4138         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4139         if (rc)
4140                 return rc;
4141
4142         ctx_pg = &ctx->stat_mem;
4143         ctx_pg->entries = ctx->stat_max_entries;
4144         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4145         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4146         if (rc)
4147                 return rc;
4148
4149         entries = ctx->qp_max_l2_entries;
4150         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4151         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4152                           ctx->tqm_max_entries_per_ring);
4153         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4154                 ctx_pg = ctx->tqm_mem[i];
4155                 /* use min tqm entries for now. */
4156                 ctx_pg->entries = entries;
4157                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4158                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4159                 if (rc)
4160                         return rc;
4161                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4162         }
4163
4164         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4165         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4166         if (rc)
4167                 PMD_DRV_LOG(ERR,
4168                             "Failed to configure context mem: rc = %d\n", rc);
4169         else
4170                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4171
4172         return rc;
4173 }
4174
4175 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4176 {
4177         struct rte_pci_device *pci_dev = bp->pdev;
4178         char mz_name[RTE_MEMZONE_NAMESIZE];
4179         const struct rte_memzone *mz = NULL;
4180         uint32_t total_alloc_len;
4181         rte_iova_t mz_phys_addr;
4182
4183         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4184                 return 0;
4185
4186         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4187                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4188                  pci_dev->addr.bus, pci_dev->addr.devid,
4189                  pci_dev->addr.function, "rx_port_stats");
4190         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4191         mz = rte_memzone_lookup(mz_name);
4192         total_alloc_len =
4193                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4194                                        sizeof(struct rx_port_stats_ext) + 512);
4195         if (!mz) {
4196                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4197                                          SOCKET_ID_ANY,
4198                                          RTE_MEMZONE_2MB |
4199                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4200                                          RTE_MEMZONE_IOVA_CONTIG);
4201                 if (mz == NULL)
4202                         return -ENOMEM;
4203         }
4204         memset(mz->addr, 0, mz->len);
4205         mz_phys_addr = mz->iova;
4206         if ((unsigned long)mz->addr == mz_phys_addr) {
4207                 PMD_DRV_LOG(DEBUG,
4208                             "Memzone physical address same as virtual.\n");
4209                 PMD_DRV_LOG(DEBUG,
4210                             "Using rte_mem_virt2iova()\n");
4211                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4212                 if (mz_phys_addr == RTE_BAD_IOVA) {
4213                         PMD_DRV_LOG(ERR,
4214                                     "Can't map address to physical memory\n");
4215                         return -ENOMEM;
4216                 }
4217         }
4218
4219         bp->rx_mem_zone = (const void *)mz;
4220         bp->hw_rx_port_stats = mz->addr;
4221         bp->hw_rx_port_stats_map = mz_phys_addr;
4222
4223         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4224                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4225                  pci_dev->addr.bus, pci_dev->addr.devid,
4226                  pci_dev->addr.function, "tx_port_stats");
4227         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4228         mz = rte_memzone_lookup(mz_name);
4229         total_alloc_len =
4230                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4231                                        sizeof(struct tx_port_stats_ext) + 512);
4232         if (!mz) {
4233                 mz = rte_memzone_reserve(mz_name,
4234                                          total_alloc_len,
4235                                          SOCKET_ID_ANY,
4236                                          RTE_MEMZONE_2MB |
4237                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4238                                          RTE_MEMZONE_IOVA_CONTIG);
4239                 if (mz == NULL)
4240                         return -ENOMEM;
4241         }
4242         memset(mz->addr, 0, mz->len);
4243         mz_phys_addr = mz->iova;
4244         if ((unsigned long)mz->addr == mz_phys_addr) {
4245                 PMD_DRV_LOG(DEBUG,
4246                             "Memzone physical address same as virtual\n");
4247                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4248                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4249                 if (mz_phys_addr == RTE_BAD_IOVA) {
4250                         PMD_DRV_LOG(ERR,
4251                                     "Can't map address to physical memory\n");
4252                         return -ENOMEM;
4253                 }
4254         }
4255
4256         bp->tx_mem_zone = (const void *)mz;
4257         bp->hw_tx_port_stats = mz->addr;
4258         bp->hw_tx_port_stats_map = mz_phys_addr;
4259         bp->flags |= BNXT_FLAG_PORT_STATS;
4260
4261         /* Display extended statistics if FW supports it */
4262         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4263             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4264             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4265                 return 0;
4266
4267         bp->hw_rx_port_stats_ext = (void *)
4268                 ((uint8_t *)bp->hw_rx_port_stats +
4269                  sizeof(struct rx_port_stats));
4270         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4271                 sizeof(struct rx_port_stats);
4272         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4273
4274         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4275             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4276                 bp->hw_tx_port_stats_ext = (void *)
4277                         ((uint8_t *)bp->hw_tx_port_stats +
4278                          sizeof(struct tx_port_stats));
4279                 bp->hw_tx_port_stats_ext_map =
4280                         bp->hw_tx_port_stats_map +
4281                         sizeof(struct tx_port_stats);
4282                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4283         }
4284
4285         return 0;
4286 }
4287
4288 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4289 {
4290         struct bnxt *bp = eth_dev->data->dev_private;
4291         int rc = 0;
4292
4293         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4294                                                RTE_ETHER_ADDR_LEN *
4295                                                bp->max_l2_ctx,
4296                                                0);
4297         if (eth_dev->data->mac_addrs == NULL) {
4298                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4299                 return -ENOMEM;
4300         }
4301
4302         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4303                 if (BNXT_PF(bp))
4304                         return -EINVAL;
4305
4306                 /* Generate a random MAC address, if none was assigned by PF */
4307                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4308                 bnxt_eth_hw_addr_random(bp->mac_addr);
4309                 PMD_DRV_LOG(INFO,
4310                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4311                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4312                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4313
4314                 rc = bnxt_hwrm_set_mac(bp);
4315                 if (!rc)
4316                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4317                                RTE_ETHER_ADDR_LEN);
4318                 return rc;
4319         }
4320
4321         /* Copy the permanent MAC from the FUNC_QCAPS response */
4322         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4323         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4324
4325         return rc;
4326 }
4327
4328 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4329 {
4330         int rc = 0;
4331
4332         /* MAC is already configured in FW */
4333         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4334                 return 0;
4335
4336         /* Restore the old MAC configured */
4337         rc = bnxt_hwrm_set_mac(bp);
4338         if (rc)
4339                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4340
4341         return rc;
4342 }
4343
4344 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4345 {
4346         if (!BNXT_PF(bp))
4347                 return;
4348
4349 #define ALLOW_FUNC(x)   \
4350         { \
4351                 uint32_t arg = (x); \
4352                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4353                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4354         }
4355
4356         /* Forward all requests if firmware is new enough */
4357         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4358              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4359             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4360                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4361         } else {
4362                 PMD_DRV_LOG(WARNING,
4363                             "Firmware too old for VF mailbox functionality\n");
4364                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4365         }
4366
4367         /*
4368          * The following are used for driver cleanup. If we disallow these,
4369          * VF drivers can't clean up cleanly.
4370          */
4371         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4372         ALLOW_FUNC(HWRM_VNIC_FREE);
4373         ALLOW_FUNC(HWRM_RING_FREE);
4374         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4375         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4376         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4377         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4378         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4379         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4380 }
4381
4382 static int bnxt_init_fw(struct bnxt *bp)
4383 {
4384         uint16_t mtu;
4385         int rc = 0;
4386
4387         rc = bnxt_hwrm_ver_get(bp);
4388         if (rc)
4389                 return rc;
4390
4391         rc = bnxt_hwrm_func_reset(bp);
4392         if (rc)
4393                 return -EIO;
4394
4395         rc = bnxt_hwrm_queue_qportcfg(bp);
4396         if (rc)
4397                 return rc;
4398
4399         /* Get the MAX capabilities for this function */
4400         rc = bnxt_hwrm_func_qcaps(bp);
4401         if (rc)
4402                 return rc;
4403
4404         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4405         if (rc)
4406                 return rc;
4407
4408         /* Get the adapter error recovery support info */
4409         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4410         if (rc)
4411                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4412
4413         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4414             mtu != bp->eth_dev->data->mtu)
4415                 bp->eth_dev->data->mtu = mtu;
4416
4417         bnxt_hwrm_port_led_qcaps(bp);
4418
4419         return 0;
4420 }
4421
4422 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4423 {
4424         int rc;
4425
4426         rc = bnxt_init_fw(bp);
4427         if (rc)
4428                 return rc;
4429
4430         if (!reconfig_dev) {
4431                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4432                 if (rc)
4433                         return rc;
4434         } else {
4435                 rc = bnxt_restore_dflt_mac(bp);
4436                 if (rc)
4437                         return rc;
4438         }
4439
4440         bnxt_config_vf_req_fwd(bp);
4441
4442         rc = bnxt_hwrm_func_driver_register(bp);
4443         if (rc) {
4444                 PMD_DRV_LOG(ERR, "Failed to register driver");
4445                 return -EBUSY;
4446         }
4447
4448         if (BNXT_PF(bp)) {
4449                 if (bp->pdev->max_vfs) {
4450                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4451                         if (rc) {
4452                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4453                                 return rc;
4454                         }
4455                 } else {
4456                         rc = bnxt_hwrm_allocate_pf_only(bp);
4457                         if (rc) {
4458                                 PMD_DRV_LOG(ERR,
4459                                             "Failed to allocate PF resources");
4460                                 return rc;
4461                         }
4462                 }
4463         }
4464
4465         rc = bnxt_alloc_mem(bp, reconfig_dev);
4466         if (rc)
4467                 return rc;
4468
4469         rc = bnxt_setup_int(bp);
4470         if (rc)
4471                 return rc;
4472
4473         bnxt_init_nic(bp);
4474
4475         rc = bnxt_request_int(bp);
4476         if (rc)
4477                 return rc;
4478
4479         return 0;
4480 }
4481
4482 static int
4483 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4484 {
4485         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4486         static int version_printed;
4487         struct bnxt *bp;
4488         int rc;
4489
4490         if (version_printed++ == 0)
4491                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4492
4493         eth_dev->dev_ops = &bnxt_dev_ops;
4494         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4495         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4496
4497         /*
4498          * For secondary processes, we don't initialise any further
4499          * as primary has already done this work.
4500          */
4501         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4502                 return 0;
4503
4504         rte_eth_copy_pci_info(eth_dev, pci_dev);
4505
4506         bp = eth_dev->data->dev_private;
4507
4508         bp->dev_stopped = 1;
4509
4510         if (bnxt_vf_pciid(pci_dev->id.device_id))
4511                 bp->flags |= BNXT_FLAG_VF;
4512
4513         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4514             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4515             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4516             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4517             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4518                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4519
4520         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4521             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4522             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4523             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4524                 bp->flags |= BNXT_FLAG_STINGRAY;
4525
4526         rc = bnxt_init_board(eth_dev);
4527         if (rc) {
4528                 PMD_DRV_LOG(ERR,
4529                             "Failed to initialize board rc: %x\n", rc);
4530                 return rc;
4531         }
4532
4533         rc = bnxt_alloc_hwrm_resources(bp);
4534         if (rc) {
4535                 PMD_DRV_LOG(ERR,
4536                             "Failed to allocate hwrm resource rc: %x\n", rc);
4537                 goto error_free;
4538         }
4539         rc = bnxt_init_resources(bp, false);
4540         if (rc)
4541                 goto error_free;
4542
4543         rc = bnxt_alloc_stats_mem(bp);
4544         if (rc)
4545                 goto error_free;
4546
4547         PMD_DRV_LOG(INFO,
4548                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4549                     pci_dev->mem_resource[0].phys_addr,
4550                     pci_dev->mem_resource[0].addr);
4551
4552         return 0;
4553
4554 error_free:
4555         bnxt_dev_uninit(eth_dev);
4556         return rc;
4557 }
4558
4559 static int
4560 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4561 {
4562         int rc;
4563
4564         bnxt_free_int(bp);
4565         bnxt_free_mem(bp, reconfig_dev);
4566         bnxt_hwrm_func_buf_unrgtr(bp);
4567         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4568         bp->flags &= ~BNXT_FLAG_REGISTERED;
4569         bnxt_free_ctx_mem(bp);
4570         if (!reconfig_dev) {
4571                 bnxt_free_hwrm_resources(bp);
4572
4573                 if (bp->recovery_info != NULL) {
4574                         rte_free(bp->recovery_info);
4575                         bp->recovery_info = NULL;
4576                 }
4577         }
4578
4579         rte_free(bp->ptp_cfg);
4580         bp->ptp_cfg = NULL;
4581         return rc;
4582 }
4583
4584 static int
4585 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4586 {
4587         struct bnxt *bp = eth_dev->data->dev_private;
4588         int rc;
4589
4590         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4591                 return -EPERM;
4592
4593         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4594
4595         rc = bnxt_uninit_resources(bp, false);
4596
4597         if (bp->grp_info != NULL) {
4598                 rte_free(bp->grp_info);
4599                 bp->grp_info = NULL;
4600         }
4601
4602         if (bp->tx_mem_zone) {
4603                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4604                 bp->tx_mem_zone = NULL;
4605         }
4606
4607         if (bp->rx_mem_zone) {
4608                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4609                 bp->rx_mem_zone = NULL;
4610         }
4611
4612         if (bp->dev_stopped == 0)
4613                 bnxt_dev_close_op(eth_dev);
4614         if (bp->pf.vf_info)
4615                 rte_free(bp->pf.vf_info);
4616         eth_dev->dev_ops = NULL;
4617         eth_dev->rx_pkt_burst = NULL;
4618         eth_dev->tx_pkt_burst = NULL;
4619
4620         return rc;
4621 }
4622
4623 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4624         struct rte_pci_device *pci_dev)
4625 {
4626         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4627                 bnxt_dev_init);
4628 }
4629
4630 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4631 {
4632         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4633                 return rte_eth_dev_pci_generic_remove(pci_dev,
4634                                 bnxt_dev_uninit);
4635         else
4636                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4637 }
4638
4639 static struct rte_pci_driver bnxt_rte_pmd = {
4640         .id_table = bnxt_pci_id_map,
4641         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4642         .probe = bnxt_pci_probe,
4643         .remove = bnxt_pci_remove,
4644 };
4645
4646 static bool
4647 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4648 {
4649         if (strcmp(dev->device->driver->name, drv->driver.name))
4650                 return false;
4651
4652         return true;
4653 }
4654
4655 bool is_bnxt_supported(struct rte_eth_dev *dev)
4656 {
4657         return is_device_supported(dev, &bnxt_rte_pmd);
4658 }
4659
4660 RTE_INIT(bnxt_init_log)
4661 {
4662         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4663         if (bnxt_logtype_driver >= 0)
4664                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4665 }
4666
4667 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4668 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4669 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");