drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 /*
  37  * The set of PCI devices this driver supports
  38  */
  39 static const struct rte_pci_id bnxt_pci_id_map[] = {
  40         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  41                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  93         { .vendor_id = 0, /* sentinel */ },
  94 };
  95
  96 #define BNXT_ETH_RSS_SUPPORT (  \
  97         ETH_RSS_IPV4 |          \
  98         ETH_RSS_NONFRAG_IPV4_TCP |      \
  99         ETH_RSS_NONFRAG_IPV4_UDP |      \
 100         ETH_RSS_IPV6 |          \
 101         ETH_RSS_NONFRAG_IPV6_TCP |      \
 102         ETH_RSS_NONFRAG_IPV6_UDP)
 103
 104 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 105                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 106                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 108                                      DEV_TX_OFFLOAD_TCP_TSO | \
 109                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 110                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 114                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 115                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 116
 117 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 118                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 119                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 120                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 122                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 123                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 124                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 125                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 126                                      DEV_RX_OFFLOAD_TCP_LRO | \
 127                                      DEV_RX_OFFLOAD_SCATTER | \
 128                                      DEV_RX_OFFLOAD_RSS_HASH)
 129
 130 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
 131 static const char *const bnxt_dev_args[] = {
 132         BNXT_DEVARG_TRUFLOW,
 133         NULL
 134 };
 135
 136 /*
 137  * truflow == false to disable the feature
 138  * truflow == true to enable the feature
 139  */
 140 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 141
 142 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 143 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 144 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 145 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 146 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 147 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 148 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 149 static void bnxt_dev_recover(void *arg);
 150
 151 int is_bnxt_in_error(struct bnxt *bp)
 152 {
 153         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 154                 return -EIO;
 155         if (bp->flags & BNXT_FLAG_FW_RESET)
 156                 return -EBUSY;
 157
 158         return 0;
 159 }
 160
 161 /***********************/
 162
 163 /*
 164  * High level utility functions
 165  */
 166
 167 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 168 {
 169         if (!BNXT_CHIP_THOR(bp))
 170                 return 1;
 171
 172         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 173                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 174                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 175 }
 176
 177 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 178 {
 179         if (!BNXT_CHIP_THOR(bp))
 180                 return HW_HASH_INDEX_SIZE;
 181
 182         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 183 }
 184
 185 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 186 {
 187         bnxt_free_filter_mem(bp);
 188         bnxt_free_vnic_attributes(bp);
 189         bnxt_free_vnic_mem(bp);
 190
 191         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 192          * If the number of rings change across fw update,
 193          * we don't have much choice except to warn the user.
 194          */
 195         if (!reconfig) {
 196                 bnxt_free_stats(bp);
 197                 bnxt_free_tx_rings(bp);
 198                 bnxt_free_rx_rings(bp);
 199         }
 200         bnxt_free_async_cp_ring(bp);
 201         bnxt_free_rxtx_nq_ring(bp);
 202
 203         rte_free(bp->grp_info);
 204         bp->grp_info = NULL;
 205 }
 206
 207 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 208 {
 209         int rc;
 210
 211         rc = bnxt_alloc_ring_grps(bp);
 212         if (rc)
 213                 goto alloc_mem_err;
 214
 215         rc = bnxt_alloc_async_ring_struct(bp);
 216         if (rc)
 217                 goto alloc_mem_err;
 218
 219         rc = bnxt_alloc_vnic_mem(bp);
 220         if (rc)
 221                 goto alloc_mem_err;
 222
 223         rc = bnxt_alloc_vnic_attributes(bp);
 224         if (rc)
 225                 goto alloc_mem_err;
 226
 227         rc = bnxt_alloc_filter_mem(bp);
 228         if (rc)
 229                 goto alloc_mem_err;
 230
 231         rc = bnxt_alloc_async_cp_ring(bp);
 232         if (rc)
 233                 goto alloc_mem_err;
 234
 235         rc = bnxt_alloc_rxtx_nq_ring(bp);
 236         if (rc)
 237                 goto alloc_mem_err;
 238
 239         return 0;
 240
 241 alloc_mem_err:
 242         bnxt_free_mem(bp, reconfig);
 243         return rc;
 244 }
 245
 246 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 247 {
 248         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 249         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 250         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 251         struct bnxt_rx_queue *rxq;
 252         unsigned int j;
 253         int rc;
 254
 255         rc = bnxt_vnic_grp_alloc(bp, vnic);
 256         if (rc)
 257                 goto err_out;
 258
 259         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 260                     vnic_id, vnic, vnic->fw_grp_ids);
 261
 262         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 263         if (rc)
 264                 goto err_out;
 265
 266         /* Alloc RSS context only if RSS mode is enabled */
 267         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 268                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 269
 270                 rc = 0;
 271                 for (j = 0; j < nr_ctxs; j++) {
 272                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 273                         if (rc)
 274                                 break;
 275                 }
 276                 if (rc) {
 277                         PMD_DRV_LOG(ERR,
 278                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 279                                     vnic_id, j, rc);
 280                         goto err_out;
 281                 }
 282                 vnic->num_lb_ctxts = nr_ctxs;
 283         }
 284
 285         /*
 286          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 287          * setting is not available at this time, it will not be
 288          * configured correctly in the CFA.
 289          */
 290         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 291                 vnic->vlan_strip = true;
 292         else
 293                 vnic->vlan_strip = false;
 294
 295         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 296         if (rc)
 297                 goto err_out;
 298
 299         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 300         if (rc)
 301                 goto err_out;
 302
 303         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 304                 rxq = bp->eth_dev->data->rx_queues[j];
 305
 306                 PMD_DRV_LOG(DEBUG,
 307                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 308                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 309
 310                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 311                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 312                 else
 313                         vnic->rx_queue_cnt++;
 314         }
 315
 316         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 317
 318         rc = bnxt_vnic_rss_configure(bp, vnic);
 319         if (rc)
 320                 goto err_out;
 321
 322         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 323
 324         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 325                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 326         else
 327                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 328
 329         return 0;
 330 err_out:
 331         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 332                     vnic_id, rc);
 333         return rc;
 334 }
 335
 336 static int bnxt_init_chip(struct bnxt *bp)
 337 {
 338         struct rte_eth_link new;
 339         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 340         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 341         uint32_t intr_vector = 0;
 342         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 343         uint32_t vec = BNXT_MISC_VEC_ID;
 344         unsigned int i, j;
 345         int rc;
 346
 347         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 348                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 349                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 350                 bp->flags |= BNXT_FLAG_JUMBO;
 351         } else {
 352                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 353                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 354                 bp->flags &= ~BNXT_FLAG_JUMBO;
 355         }
 356
 357         /* THOR does not support ring groups.
 358          * But we will use the array to save RSS context IDs.
 359          */
 360         if (BNXT_CHIP_THOR(bp))
 361                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 362
 363         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 364         if (rc) {
 365                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 366                 goto err_out;
 367         }
 368
 369         rc = bnxt_alloc_hwrm_rings(bp);
 370         if (rc) {
 371                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 372                 goto err_out;
 373         }
 374
 375         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 376         if (rc) {
 377                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 378                 goto err_out;
 379         }
 380
 381         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 382                 goto skip_cosq_cfg;
 383
 384         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 385                 if (bp->rx_cos_queue[i].id != 0xff) {
 386                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 387
 388                         if (!vnic) {
 389                                 PMD_DRV_LOG(ERR,
 390                                             "Num pools more than FW profile\n");
 391                                 rc = -EINVAL;
 392                                 goto err_out;
 393                         }
 394                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 395                         bp->rx_cosq_cnt++;
 396                 }
 397         }
 398
 399 skip_cosq_cfg:
 400         rc = bnxt_mq_rx_configure(bp);
 401         if (rc) {
 402                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 403                 goto err_out;
 404         }
 405
 406         /* VNIC configuration */
 407         for (i = 0; i < bp->nr_vnics; i++) {
 408                 rc = bnxt_setup_one_vnic(bp, i);
 409                 if (rc)
 410                         goto err_out;
 411         }
 412
 413         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 414         if (rc) {
 415                 PMD_DRV_LOG(ERR,
 416                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 417                 goto err_out;
 418         }
 419
 420         /* check and configure queue intr-vector mapping */
 421         if ((rte_intr_cap_multiple(intr_handle) ||
 422              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 423             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 424                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 425                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 426                 if (intr_vector > bp->rx_cp_nr_rings) {
 427                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 428                                         bp->rx_cp_nr_rings);
 429                         return -ENOTSUP;
 430                 }
 431                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 432                 if (rc)
 433                         return rc;
 434         }
 435
 436         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 437                 intr_handle->intr_vec =
 438                         rte_zmalloc("intr_vec",
 439                                     bp->eth_dev->data->nb_rx_queues *
 440                                     sizeof(int), 0);
 441                 if (intr_handle->intr_vec == NULL) {
 442                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 443                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 444                         rc = -ENOMEM;
 445                         goto err_disable;
 446                 }
 447                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 448                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 449                          intr_handle->intr_vec, intr_handle->nb_efd,
 450                         intr_handle->max_intr);
 451                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 452                      queue_id++) {
 453                         intr_handle->intr_vec[queue_id] =
 454                                                         vec + BNXT_RX_VEC_START;
 455                         if (vec < base + intr_handle->nb_efd - 1)
 456                                 vec++;
 457                 }
 458         }
 459
 460         /* enable uio/vfio intr/eventfd mapping */
 461         rc = rte_intr_enable(intr_handle);
 462 #ifndef RTE_EXEC_ENV_FREEBSD
 463         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 464         if (rc)
 465                 goto err_free;
 466 #endif
 467
 468         rc = bnxt_get_hwrm_link_config(bp, &new);
 469         if (rc) {
 470                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 471                 goto err_free;
 472         }
 473
 474         if (!bp->link_info.link_up) {
 475                 rc = bnxt_set_hwrm_link_config(bp, true);
 476                 if (rc) {
 477                         PMD_DRV_LOG(ERR,
 478                                 "HWRM link config failure rc: %x\n", rc);
 479                         goto err_free;
 480                 }
 481         }
 482         bnxt_print_link_info(bp->eth_dev);
 483
 484         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 485         if (!bp->mark_table)
 486                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 487
 488         return 0;
 489
 490 err_free:
 491         rte_free(intr_handle->intr_vec);
 492 err_disable:
 493         rte_intr_efd_disable(intr_handle);
 494 err_out:
 495         /* Some of the error status returned by FW may not be from errno.h */
 496         if (rc > 0)
 497                 rc = -EIO;
 498
 499         return rc;
 500 }
 501
 502 static int bnxt_shutdown_nic(struct bnxt *bp)
 503 {
 504         bnxt_free_all_hwrm_resources(bp);
 505         bnxt_free_all_filters(bp);
 506         bnxt_free_all_vnics(bp);
 507         return 0;
 508 }
 509
 510 /*
 511  * Device configuration and status function
 512  */
 513
 514 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 515                                 struct rte_eth_dev_info *dev_info)
 516 {
 517         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 518         struct bnxt *bp = eth_dev->data->dev_private;
 519         uint16_t max_vnics, i, j, vpool, vrxq;
 520         unsigned int max_rx_rings;
 521         int rc;
 522
 523         rc = is_bnxt_in_error(bp);
 524         if (rc)
 525                 return rc;
 526
 527         /* MAC Specifics */
 528         dev_info->max_mac_addrs = bp->max_l2_ctx;
 529         dev_info->max_hash_mac_addrs = 0;
 530
 531         /* PF/VF specifics */
 532         if (BNXT_PF(bp))
 533                 dev_info->max_vfs = pdev->max_vfs;
 534
 535         max_rx_rings = BNXT_MAX_RINGS(bp);
 536         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 537         dev_info->max_rx_queues = max_rx_rings;
 538         dev_info->max_tx_queues = max_rx_rings;
 539         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 540         dev_info->hash_key_size = 40;
 541         max_vnics = bp->max_vnics;
 542
 543         /* MTU specifics */
 544         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 545         dev_info->max_mtu = BNXT_MAX_MTU;
 546
 547         /* Fast path specifics */
 548         dev_info->min_rx_bufsize = 1;
 549         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 550
 551         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 552         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 553                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 554         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 555         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 556
 557         /* *INDENT-OFF* */
 558         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 559                 .rx_thresh = {
 560                         .pthresh = 8,
 561                         .hthresh = 8,
 562                         .wthresh = 0,
 563                 },
 564                 .rx_free_thresh = 32,
 565                 /* If no descriptors available, pkts are dropped by default */
 566                 .rx_drop_en = 1,
 567         };
 568
 569         dev_info->default_txconf = (struct rte_eth_txconf) {
 570                 .tx_thresh = {
 571                         .pthresh = 32,
 572                         .hthresh = 0,
 573                         .wthresh = 0,
 574                 },
 575                 .tx_free_thresh = 32,
 576                 .tx_rs_thresh = 32,
 577         };
 578         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 579
 580         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 581         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 582         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 583         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 584         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 585
 586         /* *INDENT-ON* */
 587
 588         /*
 589          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 590          *       need further investigation.
 591          */
 592
 593         /* VMDq resources */
 594         vpool = 64; /* ETH_64_POOLS */
 595         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 596         for (i = 0; i < 4; vpool >>= 1, i++) {
 597                 if (max_vnics > vpool) {
 598                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 599                                 if (dev_info->max_rx_queues > vrxq) {
 600                                         if (vpool > vrxq)
 601                                                 vpool = vrxq;
 602                                         goto found;
 603                                 }
 604                         }
 605                         /* Not enough resources to support VMDq */
 606                         break;
 607                 }
 608         }
 609         /* Not enough resources to support VMDq */
 610         vpool = 0;
 611         vrxq = 0;
 612 found:
 613         dev_info->max_vmdq_pools = vpool;
 614         dev_info->vmdq_queue_num = vrxq;
 615
 616         dev_info->vmdq_pool_base = 0;
 617         dev_info->vmdq_queue_base = 0;
 618
 619         return 0;
 620 }
 621
 622 /* Configure the device based on the configuration provided */
 623 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 624 {
 625         struct bnxt *bp = eth_dev->data->dev_private;
 626         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 627         int rc;
 628
 629         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 630         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 631         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 632         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 633
 634         rc = is_bnxt_in_error(bp);
 635         if (rc)
 636                 return rc;
 637
 638         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 639                 rc = bnxt_hwrm_check_vf_rings(bp);
 640                 if (rc) {
 641                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 642                         return -ENOSPC;
 643                 }
 644
 645                 /* If a resource has already been allocated - in this case
 646                  * it is the async completion ring, free it. Reallocate it after
 647                  * resource reservation. This will ensure the resource counts
 648                  * are calculated correctly.
 649                  */
 650
 651                 pthread_mutex_lock(&bp->def_cp_lock);
 652
 653                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 654                         bnxt_disable_int(bp);
 655                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 656                 }
 657
 658                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 659                 if (rc) {
 660                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 661                         pthread_mutex_unlock(&bp->def_cp_lock);
 662                         return -ENOSPC;
 663                 }
 664
 665                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 666                         rc = bnxt_alloc_async_cp_ring(bp);
 667                         if (rc) {
 668                                 pthread_mutex_unlock(&bp->def_cp_lock);
 669                                 return rc;
 670                         }
 671                         bnxt_enable_int(bp);
 672                 }
 673
 674                 pthread_mutex_unlock(&bp->def_cp_lock);
 675         } else {
 676                 /* legacy driver needs to get updated values */
 677                 rc = bnxt_hwrm_func_qcaps(bp);
 678                 if (rc) {
 679                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 680                         return rc;
 681                 }
 682         }
 683
 684         /* Inherit new configurations */
 685         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 686             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 687             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 688                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 689             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 690             bp->max_stat_ctx)
 691                 goto resource_error;
 692
 693         if (BNXT_HAS_RING_GRPS(bp) &&
 694             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 695                 goto resource_error;
 696
 697         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 698             bp->max_vnics < eth_dev->data->nb_rx_queues)
 699                 goto resource_error;
 700
 701         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 702         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 703
 704         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 705                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 706         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
 707
 708         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 709                 eth_dev->data->mtu =
 710                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 711                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 712                         BNXT_NUM_VLANS;
 713                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 714         }
 715         return 0;
 716
 717 resource_error:
 718         PMD_DRV_LOG(ERR,
 719                     "Insufficient resources to support requested config\n");
 720         PMD_DRV_LOG(ERR,
 721                     "Num Queues Requested: Tx %d, Rx %d\n",
 722                     eth_dev->data->nb_tx_queues,
 723                     eth_dev->data->nb_rx_queues);
 724         PMD_DRV_LOG(ERR,
 725                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 726                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 727                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 728         return -ENOSPC;
 729 }
 730
 731 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 732 {
 733         struct rte_eth_link *link = &eth_dev->data->dev_link;
 734
 735         if (link->link_status)
 736                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 737                         eth_dev->data->port_id,
 738                         (uint32_t)link->link_speed,
 739                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 740                         ("full-duplex") : ("half-duplex\n"));
 741         else
 742                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 743                         eth_dev->data->port_id);
 744 }
 745
 746 /*
 747  * Determine whether the current configuration requires support for scattered
 748  * receive; return 1 if scattered receive is required and 0 if not.
 749  */
 750 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 751 {
 752         uint16_t buf_size;
 753         int i;
 754
 755         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 756                 return 1;
 757
 758         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 759                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 760
 761                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 762                                       RTE_PKTMBUF_HEADROOM);
 763                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 764                         return 1;
 765         }
 766         return 0;
 767 }
 768
 769 static eth_rx_burst_t
 770 bnxt_receive_function(struct rte_eth_dev *eth_dev)
 771 {
 772         struct bnxt *bp = eth_dev->data->dev_private;
 773
 774 #ifdef RTE_ARCH_X86
 775 #ifndef RTE_LIBRTE_IEEE1588
 776         /*
 777          * Vector mode receive can be enabled only if scatter rx is not
 778          * in use and rx offloads are limited to VLAN stripping and
 779          * CRC stripping.
 780          */
 781         if (!eth_dev->data->scattered_rx &&
 782             !(eth_dev->data->dev_conf.rxmode.offloads &
 783               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 784                 DEV_RX_OFFLOAD_KEEP_CRC |
 785                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 786                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 787                 DEV_RX_OFFLOAD_UDP_CKSUM |
 788                 DEV_RX_OFFLOAD_TCP_CKSUM |
 789                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 790                 DEV_RX_OFFLOAD_RSS_HASH |
 791                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
 792             !bp->truflow) {
 793                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 794                             eth_dev->data->port_id);
 795                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
 796                 return bnxt_recv_pkts_vec;
 797         }
 798         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 799                     eth_dev->data->port_id);
 800         PMD_DRV_LOG(INFO,
 801                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 802                     eth_dev->data->port_id,
 803                     eth_dev->data->scattered_rx,
 804                     eth_dev->data->dev_conf.rxmode.offloads);
 805 #endif
 806 #endif
 807         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
 808         return bnxt_recv_pkts;
 809 }
 810
 811 static eth_tx_burst_t
 812 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 813 {
 814 #ifdef RTE_ARCH_X86
 815 #ifndef RTE_LIBRTE_IEEE1588
 816         /*
 817          * Vector mode transmit can be enabled only if not using scatter rx
 818          * or tx offloads.
 819          */
 820         if (!eth_dev->data->scattered_rx &&
 821             !eth_dev->data->dev_conf.txmode.offloads) {
 822                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 823                             eth_dev->data->port_id);
 824                 return bnxt_xmit_pkts_vec;
 825         }
 826         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 827                     eth_dev->data->port_id);
 828         PMD_DRV_LOG(INFO,
 829                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 830                     eth_dev->data->port_id,
 831                     eth_dev->data->scattered_rx,
 832                     eth_dev->data->dev_conf.txmode.offloads);
 833 #endif
 834 #endif
 835         return bnxt_xmit_pkts;
 836 }
 837
 838 static int bnxt_handle_if_change_status(struct bnxt *bp)
 839 {
 840         int rc;
 841
 842         /* Since fw has undergone a reset and lost all contexts,
 843          * set fatal flag to not issue hwrm during cleanup
 844          */
 845         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 846         bnxt_uninit_resources(bp, true);
 847
 848         /* clear fatal flag so that re-init happens */
 849         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 850         rc = bnxt_init_resources(bp, true);
 851
 852         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 853
 854         return rc;
 855 }
 856
 857 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 858 {
 859         struct bnxt *bp = eth_dev->data->dev_private;
 860         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 861         int vlan_mask = 0;
 862         int rc;
 863
 864         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
 865                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
 866                 return -EINVAL;
 867         }
 868
 869         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 870                 PMD_DRV_LOG(ERR,
 871                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 872                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 873         }
 874
 875         rc = bnxt_hwrm_if_change(bp, 1);
 876         if (!rc) {
 877                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 878                         rc = bnxt_handle_if_change_status(bp);
 879                         if (rc)
 880                                 return rc;
 881                 }
 882         }
 883         bnxt_enable_int(bp);
 884
 885         rc = bnxt_init_chip(bp);
 886         if (rc)
 887                 goto error;
 888
 889         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 890         eth_dev->data->dev_started = 1;
 891
 892         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
 893
 894         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 895                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 896         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 897                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 898         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 899         if (rc)
 900                 goto error;
 901
 902         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 903         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 904
 905         pthread_mutex_lock(&bp->def_cp_lock);
 906         bnxt_schedule_fw_health_check(bp);
 907         pthread_mutex_unlock(&bp->def_cp_lock);
 908
 909         if (bp->truflow)
 910                 bnxt_ulp_init(bp);
 911
 912         return 0;
 913
 914 error:
 915         bnxt_hwrm_if_change(bp, 0);
 916         bnxt_shutdown_nic(bp);
 917         bnxt_free_tx_mbufs(bp);
 918         bnxt_free_rx_mbufs(bp);
 919         eth_dev->data->dev_started = 0;
 920         return rc;
 921 }
 922
 923 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 924 {
 925         struct bnxt *bp = eth_dev->data->dev_private;
 926         int rc = 0;
 927
 928         if (!bp->link_info.link_up)
 929                 rc = bnxt_set_hwrm_link_config(bp, true);
 930         if (!rc)
 931                 eth_dev->data->dev_link.link_status = 1;
 932
 933         bnxt_print_link_info(eth_dev);
 934         return rc;
 935 }
 936
 937 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 938 {
 939         struct bnxt *bp = eth_dev->data->dev_private;
 940
 941         eth_dev->data->dev_link.link_status = 0;
 942         bnxt_set_hwrm_link_config(bp, false);
 943         bp->link_info.link_up = 0;
 944
 945         return 0;
 946 }
 947
 948 /* Unload the driver, release resources */
 949 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 950 {
 951         struct bnxt *bp = eth_dev->data->dev_private;
 952         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 953         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 954
 955         if (bp->truflow)
 956                 bnxt_ulp_deinit(bp);
 957
 958         eth_dev->data->dev_started = 0;
 959         /* Prevent crashes when queues are still in use */
 960         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 961         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 962
 963         bnxt_disable_int(bp);
 964
 965         /* disable uio/vfio intr/eventfd mapping */
 966         rte_intr_disable(intr_handle);
 967
 968         bnxt_cancel_fw_health_check(bp);
 969
 970         bnxt_dev_set_link_down_op(eth_dev);
 971
 972         /* Wait for link to be reset and the async notification to process.
 973          * During reset recovery, there is no need to wait and
 974          * VF/NPAR functions do not have privilege to change PHY config.
 975          */
 976         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
 977                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
 978
 979         /* Clean queue intr-vector mapping */
 980         rte_intr_efd_disable(intr_handle);
 981         if (intr_handle->intr_vec != NULL) {
 982                 rte_free(intr_handle->intr_vec);
 983                 intr_handle->intr_vec = NULL;
 984         }
 985
 986         bnxt_hwrm_port_clr_stats(bp);
 987         bnxt_free_tx_mbufs(bp);
 988         bnxt_free_rx_mbufs(bp);
 989         /* Process any remaining notifications in default completion queue */
 990         bnxt_int_handler(eth_dev);
 991         bnxt_shutdown_nic(bp);
 992         bnxt_hwrm_if_change(bp, 0);
 993
 994         rte_free(bp->mark_table);
 995         bp->mark_table = NULL;
 996
 997         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
 998         bp->rx_cosq_cnt = 0;
 999 }
1000
1001 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1002 {
1003         struct bnxt *bp = eth_dev->data->dev_private;
1004
1005         /* cancel the recovery handler before remove dev */
1006         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1007         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1008
1009         if (eth_dev->data->dev_started)
1010                 bnxt_dev_stop_op(eth_dev);
1011
1012         bnxt_uninit_resources(bp, false);
1013
1014         eth_dev->dev_ops = NULL;
1015         eth_dev->rx_pkt_burst = NULL;
1016         eth_dev->tx_pkt_burst = NULL;
1017
1018         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1019         bp->tx_mem_zone = NULL;
1020         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1021         bp->rx_mem_zone = NULL;
1022
1023         rte_free(bp->pf.vf_info);
1024         bp->pf.vf_info = NULL;
1025
1026         rte_free(bp->grp_info);
1027         bp->grp_info = NULL;
1028 }
1029
1030 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1031                                     uint32_t index)
1032 {
1033         struct bnxt *bp = eth_dev->data->dev_private;
1034         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1035         struct bnxt_vnic_info *vnic;
1036         struct bnxt_filter_info *filter, *temp_filter;
1037         uint32_t i;
1038
1039         if (is_bnxt_in_error(bp))
1040                 return;
1041
1042         /*
1043          * Loop through all VNICs from the specified filter flow pools to
1044          * remove the corresponding MAC addr filter
1045          */
1046         for (i = 0; i < bp->nr_vnics; i++) {
1047                 if (!(pool_mask & (1ULL << i)))
1048                         continue;
1049
1050                 vnic = &bp->vnic_info[i];
1051                 filter = STAILQ_FIRST(&vnic->filter);
1052                 while (filter) {
1053                         temp_filter = STAILQ_NEXT(filter, next);
1054                         if (filter->mac_index == index) {
1055                                 STAILQ_REMOVE(&vnic->filter, filter,
1056                                                 bnxt_filter_info, next);
1057                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1058                                 bnxt_free_filter(bp, filter);
1059                         }
1060                         filter = temp_filter;
1061                 }
1062         }
1063 }
1064
1065 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1066                                struct rte_ether_addr *mac_addr, uint32_t index,
1067                                uint32_t pool)
1068 {
1069         struct bnxt_filter_info *filter;
1070         int rc = 0;
1071
1072         /* Attach requested MAC address to the new l2_filter */
1073         STAILQ_FOREACH(filter, &vnic->filter, next) {
1074                 if (filter->mac_index == index) {
1075                         PMD_DRV_LOG(DEBUG,
1076                                     "MAC addr already existed for pool %d\n",
1077                                     pool);
1078                         return 0;
1079                 }
1080         }
1081
1082         filter = bnxt_alloc_filter(bp);
1083         if (!filter) {
1084                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1085                 return -ENODEV;
1086         }
1087
1088         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1089          * if the MAC that's been programmed now is a different one, then,
1090          * copy that addr to filter->l2_addr
1091          */
1092         if (mac_addr)
1093                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1094         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1095
1096         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1097         if (!rc) {
1098                 filter->mac_index = index;
1099                 if (filter->mac_index == 0)
1100                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1101                 else
1102                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1103         } else {
1104                 bnxt_free_filter(bp, filter);
1105         }
1106
1107         return rc;
1108 }
1109
1110 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1111                                 struct rte_ether_addr *mac_addr,
1112                                 uint32_t index, uint32_t pool)
1113 {
1114         struct bnxt *bp = eth_dev->data->dev_private;
1115         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1116         int rc = 0;
1117
1118         rc = is_bnxt_in_error(bp);
1119         if (rc)
1120                 return rc;
1121
1122         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1123                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1124                 return -ENOTSUP;
1125         }
1126
1127         if (!vnic) {
1128                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1129                 return -EINVAL;
1130         }
1131
1132         /* Filter settings will get applied when port is started */
1133         if (!eth_dev->data->dev_started)
1134                 return 0;
1135
1136         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1137
1138         return rc;
1139 }
1140
1141 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1142                      bool exp_link_status)
1143 {
1144         int rc = 0;
1145         struct bnxt *bp = eth_dev->data->dev_private;
1146         struct rte_eth_link new;
1147         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1148                   BNXT_LINK_DOWN_WAIT_CNT;
1149
1150         rc = is_bnxt_in_error(bp);
1151         if (rc)
1152                 return rc;
1153
1154         memset(&new, 0, sizeof(new));
1155         do {
1156                 /* Retrieve link info from hardware */
1157                 rc = bnxt_get_hwrm_link_config(bp, &new);
1158                 if (rc) {
1159                         new.link_speed = ETH_LINK_SPEED_100M;
1160                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1161                         PMD_DRV_LOG(ERR,
1162                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1163                         goto out;
1164                 }
1165
1166                 if (!wait_to_complete || new.link_status == exp_link_status)
1167                         break;
1168
1169                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1170         } while (cnt--);
1171
1172 out:
1173         /* Timed out or success */
1174         if (new.link_status != eth_dev->data->dev_link.link_status ||
1175         new.link_speed != eth_dev->data->dev_link.link_speed) {
1176                 rte_eth_linkstatus_set(eth_dev, &new);
1177
1178                 _rte_eth_dev_callback_process(eth_dev,
1179                                               RTE_ETH_EVENT_INTR_LSC,
1180                                               NULL);
1181
1182                 bnxt_print_link_info(eth_dev);
1183         }
1184
1185         return rc;
1186 }
1187
1188 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1189                                int wait_to_complete)
1190 {
1191         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1192 }
1193
1194 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1195 {
1196         struct bnxt *bp = eth_dev->data->dev_private;
1197         struct bnxt_vnic_info *vnic;
1198         uint32_t old_flags;
1199         int rc;
1200
1201         rc = is_bnxt_in_error(bp);
1202         if (rc)
1203                 return rc;
1204
1205         /* Filter settings will get applied when port is started */
1206         if (!eth_dev->data->dev_started)
1207                 return 0;
1208
1209         if (bp->vnic_info == NULL)
1210                 return 0;
1211
1212         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1213
1214         old_flags = vnic->flags;
1215         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1216         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1217         if (rc != 0)
1218                 vnic->flags = old_flags;
1219
1220         return rc;
1221 }
1222
1223 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1224 {
1225         struct bnxt *bp = eth_dev->data->dev_private;
1226         struct bnxt_vnic_info *vnic;
1227         uint32_t old_flags;
1228         int rc;
1229
1230         rc = is_bnxt_in_error(bp);
1231         if (rc)
1232                 return rc;
1233
1234         /* Filter settings will get applied when port is started */
1235         if (!eth_dev->data->dev_started)
1236                 return 0;
1237
1238         if (bp->vnic_info == NULL)
1239                 return 0;
1240
1241         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1242
1243         old_flags = vnic->flags;
1244         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1245         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1246         if (rc != 0)
1247                 vnic->flags = old_flags;
1248
1249         return rc;
1250 }
1251
1252 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1253 {
1254         struct bnxt *bp = eth_dev->data->dev_private;
1255         struct bnxt_vnic_info *vnic;
1256         uint32_t old_flags;
1257         int rc;
1258
1259         rc = is_bnxt_in_error(bp);
1260         if (rc)
1261                 return rc;
1262
1263         /* Filter settings will get applied when port is started */
1264         if (!eth_dev->data->dev_started)
1265                 return 0;
1266
1267         if (bp->vnic_info == NULL)
1268                 return 0;
1269
1270         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1271
1272         old_flags = vnic->flags;
1273         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1274         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1275         if (rc != 0)
1276                 vnic->flags = old_flags;
1277
1278         return rc;
1279 }
1280
1281 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1282 {
1283         struct bnxt *bp = eth_dev->data->dev_private;
1284         struct bnxt_vnic_info *vnic;
1285         uint32_t old_flags;
1286         int rc;
1287
1288         rc = is_bnxt_in_error(bp);
1289         if (rc)
1290                 return rc;
1291
1292         /* Filter settings will get applied when port is started */
1293         if (!eth_dev->data->dev_started)
1294                 return 0;
1295
1296         if (bp->vnic_info == NULL)
1297                 return 0;
1298
1299         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1300
1301         old_flags = vnic->flags;
1302         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1303         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1304         if (rc != 0)
1305                 vnic->flags = old_flags;
1306
1307         return rc;
1308 }
1309
1310 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1311 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1312 {
1313         if (qid >= bp->rx_nr_rings)
1314                 return NULL;
1315
1316         return bp->eth_dev->data->rx_queues[qid];
1317 }
1318
1319 /* Return rxq corresponding to a given rss table ring/group ID. */
1320 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1321 {
1322         struct bnxt_rx_queue *rxq;
1323         unsigned int i;
1324
1325         if (!BNXT_HAS_RING_GRPS(bp)) {
1326                 for (i = 0; i < bp->rx_nr_rings; i++) {
1327                         rxq = bp->eth_dev->data->rx_queues[i];
1328                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1329                                 return rxq->index;
1330                 }
1331         } else {
1332                 for (i = 0; i < bp->rx_nr_rings; i++) {
1333                         if (bp->grp_info[i].fw_grp_id == fwr)
1334                                 return i;
1335                 }
1336         }
1337
1338         return INVALID_HW_RING_ID;
1339 }
1340
1341 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1342                             struct rte_eth_rss_reta_entry64 *reta_conf,
1343                             uint16_t reta_size)
1344 {
1345         struct bnxt *bp = eth_dev->data->dev_private;
1346         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1347         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1348         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1349         uint16_t idx, sft;
1350         int i, rc;
1351
1352         rc = is_bnxt_in_error(bp);
1353         if (rc)
1354                 return rc;
1355
1356         if (!vnic->rss_table)
1357                 return -EINVAL;
1358
1359         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1360                 return -EINVAL;
1361
1362         if (reta_size != tbl_size) {
1363                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1364                         "(%d) must equal the size supported by the hardware "
1365                         "(%d)\n", reta_size, tbl_size);
1366                 return -EINVAL;
1367         }
1368
1369         for (i = 0; i < reta_size; i++) {
1370                 struct bnxt_rx_queue *rxq;
1371
1372                 idx = i / RTE_RETA_GROUP_SIZE;
1373                 sft = i % RTE_RETA_GROUP_SIZE;
1374
1375                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1376                         continue;
1377
1378                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1379                 if (!rxq) {
1380                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1381                         return -EINVAL;
1382                 }
1383
1384                 if (BNXT_CHIP_THOR(bp)) {
1385                         vnic->rss_table[i * 2] =
1386                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1387                         vnic->rss_table[i * 2 + 1] =
1388                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1389                 } else {
1390                         vnic->rss_table[i] =
1391                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1392                 }
1393         }
1394
1395         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1396         return 0;
1397 }
1398
1399 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1400                               struct rte_eth_rss_reta_entry64 *reta_conf,
1401                               uint16_t reta_size)
1402 {
1403         struct bnxt *bp = eth_dev->data->dev_private;
1404         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1405         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1406         uint16_t idx, sft, i;
1407         int rc;
1408
1409         rc = is_bnxt_in_error(bp);
1410         if (rc)
1411                 return rc;
1412
1413         /* Retrieve from the default VNIC */
1414         if (!vnic)
1415                 return -EINVAL;
1416         if (!vnic->rss_table)
1417                 return -EINVAL;
1418
1419         if (reta_size != tbl_size) {
1420                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1421                         "(%d) must equal the size supported by the hardware "
1422                         "(%d)\n", reta_size, tbl_size);
1423                 return -EINVAL;
1424         }
1425
1426         for (idx = 0, i = 0; i < reta_size; i++) {
1427                 idx = i / RTE_RETA_GROUP_SIZE;
1428                 sft = i % RTE_RETA_GROUP_SIZE;
1429
1430                 if (reta_conf[idx].mask & (1ULL << sft)) {
1431                         uint16_t qid;
1432
1433                         if (BNXT_CHIP_THOR(bp))
1434                                 qid = bnxt_rss_to_qid(bp,
1435                                                       vnic->rss_table[i * 2]);
1436                         else
1437                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1438
1439                         if (qid == INVALID_HW_RING_ID) {
1440                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1441                                 return -EINVAL;
1442                         }
1443                         reta_conf[idx].reta[sft] = qid;
1444                 }
1445         }
1446
1447         return 0;
1448 }
1449
1450 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1451                                    struct rte_eth_rss_conf *rss_conf)
1452 {
1453         struct bnxt *bp = eth_dev->data->dev_private;
1454         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1455         struct bnxt_vnic_info *vnic;
1456         int rc;
1457
1458         rc = is_bnxt_in_error(bp);
1459         if (rc)
1460                 return rc;
1461
1462         /*
1463          * If RSS enablement were different than dev_configure,
1464          * then return -EINVAL
1465          */
1466         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1467                 if (!rss_conf->rss_hf)
1468                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1469         } else {
1470                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1471                         return -EINVAL;
1472         }
1473
1474         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1475         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1476
1477         /* Update the default RSS VNIC(s) */
1478         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1479         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1480
1481         /*
1482          * If hashkey is not specified, use the previously configured
1483          * hashkey
1484          */
1485         if (!rss_conf->rss_key)
1486                 goto rss_config;
1487
1488         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1489                 PMD_DRV_LOG(ERR,
1490                             "Invalid hashkey length, should be 16 bytes\n");
1491                 return -EINVAL;
1492         }
1493         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1494
1495 rss_config:
1496         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1497         return 0;
1498 }
1499
1500 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1501                                      struct rte_eth_rss_conf *rss_conf)
1502 {
1503         struct bnxt *bp = eth_dev->data->dev_private;
1504         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1505         int len, rc;
1506         uint32_t hash_types;
1507
1508         rc = is_bnxt_in_error(bp);
1509         if (rc)
1510                 return rc;
1511
1512         /* RSS configuration is the same for all VNICs */
1513         if (vnic && vnic->rss_hash_key) {
1514                 if (rss_conf->rss_key) {
1515                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1516                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1517                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1518                 }
1519
1520                 hash_types = vnic->hash_type;
1521                 rss_conf->rss_hf = 0;
1522                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1523                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1524                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1525                 }
1526                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1527                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1528                         hash_types &=
1529                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1530                 }
1531                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1532                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1533                         hash_types &=
1534                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1535                 }
1536                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1537                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1538                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1539                 }
1540                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1541                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1542                         hash_types &=
1543                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1544                 }
1545                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1546                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1547                         hash_types &=
1548                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1549                 }
1550                 if (hash_types) {
1551                         PMD_DRV_LOG(ERR,
1552                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1553                                 vnic->hash_type);
1554                         return -ENOTSUP;
1555                 }
1556         } else {
1557                 rss_conf->rss_hf = 0;
1558         }
1559         return 0;
1560 }
1561
1562 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1563                                struct rte_eth_fc_conf *fc_conf)
1564 {
1565         struct bnxt *bp = dev->data->dev_private;
1566         struct rte_eth_link link_info;
1567         int rc;
1568
1569         rc = is_bnxt_in_error(bp);
1570         if (rc)
1571                 return rc;
1572
1573         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1574         if (rc)
1575                 return rc;
1576
1577         memset(fc_conf, 0, sizeof(*fc_conf));
1578         if (bp->link_info.auto_pause)
1579                 fc_conf->autoneg = 1;
1580         switch (bp->link_info.pause) {
1581         case 0:
1582                 fc_conf->mode = RTE_FC_NONE;
1583                 break;
1584         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1585                 fc_conf->mode = RTE_FC_TX_PAUSE;
1586                 break;
1587         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1588                 fc_conf->mode = RTE_FC_RX_PAUSE;
1589                 break;
1590         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1591                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1592                 fc_conf->mode = RTE_FC_FULL;
1593                 break;
1594         }
1595         return 0;
1596 }
1597
1598 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1599                                struct rte_eth_fc_conf *fc_conf)
1600 {
1601         struct bnxt *bp = dev->data->dev_private;
1602         int rc;
1603
1604         rc = is_bnxt_in_error(bp);
1605         if (rc)
1606                 return rc;
1607
1608         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1609                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1610                 return -ENOTSUP;
1611         }
1612
1613         switch (fc_conf->mode) {
1614         case RTE_FC_NONE:
1615                 bp->link_info.auto_pause = 0;
1616                 bp->link_info.force_pause = 0;
1617                 break;
1618         case RTE_FC_RX_PAUSE:
1619                 if (fc_conf->autoneg) {
1620                         bp->link_info.auto_pause =
1621                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1622                         bp->link_info.force_pause = 0;
1623                 } else {
1624                         bp->link_info.auto_pause = 0;
1625                         bp->link_info.force_pause =
1626                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1627                 }
1628                 break;
1629         case RTE_FC_TX_PAUSE:
1630                 if (fc_conf->autoneg) {
1631                         bp->link_info.auto_pause =
1632                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1633                         bp->link_info.force_pause = 0;
1634                 } else {
1635                         bp->link_info.auto_pause = 0;
1636                         bp->link_info.force_pause =
1637                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1638                 }
1639                 break;
1640         case RTE_FC_FULL:
1641                 if (fc_conf->autoneg) {
1642                         bp->link_info.auto_pause =
1643                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1644                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1645                         bp->link_info.force_pause = 0;
1646                 } else {
1647                         bp->link_info.auto_pause = 0;
1648                         bp->link_info.force_pause =
1649                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1650                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1651                 }
1652                 break;
1653         }
1654         return bnxt_set_hwrm_link_config(bp, true);
1655 }
1656
1657 /* Add UDP tunneling port */
1658 static int
1659 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1660                          struct rte_eth_udp_tunnel *udp_tunnel)
1661 {
1662         struct bnxt *bp = eth_dev->data->dev_private;
1663         uint16_t tunnel_type = 0;
1664         int rc = 0;
1665
1666         rc = is_bnxt_in_error(bp);
1667         if (rc)
1668                 return rc;
1669
1670         switch (udp_tunnel->prot_type) {
1671         case RTE_TUNNEL_TYPE_VXLAN:
1672                 if (bp->vxlan_port_cnt) {
1673                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1674                                 udp_tunnel->udp_port);
1675                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1676                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1677                                 return -ENOSPC;
1678                         }
1679                         bp->vxlan_port_cnt++;
1680                         return 0;
1681                 }
1682                 tunnel_type =
1683                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1684                 bp->vxlan_port_cnt++;
1685                 break;
1686         case RTE_TUNNEL_TYPE_GENEVE:
1687                 if (bp->geneve_port_cnt) {
1688                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1689                                 udp_tunnel->udp_port);
1690                         if (bp->geneve_port != udp_tunnel->udp_port) {
1691                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1692                                 return -ENOSPC;
1693                         }
1694                         bp->geneve_port_cnt++;
1695                         return 0;
1696                 }
1697                 tunnel_type =
1698                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1699                 bp->geneve_port_cnt++;
1700                 break;
1701         default:
1702                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1703                 return -ENOTSUP;
1704         }
1705         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1706                                              tunnel_type);
1707         return rc;
1708 }
1709
1710 static int
1711 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1712                          struct rte_eth_udp_tunnel *udp_tunnel)
1713 {
1714         struct bnxt *bp = eth_dev->data->dev_private;
1715         uint16_t tunnel_type = 0;
1716         uint16_t port = 0;
1717         int rc = 0;
1718
1719         rc = is_bnxt_in_error(bp);
1720         if (rc)
1721                 return rc;
1722
1723         switch (udp_tunnel->prot_type) {
1724         case RTE_TUNNEL_TYPE_VXLAN:
1725                 if (!bp->vxlan_port_cnt) {
1726                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1727                         return -EINVAL;
1728                 }
1729                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1730                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1731                                 udp_tunnel->udp_port, bp->vxlan_port);
1732                         return -EINVAL;
1733                 }
1734                 if (--bp->vxlan_port_cnt)
1735                         return 0;
1736
1737                 tunnel_type =
1738                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1739                 port = bp->vxlan_fw_dst_port_id;
1740                 break;
1741         case RTE_TUNNEL_TYPE_GENEVE:
1742                 if (!bp->geneve_port_cnt) {
1743                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1744                         return -EINVAL;
1745                 }
1746                 if (bp->geneve_port != udp_tunnel->udp_port) {
1747                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1748                                 udp_tunnel->udp_port, bp->geneve_port);
1749                         return -EINVAL;
1750                 }
1751                 if (--bp->geneve_port_cnt)
1752                         return 0;
1753
1754                 tunnel_type =
1755                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1756                 port = bp->geneve_fw_dst_port_id;
1757                 break;
1758         default:
1759                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1760                 return -ENOTSUP;
1761         }
1762
1763         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1764         if (!rc) {
1765                 if (tunnel_type ==
1766                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1767                         bp->vxlan_port = 0;
1768                 if (tunnel_type ==
1769                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1770                         bp->geneve_port = 0;
1771         }
1772         return rc;
1773 }
1774
1775 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1776 {
1777         struct bnxt_filter_info *filter;
1778         struct bnxt_vnic_info *vnic;
1779         int rc = 0;
1780         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1781
1782         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1783         filter = STAILQ_FIRST(&vnic->filter);
1784         while (filter) {
1785                 /* Search for this matching MAC+VLAN filter */
1786                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1787                         /* Delete the filter */
1788                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1789                         if (rc)
1790                                 return rc;
1791                         STAILQ_REMOVE(&vnic->filter, filter,
1792                                       bnxt_filter_info, next);
1793                         bnxt_free_filter(bp, filter);
1794                         PMD_DRV_LOG(INFO,
1795                                     "Deleted vlan filter for %d\n",
1796                                     vlan_id);
1797                         return 0;
1798                 }
1799                 filter = STAILQ_NEXT(filter, next);
1800         }
1801         return -ENOENT;
1802 }
1803
1804 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1805 {
1806         struct bnxt_filter_info *filter;
1807         struct bnxt_vnic_info *vnic;
1808         int rc = 0;
1809         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1810                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1811         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1812
1813         /* Implementation notes on the use of VNIC in this command:
1814          *
1815          * By default, these filters belong to default vnic for the function.
1816          * Once these filters are set up, only destination VNIC can be modified.
1817          * If the destination VNIC is not specified in this command,
1818          * then the HWRM shall only create an l2 context id.
1819          */
1820
1821         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1822         filter = STAILQ_FIRST(&vnic->filter);
1823         /* Check if the VLAN has already been added */
1824         while (filter) {
1825                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1826                         return -EEXIST;
1827
1828                 filter = STAILQ_NEXT(filter, next);
1829         }
1830
1831         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1832          * command to create MAC+VLAN filter with the right flags, enables set.
1833          */
1834         filter = bnxt_alloc_filter(bp);
1835         if (!filter) {
1836                 PMD_DRV_LOG(ERR,
1837                             "MAC/VLAN filter alloc failed\n");
1838                 return -ENOMEM;
1839         }
1840         /* MAC + VLAN ID filter */
1841         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1842          * untagged packets are received
1843          *
1844          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1845          * packets and only the programmed vlan's packets are received
1846          */
1847         filter->l2_ivlan = vlan_id;
1848         filter->l2_ivlan_mask = 0x0FFF;
1849         filter->enables |= en;
1850         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1851
1852         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1853         if (rc) {
1854                 /* Free the newly allocated filter as we were
1855                  * not able to create the filter in hardware.
1856                  */
1857                 bnxt_free_filter(bp, filter);
1858                 return rc;
1859         }
1860
1861         filter->mac_index = 0;
1862         /* Add this new filter to the list */
1863         if (vlan_id == 0)
1864                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1865         else
1866                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1867
1868         PMD_DRV_LOG(INFO,
1869                     "Added Vlan filter for %d\n", vlan_id);
1870         return rc;
1871 }
1872
1873 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1874                 uint16_t vlan_id, int on)
1875 {
1876         struct bnxt *bp = eth_dev->data->dev_private;
1877         int rc;
1878
1879         rc = is_bnxt_in_error(bp);
1880         if (rc)
1881                 return rc;
1882
1883         /* These operations apply to ALL existing MAC/VLAN filters */
1884         if (on)
1885                 return bnxt_add_vlan_filter(bp, vlan_id);
1886         else
1887                 return bnxt_del_vlan_filter(bp, vlan_id);
1888 }
1889
1890 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1891                                     struct bnxt_vnic_info *vnic)
1892 {
1893         struct bnxt_filter_info *filter;
1894         int rc;
1895
1896         filter = STAILQ_FIRST(&vnic->filter);
1897         while (filter) {
1898                 if (filter->mac_index == 0 &&
1899                     !memcmp(filter->l2_addr, bp->mac_addr,
1900                             RTE_ETHER_ADDR_LEN)) {
1901                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1902                         if (!rc) {
1903                                 STAILQ_REMOVE(&vnic->filter, filter,
1904                                               bnxt_filter_info, next);
1905                                 bnxt_free_filter(bp, filter);
1906                         }
1907                         return rc;
1908                 }
1909                 filter = STAILQ_NEXT(filter, next);
1910         }
1911         return 0;
1912 }
1913
1914 static int
1915 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
1916 {
1917         struct bnxt_vnic_info *vnic;
1918         unsigned int i;
1919         int rc;
1920
1921         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1922         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1923                 /* Remove any VLAN filters programmed */
1924                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1925                         bnxt_del_vlan_filter(bp, i);
1926
1927                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1928                 if (rc)
1929                         return rc;
1930         } else {
1931                 /* Default filter will allow packets that match the
1932                  * dest mac. So, it has to be deleted, otherwise, we
1933                  * will endup receiving vlan packets for which the
1934                  * filter is not programmed, when hw-vlan-filter
1935                  * configuration is ON
1936                  */
1937                 bnxt_del_dflt_mac_filter(bp, vnic);
1938                 /* This filter will allow only untagged packets */
1939                 bnxt_add_vlan_filter(bp, 0);
1940         }
1941         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1942                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1943
1944         return 0;
1945 }
1946
1947 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
1948 {
1949         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
1950         unsigned int i;
1951         int rc;
1952
1953         /* Destroy vnic filters and vnic */
1954         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1955             DEV_RX_OFFLOAD_VLAN_FILTER) {
1956                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1957                         bnxt_del_vlan_filter(bp, i);
1958         }
1959         bnxt_del_dflt_mac_filter(bp, vnic);
1960
1961         rc = bnxt_hwrm_vnic_free(bp, vnic);
1962         if (rc)
1963                 return rc;
1964
1965         rte_free(vnic->fw_grp_ids);
1966         vnic->fw_grp_ids = NULL;
1967
1968         return 0;
1969 }
1970
1971 static int
1972 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
1973 {
1974         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1975         int rc;
1976
1977         /* Destroy, recreate and reconfigure the default vnic */
1978         rc = bnxt_free_one_vnic(bp, 0);
1979         if (rc)
1980                 return rc;
1981
1982         /* default vnic 0 */
1983         rc = bnxt_setup_one_vnic(bp, 0);
1984         if (rc)
1985                 return rc;
1986
1987         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1988             DEV_RX_OFFLOAD_VLAN_FILTER) {
1989                 rc = bnxt_add_vlan_filter(bp, 0);
1990                 if (rc)
1991                         return rc;
1992                 rc = bnxt_restore_vlan_filters(bp);
1993                 if (rc)
1994                         return rc;
1995         } else {
1996                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1997                 if (rc)
1998                         return rc;
1999         }
2000
2001         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2002         if (rc)
2003                 return rc;
2004
2005         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2006                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2007
2008         return rc;
2009 }
2010
2011 static int
2012 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2013 {
2014         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2015         struct bnxt *bp = dev->data->dev_private;
2016         int rc;
2017
2018         rc = is_bnxt_in_error(bp);
2019         if (rc)
2020                 return rc;
2021
2022         /* Filter settings will get applied when port is started */
2023         if (!dev->data->dev_started)
2024                 return 0;
2025
2026         if (mask & ETH_VLAN_FILTER_MASK) {
2027                 /* Enable or disable VLAN filtering */
2028                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2029                 if (rc)
2030                         return rc;
2031         }
2032
2033         if (mask & ETH_VLAN_STRIP_MASK) {
2034                 /* Enable or disable VLAN stripping */
2035                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2036                 if (rc)
2037                         return rc;
2038         }
2039
2040         if (mask & ETH_VLAN_EXTEND_MASK) {
2041                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2042                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2043                 else
2044                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2045         }
2046
2047         return 0;
2048 }
2049
2050 static int
2051 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2052                       uint16_t tpid)
2053 {
2054         struct bnxt *bp = dev->data->dev_private;
2055         int qinq = dev->data->dev_conf.rxmode.offloads &
2056                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2057
2058         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2059             vlan_type != ETH_VLAN_TYPE_OUTER) {
2060                 PMD_DRV_LOG(ERR,
2061                             "Unsupported vlan type.");
2062                 return -EINVAL;
2063         }
2064         if (!qinq) {
2065                 PMD_DRV_LOG(ERR,
2066                             "QinQ not enabled. Needs to be ON as we can "
2067                             "accelerate only outer vlan\n");
2068                 return -EINVAL;
2069         }
2070
2071         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2072                 switch (tpid) {
2073                 case RTE_ETHER_TYPE_QINQ:
2074                         bp->outer_tpid_bd =
2075                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2076                                 break;
2077                 case RTE_ETHER_TYPE_VLAN:
2078                         bp->outer_tpid_bd =
2079                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2080                                 break;
2081                 case 0x9100:
2082                         bp->outer_tpid_bd =
2083                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2084                                 break;
2085                 case 0x9200:
2086                         bp->outer_tpid_bd =
2087                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2088                                 break;
2089                 case 0x9300:
2090                         bp->outer_tpid_bd =
2091                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2092                                 break;
2093                 default:
2094                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2095                         return -EINVAL;
2096                 }
2097                 bp->outer_tpid_bd |= tpid;
2098                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2099         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2100                 PMD_DRV_LOG(ERR,
2101                             "Can accelerate only outer vlan in QinQ\n");
2102                 return -EINVAL;
2103         }
2104
2105         return 0;
2106 }
2107
2108 static int
2109 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2110                              struct rte_ether_addr *addr)
2111 {
2112         struct bnxt *bp = dev->data->dev_private;
2113         /* Default Filter is tied to VNIC 0 */
2114         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2115         int rc;
2116
2117         rc = is_bnxt_in_error(bp);
2118         if (rc)
2119                 return rc;
2120
2121         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2122                 return -EPERM;
2123
2124         if (rte_is_zero_ether_addr(addr))
2125                 return -EINVAL;
2126
2127         /* Filter settings will get applied when port is started */
2128         if (!dev->data->dev_started)
2129                 return 0;
2130
2131         /* Check if the requested MAC is already added */
2132         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2133                 return 0;
2134
2135         /* Destroy filter and re-create it */
2136         bnxt_del_dflt_mac_filter(bp, vnic);
2137
2138         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2139         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2140                 /* This filter will allow only untagged packets */
2141                 rc = bnxt_add_vlan_filter(bp, 0);
2142         } else {
2143                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2144         }
2145
2146         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2147         return rc;
2148 }
2149
2150 static int
2151 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2152                           struct rte_ether_addr *mc_addr_set,
2153                           uint32_t nb_mc_addr)
2154 {
2155         struct bnxt *bp = eth_dev->data->dev_private;
2156         char *mc_addr_list = (char *)mc_addr_set;
2157         struct bnxt_vnic_info *vnic;
2158         uint32_t off = 0, i = 0;
2159         int rc;
2160
2161         rc = is_bnxt_in_error(bp);
2162         if (rc)
2163                 return rc;
2164
2165         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2166
2167         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2168                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2169                 goto allmulti;
2170         }
2171
2172         /* TODO Check for Duplicate mcast addresses */
2173         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2174         for (i = 0; i < nb_mc_addr; i++) {
2175                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2176                         RTE_ETHER_ADDR_LEN);
2177                 off += RTE_ETHER_ADDR_LEN;
2178         }
2179
2180         vnic->mc_addr_cnt = i;
2181         if (vnic->mc_addr_cnt)
2182                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2183         else
2184                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2185
2186 allmulti:
2187         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2188 }
2189
2190 static int
2191 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2192 {
2193         struct bnxt *bp = dev->data->dev_private;
2194         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2195         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2196         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2197         int ret;
2198
2199         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2200                         fw_major, fw_minor, fw_updt);
2201
2202         ret += 1; /* add the size of '\0' */
2203         if (fw_size < (uint32_t)ret)
2204                 return ret;
2205         else
2206                 return 0;
2207 }
2208
2209 static void
2210 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2211         struct rte_eth_rxq_info *qinfo)
2212 {
2213         struct bnxt *bp = dev->data->dev_private;
2214         struct bnxt_rx_queue *rxq;
2215
2216         if (is_bnxt_in_error(bp))
2217                 return;
2218
2219         rxq = dev->data->rx_queues[queue_id];
2220
2221         qinfo->mp = rxq->mb_pool;
2222         qinfo->scattered_rx = dev->data->scattered_rx;
2223         qinfo->nb_desc = rxq->nb_rx_desc;
2224
2225         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2226         qinfo->conf.rx_drop_en = 0;
2227         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2228 }
2229
2230 static void
2231 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2232         struct rte_eth_txq_info *qinfo)
2233 {
2234         struct bnxt *bp = dev->data->dev_private;
2235         struct bnxt_tx_queue *txq;
2236
2237         if (is_bnxt_in_error(bp))
2238                 return;
2239
2240         txq = dev->data->tx_queues[queue_id];
2241
2242         qinfo->nb_desc = txq->nb_tx_desc;
2243
2244         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2245         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2246         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2247
2248         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2249         qinfo->conf.tx_rs_thresh = 0;
2250         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2251 }
2252
2253 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2254 {
2255         struct bnxt *bp = eth_dev->data->dev_private;
2256         uint32_t new_pkt_size;
2257         uint32_t rc = 0;
2258         uint32_t i;
2259
2260         rc = is_bnxt_in_error(bp);
2261         if (rc)
2262                 return rc;
2263
2264         /* Exit if receive queues are not configured yet */
2265         if (!eth_dev->data->nb_rx_queues)
2266                 return rc;
2267
2268         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2269                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2270
2271 #ifdef RTE_ARCH_X86
2272         /*
2273          * If vector-mode tx/rx is active, disallow any MTU change that would
2274          * require scattered receive support.
2275          */
2276         if (eth_dev->data->dev_started &&
2277             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2278              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2279             (new_pkt_size >
2280              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2281                 PMD_DRV_LOG(ERR,
2282                             "MTU change would require scattered rx support. ");
2283                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2284                 return -EINVAL;
2285         }
2286 #endif
2287
2288         if (new_mtu > RTE_ETHER_MTU) {
2289                 bp->flags |= BNXT_FLAG_JUMBO;
2290                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2291                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2292         } else {
2293                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2294                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2295                 bp->flags &= ~BNXT_FLAG_JUMBO;
2296         }
2297
2298         /* Is there a change in mtu setting? */
2299         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2300                 return rc;
2301
2302         for (i = 0; i < bp->nr_vnics; i++) {
2303                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2304                 uint16_t size = 0;
2305
2306                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2307                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2308                 if (rc)
2309                         break;
2310
2311                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2312                 size -= RTE_PKTMBUF_HEADROOM;
2313
2314                 if (size < new_mtu) {
2315                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2316                         if (rc)
2317                                 return rc;
2318                 }
2319         }
2320
2321         if (!rc)
2322                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2323
2324         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2325
2326         return rc;
2327 }
2328
2329 static int
2330 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2331 {
2332         struct bnxt *bp = dev->data->dev_private;
2333         uint16_t vlan = bp->vlan;
2334         int rc;
2335
2336         rc = is_bnxt_in_error(bp);
2337         if (rc)
2338                 return rc;
2339
2340         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2341                 PMD_DRV_LOG(ERR,
2342                         "PVID cannot be modified for this function\n");
2343                 return -ENOTSUP;
2344         }
2345         bp->vlan = on ? pvid : 0;
2346
2347         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2348         if (rc)
2349                 bp->vlan = vlan;
2350         return rc;
2351 }
2352
2353 static int
2354 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2355 {
2356         struct bnxt *bp = dev->data->dev_private;
2357         int rc;
2358
2359         rc = is_bnxt_in_error(bp);
2360         if (rc)
2361                 return rc;
2362
2363         return bnxt_hwrm_port_led_cfg(bp, true);
2364 }
2365
2366 static int
2367 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2368 {
2369         struct bnxt *bp = dev->data->dev_private;
2370         int rc;
2371
2372         rc = is_bnxt_in_error(bp);
2373         if (rc)
2374                 return rc;
2375
2376         return bnxt_hwrm_port_led_cfg(bp, false);
2377 }
2378
2379 static uint32_t
2380 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2381 {
2382         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2383         uint32_t desc = 0, raw_cons = 0, cons;
2384         struct bnxt_cp_ring_info *cpr;
2385         struct bnxt_rx_queue *rxq;
2386         struct rx_pkt_cmpl *rxcmp;
2387         int rc;
2388
2389         rc = is_bnxt_in_error(bp);
2390         if (rc)
2391                 return rc;
2392
2393         rxq = dev->data->rx_queues[rx_queue_id];
2394         cpr = rxq->cp_ring;
2395         raw_cons = cpr->cp_raw_cons;
2396
2397         while (1) {
2398                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2399                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2400                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2401
2402                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2403                         break;
2404                 } else {
2405                         raw_cons++;
2406                         desc++;
2407                 }
2408         }
2409
2410         return desc;
2411 }
2412
2413 static int
2414 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2415 {
2416         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2417         struct bnxt_rx_ring_info *rxr;
2418         struct bnxt_cp_ring_info *cpr;
2419         struct bnxt_sw_rx_bd *rx_buf;
2420         struct rx_pkt_cmpl *rxcmp;
2421         uint32_t cons, cp_cons;
2422         int rc;
2423
2424         if (!rxq)
2425                 return -EINVAL;
2426
2427         rc = is_bnxt_in_error(rxq->bp);
2428         if (rc)
2429                 return rc;
2430
2431         cpr = rxq->cp_ring;
2432         rxr = rxq->rx_ring;
2433
2434         if (offset >= rxq->nb_rx_desc)
2435                 return -EINVAL;
2436
2437         cons = RING_CMP(cpr->cp_ring_struct, offset);
2438         cp_cons = cpr->cp_raw_cons;
2439         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2440
2441         if (cons > cp_cons) {
2442                 if (CMPL_VALID(rxcmp, cpr->valid))
2443                         return RTE_ETH_RX_DESC_DONE;
2444         } else {
2445                 if (CMPL_VALID(rxcmp, !cpr->valid))
2446                         return RTE_ETH_RX_DESC_DONE;
2447         }
2448         rx_buf = &rxr->rx_buf_ring[cons];
2449         if (rx_buf->mbuf == NULL)
2450                 return RTE_ETH_RX_DESC_UNAVAIL;
2451
2452
2453         return RTE_ETH_RX_DESC_AVAIL;
2454 }
2455
2456 static int
2457 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2458 {
2459         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2460         struct bnxt_tx_ring_info *txr;
2461         struct bnxt_cp_ring_info *cpr;
2462         struct bnxt_sw_tx_bd *tx_buf;
2463         struct tx_pkt_cmpl *txcmp;
2464         uint32_t cons, cp_cons;
2465         int rc;
2466
2467         if (!txq)
2468                 return -EINVAL;
2469
2470         rc = is_bnxt_in_error(txq->bp);
2471         if (rc)
2472                 return rc;
2473
2474         cpr = txq->cp_ring;
2475         txr = txq->tx_ring;
2476
2477         if (offset >= txq->nb_tx_desc)
2478                 return -EINVAL;
2479
2480         cons = RING_CMP(cpr->cp_ring_struct, offset);
2481         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2482         cp_cons = cpr->cp_raw_cons;
2483
2484         if (cons > cp_cons) {
2485                 if (CMPL_VALID(txcmp, cpr->valid))
2486                         return RTE_ETH_TX_DESC_UNAVAIL;
2487         } else {
2488                 if (CMPL_VALID(txcmp, !cpr->valid))
2489                         return RTE_ETH_TX_DESC_UNAVAIL;
2490         }
2491         tx_buf = &txr->tx_buf_ring[cons];
2492         if (tx_buf->mbuf == NULL)
2493                 return RTE_ETH_TX_DESC_DONE;
2494
2495         return RTE_ETH_TX_DESC_FULL;
2496 }
2497
2498 static struct bnxt_filter_info *
2499 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2500                                 struct rte_eth_ethertype_filter *efilter,
2501                                 struct bnxt_vnic_info *vnic0,
2502                                 struct bnxt_vnic_info *vnic,
2503                                 int *ret)
2504 {
2505         struct bnxt_filter_info *mfilter = NULL;
2506         int match = 0;
2507         *ret = 0;
2508
2509         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2510                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2511                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2512                         " ethertype filter.", efilter->ether_type);
2513                 *ret = -EINVAL;
2514                 goto exit;
2515         }
2516         if (efilter->queue >= bp->rx_nr_rings) {
2517                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2518                 *ret = -EINVAL;
2519                 goto exit;
2520         }
2521
2522         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2523         vnic = &bp->vnic_info[efilter->queue];
2524         if (vnic == NULL) {
2525                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2526                 *ret = -EINVAL;
2527                 goto exit;
2528         }
2529
2530         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2531                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2532                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2533                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2534                              mfilter->flags ==
2535                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2536                              mfilter->ethertype == efilter->ether_type)) {
2537                                 match = 1;
2538                                 break;
2539                         }
2540                 }
2541         } else {
2542                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2543                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2544                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2545                              mfilter->ethertype == efilter->ether_type &&
2546                              mfilter->flags ==
2547                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2548                                 match = 1;
2549                                 break;
2550                         }
2551         }
2552
2553         if (match)
2554                 *ret = -EEXIST;
2555
2556 exit:
2557         return mfilter;
2558 }
2559
2560 static int
2561 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2562                         enum rte_filter_op filter_op,
2563                         void *arg)
2564 {
2565         struct bnxt *bp = dev->data->dev_private;
2566         struct rte_eth_ethertype_filter *efilter =
2567                         (struct rte_eth_ethertype_filter *)arg;
2568         struct bnxt_filter_info *bfilter, *filter1;
2569         struct bnxt_vnic_info *vnic, *vnic0;
2570         int ret;
2571
2572         if (filter_op == RTE_ETH_FILTER_NOP)
2573                 return 0;
2574
2575         if (arg == NULL) {
2576                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2577                             filter_op);
2578                 return -EINVAL;
2579         }
2580
2581         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2582         vnic = &bp->vnic_info[efilter->queue];
2583
2584         switch (filter_op) {
2585         case RTE_ETH_FILTER_ADD:
2586                 bnxt_match_and_validate_ether_filter(bp, efilter,
2587                                                         vnic0, vnic, &ret);
2588                 if (ret < 0)
2589                         return ret;
2590
2591                 bfilter = bnxt_get_unused_filter(bp);
2592                 if (bfilter == NULL) {
2593                         PMD_DRV_LOG(ERR,
2594                                 "Not enough resources for a new filter.\n");
2595                         return -ENOMEM;
2596                 }
2597                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2598                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2599                        RTE_ETHER_ADDR_LEN);
2600                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2601                        RTE_ETHER_ADDR_LEN);
2602                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2603                 bfilter->ethertype = efilter->ether_type;
2604                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2605
2606                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2607                 if (filter1 == NULL) {
2608                         ret = -EINVAL;
2609                         goto cleanup;
2610                 }
2611                 bfilter->enables |=
2612                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2613                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2614
2615                 bfilter->dst_id = vnic->fw_vnic_id;
2616
2617                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2618                         bfilter->flags =
2619                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2620                 }
2621
2622                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2623                 if (ret)
2624                         goto cleanup;
2625                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2626                 break;
2627         case RTE_ETH_FILTER_DELETE:
2628                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2629                                                         vnic0, vnic, &ret);
2630                 if (ret == -EEXIST) {
2631                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2632
2633                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2634                                       next);
2635                         bnxt_free_filter(bp, filter1);
2636                 } else if (ret == 0) {
2637                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2638                 }
2639                 break;
2640         default:
2641                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2642                 ret = -EINVAL;
2643                 goto error;
2644         }
2645         return ret;
2646 cleanup:
2647         bnxt_free_filter(bp, bfilter);
2648 error:
2649         return ret;
2650 }
2651
2652 static inline int
2653 parse_ntuple_filter(struct bnxt *bp,
2654                     struct rte_eth_ntuple_filter *nfilter,
2655                     struct bnxt_filter_info *bfilter)
2656 {
2657         uint32_t en = 0;
2658
2659         if (nfilter->queue >= bp->rx_nr_rings) {
2660                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2661                 return -EINVAL;
2662         }
2663
2664         switch (nfilter->dst_port_mask) {
2665         case UINT16_MAX:
2666                 bfilter->dst_port_mask = -1;
2667                 bfilter->dst_port = nfilter->dst_port;
2668                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2669                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2670                 break;
2671         default:
2672                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2673                 return -EINVAL;
2674         }
2675
2676         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2677         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2678
2679         switch (nfilter->proto_mask) {
2680         case UINT8_MAX:
2681                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2682                         bfilter->ip_protocol = 17;
2683                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2684                         bfilter->ip_protocol = 6;
2685                 else
2686                         return -EINVAL;
2687                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2688                 break;
2689         default:
2690                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2691                 return -EINVAL;
2692         }
2693
2694         switch (nfilter->dst_ip_mask) {
2695         case UINT32_MAX:
2696                 bfilter->dst_ipaddr_mask[0] = -1;
2697                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2698                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2699                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2700                 break;
2701         default:
2702                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2703                 return -EINVAL;
2704         }
2705
2706         switch (nfilter->src_ip_mask) {
2707         case UINT32_MAX:
2708                 bfilter->src_ipaddr_mask[0] = -1;
2709                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2710                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2711                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2712                 break;
2713         default:
2714                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2715                 return -EINVAL;
2716         }
2717
2718         switch (nfilter->src_port_mask) {
2719         case UINT16_MAX:
2720                 bfilter->src_port_mask = -1;
2721                 bfilter->src_port = nfilter->src_port;
2722                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2723                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2724                 break;
2725         default:
2726                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2727                 return -EINVAL;
2728         }
2729
2730         bfilter->enables = en;
2731         return 0;
2732 }
2733
2734 static struct bnxt_filter_info*
2735 bnxt_match_ntuple_filter(struct bnxt *bp,
2736                          struct bnxt_filter_info *bfilter,
2737                          struct bnxt_vnic_info **mvnic)
2738 {
2739         struct bnxt_filter_info *mfilter = NULL;
2740         int i;
2741
2742         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2743                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2744                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2745                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2746                             bfilter->src_ipaddr_mask[0] ==
2747                             mfilter->src_ipaddr_mask[0] &&
2748                             bfilter->src_port == mfilter->src_port &&
2749                             bfilter->src_port_mask == mfilter->src_port_mask &&
2750                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2751                             bfilter->dst_ipaddr_mask[0] ==
2752                             mfilter->dst_ipaddr_mask[0] &&
2753                             bfilter->dst_port == mfilter->dst_port &&
2754                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2755                             bfilter->flags == mfilter->flags &&
2756                             bfilter->enables == mfilter->enables) {
2757                                 if (mvnic)
2758                                         *mvnic = vnic;
2759                                 return mfilter;
2760                         }
2761                 }
2762         }
2763         return NULL;
2764 }
2765
2766 static int
2767 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2768                        struct rte_eth_ntuple_filter *nfilter,
2769                        enum rte_filter_op filter_op)
2770 {
2771         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2772         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2773         int ret;
2774
2775         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2776                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2777                 return -EINVAL;
2778         }
2779
2780         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2781                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2782                 return -EINVAL;
2783         }
2784
2785         bfilter = bnxt_get_unused_filter(bp);
2786         if (bfilter == NULL) {
2787                 PMD_DRV_LOG(ERR,
2788                         "Not enough resources for a new filter.\n");
2789                 return -ENOMEM;
2790         }
2791         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2792         if (ret < 0)
2793                 goto free_filter;
2794
2795         vnic = &bp->vnic_info[nfilter->queue];
2796         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2797         filter1 = STAILQ_FIRST(&vnic0->filter);
2798         if (filter1 == NULL) {
2799                 ret = -EINVAL;
2800                 goto free_filter;
2801         }
2802
2803         bfilter->dst_id = vnic->fw_vnic_id;
2804         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2805         bfilter->enables |=
2806                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2807         bfilter->ethertype = 0x800;
2808         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2809
2810         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2811
2812         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2813             bfilter->dst_id == mfilter->dst_id) {
2814                 PMD_DRV_LOG(ERR, "filter exists.\n");
2815                 ret = -EEXIST;
2816                 goto free_filter;
2817         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2818                    bfilter->dst_id != mfilter->dst_id) {
2819                 mfilter->dst_id = vnic->fw_vnic_id;
2820                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2821                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2822                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2823                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2824                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2825                 goto free_filter;
2826         }
2827         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2828                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2829                 ret = -ENOENT;
2830                 goto free_filter;
2831         }
2832
2833         if (filter_op == RTE_ETH_FILTER_ADD) {
2834                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2835                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2836                 if (ret)
2837                         goto free_filter;
2838                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2839         } else {
2840                 if (mfilter == NULL) {
2841                         /* This should not happen. But for Coverity! */
2842                         ret = -ENOENT;
2843                         goto free_filter;
2844                 }
2845                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2846
2847                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2848                 bnxt_free_filter(bp, mfilter);
2849                 bnxt_free_filter(bp, bfilter);
2850         }
2851
2852         return 0;
2853 free_filter:
2854         bnxt_free_filter(bp, bfilter);
2855         return ret;
2856 }
2857
2858 static int
2859 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2860                         enum rte_filter_op filter_op,
2861                         void *arg)
2862 {
2863         struct bnxt *bp = dev->data->dev_private;
2864         int ret;
2865
2866         if (filter_op == RTE_ETH_FILTER_NOP)
2867                 return 0;
2868
2869         if (arg == NULL) {
2870                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2871                             filter_op);
2872                 return -EINVAL;
2873         }
2874
2875         switch (filter_op) {
2876         case RTE_ETH_FILTER_ADD:
2877                 ret = bnxt_cfg_ntuple_filter(bp,
2878                         (struct rte_eth_ntuple_filter *)arg,
2879                         filter_op);
2880                 break;
2881         case RTE_ETH_FILTER_DELETE:
2882                 ret = bnxt_cfg_ntuple_filter(bp,
2883                         (struct rte_eth_ntuple_filter *)arg,
2884                         filter_op);
2885                 break;
2886         default:
2887                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2888                 ret = -EINVAL;
2889                 break;
2890         }
2891         return ret;
2892 }
2893
2894 static int
2895 bnxt_parse_fdir_filter(struct bnxt *bp,
2896                        struct rte_eth_fdir_filter *fdir,
2897                        struct bnxt_filter_info *filter)
2898 {
2899         enum rte_fdir_mode fdir_mode =
2900                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2901         struct bnxt_vnic_info *vnic0, *vnic;
2902         struct bnxt_filter_info *filter1;
2903         uint32_t en = 0;
2904         int i;
2905
2906         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2907                 return -EINVAL;
2908
2909         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2910         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2911
2912         switch (fdir->input.flow_type) {
2913         case RTE_ETH_FLOW_IPV4:
2914         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2915                 /* FALLTHROUGH */
2916                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2917                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2918                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2919                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2920                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2921                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2922                 filter->ip_addr_type =
2923                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2924                 filter->src_ipaddr_mask[0] = 0xffffffff;
2925                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2926                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2927                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2928                 filter->ethertype = 0x800;
2929                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2930                 break;
2931         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2932                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2933                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2934                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2935                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2936                 filter->dst_port_mask = 0xffff;
2937                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2938                 filter->src_port_mask = 0xffff;
2939                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2940                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2941                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2942                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2943                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2944                 filter->ip_protocol = 6;
2945                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2946                 filter->ip_addr_type =
2947                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2948                 filter->src_ipaddr_mask[0] = 0xffffffff;
2949                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2950                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2951                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2952                 filter->ethertype = 0x800;
2953                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2954                 break;
2955         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2956                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2957                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2958                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2959                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2960                 filter->dst_port_mask = 0xffff;
2961                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2962                 filter->src_port_mask = 0xffff;
2963                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2964                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2965                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2966                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2967                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2968                 filter->ip_protocol = 17;
2969                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2970                 filter->ip_addr_type =
2971                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2972                 filter->src_ipaddr_mask[0] = 0xffffffff;
2973                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2974                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2975                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2976                 filter->ethertype = 0x800;
2977                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2978                 break;
2979         case RTE_ETH_FLOW_IPV6:
2980         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2981                 /* FALLTHROUGH */
2982                 filter->ip_addr_type =
2983                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2984                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2985                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2986                 rte_memcpy(filter->src_ipaddr,
2987                            fdir->input.flow.ipv6_flow.src_ip, 16);
2988                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2989                 rte_memcpy(filter->dst_ipaddr,
2990                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2991                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2992                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2993                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2994                 memset(filter->src_ipaddr_mask, 0xff, 16);
2995                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2996                 filter->ethertype = 0x86dd;
2997                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2998                 break;
2999         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3000                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3001                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3002                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3003                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3004                 filter->dst_port_mask = 0xffff;
3005                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3006                 filter->src_port_mask = 0xffff;
3007                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3008                 filter->ip_addr_type =
3009                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3010                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3011                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3012                 rte_memcpy(filter->src_ipaddr,
3013                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3014                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3015                 rte_memcpy(filter->dst_ipaddr,
3016                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3017                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3018                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3019                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3020                 memset(filter->src_ipaddr_mask, 0xff, 16);
3021                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3022                 filter->ethertype = 0x86dd;
3023                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3024                 break;
3025         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3026                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3027                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3028                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3029                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3030                 filter->dst_port_mask = 0xffff;
3031                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3032                 filter->src_port_mask = 0xffff;
3033                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3034                 filter->ip_addr_type =
3035                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3036                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3037                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3038                 rte_memcpy(filter->src_ipaddr,
3039                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3040                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3041                 rte_memcpy(filter->dst_ipaddr,
3042                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3043                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3044                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3045                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3046                 memset(filter->src_ipaddr_mask, 0xff, 16);
3047                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3048                 filter->ethertype = 0x86dd;
3049                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3050                 break;
3051         case RTE_ETH_FLOW_L2_PAYLOAD:
3052                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3053                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3054                 break;
3055         case RTE_ETH_FLOW_VXLAN:
3056                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3057                         return -EINVAL;
3058                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3059                 filter->tunnel_type =
3060                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3061                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3062                 break;
3063         case RTE_ETH_FLOW_NVGRE:
3064                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3065                         return -EINVAL;
3066                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3067                 filter->tunnel_type =
3068                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3069                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3070                 break;
3071         case RTE_ETH_FLOW_UNKNOWN:
3072         case RTE_ETH_FLOW_RAW:
3073         case RTE_ETH_FLOW_FRAG_IPV4:
3074         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3075         case RTE_ETH_FLOW_FRAG_IPV6:
3076         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3077         case RTE_ETH_FLOW_IPV6_EX:
3078         case RTE_ETH_FLOW_IPV6_TCP_EX:
3079         case RTE_ETH_FLOW_IPV6_UDP_EX:
3080         case RTE_ETH_FLOW_GENEVE:
3081                 /* FALLTHROUGH */
3082         default:
3083                 return -EINVAL;
3084         }
3085
3086         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3087         vnic = &bp->vnic_info[fdir->action.rx_queue];
3088         if (vnic == NULL) {
3089                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3090                 return -EINVAL;
3091         }
3092
3093         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3094                 rte_memcpy(filter->dst_macaddr,
3095                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3096                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3097         }
3098
3099         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3100                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3101                 filter1 = STAILQ_FIRST(&vnic0->filter);
3102                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3103         } else {
3104                 filter->dst_id = vnic->fw_vnic_id;
3105                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3106                         if (filter->dst_macaddr[i] == 0x00)
3107                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3108                         else
3109                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3110         }
3111
3112         if (filter1 == NULL)
3113                 return -EINVAL;
3114
3115         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3116         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3117
3118         filter->enables = en;
3119
3120         return 0;
3121 }
3122
3123 static struct bnxt_filter_info *
3124 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3125                 struct bnxt_vnic_info **mvnic)
3126 {
3127         struct bnxt_filter_info *mf = NULL;
3128         int i;
3129
3130         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3131                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3132
3133                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3134                         if (mf->filter_type == nf->filter_type &&
3135                             mf->flags == nf->flags &&
3136                             mf->src_port == nf->src_port &&
3137                             mf->src_port_mask == nf->src_port_mask &&
3138                             mf->dst_port == nf->dst_port &&
3139                             mf->dst_port_mask == nf->dst_port_mask &&
3140                             mf->ip_protocol == nf->ip_protocol &&
3141                             mf->ip_addr_type == nf->ip_addr_type &&
3142                             mf->ethertype == nf->ethertype &&
3143                             mf->vni == nf->vni &&
3144                             mf->tunnel_type == nf->tunnel_type &&
3145                             mf->l2_ovlan == nf->l2_ovlan &&
3146                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3147                             mf->l2_ivlan == nf->l2_ivlan &&
3148                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3149                             !memcmp(mf->l2_addr, nf->l2_addr,
3150                                     RTE_ETHER_ADDR_LEN) &&
3151                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3152                                     RTE_ETHER_ADDR_LEN) &&
3153                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3154                                     RTE_ETHER_ADDR_LEN) &&
3155                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3156                                     RTE_ETHER_ADDR_LEN) &&
3157                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3158                                     sizeof(nf->src_ipaddr)) &&
3159                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3160                                     sizeof(nf->src_ipaddr_mask)) &&
3161                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3162                                     sizeof(nf->dst_ipaddr)) &&
3163                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3164                                     sizeof(nf->dst_ipaddr_mask))) {
3165                                 if (mvnic)
3166                                         *mvnic = vnic;
3167                                 return mf;
3168                         }
3169                 }
3170         }
3171         return NULL;
3172 }
3173
3174 static int
3175 bnxt_fdir_filter(struct rte_eth_dev *dev,
3176                  enum rte_filter_op filter_op,
3177                  void *arg)
3178 {
3179         struct bnxt *bp = dev->data->dev_private;
3180         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3181         struct bnxt_filter_info *filter, *match;
3182         struct bnxt_vnic_info *vnic, *mvnic;
3183         int ret = 0, i;
3184
3185         if (filter_op == RTE_ETH_FILTER_NOP)
3186                 return 0;
3187
3188         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3189                 return -EINVAL;
3190
3191         switch (filter_op) {
3192         case RTE_ETH_FILTER_ADD:
3193         case RTE_ETH_FILTER_DELETE:
3194                 /* FALLTHROUGH */
3195                 filter = bnxt_get_unused_filter(bp);
3196                 if (filter == NULL) {
3197                         PMD_DRV_LOG(ERR,
3198                                 "Not enough resources for a new flow.\n");
3199                         return -ENOMEM;
3200                 }
3201
3202                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3203                 if (ret != 0)
3204                         goto free_filter;
3205                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3206
3207                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3208                         vnic = &bp->vnic_info[0];
3209                 else
3210                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3211
3212                 match = bnxt_match_fdir(bp, filter, &mvnic);
3213                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3214                         if (match->dst_id == vnic->fw_vnic_id) {
3215                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3216                                 ret = -EEXIST;
3217                                 goto free_filter;
3218                         } else {
3219                                 match->dst_id = vnic->fw_vnic_id;
3220                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3221                                                                   match->dst_id,
3222                                                                   match);
3223                                 STAILQ_REMOVE(&mvnic->filter, match,
3224                                               bnxt_filter_info, next);
3225                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3226                                 PMD_DRV_LOG(ERR,
3227                                         "Filter with matching pattern exist\n");
3228                                 PMD_DRV_LOG(ERR,
3229                                         "Updated it to new destination q\n");
3230                                 goto free_filter;
3231                         }
3232                 }
3233                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3234                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3235                         ret = -ENOENT;
3236                         goto free_filter;
3237                 }
3238
3239                 if (filter_op == RTE_ETH_FILTER_ADD) {
3240                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3241                                                           filter->dst_id,
3242                                                           filter);
3243                         if (ret)
3244                                 goto free_filter;
3245                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3246                 } else {
3247                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3248                         STAILQ_REMOVE(&vnic->filter, match,
3249                                       bnxt_filter_info, next);
3250                         bnxt_free_filter(bp, match);
3251                         bnxt_free_filter(bp, filter);
3252                 }
3253                 break;
3254         case RTE_ETH_FILTER_FLUSH:
3255                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3256                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3257
3258                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3259                                 if (filter->filter_type ==
3260                                     HWRM_CFA_NTUPLE_FILTER) {
3261                                         ret =
3262                                         bnxt_hwrm_clear_ntuple_filter(bp,
3263                                                                       filter);
3264                                         STAILQ_REMOVE(&vnic->filter, filter,
3265                                                       bnxt_filter_info, next);
3266                                 }
3267                         }
3268                 }
3269                 return ret;
3270         case RTE_ETH_FILTER_UPDATE:
3271         case RTE_ETH_FILTER_STATS:
3272         case RTE_ETH_FILTER_INFO:
3273                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3274                 break;
3275         default:
3276                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3277                 ret = -EINVAL;
3278                 break;
3279         }
3280         return ret;
3281
3282 free_filter:
3283         bnxt_free_filter(bp, filter);
3284         return ret;
3285 }
3286
3287 static int
3288 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3289                     enum rte_filter_type filter_type,
3290                     enum rte_filter_op filter_op, void *arg)
3291 {
3292         struct bnxt *bp = dev->data->dev_private;
3293         int ret = 0;
3294
3295         ret = is_bnxt_in_error(dev->data->dev_private);
3296         if (ret)
3297                 return ret;
3298
3299         switch (filter_type) {
3300         case RTE_ETH_FILTER_TUNNEL:
3301                 PMD_DRV_LOG(ERR,
3302                         "filter type: %d: To be implemented\n", filter_type);
3303                 break;
3304         case RTE_ETH_FILTER_FDIR:
3305                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3306                 break;
3307         case RTE_ETH_FILTER_NTUPLE:
3308                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3309                 break;
3310         case RTE_ETH_FILTER_ETHERTYPE:
3311                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3312                 break;
3313         case RTE_ETH_FILTER_GENERIC:
3314                 if (filter_op != RTE_ETH_FILTER_GET)
3315                         return -EINVAL;
3316                 if (bp->truflow)
3317                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3318                 else
3319                         *(const void **)arg = &bnxt_flow_ops;
3320                 break;
3321         default:
3322                 PMD_DRV_LOG(ERR,
3323                         "Filter type (%d) not supported", filter_type);
3324                 ret = -EINVAL;
3325                 break;
3326         }
3327         return ret;
3328 }
3329
3330 static const uint32_t *
3331 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3332 {
3333         static const uint32_t ptypes[] = {
3334                 RTE_PTYPE_L2_ETHER_VLAN,
3335                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3336                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3337                 RTE_PTYPE_L4_ICMP,
3338                 RTE_PTYPE_L4_TCP,
3339                 RTE_PTYPE_L4_UDP,
3340                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3341                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3342                 RTE_PTYPE_INNER_L4_ICMP,
3343                 RTE_PTYPE_INNER_L4_TCP,
3344                 RTE_PTYPE_INNER_L4_UDP,
3345                 RTE_PTYPE_UNKNOWN
3346         };
3347
3348         if (!dev->rx_pkt_burst)
3349                 return NULL;
3350
3351         return ptypes;
3352 }
3353
3354 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3355                          int reg_win)
3356 {
3357         uint32_t reg_base = *reg_arr & 0xfffff000;
3358         uint32_t win_off;
3359         int i;
3360
3361         for (i = 0; i < count; i++) {
3362                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3363                         return -ERANGE;
3364         }
3365         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3366         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3367         return 0;
3368 }
3369
3370 static int bnxt_map_ptp_regs(struct bnxt *bp)
3371 {
3372         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3373         uint32_t *reg_arr;
3374         int rc, i;
3375
3376         reg_arr = ptp->rx_regs;
3377         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3378         if (rc)
3379                 return rc;
3380
3381         reg_arr = ptp->tx_regs;
3382         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3383         if (rc)
3384                 return rc;
3385
3386         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3387                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3388
3389         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3390                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3391
3392         return 0;
3393 }
3394
3395 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3396 {
3397         rte_write32(0, (uint8_t *)bp->bar0 +
3398                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3399         rte_write32(0, (uint8_t *)bp->bar0 +
3400                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3401 }
3402
3403 static uint64_t bnxt_cc_read(struct bnxt *bp)
3404 {
3405         uint64_t ns;
3406
3407         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3408                               BNXT_GRCPF_REG_SYNC_TIME));
3409         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3410                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3411         return ns;
3412 }
3413
3414 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3415 {
3416         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3417         uint32_t fifo;
3418
3419         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3420                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3421         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3422                 return -EAGAIN;
3423
3424         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3425                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3426         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3427                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3428         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3429                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3430
3431         return 0;
3432 }
3433
3434 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3435 {
3436         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3437         struct bnxt_pf_info *pf = &bp->pf;
3438         uint16_t port_id;
3439         uint32_t fifo;
3440
3441         if (!ptp)
3442                 return -ENODEV;
3443
3444         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3445                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3446         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3447                 return -EAGAIN;
3448
3449         port_id = pf->port_id;
3450         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3451                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3452
3453         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3454                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3455         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3456 /*              bnxt_clr_rx_ts(bp);       TBD  */
3457                 return -EBUSY;
3458         }
3459
3460         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3461                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3462         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3463                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3464
3465         return 0;
3466 }
3467
3468 static int
3469 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3470 {
3471         uint64_t ns;
3472         struct bnxt *bp = dev->data->dev_private;
3473         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3474
3475         if (!ptp)
3476                 return 0;
3477
3478         ns = rte_timespec_to_ns(ts);
3479         /* Set the timecounters to a new value. */
3480         ptp->tc.nsec = ns;
3481
3482         return 0;
3483 }
3484
3485 static int
3486 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3487 {
3488         struct bnxt *bp = dev->data->dev_private;
3489         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3490         uint64_t ns, systime_cycles = 0;
3491         int rc = 0;
3492
3493         if (!ptp)
3494                 return 0;
3495
3496         if (BNXT_CHIP_THOR(bp))
3497                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3498                                              &systime_cycles);
3499         else
3500                 systime_cycles = bnxt_cc_read(bp);
3501
3502         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3503         *ts = rte_ns_to_timespec(ns);
3504
3505         return rc;
3506 }
3507 static int
3508 bnxt_timesync_enable(struct rte_eth_dev *dev)
3509 {
3510         struct bnxt *bp = dev->data->dev_private;
3511         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3512         uint32_t shift = 0;
3513         int rc;
3514
3515         if (!ptp)
3516                 return 0;
3517
3518         ptp->rx_filter = 1;
3519         ptp->tx_tstamp_en = 1;
3520         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3521
3522         rc = bnxt_hwrm_ptp_cfg(bp);
3523         if (rc)
3524                 return rc;
3525
3526         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3527         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3528         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3529
3530         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3531         ptp->tc.cc_shift = shift;
3532         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3533
3534         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3535         ptp->rx_tstamp_tc.cc_shift = shift;
3536         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3537
3538         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3539         ptp->tx_tstamp_tc.cc_shift = shift;
3540         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3541
3542         if (!BNXT_CHIP_THOR(bp))
3543                 bnxt_map_ptp_regs(bp);
3544
3545         return 0;
3546 }
3547
3548 static int
3549 bnxt_timesync_disable(struct rte_eth_dev *dev)
3550 {
3551         struct bnxt *bp = dev->data->dev_private;
3552         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3553
3554         if (!ptp)
3555                 return 0;
3556
3557         ptp->rx_filter = 0;
3558         ptp->tx_tstamp_en = 0;
3559         ptp->rxctl = 0;
3560
3561         bnxt_hwrm_ptp_cfg(bp);
3562
3563         if (!BNXT_CHIP_THOR(bp))
3564                 bnxt_unmap_ptp_regs(bp);
3565
3566         return 0;
3567 }
3568
3569 static int
3570 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3571                                  struct timespec *timestamp,
3572                                  uint32_t flags __rte_unused)
3573 {
3574         struct bnxt *bp = dev->data->dev_private;
3575         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3576         uint64_t rx_tstamp_cycles = 0;
3577         uint64_t ns;
3578
3579         if (!ptp)
3580                 return 0;
3581
3582         if (BNXT_CHIP_THOR(bp))
3583                 rx_tstamp_cycles = ptp->rx_timestamp;
3584         else
3585                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3586
3587         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3588         *timestamp = rte_ns_to_timespec(ns);
3589         return  0;
3590 }
3591
3592 static int
3593 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3594                                  struct timespec *timestamp)
3595 {
3596         struct bnxt *bp = dev->data->dev_private;
3597         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3598         uint64_t tx_tstamp_cycles = 0;
3599         uint64_t ns;
3600         int rc = 0;
3601
3602         if (!ptp)
3603                 return 0;
3604
3605         if (BNXT_CHIP_THOR(bp))
3606                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3607                                              &tx_tstamp_cycles);
3608         else
3609                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3610
3611         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3612         *timestamp = rte_ns_to_timespec(ns);
3613
3614         return rc;
3615 }
3616
3617 static int
3618 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3619 {
3620         struct bnxt *bp = dev->data->dev_private;
3621         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3622
3623         if (!ptp)
3624                 return 0;
3625
3626         ptp->tc.nsec += delta;
3627
3628         return 0;
3629 }
3630
3631 static int
3632 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3633 {
3634         struct bnxt *bp = dev->data->dev_private;
3635         int rc;
3636         uint32_t dir_entries;
3637         uint32_t entry_length;
3638
3639         rc = is_bnxt_in_error(bp);
3640         if (rc)
3641                 return rc;
3642
3643         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3644                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3645                     bp->pdev->addr.devid, bp->pdev->addr.function);
3646
3647         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3648         if (rc != 0)
3649                 return rc;
3650
3651         return dir_entries * entry_length;
3652 }
3653
3654 static int
3655 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3656                 struct rte_dev_eeprom_info *in_eeprom)
3657 {
3658         struct bnxt *bp = dev->data->dev_private;
3659         uint32_t index;
3660         uint32_t offset;
3661         int rc;
3662
3663         rc = is_bnxt_in_error(bp);
3664         if (rc)
3665                 return rc;
3666
3667         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3668                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3669                     bp->pdev->addr.devid, bp->pdev->addr.function,
3670                     in_eeprom->offset, in_eeprom->length);
3671
3672         if (in_eeprom->offset == 0) /* special offset value to get directory */
3673                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3674                                                 in_eeprom->data);
3675
3676         index = in_eeprom->offset >> 24;
3677         offset = in_eeprom->offset & 0xffffff;
3678
3679         if (index != 0)
3680                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3681                                            in_eeprom->length, in_eeprom->data);
3682
3683         return 0;
3684 }
3685
3686 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3687 {
3688         switch (dir_type) {
3689         case BNX_DIR_TYPE_CHIMP_PATCH:
3690         case BNX_DIR_TYPE_BOOTCODE:
3691         case BNX_DIR_TYPE_BOOTCODE_2:
3692         case BNX_DIR_TYPE_APE_FW:
3693         case BNX_DIR_TYPE_APE_PATCH:
3694         case BNX_DIR_TYPE_KONG_FW:
3695         case BNX_DIR_TYPE_KONG_PATCH:
3696         case BNX_DIR_TYPE_BONO_FW:
3697         case BNX_DIR_TYPE_BONO_PATCH:
3698                 /* FALLTHROUGH */
3699                 return true;
3700         }
3701
3702         return false;
3703 }
3704
3705 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3706 {
3707         switch (dir_type) {
3708         case BNX_DIR_TYPE_AVS:
3709         case BNX_DIR_TYPE_EXP_ROM_MBA:
3710         case BNX_DIR_TYPE_PCIE:
3711         case BNX_DIR_TYPE_TSCF_UCODE:
3712         case BNX_DIR_TYPE_EXT_PHY:
3713         case BNX_DIR_TYPE_CCM:
3714         case BNX_DIR_TYPE_ISCSI_BOOT:
3715         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3716         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3717                 /* FALLTHROUGH */
3718                 return true;
3719         }
3720
3721         return false;
3722 }
3723
3724 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3725 {
3726         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3727                 bnxt_dir_type_is_other_exec_format(dir_type);
3728 }
3729
3730 static int
3731 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3732                 struct rte_dev_eeprom_info *in_eeprom)
3733 {
3734         struct bnxt *bp = dev->data->dev_private;
3735         uint8_t index, dir_op;
3736         uint16_t type, ext, ordinal, attr;
3737         int rc;
3738
3739         rc = is_bnxt_in_error(bp);
3740         if (rc)
3741                 return rc;
3742
3743         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3744                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3745                     bp->pdev->addr.devid, bp->pdev->addr.function,
3746                     in_eeprom->offset, in_eeprom->length);
3747
3748         if (!BNXT_PF(bp)) {
3749                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3750                 return -EINVAL;
3751         }
3752
3753         type = in_eeprom->magic >> 16;
3754
3755         if (type == 0xffff) { /* special value for directory operations */
3756                 index = in_eeprom->magic & 0xff;
3757                 dir_op = in_eeprom->magic >> 8;
3758                 if (index == 0)
3759                         return -EINVAL;
3760                 switch (dir_op) {
3761                 case 0x0e: /* erase */
3762                         if (in_eeprom->offset != ~in_eeprom->magic)
3763                                 return -EINVAL;
3764                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3765                 default:
3766                         return -EINVAL;
3767                 }
3768         }
3769
3770         /* Create or re-write an NVM item: */
3771         if (bnxt_dir_type_is_executable(type) == true)
3772                 return -EOPNOTSUPP;
3773         ext = in_eeprom->magic & 0xffff;
3774         ordinal = in_eeprom->offset >> 16;
3775         attr = in_eeprom->offset & 0xffff;
3776
3777         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3778                                      in_eeprom->data, in_eeprom->length);
3779 }
3780
3781 /*
3782  * Initialization
3783  */
3784
3785 static const struct eth_dev_ops bnxt_dev_ops = {
3786         .dev_infos_get = bnxt_dev_info_get_op,
3787         .dev_close = bnxt_dev_close_op,
3788         .dev_configure = bnxt_dev_configure_op,
3789         .dev_start = bnxt_dev_start_op,
3790         .dev_stop = bnxt_dev_stop_op,
3791         .dev_set_link_up = bnxt_dev_set_link_up_op,
3792         .dev_set_link_down = bnxt_dev_set_link_down_op,
3793         .stats_get = bnxt_stats_get_op,
3794         .stats_reset = bnxt_stats_reset_op,
3795         .rx_queue_setup = bnxt_rx_queue_setup_op,
3796         .rx_queue_release = bnxt_rx_queue_release_op,
3797         .tx_queue_setup = bnxt_tx_queue_setup_op,
3798         .tx_queue_release = bnxt_tx_queue_release_op,
3799         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3800         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3801         .reta_update = bnxt_reta_update_op,
3802         .reta_query = bnxt_reta_query_op,
3803         .rss_hash_update = bnxt_rss_hash_update_op,
3804         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3805         .link_update = bnxt_link_update_op,
3806         .promiscuous_enable = bnxt_promiscuous_enable_op,
3807         .promiscuous_disable = bnxt_promiscuous_disable_op,
3808         .allmulticast_enable = bnxt_allmulticast_enable_op,
3809         .allmulticast_disable = bnxt_allmulticast_disable_op,
3810         .mac_addr_add = bnxt_mac_addr_add_op,
3811         .mac_addr_remove = bnxt_mac_addr_remove_op,
3812         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3813         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3814         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3815         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3816         .vlan_filter_set = bnxt_vlan_filter_set_op,
3817         .vlan_offload_set = bnxt_vlan_offload_set_op,
3818         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3819         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3820         .mtu_set = bnxt_mtu_set_op,
3821         .mac_addr_set = bnxt_set_default_mac_addr_op,
3822         .xstats_get = bnxt_dev_xstats_get_op,
3823         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3824         .xstats_reset = bnxt_dev_xstats_reset_op,
3825         .fw_version_get = bnxt_fw_version_get,
3826         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3827         .rxq_info_get = bnxt_rxq_info_get_op,
3828         .txq_info_get = bnxt_txq_info_get_op,
3829         .dev_led_on = bnxt_dev_led_on_op,
3830         .dev_led_off = bnxt_dev_led_off_op,
3831         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3832         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3833         .rx_queue_count = bnxt_rx_queue_count_op,
3834         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3835         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3836         .rx_queue_start = bnxt_rx_queue_start,
3837         .rx_queue_stop = bnxt_rx_queue_stop,
3838         .tx_queue_start = bnxt_tx_queue_start,
3839         .tx_queue_stop = bnxt_tx_queue_stop,
3840         .filter_ctrl = bnxt_filter_ctrl_op,
3841         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3842         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3843         .get_eeprom           = bnxt_get_eeprom_op,
3844         .set_eeprom           = bnxt_set_eeprom_op,
3845         .timesync_enable      = bnxt_timesync_enable,
3846         .timesync_disable     = bnxt_timesync_disable,
3847         .timesync_read_time   = bnxt_timesync_read_time,
3848         .timesync_write_time   = bnxt_timesync_write_time,
3849         .timesync_adjust_time = bnxt_timesync_adjust_time,
3850         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3851         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3852 };
3853
3854 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3855 {
3856         uint32_t offset;
3857
3858         /* Only pre-map the reset GRC registers using window 3 */
3859         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3860                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3861
3862         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3863
3864         return offset;
3865 }
3866
3867 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3868 {
3869         struct bnxt_error_recovery_info *info = bp->recovery_info;
3870         uint32_t reg_base = 0xffffffff;
3871         int i;
3872
3873         /* Only pre-map the monitoring GRC registers using window 2 */
3874         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3875                 uint32_t reg = info->status_regs[i];
3876
3877                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3878                         continue;
3879
3880                 if (reg_base == 0xffffffff)
3881                         reg_base = reg & 0xfffff000;
3882                 if ((reg & 0xfffff000) != reg_base)
3883                         return -ERANGE;
3884
3885                 /* Use mask 0xffc as the Lower 2 bits indicates
3886                  * address space location
3887                  */
3888                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3889                                                 (reg & 0xffc);
3890         }
3891
3892         if (reg_base == 0xffffffff)
3893                 return 0;
3894
3895         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3896                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3897
3898         return 0;
3899 }
3900
3901 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3902 {
3903         struct bnxt_error_recovery_info *info = bp->recovery_info;
3904         uint32_t delay = info->delay_after_reset[index];
3905         uint32_t val = info->reset_reg_val[index];
3906         uint32_t reg = info->reset_reg[index];
3907         uint32_t type, offset;
3908
3909         type = BNXT_FW_STATUS_REG_TYPE(reg);
3910         offset = BNXT_FW_STATUS_REG_OFF(reg);
3911
3912         switch (type) {
3913         case BNXT_FW_STATUS_REG_TYPE_CFG:
3914                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3915                 break;
3916         case BNXT_FW_STATUS_REG_TYPE_GRC:
3917                 offset = bnxt_map_reset_regs(bp, offset);
3918                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3919                 break;
3920         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3921                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3922                 break;
3923         }
3924         /* wait on a specific interval of time until core reset is complete */
3925         if (delay)
3926                 rte_delay_ms(delay);
3927 }
3928
3929 static void bnxt_dev_cleanup(struct bnxt *bp)
3930 {
3931         bnxt_set_hwrm_link_config(bp, false);
3932         bp->link_info.link_up = 0;
3933         if (bp->eth_dev->data->dev_started)
3934                 bnxt_dev_stop_op(bp->eth_dev);
3935
3936         bnxt_uninit_resources(bp, true);
3937 }
3938
3939 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3940 {
3941         struct rte_eth_dev *dev = bp->eth_dev;
3942         struct rte_vlan_filter_conf *vfc;
3943         int vidx, vbit, rc;
3944         uint16_t vlan_id;
3945
3946         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3947                 vfc = &dev->data->vlan_filter_conf;
3948                 vidx = vlan_id / 64;
3949                 vbit = vlan_id % 64;
3950
3951                 /* Each bit corresponds to a VLAN id */
3952                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3953                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3954                         if (rc)
3955                                 return rc;
3956                 }
3957         }
3958
3959         return 0;
3960 }
3961
3962 static int bnxt_restore_mac_filters(struct bnxt *bp)
3963 {
3964         struct rte_eth_dev *dev = bp->eth_dev;
3965         struct rte_eth_dev_info dev_info;
3966         struct rte_ether_addr *addr;
3967         uint64_t pool_mask;
3968         uint32_t pool = 0;
3969         uint16_t i;
3970         int rc;
3971
3972         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
3973                 return 0;
3974
3975         rc = bnxt_dev_info_get_op(dev, &dev_info);
3976         if (rc)
3977                 return rc;
3978
3979         /* replay MAC address configuration */
3980         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3981                 addr = &dev->data->mac_addrs[i];
3982
3983                 /* skip zero address */
3984                 if (rte_is_zero_ether_addr(addr))
3985                         continue;
3986
3987                 pool = 0;
3988                 pool_mask = dev->data->mac_pool_sel[i];
3989
3990                 do {
3991                         if (pool_mask & 1ULL) {
3992                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3993                                 if (rc)
3994                                         return rc;
3995                         }
3996                         pool_mask >>= 1;
3997                         pool++;
3998                 } while (pool_mask);
3999         }
4000
4001         return 0;
4002 }
4003
4004 static int bnxt_restore_filters(struct bnxt *bp)
4005 {
4006         struct rte_eth_dev *dev = bp->eth_dev;
4007         int ret = 0;
4008
4009         if (dev->data->all_multicast) {
4010                 ret = bnxt_allmulticast_enable_op(dev);
4011                 if (ret)
4012                         return ret;
4013         }
4014         if (dev->data->promiscuous) {
4015                 ret = bnxt_promiscuous_enable_op(dev);
4016                 if (ret)
4017                         return ret;
4018         }
4019
4020         ret = bnxt_restore_mac_filters(bp);
4021         if (ret)
4022                 return ret;
4023
4024         ret = bnxt_restore_vlan_filters(bp);
4025         /* TODO restore other filters as well */
4026         return ret;
4027 }
4028
4029 static void bnxt_dev_recover(void *arg)
4030 {
4031         struct bnxt *bp = arg;
4032         int timeout = bp->fw_reset_max_msecs;
4033         int rc = 0;
4034
4035         /* Clear Error flag so that device re-init should happen */
4036         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4037
4038         do {
4039                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4040                 if (rc == 0)
4041                         break;
4042                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4043                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4044         } while (rc && timeout);
4045
4046         if (rc) {
4047                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4048                 goto err;
4049         }
4050
4051         rc = bnxt_init_resources(bp, true);
4052         if (rc) {
4053                 PMD_DRV_LOG(ERR,
4054                             "Failed to initialize resources after reset\n");
4055                 goto err;
4056         }
4057         /* clear reset flag as the device is initialized now */
4058         bp->flags &= ~BNXT_FLAG_FW_RESET;
4059
4060         rc = bnxt_dev_start_op(bp->eth_dev);
4061         if (rc) {
4062                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4063                 goto err_start;
4064         }
4065
4066         rc = bnxt_restore_filters(bp);
4067         if (rc)
4068                 goto err_start;
4069
4070         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4071         return;
4072 err_start:
4073         bnxt_dev_stop_op(bp->eth_dev);
4074 err:
4075         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4076         bnxt_uninit_resources(bp, false);
4077         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4078 }
4079
4080 void bnxt_dev_reset_and_resume(void *arg)
4081 {
4082         struct bnxt *bp = arg;
4083         int rc;
4084
4085         bnxt_dev_cleanup(bp);
4086
4087         bnxt_wait_for_device_shutdown(bp);
4088
4089         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4090                                bnxt_dev_recover, (void *)bp);
4091         if (rc)
4092                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4093 }
4094
4095 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4096 {
4097         struct bnxt_error_recovery_info *info = bp->recovery_info;
4098         uint32_t reg = info->status_regs[index];
4099         uint32_t type, offset, val = 0;
4100
4101         type = BNXT_FW_STATUS_REG_TYPE(reg);
4102         offset = BNXT_FW_STATUS_REG_OFF(reg);
4103
4104         switch (type) {
4105         case BNXT_FW_STATUS_REG_TYPE_CFG:
4106                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4107                 break;
4108         case BNXT_FW_STATUS_REG_TYPE_GRC:
4109                 offset = info->mapped_status_regs[index];
4110                 /* FALLTHROUGH */
4111         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4112                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4113                                        offset));
4114                 break;
4115         }
4116
4117         return val;
4118 }
4119
4120 static int bnxt_fw_reset_all(struct bnxt *bp)
4121 {
4122         struct bnxt_error_recovery_info *info = bp->recovery_info;
4123         uint32_t i;
4124         int rc = 0;
4125
4126         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4127                 /* Reset through master function driver */
4128                 for (i = 0; i < info->reg_array_cnt; i++)
4129                         bnxt_write_fw_reset_reg(bp, i);
4130                 /* Wait for time specified by FW after triggering reset */
4131                 rte_delay_ms(info->master_func_wait_period_after_reset);
4132         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4133                 /* Reset with the help of Kong processor */
4134                 rc = bnxt_hwrm_fw_reset(bp);
4135                 if (rc)
4136                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4137         }
4138
4139         return rc;
4140 }
4141
4142 static void bnxt_fw_reset_cb(void *arg)
4143 {
4144         struct bnxt *bp = arg;
4145         struct bnxt_error_recovery_info *info = bp->recovery_info;
4146         int rc = 0;
4147
4148         /* Only Master function can do FW reset */
4149         if (bnxt_is_master_func(bp) &&
4150             bnxt_is_recovery_enabled(bp)) {
4151                 rc = bnxt_fw_reset_all(bp);
4152                 if (rc) {
4153                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4154                         return;
4155                 }
4156         }
4157
4158         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4159          * EXCEPTION_FATAL_ASYNC event to all the functions
4160          * (including MASTER FUNC). After receiving this Async, all the active
4161          * drivers should treat this case as FW initiated recovery
4162          */
4163         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4164                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4165                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4166
4167                 /* To recover from error */
4168                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4169                                   (void *)bp);
4170         }
4171 }
4172
4173 /* Driver should poll FW heartbeat, reset_counter with the frequency
4174  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4175  * When the driver detects heartbeat stop or change in reset_counter,
4176  * it has to trigger a reset to recover from the error condition.
4177  * A “master PF” is the function who will have the privilege to
4178  * initiate the chimp reset. The master PF will be elected by the
4179  * firmware and will be notified through async message.
4180  */
4181 static void bnxt_check_fw_health(void *arg)
4182 {
4183         struct bnxt *bp = arg;
4184         struct bnxt_error_recovery_info *info = bp->recovery_info;
4185         uint32_t val = 0, wait_msec;
4186
4187         if (!info || !bnxt_is_recovery_enabled(bp) ||
4188             is_bnxt_in_error(bp))
4189                 return;
4190
4191         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4192         if (val == info->last_heart_beat)
4193                 goto reset;
4194
4195         info->last_heart_beat = val;
4196
4197         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4198         if (val != info->last_reset_counter)
4199                 goto reset;
4200
4201         info->last_reset_counter = val;
4202
4203         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4204                           bnxt_check_fw_health, (void *)bp);
4205
4206         return;
4207 reset:
4208         /* Stop DMA to/from device */
4209         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4210         bp->flags |= BNXT_FLAG_FW_RESET;
4211
4212         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4213
4214         if (bnxt_is_master_func(bp))
4215                 wait_msec = info->master_func_wait_period;
4216         else
4217                 wait_msec = info->normal_func_wait_period;
4218
4219         rte_eal_alarm_set(US_PER_MS * wait_msec,
4220                           bnxt_fw_reset_cb, (void *)bp);
4221 }
4222
4223 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4224 {
4225         uint32_t polling_freq;
4226
4227         if (!bnxt_is_recovery_enabled(bp))
4228                 return;
4229
4230         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4231                 return;
4232
4233         polling_freq = bp->recovery_info->driver_polling_freq;
4234
4235         rte_eal_alarm_set(US_PER_MS * polling_freq,
4236                           bnxt_check_fw_health, (void *)bp);
4237         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4238 }
4239
4240 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4241 {
4242         if (!bnxt_is_recovery_enabled(bp))
4243                 return;
4244
4245         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4246         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4247 }
4248
4249 static bool bnxt_vf_pciid(uint16_t device_id)
4250 {
4251         switch (device_id) {
4252         case BROADCOM_DEV_ID_57304_VF:
4253         case BROADCOM_DEV_ID_57406_VF:
4254         case BROADCOM_DEV_ID_5731X_VF:
4255         case BROADCOM_DEV_ID_5741X_VF:
4256         case BROADCOM_DEV_ID_57414_VF:
4257         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4258         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4259         case BROADCOM_DEV_ID_58802_VF:
4260         case BROADCOM_DEV_ID_57500_VF1:
4261         case BROADCOM_DEV_ID_57500_VF2:
4262                 /* FALLTHROUGH */
4263                 return true;
4264         default:
4265                 return false;
4266         }
4267 }
4268
4269 static bool bnxt_thor_device(uint16_t device_id)
4270 {
4271         switch (device_id) {
4272         case BROADCOM_DEV_ID_57508:
4273         case BROADCOM_DEV_ID_57504:
4274         case BROADCOM_DEV_ID_57502:
4275         case BROADCOM_DEV_ID_57508_MF1:
4276         case BROADCOM_DEV_ID_57504_MF1:
4277         case BROADCOM_DEV_ID_57502_MF1:
4278         case BROADCOM_DEV_ID_57508_MF2:
4279         case BROADCOM_DEV_ID_57504_MF2:
4280         case BROADCOM_DEV_ID_57502_MF2:
4281         case BROADCOM_DEV_ID_57500_VF1:
4282         case BROADCOM_DEV_ID_57500_VF2:
4283                 /* FALLTHROUGH */
4284                 return true;
4285         default:
4286                 return false;
4287         }
4288 }
4289
4290 bool bnxt_stratus_device(struct bnxt *bp)
4291 {
4292         uint16_t device_id = bp->pdev->id.device_id;
4293
4294         switch (device_id) {
4295         case BROADCOM_DEV_ID_STRATUS_NIC:
4296         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4297         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4298                 /* FALLTHROUGH */
4299                 return true;
4300         default:
4301                 return false;
4302         }
4303 }
4304
4305 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4306 {
4307         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4308         struct bnxt *bp = eth_dev->data->dev_private;
4309
4310         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4311         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4312         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4313         if (!bp->bar0 || !bp->doorbell_base) {
4314                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4315                 return -ENODEV;
4316         }
4317
4318         bp->eth_dev = eth_dev;
4319         bp->pdev = pci_dev;
4320
4321         return 0;
4322 }
4323
4324 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4325                                   struct bnxt_ctx_pg_info *ctx_pg,
4326                                   uint32_t mem_size,
4327                                   const char *suffix,
4328                                   uint16_t idx)
4329 {
4330         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4331         const struct rte_memzone *mz = NULL;
4332         char mz_name[RTE_MEMZONE_NAMESIZE];
4333         rte_iova_t mz_phys_addr;
4334         uint64_t valid_bits = 0;
4335         uint32_t sz;
4336         int i;
4337
4338         if (!mem_size)
4339                 return 0;
4340
4341         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4342                          BNXT_PAGE_SIZE;
4343         rmem->page_size = BNXT_PAGE_SIZE;
4344         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4345         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4346         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4347
4348         valid_bits = PTU_PTE_VALID;
4349
4350         if (rmem->nr_pages > 1) {
4351                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4352                          "bnxt_ctx_pg_tbl%s_%x_%d",
4353                          suffix, idx, bp->eth_dev->data->port_id);
4354                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4355                 mz = rte_memzone_lookup(mz_name);
4356                 if (!mz) {
4357                         mz = rte_memzone_reserve_aligned(mz_name,
4358                                                 rmem->nr_pages * 8,
4359                                                 SOCKET_ID_ANY,
4360                                                 RTE_MEMZONE_2MB |
4361                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4362                                                 RTE_MEMZONE_IOVA_CONTIG,
4363                                                 BNXT_PAGE_SIZE);
4364                         if (mz == NULL)
4365                                 return -ENOMEM;
4366                 }
4367
4368                 memset(mz->addr, 0, mz->len);
4369                 mz_phys_addr = mz->iova;
4370
4371                 rmem->pg_tbl = mz->addr;
4372                 rmem->pg_tbl_map = mz_phys_addr;
4373                 rmem->pg_tbl_mz = mz;
4374         }
4375
4376         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4377                  suffix, idx, bp->eth_dev->data->port_id);
4378         mz = rte_memzone_lookup(mz_name);
4379         if (!mz) {
4380                 mz = rte_memzone_reserve_aligned(mz_name,
4381                                                  mem_size,
4382                                                  SOCKET_ID_ANY,
4383                                                  RTE_MEMZONE_1GB |
4384                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4385                                                  RTE_MEMZONE_IOVA_CONTIG,
4386                                                  BNXT_PAGE_SIZE);
4387                 if (mz == NULL)
4388                         return -ENOMEM;
4389         }
4390
4391         memset(mz->addr, 0, mz->len);
4392         mz_phys_addr = mz->iova;
4393
4394         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4395                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4396                 rmem->dma_arr[i] = mz_phys_addr + sz;
4397
4398                 if (rmem->nr_pages > 1) {
4399                         if (i == rmem->nr_pages - 2 &&
4400                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4401                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4402                         else if (i == rmem->nr_pages - 1 &&
4403                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4404                                 valid_bits |= PTU_PTE_LAST;
4405
4406                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4407                                                            valid_bits);
4408                 }
4409         }
4410
4411         rmem->mz = mz;
4412         if (rmem->vmem_size)
4413                 rmem->vmem = (void **)mz->addr;
4414         rmem->dma_arr[0] = mz_phys_addr;
4415         return 0;
4416 }
4417
4418 static void bnxt_free_ctx_mem(struct bnxt *bp)
4419 {
4420         int i;
4421
4422         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4423                 return;
4424
4425         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4426         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4427         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4428         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4429         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4430         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4431         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4432         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4433         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4434         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4435         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4436
4437         for (i = 0; i < BNXT_MAX_Q; i++) {
4438                 if (bp->ctx->tqm_mem[i])
4439                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4440         }
4441
4442         rte_free(bp->ctx);
4443         bp->ctx = NULL;
4444 }
4445
4446 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4447
4448 #define min_t(type, x, y) ({                    \
4449         type __min1 = (x);                      \
4450         type __min2 = (y);                      \
4451         __min1 < __min2 ? __min1 : __min2; })
4452
4453 #define max_t(type, x, y) ({                    \
4454         type __max1 = (x);                      \
4455         type __max2 = (y);                      \
4456         __max1 > __max2 ? __max1 : __max2; })
4457
4458 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4459
4460 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4461 {
4462         struct bnxt_ctx_pg_info *ctx_pg;
4463         struct bnxt_ctx_mem_info *ctx;
4464         uint32_t mem_size, ena, entries;
4465         int i, rc;
4466
4467         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4468         if (rc) {
4469                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4470                 return rc;
4471         }
4472         ctx = bp->ctx;
4473         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4474                 return 0;
4475
4476         ctx_pg = &ctx->qp_mem;
4477         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4478         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4479         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4480         if (rc)
4481                 return rc;
4482
4483         ctx_pg = &ctx->srq_mem;
4484         ctx_pg->entries = ctx->srq_max_l2_entries;
4485         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4486         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4487         if (rc)
4488                 return rc;
4489
4490         ctx_pg = &ctx->cq_mem;
4491         ctx_pg->entries = ctx->cq_max_l2_entries;
4492         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4493         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4494         if (rc)
4495                 return rc;
4496
4497         ctx_pg = &ctx->vnic_mem;
4498         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4499                 ctx->vnic_max_ring_table_entries;
4500         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4501         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4502         if (rc)
4503                 return rc;
4504
4505         ctx_pg = &ctx->stat_mem;
4506         ctx_pg->entries = ctx->stat_max_entries;
4507         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4508         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4509         if (rc)
4510                 return rc;
4511
4512         entries = ctx->qp_max_l2_entries +
4513                   ctx->vnic_max_vnic_entries +
4514                   ctx->tqm_min_entries_per_ring;
4515         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4516         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4517                           ctx->tqm_max_entries_per_ring);
4518         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4519                 ctx_pg = ctx->tqm_mem[i];
4520                 /* use min tqm entries for now. */
4521                 ctx_pg->entries = entries;
4522                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4523                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4524                 if (rc)
4525                         return rc;
4526                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4527         }
4528
4529         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4530         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4531         if (rc)
4532                 PMD_DRV_LOG(ERR,
4533                             "Failed to configure context mem: rc = %d\n", rc);
4534         else
4535                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4536
4537         return rc;
4538 }
4539
4540 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4541 {
4542         struct rte_pci_device *pci_dev = bp->pdev;
4543         char mz_name[RTE_MEMZONE_NAMESIZE];
4544         const struct rte_memzone *mz = NULL;
4545         uint32_t total_alloc_len;
4546         rte_iova_t mz_phys_addr;
4547
4548         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4549                 return 0;
4550
4551         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4552                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4553                  pci_dev->addr.bus, pci_dev->addr.devid,
4554                  pci_dev->addr.function, "rx_port_stats");
4555         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4556         mz = rte_memzone_lookup(mz_name);
4557         total_alloc_len =
4558                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4559                                        sizeof(struct rx_port_stats_ext) + 512);
4560         if (!mz) {
4561                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4562                                          SOCKET_ID_ANY,
4563                                          RTE_MEMZONE_2MB |
4564                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4565                                          RTE_MEMZONE_IOVA_CONTIG);
4566                 if (mz == NULL)
4567                         return -ENOMEM;
4568         }
4569         memset(mz->addr, 0, mz->len);
4570         mz_phys_addr = mz->iova;
4571
4572         bp->rx_mem_zone = (const void *)mz;
4573         bp->hw_rx_port_stats = mz->addr;
4574         bp->hw_rx_port_stats_map = mz_phys_addr;
4575
4576         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4577                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4578                  pci_dev->addr.bus, pci_dev->addr.devid,
4579                  pci_dev->addr.function, "tx_port_stats");
4580         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4581         mz = rte_memzone_lookup(mz_name);
4582         total_alloc_len =
4583                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4584                                        sizeof(struct tx_port_stats_ext) + 512);
4585         if (!mz) {
4586                 mz = rte_memzone_reserve(mz_name,
4587                                          total_alloc_len,
4588                                          SOCKET_ID_ANY,
4589                                          RTE_MEMZONE_2MB |
4590                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4591                                          RTE_MEMZONE_IOVA_CONTIG);
4592                 if (mz == NULL)
4593                         return -ENOMEM;
4594         }
4595         memset(mz->addr, 0, mz->len);
4596         mz_phys_addr = mz->iova;
4597
4598         bp->tx_mem_zone = (const void *)mz;
4599         bp->hw_tx_port_stats = mz->addr;
4600         bp->hw_tx_port_stats_map = mz_phys_addr;
4601         bp->flags |= BNXT_FLAG_PORT_STATS;
4602
4603         /* Display extended statistics if FW supports it */
4604         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4605             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4606             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4607                 return 0;
4608
4609         bp->hw_rx_port_stats_ext = (void *)
4610                 ((uint8_t *)bp->hw_rx_port_stats +
4611                  sizeof(struct rx_port_stats));
4612         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4613                 sizeof(struct rx_port_stats);
4614         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4615
4616         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4617             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4618                 bp->hw_tx_port_stats_ext = (void *)
4619                         ((uint8_t *)bp->hw_tx_port_stats +
4620                          sizeof(struct tx_port_stats));
4621                 bp->hw_tx_port_stats_ext_map =
4622                         bp->hw_tx_port_stats_map +
4623                         sizeof(struct tx_port_stats);
4624                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4625         }
4626
4627         return 0;
4628 }
4629
4630 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4631 {
4632         struct bnxt *bp = eth_dev->data->dev_private;
4633         int rc = 0;
4634
4635         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4636                                                RTE_ETHER_ADDR_LEN *
4637                                                bp->max_l2_ctx,
4638                                                0);
4639         if (eth_dev->data->mac_addrs == NULL) {
4640                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4641                 return -ENOMEM;
4642         }
4643
4644         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4645                 if (BNXT_PF(bp))
4646                         return -EINVAL;
4647
4648                 /* Generate a random MAC address, if none was assigned by PF */
4649                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4650                 bnxt_eth_hw_addr_random(bp->mac_addr);
4651                 PMD_DRV_LOG(INFO,
4652                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4653                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4654                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4655
4656                 rc = bnxt_hwrm_set_mac(bp);
4657                 if (!rc)
4658                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4659                                RTE_ETHER_ADDR_LEN);
4660                 return rc;
4661         }
4662
4663         /* Copy the permanent MAC from the FUNC_QCAPS response */
4664         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4665         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4666
4667         return rc;
4668 }
4669
4670 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4671 {
4672         int rc = 0;
4673
4674         /* MAC is already configured in FW */
4675         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4676                 return 0;
4677
4678         /* Restore the old MAC configured */
4679         rc = bnxt_hwrm_set_mac(bp);
4680         if (rc)
4681                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4682
4683         return rc;
4684 }
4685
4686 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4687 {
4688         if (!BNXT_PF(bp))
4689                 return;
4690
4691 #define ALLOW_FUNC(x)   \
4692         { \
4693                 uint32_t arg = (x); \
4694                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4695                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4696         }
4697
4698         /* Forward all requests if firmware is new enough */
4699         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4700              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4701             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4702                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4703         } else {
4704                 PMD_DRV_LOG(WARNING,
4705                             "Firmware too old for VF mailbox functionality\n");
4706                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4707         }
4708
4709         /*
4710          * The following are used for driver cleanup. If we disallow these,
4711          * VF drivers can't clean up cleanly.
4712          */
4713         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4714         ALLOW_FUNC(HWRM_VNIC_FREE);
4715         ALLOW_FUNC(HWRM_RING_FREE);
4716         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4717         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4718         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4719         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4720         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4721         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4722 }
4723
4724 uint16_t
4725 bnxt_get_svif(uint16_t port_id, bool func_svif)
4726 {
4727         struct rte_eth_dev *eth_dev;
4728         struct bnxt *bp;
4729
4730         eth_dev = &rte_eth_devices[port_id];
4731         bp = eth_dev->data->dev_private;
4732
4733         return func_svif ? bp->func_svif : bp->port_svif;
4734 }
4735
4736 uint16_t
4737 bnxt_get_vnic_id(uint16_t port)
4738 {
4739         struct rte_eth_dev *eth_dev;
4740         struct bnxt_vnic_info *vnic;
4741         struct bnxt *bp;
4742
4743         eth_dev = &rte_eth_devices[port];
4744         bp = eth_dev->data->dev_private;
4745
4746         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4747
4748         return vnic->fw_vnic_id;
4749 }
4750
4751 static int bnxt_init_fw(struct bnxt *bp)
4752 {
4753         uint16_t mtu;
4754         int rc = 0;
4755
4756         bp->fw_cap = 0;
4757
4758         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4759         if (rc)
4760                 return rc;
4761
4762         rc = bnxt_hwrm_func_reset(bp);
4763         if (rc)
4764                 return -EIO;
4765
4766         rc = bnxt_hwrm_vnic_qcaps(bp);
4767         if (rc)
4768                 return rc;
4769
4770         rc = bnxt_hwrm_queue_qportcfg(bp);
4771         if (rc)
4772                 return rc;
4773
4774         /* Get the MAX capabilities for this function.
4775          * This function also allocates context memory for TQM rings and
4776          * informs the firmware about this allocated backing store memory.
4777          */
4778         rc = bnxt_hwrm_func_qcaps(bp);
4779         if (rc)
4780                 return rc;
4781
4782         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4783         if (rc)
4784                 return rc;
4785
4786         bnxt_hwrm_port_mac_qcfg(bp);
4787
4788         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4789         if (rc)
4790                 return rc;
4791
4792         /* Get the adapter error recovery support info */
4793         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4794         if (rc)
4795                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4796
4797         bnxt_hwrm_port_led_qcaps(bp);
4798
4799         return 0;
4800 }
4801
4802 static int
4803 bnxt_init_locks(struct bnxt *bp)
4804 {
4805         int err;
4806
4807         err = pthread_mutex_init(&bp->flow_lock, NULL);
4808         if (err) {
4809                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4810                 return err;
4811         }
4812
4813         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4814         if (err)
4815                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4816         return err;
4817 }
4818
4819 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4820 {
4821         int rc;
4822
4823         rc = bnxt_init_fw(bp);
4824         if (rc)
4825                 return rc;
4826
4827         if (!reconfig_dev) {
4828                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4829                 if (rc)
4830                         return rc;
4831         } else {
4832                 rc = bnxt_restore_dflt_mac(bp);
4833                 if (rc)
4834                         return rc;
4835         }
4836
4837         bnxt_config_vf_req_fwd(bp);
4838
4839         rc = bnxt_hwrm_func_driver_register(bp);
4840         if (rc) {
4841                 PMD_DRV_LOG(ERR, "Failed to register driver");
4842                 return -EBUSY;
4843         }
4844
4845         if (BNXT_PF(bp)) {
4846                 if (bp->pdev->max_vfs) {
4847                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4848                         if (rc) {
4849                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4850                                 return rc;
4851                         }
4852                 } else {
4853                         rc = bnxt_hwrm_allocate_pf_only(bp);
4854                         if (rc) {
4855                                 PMD_DRV_LOG(ERR,
4856                                             "Failed to allocate PF resources");
4857                                 return rc;
4858                         }
4859                 }
4860         }
4861
4862         rc = bnxt_alloc_mem(bp, reconfig_dev);
4863         if (rc)
4864                 return rc;
4865
4866         rc = bnxt_setup_int(bp);
4867         if (rc)
4868                 return rc;
4869
4870         rc = bnxt_request_int(bp);
4871         if (rc)
4872                 return rc;
4873
4874         rc = bnxt_init_locks(bp);
4875         if (rc)
4876                 return rc;
4877
4878         return 0;
4879 }
4880
4881 static int
4882 bnxt_parse_devarg_truflow(__rte_unused const char *key,
4883                           const char *value, void *opaque_arg)
4884 {
4885         struct bnxt *bp = opaque_arg;
4886         unsigned long truflow;
4887         char *end = NULL;
4888
4889         if (!value || !opaque_arg) {
4890                 PMD_DRV_LOG(ERR,
4891                             "Invalid parameter passed to truflow devargs.\n");
4892                 return -EINVAL;
4893         }
4894
4895         truflow = strtoul(value, &end, 10);
4896         if (end == NULL || *end != '\0' ||
4897             (truflow == ULONG_MAX && errno == ERANGE)) {
4898                 PMD_DRV_LOG(ERR,
4899                             "Invalid parameter passed to truflow devargs.\n");
4900                 return -EINVAL;
4901         }
4902
4903         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
4904                 PMD_DRV_LOG(ERR,
4905                             "Invalid value passed to truflow devargs.\n");
4906                 return -EINVAL;
4907         }
4908
4909         bp->truflow = truflow;
4910         if (bp->truflow)
4911                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
4912
4913         return 0;
4914 }
4915
4916 static void
4917 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
4918 {
4919         struct rte_kvargs *kvlist;
4920
4921         if (devargs == NULL)
4922                 return;
4923
4924         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
4925         if (kvlist == NULL)
4926                 return;
4927
4928         /*
4929          * Handler for "truflow" devarg.
4930          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1”
4931          */
4932         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
4933                            bnxt_parse_devarg_truflow, bp);
4934
4935         rte_kvargs_free(kvlist);
4936 }
4937
4938 static int
4939 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4940 {
4941         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4942         static int version_printed;
4943         struct bnxt *bp;
4944         int rc;
4945
4946         if (version_printed++ == 0)
4947                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4948
4949         eth_dev->dev_ops = &bnxt_dev_ops;
4950         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4951         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4952
4953         /*
4954          * For secondary processes, we don't initialise any further
4955          * as primary has already done this work.
4956          */
4957         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4958                 return 0;
4959
4960         rte_eth_copy_pci_info(eth_dev, pci_dev);
4961
4962         bp = eth_dev->data->dev_private;
4963
4964         /* Parse dev arguments passed on when starting the DPDK application. */
4965         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
4966
4967         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
4968
4969         if (bnxt_vf_pciid(pci_dev->id.device_id))
4970                 bp->flags |= BNXT_FLAG_VF;
4971
4972         if (bnxt_thor_device(pci_dev->id.device_id))
4973                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4974
4975         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4976             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4977             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4978             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4979                 bp->flags |= BNXT_FLAG_STINGRAY;
4980
4981         rc = bnxt_init_board(eth_dev);
4982         if (rc) {
4983                 PMD_DRV_LOG(ERR,
4984                             "Failed to initialize board rc: %x\n", rc);
4985                 return rc;
4986         }
4987
4988         rc = bnxt_alloc_hwrm_resources(bp);
4989         if (rc) {
4990                 PMD_DRV_LOG(ERR,
4991                             "Failed to allocate hwrm resource rc: %x\n", rc);
4992                 goto error_free;
4993         }
4994         rc = bnxt_init_resources(bp, false);
4995         if (rc)
4996                 goto error_free;
4997
4998         rc = bnxt_alloc_stats_mem(bp);
4999         if (rc)
5000                 goto error_free;
5001
5002         /* Pass the information to the rte_eth_dev_close() that it should also
5003          * release the private port resources.
5004          */
5005         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5006
5007         PMD_DRV_LOG(INFO,
5008                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5009                     pci_dev->mem_resource[0].phys_addr,
5010                     pci_dev->mem_resource[0].addr);
5011
5012         return 0;
5013
5014 error_free:
5015         bnxt_dev_uninit(eth_dev);
5016         return rc;
5017 }
5018
5019 static void
5020 bnxt_uninit_locks(struct bnxt *bp)
5021 {
5022         pthread_mutex_destroy(&bp->flow_lock);
5023         pthread_mutex_destroy(&bp->def_cp_lock);
5024 }
5025
5026 static int
5027 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5028 {
5029         int rc;
5030
5031         bnxt_free_int(bp);
5032         bnxt_free_mem(bp, reconfig_dev);
5033         bnxt_hwrm_func_buf_unrgtr(bp);
5034         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5035         bp->flags &= ~BNXT_FLAG_REGISTERED;
5036         bnxt_free_ctx_mem(bp);
5037         if (!reconfig_dev) {
5038                 bnxt_free_hwrm_resources(bp);
5039
5040                 if (bp->recovery_info != NULL) {
5041                         rte_free(bp->recovery_info);
5042                         bp->recovery_info = NULL;
5043                 }
5044         }
5045
5046         bnxt_uninit_locks(bp);
5047         rte_free(bp->ptp_cfg);
5048         bp->ptp_cfg = NULL;
5049         return rc;
5050 }
5051
5052 static int
5053 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5054 {
5055         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5056                 return -EPERM;
5057
5058         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5059
5060         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5061                 bnxt_dev_close_op(eth_dev);
5062
5063         return 0;
5064 }
5065
5066 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5067         struct rte_pci_device *pci_dev)
5068 {
5069         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
5070                 bnxt_dev_init);
5071 }
5072
5073 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5074 {
5075         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
5076                 return rte_eth_dev_pci_generic_remove(pci_dev,
5077                                 bnxt_dev_uninit);
5078         else
5079                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5080 }
5081
5082 static struct rte_pci_driver bnxt_rte_pmd = {
5083         .id_table = bnxt_pci_id_map,
5084         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5085         .probe = bnxt_pci_probe,
5086         .remove = bnxt_pci_remove,
5087 };
5088
5089 static bool
5090 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5091 {
5092         if (strcmp(dev->device->driver->name, drv->driver.name))
5093                 return false;
5094
5095         return true;
5096 }
5097
5098 bool is_bnxt_supported(struct rte_eth_dev *dev)
5099 {
5100         return is_device_supported(dev, &bnxt_rte_pmd);
5101 }
5102
5103 RTE_INIT(bnxt_init_log)
5104 {
5105         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
5106         if (bnxt_logtype_driver >= 0)
5107                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
5108 }
5109
5110 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5111 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5112 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");