drivers/net/bnxt/bnxt_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <inttypes.h>
  35 #include <stdbool.h>
  36
  37 #include <rte_dev.h>
  38 #include <rte_ethdev.h>
  39 #include <rte_ethdev_pci.h>
  40 #include <rte_malloc.h>
  41 #include <rte_cycles.h>
  42
  43 #include "bnxt.h"
  44 #include "bnxt_cpr.h"
  45 #include "bnxt_filter.h"
  46 #include "bnxt_hwrm.h"
  47 #include "bnxt_irq.h"
  48 #include "bnxt_ring.h"
  49 #include "bnxt_rxq.h"
  50 #include "bnxt_rxr.h"
  51 #include "bnxt_stats.h"
  52 #include "bnxt_txq.h"
  53 #include "bnxt_txr.h"
  54 #include "bnxt_vnic.h"
  55 #include "hsi_struct_def_dpdk.h"
  56 #include "bnxt_nvm_defs.h"
  57
  58 #define DRV_MODULE_NAME         "bnxt"
  59 static const char bnxt_version[] =
  60         "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
  61
  62 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  63
  64 #define BROADCOM_DEV_ID_STRATUS_NIC_VF 0x1609
  65 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  66 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  67 #define BROADCOM_DEV_ID_57301 0x16c8
  68 #define BROADCOM_DEV_ID_57302 0x16c9
  69 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  70 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  71 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  72 #define BROADCOM_DEV_ID_NS2 0x16cd
  73 #define BROADCOM_DEV_ID_57311 0x16ce
  74 #define BROADCOM_DEV_ID_57312 0x16cf
  75 #define BROADCOM_DEV_ID_57402 0x16d0
  76 #define BROADCOM_DEV_ID_57404 0x16d1
  77 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  78 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  79 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  80 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  81 #define BROADCOM_DEV_ID_57412 0x16d6
  82 #define BROADCOM_DEV_ID_57414 0x16d7
  83 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  84 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  85 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  86 #define BROADCOM_DEV_ID_57412_MF 0x16de
  87 #define BROADCOM_DEV_ID_57314 0x16df
  88 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  89 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  90 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  91 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  92 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  93 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  94 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  95 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  96 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  97 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  98 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  99
 100 static const struct rte_pci_id bnxt_pci_id_map[] = {
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
 102                          BROADCOM_DEV_ID_STRATUS_NIC_VF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 130         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 131         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 132         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 133         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 134         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 135         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 136         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 137         { .vendor_id = 0, /* sentinel */ },
 138 };
 139
 140 #define BNXT_ETH_RSS_SUPPORT (  \
 141         ETH_RSS_IPV4 |          \
 142         ETH_RSS_NONFRAG_IPV4_TCP |      \
 143         ETH_RSS_NONFRAG_IPV4_UDP |      \
 144         ETH_RSS_IPV6 |          \
 145         ETH_RSS_NONFRAG_IPV6_TCP |      \
 146         ETH_RSS_NONFRAG_IPV6_UDP)
 147
 148 static void bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 149
 150 /***********************/
 151
 152 /*
 153  * High level utility functions
 154  */
 155
 156 static void bnxt_free_mem(struct bnxt *bp)
 157 {
 158         bnxt_free_filter_mem(bp);
 159         bnxt_free_vnic_attributes(bp);
 160         bnxt_free_vnic_mem(bp);
 161
 162         bnxt_free_stats(bp);
 163         bnxt_free_tx_rings(bp);
 164         bnxt_free_rx_rings(bp);
 165         bnxt_free_def_cp_ring(bp);
 166 }
 167
 168 static int bnxt_alloc_mem(struct bnxt *bp)
 169 {
 170         int rc;
 171
 172         /* Default completion ring */
 173         rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
 174         if (rc)
 175                 goto alloc_mem_err;
 176
 177         rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
 178                               bp->def_cp_ring, "def_cp");
 179         if (rc)
 180                 goto alloc_mem_err;
 181
 182         rc = bnxt_alloc_vnic_mem(bp);
 183         if (rc)
 184                 goto alloc_mem_err;
 185
 186         rc = bnxt_alloc_vnic_attributes(bp);
 187         if (rc)
 188                 goto alloc_mem_err;
 189
 190         rc = bnxt_alloc_filter_mem(bp);
 191         if (rc)
 192                 goto alloc_mem_err;
 193
 194         return 0;
 195
 196 alloc_mem_err:
 197         bnxt_free_mem(bp);
 198         return rc;
 199 }
 200
 201 static int bnxt_init_chip(struct bnxt *bp)
 202 {
 203         unsigned int i, rss_idx, fw_idx;
 204         struct rte_eth_link new;
 205         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 206         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 207         uint32_t intr_vector = 0;
 208         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 209         uint32_t vec = BNXT_MISC_VEC_ID;
 210         int rc;
 211
 212         /* disable uio/vfio intr/eventfd mapping */
 213         rte_intr_disable(intr_handle);
 214
 215         if (bp->eth_dev->data->mtu > ETHER_MTU) {
 216                 bp->eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
 217                 bp->flags |= BNXT_FLAG_JUMBO;
 218         } else {
 219                 bp->eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
 220                 bp->flags &= ~BNXT_FLAG_JUMBO;
 221         }
 222
 223         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 224         if (rc) {
 225                 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
 226                 goto err_out;
 227         }
 228
 229         rc = bnxt_alloc_hwrm_rings(bp);
 230         if (rc) {
 231                 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
 232                 goto err_out;
 233         }
 234
 235         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 236         if (rc) {
 237                 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
 238                 goto err_out;
 239         }
 240
 241         rc = bnxt_mq_rx_configure(bp);
 242         if (rc) {
 243                 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
 244                 goto err_out;
 245         }
 246
 247         /* VNIC configuration */
 248         for (i = 0; i < bp->nr_vnics; i++) {
 249                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 250
 251                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 252                 if (rc) {
 253                         RTE_LOG(ERR, PMD, "HWRM vnic %d alloc failure rc: %x\n",
 254                                 i, rc);
 255                         goto err_out;
 256                 }
 257
 258                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
 259                 if (rc) {
 260                         RTE_LOG(ERR, PMD,
 261                                 "HWRM vnic %d ctx alloc failure rc: %x\n",
 262                                 i, rc);
 263                         goto err_out;
 264                 }
 265
 266                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 267                 if (rc) {
 268                         RTE_LOG(ERR, PMD, "HWRM vnic %d cfg failure rc: %x\n",
 269                                 i, rc);
 270                         goto err_out;
 271                 }
 272
 273                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 274                 if (rc) {
 275                         RTE_LOG(ERR, PMD,
 276                                 "HWRM vnic %d filter failure rc: %x\n",
 277                                 i, rc);
 278                         goto err_out;
 279                 }
 280                 if (vnic->rss_table && vnic->hash_type) {
 281                         /*
 282                          * Fill the RSS hash & redirection table with
 283                          * ring group ids for all VNICs
 284                          */
 285                         for (rss_idx = 0, fw_idx = 0;
 286                              rss_idx < HW_HASH_INDEX_SIZE;
 287                              rss_idx++, fw_idx++) {
 288                                 if (vnic->fw_grp_ids[fw_idx] ==
 289                                     INVALID_HW_RING_ID)
 290                                         fw_idx = 0;
 291                                 vnic->rss_table[rss_idx] =
 292                                                 vnic->fw_grp_ids[fw_idx];
 293                         }
 294                         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 295                         if (rc) {
 296                                 RTE_LOG(ERR, PMD,
 297                                         "HWRM vnic %d set RSS failure rc: %x\n",
 298                                         i, rc);
 299                                 goto err_out;
 300                         }
 301                 }
 302
 303                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 304
 305                 if (bp->eth_dev->data->dev_conf.rxmode.enable_lro)
 306                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 307                 else
 308                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 309         }
 310         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 311         if (rc) {
 312                 RTE_LOG(ERR, PMD,
 313                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 314                 goto err_out;
 315         }
 316
 317         /* check and configure queue intr-vector mapping */
 318         if ((rte_intr_cap_multiple(intr_handle) ||
 319              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 320             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 321                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 322                 RTE_LOG(INFO, PMD, "%s(): intr_vector = %d\n", __func__,
 323                         intr_vector);
 324                 if (intr_vector > bp->rx_cp_nr_rings) {
 325                         RTE_LOG(ERR, PMD, "At most %d intr queues supported",
 326                                         bp->rx_cp_nr_rings);
 327                         return -ENOTSUP;
 328                 }
 329                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 330                         return -1;
 331         }
 332
 333         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 334                 intr_handle->intr_vec =
 335                         rte_zmalloc("intr_vec",
 336                                     bp->eth_dev->data->nb_rx_queues *
 337                                     sizeof(int), 0);
 338                 if (intr_handle->intr_vec == NULL) {
 339                         RTE_LOG(ERR, PMD, "Failed to allocate %d rx_queues"
 340                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 341                         return -ENOMEM;
 342                 }
 343                 RTE_LOG(DEBUG, PMD, "%s(): intr_handle->intr_vec = %p "
 344                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 345                          __func__, intr_handle->intr_vec, intr_handle->nb_efd,
 346                         intr_handle->max_intr);
 347         }
 348
 349         for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 350              queue_id++) {
 351                 intr_handle->intr_vec[queue_id] = vec;
 352                 if (vec < base + intr_handle->nb_efd - 1)
 353                         vec++;
 354         }
 355
 356         /* enable uio/vfio intr/eventfd mapping */
 357         rte_intr_enable(intr_handle);
 358
 359         rc = bnxt_get_hwrm_link_config(bp, &new);
 360         if (rc) {
 361                 RTE_LOG(ERR, PMD, "HWRM Get link config failure rc: %x\n", rc);
 362                 goto err_out;
 363         }
 364
 365         if (!bp->link_info.link_up) {
 366                 rc = bnxt_set_hwrm_link_config(bp, true);
 367                 if (rc) {
 368                         RTE_LOG(ERR, PMD,
 369                                 "HWRM link config failure rc: %x\n", rc);
 370                         goto err_out;
 371                 }
 372         }
 373
 374         return 0;
 375
 376 err_out:
 377         bnxt_free_all_hwrm_resources(bp);
 378
 379         return rc;
 380 }
 381
 382 static int bnxt_shutdown_nic(struct bnxt *bp)
 383 {
 384         bnxt_free_all_hwrm_resources(bp);
 385         bnxt_free_all_filters(bp);
 386         bnxt_free_all_vnics(bp);
 387         return 0;
 388 }
 389
 390 static int bnxt_init_nic(struct bnxt *bp)
 391 {
 392         int rc;
 393
 394         bnxt_init_ring_grps(bp);
 395         bnxt_init_vnics(bp);
 396         bnxt_init_filters(bp);
 397
 398         rc = bnxt_init_chip(bp);
 399         if (rc)
 400                 return rc;
 401
 402         return 0;
 403 }
 404
 405 /*
 406  * Device configuration and status function
 407  */
 408
 409 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 410                                   struct rte_eth_dev_info *dev_info)
 411 {
 412         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 413         uint16_t max_vnics, i, j, vpool, vrxq;
 414         unsigned int max_rx_rings;
 415
 416         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 417
 418         /* MAC Specifics */
 419         dev_info->max_mac_addrs = MAX_NUM_MAC_ADDR;
 420         dev_info->max_hash_mac_addrs = 0;
 421
 422         /* PF/VF specifics */
 423         if (BNXT_PF(bp))
 424                 dev_info->max_vfs = bp->pdev->max_vfs;
 425         max_rx_rings = RTE_MIN(bp->max_vnics, RTE_MIN(bp->max_l2_ctx,
 426                                                 RTE_MIN(bp->max_rsscos_ctx,
 427                                                 bp->max_stat_ctx)));
 428         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 429         dev_info->max_rx_queues = max_rx_rings;
 430         dev_info->max_tx_queues = max_rx_rings;
 431         dev_info->reta_size = bp->max_rsscos_ctx;
 432         dev_info->hash_key_size = 40;
 433         max_vnics = bp->max_vnics;
 434
 435         /* Fast path specifics */
 436         dev_info->min_rx_bufsize = 1;
 437         dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
 438                                   + VLAN_TAG_SIZE;
 439         dev_info->rx_offload_capa = 0;
 440         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
 441                                         DEV_TX_OFFLOAD_TCP_CKSUM |
 442                                         DEV_TX_OFFLOAD_UDP_CKSUM |
 443                                         DEV_TX_OFFLOAD_TCP_TSO |
 444                                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 445                                         DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 446                                         DEV_TX_OFFLOAD_GRE_TNL_TSO |
 447                                         DEV_TX_OFFLOAD_IPIP_TNL_TSO |
 448                                         DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
 449
 450         /* *INDENT-OFF* */
 451         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 452                 .rx_thresh = {
 453                         .pthresh = 8,
 454                         .hthresh = 8,
 455                         .wthresh = 0,
 456                 },
 457                 .rx_free_thresh = 32,
 458                 .rx_drop_en = 0,
 459         };
 460
 461         dev_info->default_txconf = (struct rte_eth_txconf) {
 462                 .tx_thresh = {
 463                         .pthresh = 32,
 464                         .hthresh = 0,
 465                         .wthresh = 0,
 466                 },
 467                 .tx_free_thresh = 32,
 468                 .tx_rs_thresh = 32,
 469                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
 470                              ETH_TXQ_FLAGS_NOOFFLOADS,
 471         };
 472         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 473
 474         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 475
 476         /* *INDENT-ON* */
 477
 478         /*
 479          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 480          *       need further investigation.
 481          */
 482
 483         /* VMDq resources */
 484         vpool = 64; /* ETH_64_POOLS */
 485         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 486         for (i = 0; i < 4; vpool >>= 1, i++) {
 487                 if (max_vnics > vpool) {
 488                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 489                                 if (dev_info->max_rx_queues > vrxq) {
 490                                         if (vpool > vrxq)
 491                                                 vpool = vrxq;
 492                                         goto found;
 493                                 }
 494                         }
 495                         /* Not enough resources to support VMDq */
 496                         break;
 497                 }
 498         }
 499         /* Not enough resources to support VMDq */
 500         vpool = 0;
 501         vrxq = 0;
 502 found:
 503         dev_info->max_vmdq_pools = vpool;
 504         dev_info->vmdq_queue_num = vrxq;
 505
 506         dev_info->vmdq_pool_base = 0;
 507         dev_info->vmdq_queue_base = 0;
 508 }
 509
 510 /* Configure the device based on the configuration provided */
 511 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 512 {
 513         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 514
 515         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 516         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 517
 518         /* Inherit new configurations */
 519         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 520         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 521         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 522         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 523
 524         if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
 525                 eth_dev->data->mtu =
 526                                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 527                                 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
 528         return 0;
 529 }
 530
 531 static inline int
 532 rte_bnxt_atomic_write_link_status(struct rte_eth_dev *eth_dev,
 533                                 struct rte_eth_link *link)
 534 {
 535         struct rte_eth_link *dst = &eth_dev->data->dev_link;
 536         struct rte_eth_link *src = link;
 537
 538         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 539                                         *(uint64_t *)src) == 0)
 540                 return 1;
 541
 542         return 0;
 543 }
 544
 545 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 546 {
 547         struct rte_eth_link *link = &eth_dev->data->dev_link;
 548
 549         if (link->link_status)
 550                 RTE_LOG(INFO, PMD, "Port %d Link Up - speed %u Mbps - %s\n",
 551                         (uint8_t)(eth_dev->data->port_id),
 552                         (uint32_t)link->link_speed,
 553                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 554                         ("full-duplex") : ("half-duplex\n"));
 555         else
 556                 RTE_LOG(INFO, PMD, "Port %d Link Down\n",
 557                         (uint8_t)(eth_dev->data->port_id));
 558 }
 559
 560 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
 561 {
 562         bnxt_print_link_info(eth_dev);
 563         return 0;
 564 }
 565
 566 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 567 {
 568         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 569         int vlan_mask = 0;
 570         int rc;
 571
 572         bp->dev_stopped = 0;
 573
 574         rc = bnxt_init_nic(bp);
 575         if (rc)
 576                 goto error;
 577
 578         bnxt_link_update_op(eth_dev, 0);
 579
 580         if (eth_dev->data->dev_conf.rxmode.hw_vlan_filter)
 581                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 582         if (eth_dev->data->dev_conf.rxmode.hw_vlan_strip)
 583                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 584         bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 585
 586         return 0;
 587
 588 error:
 589         bnxt_shutdown_nic(bp);
 590         bnxt_free_tx_mbufs(bp);
 591         bnxt_free_rx_mbufs(bp);
 592         return rc;
 593 }
 594
 595 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 596 {
 597         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 598
 599         eth_dev->data->dev_link.link_status = 1;
 600         bnxt_set_hwrm_link_config(bp, true);
 601         return 0;
 602 }
 603
 604 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 605 {
 606         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 607
 608         eth_dev->data->dev_link.link_status = 0;
 609         bnxt_set_hwrm_link_config(bp, false);
 610         return 0;
 611 }
 612
 613 /* Unload the driver, release resources */
 614 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 615 {
 616         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 617
 618         if (bp->eth_dev->data->dev_started) {
 619                 /* TBD: STOP HW queues DMA */
 620                 eth_dev->data->dev_link.link_status = 0;
 621         }
 622         bnxt_set_hwrm_link_config(bp, false);
 623         bnxt_hwrm_port_clr_stats(bp);
 624         bnxt_shutdown_nic(bp);
 625         bp->dev_stopped = 1;
 626 }
 627
 628 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 629 {
 630         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 631
 632         if (bp->dev_stopped == 0)
 633                 bnxt_dev_stop_op(eth_dev);
 634
 635         bnxt_free_tx_mbufs(bp);
 636         bnxt_free_rx_mbufs(bp);
 637         bnxt_free_mem(bp);
 638         if (eth_dev->data->mac_addrs != NULL) {
 639                 rte_free(eth_dev->data->mac_addrs);
 640                 eth_dev->data->mac_addrs = NULL;
 641         }
 642         if (bp->grp_info != NULL) {
 643                 rte_free(bp->grp_info);
 644                 bp->grp_info = NULL;
 645         }
 646 }
 647
 648 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 649                                     uint32_t index)
 650 {
 651         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 652         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 653         struct bnxt_vnic_info *vnic;
 654         struct bnxt_filter_info *filter, *temp_filter;
 655         int i;
 656
 657         /*
 658          * Loop through all VNICs from the specified filter flow pools to
 659          * remove the corresponding MAC addr filter
 660          */
 661         for (i = 0; i < MAX_FF_POOLS; i++) {
 662                 if (!(pool_mask & (1ULL << i)))
 663                         continue;
 664
 665                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 666                         filter = STAILQ_FIRST(&vnic->filter);
 667                         while (filter) {
 668                                 temp_filter = STAILQ_NEXT(filter, next);
 669                                 if (filter->mac_index == index) {
 670                                         STAILQ_REMOVE(&vnic->filter, filter,
 671                                                       bnxt_filter_info, next);
 672                                         bnxt_hwrm_clear_l2_filter(bp, filter);
 673                                         filter->mac_index = INVALID_MAC_INDEX;
 674                                         memset(&filter->l2_addr, 0,
 675                                                ETHER_ADDR_LEN);
 676                                         STAILQ_INSERT_TAIL(
 677                                                         &bp->free_filter_list,
 678                                                         filter, next);
 679                                 }
 680                                 filter = temp_filter;
 681                         }
 682                 }
 683         }
 684 }
 685
 686 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 687                                 struct ether_addr *mac_addr,
 688                                 uint32_t index, uint32_t pool)
 689 {
 690         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 691         struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
 692         struct bnxt_filter_info *filter;
 693
 694         if (BNXT_VF(bp)) {
 695                 RTE_LOG(ERR, PMD, "Cannot add MAC address to a VF interface\n");
 696                 return -ENOTSUP;
 697         }
 698
 699         if (!vnic) {
 700                 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
 701                 return -EINVAL;
 702         }
 703         /* Attach requested MAC address to the new l2_filter */
 704         STAILQ_FOREACH(filter, &vnic->filter, next) {
 705                 if (filter->mac_index == index) {
 706                         RTE_LOG(ERR, PMD,
 707                                 "MAC addr already existed for pool %d\n", pool);
 708                         return -EINVAL;
 709                 }
 710         }
 711         filter = bnxt_alloc_filter(bp);
 712         if (!filter) {
 713                 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
 714                 return -ENODEV;
 715         }
 716         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 717         filter->mac_index = index;
 718         memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
 719         return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 720 }
 721
 722 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 723 {
 724         int rc = 0;
 725         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 726         struct rte_eth_link new;
 727         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 728
 729         memset(&new, 0, sizeof(new));
 730         do {
 731                 /* Retrieve link info from hardware */
 732                 rc = bnxt_get_hwrm_link_config(bp, &new);
 733                 if (rc) {
 734                         new.link_speed = ETH_LINK_SPEED_100M;
 735                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 736                         RTE_LOG(ERR, PMD,
 737                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 738                         goto out;
 739                 }
 740                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 741
 742                 if (!wait_to_complete)
 743                         break;
 744         } while (!new.link_status && cnt--);
 745
 746 out:
 747         /* Timed out or success */
 748         if (new.link_status != eth_dev->data->dev_link.link_status ||
 749         new.link_speed != eth_dev->data->dev_link.link_speed) {
 750                 rte_bnxt_atomic_write_link_status(eth_dev, &new);
 751                 bnxt_print_link_info(eth_dev);
 752         }
 753
 754         return rc;
 755 }
 756
 757 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
 758 {
 759         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 760         struct bnxt_vnic_info *vnic;
 761
 762         if (bp->vnic_info == NULL)
 763                 return;
 764
 765         vnic = &bp->vnic_info[0];
 766
 767         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
 768         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 769 }
 770
 771 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
 772 {
 773         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 774         struct bnxt_vnic_info *vnic;
 775
 776         if (bp->vnic_info == NULL)
 777                 return;
 778
 779         vnic = &bp->vnic_info[0];
 780
 781         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
 782         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 783 }
 784
 785 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
 786 {
 787         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 788         struct bnxt_vnic_info *vnic;
 789
 790         if (bp->vnic_info == NULL)
 791                 return;
 792
 793         vnic = &bp->vnic_info[0];
 794
 795         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
 796         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 797 }
 798
 799 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
 800 {
 801         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 802         struct bnxt_vnic_info *vnic;
 803
 804         if (bp->vnic_info == NULL)
 805                 return;
 806
 807         vnic = &bp->vnic_info[0];
 808
 809         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
 810         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 811 }
 812
 813 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
 814                             struct rte_eth_rss_reta_entry64 *reta_conf,
 815                             uint16_t reta_size)
 816 {
 817         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 818         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 819         struct bnxt_vnic_info *vnic;
 820         int i;
 821
 822         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
 823                 return -EINVAL;
 824
 825         if (reta_size != HW_HASH_INDEX_SIZE) {
 826                 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
 827                         "(%d) must equal the size supported by the hardware "
 828                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 829                 return -EINVAL;
 830         }
 831         /* Update the RSS VNIC(s) */
 832         for (i = 0; i < MAX_FF_POOLS; i++) {
 833                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 834                         memcpy(vnic->rss_table, reta_conf, reta_size);
 835
 836                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 837                 }
 838         }
 839         return 0;
 840 }
 841
 842 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
 843                               struct rte_eth_rss_reta_entry64 *reta_conf,
 844                               uint16_t reta_size)
 845 {
 846         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 847         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 848         struct rte_intr_handle *intr_handle
 849                 = &bp->pdev->intr_handle;
 850
 851         /* Retrieve from the default VNIC */
 852         if (!vnic)
 853                 return -EINVAL;
 854         if (!vnic->rss_table)
 855                 return -EINVAL;
 856
 857         if (reta_size != HW_HASH_INDEX_SIZE) {
 858                 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
 859                         "(%d) must equal the size supported by the hardware "
 860                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 861                 return -EINVAL;
 862         }
 863         /* EW - need to revisit here copying from u64 to u16 */
 864         memcpy(reta_conf, vnic->rss_table, reta_size);
 865
 866         if (rte_intr_allow_others(intr_handle)) {
 867                 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
 868                         bnxt_dev_lsc_intr_setup(eth_dev);
 869         }
 870
 871         return 0;
 872 }
 873
 874 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
 875                                    struct rte_eth_rss_conf *rss_conf)
 876 {
 877         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 878         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 879         struct bnxt_vnic_info *vnic;
 880         uint16_t hash_type = 0;
 881         int i;
 882
 883         /*
 884          * If RSS enablement were different than dev_configure,
 885          * then return -EINVAL
 886          */
 887         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
 888                 if (!rss_conf->rss_hf)
 889                         RTE_LOG(ERR, PMD, "Hash type NONE\n");
 890         } else {
 891                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
 892                         return -EINVAL;
 893         }
 894
 895         bp->flags |= BNXT_FLAG_UPDATE_HASH;
 896         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
 897
 898         if (rss_conf->rss_hf & ETH_RSS_IPV4)
 899                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 900         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
 901                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 902         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
 903                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
 904         if (rss_conf->rss_hf & ETH_RSS_IPV6)
 905                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
 906         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
 907                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
 908         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
 909                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
 910
 911         /* Update the RSS VNIC(s) */
 912         for (i = 0; i < MAX_FF_POOLS; i++) {
 913                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 914                         vnic->hash_type = hash_type;
 915
 916                         /*
 917                          * Use the supplied key if the key length is
 918                          * acceptable and the rss_key is not NULL
 919                          */
 920                         if (rss_conf->rss_key &&
 921                             rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
 922                                 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
 923                                        rss_conf->rss_key_len);
 924
 925                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 926                 }
 927         }
 928         return 0;
 929 }
 930
 931 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
 932                                      struct rte_eth_rss_conf *rss_conf)
 933 {
 934         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 935         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 936         int len;
 937         uint32_t hash_types;
 938
 939         /* RSS configuration is the same for all VNICs */
 940         if (vnic && vnic->rss_hash_key) {
 941                 if (rss_conf->rss_key) {
 942                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
 943                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
 944                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
 945                 }
 946
 947                 hash_types = vnic->hash_type;
 948                 rss_conf->rss_hf = 0;
 949                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
 950                         rss_conf->rss_hf |= ETH_RSS_IPV4;
 951                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 952                 }
 953                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
 954                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
 955                         hash_types &=
 956                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 957                 }
 958                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
 959                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
 960                         hash_types &=
 961                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
 962                 }
 963                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
 964                         rss_conf->rss_hf |= ETH_RSS_IPV6;
 965                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
 966                 }
 967                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
 968                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
 969                         hash_types &=
 970                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
 971                 }
 972                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
 973                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
 974                         hash_types &=
 975                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
 976                 }
 977                 if (hash_types) {
 978                         RTE_LOG(ERR, PMD,
 979                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
 980                                 vnic->hash_type);
 981                         return -ENOTSUP;
 982                 }
 983         } else {
 984                 rss_conf->rss_hf = 0;
 985         }
 986         return 0;
 987 }
 988
 989 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
 990                                struct rte_eth_fc_conf *fc_conf)
 991 {
 992         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
 993         struct rte_eth_link link_info;
 994         int rc;
 995
 996         rc = bnxt_get_hwrm_link_config(bp, &link_info);
 997         if (rc)
 998                 return rc;
 999
1000         memset(fc_conf, 0, sizeof(*fc_conf));
1001         if (bp->link_info.auto_pause)
1002                 fc_conf->autoneg = 1;
1003         switch (bp->link_info.pause) {
1004         case 0:
1005                 fc_conf->mode = RTE_FC_NONE;
1006                 break;
1007         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1008                 fc_conf->mode = RTE_FC_TX_PAUSE;
1009                 break;
1010         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1011                 fc_conf->mode = RTE_FC_RX_PAUSE;
1012                 break;
1013         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1014                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1015                 fc_conf->mode = RTE_FC_FULL;
1016                 break;
1017         }
1018         return 0;
1019 }
1020
1021 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1022                                struct rte_eth_fc_conf *fc_conf)
1023 {
1024         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1025
1026         if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
1027                 RTE_LOG(ERR, PMD, "Flow Control Settings cannot be modified\n");
1028                 return -ENOTSUP;
1029         }
1030
1031         switch (fc_conf->mode) {
1032         case RTE_FC_NONE:
1033                 bp->link_info.auto_pause = 0;
1034                 bp->link_info.force_pause = 0;
1035                 break;
1036         case RTE_FC_RX_PAUSE:
1037                 if (fc_conf->autoneg) {
1038                         bp->link_info.auto_pause =
1039                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1040                         bp->link_info.force_pause = 0;
1041                 } else {
1042                         bp->link_info.auto_pause = 0;
1043                         bp->link_info.force_pause =
1044                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1045                 }
1046                 break;
1047         case RTE_FC_TX_PAUSE:
1048                 if (fc_conf->autoneg) {
1049                         bp->link_info.auto_pause =
1050                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1051                         bp->link_info.force_pause = 0;
1052                 } else {
1053                         bp->link_info.auto_pause = 0;
1054                         bp->link_info.force_pause =
1055                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1056                 }
1057                 break;
1058         case RTE_FC_FULL:
1059                 if (fc_conf->autoneg) {
1060                         bp->link_info.auto_pause =
1061                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1062                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1063                         bp->link_info.force_pause = 0;
1064                 } else {
1065                         bp->link_info.auto_pause = 0;
1066                         bp->link_info.force_pause =
1067                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1068                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1069                 }
1070                 break;
1071         }
1072         return bnxt_set_hwrm_link_config(bp, true);
1073 }
1074
1075 /* Add UDP tunneling port */
1076 static int
1077 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1078                          struct rte_eth_udp_tunnel *udp_tunnel)
1079 {
1080         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1081         uint16_t tunnel_type = 0;
1082         int rc = 0;
1083
1084         switch (udp_tunnel->prot_type) {
1085         case RTE_TUNNEL_TYPE_VXLAN:
1086                 if (bp->vxlan_port_cnt) {
1087                         RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n",
1088                                 udp_tunnel->udp_port);
1089                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1090                                 RTE_LOG(ERR, PMD, "Only one port allowed\n");
1091                                 return -ENOSPC;
1092                         }
1093                         bp->vxlan_port_cnt++;
1094                         return 0;
1095                 }
1096                 tunnel_type =
1097                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1098                 bp->vxlan_port_cnt++;
1099                 break;
1100         case RTE_TUNNEL_TYPE_GENEVE:
1101                 if (bp->geneve_port_cnt) {
1102                         RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n",
1103                                 udp_tunnel->udp_port);
1104                         if (bp->geneve_port != udp_tunnel->udp_port) {
1105                                 RTE_LOG(ERR, PMD, "Only one port allowed\n");
1106                                 return -ENOSPC;
1107                         }
1108                         bp->geneve_port_cnt++;
1109                         return 0;
1110                 }
1111                 tunnel_type =
1112                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1113                 bp->geneve_port_cnt++;
1114                 break;
1115         default:
1116                 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n");
1117                 return -ENOTSUP;
1118         }
1119         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1120                                              tunnel_type);
1121         return rc;
1122 }
1123
1124 static int
1125 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1126                          struct rte_eth_udp_tunnel *udp_tunnel)
1127 {
1128         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1129         uint16_t tunnel_type = 0;
1130         uint16_t port = 0;
1131         int rc = 0;
1132
1133         switch (udp_tunnel->prot_type) {
1134         case RTE_TUNNEL_TYPE_VXLAN:
1135                 if (!bp->vxlan_port_cnt) {
1136                         RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n");
1137                         return -EINVAL;
1138                 }
1139                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1140                         RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n",
1141                                 udp_tunnel->udp_port, bp->vxlan_port);
1142                         return -EINVAL;
1143                 }
1144                 if (--bp->vxlan_port_cnt)
1145                         return 0;
1146
1147                 tunnel_type =
1148                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1149                 port = bp->vxlan_fw_dst_port_id;
1150                 break;
1151         case RTE_TUNNEL_TYPE_GENEVE:
1152                 if (!bp->geneve_port_cnt) {
1153                         RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n");
1154                         return -EINVAL;
1155                 }
1156                 if (bp->geneve_port != udp_tunnel->udp_port) {
1157                         RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n",
1158                                 udp_tunnel->udp_port, bp->geneve_port);
1159                         return -EINVAL;
1160                 }
1161                 if (--bp->geneve_port_cnt)
1162                         return 0;
1163
1164                 tunnel_type =
1165                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1166                 port = bp->geneve_fw_dst_port_id;
1167                 break;
1168         default:
1169                 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n");
1170                 return -ENOTSUP;
1171         }
1172
1173         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1174         if (!rc) {
1175                 if (tunnel_type ==
1176                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1177                         bp->vxlan_port = 0;
1178                 if (tunnel_type ==
1179                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1180                         bp->geneve_port = 0;
1181         }
1182         return rc;
1183 }
1184
1185 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1186 {
1187         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1188         struct bnxt_vnic_info *vnic;
1189         unsigned int i;
1190         int rc = 0;
1191         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1192
1193         /* Cycle through all VNICs */
1194         for (i = 0; i < bp->nr_vnics; i++) {
1195                 /*
1196                  * For each VNIC and each associated filter(s)
1197                  * if VLAN exists && VLAN matches vlan_id
1198                  *      remove the MAC+VLAN filter
1199                  *      add a new MAC only filter
1200                  * else
1201                  *      VLAN filter doesn't exist, just skip and continue
1202                  */
1203                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1204                         filter = STAILQ_FIRST(&vnic->filter);
1205                         while (filter) {
1206                                 temp_filter = STAILQ_NEXT(filter, next);
1207
1208                                 if (filter->enables & chk &&
1209                                     filter->l2_ovlan == vlan_id) {
1210                                         /* Must delete the filter */
1211                                         STAILQ_REMOVE(&vnic->filter, filter,
1212                                                       bnxt_filter_info, next);
1213                                         bnxt_hwrm_clear_l2_filter(bp, filter);
1214                                         STAILQ_INSERT_TAIL(
1215                                                         &bp->free_filter_list,
1216                                                         filter, next);
1217
1218                                         /*
1219                                          * Need to examine to see if the MAC
1220                                          * filter already existed or not before
1221                                          * allocating a new one
1222                                          */
1223
1224                                         new_filter = bnxt_alloc_filter(bp);
1225                                         if (!new_filter) {
1226                                                 RTE_LOG(ERR, PMD,
1227                                                         "MAC/VLAN filter alloc failed\n");
1228                                                 rc = -ENOMEM;
1229                                                 goto exit;
1230                                         }
1231                                         STAILQ_INSERT_TAIL(&vnic->filter,
1232                                                            new_filter, next);
1233                                         /* Inherit MAC from previous filter */
1234                                         new_filter->mac_index =
1235                                                         filter->mac_index;
1236                                         memcpy(new_filter->l2_addr,
1237                                                filter->l2_addr, ETHER_ADDR_LEN);
1238                                         /* MAC only filter */
1239                                         rc = bnxt_hwrm_set_l2_filter(bp,
1240                                                         vnic->fw_vnic_id,
1241                                                         new_filter);
1242                                         if (rc)
1243                                                 goto exit;
1244                                         RTE_LOG(INFO, PMD,
1245                                                 "Del Vlan filter for %d\n",
1246                                                 vlan_id);
1247                                 }
1248                                 filter = temp_filter;
1249                         }
1250                 }
1251         }
1252 exit:
1253         return rc;
1254 }
1255
1256 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1257 {
1258         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1259         struct bnxt_vnic_info *vnic;
1260         unsigned int i;
1261         int rc = 0;
1262         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1263                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1264         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1265
1266         /* Cycle through all VNICs */
1267         for (i = 0; i < bp->nr_vnics; i++) {
1268                 /*
1269                  * For each VNIC and each associated filter(s)
1270                  * if VLAN exists:
1271                  *   if VLAN matches vlan_id
1272                  *      VLAN filter already exists, just skip and continue
1273                  *   else
1274                  *      add a new MAC+VLAN filter
1275                  * else
1276                  *   Remove the old MAC only filter
1277                  *    Add a new MAC+VLAN filter
1278                  */
1279                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1280                         filter = STAILQ_FIRST(&vnic->filter);
1281                         while (filter) {
1282                                 temp_filter = STAILQ_NEXT(filter, next);
1283
1284                                 if (filter->enables & chk) {
1285                                         if (filter->l2_ovlan == vlan_id)
1286                                                 goto cont;
1287                                 } else {
1288                                         /* Must delete the MAC filter */
1289                                         STAILQ_REMOVE(&vnic->filter, filter,
1290                                                       bnxt_filter_info, next);
1291                                         bnxt_hwrm_clear_l2_filter(bp, filter);
1292                                         filter->l2_ovlan = 0;
1293                                         STAILQ_INSERT_TAIL(
1294                                                         &bp->free_filter_list,
1295                                                         filter, next);
1296                                 }
1297                                 new_filter = bnxt_alloc_filter(bp);
1298                                 if (!new_filter) {
1299                                         RTE_LOG(ERR, PMD,
1300                                                 "MAC/VLAN filter alloc failed\n");
1301                                         rc = -ENOMEM;
1302                                         goto exit;
1303                                 }
1304                                 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1305                                                    next);
1306                                 /* Inherit MAC from the previous filter */
1307                                 new_filter->mac_index = filter->mac_index;
1308                                 memcpy(new_filter->l2_addr, filter->l2_addr,
1309                                        ETHER_ADDR_LEN);
1310                                 /* MAC + VLAN ID filter */
1311                                 new_filter->l2_ovlan = vlan_id;
1312                                 new_filter->l2_ovlan_mask = 0xF000;
1313                                 new_filter->enables |= en;
1314                                 rc = bnxt_hwrm_set_l2_filter(bp,
1315                                                              vnic->fw_vnic_id,
1316                                                              new_filter);
1317                                 if (rc)
1318                                         goto exit;
1319                                 RTE_LOG(INFO, PMD,
1320                                         "Added Vlan filter for %d\n", vlan_id);
1321 cont:
1322                                 filter = temp_filter;
1323                         }
1324                 }
1325         }
1326 exit:
1327         return rc;
1328 }
1329
1330 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1331                                    uint16_t vlan_id, int on)
1332 {
1333         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1334
1335         /* These operations apply to ALL existing MAC/VLAN filters */
1336         if (on)
1337                 return bnxt_add_vlan_filter(bp, vlan_id);
1338         else
1339                 return bnxt_del_vlan_filter(bp, vlan_id);
1340 }
1341
1342 static void
1343 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1344 {
1345         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1346         unsigned int i;
1347
1348         if (mask & ETH_VLAN_FILTER_MASK) {
1349                 if (!dev->data->dev_conf.rxmode.hw_vlan_filter) {
1350                         /* Remove any VLAN filters programmed */
1351                         for (i = 0; i < 4095; i++)
1352                                 bnxt_del_vlan_filter(bp, i);
1353                 }
1354                 RTE_LOG(INFO, PMD, "VLAN Filtering: %d\n",
1355                         dev->data->dev_conf.rxmode.hw_vlan_filter);
1356         }
1357
1358         if (mask & ETH_VLAN_STRIP_MASK) {
1359                 /* Enable or disable VLAN stripping */
1360                 for (i = 0; i < bp->nr_vnics; i++) {
1361                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1362                         if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1363                                 vnic->vlan_strip = true;
1364                         else
1365                                 vnic->vlan_strip = false;
1366                         bnxt_hwrm_vnic_cfg(bp, vnic);
1367                 }
1368                 RTE_LOG(INFO, PMD, "VLAN Strip Offload: %d\n",
1369                         dev->data->dev_conf.rxmode.hw_vlan_strip);
1370         }
1371
1372         if (mask & ETH_VLAN_EXTEND_MASK)
1373                 RTE_LOG(ERR, PMD, "Extend VLAN Not supported\n");
1374 }
1375
1376 static void
1377 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1378 {
1379         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1380         /* Default Filter is tied to VNIC 0 */
1381         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1382         struct bnxt_filter_info *filter;
1383         int rc;
1384
1385         if (BNXT_VF(bp))
1386                 return;
1387
1388         memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1389         memcpy(&dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1390
1391         STAILQ_FOREACH(filter, &vnic->filter, next) {
1392                 /* Default Filter is at Index 0 */
1393                 if (filter->mac_index != 0)
1394                         continue;
1395                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1396                 if (rc)
1397                         break;
1398                 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1399                 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1400                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1401                 filter->enables |=
1402                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1403                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1404                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1405                 if (rc)
1406                         break;
1407                 filter->mac_index = 0;
1408                 RTE_LOG(DEBUG, PMD, "Set MAC addr\n");
1409         }
1410 }
1411
1412 static int
1413 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1414                           struct ether_addr *mc_addr_set,
1415                           uint32_t nb_mc_addr)
1416 {
1417         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1418         char *mc_addr_list = (char *)mc_addr_set;
1419         struct bnxt_vnic_info *vnic;
1420         uint32_t off = 0, i = 0;
1421
1422         vnic = &bp->vnic_info[0];
1423
1424         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1425                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1426                 goto allmulti;
1427         }
1428
1429         /* TODO Check for Duplicate mcast addresses */
1430         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1431         for (i = 0; i < nb_mc_addr; i++) {
1432                 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1433                 off += ETHER_ADDR_LEN;
1434         }
1435
1436         vnic->mc_addr_cnt = i;
1437
1438 allmulti:
1439         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1440 }
1441
1442 static int
1443 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1444 {
1445         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1446         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1447         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1448         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1449         int ret;
1450
1451         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1452                         fw_major, fw_minor, fw_updt);
1453
1454         ret += 1; /* add the size of '\0' */
1455         if (fw_size < (uint32_t)ret)
1456                 return ret;
1457         else
1458                 return 0;
1459 }
1460
1461 static void
1462 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1463         struct rte_eth_rxq_info *qinfo)
1464 {
1465         struct bnxt_rx_queue *rxq;
1466
1467         rxq = dev->data->rx_queues[queue_id];
1468
1469         qinfo->mp = rxq->mb_pool;
1470         qinfo->scattered_rx = dev->data->scattered_rx;
1471         qinfo->nb_desc = rxq->nb_rx_desc;
1472
1473         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1474         qinfo->conf.rx_drop_en = 0;
1475         qinfo->conf.rx_deferred_start = 0;
1476 }
1477
1478 static void
1479 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1480         struct rte_eth_txq_info *qinfo)
1481 {
1482         struct bnxt_tx_queue *txq;
1483
1484         txq = dev->data->tx_queues[queue_id];
1485
1486         qinfo->nb_desc = txq->nb_tx_desc;
1487
1488         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1489         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1490         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1491
1492         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1493         qinfo->conf.tx_rs_thresh = 0;
1494         qinfo->conf.txq_flags = txq->txq_flags;
1495         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1496 }
1497
1498 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1499 {
1500         struct bnxt *bp = eth_dev->data->dev_private;
1501         struct rte_eth_dev_info dev_info;
1502         uint32_t max_dev_mtu;
1503         uint32_t rc = 0;
1504         uint32_t i;
1505
1506         bnxt_dev_info_get_op(eth_dev, &dev_info);
1507         max_dev_mtu = dev_info.max_rx_pktlen -
1508                       ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1509
1510         if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1511                 RTE_LOG(ERR, PMD, "MTU requested must be within (%d, %d)\n",
1512                         ETHER_MIN_MTU, max_dev_mtu);
1513                 return -EINVAL;
1514         }
1515
1516
1517         if (new_mtu > ETHER_MTU) {
1518                 bp->flags |= BNXT_FLAG_JUMBO;
1519                 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
1520         } else {
1521                 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
1522                 bp->flags &= ~BNXT_FLAG_JUMBO;
1523         }
1524
1525         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1526                 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1527
1528         eth_dev->data->mtu = new_mtu;
1529         RTE_LOG(INFO, PMD, "New MTU is %d\n", eth_dev->data->mtu);
1530
1531         for (i = 0; i < bp->nr_vnics; i++) {
1532                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1533
1534                 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1535                                         ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1536                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1537                 if (rc)
1538                         break;
1539
1540                 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1541                 if (rc)
1542                         return rc;
1543         }
1544
1545         return rc;
1546 }
1547
1548 static int
1549 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1550 {
1551         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1552         uint16_t vlan = bp->vlan;
1553         int rc;
1554
1555         if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
1556                 RTE_LOG(ERR, PMD,
1557                         "PVID cannot be modified for this function\n");
1558                 return -ENOTSUP;
1559         }
1560         bp->vlan = on ? pvid : 0;
1561
1562         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1563         if (rc)
1564                 bp->vlan = vlan;
1565         return rc;
1566 }
1567
1568 static int
1569 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1570 {
1571         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1572
1573         return bnxt_hwrm_port_led_cfg(bp, true);
1574 }
1575
1576 static int
1577 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1578 {
1579         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1580
1581         return bnxt_hwrm_port_led_cfg(bp, false);
1582 }
1583
1584 static uint32_t
1585 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1586 {
1587         uint32_t desc = 0, raw_cons = 0, cons;
1588         struct bnxt_cp_ring_info *cpr;
1589         struct bnxt_rx_queue *rxq;
1590         struct rx_pkt_cmpl *rxcmp;
1591         uint16_t cmp_type;
1592         uint8_t cmp = 1;
1593         bool valid;
1594
1595         rxq = dev->data->rx_queues[rx_queue_id];
1596         cpr = rxq->cp_ring;
1597         valid = cpr->valid;
1598
1599         while (raw_cons < rxq->nb_rx_desc) {
1600                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1601                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1602
1603                 if (!CMPL_VALID(rxcmp, valid))
1604                         goto nothing_to_do;
1605                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1606                 cmp_type = CMP_TYPE(rxcmp);
1607                 if (cmp_type == RX_PKT_CMPL_TYPE_RX_L2_TPA_END) {
1608                         cmp = (rte_le_to_cpu_32(
1609                                         ((struct rx_tpa_end_cmpl *)
1610                                          (rxcmp))->agg_bufs_v1) &
1611                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1612                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1613                         desc++;
1614                 } else if (cmp_type == 0x11) {
1615                         desc++;
1616                         cmp = (rxcmp->agg_bufs_v1 &
1617                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1618                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1619                 } else {
1620                         cmp = 1;
1621                 }
1622 nothing_to_do:
1623                 raw_cons += cmp ? cmp : 2;
1624         }
1625
1626         return desc;
1627 }
1628
1629 static int
1630 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1631 {
1632         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1633         struct bnxt_rx_ring_info *rxr;
1634         struct bnxt_cp_ring_info *cpr;
1635         struct bnxt_sw_rx_bd *rx_buf;
1636         struct rx_pkt_cmpl *rxcmp;
1637         uint32_t cons, cp_cons;
1638
1639         if (!rxq)
1640                 return -EINVAL;
1641
1642         cpr = rxq->cp_ring;
1643         rxr = rxq->rx_ring;
1644
1645         if (offset >= rxq->nb_rx_desc)
1646                 return -EINVAL;
1647
1648         cons = RING_CMP(cpr->cp_ring_struct, offset);
1649         cp_cons = cpr->cp_raw_cons;
1650         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1651
1652         if (cons > cp_cons) {
1653                 if (CMPL_VALID(rxcmp, cpr->valid))
1654                         return RTE_ETH_RX_DESC_DONE;
1655         } else {
1656                 if (CMPL_VALID(rxcmp, !cpr->valid))
1657                         return RTE_ETH_RX_DESC_DONE;
1658         }
1659         rx_buf = &rxr->rx_buf_ring[cons];
1660         if (rx_buf->mbuf == NULL)
1661                 return RTE_ETH_RX_DESC_UNAVAIL;
1662
1663
1664         return RTE_ETH_RX_DESC_AVAIL;
1665 }
1666
1667 static int
1668 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1669 {
1670         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1671         struct bnxt_tx_ring_info *txr;
1672         struct bnxt_cp_ring_info *cpr;
1673         struct bnxt_sw_tx_bd *tx_buf;
1674         struct tx_pkt_cmpl *txcmp;
1675         uint32_t cons, cp_cons;
1676
1677         if (!txq)
1678                 return -EINVAL;
1679
1680         cpr = txq->cp_ring;
1681         txr = txq->tx_ring;
1682
1683         if (offset >= txq->nb_tx_desc)
1684                 return -EINVAL;
1685
1686         cons = RING_CMP(cpr->cp_ring_struct, offset);
1687         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1688         cp_cons = cpr->cp_raw_cons;
1689
1690         if (cons > cp_cons) {
1691                 if (CMPL_VALID(txcmp, cpr->valid))
1692                         return RTE_ETH_TX_DESC_UNAVAIL;
1693         } else {
1694                 if (CMPL_VALID(txcmp, !cpr->valid))
1695                         return RTE_ETH_TX_DESC_UNAVAIL;
1696         }
1697         tx_buf = &txr->tx_buf_ring[cons];
1698         if (tx_buf->mbuf == NULL)
1699                 return RTE_ETH_TX_DESC_DONE;
1700
1701         return RTE_ETH_TX_DESC_FULL;
1702 }
1703
1704 static struct bnxt_filter_info *
1705 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1706                                 struct rte_eth_ethertype_filter *efilter,
1707                                 struct bnxt_vnic_info *vnic0,
1708                                 struct bnxt_vnic_info *vnic,
1709                                 int *ret)
1710 {
1711         struct bnxt_filter_info *mfilter = NULL;
1712         int match = 0;
1713         *ret = 0;
1714
1715         if (efilter->ether_type != ETHER_TYPE_IPv4 &&
1716                 efilter->ether_type != ETHER_TYPE_IPv6) {
1717                 RTE_LOG(ERR, PMD, "unsupported ether_type(0x%04x) in"
1718                         " ethertype filter.", efilter->ether_type);
1719                 *ret = -EINVAL;
1720         }
1721         if (efilter->queue >= bp->rx_nr_rings) {
1722                 RTE_LOG(ERR, PMD, "Invalid queue %d\n", efilter->queue);
1723                 *ret = -EINVAL;
1724         }
1725
1726         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1727         vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1728         if (vnic == NULL) {
1729                 RTE_LOG(ERR, PMD, "Invalid queue %d\n", efilter->queue);
1730                 *ret = -EINVAL;
1731         }
1732
1733         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1734                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1735                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1736                                      mfilter->l2_addr, ETHER_ADDR_LEN) &&
1737                              mfilter->flags ==
1738                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1739                              mfilter->ethertype == efilter->ether_type)) {
1740                                 match = 1;
1741                                 break;
1742                         }
1743                 }
1744         } else {
1745                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1746                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1747                                      mfilter->l2_addr, ETHER_ADDR_LEN) &&
1748                              mfilter->ethertype == efilter->ether_type &&
1749                              mfilter->flags ==
1750                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1751                                 match = 1;
1752                                 break;
1753                         }
1754         }
1755
1756         if (match)
1757                 *ret = -EEXIST;
1758
1759         return mfilter;
1760 }
1761
1762 static int
1763 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1764                         enum rte_filter_op filter_op,
1765                         void *arg)
1766 {
1767         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1768         struct rte_eth_ethertype_filter *efilter =
1769                         (struct rte_eth_ethertype_filter *)arg;
1770         struct bnxt_filter_info *bfilter, *filter1;
1771         struct bnxt_vnic_info *vnic, *vnic0;
1772         int ret;
1773
1774         if (filter_op == RTE_ETH_FILTER_NOP)
1775                 return 0;
1776
1777         if (arg == NULL) {
1778                 RTE_LOG(ERR, PMD, "arg shouldn't be NULL for operation %u.",
1779                             filter_op);
1780                 return -EINVAL;
1781         }
1782
1783         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1784         vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1785
1786         switch (filter_op) {
1787         case RTE_ETH_FILTER_ADD:
1788                 bnxt_match_and_validate_ether_filter(bp, efilter,
1789                                                         vnic0, vnic, &ret);
1790                 if (ret < 0)
1791                         return ret;
1792
1793                 bfilter = bnxt_get_unused_filter(bp);
1794                 if (bfilter == NULL) {
1795                         RTE_LOG(ERR, PMD,
1796                                 "Not enough resources for a new filter.\n");
1797                         return -ENOMEM;
1798                 }
1799                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1800                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1801                        ETHER_ADDR_LEN);
1802                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1803                        ETHER_ADDR_LEN);
1804                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1805                 bfilter->ethertype = efilter->ether_type;
1806                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1807
1808                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1809                 if (filter1 == NULL) {
1810                         ret = -1;
1811                         goto cleanup;
1812                 }
1813                 bfilter->enables |=
1814                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1815                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1816
1817                 bfilter->dst_id = vnic->fw_vnic_id;
1818
1819                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1820                         bfilter->flags =
1821                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1822                 }
1823
1824                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1825                 if (ret)
1826                         goto cleanup;
1827                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1828                 break;
1829         case RTE_ETH_FILTER_DELETE:
1830                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1831                                                         vnic0, vnic, &ret);
1832                 if (ret == -EEXIST) {
1833                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1834
1835                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1836                                       next);
1837                         bnxt_free_filter(bp, filter1);
1838                 } else if (ret == 0) {
1839                         RTE_LOG(ERR, PMD, "No matching filter found\n");
1840                 }
1841                 break;
1842         default:
1843                 RTE_LOG(ERR, PMD, "unsupported operation %u.", filter_op);
1844                 ret = -EINVAL;
1845                 goto error;
1846         }
1847         return ret;
1848 cleanup:
1849         bnxt_free_filter(bp, bfilter);
1850 error:
1851         return ret;
1852 }
1853
1854 static int
1855 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
1856                     enum rte_filter_type filter_type,
1857                     enum rte_filter_op filter_op, void *arg)
1858 {
1859         int ret = 0;
1860
1861         switch (filter_type) {
1862         case RTE_ETH_FILTER_NTUPLE:
1863         case RTE_ETH_FILTER_FDIR:
1864         case RTE_ETH_FILTER_TUNNEL:
1865                 /* FALLTHROUGH */
1866                 RTE_LOG(ERR, PMD,
1867                         "filter type: %d: To be implemented\n", filter_type);
1868                 break;
1869         case RTE_ETH_FILTER_ETHERTYPE:
1870                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
1871                 break;
1872         case RTE_ETH_FILTER_GENERIC:
1873                 if (filter_op != RTE_ETH_FILTER_GET)
1874                         return -EINVAL;
1875                 *(const void **)arg = &bnxt_flow_ops;
1876                 break;
1877         default:
1878                 RTE_LOG(ERR, PMD,
1879                         "Filter type (%d) not supported", filter_type);
1880                 ret = -EINVAL;
1881                 break;
1882         }
1883         return ret;
1884 }
1885
1886 static const uint32_t *
1887 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
1888 {
1889         static const uint32_t ptypes[] = {
1890                 RTE_PTYPE_L2_ETHER_VLAN,
1891                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1892                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1893                 RTE_PTYPE_L4_ICMP,
1894                 RTE_PTYPE_L4_TCP,
1895                 RTE_PTYPE_L4_UDP,
1896                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1897                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1898                 RTE_PTYPE_INNER_L4_ICMP,
1899                 RTE_PTYPE_INNER_L4_TCP,
1900                 RTE_PTYPE_INNER_L4_UDP,
1901                 RTE_PTYPE_UNKNOWN
1902         };
1903
1904         if (dev->rx_pkt_burst == bnxt_recv_pkts)
1905                 return ptypes;
1906         return NULL;
1907 }
1908
1909
1910
1911 static int
1912 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
1913 {
1914         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1915         int rc;
1916         uint32_t dir_entries;
1917         uint32_t entry_length;
1918
1919         RTE_LOG(INFO, PMD, "%s(): %04x:%02x:%02x:%02x\n",
1920                 __func__, bp->pdev->addr.domain, bp->pdev->addr.bus,
1921                 bp->pdev->addr.devid, bp->pdev->addr.function);
1922
1923         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
1924         if (rc != 0)
1925                 return rc;
1926
1927         return dir_entries * entry_length;
1928 }
1929
1930 static int
1931 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
1932                 struct rte_dev_eeprom_info *in_eeprom)
1933 {
1934         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1935         uint32_t index;
1936         uint32_t offset;
1937
1938         RTE_LOG(INFO, PMD, "%s(): %04x:%02x:%02x:%02x in_eeprom->offset = %d "
1939                 "len = %d\n", __func__, bp->pdev->addr.domain,
1940                 bp->pdev->addr.bus, bp->pdev->addr.devid,
1941                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
1942
1943         if (in_eeprom->offset == 0) /* special offset value to get directory */
1944                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
1945                                                 in_eeprom->data);
1946
1947         index = in_eeprom->offset >> 24;
1948         offset = in_eeprom->offset & 0xffffff;
1949
1950         if (index != 0)
1951                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
1952                                            in_eeprom->length, in_eeprom->data);
1953
1954         return 0;
1955 }
1956
1957 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
1958 {
1959         switch (dir_type) {
1960         case BNX_DIR_TYPE_CHIMP_PATCH:
1961         case BNX_DIR_TYPE_BOOTCODE:
1962         case BNX_DIR_TYPE_BOOTCODE_2:
1963         case BNX_DIR_TYPE_APE_FW:
1964         case BNX_DIR_TYPE_APE_PATCH:
1965         case BNX_DIR_TYPE_KONG_FW:
1966         case BNX_DIR_TYPE_KONG_PATCH:
1967         case BNX_DIR_TYPE_BONO_FW:
1968         case BNX_DIR_TYPE_BONO_PATCH:
1969                 return true;
1970         }
1971
1972         return false;
1973 }
1974
1975 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
1976 {
1977         switch (dir_type) {
1978         case BNX_DIR_TYPE_AVS:
1979         case BNX_DIR_TYPE_EXP_ROM_MBA:
1980         case BNX_DIR_TYPE_PCIE:
1981         case BNX_DIR_TYPE_TSCF_UCODE:
1982         case BNX_DIR_TYPE_EXT_PHY:
1983         case BNX_DIR_TYPE_CCM:
1984         case BNX_DIR_TYPE_ISCSI_BOOT:
1985         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
1986         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
1987                 return true;
1988         }
1989
1990         return false;
1991 }
1992
1993 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
1994 {
1995         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
1996                 bnxt_dir_type_is_other_exec_format(dir_type);
1997 }
1998
1999 static int
2000 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2001                 struct rte_dev_eeprom_info *in_eeprom)
2002 {
2003         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2004         uint8_t index, dir_op;
2005         uint16_t type, ext, ordinal, attr;
2006
2007         RTE_LOG(INFO, PMD, "%s(): %04x:%02x:%02x:%02x in_eeprom->offset = %d "
2008                 "len = %d\n", __func__, bp->pdev->addr.domain,
2009                 bp->pdev->addr.bus, bp->pdev->addr.devid,
2010                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2011
2012         if (!BNXT_PF(bp)) {
2013                 RTE_LOG(ERR, PMD, "NVM write not supported from a VF\n");
2014                 return -EINVAL;
2015         }
2016
2017         type = in_eeprom->magic >> 16;
2018
2019         if (type == 0xffff) { /* special value for directory operations */
2020                 index = in_eeprom->magic & 0xff;
2021                 dir_op = in_eeprom->magic >> 8;
2022                 if (index == 0)
2023                         return -EINVAL;
2024                 switch (dir_op) {
2025                 case 0x0e: /* erase */
2026                         if (in_eeprom->offset != ~in_eeprom->magic)
2027                                 return -EINVAL;
2028                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
2029                 default:
2030                         return -EINVAL;
2031                 }
2032         }
2033
2034         /* Create or re-write an NVM item: */
2035         if (bnxt_dir_type_is_executable(type) == true)
2036                 return -EOPNOTSUPP;
2037         ext = in_eeprom->magic & 0xffff;
2038         ordinal = in_eeprom->offset >> 16;
2039         attr = in_eeprom->offset & 0xffff;
2040
2041         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
2042                                      in_eeprom->data, in_eeprom->length);
2043         return 0;
2044 }
2045
2046 /*
2047  * Initialization
2048  */
2049
2050 static const struct eth_dev_ops bnxt_dev_ops = {
2051         .dev_infos_get = bnxt_dev_info_get_op,
2052         .dev_close = bnxt_dev_close_op,
2053         .dev_configure = bnxt_dev_configure_op,
2054         .dev_start = bnxt_dev_start_op,
2055         .dev_stop = bnxt_dev_stop_op,
2056         .dev_set_link_up = bnxt_dev_set_link_up_op,
2057         .dev_set_link_down = bnxt_dev_set_link_down_op,
2058         .stats_get = bnxt_stats_get_op,
2059         .stats_reset = bnxt_stats_reset_op,
2060         .rx_queue_setup = bnxt_rx_queue_setup_op,
2061         .rx_queue_release = bnxt_rx_queue_release_op,
2062         .tx_queue_setup = bnxt_tx_queue_setup_op,
2063         .tx_queue_release = bnxt_tx_queue_release_op,
2064         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
2065         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
2066         .reta_update = bnxt_reta_update_op,
2067         .reta_query = bnxt_reta_query_op,
2068         .rss_hash_update = bnxt_rss_hash_update_op,
2069         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
2070         .link_update = bnxt_link_update_op,
2071         .promiscuous_enable = bnxt_promiscuous_enable_op,
2072         .promiscuous_disable = bnxt_promiscuous_disable_op,
2073         .allmulticast_enable = bnxt_allmulticast_enable_op,
2074         .allmulticast_disable = bnxt_allmulticast_disable_op,
2075         .mac_addr_add = bnxt_mac_addr_add_op,
2076         .mac_addr_remove = bnxt_mac_addr_remove_op,
2077         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
2078         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
2079         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
2080         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
2081         .vlan_filter_set = bnxt_vlan_filter_set_op,
2082         .vlan_offload_set = bnxt_vlan_offload_set_op,
2083         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
2084         .mtu_set = bnxt_mtu_set_op,
2085         .mac_addr_set = bnxt_set_default_mac_addr_op,
2086         .xstats_get = bnxt_dev_xstats_get_op,
2087         .xstats_get_names = bnxt_dev_xstats_get_names_op,
2088         .xstats_reset = bnxt_dev_xstats_reset_op,
2089         .fw_version_get = bnxt_fw_version_get,
2090         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
2091         .rxq_info_get = bnxt_rxq_info_get_op,
2092         .txq_info_get = bnxt_txq_info_get_op,
2093         .dev_led_on = bnxt_dev_led_on_op,
2094         .dev_led_off = bnxt_dev_led_off_op,
2095         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
2096         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
2097         .rx_queue_count = bnxt_rx_queue_count_op,
2098         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
2099         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
2100         .filter_ctrl = bnxt_filter_ctrl_op,
2101         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
2102         .get_eeprom_length    = bnxt_get_eeprom_length_op,
2103         .get_eeprom           = bnxt_get_eeprom_op,
2104         .set_eeprom           = bnxt_set_eeprom_op,
2105 };
2106
2107 static bool bnxt_vf_pciid(uint16_t id)
2108 {
2109         if (id == BROADCOM_DEV_ID_57304_VF ||
2110             id == BROADCOM_DEV_ID_57406_VF ||
2111             id == BROADCOM_DEV_ID_5731X_VF ||
2112             id == BROADCOM_DEV_ID_5741X_VF ||
2113             id == BROADCOM_DEV_ID_57414_VF ||
2114             id == BROADCOM_DEV_ID_STRATUS_NIC_VF)
2115                 return true;
2116         return false;
2117 }
2118
2119 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
2120 {
2121         struct bnxt *bp = eth_dev->data->dev_private;
2122         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2123         int rc;
2124
2125         /* enable device (incl. PCI PM wakeup), and bus-mastering */
2126         if (!pci_dev->mem_resource[0].addr) {
2127                 RTE_LOG(ERR, PMD,
2128                         "Cannot find PCI device base address, aborting\n");
2129                 rc = -ENODEV;
2130                 goto init_err_disable;
2131         }
2132
2133         bp->eth_dev = eth_dev;
2134         bp->pdev = pci_dev;
2135
2136         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
2137         if (!bp->bar0) {
2138                 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
2139                 rc = -ENOMEM;
2140                 goto init_err_release;
2141         }
2142         return 0;
2143
2144 init_err_release:
2145         if (bp->bar0)
2146                 bp->bar0 = NULL;
2147
2148 init_err_disable:
2149
2150         return rc;
2151 }
2152
2153 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
2154
2155 #define ALLOW_FUNC(x)   \
2156         { \
2157                 typeof(x) arg = (x); \
2158                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
2159                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
2160         }
2161 static int
2162 bnxt_dev_init(struct rte_eth_dev *eth_dev)
2163 {
2164         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2165         char mz_name[RTE_MEMZONE_NAMESIZE];
2166         const struct rte_memzone *mz = NULL;
2167         static int version_printed;
2168         uint32_t total_alloc_len;
2169         phys_addr_t mz_phys_addr;
2170         struct bnxt *bp;
2171         int rc;
2172
2173         if (version_printed++ == 0)
2174                 RTE_LOG(INFO, PMD, "%s\n", bnxt_version);
2175
2176         rte_eth_copy_pci_info(eth_dev, pci_dev);
2177         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
2178
2179         bp = eth_dev->data->dev_private;
2180
2181         rte_atomic64_init(&bp->rx_mbuf_alloc_fail);
2182         bp->dev_stopped = 1;
2183
2184         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2185                 goto skip_init;
2186
2187         if (bnxt_vf_pciid(pci_dev->id.device_id))
2188                 bp->flags |= BNXT_FLAG_VF;
2189
2190         rc = bnxt_init_board(eth_dev);
2191         if (rc) {
2192                 RTE_LOG(ERR, PMD,
2193                         "Board initialization failed rc: %x\n", rc);
2194                 goto error;
2195         }
2196 skip_init:
2197         eth_dev->dev_ops = &bnxt_dev_ops;
2198         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2199                 return 0;
2200         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
2201         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
2202
2203         if (BNXT_PF(bp) && pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
2204                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
2205                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
2206                          pci_dev->addr.bus, pci_dev->addr.devid,
2207                          pci_dev->addr.function, "rx_port_stats");
2208                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
2209                 mz = rte_memzone_lookup(mz_name);
2210                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
2211                                 sizeof(struct rx_port_stats) + 512);
2212                 if (!mz) {
2213                         mz = rte_memzone_reserve(mz_name, total_alloc_len,
2214                                                  SOCKET_ID_ANY,
2215                                                  RTE_MEMZONE_2MB |
2216                                                  RTE_MEMZONE_SIZE_HINT_ONLY);
2217                         if (mz == NULL)
2218                                 return -ENOMEM;
2219                 }
2220                 memset(mz->addr, 0, mz->len);
2221                 mz_phys_addr = mz->phys_addr;
2222                 if ((unsigned long)mz->addr == mz_phys_addr) {
2223                         RTE_LOG(WARNING, PMD,
2224                                 "Memzone physical address same as virtual.\n");
2225                         RTE_LOG(WARNING, PMD,
2226                                 "Using rte_mem_virt2phy()\n");
2227                         mz_phys_addr = rte_mem_virt2phy(mz->addr);
2228                         if (mz_phys_addr == 0) {
2229                                 RTE_LOG(ERR, PMD,
2230                                 "unable to map address to physical memory\n");
2231                                 return -ENOMEM;
2232                         }
2233                 }
2234
2235                 bp->rx_mem_zone = (const void *)mz;
2236                 bp->hw_rx_port_stats = mz->addr;
2237                 bp->hw_rx_port_stats_map = mz_phys_addr;
2238
2239                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
2240                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
2241                          pci_dev->addr.bus, pci_dev->addr.devid,
2242                          pci_dev->addr.function, "tx_port_stats");
2243                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
2244                 mz = rte_memzone_lookup(mz_name);
2245                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
2246                                 sizeof(struct tx_port_stats) + 512);
2247                 if (!mz) {
2248                         mz = rte_memzone_reserve(mz_name, total_alloc_len,
2249                                                  SOCKET_ID_ANY,
2250                                                  RTE_MEMZONE_2MB |
2251                                                  RTE_MEMZONE_SIZE_HINT_ONLY);
2252                         if (mz == NULL)
2253                                 return -ENOMEM;
2254                 }
2255                 memset(mz->addr, 0, mz->len);
2256                 mz_phys_addr = mz->phys_addr;
2257                 if ((unsigned long)mz->addr == mz_phys_addr) {
2258                         RTE_LOG(WARNING, PMD,
2259                                 "Memzone physical address same as virtual.\n");
2260                         RTE_LOG(WARNING, PMD,
2261                                 "Using rte_mem_virt2phy()\n");
2262                         mz_phys_addr = rte_mem_virt2phy(mz->addr);
2263                         if (mz_phys_addr == 0) {
2264                                 RTE_LOG(ERR, PMD,
2265                                 "unable to map address to physical memory\n");
2266                                 return -ENOMEM;
2267                         }
2268                 }
2269
2270                 bp->tx_mem_zone = (const void *)mz;
2271                 bp->hw_tx_port_stats = mz->addr;
2272                 bp->hw_tx_port_stats_map = mz_phys_addr;
2273
2274                 bp->flags |= BNXT_FLAG_PORT_STATS;
2275         }
2276
2277         rc = bnxt_alloc_hwrm_resources(bp);
2278         if (rc) {
2279                 RTE_LOG(ERR, PMD,
2280                         "hwrm resource allocation failure rc: %x\n", rc);
2281                 goto error_free;
2282         }
2283         rc = bnxt_hwrm_ver_get(bp);
2284         if (rc)
2285                 goto error_free;
2286         bnxt_hwrm_queue_qportcfg(bp);
2287
2288         bnxt_hwrm_func_qcfg(bp);
2289
2290         /* Get the MAX capabilities for this function */
2291         rc = bnxt_hwrm_func_qcaps(bp);
2292         if (rc) {
2293                 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
2294                 goto error_free;
2295         }
2296         if (bp->max_tx_rings == 0) {
2297                 RTE_LOG(ERR, PMD, "No TX rings available!\n");
2298                 rc = -EBUSY;
2299                 goto error_free;
2300         }
2301         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
2302                                         ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR, 0);
2303         if (eth_dev->data->mac_addrs == NULL) {
2304                 RTE_LOG(ERR, PMD,
2305                         "Failed to alloc %u bytes needed to store MAC addr tbl",
2306                         ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR);
2307                 rc = -ENOMEM;
2308                 goto error_free;
2309         }
2310         /* Copy the permanent MAC from the qcap response address now. */
2311         memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
2312         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
2313         bp->grp_info = rte_zmalloc("bnxt_grp_info",
2314                                 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
2315         if (!bp->grp_info) {
2316                 RTE_LOG(ERR, PMD,
2317                         "Failed to alloc %zu bytes needed to store group info table\n",
2318                         sizeof(*bp->grp_info) * bp->max_ring_grps);
2319                 rc = -ENOMEM;
2320                 goto error_free;
2321         }
2322
2323         /* Forward all requests if firmware is new enough */
2324         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
2325             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
2326             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
2327                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
2328         } else {
2329                 RTE_LOG(WARNING, PMD,
2330                         "Firmware too old for VF mailbox functionality\n");
2331                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
2332         }
2333
2334         /*
2335          * The following are used for driver cleanup.  If we disallow these,
2336          * VF drivers can't clean up cleanly.
2337          */
2338         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
2339         ALLOW_FUNC(HWRM_VNIC_FREE);
2340         ALLOW_FUNC(HWRM_RING_FREE);
2341         ALLOW_FUNC(HWRM_RING_GRP_FREE);
2342         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
2343         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
2344         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
2345         rc = bnxt_hwrm_func_driver_register(bp);
2346         if (rc) {
2347                 RTE_LOG(ERR, PMD,
2348                         "Failed to register driver");
2349                 rc = -EBUSY;
2350                 goto error_free;
2351         }
2352
2353         RTE_LOG(INFO, PMD,
2354                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
2355                 pci_dev->mem_resource[0].phys_addr,
2356                 pci_dev->mem_resource[0].addr);
2357
2358         rc = bnxt_hwrm_func_reset(bp);
2359         if (rc) {
2360                 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
2361                 rc = -1;
2362                 goto error_free;
2363         }
2364
2365         if (BNXT_PF(bp)) {
2366                 //if (bp->pf.active_vfs) {
2367                         // TODO: Deallocate VF resources?
2368                 //}
2369                 if (bp->pdev->max_vfs) {
2370                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
2371                         if (rc) {
2372                                 RTE_LOG(ERR, PMD, "Failed to allocate VFs\n");
2373                                 goto error_free;
2374                         }
2375                 } else {
2376                         rc = bnxt_hwrm_allocate_pf_only(bp);
2377                         if (rc) {
2378                                 RTE_LOG(ERR, PMD,
2379                                         "Failed to allocate PF resources\n");
2380                                 goto error_free;
2381                         }
2382                 }
2383         }
2384
2385         bnxt_hwrm_port_led_qcaps(bp);
2386
2387         rc = bnxt_setup_int(bp);
2388         if (rc)
2389                 goto error_free;
2390
2391         rc = bnxt_alloc_mem(bp);
2392         if (rc)
2393                 goto error_free_int;
2394
2395         rc = bnxt_request_int(bp);
2396         if (rc)
2397                 goto error_free_int;
2398
2399         rc = bnxt_alloc_def_cp_ring(bp);
2400         if (rc)
2401                 goto error_free_int;
2402
2403         bnxt_enable_int(bp);
2404
2405         return 0;
2406
2407 error_free_int:
2408         bnxt_disable_int(bp);
2409         bnxt_free_def_cp_ring(bp);
2410         bnxt_hwrm_func_buf_unrgtr(bp);
2411         bnxt_free_int(bp);
2412         bnxt_free_mem(bp);
2413 error_free:
2414         bnxt_dev_uninit(eth_dev);
2415 error:
2416         return rc;
2417 }
2418
2419 static int
2420 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
2421         struct bnxt *bp = eth_dev->data->dev_private;
2422         int rc;
2423
2424         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2425                 return -EPERM;
2426
2427         bnxt_disable_int(bp);
2428         bnxt_free_int(bp);
2429         bnxt_free_mem(bp);
2430         if (eth_dev->data->mac_addrs != NULL) {
2431                 rte_free(eth_dev->data->mac_addrs);
2432                 eth_dev->data->mac_addrs = NULL;
2433         }
2434         if (bp->grp_info != NULL) {
2435                 rte_free(bp->grp_info);
2436                 bp->grp_info = NULL;
2437         }
2438         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
2439         bnxt_free_hwrm_resources(bp);
2440         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
2441         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
2442         if (bp->dev_stopped == 0)
2443                 bnxt_dev_close_op(eth_dev);
2444         if (bp->pf.vf_info)
2445                 rte_free(bp->pf.vf_info);
2446         eth_dev->dev_ops = NULL;
2447         eth_dev->rx_pkt_burst = NULL;
2448         eth_dev->tx_pkt_burst = NULL;
2449
2450         return rc;
2451 }
2452
2453 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2454         struct rte_pci_device *pci_dev)
2455 {
2456         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
2457                 bnxt_dev_init);
2458 }
2459
2460 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
2461 {
2462         return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
2463 }
2464
2465 static struct rte_pci_driver bnxt_rte_pmd = {
2466         .id_table = bnxt_pci_id_map,
2467         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
2468                 RTE_PCI_DRV_INTR_LSC,
2469         .probe = bnxt_pci_probe,
2470         .remove = bnxt_pci_remove,
2471 };
2472
2473 static bool
2474 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
2475 {
2476         if (strcmp(dev->device->driver->name, drv->driver.name))
2477                 return false;
2478
2479         return true;
2480 }
2481
2482 bool is_bnxt_supported(struct rte_eth_dev *dev)
2483 {
2484         return is_device_supported(dev, &bnxt_rte_pmd);
2485 }
2486
2487 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
2488 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
2489 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");