drivers/net/bnxt/bnxt_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <inttypes.h>
  35 #include <stdbool.h>
  36
  37 #include <rte_dev.h>
  38 #include <rte_ethdev.h>
  39 #include <rte_malloc.h>
  40 #include <rte_cycles.h>
  41
  42 #include "bnxt.h"
  43 #include "bnxt_cpr.h"
  44 #include "bnxt_filter.h"
  45 #include "bnxt_hwrm.h"
  46 #include "bnxt_irq.h"
  47 #include "bnxt_ring.h"
  48 #include "bnxt_rxq.h"
  49 #include "bnxt_rxr.h"
  50 #include "bnxt_stats.h"
  51 #include "bnxt_txq.h"
  52 #include "bnxt_txr.h"
  53 #include "bnxt_vnic.h"
  54 #include "hsi_struct_def_dpdk.h"
  55
  56 #define DRV_MODULE_NAME         "bnxt"
  57 static const char bnxt_version[] =
  58         "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
  59
  60 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  61
  62 #define BROADCOM_DEV_ID_57301 0x16c8
  63 #define BROADCOM_DEV_ID_57302 0x16c9
  64 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  65 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  66 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  67 #define BROADCOM_DEV_ID_NS2 0x16cd
  68 #define BROADCOM_DEV_ID_57311 0x16ce
  69 #define BROADCOM_DEV_ID_57312 0x16cf
  70 #define BROADCOM_DEV_ID_57402 0x16d0
  71 #define BROADCOM_DEV_ID_57404 0x16d1
  72 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  73 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  74 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  75 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  76 #define BROADCOM_DEV_ID_57412 0x16d6
  77 #define BROADCOM_DEV_ID_57414 0x16d7
  78 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  79 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  80 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  81 #define BROADCOM_DEV_ID_57412_MF 0x16de
  82 #define BROADCOM_DEV_ID_57314 0x16df
  83 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  84 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  85 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  86 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  87 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  88 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  89 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  90 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  91 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  92 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  93 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  94
  95 static struct rte_pci_id bnxt_pci_id_map[] = {
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 128         { .vendor_id = 0, /* sentinel */ },
 129 };
 130
 131 #define BNXT_ETH_RSS_SUPPORT (  \
 132         ETH_RSS_IPV4 |          \
 133         ETH_RSS_NONFRAG_IPV4_TCP |      \
 134         ETH_RSS_NONFRAG_IPV4_UDP |      \
 135         ETH_RSS_IPV6 |          \
 136         ETH_RSS_NONFRAG_IPV6_TCP |      \
 137         ETH_RSS_NONFRAG_IPV6_UDP)
 138
 139 /***********************/
 140
 141 /*
 142  * High level utility functions
 143  */
 144
 145 static void bnxt_free_mem(struct bnxt *bp)
 146 {
 147         bnxt_free_filter_mem(bp);
 148         bnxt_free_vnic_attributes(bp);
 149         bnxt_free_vnic_mem(bp);
 150
 151         bnxt_free_stats(bp);
 152         bnxt_free_tx_rings(bp);
 153         bnxt_free_rx_rings(bp);
 154         bnxt_free_def_cp_ring(bp);
 155 }
 156
 157 static int bnxt_alloc_mem(struct bnxt *bp)
 158 {
 159         int rc;
 160
 161         /* Default completion ring */
 162         rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
 163         if (rc)
 164                 goto alloc_mem_err;
 165
 166         rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
 167                               bp->def_cp_ring, "def_cp");
 168         if (rc)
 169                 goto alloc_mem_err;
 170
 171         rc = bnxt_alloc_vnic_mem(bp);
 172         if (rc)
 173                 goto alloc_mem_err;
 174
 175         rc = bnxt_alloc_vnic_attributes(bp);
 176         if (rc)
 177                 goto alloc_mem_err;
 178
 179         rc = bnxt_alloc_filter_mem(bp);
 180         if (rc)
 181                 goto alloc_mem_err;
 182
 183         return 0;
 184
 185 alloc_mem_err:
 186         bnxt_free_mem(bp);
 187         return rc;
 188 }
 189
 190 static int bnxt_init_chip(struct bnxt *bp)
 191 {
 192         unsigned int i, rss_idx, fw_idx;
 193         struct rte_eth_link new;
 194         int rc;
 195
 196         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 197         if (rc) {
 198                 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
 199                 goto err_out;
 200         }
 201
 202         rc = bnxt_alloc_hwrm_rings(bp);
 203         if (rc) {
 204                 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
 205                 goto err_out;
 206         }
 207
 208         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 209         if (rc) {
 210                 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
 211                 goto err_out;
 212         }
 213
 214         rc = bnxt_mq_rx_configure(bp);
 215         if (rc) {
 216                 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
 217                 goto err_out;
 218         }
 219
 220         /* VNIC configuration */
 221         for (i = 0; i < bp->nr_vnics; i++) {
 222                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 223
 224                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 225                 if (rc) {
 226                         RTE_LOG(ERR, PMD, "HWRM vnic alloc failure rc: %x\n",
 227                                 rc);
 228                         goto err_out;
 229                 }
 230
 231                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
 232                 if (rc) {
 233                         RTE_LOG(ERR, PMD,
 234                                 "HWRM vnic ctx alloc failure rc: %x\n", rc);
 235                         goto err_out;
 236                 }
 237
 238                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 239                 if (rc) {
 240                         RTE_LOG(ERR, PMD, "HWRM vnic cfg failure rc: %x\n", rc);
 241                         goto err_out;
 242                 }
 243
 244                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 245                 if (rc) {
 246                         RTE_LOG(ERR, PMD, "HWRM vnic filter failure rc: %x\n",
 247                                 rc);
 248                         goto err_out;
 249                 }
 250                 if (vnic->rss_table && vnic->hash_type) {
 251                         /*
 252                          * Fill the RSS hash & redirection table with
 253                          * ring group ids for all VNICs
 254                          */
 255                         for (rss_idx = 0, fw_idx = 0;
 256                              rss_idx < HW_HASH_INDEX_SIZE;
 257                              rss_idx++, fw_idx++) {
 258                                 if (vnic->fw_grp_ids[fw_idx] ==
 259                                     INVALID_HW_RING_ID)
 260                                         fw_idx = 0;
 261                                 vnic->rss_table[rss_idx] =
 262                                                 vnic->fw_grp_ids[fw_idx];
 263                         }
 264                         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 265                         if (rc) {
 266                                 RTE_LOG(ERR, PMD,
 267                                         "HWRM vnic set RSS failure rc: %x\n",
 268                                         rc);
 269                                 goto err_out;
 270                         }
 271                 }
 272         }
 273         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0]);
 274         if (rc) {
 275                 RTE_LOG(ERR, PMD,
 276                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 277                 goto err_out;
 278         }
 279
 280         rc = bnxt_get_hwrm_link_config(bp, &new);
 281         if (rc) {
 282                 RTE_LOG(ERR, PMD, "HWRM Get link config failure rc: %x\n", rc);
 283                 goto err_out;
 284         }
 285
 286         if (!bp->link_info.link_up) {
 287                 rc = bnxt_set_hwrm_link_config(bp, true);
 288                 if (rc) {
 289                         RTE_LOG(ERR, PMD,
 290                                 "HWRM link config failure rc: %x\n", rc);
 291                         goto err_out;
 292                 }
 293         }
 294
 295         return 0;
 296
 297 err_out:
 298         bnxt_free_all_hwrm_resources(bp);
 299
 300         return rc;
 301 }
 302
 303 static int bnxt_shutdown_nic(struct bnxt *bp)
 304 {
 305         bnxt_free_all_hwrm_resources(bp);
 306         bnxt_free_all_filters(bp);
 307         bnxt_free_all_vnics(bp);
 308         return 0;
 309 }
 310
 311 static int bnxt_init_nic(struct bnxt *bp)
 312 {
 313         int rc;
 314
 315         bnxt_init_ring_grps(bp);
 316         bnxt_init_vnics(bp);
 317         bnxt_init_filters(bp);
 318
 319         rc = bnxt_init_chip(bp);
 320         if (rc)
 321                 return rc;
 322
 323         return 0;
 324 }
 325
 326 /*
 327  * Device configuration and status function
 328  */
 329
 330 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 331                                   struct rte_eth_dev_info *dev_info)
 332 {
 333         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 334         uint16_t max_vnics, i, j, vpool, vrxq;
 335
 336         /* MAC Specifics */
 337         dev_info->max_mac_addrs = MAX_NUM_MAC_ADDR;
 338         dev_info->max_hash_mac_addrs = 0;
 339
 340         /* PF/VF specifics */
 341         if (BNXT_PF(bp)) {
 342                 dev_info->max_rx_queues = bp->pf.max_rx_rings;
 343                 dev_info->max_tx_queues = bp->pf.max_tx_rings;
 344                 dev_info->max_vfs = bp->pf.active_vfs;
 345                 dev_info->reta_size = bp->pf.max_rsscos_ctx;
 346                 max_vnics = bp->pf.max_vnics;
 347         } else {
 348                 dev_info->max_rx_queues = bp->vf.max_rx_rings;
 349                 dev_info->max_tx_queues = bp->vf.max_tx_rings;
 350                 dev_info->reta_size = bp->vf.max_rsscos_ctx;
 351                 max_vnics = bp->vf.max_vnics;
 352         }
 353
 354         /* Fast path specifics */
 355         dev_info->min_rx_bufsize = 1;
 356         dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
 357                                   + VLAN_TAG_SIZE;
 358         dev_info->rx_offload_capa = 0;
 359         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
 360                                         DEV_TX_OFFLOAD_TCP_CKSUM |
 361                                         DEV_TX_OFFLOAD_UDP_CKSUM |
 362                                         DEV_TX_OFFLOAD_TCP_TSO;
 363
 364         /* *INDENT-OFF* */
 365         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 366                 .rx_thresh = {
 367                         .pthresh = 8,
 368                         .hthresh = 8,
 369                         .wthresh = 0,
 370                 },
 371                 .rx_free_thresh = 32,
 372                 .rx_drop_en = 0,
 373         };
 374
 375         dev_info->default_txconf = (struct rte_eth_txconf) {
 376                 .tx_thresh = {
 377                         .pthresh = 32,
 378                         .hthresh = 0,
 379                         .wthresh = 0,
 380                 },
 381                 .tx_free_thresh = 32,
 382                 .tx_rs_thresh = 32,
 383                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
 384                              ETH_TXQ_FLAGS_NOOFFLOADS,
 385         };
 386         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 387
 388         /* *INDENT-ON* */
 389
 390         /*
 391          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 392          *       need further investigation.
 393          */
 394
 395         /* VMDq resources */
 396         vpool = 64; /* ETH_64_POOLS */
 397         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 398         for (i = 0; i < 4; vpool >>= 1, i++) {
 399                 if (max_vnics > vpool) {
 400                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 401                                 if (dev_info->max_rx_queues > vrxq) {
 402                                         if (vpool > vrxq)
 403                                                 vpool = vrxq;
 404                                         goto found;
 405                                 }
 406                         }
 407                         /* Not enough resources to support VMDq */
 408                         break;
 409                 }
 410         }
 411         /* Not enough resources to support VMDq */
 412         vpool = 0;
 413         vrxq = 0;
 414 found:
 415         dev_info->max_vmdq_pools = vpool;
 416         dev_info->vmdq_queue_num = vrxq;
 417
 418         dev_info->vmdq_pool_base = 0;
 419         dev_info->vmdq_queue_base = 0;
 420 }
 421
 422 /* Configure the device based on the configuration provided */
 423 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 424 {
 425         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 426
 427         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 428         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 429
 430         /* Inherit new configurations */
 431         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 432         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 433         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 434         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 435
 436         if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
 437                 eth_dev->data->mtu =
 438                                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 439                                 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
 440         return 0;
 441 }
 442
 443 static inline int
 444 rte_bnxt_atomic_write_link_status(struct rte_eth_dev *eth_dev,
 445                                 struct rte_eth_link *link)
 446 {
 447         struct rte_eth_link *dst = &eth_dev->data->dev_link;
 448         struct rte_eth_link *src = link;
 449
 450         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 451                                         *(uint64_t *)src) == 0)
 452                 return 1;
 453
 454         return 0;
 455 }
 456
 457 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 458 {
 459         struct rte_eth_link *link = &eth_dev->data->dev_link;
 460
 461         if (link->link_status)
 462                 RTE_LOG(INFO, PMD, "Port %d Link Up - speed %u Mbps - %s\n",
 463                         (uint8_t)(eth_dev->data->port_id),
 464                         (uint32_t)link->link_speed,
 465                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 466                         ("full-duplex") : ("half-duplex\n"));
 467         else
 468                 RTE_LOG(INFO, PMD, "Port %d Link Down\n",
 469                         (uint8_t)(eth_dev->data->port_id));
 470 }
 471
 472 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
 473 {
 474         bnxt_print_link_info(eth_dev);
 475         return 0;
 476 }
 477
 478 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 479 {
 480         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 481         int rc;
 482
 483         bp->dev_stopped = 0;
 484         rc = bnxt_hwrm_func_reset(bp);
 485         if (rc) {
 486                 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
 487                 rc = -1;
 488                 goto error;
 489         }
 490
 491         rc = bnxt_setup_int(bp);
 492         if (rc)
 493                 goto error;
 494
 495         rc = bnxt_alloc_mem(bp);
 496         if (rc)
 497                 goto error;
 498
 499         rc = bnxt_request_int(bp);
 500         if (rc)
 501                 goto error;
 502
 503         rc = bnxt_init_nic(bp);
 504         if (rc)
 505                 goto error;
 506
 507         bnxt_enable_int(bp);
 508
 509         bnxt_link_update_op(eth_dev, 0);
 510         return 0;
 511
 512 error:
 513         bnxt_shutdown_nic(bp);
 514         bnxt_disable_int(bp);
 515         bnxt_free_int(bp);
 516         bnxt_free_tx_mbufs(bp);
 517         bnxt_free_rx_mbufs(bp);
 518         bnxt_free_mem(bp);
 519         return rc;
 520 }
 521
 522 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 523 {
 524         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 525
 526         eth_dev->data->dev_link.link_status = 1;
 527         bnxt_set_hwrm_link_config(bp, true);
 528         return 0;
 529 }
 530
 531 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 532 {
 533         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 534
 535         eth_dev->data->dev_link.link_status = 0;
 536         bnxt_set_hwrm_link_config(bp, false);
 537         return 0;
 538 }
 539
 540 /* Unload the driver, release resources */
 541 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 542 {
 543         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 544
 545         if (bp->eth_dev->data->dev_started) {
 546                 /* TBD: STOP HW queues DMA */
 547                 eth_dev->data->dev_link.link_status = 0;
 548         }
 549         bnxt_set_hwrm_link_config(bp, false);
 550         bnxt_disable_int(bp);
 551         bnxt_free_int(bp);
 552         bnxt_shutdown_nic(bp);
 553         bp->dev_stopped = 1;
 554 }
 555
 556 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 557 {
 558         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 559
 560         if (bp->dev_stopped == 0)
 561                 bnxt_dev_stop_op(eth_dev);
 562
 563         bnxt_free_tx_mbufs(bp);
 564         bnxt_free_rx_mbufs(bp);
 565         bnxt_free_mem(bp);
 566         if (eth_dev->data->mac_addrs != NULL) {
 567                 rte_free(eth_dev->data->mac_addrs);
 568                 eth_dev->data->mac_addrs = NULL;
 569         }
 570         if (bp->grp_info != NULL) {
 571                 rte_free(bp->grp_info);
 572                 bp->grp_info = NULL;
 573         }
 574 }
 575
 576 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 577                                     uint32_t index)
 578 {
 579         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 580         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 581         struct bnxt_vnic_info *vnic;
 582         struct bnxt_filter_info *filter, *temp_filter;
 583         int i;
 584
 585         /*
 586          * Loop through all VNICs from the specified filter flow pools to
 587          * remove the corresponding MAC addr filter
 588          */
 589         for (i = 0; i < MAX_FF_POOLS; i++) {
 590                 if (!(pool_mask & (1ULL << i)))
 591                         continue;
 592
 593                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 594                         filter = STAILQ_FIRST(&vnic->filter);
 595                         while (filter) {
 596                                 temp_filter = STAILQ_NEXT(filter, next);
 597                                 if (filter->mac_index == index) {
 598                                         STAILQ_REMOVE(&vnic->filter, filter,
 599                                                       bnxt_filter_info, next);
 600                                         bnxt_hwrm_clear_filter(bp, filter);
 601                                         filter->mac_index = INVALID_MAC_INDEX;
 602                                         memset(&filter->l2_addr, 0,
 603                                                ETHER_ADDR_LEN);
 604                                         STAILQ_INSERT_TAIL(
 605                                                         &bp->free_filter_list,
 606                                                         filter, next);
 607                                 }
 608                                 filter = temp_filter;
 609                         }
 610                 }
 611         }
 612 }
 613
 614 static void bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 615                                  struct ether_addr *mac_addr,
 616                                  uint32_t index, uint32_t pool)
 617 {
 618         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 619         struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
 620         struct bnxt_filter_info *filter;
 621
 622         if (BNXT_VF(bp)) {
 623                 RTE_LOG(ERR, PMD, "Cannot add MAC address to a VF interface\n");
 624                 return;
 625         }
 626
 627         if (!vnic) {
 628                 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
 629                 return;
 630         }
 631         /* Attach requested MAC address to the new l2_filter */
 632         STAILQ_FOREACH(filter, &vnic->filter, next) {
 633                 if (filter->mac_index == index) {
 634                         RTE_LOG(ERR, PMD,
 635                                 "MAC addr already existed for pool %d\n", pool);
 636                         return;
 637                 }
 638         }
 639         filter = bnxt_alloc_filter(bp);
 640         if (!filter) {
 641                 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
 642                 return;
 643         }
 644         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 645         filter->mac_index = index;
 646         memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
 647         bnxt_hwrm_set_filter(bp, vnic, filter);
 648 }
 649
 650 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 651 {
 652         int rc = 0;
 653         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 654         struct rte_eth_link new;
 655         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 656
 657         memset(&new, 0, sizeof(new));
 658         do {
 659                 /* Retrieve link info from hardware */
 660                 rc = bnxt_get_hwrm_link_config(bp, &new);
 661                 if (rc) {
 662                         new.link_speed = ETH_LINK_SPEED_100M;
 663                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 664                         RTE_LOG(ERR, PMD,
 665                                 "Failed to retrieve link rc = 0x%x!", rc);
 666                         goto out;
 667                 }
 668                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 669
 670                 if (!wait_to_complete)
 671                         break;
 672         } while (!new.link_status && cnt--);
 673
 674 out:
 675         /* Timed out or success */
 676         if (new.link_status != eth_dev->data->dev_link.link_status ||
 677         new.link_speed != eth_dev->data->dev_link.link_speed) {
 678                 rte_bnxt_atomic_write_link_status(eth_dev, &new);
 679                 bnxt_print_link_info(eth_dev);
 680         }
 681
 682         return rc;
 683 }
 684
 685 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
 686 {
 687         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 688         struct bnxt_vnic_info *vnic;
 689
 690         if (bp->vnic_info == NULL)
 691                 return;
 692
 693         vnic = &bp->vnic_info[0];
 694
 695         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
 696         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
 697 }
 698
 699 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
 700 {
 701         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 702         struct bnxt_vnic_info *vnic;
 703
 704         if (bp->vnic_info == NULL)
 705                 return;
 706
 707         vnic = &bp->vnic_info[0];
 708
 709         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
 710         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
 711 }
 712
 713 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
 714 {
 715         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 716         struct bnxt_vnic_info *vnic;
 717
 718         if (bp->vnic_info == NULL)
 719                 return;
 720
 721         vnic = &bp->vnic_info[0];
 722
 723         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
 724         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
 725 }
 726
 727 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
 728 {
 729         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 730         struct bnxt_vnic_info *vnic;
 731
 732         if (bp->vnic_info == NULL)
 733                 return;
 734
 735         vnic = &bp->vnic_info[0];
 736
 737         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
 738         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
 739 }
 740
 741 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
 742                             struct rte_eth_rss_reta_entry64 *reta_conf,
 743                             uint16_t reta_size)
 744 {
 745         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 746         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 747         struct bnxt_vnic_info *vnic;
 748         int i;
 749
 750         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
 751                 return -EINVAL;
 752
 753         if (reta_size != HW_HASH_INDEX_SIZE) {
 754                 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
 755                         "(%d) must equal the size supported by the hardware "
 756                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 757                 return -EINVAL;
 758         }
 759         /* Update the RSS VNIC(s) */
 760         for (i = 0; i < MAX_FF_POOLS; i++) {
 761                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 762                         memcpy(vnic->rss_table, reta_conf, reta_size);
 763
 764                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 765                 }
 766         }
 767         return 0;
 768 }
 769
 770 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
 771                               struct rte_eth_rss_reta_entry64 *reta_conf,
 772                               uint16_t reta_size)
 773 {
 774         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 775         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 776
 777         /* Retrieve from the default VNIC */
 778         if (!vnic)
 779                 return -EINVAL;
 780         if (!vnic->rss_table)
 781                 return -EINVAL;
 782
 783         if (reta_size != HW_HASH_INDEX_SIZE) {
 784                 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
 785                         "(%d) must equal the size supported by the hardware "
 786                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 787                 return -EINVAL;
 788         }
 789         /* EW - need to revisit here copying from u64 to u16 */
 790         memcpy(reta_conf, vnic->rss_table, reta_size);
 791
 792         if (rte_intr_allow_others(&eth_dev->pci_dev->intr_handle)) {
 793                 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
 794                         bnxt_dev_lsc_intr_setup(eth_dev);
 795         }
 796
 797         return 0;
 798 }
 799
 800 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
 801                                    struct rte_eth_rss_conf *rss_conf)
 802 {
 803         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 804         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 805         struct bnxt_vnic_info *vnic;
 806         uint16_t hash_type = 0;
 807         int i;
 808
 809         /*
 810          * If RSS enablement were different than dev_configure,
 811          * then return -EINVAL
 812          */
 813         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
 814                 if (!rss_conf->rss_hf)
 815                         return -EINVAL;
 816         } else {
 817                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
 818                         return -EINVAL;
 819         }
 820         if (rss_conf->rss_hf & ETH_RSS_IPV4)
 821                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 822         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
 823                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 824         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
 825                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
 826         if (rss_conf->rss_hf & ETH_RSS_IPV6)
 827                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
 828         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
 829                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
 830         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
 831                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
 832
 833         /* Update the RSS VNIC(s) */
 834         for (i = 0; i < MAX_FF_POOLS; i++) {
 835                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 836                         vnic->hash_type = hash_type;
 837
 838                         /*
 839                          * Use the supplied key if the key length is
 840                          * acceptable and the rss_key is not NULL
 841                          */
 842                         if (rss_conf->rss_key &&
 843                             rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
 844                                 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
 845                                        rss_conf->rss_key_len);
 846
 847                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 848                 }
 849         }
 850         return 0;
 851 }
 852
 853 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
 854                                      struct rte_eth_rss_conf *rss_conf)
 855 {
 856         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 857         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 858         int len;
 859         uint32_t hash_types;
 860
 861         /* RSS configuration is the same for all VNICs */
 862         if (vnic && vnic->rss_hash_key) {
 863                 if (rss_conf->rss_key) {
 864                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
 865                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
 866                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
 867                 }
 868
 869                 hash_types = vnic->hash_type;
 870                 rss_conf->rss_hf = 0;
 871                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
 872                         rss_conf->rss_hf |= ETH_RSS_IPV4;
 873                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 874                 }
 875                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
 876                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
 877                         hash_types &=
 878                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 879                 }
 880                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
 881                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
 882                         hash_types &=
 883                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
 884                 }
 885                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
 886                         rss_conf->rss_hf |= ETH_RSS_IPV6;
 887                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
 888                 }
 889                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
 890                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
 891                         hash_types &=
 892                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
 893                 }
 894                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
 895                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
 896                         hash_types &=
 897                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
 898                 }
 899                 if (hash_types) {
 900                         RTE_LOG(ERR, PMD,
 901                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
 902                                 vnic->hash_type);
 903                         return -ENOTSUP;
 904                 }
 905         } else {
 906                 rss_conf->rss_hf = 0;
 907         }
 908         return 0;
 909 }
 910
 911 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
 912                                struct rte_eth_fc_conf *fc_conf __rte_unused)
 913 {
 914         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
 915         struct rte_eth_link link_info;
 916         int rc;
 917
 918         rc = bnxt_get_hwrm_link_config(bp, &link_info);
 919         if (rc)
 920                 return rc;
 921
 922         memset(fc_conf, 0, sizeof(*fc_conf));
 923         if (bp->link_info.auto_pause)
 924                 fc_conf->autoneg = 1;
 925         switch (bp->link_info.pause) {
 926         case 0:
 927                 fc_conf->mode = RTE_FC_NONE;
 928                 break;
 929         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
 930                 fc_conf->mode = RTE_FC_TX_PAUSE;
 931                 break;
 932         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
 933                 fc_conf->mode = RTE_FC_RX_PAUSE;
 934                 break;
 935         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
 936                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
 937                 fc_conf->mode = RTE_FC_FULL;
 938                 break;
 939         }
 940         return 0;
 941 }
 942
 943 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
 944                                struct rte_eth_fc_conf *fc_conf)
 945 {
 946         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
 947
 948         if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
 949                 RTE_LOG(ERR, PMD, "Flow Control Settings cannot be modified\n");
 950                 return -ENOTSUP;
 951         }
 952
 953         switch (fc_conf->mode) {
 954         case RTE_FC_NONE:
 955                 bp->link_info.auto_pause = 0;
 956                 bp->link_info.force_pause = 0;
 957                 break;
 958         case RTE_FC_RX_PAUSE:
 959                 if (fc_conf->autoneg) {
 960                         bp->link_info.auto_pause =
 961                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
 962                         bp->link_info.force_pause = 0;
 963                 } else {
 964                         bp->link_info.auto_pause = 0;
 965                         bp->link_info.force_pause =
 966                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
 967                 }
 968                 break;
 969         case RTE_FC_TX_PAUSE:
 970                 if (fc_conf->autoneg) {
 971                         bp->link_info.auto_pause =
 972                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
 973                         bp->link_info.force_pause = 0;
 974                 } else {
 975                         bp->link_info.auto_pause = 0;
 976                         bp->link_info.force_pause =
 977                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
 978                 }
 979                 break;
 980         case RTE_FC_FULL:
 981                 if (fc_conf->autoneg) {
 982                         bp->link_info.auto_pause =
 983                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
 984                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
 985                         bp->link_info.force_pause = 0;
 986                 } else {
 987                         bp->link_info.auto_pause = 0;
 988                         bp->link_info.force_pause =
 989                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
 990                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
 991                 }
 992                 break;
 993         }
 994         return bnxt_set_hwrm_link_config(bp, true);
 995 }
 996
 997 /*
 998  * Initialization
 999  */
1000
1001 static struct eth_dev_ops bnxt_dev_ops = {
1002         .dev_infos_get = bnxt_dev_info_get_op,
1003         .dev_close = bnxt_dev_close_op,
1004         .dev_configure = bnxt_dev_configure_op,
1005         .dev_start = bnxt_dev_start_op,
1006         .dev_stop = bnxt_dev_stop_op,
1007         .dev_set_link_up = bnxt_dev_set_link_up_op,
1008         .dev_set_link_down = bnxt_dev_set_link_down_op,
1009         .stats_get = bnxt_stats_get_op,
1010         .stats_reset = bnxt_stats_reset_op,
1011         .rx_queue_setup = bnxt_rx_queue_setup_op,
1012         .rx_queue_release = bnxt_rx_queue_release_op,
1013         .tx_queue_setup = bnxt_tx_queue_setup_op,
1014         .tx_queue_release = bnxt_tx_queue_release_op,
1015         .reta_update = bnxt_reta_update_op,
1016         .reta_query = bnxt_reta_query_op,
1017         .rss_hash_update = bnxt_rss_hash_update_op,
1018         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
1019         .link_update = bnxt_link_update_op,
1020         .promiscuous_enable = bnxt_promiscuous_enable_op,
1021         .promiscuous_disable = bnxt_promiscuous_disable_op,
1022         .allmulticast_enable = bnxt_allmulticast_enable_op,
1023         .allmulticast_disable = bnxt_allmulticast_disable_op,
1024         .mac_addr_add = bnxt_mac_addr_add_op,
1025         .mac_addr_remove = bnxt_mac_addr_remove_op,
1026         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
1027         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
1028 };
1029
1030 static bool bnxt_vf_pciid(uint16_t id)
1031 {
1032         if (id == BROADCOM_DEV_ID_57304_VF ||
1033             id == BROADCOM_DEV_ID_57406_VF ||
1034             id == BROADCOM_DEV_ID_5731X_VF ||
1035             id == BROADCOM_DEV_ID_5741X_VF)
1036                 return true;
1037         return false;
1038 }
1039
1040 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
1041 {
1042         int rc;
1043         struct bnxt *bp = eth_dev->data->dev_private;
1044
1045         /* enable device (incl. PCI PM wakeup), and bus-mastering */
1046         if (!eth_dev->pci_dev->mem_resource[0].addr) {
1047                 RTE_LOG(ERR, PMD,
1048                         "Cannot find PCI device base address, aborting\n");
1049                 rc = -ENODEV;
1050                 goto init_err_disable;
1051         }
1052
1053         bp->eth_dev = eth_dev;
1054         bp->pdev = eth_dev->pci_dev;
1055
1056         bp->bar0 = (void *)eth_dev->pci_dev->mem_resource[0].addr;
1057         if (!bp->bar0) {
1058                 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
1059                 rc = -ENOMEM;
1060                 goto init_err_release;
1061         }
1062         return 0;
1063
1064 init_err_release:
1065         if (bp->bar0)
1066                 bp->bar0 = NULL;
1067
1068 init_err_disable:
1069
1070         return rc;
1071 }
1072
1073 static int
1074 bnxt_dev_init(struct rte_eth_dev *eth_dev)
1075 {
1076         static int version_printed;
1077         struct bnxt *bp;
1078         int rc;
1079
1080         if (version_printed++ == 0)
1081                 RTE_LOG(INFO, PMD, "%s", bnxt_version);
1082
1083         rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
1084         bp = eth_dev->data->dev_private;
1085
1086         if (bnxt_vf_pciid(eth_dev->pci_dev->id.device_id))
1087                 bp->flags |= BNXT_FLAG_VF;
1088
1089         rc = bnxt_init_board(eth_dev);
1090         if (rc) {
1091                 RTE_LOG(ERR, PMD,
1092                         "Board initialization failed rc: %x\n", rc);
1093                 goto error;
1094         }
1095         eth_dev->dev_ops = &bnxt_dev_ops;
1096         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
1097         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
1098
1099         rc = bnxt_alloc_hwrm_resources(bp);
1100         if (rc) {
1101                 RTE_LOG(ERR, PMD,
1102                         "hwrm resource allocation failure rc: %x\n", rc);
1103                 goto error_free;
1104         }
1105         rc = bnxt_hwrm_ver_get(bp);
1106         if (rc)
1107                 goto error_free;
1108         bnxt_hwrm_queue_qportcfg(bp);
1109
1110         bnxt_hwrm_func_qcfg(bp);
1111
1112         /* Get the MAX capabilities for this function */
1113         rc = bnxt_hwrm_func_qcaps(bp);
1114         if (rc) {
1115                 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
1116                 goto error_free;
1117         }
1118         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
1119                                         ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR, 0);
1120         if (eth_dev->data->mac_addrs == NULL) {
1121                 RTE_LOG(ERR, PMD,
1122                         "Failed to alloc %u bytes needed to store MAC addr tbl",
1123                         ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR);
1124                 rc = -ENOMEM;
1125                 goto error_free;
1126         }
1127         /* Copy the permanent MAC from the qcap response address now. */
1128         if (BNXT_PF(bp))
1129                 memcpy(bp->mac_addr, bp->pf.mac_addr, sizeof(bp->mac_addr));
1130         else
1131                 memcpy(bp->mac_addr, bp->vf.mac_addr, sizeof(bp->mac_addr));
1132         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1133         bp->grp_info = rte_zmalloc("bnxt_grp_info",
1134                                 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
1135         if (!bp->grp_info) {
1136                 RTE_LOG(ERR, PMD,
1137                         "Failed to alloc %zu bytes needed to store group info table\n",
1138                         sizeof(*bp->grp_info) * bp->max_ring_grps);
1139                 rc = -ENOMEM;
1140                 goto error_free;
1141         }
1142
1143         rc = bnxt_hwrm_func_driver_register(bp, 0,
1144                                             bp->pf.vf_req_fwd);
1145         if (rc) {
1146                 RTE_LOG(ERR, PMD,
1147                         "Failed to register driver");
1148                 rc = -EBUSY;
1149                 goto error_free;
1150         }
1151
1152         RTE_LOG(INFO, PMD,
1153                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
1154                 eth_dev->pci_dev->mem_resource[0].phys_addr,
1155                 eth_dev->pci_dev->mem_resource[0].addr);
1156
1157         bp->dev_stopped = 0;
1158
1159         return 0;
1160
1161 error_free:
1162         eth_dev->driver->eth_dev_uninit(eth_dev);
1163 error:
1164         return rc;
1165 }
1166
1167 static int
1168 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
1169         struct bnxt *bp = eth_dev->data->dev_private;
1170         int rc;
1171
1172         if (eth_dev->data->mac_addrs != NULL) {
1173                 rte_free(eth_dev->data->mac_addrs);
1174                 eth_dev->data->mac_addrs = NULL;
1175         }
1176         if (bp->grp_info != NULL) {
1177                 rte_free(bp->grp_info);
1178                 bp->grp_info = NULL;
1179         }
1180         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
1181         bnxt_free_hwrm_resources(bp);
1182         if (bp->dev_stopped == 0)
1183                 bnxt_dev_close_op(eth_dev);
1184         eth_dev->dev_ops = NULL;
1185         eth_dev->rx_pkt_burst = NULL;
1186         eth_dev->tx_pkt_burst = NULL;
1187
1188         return rc;
1189 }
1190
1191 static struct eth_driver bnxt_rte_pmd = {
1192         .pci_drv = {
1193                     .id_table = bnxt_pci_id_map,
1194                     .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
1195                             RTE_PCI_DRV_DETACHABLE | RTE_PCI_DRV_INTR_LSC,
1196                     .probe = rte_eth_dev_pci_probe,
1197                     .remove = rte_eth_dev_pci_remove
1198                     },
1199         .eth_dev_init = bnxt_dev_init,
1200         .eth_dev_uninit = bnxt_dev_uninit,
1201         .dev_private_size = sizeof(struct bnxt),
1202 };
1203
1204 DRIVER_REGISTER_PCI(net_bnxt, bnxt_rte_pmd.pci_drv);
1205 DRIVER_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);