drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29 #include "bnxt_util.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  37
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  42 #define BROADCOM_DEV_ID_57301 0x16c8
  43 #define BROADCOM_DEV_ID_57302 0x16c9
  44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  47 #define BROADCOM_DEV_ID_NS2 0x16cd
  48 #define BROADCOM_DEV_ID_57311 0x16ce
  49 #define BROADCOM_DEV_ID_57312 0x16cf
  50 #define BROADCOM_DEV_ID_57402 0x16d0
  51 #define BROADCOM_DEV_ID_57404 0x16d1
  52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  56 #define BROADCOM_DEV_ID_57412 0x16d6
  57 #define BROADCOM_DEV_ID_57414 0x16d7
  58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  61 #define BROADCOM_DEV_ID_57412_MF 0x16de
  62 #define BROADCOM_DEV_ID_57314 0x16df
  63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  74 #define BROADCOM_DEV_ID_57508 0x1750
  75 #define BROADCOM_DEV_ID_57504 0x1751
  76 #define BROADCOM_DEV_ID_57502 0x1752
  77 #define BROADCOM_DEV_ID_57500_VF1 0x1806
  78 #define BROADCOM_DEV_ID_57500_VF2 0x1807
  79 #define BROADCOM_DEV_ID_58802 0xd802
  80 #define BROADCOM_DEV_ID_58804 0xd804
  81 #define BROADCOM_DEV_ID_58808 0x16f0
  82 #define BROADCOM_DEV_ID_58802_VF 0xd800
  83
  84 static const struct rte_pci_id bnxt_pci_id_map[] = {
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  86                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  88                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 130         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
 131         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
 132         { .vendor_id = 0, /* sentinel */ },
 133 };
 134
 135 #define BNXT_ETH_RSS_SUPPORT (  \
 136         ETH_RSS_IPV4 |          \
 137         ETH_RSS_NONFRAG_IPV4_TCP |      \
 138         ETH_RSS_NONFRAG_IPV4_UDP |      \
 139         ETH_RSS_IPV6 |          \
 140         ETH_RSS_NONFRAG_IPV6_TCP |      \
 141         ETH_RSS_NONFRAG_IPV6_UDP)
 142
 143 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 144                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 145                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 146                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 147                                      DEV_TX_OFFLOAD_TCP_TSO | \
 148                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 149                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 150                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 152                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 153                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 154
 155 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 156                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 157                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 158                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 159                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 160                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 161                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 162                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 163                                      DEV_RX_OFFLOAD_TCP_LRO)
 164
 165 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 166 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 167 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 168 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 169
 170 /***********************/
 171
 172 /*
 173  * High level utility functions
 174  */
 175
 176 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 177 {
 178         if (!BNXT_CHIP_THOR(bp))
 179                 return 1;
 180
 181         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 182                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 183                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 184 }
 185
 186 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 187 {
 188         if (!BNXT_CHIP_THOR(bp))
 189                 return HW_HASH_INDEX_SIZE;
 190
 191         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 192 }
 193
 194 static void bnxt_free_mem(struct bnxt *bp)
 195 {
 196         bnxt_free_filter_mem(bp);
 197         bnxt_free_vnic_attributes(bp);
 198         bnxt_free_vnic_mem(bp);
 199
 200         bnxt_free_stats(bp);
 201         bnxt_free_tx_rings(bp);
 202         bnxt_free_rx_rings(bp);
 203         bnxt_free_async_cp_ring(bp);
 204 }
 205
 206 static int bnxt_alloc_mem(struct bnxt *bp)
 207 {
 208         int rc;
 209
 210         rc = bnxt_alloc_async_ring_struct(bp);
 211         if (rc)
 212                 goto alloc_mem_err;
 213
 214         rc = bnxt_alloc_vnic_mem(bp);
 215         if (rc)
 216                 goto alloc_mem_err;
 217
 218         rc = bnxt_alloc_vnic_attributes(bp);
 219         if (rc)
 220                 goto alloc_mem_err;
 221
 222         rc = bnxt_alloc_filter_mem(bp);
 223         if (rc)
 224                 goto alloc_mem_err;
 225
 226         rc = bnxt_alloc_async_cp_ring(bp);
 227         if (rc)
 228                 goto alloc_mem_err;
 229
 230         return 0;
 231
 232 alloc_mem_err:
 233         bnxt_free_mem(bp);
 234         return rc;
 235 }
 236
 237 static int bnxt_init_chip(struct bnxt *bp)
 238 {
 239         struct bnxt_rx_queue *rxq;
 240         struct rte_eth_link new;
 241         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 242         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 243         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 244         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 245         uint32_t intr_vector = 0;
 246         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 247         uint32_t vec = BNXT_MISC_VEC_ID;
 248         unsigned int i, j;
 249         int rc;
 250
 251         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 252                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 253                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 254                 bp->flags |= BNXT_FLAG_JUMBO;
 255         } else {
 256                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 257                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 258                 bp->flags &= ~BNXT_FLAG_JUMBO;
 259         }
 260
 261         /* THOR does not support ring groups.
 262          * But we will use the array to save RSS context IDs.
 263          */
 264         if (BNXT_CHIP_THOR(bp))
 265                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 266
 267         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 268         if (rc) {
 269                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 270                 goto err_out;
 271         }
 272
 273         rc = bnxt_alloc_hwrm_rings(bp);
 274         if (rc) {
 275                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 276                 goto err_out;
 277         }
 278
 279         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 280         if (rc) {
 281                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 282                 goto err_out;
 283         }
 284
 285         rc = bnxt_mq_rx_configure(bp);
 286         if (rc) {
 287                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 288                 goto err_out;
 289         }
 290
 291         /* VNIC configuration */
 292         for (i = 0; i < bp->nr_vnics; i++) {
 293                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 294                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 295                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 296
 297                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 298                 if (!vnic->fw_grp_ids) {
 299                         PMD_DRV_LOG(ERR,
 300                                     "Failed to alloc %d bytes for group ids\n",
 301                                     size);
 302                         rc = -ENOMEM;
 303                         goto err_out;
 304                 }
 305                 memset(vnic->fw_grp_ids, -1, size);
 306
 307                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 308                             i, vnic, vnic->fw_grp_ids);
 309
 310                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 311                 if (rc) {
 312                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 313                                 i, rc);
 314                         goto err_out;
 315                 }
 316
 317                 /* Alloc RSS context only if RSS mode is enabled */
 318                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 319                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 320
 321                         rc = 0;
 322                         for (j = 0; j < nr_ctxs; j++) {
 323                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 324                                 if (rc)
 325                                         break;
 326                         }
 327                         if (rc) {
 328                                 PMD_DRV_LOG(ERR,
 329                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 330                                   i, j, rc);
 331                                 goto err_out;
 332                         }
 333                         vnic->num_lb_ctxts = nr_ctxs;
 334                 }
 335
 336                 /*
 337                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 338                  * setting is not available at this time, it will not be
 339                  * configured correctly in the CFA.
 340                  */
 341                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 342                         vnic->vlan_strip = true;
 343                 else
 344                         vnic->vlan_strip = false;
 345
 346                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 347                 if (rc) {
 348                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 349                                 i, rc);
 350                         goto err_out;
 351                 }
 352
 353                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 354                 if (rc) {
 355                         PMD_DRV_LOG(ERR,
 356                                 "HWRM vnic %d filter failure rc: %x\n",
 357                                 i, rc);
 358                         goto err_out;
 359                 }
 360
 361                 for (j = 0; j < bp->rx_nr_rings; j++) {
 362                         rxq = bp->eth_dev->data->rx_queues[j];
 363
 364                         PMD_DRV_LOG(DEBUG,
 365                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 366                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 367
 368                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 369                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 370                 }
 371
 372                 rc = bnxt_vnic_rss_configure(bp, vnic);
 373                 if (rc) {
 374                         PMD_DRV_LOG(ERR,
 375                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 376                         goto err_out;
 377                 }
 378
 379                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 380
 381                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 382                     DEV_RX_OFFLOAD_TCP_LRO)
 383                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 384                 else
 385                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 386         }
 387         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 388         if (rc) {
 389                 PMD_DRV_LOG(ERR,
 390                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 391                 goto err_out;
 392         }
 393
 394         /* check and configure queue intr-vector mapping */
 395         if ((rte_intr_cap_multiple(intr_handle) ||
 396              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 397             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 398                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 399                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 400                 if (intr_vector > bp->rx_cp_nr_rings) {
 401                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 402                                         bp->rx_cp_nr_rings);
 403                         return -ENOTSUP;
 404                 }
 405                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 406                 if (rc)
 407                         return rc;
 408         }
 409
 410         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 411                 intr_handle->intr_vec =
 412                         rte_zmalloc("intr_vec",
 413                                     bp->eth_dev->data->nb_rx_queues *
 414                                     sizeof(int), 0);
 415                 if (intr_handle->intr_vec == NULL) {
 416                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 417                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 418                         rc = -ENOMEM;
 419                         goto err_disable;
 420                 }
 421                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 422                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 423                          intr_handle->intr_vec, intr_handle->nb_efd,
 424                         intr_handle->max_intr);
 425                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 426                      queue_id++) {
 427                         intr_handle->intr_vec[queue_id] =
 428                                                         vec + BNXT_RX_VEC_START;
 429                         if (vec < base + intr_handle->nb_efd - 1)
 430                                 vec++;
 431                 }
 432         }
 433
 434         /* enable uio/vfio intr/eventfd mapping */
 435         rc = rte_intr_enable(intr_handle);
 436         if (rc)
 437                 goto err_free;
 438
 439         rc = bnxt_get_hwrm_link_config(bp, &new);
 440         if (rc) {
 441                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 442                 goto err_free;
 443         }
 444
 445         if (!bp->link_info.link_up) {
 446                 rc = bnxt_set_hwrm_link_config(bp, true);
 447                 if (rc) {
 448                         PMD_DRV_LOG(ERR,
 449                                 "HWRM link config failure rc: %x\n", rc);
 450                         goto err_free;
 451                 }
 452         }
 453         bnxt_print_link_info(bp->eth_dev);
 454
 455         return 0;
 456
 457 err_free:
 458         rte_free(intr_handle->intr_vec);
 459 err_disable:
 460         rte_intr_efd_disable(intr_handle);
 461 err_out:
 462         /* Some of the error status returned by FW may not be from errno.h */
 463         if (rc > 0)
 464                 rc = -EIO;
 465
 466         return rc;
 467 }
 468
 469 static int bnxt_shutdown_nic(struct bnxt *bp)
 470 {
 471         bnxt_free_all_hwrm_resources(bp);
 472         bnxt_free_all_filters(bp);
 473         bnxt_free_all_vnics(bp);
 474         return 0;
 475 }
 476
 477 static int bnxt_init_nic(struct bnxt *bp)
 478 {
 479         int rc;
 480
 481         if (BNXT_HAS_RING_GRPS(bp)) {
 482                 rc = bnxt_init_ring_grps(bp);
 483                 if (rc)
 484                         return rc;
 485         }
 486
 487         bnxt_init_vnics(bp);
 488         bnxt_init_filters(bp);
 489
 490         return 0;
 491 }
 492
 493 /*
 494  * Device configuration and status function
 495  */
 496
 497 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 498                                 struct rte_eth_dev_info *dev_info)
 499 {
 500         struct bnxt *bp = eth_dev->data->dev_private;
 501         uint16_t max_vnics, i, j, vpool, vrxq;
 502         unsigned int max_rx_rings;
 503
 504         /* MAC Specifics */
 505         dev_info->max_mac_addrs = bp->max_l2_ctx;
 506         dev_info->max_hash_mac_addrs = 0;
 507
 508         /* PF/VF specifics */
 509         if (BNXT_PF(bp))
 510                 dev_info->max_vfs = bp->pdev->max_vfs;
 511         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 512         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 513         dev_info->max_rx_queues = max_rx_rings;
 514         dev_info->max_tx_queues = max_rx_rings;
 515         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 516         dev_info->hash_key_size = 40;
 517         max_vnics = bp->max_vnics;
 518
 519         /* Fast path specifics */
 520         dev_info->min_rx_bufsize = 1;
 521         dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
 522                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
 523
 524         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 525         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 526                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 527         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 528         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 529
 530         /* *INDENT-OFF* */
 531         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 532                 .rx_thresh = {
 533                         .pthresh = 8,
 534                         .hthresh = 8,
 535                         .wthresh = 0,
 536                 },
 537                 .rx_free_thresh = 32,
 538                 /* If no descriptors available, pkts are dropped by default */
 539                 .rx_drop_en = 1,
 540         };
 541
 542         dev_info->default_txconf = (struct rte_eth_txconf) {
 543                 .tx_thresh = {
 544                         .pthresh = 32,
 545                         .hthresh = 0,
 546                         .wthresh = 0,
 547                 },
 548                 .tx_free_thresh = 32,
 549                 .tx_rs_thresh = 32,
 550         };
 551         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 552
 553         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 554         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 555         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 556         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 557         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 558
 559         /* *INDENT-ON* */
 560
 561         /*
 562          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 563          *       need further investigation.
 564          */
 565
 566         /* VMDq resources */
 567         vpool = 64; /* ETH_64_POOLS */
 568         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 569         for (i = 0; i < 4; vpool >>= 1, i++) {
 570                 if (max_vnics > vpool) {
 571                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 572                                 if (dev_info->max_rx_queues > vrxq) {
 573                                         if (vpool > vrxq)
 574                                                 vpool = vrxq;
 575                                         goto found;
 576                                 }
 577                         }
 578                         /* Not enough resources to support VMDq */
 579                         break;
 580                 }
 581         }
 582         /* Not enough resources to support VMDq */
 583         vpool = 0;
 584         vrxq = 0;
 585 found:
 586         dev_info->max_vmdq_pools = vpool;
 587         dev_info->vmdq_queue_num = vrxq;
 588
 589         dev_info->vmdq_pool_base = 0;
 590         dev_info->vmdq_queue_base = 0;
 591
 592         return 0;
 593 }
 594
 595 /* Configure the device based on the configuration provided */
 596 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 597 {
 598         struct bnxt *bp = eth_dev->data->dev_private;
 599         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 600         int rc;
 601
 602         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 603         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 604         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 605         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 606
 607         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 608                 rc = bnxt_hwrm_check_vf_rings(bp);
 609                 if (rc) {
 610                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 611                         return -ENOSPC;
 612                 }
 613
 614                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 615                 if (rc) {
 616                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 617                         return -ENOSPC;
 618                 }
 619         } else {
 620                 /* legacy driver needs to get updated values */
 621                 rc = bnxt_hwrm_func_qcaps(bp);
 622                 if (rc) {
 623                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 624                         return rc;
 625                 }
 626         }
 627
 628         /* Inherit new configurations */
 629         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 630             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 631             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 632                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 633             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 634             bp->max_stat_ctx)
 635                 goto resource_error;
 636
 637         if (BNXT_HAS_RING_GRPS(bp) &&
 638             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 639                 goto resource_error;
 640
 641         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 642             bp->max_vnics < eth_dev->data->nb_rx_queues)
 643                 goto resource_error;
 644
 645         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 646         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 647
 648         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 649                 eth_dev->data->mtu =
 650                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 651                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 652                         BNXT_NUM_VLANS;
 653                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 654         }
 655         return 0;
 656
 657 resource_error:
 658         PMD_DRV_LOG(ERR,
 659                     "Insufficient resources to support requested config\n");
 660         PMD_DRV_LOG(ERR,
 661                     "Num Queues Requested: Tx %d, Rx %d\n",
 662                     eth_dev->data->nb_tx_queues,
 663                     eth_dev->data->nb_rx_queues);
 664         PMD_DRV_LOG(ERR,
 665                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 666                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 667                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 668         return -ENOSPC;
 669 }
 670
 671 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 672 {
 673         struct rte_eth_link *link = &eth_dev->data->dev_link;
 674
 675         if (link->link_status)
 676                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 677                         eth_dev->data->port_id,
 678                         (uint32_t)link->link_speed,
 679                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 680                         ("full-duplex") : ("half-duplex\n"));
 681         else
 682                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 683                         eth_dev->data->port_id);
 684 }
 685
 686 /*
 687  * Determine whether the current configuration requires support for scattered
 688  * receive; return 1 if scattered receive is required and 0 if not.
 689  */
 690 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 691 {
 692         uint16_t buf_size;
 693         int i;
 694
 695         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 696                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 697
 698                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 699                                       RTE_PKTMBUF_HEADROOM);
 700                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 701                         return 1;
 702         }
 703         return 0;
 704 }
 705
 706 static eth_rx_burst_t
 707 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 708 {
 709 #ifdef RTE_ARCH_X86
 710         /*
 711          * Vector mode receive can be enabled only if scatter rx is not
 712          * in use and rx offloads are limited to VLAN stripping and
 713          * CRC stripping.
 714          */
 715         if (!eth_dev->data->scattered_rx &&
 716             !(eth_dev->data->dev_conf.rxmode.offloads &
 717               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 718                 DEV_RX_OFFLOAD_KEEP_CRC |
 719                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 720                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 721                 DEV_RX_OFFLOAD_UDP_CKSUM |
 722                 DEV_RX_OFFLOAD_TCP_CKSUM |
 723                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 724                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 725                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 726                             eth_dev->data->port_id);
 727                 return bnxt_recv_pkts_vec;
 728         }
 729         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 730                     eth_dev->data->port_id);
 731         PMD_DRV_LOG(INFO,
 732                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 733                     eth_dev->data->port_id,
 734                     eth_dev->data->scattered_rx,
 735                     eth_dev->data->dev_conf.rxmode.offloads);
 736 #endif
 737         return bnxt_recv_pkts;
 738 }
 739
 740 static eth_tx_burst_t
 741 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 742 {
 743 #ifdef RTE_ARCH_X86
 744         /*
 745          * Vector mode transmit can be enabled only if not using scatter rx
 746          * or tx offloads.
 747          */
 748         if (!eth_dev->data->scattered_rx &&
 749             !eth_dev->data->dev_conf.txmode.offloads) {
 750                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 751                             eth_dev->data->port_id);
 752                 return bnxt_xmit_pkts_vec;
 753         }
 754         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 755                     eth_dev->data->port_id);
 756         PMD_DRV_LOG(INFO,
 757                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 758                     eth_dev->data->port_id,
 759                     eth_dev->data->scattered_rx,
 760                     eth_dev->data->dev_conf.txmode.offloads);
 761 #endif
 762         return bnxt_xmit_pkts;
 763 }
 764
 765 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 766 {
 767         struct bnxt *bp = eth_dev->data->dev_private;
 768         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 769         int vlan_mask = 0;
 770         int rc;
 771
 772         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 773                 PMD_DRV_LOG(ERR,
 774                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 775                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 776         }
 777
 778         rc = bnxt_init_chip(bp);
 779         if (rc)
 780                 goto error;
 781
 782         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 783
 784         bnxt_link_update_op(eth_dev, 1);
 785
 786         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 787                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 788         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 789                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 790         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 791         if (rc)
 792                 goto error;
 793
 794         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 795         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 796         bnxt_enable_int(bp);
 797         bp->flags |= BNXT_FLAG_INIT_DONE;
 798         bp->dev_stopped = 0;
 799         return 0;
 800
 801 error:
 802         bnxt_shutdown_nic(bp);
 803         bnxt_free_tx_mbufs(bp);
 804         bnxt_free_rx_mbufs(bp);
 805         return rc;
 806 }
 807
 808 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 809 {
 810         struct bnxt *bp = eth_dev->data->dev_private;
 811         int rc = 0;
 812
 813         if (!bp->link_info.link_up)
 814                 rc = bnxt_set_hwrm_link_config(bp, true);
 815         if (!rc)
 816                 eth_dev->data->dev_link.link_status = 1;
 817
 818         bnxt_print_link_info(eth_dev);
 819         return 0;
 820 }
 821
 822 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 823 {
 824         struct bnxt *bp = eth_dev->data->dev_private;
 825
 826         eth_dev->data->dev_link.link_status = 0;
 827         bnxt_set_hwrm_link_config(bp, false);
 828         bp->link_info.link_up = 0;
 829
 830         return 0;
 831 }
 832
 833 /* Unload the driver, release resources */
 834 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 835 {
 836         struct bnxt *bp = eth_dev->data->dev_private;
 837         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 838         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 839
 840         bnxt_disable_int(bp);
 841
 842         /* disable uio/vfio intr/eventfd mapping */
 843         rte_intr_disable(intr_handle);
 844
 845         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 846         if (bp->eth_dev->data->dev_started) {
 847                 /* TBD: STOP HW queues DMA */
 848                 eth_dev->data->dev_link.link_status = 0;
 849         }
 850         bnxt_set_hwrm_link_config(bp, false);
 851
 852         /* Clean queue intr-vector mapping */
 853         rte_intr_efd_disable(intr_handle);
 854         if (intr_handle->intr_vec != NULL) {
 855                 rte_free(intr_handle->intr_vec);
 856                 intr_handle->intr_vec = NULL;
 857         }
 858
 859         bnxt_hwrm_port_clr_stats(bp);
 860         bnxt_free_tx_mbufs(bp);
 861         bnxt_free_rx_mbufs(bp);
 862         bnxt_shutdown_nic(bp);
 863         bp->dev_stopped = 1;
 864 }
 865
 866 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 867 {
 868         struct bnxt *bp = eth_dev->data->dev_private;
 869
 870         if (bp->dev_stopped == 0)
 871                 bnxt_dev_stop_op(eth_dev);
 872
 873         if (eth_dev->data->mac_addrs != NULL) {
 874                 rte_free(eth_dev->data->mac_addrs);
 875                 eth_dev->data->mac_addrs = NULL;
 876         }
 877         if (bp->grp_info != NULL) {
 878                 rte_free(bp->grp_info);
 879                 bp->grp_info = NULL;
 880         }
 881
 882         bnxt_dev_uninit(eth_dev);
 883 }
 884
 885 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 886                                     uint32_t index)
 887 {
 888         struct bnxt *bp = eth_dev->data->dev_private;
 889         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 890         struct bnxt_vnic_info *vnic;
 891         struct bnxt_filter_info *filter, *temp_filter;
 892         uint32_t i;
 893
 894         /*
 895          * Loop through all VNICs from the specified filter flow pools to
 896          * remove the corresponding MAC addr filter
 897          */
 898         for (i = 0; i < bp->nr_vnics; i++) {
 899                 if (!(pool_mask & (1ULL << i)))
 900                         continue;
 901
 902                 vnic = &bp->vnic_info[i];
 903                 filter = STAILQ_FIRST(&vnic->filter);
 904                 while (filter) {
 905                         temp_filter = STAILQ_NEXT(filter, next);
 906                         if (filter->mac_index == index) {
 907                                 STAILQ_REMOVE(&vnic->filter, filter,
 908                                                 bnxt_filter_info, next);
 909                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 910                                 filter->mac_index = INVALID_MAC_INDEX;
 911                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 912                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 913                                                    filter, next);
 914                         }
 915                         filter = temp_filter;
 916                 }
 917         }
 918 }
 919
 920 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 921                                 struct rte_ether_addr *mac_addr,
 922                                 uint32_t index, uint32_t pool)
 923 {
 924         struct bnxt *bp = eth_dev->data->dev_private;
 925         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
 926         struct bnxt_filter_info *filter;
 927         int rc = 0;
 928
 929         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
 930                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
 931                 return -ENOTSUP;
 932         }
 933
 934         if (!vnic) {
 935                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
 936                 return -EINVAL;
 937         }
 938         /* Attach requested MAC address to the new l2_filter */
 939         STAILQ_FOREACH(filter, &vnic->filter, next) {
 940                 if (filter->mac_index == index) {
 941                         PMD_DRV_LOG(ERR,
 942                                 "MAC addr already existed for pool %d\n", pool);
 943                         return 0;
 944                 }
 945         }
 946         filter = bnxt_alloc_filter(bp);
 947         if (!filter) {
 948                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
 949                 return -ENODEV;
 950         }
 951
 952         filter->mac_index = index;
 953         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
 954
 955         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 956         if (!rc) {
 957                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 958         } else {
 959                 filter->mac_index = INVALID_MAC_INDEX;
 960                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 961                 bnxt_free_filter(bp, filter);
 962         }
 963
 964         return rc;
 965 }
 966
 967 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 968 {
 969         int rc = 0;
 970         struct bnxt *bp = eth_dev->data->dev_private;
 971         struct rte_eth_link new;
 972         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 973
 974         memset(&new, 0, sizeof(new));
 975         do {
 976                 /* Retrieve link info from hardware */
 977                 rc = bnxt_get_hwrm_link_config(bp, &new);
 978                 if (rc) {
 979                         new.link_speed = ETH_LINK_SPEED_100M;
 980                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 981                         PMD_DRV_LOG(ERR,
 982                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 983                         goto out;
 984                 }
 985
 986                 if (!wait_to_complete || new.link_status)
 987                         break;
 988
 989                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 990         } while (cnt--);
 991
 992 out:
 993         /* Timed out or success */
 994         if (new.link_status != eth_dev->data->dev_link.link_status ||
 995         new.link_speed != eth_dev->data->dev_link.link_speed) {
 996                 memcpy(&eth_dev->data->dev_link, &new,
 997                         sizeof(struct rte_eth_link));
 998
 999                 _rte_eth_dev_callback_process(eth_dev,
1000                                               RTE_ETH_EVENT_INTR_LSC,
1001                                               NULL);
1002
1003                 bnxt_print_link_info(eth_dev);
1004         }
1005
1006         return rc;
1007 }
1008
1009 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1010 {
1011         struct bnxt *bp = eth_dev->data->dev_private;
1012         struct bnxt_vnic_info *vnic;
1013         uint32_t old_flags;
1014         int rc;
1015
1016         if (bp->vnic_info == NULL)
1017                 return 0;
1018
1019         vnic = &bp->vnic_info[0];
1020
1021         old_flags = vnic->flags;
1022         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1023         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1024         if (rc != 0)
1025                 vnic->flags = old_flags;
1026
1027         return rc;
1028 }
1029
1030 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1031 {
1032         struct bnxt *bp = eth_dev->data->dev_private;
1033         struct bnxt_vnic_info *vnic;
1034         uint32_t old_flags;
1035         int rc;
1036
1037         if (bp->vnic_info == NULL)
1038                 return 0;
1039
1040         vnic = &bp->vnic_info[0];
1041
1042         old_flags = vnic->flags;
1043         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1044         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1045         if (rc != 0)
1046                 vnic->flags = old_flags;
1047
1048         return rc;
1049 }
1050
1051 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1052 {
1053         struct bnxt *bp = eth_dev->data->dev_private;
1054         struct bnxt_vnic_info *vnic;
1055
1056         if (bp->vnic_info == NULL)
1057                 return;
1058
1059         vnic = &bp->vnic_info[0];
1060
1061         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1062         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1063 }
1064
1065 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1066 {
1067         struct bnxt *bp = eth_dev->data->dev_private;
1068         struct bnxt_vnic_info *vnic;
1069
1070         if (bp->vnic_info == NULL)
1071                 return;
1072
1073         vnic = &bp->vnic_info[0];
1074
1075         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1076         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1077 }
1078
1079 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1080 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1081 {
1082         if (qid >= bp->rx_nr_rings)
1083                 return NULL;
1084
1085         return bp->eth_dev->data->rx_queues[qid];
1086 }
1087
1088 /* Return rxq corresponding to a given rss table ring/group ID. */
1089 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1090 {
1091         struct bnxt_rx_queue *rxq;
1092         unsigned int i;
1093
1094         if (!BNXT_HAS_RING_GRPS(bp)) {
1095                 for (i = 0; i < bp->rx_nr_rings; i++) {
1096                         rxq = bp->eth_dev->data->rx_queues[i];
1097                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1098                                 return rxq->index;
1099                 }
1100         } else {
1101                 for (i = 0; i < bp->rx_nr_rings; i++) {
1102                         if (bp->grp_info[i].fw_grp_id == fwr)
1103                                 return i;
1104                 }
1105         }
1106
1107         return INVALID_HW_RING_ID;
1108 }
1109
1110 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1111                             struct rte_eth_rss_reta_entry64 *reta_conf,
1112                             uint16_t reta_size)
1113 {
1114         struct bnxt *bp = eth_dev->data->dev_private;
1115         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1116         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1117         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1118         uint16_t idx, sft;
1119         int i;
1120
1121         if (!vnic->rss_table)
1122                 return -EINVAL;
1123
1124         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1125                 return -EINVAL;
1126
1127         if (reta_size != tbl_size) {
1128                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1129                         "(%d) must equal the size supported by the hardware "
1130                         "(%d)\n", reta_size, tbl_size);
1131                 return -EINVAL;
1132         }
1133
1134         for (i = 0; i < reta_size; i++) {
1135                 struct bnxt_rx_queue *rxq;
1136
1137                 idx = i / RTE_RETA_GROUP_SIZE;
1138                 sft = i % RTE_RETA_GROUP_SIZE;
1139
1140                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1141                         continue;
1142
1143                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1144                 if (!rxq) {
1145                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1146                         return -EINVAL;
1147                 }
1148
1149                 if (BNXT_CHIP_THOR(bp)) {
1150                         vnic->rss_table[i * 2] =
1151                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1152                         vnic->rss_table[i * 2 + 1] =
1153                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1154                 } else {
1155                         vnic->rss_table[i] =
1156                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1157                 }
1158
1159                 vnic->rss_table[i] =
1160                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1161         }
1162
1163         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1164         return 0;
1165 }
1166
1167 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1168                               struct rte_eth_rss_reta_entry64 *reta_conf,
1169                               uint16_t reta_size)
1170 {
1171         struct bnxt *bp = eth_dev->data->dev_private;
1172         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1173         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1174         uint16_t idx, sft, i;
1175
1176         /* Retrieve from the default VNIC */
1177         if (!vnic)
1178                 return -EINVAL;
1179         if (!vnic->rss_table)
1180                 return -EINVAL;
1181
1182         if (reta_size != tbl_size) {
1183                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1184                         "(%d) must equal the size supported by the hardware "
1185                         "(%d)\n", reta_size, tbl_size);
1186                 return -EINVAL;
1187         }
1188
1189         for (idx = 0, i = 0; i < reta_size; i++) {
1190                 idx = i / RTE_RETA_GROUP_SIZE;
1191                 sft = i % RTE_RETA_GROUP_SIZE;
1192
1193                 if (reta_conf[idx].mask & (1ULL << sft)) {
1194                         uint16_t qid;
1195
1196                         if (BNXT_CHIP_THOR(bp))
1197                                 qid = bnxt_rss_to_qid(bp,
1198                                                       vnic->rss_table[i * 2]);
1199                         else
1200                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1201
1202                         if (qid == INVALID_HW_RING_ID) {
1203                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1204                                 return -EINVAL;
1205                         }
1206                         reta_conf[idx].reta[sft] = qid;
1207                 }
1208         }
1209
1210         return 0;
1211 }
1212
1213 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1214                                    struct rte_eth_rss_conf *rss_conf)
1215 {
1216         struct bnxt *bp = eth_dev->data->dev_private;
1217         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1218         struct bnxt_vnic_info *vnic;
1219         uint16_t hash_type = 0;
1220         unsigned int i;
1221
1222         /*
1223          * If RSS enablement were different than dev_configure,
1224          * then return -EINVAL
1225          */
1226         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1227                 if (!rss_conf->rss_hf)
1228                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1229         } else {
1230                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1231                         return -EINVAL;
1232         }
1233
1234         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1235         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1236
1237         if (rss_conf->rss_hf & ETH_RSS_IPV4)
1238                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1239         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1240                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1241         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1242                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1243         if (rss_conf->rss_hf & ETH_RSS_IPV6)
1244                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1245         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1246                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1247         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1248                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1249
1250         /* Update the RSS VNIC(s) */
1251         for (i = 0; i < bp->nr_vnics; i++) {
1252                 vnic = &bp->vnic_info[i];
1253                 vnic->hash_type = hash_type;
1254
1255                 /*
1256                  * Use the supplied key if the key length is
1257                  * acceptable and the rss_key is not NULL
1258                  */
1259                 if (rss_conf->rss_key &&
1260                     rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1261                         memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1262                                rss_conf->rss_key_len);
1263
1264                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1265         }
1266         return 0;
1267 }
1268
1269 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1270                                      struct rte_eth_rss_conf *rss_conf)
1271 {
1272         struct bnxt *bp = eth_dev->data->dev_private;
1273         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1274         int len;
1275         uint32_t hash_types;
1276
1277         /* RSS configuration is the same for all VNICs */
1278         if (vnic && vnic->rss_hash_key) {
1279                 if (rss_conf->rss_key) {
1280                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1281                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1282                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1283                 }
1284
1285                 hash_types = vnic->hash_type;
1286                 rss_conf->rss_hf = 0;
1287                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1288                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1289                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1290                 }
1291                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1292                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1293                         hash_types &=
1294                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1295                 }
1296                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1297                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1298                         hash_types &=
1299                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1300                 }
1301                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1302                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1303                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1304                 }
1305                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1306                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1307                         hash_types &=
1308                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1309                 }
1310                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1311                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1312                         hash_types &=
1313                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1314                 }
1315                 if (hash_types) {
1316                         PMD_DRV_LOG(ERR,
1317                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1318                                 vnic->hash_type);
1319                         return -ENOTSUP;
1320                 }
1321         } else {
1322                 rss_conf->rss_hf = 0;
1323         }
1324         return 0;
1325 }
1326
1327 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1328                                struct rte_eth_fc_conf *fc_conf)
1329 {
1330         struct bnxt *bp = dev->data->dev_private;
1331         struct rte_eth_link link_info;
1332         int rc;
1333
1334         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1335         if (rc)
1336                 return rc;
1337
1338         memset(fc_conf, 0, sizeof(*fc_conf));
1339         if (bp->link_info.auto_pause)
1340                 fc_conf->autoneg = 1;
1341         switch (bp->link_info.pause) {
1342         case 0:
1343                 fc_conf->mode = RTE_FC_NONE;
1344                 break;
1345         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1346                 fc_conf->mode = RTE_FC_TX_PAUSE;
1347                 break;
1348         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1349                 fc_conf->mode = RTE_FC_RX_PAUSE;
1350                 break;
1351         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1352                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1353                 fc_conf->mode = RTE_FC_FULL;
1354                 break;
1355         }
1356         return 0;
1357 }
1358
1359 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1360                                struct rte_eth_fc_conf *fc_conf)
1361 {
1362         struct bnxt *bp = dev->data->dev_private;
1363
1364         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1365                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1366                 return -ENOTSUP;
1367         }
1368
1369         switch (fc_conf->mode) {
1370         case RTE_FC_NONE:
1371                 bp->link_info.auto_pause = 0;
1372                 bp->link_info.force_pause = 0;
1373                 break;
1374         case RTE_FC_RX_PAUSE:
1375                 if (fc_conf->autoneg) {
1376                         bp->link_info.auto_pause =
1377                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1378                         bp->link_info.force_pause = 0;
1379                 } else {
1380                         bp->link_info.auto_pause = 0;
1381                         bp->link_info.force_pause =
1382                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1383                 }
1384                 break;
1385         case RTE_FC_TX_PAUSE:
1386                 if (fc_conf->autoneg) {
1387                         bp->link_info.auto_pause =
1388                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1389                         bp->link_info.force_pause = 0;
1390                 } else {
1391                         bp->link_info.auto_pause = 0;
1392                         bp->link_info.force_pause =
1393                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1394                 }
1395                 break;
1396         case RTE_FC_FULL:
1397                 if (fc_conf->autoneg) {
1398                         bp->link_info.auto_pause =
1399                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1400                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1401                         bp->link_info.force_pause = 0;
1402                 } else {
1403                         bp->link_info.auto_pause = 0;
1404                         bp->link_info.force_pause =
1405                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1406                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1407                 }
1408                 break;
1409         }
1410         return bnxt_set_hwrm_link_config(bp, true);
1411 }
1412
1413 /* Add UDP tunneling port */
1414 static int
1415 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1416                          struct rte_eth_udp_tunnel *udp_tunnel)
1417 {
1418         struct bnxt *bp = eth_dev->data->dev_private;
1419         uint16_t tunnel_type = 0;
1420         int rc = 0;
1421
1422         switch (udp_tunnel->prot_type) {
1423         case RTE_TUNNEL_TYPE_VXLAN:
1424                 if (bp->vxlan_port_cnt) {
1425                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1426                                 udp_tunnel->udp_port);
1427                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1428                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1429                                 return -ENOSPC;
1430                         }
1431                         bp->vxlan_port_cnt++;
1432                         return 0;
1433                 }
1434                 tunnel_type =
1435                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1436                 bp->vxlan_port_cnt++;
1437                 break;
1438         case RTE_TUNNEL_TYPE_GENEVE:
1439                 if (bp->geneve_port_cnt) {
1440                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1441                                 udp_tunnel->udp_port);
1442                         if (bp->geneve_port != udp_tunnel->udp_port) {
1443                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1444                                 return -ENOSPC;
1445                         }
1446                         bp->geneve_port_cnt++;
1447                         return 0;
1448                 }
1449                 tunnel_type =
1450                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1451                 bp->geneve_port_cnt++;
1452                 break;
1453         default:
1454                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1455                 return -ENOTSUP;
1456         }
1457         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1458                                              tunnel_type);
1459         return rc;
1460 }
1461
1462 static int
1463 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1464                          struct rte_eth_udp_tunnel *udp_tunnel)
1465 {
1466         struct bnxt *bp = eth_dev->data->dev_private;
1467         uint16_t tunnel_type = 0;
1468         uint16_t port = 0;
1469         int rc = 0;
1470
1471         switch (udp_tunnel->prot_type) {
1472         case RTE_TUNNEL_TYPE_VXLAN:
1473                 if (!bp->vxlan_port_cnt) {
1474                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1475                         return -EINVAL;
1476                 }
1477                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1478                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1479                                 udp_tunnel->udp_port, bp->vxlan_port);
1480                         return -EINVAL;
1481                 }
1482                 if (--bp->vxlan_port_cnt)
1483                         return 0;
1484
1485                 tunnel_type =
1486                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1487                 port = bp->vxlan_fw_dst_port_id;
1488                 break;
1489         case RTE_TUNNEL_TYPE_GENEVE:
1490                 if (!bp->geneve_port_cnt) {
1491                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1492                         return -EINVAL;
1493                 }
1494                 if (bp->geneve_port != udp_tunnel->udp_port) {
1495                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1496                                 udp_tunnel->udp_port, bp->geneve_port);
1497                         return -EINVAL;
1498                 }
1499                 if (--bp->geneve_port_cnt)
1500                         return 0;
1501
1502                 tunnel_type =
1503                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1504                 port = bp->geneve_fw_dst_port_id;
1505                 break;
1506         default:
1507                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1508                 return -ENOTSUP;
1509         }
1510
1511         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1512         if (!rc) {
1513                 if (tunnel_type ==
1514                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1515                         bp->vxlan_port = 0;
1516                 if (tunnel_type ==
1517                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1518                         bp->geneve_port = 0;
1519         }
1520         return rc;
1521 }
1522
1523 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1524 {
1525         struct bnxt_filter_info *filter;
1526         struct bnxt_vnic_info *vnic;
1527         int rc = 0;
1528         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1529
1530         /* if VLAN exists && VLAN matches vlan_id
1531          *      remove the MAC+VLAN filter
1532          *      add a new MAC only filter
1533          * else
1534          *      VLAN filter doesn't exist, just skip and continue
1535          */
1536         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1537         filter = STAILQ_FIRST(&vnic->filter);
1538         while (filter) {
1539                 /* Search for this matching MAC+VLAN filter */
1540                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1541                     !memcmp(filter->l2_addr,
1542                             bp->mac_addr,
1543                             RTE_ETHER_ADDR_LEN)) {
1544                         /* Delete the filter */
1545                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1546                         if (rc)
1547                                 return rc;
1548                         STAILQ_REMOVE(&vnic->filter, filter,
1549                                       bnxt_filter_info, next);
1550                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1551
1552                         PMD_DRV_LOG(INFO,
1553                                     "Del Vlan filter for %d\n",
1554                                     vlan_id);
1555                         return rc;
1556                 }
1557                 filter = STAILQ_NEXT(filter, next);
1558         }
1559         return -ENOENT;
1560 }
1561
1562 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1563 {
1564         struct bnxt_filter_info *filter;
1565         struct bnxt_vnic_info *vnic;
1566         int rc = 0;
1567         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1568                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1569         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1570
1571         /* Implementation notes on the use of VNIC in this command:
1572          *
1573          * By default, these filters belong to default vnic for the function.
1574          * Once these filters are set up, only destination VNIC can be modified.
1575          * If the destination VNIC is not specified in this command,
1576          * then the HWRM shall only create an l2 context id.
1577          */
1578
1579         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1580         filter = STAILQ_FIRST(&vnic->filter);
1581         /* Check if the VLAN has already been added */
1582         while (filter) {
1583                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1584                     !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1585                         return -EEXIST;
1586
1587                 filter = STAILQ_NEXT(filter, next);
1588         }
1589
1590         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1591          * command to create MAC+VLAN filter with the right flags, enables set.
1592          */
1593         filter = bnxt_alloc_filter(bp);
1594         if (!filter) {
1595                 PMD_DRV_LOG(ERR,
1596                             "MAC/VLAN filter alloc failed\n");
1597                 return -ENOMEM;
1598         }
1599         /* MAC + VLAN ID filter */
1600         filter->l2_ivlan = vlan_id;
1601         filter->l2_ivlan_mask = 0x0FFF;
1602         filter->enables |= en;
1603         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1604         if (rc) {
1605                 /* Free the newly allocated filter as we were
1606                  * not able to create the filter in hardware.
1607                  */
1608                 filter->fw_l2_filter_id = UINT64_MAX;
1609                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1610                 return rc;
1611         }
1612
1613         /* Add this new filter to the list */
1614         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1615         PMD_DRV_LOG(INFO,
1616                     "Added Vlan filter for %d\n", vlan_id);
1617         return rc;
1618 }
1619
1620 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1621                 uint16_t vlan_id, int on)
1622 {
1623         struct bnxt *bp = eth_dev->data->dev_private;
1624
1625         /* These operations apply to ALL existing MAC/VLAN filters */
1626         if (on)
1627                 return bnxt_add_vlan_filter(bp, vlan_id);
1628         else
1629                 return bnxt_del_vlan_filter(bp, vlan_id);
1630 }
1631
1632 static int
1633 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1634 {
1635         struct bnxt *bp = dev->data->dev_private;
1636         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1637         unsigned int i;
1638
1639         if (mask & ETH_VLAN_FILTER_MASK) {
1640                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1641                         /* Remove any VLAN filters programmed */
1642                         for (i = 0; i < 4095; i++)
1643                                 bnxt_del_vlan_filter(bp, i);
1644                 }
1645                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1646                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1647         }
1648
1649         if (mask & ETH_VLAN_STRIP_MASK) {
1650                 /* Enable or disable VLAN stripping */
1651                 for (i = 0; i < bp->nr_vnics; i++) {
1652                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1653                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1654                                 vnic->vlan_strip = true;
1655                         else
1656                                 vnic->vlan_strip = false;
1657                         bnxt_hwrm_vnic_cfg(bp, vnic);
1658                 }
1659                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1660                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1661         }
1662
1663         if (mask & ETH_VLAN_EXTEND_MASK)
1664                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1665
1666         return 0;
1667 }
1668
1669 static int
1670 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1671                         struct rte_ether_addr *addr)
1672 {
1673         struct bnxt *bp = dev->data->dev_private;
1674         /* Default Filter is tied to VNIC 0 */
1675         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1676         struct bnxt_filter_info *filter;
1677         int rc;
1678
1679         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1680                 return -EPERM;
1681
1682         if (rte_is_zero_ether_addr(addr))
1683                 return -EINVAL;
1684
1685         STAILQ_FOREACH(filter, &vnic->filter, next) {
1686                 /* Default Filter is at Index 0 */
1687                 if (filter->mac_index != 0)
1688                         continue;
1689
1690                 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1691                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1692                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1693                 filter->enables |=
1694                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1695                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1696
1697                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1698                 if (rc)
1699                         return rc;
1700
1701                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1702                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1703                 return 0;
1704         }
1705
1706         return 0;
1707 }
1708
1709 static int
1710 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1711                           struct rte_ether_addr *mc_addr_set,
1712                           uint32_t nb_mc_addr)
1713 {
1714         struct bnxt *bp = eth_dev->data->dev_private;
1715         char *mc_addr_list = (char *)mc_addr_set;
1716         struct bnxt_vnic_info *vnic;
1717         uint32_t off = 0, i = 0;
1718
1719         vnic = &bp->vnic_info[0];
1720
1721         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1722                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1723                 goto allmulti;
1724         }
1725
1726         /* TODO Check for Duplicate mcast addresses */
1727         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1728         for (i = 0; i < nb_mc_addr; i++) {
1729                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1730                         RTE_ETHER_ADDR_LEN);
1731                 off += RTE_ETHER_ADDR_LEN;
1732         }
1733
1734         vnic->mc_addr_cnt = i;
1735
1736 allmulti:
1737         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1738 }
1739
1740 static int
1741 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1742 {
1743         struct bnxt *bp = dev->data->dev_private;
1744         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1745         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1746         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1747         int ret;
1748
1749         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1750                         fw_major, fw_minor, fw_updt);
1751
1752         ret += 1; /* add the size of '\0' */
1753         if (fw_size < (uint32_t)ret)
1754                 return ret;
1755         else
1756                 return 0;
1757 }
1758
1759 static void
1760 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1761         struct rte_eth_rxq_info *qinfo)
1762 {
1763         struct bnxt_rx_queue *rxq;
1764
1765         rxq = dev->data->rx_queues[queue_id];
1766
1767         qinfo->mp = rxq->mb_pool;
1768         qinfo->scattered_rx = dev->data->scattered_rx;
1769         qinfo->nb_desc = rxq->nb_rx_desc;
1770
1771         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1772         qinfo->conf.rx_drop_en = 0;
1773         qinfo->conf.rx_deferred_start = 0;
1774 }
1775
1776 static void
1777 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1778         struct rte_eth_txq_info *qinfo)
1779 {
1780         struct bnxt_tx_queue *txq;
1781
1782         txq = dev->data->tx_queues[queue_id];
1783
1784         qinfo->nb_desc = txq->nb_tx_desc;
1785
1786         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1787         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1788         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1789
1790         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1791         qinfo->conf.tx_rs_thresh = 0;
1792         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1793 }
1794
1795 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1796 {
1797         struct bnxt *bp = eth_dev->data->dev_private;
1798         struct rte_eth_dev_info dev_info;
1799         uint32_t new_pkt_size;
1800         uint32_t rc = 0;
1801         uint32_t i;
1802
1803         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1804                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1805
1806         rc = bnxt_dev_info_get_op(eth_dev, &dev_info);
1807         if (rc != 0) {
1808                 PMD_DRV_LOG(ERR, "Error during getting ethernet device info\n");
1809                 return rc;
1810         }
1811
1812         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1813                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1814                         RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1815                 return -EINVAL;
1816         }
1817
1818 #ifdef RTE_ARCH_X86
1819         /*
1820          * If vector-mode tx/rx is active, disallow any MTU change that would
1821          * require scattered receive support.
1822          */
1823         if (eth_dev->data->dev_started &&
1824             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1825              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1826             (new_pkt_size >
1827              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1828                 PMD_DRV_LOG(ERR,
1829                             "MTU change would require scattered rx support. ");
1830                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1831                 return -EINVAL;
1832         }
1833 #endif
1834
1835         if (new_mtu > RTE_ETHER_MTU) {
1836                 bp->flags |= BNXT_FLAG_JUMBO;
1837                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1838                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1839         } else {
1840                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1841                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1842                 bp->flags &= ~BNXT_FLAG_JUMBO;
1843         }
1844
1845         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
1846
1847         eth_dev->data->mtu = new_mtu;
1848         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1849
1850         for (i = 0; i < bp->nr_vnics; i++) {
1851                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1852                 uint16_t size = 0;
1853
1854                 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1855                                         RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1856                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1857                 if (rc)
1858                         break;
1859
1860                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1861                 size -= RTE_PKTMBUF_HEADROOM;
1862
1863                 if (size < new_mtu) {
1864                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1865                         if (rc)
1866                                 return rc;
1867                 }
1868         }
1869
1870         return rc;
1871 }
1872
1873 static int
1874 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1875 {
1876         struct bnxt *bp = dev->data->dev_private;
1877         uint16_t vlan = bp->vlan;
1878         int rc;
1879
1880         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1881                 PMD_DRV_LOG(ERR,
1882                         "PVID cannot be modified for this function\n");
1883                 return -ENOTSUP;
1884         }
1885         bp->vlan = on ? pvid : 0;
1886
1887         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1888         if (rc)
1889                 bp->vlan = vlan;
1890         return rc;
1891 }
1892
1893 static int
1894 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1895 {
1896         struct bnxt *bp = dev->data->dev_private;
1897
1898         return bnxt_hwrm_port_led_cfg(bp, true);
1899 }
1900
1901 static int
1902 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1903 {
1904         struct bnxt *bp = dev->data->dev_private;
1905
1906         return bnxt_hwrm_port_led_cfg(bp, false);
1907 }
1908
1909 static uint32_t
1910 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1911 {
1912         uint32_t desc = 0, raw_cons = 0, cons;
1913         struct bnxt_cp_ring_info *cpr;
1914         struct bnxt_rx_queue *rxq;
1915         struct rx_pkt_cmpl *rxcmp;
1916         uint16_t cmp_type;
1917         uint8_t cmp = 1;
1918         bool valid;
1919
1920         rxq = dev->data->rx_queues[rx_queue_id];
1921         cpr = rxq->cp_ring;
1922         valid = cpr->valid;
1923
1924         while (raw_cons < rxq->nb_rx_desc) {
1925                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1926                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1927
1928                 if (!CMPL_VALID(rxcmp, valid))
1929                         goto nothing_to_do;
1930                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1931                 cmp_type = CMP_TYPE(rxcmp);
1932                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1933                         cmp = (rte_le_to_cpu_32(
1934                                         ((struct rx_tpa_end_cmpl *)
1935                                          (rxcmp))->agg_bufs_v1) &
1936                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1937                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1938                         desc++;
1939                 } else if (cmp_type == 0x11) {
1940                         desc++;
1941                         cmp = (rxcmp->agg_bufs_v1 &
1942                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1943                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1944                 } else {
1945                         cmp = 1;
1946                 }
1947 nothing_to_do:
1948                 raw_cons += cmp ? cmp : 2;
1949         }
1950
1951         return desc;
1952 }
1953
1954 static int
1955 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1956 {
1957         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1958         struct bnxt_rx_ring_info *rxr;
1959         struct bnxt_cp_ring_info *cpr;
1960         struct bnxt_sw_rx_bd *rx_buf;
1961         struct rx_pkt_cmpl *rxcmp;
1962         uint32_t cons, cp_cons;
1963
1964         if (!rxq)
1965                 return -EINVAL;
1966
1967         cpr = rxq->cp_ring;
1968         rxr = rxq->rx_ring;
1969
1970         if (offset >= rxq->nb_rx_desc)
1971                 return -EINVAL;
1972
1973         cons = RING_CMP(cpr->cp_ring_struct, offset);
1974         cp_cons = cpr->cp_raw_cons;
1975         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1976
1977         if (cons > cp_cons) {
1978                 if (CMPL_VALID(rxcmp, cpr->valid))
1979                         return RTE_ETH_RX_DESC_DONE;
1980         } else {
1981                 if (CMPL_VALID(rxcmp, !cpr->valid))
1982                         return RTE_ETH_RX_DESC_DONE;
1983         }
1984         rx_buf = &rxr->rx_buf_ring[cons];
1985         if (rx_buf->mbuf == NULL)
1986                 return RTE_ETH_RX_DESC_UNAVAIL;
1987
1988
1989         return RTE_ETH_RX_DESC_AVAIL;
1990 }
1991
1992 static int
1993 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1994 {
1995         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1996         struct bnxt_tx_ring_info *txr;
1997         struct bnxt_cp_ring_info *cpr;
1998         struct bnxt_sw_tx_bd *tx_buf;
1999         struct tx_pkt_cmpl *txcmp;
2000         uint32_t cons, cp_cons;
2001
2002         if (!txq)
2003                 return -EINVAL;
2004
2005         cpr = txq->cp_ring;
2006         txr = txq->tx_ring;
2007
2008         if (offset >= txq->nb_tx_desc)
2009                 return -EINVAL;
2010
2011         cons = RING_CMP(cpr->cp_ring_struct, offset);
2012         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2013         cp_cons = cpr->cp_raw_cons;
2014
2015         if (cons > cp_cons) {
2016                 if (CMPL_VALID(txcmp, cpr->valid))
2017                         return RTE_ETH_TX_DESC_UNAVAIL;
2018         } else {
2019                 if (CMPL_VALID(txcmp, !cpr->valid))
2020                         return RTE_ETH_TX_DESC_UNAVAIL;
2021         }
2022         tx_buf = &txr->tx_buf_ring[cons];
2023         if (tx_buf->mbuf == NULL)
2024                 return RTE_ETH_TX_DESC_DONE;
2025
2026         return RTE_ETH_TX_DESC_FULL;
2027 }
2028
2029 static struct bnxt_filter_info *
2030 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2031                                 struct rte_eth_ethertype_filter *efilter,
2032                                 struct bnxt_vnic_info *vnic0,
2033                                 struct bnxt_vnic_info *vnic,
2034                                 int *ret)
2035 {
2036         struct bnxt_filter_info *mfilter = NULL;
2037         int match = 0;
2038         *ret = 0;
2039
2040         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2041                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2042                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2043                         " ethertype filter.", efilter->ether_type);
2044                 *ret = -EINVAL;
2045                 goto exit;
2046         }
2047         if (efilter->queue >= bp->rx_nr_rings) {
2048                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2049                 *ret = -EINVAL;
2050                 goto exit;
2051         }
2052
2053         vnic0 = &bp->vnic_info[0];
2054         vnic = &bp->vnic_info[efilter->queue];
2055         if (vnic == NULL) {
2056                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2057                 *ret = -EINVAL;
2058                 goto exit;
2059         }
2060
2061         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2062                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2063                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2064                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2065                              mfilter->flags ==
2066                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2067                              mfilter->ethertype == efilter->ether_type)) {
2068                                 match = 1;
2069                                 break;
2070                         }
2071                 }
2072         } else {
2073                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2074                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2075                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2076                              mfilter->ethertype == efilter->ether_type &&
2077                              mfilter->flags ==
2078                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2079                                 match = 1;
2080                                 break;
2081                         }
2082         }
2083
2084         if (match)
2085                 *ret = -EEXIST;
2086
2087 exit:
2088         return mfilter;
2089 }
2090
2091 static int
2092 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2093                         enum rte_filter_op filter_op,
2094                         void *arg)
2095 {
2096         struct bnxt *bp = dev->data->dev_private;
2097         struct rte_eth_ethertype_filter *efilter =
2098                         (struct rte_eth_ethertype_filter *)arg;
2099         struct bnxt_filter_info *bfilter, *filter1;
2100         struct bnxt_vnic_info *vnic, *vnic0;
2101         int ret;
2102
2103         if (filter_op == RTE_ETH_FILTER_NOP)
2104                 return 0;
2105
2106         if (arg == NULL) {
2107                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2108                             filter_op);
2109                 return -EINVAL;
2110         }
2111
2112         vnic0 = &bp->vnic_info[0];
2113         vnic = &bp->vnic_info[efilter->queue];
2114
2115         switch (filter_op) {
2116         case RTE_ETH_FILTER_ADD:
2117                 bnxt_match_and_validate_ether_filter(bp, efilter,
2118                                                         vnic0, vnic, &ret);
2119                 if (ret < 0)
2120                         return ret;
2121
2122                 bfilter = bnxt_get_unused_filter(bp);
2123                 if (bfilter == NULL) {
2124                         PMD_DRV_LOG(ERR,
2125                                 "Not enough resources for a new filter.\n");
2126                         return -ENOMEM;
2127                 }
2128                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2129                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2130                        RTE_ETHER_ADDR_LEN);
2131                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2132                        RTE_ETHER_ADDR_LEN);
2133                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2134                 bfilter->ethertype = efilter->ether_type;
2135                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2136
2137                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2138                 if (filter1 == NULL) {
2139                         ret = -EINVAL;
2140                         goto cleanup;
2141                 }
2142                 bfilter->enables |=
2143                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2144                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2145
2146                 bfilter->dst_id = vnic->fw_vnic_id;
2147
2148                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2149                         bfilter->flags =
2150                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2151                 }
2152
2153                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2154                 if (ret)
2155                         goto cleanup;
2156                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2157                 break;
2158         case RTE_ETH_FILTER_DELETE:
2159                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2160                                                         vnic0, vnic, &ret);
2161                 if (ret == -EEXIST) {
2162                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2163
2164                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2165                                       next);
2166                         bnxt_free_filter(bp, filter1);
2167                 } else if (ret == 0) {
2168                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2169                 }
2170                 break;
2171         default:
2172                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2173                 ret = -EINVAL;
2174                 goto error;
2175         }
2176         return ret;
2177 cleanup:
2178         bnxt_free_filter(bp, bfilter);
2179 error:
2180         return ret;
2181 }
2182
2183 static inline int
2184 parse_ntuple_filter(struct bnxt *bp,
2185                     struct rte_eth_ntuple_filter *nfilter,
2186                     struct bnxt_filter_info *bfilter)
2187 {
2188         uint32_t en = 0;
2189
2190         if (nfilter->queue >= bp->rx_nr_rings) {
2191                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2192                 return -EINVAL;
2193         }
2194
2195         switch (nfilter->dst_port_mask) {
2196         case UINT16_MAX:
2197                 bfilter->dst_port_mask = -1;
2198                 bfilter->dst_port = nfilter->dst_port;
2199                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2200                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2201                 break;
2202         default:
2203                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2204                 return -EINVAL;
2205         }
2206
2207         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2208         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2209
2210         switch (nfilter->proto_mask) {
2211         case UINT8_MAX:
2212                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2213                         bfilter->ip_protocol = 17;
2214                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2215                         bfilter->ip_protocol = 6;
2216                 else
2217                         return -EINVAL;
2218                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2219                 break;
2220         default:
2221                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2222                 return -EINVAL;
2223         }
2224
2225         switch (nfilter->dst_ip_mask) {
2226         case UINT32_MAX:
2227                 bfilter->dst_ipaddr_mask[0] = -1;
2228                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2229                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2230                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2231                 break;
2232         default:
2233                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2234                 return -EINVAL;
2235         }
2236
2237         switch (nfilter->src_ip_mask) {
2238         case UINT32_MAX:
2239                 bfilter->src_ipaddr_mask[0] = -1;
2240                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2241                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2242                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2243                 break;
2244         default:
2245                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2246                 return -EINVAL;
2247         }
2248
2249         switch (nfilter->src_port_mask) {
2250         case UINT16_MAX:
2251                 bfilter->src_port_mask = -1;
2252                 bfilter->src_port = nfilter->src_port;
2253                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2254                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2255                 break;
2256         default:
2257                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2258                 return -EINVAL;
2259         }
2260
2261         //TODO Priority
2262         //nfilter->priority = (uint8_t)filter->priority;
2263
2264         bfilter->enables = en;
2265         return 0;
2266 }
2267
2268 static struct bnxt_filter_info*
2269 bnxt_match_ntuple_filter(struct bnxt *bp,
2270                          struct bnxt_filter_info *bfilter,
2271                          struct bnxt_vnic_info **mvnic)
2272 {
2273         struct bnxt_filter_info *mfilter = NULL;
2274         int i;
2275
2276         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2277                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2278                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2279                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2280                             bfilter->src_ipaddr_mask[0] ==
2281                             mfilter->src_ipaddr_mask[0] &&
2282                             bfilter->src_port == mfilter->src_port &&
2283                             bfilter->src_port_mask == mfilter->src_port_mask &&
2284                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2285                             bfilter->dst_ipaddr_mask[0] ==
2286                             mfilter->dst_ipaddr_mask[0] &&
2287                             bfilter->dst_port == mfilter->dst_port &&
2288                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2289                             bfilter->flags == mfilter->flags &&
2290                             bfilter->enables == mfilter->enables) {
2291                                 if (mvnic)
2292                                         *mvnic = vnic;
2293                                 return mfilter;
2294                         }
2295                 }
2296         }
2297         return NULL;
2298 }
2299
2300 static int
2301 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2302                        struct rte_eth_ntuple_filter *nfilter,
2303                        enum rte_filter_op filter_op)
2304 {
2305         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2306         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2307         int ret;
2308
2309         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2310                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2311                 return -EINVAL;
2312         }
2313
2314         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2315                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2316                 return -EINVAL;
2317         }
2318
2319         bfilter = bnxt_get_unused_filter(bp);
2320         if (bfilter == NULL) {
2321                 PMD_DRV_LOG(ERR,
2322                         "Not enough resources for a new filter.\n");
2323                 return -ENOMEM;
2324         }
2325         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2326         if (ret < 0)
2327                 goto free_filter;
2328
2329         vnic = &bp->vnic_info[nfilter->queue];
2330         vnic0 = &bp->vnic_info[0];
2331         filter1 = STAILQ_FIRST(&vnic0->filter);
2332         if (filter1 == NULL) {
2333                 ret = -EINVAL;
2334                 goto free_filter;
2335         }
2336
2337         bfilter->dst_id = vnic->fw_vnic_id;
2338         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2339         bfilter->enables |=
2340                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2341         bfilter->ethertype = 0x800;
2342         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2343
2344         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2345
2346         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2347             bfilter->dst_id == mfilter->dst_id) {
2348                 PMD_DRV_LOG(ERR, "filter exists.\n");
2349                 ret = -EEXIST;
2350                 goto free_filter;
2351         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2352                    bfilter->dst_id != mfilter->dst_id) {
2353                 mfilter->dst_id = vnic->fw_vnic_id;
2354                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2355                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2356                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2357                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2358                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2359                 goto free_filter;
2360         }
2361         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2362                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2363                 ret = -ENOENT;
2364                 goto free_filter;
2365         }
2366
2367         if (filter_op == RTE_ETH_FILTER_ADD) {
2368                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2369                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2370                 if (ret)
2371                         goto free_filter;
2372                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2373         } else {
2374                 if (mfilter == NULL) {
2375                         /* This should not happen. But for Coverity! */
2376                         ret = -ENOENT;
2377                         goto free_filter;
2378                 }
2379                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2380
2381                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2382                 bnxt_free_filter(bp, mfilter);
2383                 mfilter->fw_l2_filter_id = -1;
2384                 bnxt_free_filter(bp, bfilter);
2385                 bfilter->fw_l2_filter_id = -1;
2386         }
2387
2388         return 0;
2389 free_filter:
2390         bfilter->fw_l2_filter_id = -1;
2391         bnxt_free_filter(bp, bfilter);
2392         return ret;
2393 }
2394
2395 static int
2396 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2397                         enum rte_filter_op filter_op,
2398                         void *arg)
2399 {
2400         struct bnxt *bp = dev->data->dev_private;
2401         int ret;
2402
2403         if (filter_op == RTE_ETH_FILTER_NOP)
2404                 return 0;
2405
2406         if (arg == NULL) {
2407                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2408                             filter_op);
2409                 return -EINVAL;
2410         }
2411
2412         switch (filter_op) {
2413         case RTE_ETH_FILTER_ADD:
2414                 ret = bnxt_cfg_ntuple_filter(bp,
2415                         (struct rte_eth_ntuple_filter *)arg,
2416                         filter_op);
2417                 break;
2418         case RTE_ETH_FILTER_DELETE:
2419                 ret = bnxt_cfg_ntuple_filter(bp,
2420                         (struct rte_eth_ntuple_filter *)arg,
2421                         filter_op);
2422                 break;
2423         default:
2424                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2425                 ret = -EINVAL;
2426                 break;
2427         }
2428         return ret;
2429 }
2430
2431 static int
2432 bnxt_parse_fdir_filter(struct bnxt *bp,
2433                        struct rte_eth_fdir_filter *fdir,
2434                        struct bnxt_filter_info *filter)
2435 {
2436         enum rte_fdir_mode fdir_mode =
2437                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2438         struct bnxt_vnic_info *vnic0, *vnic;
2439         struct bnxt_filter_info *filter1;
2440         uint32_t en = 0;
2441         int i;
2442
2443         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2444                 return -EINVAL;
2445
2446         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2447         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2448
2449         switch (fdir->input.flow_type) {
2450         case RTE_ETH_FLOW_IPV4:
2451         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2452                 /* FALLTHROUGH */
2453                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2454                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2455                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2456                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2457                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2458                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2459                 filter->ip_addr_type =
2460                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2461                 filter->src_ipaddr_mask[0] = 0xffffffff;
2462                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2463                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2464                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2465                 filter->ethertype = 0x800;
2466                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2467                 break;
2468         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2469                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2470                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2471                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2472                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2473                 filter->dst_port_mask = 0xffff;
2474                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2475                 filter->src_port_mask = 0xffff;
2476                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2477                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2478                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2479                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2480                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2481                 filter->ip_protocol = 6;
2482                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2483                 filter->ip_addr_type =
2484                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2485                 filter->src_ipaddr_mask[0] = 0xffffffff;
2486                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2487                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2488                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2489                 filter->ethertype = 0x800;
2490                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2491                 break;
2492         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2493                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2494                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2495                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2496                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2497                 filter->dst_port_mask = 0xffff;
2498                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2499                 filter->src_port_mask = 0xffff;
2500                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2501                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2502                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2503                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2504                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2505                 filter->ip_protocol = 17;
2506                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2507                 filter->ip_addr_type =
2508                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2509                 filter->src_ipaddr_mask[0] = 0xffffffff;
2510                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2511                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2512                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2513                 filter->ethertype = 0x800;
2514                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2515                 break;
2516         case RTE_ETH_FLOW_IPV6:
2517         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2518                 /* FALLTHROUGH */
2519                 filter->ip_addr_type =
2520                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2521                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2522                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2523                 rte_memcpy(filter->src_ipaddr,
2524                            fdir->input.flow.ipv6_flow.src_ip, 16);
2525                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2526                 rte_memcpy(filter->dst_ipaddr,
2527                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2528                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2529                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2530                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2531                 memset(filter->src_ipaddr_mask, 0xff, 16);
2532                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2533                 filter->ethertype = 0x86dd;
2534                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2535                 break;
2536         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2537                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2538                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2539                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2540                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2541                 filter->dst_port_mask = 0xffff;
2542                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2543                 filter->src_port_mask = 0xffff;
2544                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2545                 filter->ip_addr_type =
2546                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2547                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2548                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2549                 rte_memcpy(filter->src_ipaddr,
2550                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2551                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2552                 rte_memcpy(filter->dst_ipaddr,
2553                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2554                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2555                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2556                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2557                 memset(filter->src_ipaddr_mask, 0xff, 16);
2558                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2559                 filter->ethertype = 0x86dd;
2560                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2561                 break;
2562         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2563                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2564                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2565                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2566                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2567                 filter->dst_port_mask = 0xffff;
2568                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2569                 filter->src_port_mask = 0xffff;
2570                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2571                 filter->ip_addr_type =
2572                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2573                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2574                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2575                 rte_memcpy(filter->src_ipaddr,
2576                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2577                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2578                 rte_memcpy(filter->dst_ipaddr,
2579                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2580                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2581                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2582                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2583                 memset(filter->src_ipaddr_mask, 0xff, 16);
2584                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2585                 filter->ethertype = 0x86dd;
2586                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2587                 break;
2588         case RTE_ETH_FLOW_L2_PAYLOAD:
2589                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2590                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2591                 break;
2592         case RTE_ETH_FLOW_VXLAN:
2593                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2594                         return -EINVAL;
2595                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2596                 filter->tunnel_type =
2597                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2598                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2599                 break;
2600         case RTE_ETH_FLOW_NVGRE:
2601                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2602                         return -EINVAL;
2603                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2604                 filter->tunnel_type =
2605                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2606                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2607                 break;
2608         case RTE_ETH_FLOW_UNKNOWN:
2609         case RTE_ETH_FLOW_RAW:
2610         case RTE_ETH_FLOW_FRAG_IPV4:
2611         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2612         case RTE_ETH_FLOW_FRAG_IPV6:
2613         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2614         case RTE_ETH_FLOW_IPV6_EX:
2615         case RTE_ETH_FLOW_IPV6_TCP_EX:
2616         case RTE_ETH_FLOW_IPV6_UDP_EX:
2617         case RTE_ETH_FLOW_GENEVE:
2618                 /* FALLTHROUGH */
2619         default:
2620                 return -EINVAL;
2621         }
2622
2623         vnic0 = &bp->vnic_info[0];
2624         vnic = &bp->vnic_info[fdir->action.rx_queue];
2625         if (vnic == NULL) {
2626                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2627                 return -EINVAL;
2628         }
2629
2630
2631         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2632                 rte_memcpy(filter->dst_macaddr,
2633                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2634                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2635         }
2636
2637         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2638                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2639                 filter1 = STAILQ_FIRST(&vnic0->filter);
2640                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2641         } else {
2642                 filter->dst_id = vnic->fw_vnic_id;
2643                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2644                         if (filter->dst_macaddr[i] == 0x00)
2645                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2646                         else
2647                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2648         }
2649
2650         if (filter1 == NULL)
2651                 return -EINVAL;
2652
2653         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2654         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2655
2656         filter->enables = en;
2657
2658         return 0;
2659 }
2660
2661 static struct bnxt_filter_info *
2662 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2663                 struct bnxt_vnic_info **mvnic)
2664 {
2665         struct bnxt_filter_info *mf = NULL;
2666         int i;
2667
2668         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2669                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2670
2671                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2672                         if (mf->filter_type == nf->filter_type &&
2673                             mf->flags == nf->flags &&
2674                             mf->src_port == nf->src_port &&
2675                             mf->src_port_mask == nf->src_port_mask &&
2676                             mf->dst_port == nf->dst_port &&
2677                             mf->dst_port_mask == nf->dst_port_mask &&
2678                             mf->ip_protocol == nf->ip_protocol &&
2679                             mf->ip_addr_type == nf->ip_addr_type &&
2680                             mf->ethertype == nf->ethertype &&
2681                             mf->vni == nf->vni &&
2682                             mf->tunnel_type == nf->tunnel_type &&
2683                             mf->l2_ovlan == nf->l2_ovlan &&
2684                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2685                             mf->l2_ivlan == nf->l2_ivlan &&
2686                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2687                             !memcmp(mf->l2_addr, nf->l2_addr,
2688                                     RTE_ETHER_ADDR_LEN) &&
2689                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2690                                     RTE_ETHER_ADDR_LEN) &&
2691                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2692                                     RTE_ETHER_ADDR_LEN) &&
2693                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2694                                     RTE_ETHER_ADDR_LEN) &&
2695                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2696                                     sizeof(nf->src_ipaddr)) &&
2697                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2698                                     sizeof(nf->src_ipaddr_mask)) &&
2699                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2700                                     sizeof(nf->dst_ipaddr)) &&
2701                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2702                                     sizeof(nf->dst_ipaddr_mask))) {
2703                                 if (mvnic)
2704                                         *mvnic = vnic;
2705                                 return mf;
2706                         }
2707                 }
2708         }
2709         return NULL;
2710 }
2711
2712 static int
2713 bnxt_fdir_filter(struct rte_eth_dev *dev,
2714                  enum rte_filter_op filter_op,
2715                  void *arg)
2716 {
2717         struct bnxt *bp = dev->data->dev_private;
2718         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2719         struct bnxt_filter_info *filter, *match;
2720         struct bnxt_vnic_info *vnic, *mvnic;
2721         int ret = 0, i;
2722
2723         if (filter_op == RTE_ETH_FILTER_NOP)
2724                 return 0;
2725
2726         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2727                 return -EINVAL;
2728
2729         switch (filter_op) {
2730         case RTE_ETH_FILTER_ADD:
2731         case RTE_ETH_FILTER_DELETE:
2732                 /* FALLTHROUGH */
2733                 filter = bnxt_get_unused_filter(bp);
2734                 if (filter == NULL) {
2735                         PMD_DRV_LOG(ERR,
2736                                 "Not enough resources for a new flow.\n");
2737                         return -ENOMEM;
2738                 }
2739
2740                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2741                 if (ret != 0)
2742                         goto free_filter;
2743                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2744
2745                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2746                         vnic = &bp->vnic_info[0];
2747                 else
2748                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2749
2750                 match = bnxt_match_fdir(bp, filter, &mvnic);
2751                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2752                         if (match->dst_id == vnic->fw_vnic_id) {
2753                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2754                                 ret = -EEXIST;
2755                                 goto free_filter;
2756                         } else {
2757                                 match->dst_id = vnic->fw_vnic_id;
2758                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2759                                                                   match->dst_id,
2760                                                                   match);
2761                                 STAILQ_REMOVE(&mvnic->filter, match,
2762                                               bnxt_filter_info, next);
2763                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2764                                 PMD_DRV_LOG(ERR,
2765                                         "Filter with matching pattern exist\n");
2766                                 PMD_DRV_LOG(ERR,
2767                                         "Updated it to new destination q\n");
2768                                 goto free_filter;
2769                         }
2770                 }
2771                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2772                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2773                         ret = -ENOENT;
2774                         goto free_filter;
2775                 }
2776
2777                 if (filter_op == RTE_ETH_FILTER_ADD) {
2778                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2779                                                           filter->dst_id,
2780                                                           filter);
2781                         if (ret)
2782                                 goto free_filter;
2783                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2784                 } else {
2785                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2786                         STAILQ_REMOVE(&vnic->filter, match,
2787                                       bnxt_filter_info, next);
2788                         bnxt_free_filter(bp, match);
2789                         filter->fw_l2_filter_id = -1;
2790                         bnxt_free_filter(bp, filter);
2791                 }
2792                 break;
2793         case RTE_ETH_FILTER_FLUSH:
2794                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2795                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2796
2797                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2798                                 if (filter->filter_type ==
2799                                     HWRM_CFA_NTUPLE_FILTER) {
2800                                         ret =
2801                                         bnxt_hwrm_clear_ntuple_filter(bp,
2802                                                                       filter);
2803                                         STAILQ_REMOVE(&vnic->filter, filter,
2804                                                       bnxt_filter_info, next);
2805                                 }
2806                         }
2807                 }
2808                 return ret;
2809         case RTE_ETH_FILTER_UPDATE:
2810         case RTE_ETH_FILTER_STATS:
2811         case RTE_ETH_FILTER_INFO:
2812                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2813                 break;
2814         default:
2815                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2816                 ret = -EINVAL;
2817                 break;
2818         }
2819         return ret;
2820
2821 free_filter:
2822         filter->fw_l2_filter_id = -1;
2823         bnxt_free_filter(bp, filter);
2824         return ret;
2825 }
2826
2827 static int
2828 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2829                     enum rte_filter_type filter_type,
2830                     enum rte_filter_op filter_op, void *arg)
2831 {
2832         int ret = 0;
2833
2834         switch (filter_type) {
2835         case RTE_ETH_FILTER_TUNNEL:
2836                 PMD_DRV_LOG(ERR,
2837                         "filter type: %d: To be implemented\n", filter_type);
2838                 break;
2839         case RTE_ETH_FILTER_FDIR:
2840                 ret = bnxt_fdir_filter(dev, filter_op, arg);
2841                 break;
2842         case RTE_ETH_FILTER_NTUPLE:
2843                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2844                 break;
2845         case RTE_ETH_FILTER_ETHERTYPE:
2846                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2847                 break;
2848         case RTE_ETH_FILTER_GENERIC:
2849                 if (filter_op != RTE_ETH_FILTER_GET)
2850                         return -EINVAL;
2851                 *(const void **)arg = &bnxt_flow_ops;
2852                 break;
2853         default:
2854                 PMD_DRV_LOG(ERR,
2855                         "Filter type (%d) not supported", filter_type);
2856                 ret = -EINVAL;
2857                 break;
2858         }
2859         return ret;
2860 }
2861
2862 static const uint32_t *
2863 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2864 {
2865         static const uint32_t ptypes[] = {
2866                 RTE_PTYPE_L2_ETHER_VLAN,
2867                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2868                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2869                 RTE_PTYPE_L4_ICMP,
2870                 RTE_PTYPE_L4_TCP,
2871                 RTE_PTYPE_L4_UDP,
2872                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2873                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2874                 RTE_PTYPE_INNER_L4_ICMP,
2875                 RTE_PTYPE_INNER_L4_TCP,
2876                 RTE_PTYPE_INNER_L4_UDP,
2877                 RTE_PTYPE_UNKNOWN
2878         };
2879
2880         if (!dev->rx_pkt_burst)
2881                 return NULL;
2882
2883         return ptypes;
2884 }
2885
2886 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2887                          int reg_win)
2888 {
2889         uint32_t reg_base = *reg_arr & 0xfffff000;
2890         uint32_t win_off;
2891         int i;
2892
2893         for (i = 0; i < count; i++) {
2894                 if ((reg_arr[i] & 0xfffff000) != reg_base)
2895                         return -ERANGE;
2896         }
2897         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2898         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
2899         return 0;
2900 }
2901
2902 static int bnxt_map_ptp_regs(struct bnxt *bp)
2903 {
2904         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2905         uint32_t *reg_arr;
2906         int rc, i;
2907
2908         reg_arr = ptp->rx_regs;
2909         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2910         if (rc)
2911                 return rc;
2912
2913         reg_arr = ptp->tx_regs;
2914         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2915         if (rc)
2916                 return rc;
2917
2918         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2919                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2920
2921         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2922                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2923
2924         return 0;
2925 }
2926
2927 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2928 {
2929         rte_write32(0, (uint8_t *)bp->bar0 +
2930                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
2931         rte_write32(0, (uint8_t *)bp->bar0 +
2932                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
2933 }
2934
2935 static uint64_t bnxt_cc_read(struct bnxt *bp)
2936 {
2937         uint64_t ns;
2938
2939         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2940                               BNXT_GRCPF_REG_SYNC_TIME));
2941         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2942                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2943         return ns;
2944 }
2945
2946 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2947 {
2948         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2949         uint32_t fifo;
2950
2951         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2952                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2953         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2954                 return -EAGAIN;
2955
2956         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2957                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2958         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2959                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2960         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2961                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2962
2963         return 0;
2964 }
2965
2966 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2967 {
2968         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2969         struct bnxt_pf_info *pf = &bp->pf;
2970         uint16_t port_id;
2971         uint32_t fifo;
2972
2973         if (!ptp)
2974                 return -ENODEV;
2975
2976         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2977                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2978         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2979                 return -EAGAIN;
2980
2981         port_id = pf->port_id;
2982         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2983                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
2984
2985         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2986                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2987         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2988 /*              bnxt_clr_rx_ts(bp);       TBD  */
2989                 return -EBUSY;
2990         }
2991
2992         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2993                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2994         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2995                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2996
2997         return 0;
2998 }
2999
3000 static int
3001 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3002 {
3003         uint64_t ns;
3004         struct bnxt *bp = dev->data->dev_private;
3005         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3006
3007         if (!ptp)
3008                 return 0;
3009
3010         ns = rte_timespec_to_ns(ts);
3011         /* Set the timecounters to a new value. */
3012         ptp->tc.nsec = ns;
3013
3014         return 0;
3015 }
3016
3017 static int
3018 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3019 {
3020         uint64_t ns, systime_cycles;
3021         struct bnxt *bp = dev->data->dev_private;
3022         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3023
3024         if (!ptp)
3025                 return 0;
3026
3027         systime_cycles = bnxt_cc_read(bp);
3028         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3029         *ts = rte_ns_to_timespec(ns);
3030
3031         return 0;
3032 }
3033 static int
3034 bnxt_timesync_enable(struct rte_eth_dev *dev)
3035 {
3036         struct bnxt *bp = dev->data->dev_private;
3037         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3038         uint32_t shift = 0;
3039
3040         if (!ptp)
3041                 return 0;
3042
3043         ptp->rx_filter = 1;
3044         ptp->tx_tstamp_en = 1;
3045         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3046
3047         if (!bnxt_hwrm_ptp_cfg(bp))
3048                 bnxt_map_ptp_regs(bp);
3049
3050         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3051         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3052         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3053
3054         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3055         ptp->tc.cc_shift = shift;
3056         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3057
3058         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3059         ptp->rx_tstamp_tc.cc_shift = shift;
3060         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3061
3062         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3063         ptp->tx_tstamp_tc.cc_shift = shift;
3064         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3065
3066         return 0;
3067 }
3068
3069 static int
3070 bnxt_timesync_disable(struct rte_eth_dev *dev)
3071 {
3072         struct bnxt *bp = dev->data->dev_private;
3073         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3074
3075         if (!ptp)
3076                 return 0;
3077
3078         ptp->rx_filter = 0;
3079         ptp->tx_tstamp_en = 0;
3080         ptp->rxctl = 0;
3081
3082         bnxt_hwrm_ptp_cfg(bp);
3083
3084         bnxt_unmap_ptp_regs(bp);
3085
3086         return 0;
3087 }
3088
3089 static int
3090 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3091                                  struct timespec *timestamp,
3092                                  uint32_t flags __rte_unused)
3093 {
3094         struct bnxt *bp = dev->data->dev_private;
3095         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3096         uint64_t rx_tstamp_cycles = 0;
3097         uint64_t ns;
3098
3099         if (!ptp)
3100                 return 0;
3101
3102         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3103         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3104         *timestamp = rte_ns_to_timespec(ns);
3105         return  0;
3106 }
3107
3108 static int
3109 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3110                                  struct timespec *timestamp)
3111 {
3112         struct bnxt *bp = dev->data->dev_private;
3113         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3114         uint64_t tx_tstamp_cycles = 0;
3115         uint64_t ns;
3116
3117         if (!ptp)
3118                 return 0;
3119
3120         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3121         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3122         *timestamp = rte_ns_to_timespec(ns);
3123
3124         return 0;
3125 }
3126
3127 static int
3128 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3129 {
3130         struct bnxt *bp = dev->data->dev_private;
3131         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3132
3133         if (!ptp)
3134                 return 0;
3135
3136         ptp->tc.nsec += delta;
3137
3138         return 0;
3139 }
3140
3141 static int
3142 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3143 {
3144         struct bnxt *bp = dev->data->dev_private;
3145         int rc;
3146         uint32_t dir_entries;
3147         uint32_t entry_length;
3148
3149         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3150                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3151                 bp->pdev->addr.devid, bp->pdev->addr.function);
3152
3153         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3154         if (rc != 0)
3155                 return rc;
3156
3157         return dir_entries * entry_length;
3158 }
3159
3160 static int
3161 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3162                 struct rte_dev_eeprom_info *in_eeprom)
3163 {
3164         struct bnxt *bp = dev->data->dev_private;
3165         uint32_t index;
3166         uint32_t offset;
3167
3168         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3169                 "len = %d\n", bp->pdev->addr.domain,
3170                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3171                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3172
3173         if (in_eeprom->offset == 0) /* special offset value to get directory */
3174                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3175                                                 in_eeprom->data);
3176
3177         index = in_eeprom->offset >> 24;
3178         offset = in_eeprom->offset & 0xffffff;
3179
3180         if (index != 0)
3181                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3182                                            in_eeprom->length, in_eeprom->data);
3183
3184         return 0;
3185 }
3186
3187 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3188 {
3189         switch (dir_type) {
3190         case BNX_DIR_TYPE_CHIMP_PATCH:
3191         case BNX_DIR_TYPE_BOOTCODE:
3192         case BNX_DIR_TYPE_BOOTCODE_2:
3193         case BNX_DIR_TYPE_APE_FW:
3194         case BNX_DIR_TYPE_APE_PATCH:
3195         case BNX_DIR_TYPE_KONG_FW:
3196         case BNX_DIR_TYPE_KONG_PATCH:
3197         case BNX_DIR_TYPE_BONO_FW:
3198         case BNX_DIR_TYPE_BONO_PATCH:
3199                 /* FALLTHROUGH */
3200                 return true;
3201         }
3202
3203         return false;
3204 }
3205
3206 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3207 {
3208         switch (dir_type) {
3209         case BNX_DIR_TYPE_AVS:
3210         case BNX_DIR_TYPE_EXP_ROM_MBA:
3211         case BNX_DIR_TYPE_PCIE:
3212         case BNX_DIR_TYPE_TSCF_UCODE:
3213         case BNX_DIR_TYPE_EXT_PHY:
3214         case BNX_DIR_TYPE_CCM:
3215         case BNX_DIR_TYPE_ISCSI_BOOT:
3216         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3217         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3218                 /* FALLTHROUGH */
3219                 return true;
3220         }
3221
3222         return false;
3223 }
3224
3225 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3226 {
3227         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3228                 bnxt_dir_type_is_other_exec_format(dir_type);
3229 }
3230
3231 static int
3232 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3233                 struct rte_dev_eeprom_info *in_eeprom)
3234 {
3235         struct bnxt *bp = dev->data->dev_private;
3236         uint8_t index, dir_op;
3237         uint16_t type, ext, ordinal, attr;
3238
3239         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3240                 "len = %d\n", bp->pdev->addr.domain,
3241                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3242                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3243
3244         if (!BNXT_PF(bp)) {
3245                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3246                 return -EINVAL;
3247         }
3248
3249         type = in_eeprom->magic >> 16;
3250
3251         if (type == 0xffff) { /* special value for directory operations */
3252                 index = in_eeprom->magic & 0xff;
3253                 dir_op = in_eeprom->magic >> 8;
3254                 if (index == 0)
3255                         return -EINVAL;
3256                 switch (dir_op) {
3257                 case 0x0e: /* erase */
3258                         if (in_eeprom->offset != ~in_eeprom->magic)
3259                                 return -EINVAL;
3260                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3261                 default:
3262                         return -EINVAL;
3263                 }
3264         }
3265
3266         /* Create or re-write an NVM item: */
3267         if (bnxt_dir_type_is_executable(type) == true)
3268                 return -EOPNOTSUPP;
3269         ext = in_eeprom->magic & 0xffff;
3270         ordinal = in_eeprom->offset >> 16;
3271         attr = in_eeprom->offset & 0xffff;
3272
3273         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3274                                      in_eeprom->data, in_eeprom->length);
3275 }
3276
3277 /*
3278  * Initialization
3279  */
3280
3281 static const struct eth_dev_ops bnxt_dev_ops = {
3282         .dev_infos_get = bnxt_dev_info_get_op,
3283         .dev_close = bnxt_dev_close_op,
3284         .dev_configure = bnxt_dev_configure_op,
3285         .dev_start = bnxt_dev_start_op,
3286         .dev_stop = bnxt_dev_stop_op,
3287         .dev_set_link_up = bnxt_dev_set_link_up_op,
3288         .dev_set_link_down = bnxt_dev_set_link_down_op,
3289         .stats_get = bnxt_stats_get_op,
3290         .stats_reset = bnxt_stats_reset_op,
3291         .rx_queue_setup = bnxt_rx_queue_setup_op,
3292         .rx_queue_release = bnxt_rx_queue_release_op,
3293         .tx_queue_setup = bnxt_tx_queue_setup_op,
3294         .tx_queue_release = bnxt_tx_queue_release_op,
3295         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3296         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3297         .reta_update = bnxt_reta_update_op,
3298         .reta_query = bnxt_reta_query_op,
3299         .rss_hash_update = bnxt_rss_hash_update_op,
3300         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3301         .link_update = bnxt_link_update_op,
3302         .promiscuous_enable = bnxt_promiscuous_enable_op,
3303         .promiscuous_disable = bnxt_promiscuous_disable_op,
3304         .allmulticast_enable = bnxt_allmulticast_enable_op,
3305         .allmulticast_disable = bnxt_allmulticast_disable_op,
3306         .mac_addr_add = bnxt_mac_addr_add_op,
3307         .mac_addr_remove = bnxt_mac_addr_remove_op,
3308         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3309         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3310         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3311         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3312         .vlan_filter_set = bnxt_vlan_filter_set_op,
3313         .vlan_offload_set = bnxt_vlan_offload_set_op,
3314         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3315         .mtu_set = bnxt_mtu_set_op,
3316         .mac_addr_set = bnxt_set_default_mac_addr_op,
3317         .xstats_get = bnxt_dev_xstats_get_op,
3318         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3319         .xstats_reset = bnxt_dev_xstats_reset_op,
3320         .fw_version_get = bnxt_fw_version_get,
3321         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3322         .rxq_info_get = bnxt_rxq_info_get_op,
3323         .txq_info_get = bnxt_txq_info_get_op,
3324         .dev_led_on = bnxt_dev_led_on_op,
3325         .dev_led_off = bnxt_dev_led_off_op,
3326         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3327         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3328         .rx_queue_count = bnxt_rx_queue_count_op,
3329         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3330         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3331         .rx_queue_start = bnxt_rx_queue_start,
3332         .rx_queue_stop = bnxt_rx_queue_stop,
3333         .tx_queue_start = bnxt_tx_queue_start,
3334         .tx_queue_stop = bnxt_tx_queue_stop,
3335         .filter_ctrl = bnxt_filter_ctrl_op,
3336         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3337         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3338         .get_eeprom           = bnxt_get_eeprom_op,
3339         .set_eeprom           = bnxt_set_eeprom_op,
3340         .timesync_enable      = bnxt_timesync_enable,
3341         .timesync_disable     = bnxt_timesync_disable,
3342         .timesync_read_time   = bnxt_timesync_read_time,
3343         .timesync_write_time   = bnxt_timesync_write_time,
3344         .timesync_adjust_time = bnxt_timesync_adjust_time,
3345         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3346         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3347 };
3348
3349 static bool bnxt_vf_pciid(uint16_t id)
3350 {
3351         if (id == BROADCOM_DEV_ID_57304_VF ||
3352             id == BROADCOM_DEV_ID_57406_VF ||
3353             id == BROADCOM_DEV_ID_5731X_VF ||
3354             id == BROADCOM_DEV_ID_5741X_VF ||
3355             id == BROADCOM_DEV_ID_57414_VF ||
3356             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3357             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3358             id == BROADCOM_DEV_ID_58802_VF ||
3359             id == BROADCOM_DEV_ID_57500_VF1 ||
3360             id == BROADCOM_DEV_ID_57500_VF2)
3361                 return true;
3362         return false;
3363 }
3364
3365 bool bnxt_stratus_device(struct bnxt *bp)
3366 {
3367         uint16_t id = bp->pdev->id.device_id;
3368
3369         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3370             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3371             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3372                 return true;
3373         return false;
3374 }
3375
3376 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3377 {
3378         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3379         struct bnxt *bp = eth_dev->data->dev_private;
3380
3381         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3382         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3383         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3384         if (!bp->bar0 || !bp->doorbell_base) {
3385                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3386                 return -ENODEV;
3387         }
3388
3389         bp->eth_dev = eth_dev;
3390         bp->pdev = pci_dev;
3391
3392         return 0;
3393 }
3394
3395 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3396                                   struct bnxt_ctx_pg_info *ctx_pg,
3397                                   uint32_t mem_size,
3398                                   const char *suffix,
3399                                   uint16_t idx)
3400 {
3401         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3402         const struct rte_memzone *mz = NULL;
3403         char mz_name[RTE_MEMZONE_NAMESIZE];
3404         rte_iova_t mz_phys_addr;
3405         uint64_t valid_bits = 0;
3406         uint32_t sz;
3407         int i;
3408
3409         if (!mem_size)
3410                 return 0;
3411
3412         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3413                          BNXT_PAGE_SIZE;
3414         rmem->page_size = BNXT_PAGE_SIZE;
3415         rmem->pg_arr = ctx_pg->ctx_pg_arr;
3416         rmem->dma_arr = ctx_pg->ctx_dma_arr;
3417         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3418
3419         valid_bits = PTU_PTE_VALID;
3420
3421         if (rmem->nr_pages > 1) {
3422                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3423                          "bnxt_ctx_pg_tbl%s_%x_%d",
3424                          suffix, idx, bp->eth_dev->data->port_id);
3425                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3426                 mz = rte_memzone_lookup(mz_name);
3427                 if (!mz) {
3428                         mz = rte_memzone_reserve_aligned(mz_name,
3429                                                 rmem->nr_pages * 8,
3430                                                 SOCKET_ID_ANY,
3431                                                 RTE_MEMZONE_2MB |
3432                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
3433                                                 RTE_MEMZONE_IOVA_CONTIG,
3434                                                 BNXT_PAGE_SIZE);
3435                         if (mz == NULL)
3436                                 return -ENOMEM;
3437                 }
3438
3439                 memset(mz->addr, 0, mz->len);
3440                 mz_phys_addr = mz->iova;
3441                 if ((unsigned long)mz->addr == mz_phys_addr) {
3442                         PMD_DRV_LOG(WARNING,
3443                                 "Memzone physical address same as virtual.\n");
3444                         PMD_DRV_LOG(WARNING,
3445                                     "Using rte_mem_virt2iova()\n");
3446                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3447                         if (mz_phys_addr == RTE_BAD_IOVA) {
3448                                 PMD_DRV_LOG(ERR,
3449                                         "unable to map addr to phys memory\n");
3450                                 return -ENOMEM;
3451                         }
3452                 }
3453                 rte_mem_lock_page(((char *)mz->addr));
3454
3455                 rmem->pg_tbl = mz->addr;
3456                 rmem->pg_tbl_map = mz_phys_addr;
3457                 rmem->pg_tbl_mz = mz;
3458         }
3459
3460         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
3461                  suffix, idx, bp->eth_dev->data->port_id);
3462         mz = rte_memzone_lookup(mz_name);
3463         if (!mz) {
3464                 mz = rte_memzone_reserve_aligned(mz_name,
3465                                                  mem_size,
3466                                                  SOCKET_ID_ANY,
3467                                                  RTE_MEMZONE_1GB |
3468                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
3469                                                  RTE_MEMZONE_IOVA_CONTIG,
3470                                                  BNXT_PAGE_SIZE);
3471                 if (mz == NULL)
3472                         return -ENOMEM;
3473         }
3474
3475         memset(mz->addr, 0, mz->len);
3476         mz_phys_addr = mz->iova;
3477         if ((unsigned long)mz->addr == mz_phys_addr) {
3478                 PMD_DRV_LOG(WARNING,
3479                             "Memzone physical address same as virtual.\n");
3480                 PMD_DRV_LOG(WARNING,
3481                             "Using rte_mem_virt2iova()\n");
3482                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
3483                         rte_mem_lock_page(((char *)mz->addr) + sz);
3484                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3485                 if (mz_phys_addr == RTE_BAD_IOVA) {
3486                         PMD_DRV_LOG(ERR,
3487                                     "unable to map addr to phys memory\n");
3488                         return -ENOMEM;
3489                 }
3490         }
3491
3492         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
3493                 rte_mem_lock_page(((char *)mz->addr) + sz);
3494                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
3495                 rmem->dma_arr[i] = mz_phys_addr + sz;
3496
3497                 if (rmem->nr_pages > 1) {
3498                         if (i == rmem->nr_pages - 2 &&
3499                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3500                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
3501                         else if (i == rmem->nr_pages - 1 &&
3502                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3503                                 valid_bits |= PTU_PTE_LAST;
3504
3505                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
3506                                                            valid_bits);
3507                 }
3508         }
3509
3510         rmem->mz = mz;
3511         if (rmem->vmem_size)
3512                 rmem->vmem = (void **)mz->addr;
3513         rmem->dma_arr[0] = mz_phys_addr;
3514         return 0;
3515 }
3516
3517 static void bnxt_free_ctx_mem(struct bnxt *bp)
3518 {
3519         int i;
3520
3521         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
3522                 return;
3523
3524         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
3525         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
3526         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
3527         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
3528         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
3529         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
3530         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
3531         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
3532         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
3533         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
3534         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
3535
3536         for (i = 0; i < BNXT_MAX_Q; i++) {
3537                 if (bp->ctx->tqm_mem[i])
3538                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
3539         }
3540
3541         rte_free(bp->ctx);
3542         bp->ctx = NULL;
3543 }
3544
3545 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
3546
3547 #define min_t(type, x, y) ({                    \
3548         type __min1 = (x);                      \
3549         type __min2 = (y);                      \
3550         __min1 < __min2 ? __min1 : __min2; })
3551
3552 #define max_t(type, x, y) ({                    \
3553         type __max1 = (x);                      \
3554         type __max2 = (y);                      \
3555         __max1 > __max2 ? __max1 : __max2; })
3556
3557 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
3558
3559 int bnxt_alloc_ctx_mem(struct bnxt *bp)
3560 {
3561         struct bnxt_ctx_pg_info *ctx_pg;
3562         struct bnxt_ctx_mem_info *ctx;
3563         uint32_t mem_size, ena, entries;
3564         int i, rc;
3565
3566         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
3567         if (rc) {
3568                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
3569                 return rc;
3570         }
3571         ctx = bp->ctx;
3572         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
3573                 return 0;
3574
3575         ctx_pg = &ctx->qp_mem;
3576         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
3577         mem_size = ctx->qp_entry_size * ctx_pg->entries;
3578         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
3579         if (rc)
3580                 return rc;
3581
3582         ctx_pg = &ctx->srq_mem;
3583         ctx_pg->entries = ctx->srq_max_l2_entries;
3584         mem_size = ctx->srq_entry_size * ctx_pg->entries;
3585         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
3586         if (rc)
3587                 return rc;
3588
3589         ctx_pg = &ctx->cq_mem;
3590         ctx_pg->entries = ctx->cq_max_l2_entries;
3591         mem_size = ctx->cq_entry_size * ctx_pg->entries;
3592         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
3593         if (rc)
3594                 return rc;
3595
3596         ctx_pg = &ctx->vnic_mem;
3597         ctx_pg->entries = ctx->vnic_max_vnic_entries +
3598                 ctx->vnic_max_ring_table_entries;
3599         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
3600         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
3601         if (rc)
3602                 return rc;
3603
3604         ctx_pg = &ctx->stat_mem;
3605         ctx_pg->entries = ctx->stat_max_entries;
3606         mem_size = ctx->stat_entry_size * ctx_pg->entries;
3607         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
3608         if (rc)
3609                 return rc;
3610
3611         entries = ctx->qp_max_l2_entries;
3612         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
3613         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
3614                           ctx->tqm_max_entries_per_ring);
3615         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
3616                 ctx_pg = ctx->tqm_mem[i];
3617                 /* use min tqm entries for now. */
3618                 ctx_pg->entries = entries;
3619                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
3620                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
3621                 if (rc)
3622                         return rc;
3623                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
3624         }
3625
3626         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
3627         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
3628         if (rc)
3629                 PMD_DRV_LOG(ERR,
3630                             "Failed to configure context mem: rc = %d\n", rc);
3631         else
3632                 ctx->flags |= BNXT_CTX_FLAG_INITED;
3633
3634         return rc;
3635 }
3636
3637 static int bnxt_alloc_stats_mem(struct bnxt *bp)
3638 {
3639         struct rte_pci_device *pci_dev = bp->pdev;
3640         char mz_name[RTE_MEMZONE_NAMESIZE];
3641         const struct rte_memzone *mz = NULL;
3642         uint32_t total_alloc_len;
3643         rte_iova_t mz_phys_addr;
3644
3645         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
3646                 return 0;
3647
3648         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3649                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3650                  pci_dev->addr.bus, pci_dev->addr.devid,
3651                  pci_dev->addr.function, "rx_port_stats");
3652         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3653         mz = rte_memzone_lookup(mz_name);
3654         total_alloc_len =
3655                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
3656                                        sizeof(struct rx_port_stats_ext) + 512);
3657         if (!mz) {
3658                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3659                                          SOCKET_ID_ANY,
3660                                          RTE_MEMZONE_2MB |
3661                                          RTE_MEMZONE_SIZE_HINT_ONLY |
3662                                          RTE_MEMZONE_IOVA_CONTIG);
3663                 if (mz == NULL)
3664                         return -ENOMEM;
3665         }
3666         memset(mz->addr, 0, mz->len);
3667         mz_phys_addr = mz->iova;
3668         if ((unsigned long)mz->addr == mz_phys_addr) {
3669                 PMD_DRV_LOG(WARNING,
3670                             "Memzone physical address same as virtual.\n");
3671                 PMD_DRV_LOG(WARNING,
3672                             "Using rte_mem_virt2iova()\n");
3673                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3674                 if (mz_phys_addr == RTE_BAD_IOVA) {
3675                         PMD_DRV_LOG(ERR,
3676                                     "Can't map address to physical memory\n");
3677                         return -ENOMEM;
3678                 }
3679         }
3680
3681         bp->rx_mem_zone = (const void *)mz;
3682         bp->hw_rx_port_stats = mz->addr;
3683         bp->hw_rx_port_stats_map = mz_phys_addr;
3684
3685         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3686                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3687                  pci_dev->addr.bus, pci_dev->addr.devid,
3688                  pci_dev->addr.function, "tx_port_stats");
3689         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3690         mz = rte_memzone_lookup(mz_name);
3691         total_alloc_len =
3692                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
3693                                        sizeof(struct tx_port_stats_ext) + 512);
3694         if (!mz) {
3695                 mz = rte_memzone_reserve(mz_name,
3696                                          total_alloc_len,
3697                                          SOCKET_ID_ANY,
3698                                          RTE_MEMZONE_2MB |
3699                                          RTE_MEMZONE_SIZE_HINT_ONLY |
3700                                          RTE_MEMZONE_IOVA_CONTIG);
3701                 if (mz == NULL)
3702                         return -ENOMEM;
3703         }
3704         memset(mz->addr, 0, mz->len);
3705         mz_phys_addr = mz->iova;
3706         if ((unsigned long)mz->addr == mz_phys_addr) {
3707                 PMD_DRV_LOG(WARNING,
3708                             "Memzone physical address same as virtual\n");
3709                 PMD_DRV_LOG(WARNING,
3710                             "Using rte_mem_virt2iova()\n");
3711                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3712                 if (mz_phys_addr == RTE_BAD_IOVA) {
3713                         PMD_DRV_LOG(ERR,
3714                                     "Can't map address to physical memory\n");
3715                         return -ENOMEM;
3716                 }
3717         }
3718
3719         bp->tx_mem_zone = (const void *)mz;
3720         bp->hw_tx_port_stats = mz->addr;
3721         bp->hw_tx_port_stats_map = mz_phys_addr;
3722         bp->flags |= BNXT_FLAG_PORT_STATS;
3723
3724         /* Display extended statistics if FW supports it */
3725         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3726             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
3727             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
3728                 return 0;
3729
3730         bp->hw_rx_port_stats_ext = (void *)
3731                 ((uint8_t *)bp->hw_rx_port_stats +
3732                  sizeof(struct rx_port_stats));
3733         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3734                 sizeof(struct rx_port_stats);
3735         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3736
3737         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
3738             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
3739                 bp->hw_tx_port_stats_ext = (void *)
3740                         ((uint8_t *)bp->hw_tx_port_stats +
3741                          sizeof(struct tx_port_stats));
3742                 bp->hw_tx_port_stats_ext_map =
3743                         bp->hw_tx_port_stats_map +
3744                         sizeof(struct tx_port_stats);
3745                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3746         }
3747
3748         return 0;
3749 }
3750
3751 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
3752 {
3753         struct bnxt *bp = eth_dev->data->dev_private;
3754         int rc = 0;
3755
3756         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3757                                                RTE_ETHER_ADDR_LEN *
3758                                                bp->max_l2_ctx,
3759                                                0);
3760         if (eth_dev->data->mac_addrs == NULL) {
3761                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
3762                 return -ENOMEM;
3763         }
3764
3765         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
3766                 if (BNXT_PF(bp))
3767                         return -EINVAL;
3768
3769                 /* Generate a random MAC address, if none was assigned by PF */
3770                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
3771                 bnxt_eth_hw_addr_random(bp->mac_addr);
3772                 PMD_DRV_LOG(INFO,
3773                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
3774                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
3775                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
3776
3777                 rc = bnxt_hwrm_set_mac(bp);
3778                 if (!rc)
3779                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
3780                                RTE_ETHER_ADDR_LEN);
3781                 return rc;
3782         }
3783
3784         /* Copy the permanent MAC from the FUNC_QCAPS response */
3785         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
3786         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
3787
3788         return rc;
3789 }
3790
3791 #define ALLOW_FUNC(x)   \
3792         { \
3793                 uint32_t arg = (x); \
3794                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3795                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3796         }
3797 static int
3798 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3799 {
3800         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3801         static int version_printed;
3802         struct bnxt *bp;
3803         uint16_t mtu;
3804         int rc;
3805
3806         if (version_printed++ == 0)
3807                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3808
3809         rte_eth_copy_pci_info(eth_dev, pci_dev);
3810
3811         bp = eth_dev->data->dev_private;
3812
3813         bp->dev_stopped = 1;
3814
3815         eth_dev->dev_ops = &bnxt_dev_ops;
3816         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3817         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3818
3819         /*
3820          * For secondary processes, we don't initialise any further
3821          * as primary has already done this work.
3822          */
3823         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3824                 return 0;
3825
3826         if (bnxt_vf_pciid(pci_dev->id.device_id))
3827                 bp->flags |= BNXT_FLAG_VF;
3828
3829         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
3830             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
3831             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
3832             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
3833             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
3834                 bp->flags |= BNXT_FLAG_THOR_CHIP;
3835
3836         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
3837             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
3838             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
3839             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
3840                 bp->flags |= BNXT_FLAG_STINGRAY;
3841
3842         rc = bnxt_init_board(eth_dev);
3843         if (rc) {
3844                 PMD_DRV_LOG(ERR,
3845                         "Board initialization failed rc: %x\n", rc);
3846                 goto error;
3847         }
3848
3849         rc = bnxt_alloc_hwrm_resources(bp);
3850         if (rc) {
3851                 PMD_DRV_LOG(ERR,
3852                         "hwrm resource allocation failure rc: %x\n", rc);
3853                 goto error_free;
3854         }
3855         rc = bnxt_hwrm_ver_get(bp);
3856         if (rc)
3857                 goto error_free;
3858
3859         rc = bnxt_hwrm_func_reset(bp);
3860         if (rc) {
3861                 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3862                 rc = -EIO;
3863                 goto error_free;
3864         }
3865
3866         rc = bnxt_hwrm_queue_qportcfg(bp);
3867         if (rc) {
3868                 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3869                 goto error_free;
3870         }
3871         /* Get the MAX capabilities for this function */
3872         rc = bnxt_hwrm_func_qcaps(bp);
3873         if (rc) {
3874                 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3875                 goto error_free;
3876         }
3877
3878         rc = bnxt_alloc_stats_mem(bp);
3879         if (rc)
3880                 goto error_free;
3881
3882         if (bp->max_tx_rings == 0) {
3883                 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3884                 rc = -EBUSY;
3885                 goto error_free;
3886         }
3887
3888         rc = bnxt_setup_mac_addr(eth_dev);
3889         if (rc)
3890                 goto error_free;
3891
3892         /* THOR does not support ring groups.
3893          * But we will use the array to save RSS context IDs.
3894          */
3895         if (BNXT_CHIP_THOR(bp)) {
3896                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
3897         } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3898                 /* 1 ring is for default completion ring */
3899                 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3900                 rc = -ENOSPC;
3901                 goto error_free;
3902         }
3903
3904         if (BNXT_HAS_RING_GRPS(bp)) {
3905                 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3906                                         sizeof(*bp->grp_info) *
3907                                                 bp->max_ring_grps, 0);
3908                 if (!bp->grp_info) {
3909                         PMD_DRV_LOG(ERR,
3910                                 "Failed to alloc %zu bytes for grp info tbl.\n",
3911                                 sizeof(*bp->grp_info) * bp->max_ring_grps);
3912                         rc = -ENOMEM;
3913                         goto error_free;
3914                 }
3915         }
3916
3917         /* Forward all requests if firmware is new enough */
3918         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3919             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3920             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3921                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3922         } else {
3923                 PMD_DRV_LOG(WARNING,
3924                         "Firmware too old for VF mailbox functionality\n");
3925                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3926         }
3927
3928         /*
3929          * The following are used for driver cleanup.  If we disallow these,
3930          * VF drivers can't clean up cleanly.
3931          */
3932         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3933         ALLOW_FUNC(HWRM_VNIC_FREE);
3934         ALLOW_FUNC(HWRM_RING_FREE);
3935         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3936         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3937         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3938         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3939         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3940         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3941         rc = bnxt_hwrm_func_driver_register(bp);
3942         if (rc) {
3943                 PMD_DRV_LOG(ERR,
3944                         "Failed to register driver");
3945                 rc = -EBUSY;
3946                 goto error_free;
3947         }
3948
3949         PMD_DRV_LOG(INFO,
3950                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3951                 pci_dev->mem_resource[0].phys_addr,
3952                 pci_dev->mem_resource[0].addr);
3953
3954         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
3955         if (rc) {
3956                 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3957                 goto error_free;
3958         }
3959
3960         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
3961             mtu != eth_dev->data->mtu)
3962                 eth_dev->data->mtu = mtu;
3963
3964         if (BNXT_PF(bp)) {
3965                 //if (bp->pf.active_vfs) {
3966                         // TODO: Deallocate VF resources?
3967                 //}
3968                 if (bp->pdev->max_vfs) {
3969                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3970                         if (rc) {
3971                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3972                                 goto error_free;
3973                         }
3974                 } else {
3975                         rc = bnxt_hwrm_allocate_pf_only(bp);
3976                         if (rc) {
3977                                 PMD_DRV_LOG(ERR,
3978                                         "Failed to allocate PF resources\n");
3979                                 goto error_free;
3980                         }
3981                 }
3982         }
3983
3984         bnxt_hwrm_port_led_qcaps(bp);
3985
3986         rc = bnxt_setup_int(bp);
3987         if (rc)
3988                 goto error_free;
3989
3990         rc = bnxt_alloc_mem(bp);
3991         if (rc)
3992                 goto error_free;
3993
3994         bnxt_init_nic(bp);
3995
3996         rc = bnxt_request_int(bp);
3997         if (rc)
3998                 goto error_free;
3999
4000         return 0;
4001
4002 error_free:
4003         bnxt_dev_uninit(eth_dev);
4004 error:
4005         return rc;
4006 }
4007
4008 static int
4009 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4010 {
4011         struct bnxt *bp = eth_dev->data->dev_private;
4012         int rc;
4013
4014         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4015                 return -EPERM;
4016
4017         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4018         bnxt_disable_int(bp);
4019         bnxt_free_int(bp);
4020         bnxt_free_mem(bp);
4021
4022         bnxt_hwrm_func_buf_unrgtr(bp);
4023
4024         if (bp->grp_info != NULL) {
4025                 rte_free(bp->grp_info);
4026                 bp->grp_info = NULL;
4027         }
4028         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4029         bnxt_free_hwrm_resources(bp);
4030
4031         if (bp->tx_mem_zone) {
4032                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4033                 bp->tx_mem_zone = NULL;
4034         }
4035
4036         if (bp->rx_mem_zone) {
4037                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4038                 bp->rx_mem_zone = NULL;
4039         }
4040
4041         if (bp->dev_stopped == 0)
4042                 bnxt_dev_close_op(eth_dev);
4043         if (bp->pf.vf_info)
4044                 rte_free(bp->pf.vf_info);
4045         bnxt_free_ctx_mem(bp);
4046         eth_dev->dev_ops = NULL;
4047         eth_dev->rx_pkt_burst = NULL;
4048         eth_dev->tx_pkt_burst = NULL;
4049
4050         return rc;
4051 }
4052
4053 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4054         struct rte_pci_device *pci_dev)
4055 {
4056         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4057                 bnxt_dev_init);
4058 }
4059
4060 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4061 {
4062         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4063                 return rte_eth_dev_pci_generic_remove(pci_dev,
4064                                 bnxt_dev_uninit);
4065         else
4066                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4067 }
4068
4069 static struct rte_pci_driver bnxt_rte_pmd = {
4070         .id_table = bnxt_pci_id_map,
4071         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4072         .probe = bnxt_pci_probe,
4073         .remove = bnxt_pci_remove,
4074 };
4075
4076 static bool
4077 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4078 {
4079         if (strcmp(dev->device->driver->name, drv->driver.name))
4080                 return false;
4081
4082         return true;
4083 }
4084
4085 bool is_bnxt_supported(struct rte_eth_dev *dev)
4086 {
4087         return is_device_supported(dev, &bnxt_rte_pmd);
4088 }
4089
4090 RTE_INIT(bnxt_init_log)
4091 {
4092         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4093         if (bnxt_logtype_driver >= 0)
4094                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4095 }
4096
4097 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4098 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4099 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");