drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29
  30 #define DRV_MODULE_NAME         "bnxt"
  31 static const char bnxt_version[] =
  32         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  33 int bnxt_logtype_driver;
  34
  35 /*
  36  * The set of PCI devices this driver supports
  37  */
  38 static const struct rte_pci_id bnxt_pci_id_map[] = {
  39         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  40                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  41         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  42                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  43         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  86         { .vendor_id = 0, /* sentinel */ },
  87 };
  88
  89 #define BNXT_ETH_RSS_SUPPORT (  \
  90         ETH_RSS_IPV4 |          \
  91         ETH_RSS_NONFRAG_IPV4_TCP |      \
  92         ETH_RSS_NONFRAG_IPV4_UDP |      \
  93         ETH_RSS_IPV6 |          \
  94         ETH_RSS_NONFRAG_IPV6_TCP |      \
  95         ETH_RSS_NONFRAG_IPV6_UDP)
  96
  97 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
  98                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
  99                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 100                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 101                                      DEV_TX_OFFLOAD_TCP_TSO | \
 102                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 103                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 104                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 105                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 106                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 107                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 108                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 109
 110 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 111                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 112                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 113                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 114                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 115                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 116                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 117                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 118                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 119                                      DEV_RX_OFFLOAD_TCP_LRO | \
 120                                      DEV_RX_OFFLOAD_SCATTER)
 121
 122 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 123 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 124 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 125 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 126 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 127 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 128 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 129
 130 int is_bnxt_in_error(struct bnxt *bp)
 131 {
 132         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 133                 return -EIO;
 134         if (bp->flags & BNXT_FLAG_FW_RESET)
 135                 return -EBUSY;
 136
 137         return 0;
 138 }
 139
 140 /***********************/
 141
 142 /*
 143  * High level utility functions
 144  */
 145
 146 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 147 {
 148         if (!BNXT_CHIP_THOR(bp))
 149                 return 1;
 150
 151         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 152                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 153                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 154 }
 155
 156 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 157 {
 158         if (!BNXT_CHIP_THOR(bp))
 159                 return HW_HASH_INDEX_SIZE;
 160
 161         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 162 }
 163
 164 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 165 {
 166         bnxt_free_filter_mem(bp);
 167         bnxt_free_vnic_attributes(bp);
 168         bnxt_free_vnic_mem(bp);
 169
 170         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 171          * If the number of rings change across fw update,
 172          * we don't have much choice except to warn the user.
 173          */
 174         if (!reconfig) {
 175                 bnxt_free_stats(bp);
 176                 bnxt_free_tx_rings(bp);
 177                 bnxt_free_rx_rings(bp);
 178         }
 179         bnxt_free_async_cp_ring(bp);
 180         bnxt_free_rxtx_nq_ring(bp);
 181 }
 182
 183 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 184 {
 185         int rc;
 186
 187         rc = bnxt_alloc_ring_grps(bp);
 188         if (rc)
 189                 goto alloc_mem_err;
 190
 191         rc = bnxt_alloc_async_ring_struct(bp);
 192         if (rc)
 193                 goto alloc_mem_err;
 194
 195         rc = bnxt_alloc_vnic_mem(bp);
 196         if (rc)
 197                 goto alloc_mem_err;
 198
 199         rc = bnxt_alloc_vnic_attributes(bp);
 200         if (rc)
 201                 goto alloc_mem_err;
 202
 203         rc = bnxt_alloc_filter_mem(bp);
 204         if (rc)
 205                 goto alloc_mem_err;
 206
 207         rc = bnxt_alloc_async_cp_ring(bp);
 208         if (rc)
 209                 goto alloc_mem_err;
 210
 211         rc = bnxt_alloc_rxtx_nq_ring(bp);
 212         if (rc)
 213                 goto alloc_mem_err;
 214
 215         return 0;
 216
 217 alloc_mem_err:
 218         bnxt_free_mem(bp, reconfig);
 219         return rc;
 220 }
 221
 222 static int bnxt_init_chip(struct bnxt *bp)
 223 {
 224         struct bnxt_rx_queue *rxq;
 225         struct rte_eth_link new;
 226         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 227         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 228         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 229         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 230         uint32_t intr_vector = 0;
 231         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 232         uint32_t vec = BNXT_MISC_VEC_ID;
 233         unsigned int i, j;
 234         int rc;
 235
 236         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 237                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 238                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 239                 bp->flags |= BNXT_FLAG_JUMBO;
 240         } else {
 241                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 242                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 243                 bp->flags &= ~BNXT_FLAG_JUMBO;
 244         }
 245
 246         /* THOR does not support ring groups.
 247          * But we will use the array to save RSS context IDs.
 248          */
 249         if (BNXT_CHIP_THOR(bp))
 250                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 251
 252         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 253         if (rc) {
 254                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 255                 goto err_out;
 256         }
 257
 258         rc = bnxt_alloc_hwrm_rings(bp);
 259         if (rc) {
 260                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 261                 goto err_out;
 262         }
 263
 264         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 265         if (rc) {
 266                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 267                 goto err_out;
 268         }
 269
 270         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 271                 goto skip_cosq_cfg;
 272
 273         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 274                 if (bp->rx_cos_queue[i].id != 0xff) {
 275                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 276
 277                         if (!vnic) {
 278                                 PMD_DRV_LOG(ERR,
 279                                             "Num pools more than FW profile\n");
 280                                 rc = -EINVAL;
 281                                 goto err_out;
 282                         }
 283                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 284                         bp->rx_cosq_cnt++;
 285                 }
 286         }
 287
 288 skip_cosq_cfg:
 289         rc = bnxt_mq_rx_configure(bp);
 290         if (rc) {
 291                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 292                 goto err_out;
 293         }
 294
 295         /* VNIC configuration */
 296         for (i = 0; i < bp->nr_vnics; i++) {
 297                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 298                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 299
 300                 rc = bnxt_vnic_grp_alloc(bp, vnic);
 301                 if (rc)
 302                         goto err_out;
 303
 304                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 305                             i, vnic, vnic->fw_grp_ids);
 306
 307                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 308                 if (rc) {
 309                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 310                                 i, rc);
 311                         goto err_out;
 312                 }
 313
 314                 /* Alloc RSS context only if RSS mode is enabled */
 315                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 316                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 317
 318                         rc = 0;
 319                         for (j = 0; j < nr_ctxs; j++) {
 320                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 321                                 if (rc)
 322                                         break;
 323                         }
 324                         if (rc) {
 325                                 PMD_DRV_LOG(ERR,
 326                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 327                                   i, j, rc);
 328                                 goto err_out;
 329                         }
 330                         vnic->num_lb_ctxts = nr_ctxs;
 331                 }
 332
 333                 /*
 334                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 335                  * setting is not available at this time, it will not be
 336                  * configured correctly in the CFA.
 337                  */
 338                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 339                         vnic->vlan_strip = true;
 340                 else
 341                         vnic->vlan_strip = false;
 342
 343                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 344                 if (rc) {
 345                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 346                                 i, rc);
 347                         goto err_out;
 348                 }
 349
 350                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 351                 if (rc) {
 352                         PMD_DRV_LOG(ERR,
 353                                 "HWRM vnic %d filter failure rc: %x\n",
 354                                 i, rc);
 355                         goto err_out;
 356                 }
 357
 358                 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 359                         rxq = bp->eth_dev->data->rx_queues[j];
 360
 361                         PMD_DRV_LOG(DEBUG,
 362                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 363                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 364
 365                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 366                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 367                 }
 368
 369                 rc = bnxt_vnic_rss_configure(bp, vnic);
 370                 if (rc) {
 371                         PMD_DRV_LOG(ERR,
 372                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 373                         goto err_out;
 374                 }
 375
 376                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 377
 378                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 379                     DEV_RX_OFFLOAD_TCP_LRO)
 380                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 381                 else
 382                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 383         }
 384         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 385         if (rc) {
 386                 PMD_DRV_LOG(ERR,
 387                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 388                 goto err_out;
 389         }
 390
 391         /* check and configure queue intr-vector mapping */
 392         if ((rte_intr_cap_multiple(intr_handle) ||
 393              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 394             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 395                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 396                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 397                 if (intr_vector > bp->rx_cp_nr_rings) {
 398                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 399                                         bp->rx_cp_nr_rings);
 400                         return -ENOTSUP;
 401                 }
 402                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 403                 if (rc)
 404                         return rc;
 405         }
 406
 407         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 408                 intr_handle->intr_vec =
 409                         rte_zmalloc("intr_vec",
 410                                     bp->eth_dev->data->nb_rx_queues *
 411                                     sizeof(int), 0);
 412                 if (intr_handle->intr_vec == NULL) {
 413                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 414                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 415                         rc = -ENOMEM;
 416                         goto err_disable;
 417                 }
 418                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 419                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 420                          intr_handle->intr_vec, intr_handle->nb_efd,
 421                         intr_handle->max_intr);
 422                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 423                      queue_id++) {
 424                         intr_handle->intr_vec[queue_id] =
 425                                                         vec + BNXT_RX_VEC_START;
 426                         if (vec < base + intr_handle->nb_efd - 1)
 427                                 vec++;
 428                 }
 429         }
 430
 431         /* enable uio/vfio intr/eventfd mapping */
 432         rc = rte_intr_enable(intr_handle);
 433         if (rc)
 434                 goto err_free;
 435
 436         rc = bnxt_get_hwrm_link_config(bp, &new);
 437         if (rc) {
 438                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 439                 goto err_free;
 440         }
 441
 442         if (!bp->link_info.link_up) {
 443                 rc = bnxt_set_hwrm_link_config(bp, true);
 444                 if (rc) {
 445                         PMD_DRV_LOG(ERR,
 446                                 "HWRM link config failure rc: %x\n", rc);
 447                         goto err_free;
 448                 }
 449         }
 450         bnxt_print_link_info(bp->eth_dev);
 451
 452         return 0;
 453
 454 err_free:
 455         rte_free(intr_handle->intr_vec);
 456 err_disable:
 457         rte_intr_efd_disable(intr_handle);
 458 err_out:
 459         /* Some of the error status returned by FW may not be from errno.h */
 460         if (rc > 0)
 461                 rc = -EIO;
 462
 463         return rc;
 464 }
 465
 466 static int bnxt_shutdown_nic(struct bnxt *bp)
 467 {
 468         bnxt_free_all_hwrm_resources(bp);
 469         bnxt_free_all_filters(bp);
 470         bnxt_free_all_vnics(bp);
 471         return 0;
 472 }
 473
 474 static int bnxt_init_nic(struct bnxt *bp)
 475 {
 476         int rc;
 477
 478         if (BNXT_HAS_RING_GRPS(bp)) {
 479                 rc = bnxt_init_ring_grps(bp);
 480                 if (rc)
 481                         return rc;
 482         }
 483
 484         bnxt_init_vnics(bp);
 485         bnxt_init_filters(bp);
 486
 487         return 0;
 488 }
 489
 490 /*
 491  * Device configuration and status function
 492  */
 493
 494 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 495                                 struct rte_eth_dev_info *dev_info)
 496 {
 497         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 498         struct bnxt *bp = eth_dev->data->dev_private;
 499         uint16_t max_vnics, i, j, vpool, vrxq;
 500         unsigned int max_rx_rings;
 501         int rc;
 502
 503         rc = is_bnxt_in_error(bp);
 504         if (rc)
 505                 return rc;
 506
 507         /* MAC Specifics */
 508         dev_info->max_mac_addrs = bp->max_l2_ctx;
 509         dev_info->max_hash_mac_addrs = 0;
 510
 511         /* PF/VF specifics */
 512         if (BNXT_PF(bp))
 513                 dev_info->max_vfs = pdev->max_vfs;
 514
 515         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 516         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 517         dev_info->max_rx_queues = max_rx_rings;
 518         dev_info->max_tx_queues = max_rx_rings;
 519         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 520         dev_info->hash_key_size = 40;
 521         max_vnics = bp->max_vnics;
 522
 523         /* MTU specifics */
 524         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 525         dev_info->max_mtu = BNXT_MAX_MTU;
 526
 527         /* Fast path specifics */
 528         dev_info->min_rx_bufsize = 1;
 529         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 530
 531         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 532         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 533                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 534         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 535         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 536
 537         /* *INDENT-OFF* */
 538         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 539                 .rx_thresh = {
 540                         .pthresh = 8,
 541                         .hthresh = 8,
 542                         .wthresh = 0,
 543                 },
 544                 .rx_free_thresh = 32,
 545                 /* If no descriptors available, pkts are dropped by default */
 546                 .rx_drop_en = 1,
 547         };
 548
 549         dev_info->default_txconf = (struct rte_eth_txconf) {
 550                 .tx_thresh = {
 551                         .pthresh = 32,
 552                         .hthresh = 0,
 553                         .wthresh = 0,
 554                 },
 555                 .tx_free_thresh = 32,
 556                 .tx_rs_thresh = 32,
 557         };
 558         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 559
 560         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 561         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 562         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 563         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 564         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 565
 566         /* *INDENT-ON* */
 567
 568         /*
 569          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 570          *       need further investigation.
 571          */
 572
 573         /* VMDq resources */
 574         vpool = 64; /* ETH_64_POOLS */
 575         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 576         for (i = 0; i < 4; vpool >>= 1, i++) {
 577                 if (max_vnics > vpool) {
 578                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 579                                 if (dev_info->max_rx_queues > vrxq) {
 580                                         if (vpool > vrxq)
 581                                                 vpool = vrxq;
 582                                         goto found;
 583                                 }
 584                         }
 585                         /* Not enough resources to support VMDq */
 586                         break;
 587                 }
 588         }
 589         /* Not enough resources to support VMDq */
 590         vpool = 0;
 591         vrxq = 0;
 592 found:
 593         dev_info->max_vmdq_pools = vpool;
 594         dev_info->vmdq_queue_num = vrxq;
 595
 596         dev_info->vmdq_pool_base = 0;
 597         dev_info->vmdq_queue_base = 0;
 598
 599         return 0;
 600 }
 601
 602 /* Configure the device based on the configuration provided */
 603 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 604 {
 605         struct bnxt *bp = eth_dev->data->dev_private;
 606         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 607         int rc;
 608
 609         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 610         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 611         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 612         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 613
 614         rc = is_bnxt_in_error(bp);
 615         if (rc)
 616                 return rc;
 617
 618         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 619                 rc = bnxt_hwrm_check_vf_rings(bp);
 620                 if (rc) {
 621                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 622                         return -ENOSPC;
 623                 }
 624
 625                 /* If a resource has already been allocated - in this case
 626                  * it is the async completion ring, free it. Reallocate it after
 627                  * resource reservation. This will ensure the resource counts
 628                  * are calculated correctly.
 629                  */
 630
 631                 pthread_mutex_lock(&bp->def_cp_lock);
 632
 633                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 634                         bnxt_disable_int(bp);
 635                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 636                 }
 637
 638                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 639                 if (rc) {
 640                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 641                         pthread_mutex_unlock(&bp->def_cp_lock);
 642                         return -ENOSPC;
 643                 }
 644
 645                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 646                         rc = bnxt_alloc_async_cp_ring(bp);
 647                         if (rc) {
 648                                 pthread_mutex_unlock(&bp->def_cp_lock);
 649                                 return rc;
 650                         }
 651                         bnxt_enable_int(bp);
 652                 }
 653
 654                 pthread_mutex_unlock(&bp->def_cp_lock);
 655         } else {
 656                 /* legacy driver needs to get updated values */
 657                 rc = bnxt_hwrm_func_qcaps(bp);
 658                 if (rc) {
 659                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 660                         return rc;
 661                 }
 662         }
 663
 664         /* Inherit new configurations */
 665         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 666             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 667             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 668                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 669             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 670             bp->max_stat_ctx)
 671                 goto resource_error;
 672
 673         if (BNXT_HAS_RING_GRPS(bp) &&
 674             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 675                 goto resource_error;
 676
 677         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 678             bp->max_vnics < eth_dev->data->nb_rx_queues)
 679                 goto resource_error;
 680
 681         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 682         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 683
 684         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 685                 eth_dev->data->mtu =
 686                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 687                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 688                         BNXT_NUM_VLANS;
 689                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 690         }
 691         return 0;
 692
 693 resource_error:
 694         PMD_DRV_LOG(ERR,
 695                     "Insufficient resources to support requested config\n");
 696         PMD_DRV_LOG(ERR,
 697                     "Num Queues Requested: Tx %d, Rx %d\n",
 698                     eth_dev->data->nb_tx_queues,
 699                     eth_dev->data->nb_rx_queues);
 700         PMD_DRV_LOG(ERR,
 701                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 702                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 703                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 704         return -ENOSPC;
 705 }
 706
 707 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 708 {
 709         struct rte_eth_link *link = &eth_dev->data->dev_link;
 710
 711         if (link->link_status)
 712                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 713                         eth_dev->data->port_id,
 714                         (uint32_t)link->link_speed,
 715                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 716                         ("full-duplex") : ("half-duplex\n"));
 717         else
 718                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 719                         eth_dev->data->port_id);
 720 }
 721
 722 /*
 723  * Determine whether the current configuration requires support for scattered
 724  * receive; return 1 if scattered receive is required and 0 if not.
 725  */
 726 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 727 {
 728         uint16_t buf_size;
 729         int i;
 730
 731         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 732                 return 1;
 733
 734         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 735                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 736
 737                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 738                                       RTE_PKTMBUF_HEADROOM);
 739                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 740                         return 1;
 741         }
 742         return 0;
 743 }
 744
 745 static eth_rx_burst_t
 746 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 747 {
 748 #ifdef RTE_ARCH_X86
 749 #ifndef RTE_LIBRTE_IEEE1588
 750         /*
 751          * Vector mode receive can be enabled only if scatter rx is not
 752          * in use and rx offloads are limited to VLAN stripping and
 753          * CRC stripping.
 754          */
 755         if (!eth_dev->data->scattered_rx &&
 756             !(eth_dev->data->dev_conf.rxmode.offloads &
 757               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 758                 DEV_RX_OFFLOAD_KEEP_CRC |
 759                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 760                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 761                 DEV_RX_OFFLOAD_UDP_CKSUM |
 762                 DEV_RX_OFFLOAD_TCP_CKSUM |
 763                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 764                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 765                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 766                             eth_dev->data->port_id);
 767                 return bnxt_recv_pkts_vec;
 768         }
 769         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 770                     eth_dev->data->port_id);
 771         PMD_DRV_LOG(INFO,
 772                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 773                     eth_dev->data->port_id,
 774                     eth_dev->data->scattered_rx,
 775                     eth_dev->data->dev_conf.rxmode.offloads);
 776 #endif
 777 #endif
 778         return bnxt_recv_pkts;
 779 }
 780
 781 static eth_tx_burst_t
 782 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 783 {
 784 #ifdef RTE_ARCH_X86
 785 #ifndef RTE_LIBRTE_IEEE1588
 786         /*
 787          * Vector mode transmit can be enabled only if not using scatter rx
 788          * or tx offloads.
 789          */
 790         if (!eth_dev->data->scattered_rx &&
 791             !eth_dev->data->dev_conf.txmode.offloads) {
 792                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 793                             eth_dev->data->port_id);
 794                 return bnxt_xmit_pkts_vec;
 795         }
 796         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 797                     eth_dev->data->port_id);
 798         PMD_DRV_LOG(INFO,
 799                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 800                     eth_dev->data->port_id,
 801                     eth_dev->data->scattered_rx,
 802                     eth_dev->data->dev_conf.txmode.offloads);
 803 #endif
 804 #endif
 805         return bnxt_xmit_pkts;
 806 }
 807
 808 static int bnxt_handle_if_change_status(struct bnxt *bp)
 809 {
 810         int rc;
 811
 812         /* Since fw has undergone a reset and lost all contexts,
 813          * set fatal flag to not issue hwrm during cleanup
 814          */
 815         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 816         bnxt_uninit_resources(bp, true);
 817
 818         /* clear fatal flag so that re-init happens */
 819         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 820         rc = bnxt_init_resources(bp, true);
 821
 822         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 823
 824         return rc;
 825 }
 826
 827 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 828 {
 829         struct bnxt *bp = eth_dev->data->dev_private;
 830         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 831         int vlan_mask = 0;
 832         int rc;
 833
 834         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 835                 PMD_DRV_LOG(ERR,
 836                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 837                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 838         }
 839
 840         rc = bnxt_hwrm_if_change(bp, 1);
 841         if (!rc) {
 842                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 843                         rc = bnxt_handle_if_change_status(bp);
 844                         if (rc)
 845                                 return rc;
 846                 }
 847         }
 848         bnxt_enable_int(bp);
 849
 850         rc = bnxt_init_chip(bp);
 851         if (rc)
 852                 goto error;
 853
 854         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 855
 856         bnxt_link_update_op(eth_dev, 1);
 857
 858         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 859                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 860         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 861                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 862         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 863         if (rc)
 864                 goto error;
 865
 866         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 867         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 868
 869         bp->flags |= BNXT_FLAG_INIT_DONE;
 870         eth_dev->data->dev_started = 1;
 871         bp->dev_stopped = 0;
 872         bnxt_schedule_fw_health_check(bp);
 873         return 0;
 874
 875 error:
 876         bnxt_hwrm_if_change(bp, 0);
 877         bnxt_shutdown_nic(bp);
 878         bnxt_free_tx_mbufs(bp);
 879         bnxt_free_rx_mbufs(bp);
 880         return rc;
 881 }
 882
 883 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 884 {
 885         struct bnxt *bp = eth_dev->data->dev_private;
 886         int rc = 0;
 887
 888         if (!bp->link_info.link_up)
 889                 rc = bnxt_set_hwrm_link_config(bp, true);
 890         if (!rc)
 891                 eth_dev->data->dev_link.link_status = 1;
 892
 893         bnxt_print_link_info(eth_dev);
 894         return rc;
 895 }
 896
 897 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 898 {
 899         struct bnxt *bp = eth_dev->data->dev_private;
 900
 901         eth_dev->data->dev_link.link_status = 0;
 902         bnxt_set_hwrm_link_config(bp, false);
 903         bp->link_info.link_up = 0;
 904
 905         return 0;
 906 }
 907
 908 /* Unload the driver, release resources */
 909 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 910 {
 911         struct bnxt *bp = eth_dev->data->dev_private;
 912         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 913         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 914
 915         eth_dev->data->dev_started = 0;
 916         /* Prevent crashes when queues are still in use */
 917         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 918         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 919
 920         bnxt_disable_int(bp);
 921
 922         /* disable uio/vfio intr/eventfd mapping */
 923         rte_intr_disable(intr_handle);
 924
 925         bnxt_cancel_fw_health_check(bp);
 926
 927         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 928         if (bp->eth_dev->data->dev_started) {
 929                 /* TBD: STOP HW queues DMA */
 930                 eth_dev->data->dev_link.link_status = 0;
 931         }
 932         bnxt_dev_set_link_down_op(eth_dev);
 933
 934         /* Wait for link to be reset and the async notification to process.
 935          * During reset recovery, there is no need to wait
 936          */
 937         if (!is_bnxt_in_error(bp))
 938                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
 939
 940         /* Clean queue intr-vector mapping */
 941         rte_intr_efd_disable(intr_handle);
 942         if (intr_handle->intr_vec != NULL) {
 943                 rte_free(intr_handle->intr_vec);
 944                 intr_handle->intr_vec = NULL;
 945         }
 946
 947         bnxt_hwrm_port_clr_stats(bp);
 948         bnxt_free_tx_mbufs(bp);
 949         bnxt_free_rx_mbufs(bp);
 950         /* Process any remaining notifications in default completion queue */
 951         bnxt_int_handler(eth_dev);
 952         bnxt_shutdown_nic(bp);
 953         bnxt_hwrm_if_change(bp, 0);
 954         bp->dev_stopped = 1;
 955 }
 956
 957 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 958 {
 959         struct bnxt *bp = eth_dev->data->dev_private;
 960
 961         if (bp->dev_stopped == 0)
 962                 bnxt_dev_stop_op(eth_dev);
 963
 964         if (eth_dev->data->mac_addrs != NULL) {
 965                 rte_free(eth_dev->data->mac_addrs);
 966                 eth_dev->data->mac_addrs = NULL;
 967         }
 968         if (bp->grp_info != NULL) {
 969                 rte_free(bp->grp_info);
 970                 bp->grp_info = NULL;
 971         }
 972
 973         bnxt_dev_uninit(eth_dev);
 974 }
 975
 976 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 977                                     uint32_t index)
 978 {
 979         struct bnxt *bp = eth_dev->data->dev_private;
 980         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 981         struct bnxt_vnic_info *vnic;
 982         struct bnxt_filter_info *filter, *temp_filter;
 983         uint32_t i;
 984
 985         if (is_bnxt_in_error(bp))
 986                 return;
 987
 988         /*
 989          * Loop through all VNICs from the specified filter flow pools to
 990          * remove the corresponding MAC addr filter
 991          */
 992         for (i = 0; i < bp->nr_vnics; i++) {
 993                 if (!(pool_mask & (1ULL << i)))
 994                         continue;
 995
 996                 vnic = &bp->vnic_info[i];
 997                 filter = STAILQ_FIRST(&vnic->filter);
 998                 while (filter) {
 999                         temp_filter = STAILQ_NEXT(filter, next);
1000                         if (filter->mac_index == index) {
1001                                 STAILQ_REMOVE(&vnic->filter, filter,
1002                                                 bnxt_filter_info, next);
1003                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1004                                 filter->mac_index = INVALID_MAC_INDEX;
1005                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1006                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1007                                                    filter, next);
1008                         }
1009                         filter = temp_filter;
1010                 }
1011         }
1012 }
1013
1014 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1015                                struct rte_ether_addr *mac_addr, uint32_t index)
1016 {
1017         struct bnxt_filter_info *filter;
1018         int rc = 0;
1019
1020         filter = STAILQ_FIRST(&vnic->filter);
1021         /* During bnxt_mac_addr_add_op, default MAC is
1022          * already programmed, so skip it. But, when
1023          * hw-vlan-filter is turned OFF from ON, default
1024          * MAC filter should be restored
1025          */
1026         if (index == 0 && filter->dflt)
1027                 return 0;
1028
1029         filter = bnxt_alloc_filter(bp);
1030         if (!filter) {
1031                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1032                 return -ENODEV;
1033         }
1034
1035         filter->mac_index = index;
1036         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1037          * if the MAC that's been programmed now is a different one, then,
1038          * copy that addr to filter->l2_addr
1039          */
1040         if (mac_addr)
1041                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1042         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1043
1044         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1045         if (!rc) {
1046                 if (filter->mac_index == 0) {
1047                         filter->dflt = true;
1048                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1049                 } else {
1050                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1051                 }
1052         } else {
1053                 filter->mac_index = INVALID_MAC_INDEX;
1054                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1055                 bnxt_free_filter(bp, filter);
1056         }
1057
1058         return rc;
1059 }
1060
1061 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1062                                 struct rte_ether_addr *mac_addr,
1063                                 uint32_t index, uint32_t pool)
1064 {
1065         struct bnxt *bp = eth_dev->data->dev_private;
1066         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1067         struct bnxt_filter_info *filter;
1068         int rc = 0;
1069
1070         rc = is_bnxt_in_error(bp);
1071         if (rc)
1072                 return rc;
1073
1074         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1075                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1076                 return -ENOTSUP;
1077         }
1078
1079         if (!vnic) {
1080                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1081                 return -EINVAL;
1082         }
1083         /* Attach requested MAC address to the new l2_filter */
1084         STAILQ_FOREACH(filter, &vnic->filter, next) {
1085                 if (filter->mac_index == index) {
1086                         PMD_DRV_LOG(ERR,
1087                                 "MAC addr already existed for pool %d\n", pool);
1088                         return 0;
1089                 }
1090         }
1091
1092         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index);
1093
1094         return rc;
1095 }
1096
1097 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1098 {
1099         int rc = 0;
1100         struct bnxt *bp = eth_dev->data->dev_private;
1101         struct rte_eth_link new;
1102         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1103
1104         rc = is_bnxt_in_error(bp);
1105         if (rc)
1106                 return rc;
1107
1108         memset(&new, 0, sizeof(new));
1109         do {
1110                 /* Retrieve link info from hardware */
1111                 rc = bnxt_get_hwrm_link_config(bp, &new);
1112                 if (rc) {
1113                         new.link_speed = ETH_LINK_SPEED_100M;
1114                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1115                         PMD_DRV_LOG(ERR,
1116                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1117                         goto out;
1118                 }
1119
1120                 if (!wait_to_complete || new.link_status)
1121                         break;
1122
1123                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1124         } while (cnt--);
1125
1126 out:
1127         /* Timed out or success */
1128         if (new.link_status != eth_dev->data->dev_link.link_status ||
1129         new.link_speed != eth_dev->data->dev_link.link_speed) {
1130                 rte_eth_linkstatus_set(eth_dev, &new);
1131
1132                 _rte_eth_dev_callback_process(eth_dev,
1133                                               RTE_ETH_EVENT_INTR_LSC,
1134                                               NULL);
1135
1136                 bnxt_print_link_info(eth_dev);
1137         }
1138
1139         return rc;
1140 }
1141
1142 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1143 {
1144         struct bnxt *bp = eth_dev->data->dev_private;
1145         struct bnxt_vnic_info *vnic;
1146         uint32_t old_flags;
1147         int rc;
1148
1149         rc = is_bnxt_in_error(bp);
1150         if (rc)
1151                 return rc;
1152
1153         if (bp->vnic_info == NULL)
1154                 return 0;
1155
1156         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1157
1158         old_flags = vnic->flags;
1159         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1160         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1161         if (rc != 0)
1162                 vnic->flags = old_flags;
1163
1164         return rc;
1165 }
1166
1167 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1168 {
1169         struct bnxt *bp = eth_dev->data->dev_private;
1170         struct bnxt_vnic_info *vnic;
1171         uint32_t old_flags;
1172         int rc;
1173
1174         rc = is_bnxt_in_error(bp);
1175         if (rc)
1176                 return rc;
1177
1178         if (bp->vnic_info == NULL)
1179                 return 0;
1180
1181         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1182
1183         old_flags = vnic->flags;
1184         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1185         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1186         if (rc != 0)
1187                 vnic->flags = old_flags;
1188
1189         return rc;
1190 }
1191
1192 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1193 {
1194         struct bnxt *bp = eth_dev->data->dev_private;
1195         struct bnxt_vnic_info *vnic;
1196         uint32_t old_flags;
1197         int rc;
1198
1199         rc = is_bnxt_in_error(bp);
1200         if (rc)
1201                 return rc;
1202
1203         if (bp->vnic_info == NULL)
1204                 return 0;
1205
1206         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1207
1208         old_flags = vnic->flags;
1209         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1210         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1211         if (rc != 0)
1212                 vnic->flags = old_flags;
1213
1214         return rc;
1215 }
1216
1217 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1218 {
1219         struct bnxt *bp = eth_dev->data->dev_private;
1220         struct bnxt_vnic_info *vnic;
1221         uint32_t old_flags;
1222         int rc;
1223
1224         rc = is_bnxt_in_error(bp);
1225         if (rc)
1226                 return rc;
1227
1228         if (bp->vnic_info == NULL)
1229                 return 0;
1230
1231         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1232
1233         old_flags = vnic->flags;
1234         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1235         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1236         if (rc != 0)
1237                 vnic->flags = old_flags;
1238
1239         return rc;
1240 }
1241
1242 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1243 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1244 {
1245         if (qid >= bp->rx_nr_rings)
1246                 return NULL;
1247
1248         return bp->eth_dev->data->rx_queues[qid];
1249 }
1250
1251 /* Return rxq corresponding to a given rss table ring/group ID. */
1252 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1253 {
1254         struct bnxt_rx_queue *rxq;
1255         unsigned int i;
1256
1257         if (!BNXT_HAS_RING_GRPS(bp)) {
1258                 for (i = 0; i < bp->rx_nr_rings; i++) {
1259                         rxq = bp->eth_dev->data->rx_queues[i];
1260                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1261                                 return rxq->index;
1262                 }
1263         } else {
1264                 for (i = 0; i < bp->rx_nr_rings; i++) {
1265                         if (bp->grp_info[i].fw_grp_id == fwr)
1266                                 return i;
1267                 }
1268         }
1269
1270         return INVALID_HW_RING_ID;
1271 }
1272
1273 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1274                             struct rte_eth_rss_reta_entry64 *reta_conf,
1275                             uint16_t reta_size)
1276 {
1277         struct bnxt *bp = eth_dev->data->dev_private;
1278         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1279         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1280         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1281         uint16_t idx, sft;
1282         int i, rc;
1283
1284         rc = is_bnxt_in_error(bp);
1285         if (rc)
1286                 return rc;
1287
1288         if (!vnic->rss_table)
1289                 return -EINVAL;
1290
1291         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1292                 return -EINVAL;
1293
1294         if (reta_size != tbl_size) {
1295                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1296                         "(%d) must equal the size supported by the hardware "
1297                         "(%d)\n", reta_size, tbl_size);
1298                 return -EINVAL;
1299         }
1300
1301         for (i = 0; i < reta_size; i++) {
1302                 struct bnxt_rx_queue *rxq;
1303
1304                 idx = i / RTE_RETA_GROUP_SIZE;
1305                 sft = i % RTE_RETA_GROUP_SIZE;
1306
1307                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1308                         continue;
1309
1310                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1311                 if (!rxq) {
1312                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1313                         return -EINVAL;
1314                 }
1315
1316                 if (BNXT_CHIP_THOR(bp)) {
1317                         vnic->rss_table[i * 2] =
1318                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1319                         vnic->rss_table[i * 2 + 1] =
1320                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1321                 } else {
1322                         vnic->rss_table[i] =
1323                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1324                 }
1325         }
1326
1327         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1328         return 0;
1329 }
1330
1331 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1332                               struct rte_eth_rss_reta_entry64 *reta_conf,
1333                               uint16_t reta_size)
1334 {
1335         struct bnxt *bp = eth_dev->data->dev_private;
1336         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1337         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1338         uint16_t idx, sft, i;
1339         int rc;
1340
1341         rc = is_bnxt_in_error(bp);
1342         if (rc)
1343                 return rc;
1344
1345         /* Retrieve from the default VNIC */
1346         if (!vnic)
1347                 return -EINVAL;
1348         if (!vnic->rss_table)
1349                 return -EINVAL;
1350
1351         if (reta_size != tbl_size) {
1352                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1353                         "(%d) must equal the size supported by the hardware "
1354                         "(%d)\n", reta_size, tbl_size);
1355                 return -EINVAL;
1356         }
1357
1358         for (idx = 0, i = 0; i < reta_size; i++) {
1359                 idx = i / RTE_RETA_GROUP_SIZE;
1360                 sft = i % RTE_RETA_GROUP_SIZE;
1361
1362                 if (reta_conf[idx].mask & (1ULL << sft)) {
1363                         uint16_t qid;
1364
1365                         if (BNXT_CHIP_THOR(bp))
1366                                 qid = bnxt_rss_to_qid(bp,
1367                                                       vnic->rss_table[i * 2]);
1368                         else
1369                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1370
1371                         if (qid == INVALID_HW_RING_ID) {
1372                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1373                                 return -EINVAL;
1374                         }
1375                         reta_conf[idx].reta[sft] = qid;
1376                 }
1377         }
1378
1379         return 0;
1380 }
1381
1382 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1383                                    struct rte_eth_rss_conf *rss_conf)
1384 {
1385         struct bnxt *bp = eth_dev->data->dev_private;
1386         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1387         struct bnxt_vnic_info *vnic;
1388         int rc;
1389
1390         rc = is_bnxt_in_error(bp);
1391         if (rc)
1392                 return rc;
1393
1394         /*
1395          * If RSS enablement were different than dev_configure,
1396          * then return -EINVAL
1397          */
1398         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1399                 if (!rss_conf->rss_hf)
1400                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1401         } else {
1402                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1403                         return -EINVAL;
1404         }
1405
1406         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1407         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1408
1409         /* Update the default RSS VNIC(s) */
1410         vnic = &bp->vnic_info[0];
1411         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1412
1413         /*
1414          * If hashkey is not specified, use the previously configured
1415          * hashkey
1416          */
1417         if (!rss_conf->rss_key)
1418                 goto rss_config;
1419
1420         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1421                 PMD_DRV_LOG(ERR,
1422                             "Invalid hashkey length, should be 16 bytes\n");
1423                 return -EINVAL;
1424         }
1425         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1426
1427 rss_config:
1428         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1429         return 0;
1430 }
1431
1432 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1433                                      struct rte_eth_rss_conf *rss_conf)
1434 {
1435         struct bnxt *bp = eth_dev->data->dev_private;
1436         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1437         int len, rc;
1438         uint32_t hash_types;
1439
1440         rc = is_bnxt_in_error(bp);
1441         if (rc)
1442                 return rc;
1443
1444         /* RSS configuration is the same for all VNICs */
1445         if (vnic && vnic->rss_hash_key) {
1446                 if (rss_conf->rss_key) {
1447                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1448                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1449                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1450                 }
1451
1452                 hash_types = vnic->hash_type;
1453                 rss_conf->rss_hf = 0;
1454                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1455                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1456                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1457                 }
1458                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1459                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1460                         hash_types &=
1461                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1462                 }
1463                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1464                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1465                         hash_types &=
1466                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1467                 }
1468                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1469                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1470                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1471                 }
1472                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1473                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1474                         hash_types &=
1475                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1476                 }
1477                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1478                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1479                         hash_types &=
1480                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1481                 }
1482                 if (hash_types) {
1483                         PMD_DRV_LOG(ERR,
1484                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1485                                 vnic->hash_type);
1486                         return -ENOTSUP;
1487                 }
1488         } else {
1489                 rss_conf->rss_hf = 0;
1490         }
1491         return 0;
1492 }
1493
1494 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1495                                struct rte_eth_fc_conf *fc_conf)
1496 {
1497         struct bnxt *bp = dev->data->dev_private;
1498         struct rte_eth_link link_info;
1499         int rc;
1500
1501         rc = is_bnxt_in_error(bp);
1502         if (rc)
1503                 return rc;
1504
1505         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1506         if (rc)
1507                 return rc;
1508
1509         memset(fc_conf, 0, sizeof(*fc_conf));
1510         if (bp->link_info.auto_pause)
1511                 fc_conf->autoneg = 1;
1512         switch (bp->link_info.pause) {
1513         case 0:
1514                 fc_conf->mode = RTE_FC_NONE;
1515                 break;
1516         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1517                 fc_conf->mode = RTE_FC_TX_PAUSE;
1518                 break;
1519         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1520                 fc_conf->mode = RTE_FC_RX_PAUSE;
1521                 break;
1522         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1523                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1524                 fc_conf->mode = RTE_FC_FULL;
1525                 break;
1526         }
1527         return 0;
1528 }
1529
1530 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1531                                struct rte_eth_fc_conf *fc_conf)
1532 {
1533         struct bnxt *bp = dev->data->dev_private;
1534         int rc;
1535
1536         rc = is_bnxt_in_error(bp);
1537         if (rc)
1538                 return rc;
1539
1540         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1541                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1542                 return -ENOTSUP;
1543         }
1544
1545         switch (fc_conf->mode) {
1546         case RTE_FC_NONE:
1547                 bp->link_info.auto_pause = 0;
1548                 bp->link_info.force_pause = 0;
1549                 break;
1550         case RTE_FC_RX_PAUSE:
1551                 if (fc_conf->autoneg) {
1552                         bp->link_info.auto_pause =
1553                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1554                         bp->link_info.force_pause = 0;
1555                 } else {
1556                         bp->link_info.auto_pause = 0;
1557                         bp->link_info.force_pause =
1558                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1559                 }
1560                 break;
1561         case RTE_FC_TX_PAUSE:
1562                 if (fc_conf->autoneg) {
1563                         bp->link_info.auto_pause =
1564                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1565                         bp->link_info.force_pause = 0;
1566                 } else {
1567                         bp->link_info.auto_pause = 0;
1568                         bp->link_info.force_pause =
1569                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1570                 }
1571                 break;
1572         case RTE_FC_FULL:
1573                 if (fc_conf->autoneg) {
1574                         bp->link_info.auto_pause =
1575                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1576                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1577                         bp->link_info.force_pause = 0;
1578                 } else {
1579                         bp->link_info.auto_pause = 0;
1580                         bp->link_info.force_pause =
1581                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1582                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1583                 }
1584                 break;
1585         }
1586         return bnxt_set_hwrm_link_config(bp, true);
1587 }
1588
1589 /* Add UDP tunneling port */
1590 static int
1591 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1592                          struct rte_eth_udp_tunnel *udp_tunnel)
1593 {
1594         struct bnxt *bp = eth_dev->data->dev_private;
1595         uint16_t tunnel_type = 0;
1596         int rc = 0;
1597
1598         rc = is_bnxt_in_error(bp);
1599         if (rc)
1600                 return rc;
1601
1602         switch (udp_tunnel->prot_type) {
1603         case RTE_TUNNEL_TYPE_VXLAN:
1604                 if (bp->vxlan_port_cnt) {
1605                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1606                                 udp_tunnel->udp_port);
1607                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1608                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1609                                 return -ENOSPC;
1610                         }
1611                         bp->vxlan_port_cnt++;
1612                         return 0;
1613                 }
1614                 tunnel_type =
1615                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1616                 bp->vxlan_port_cnt++;
1617                 break;
1618         case RTE_TUNNEL_TYPE_GENEVE:
1619                 if (bp->geneve_port_cnt) {
1620                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1621                                 udp_tunnel->udp_port);
1622                         if (bp->geneve_port != udp_tunnel->udp_port) {
1623                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1624                                 return -ENOSPC;
1625                         }
1626                         bp->geneve_port_cnt++;
1627                         return 0;
1628                 }
1629                 tunnel_type =
1630                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1631                 bp->geneve_port_cnt++;
1632                 break;
1633         default:
1634                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1635                 return -ENOTSUP;
1636         }
1637         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1638                                              tunnel_type);
1639         return rc;
1640 }
1641
1642 static int
1643 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1644                          struct rte_eth_udp_tunnel *udp_tunnel)
1645 {
1646         struct bnxt *bp = eth_dev->data->dev_private;
1647         uint16_t tunnel_type = 0;
1648         uint16_t port = 0;
1649         int rc = 0;
1650
1651         rc = is_bnxt_in_error(bp);
1652         if (rc)
1653                 return rc;
1654
1655         switch (udp_tunnel->prot_type) {
1656         case RTE_TUNNEL_TYPE_VXLAN:
1657                 if (!bp->vxlan_port_cnt) {
1658                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1659                         return -EINVAL;
1660                 }
1661                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1662                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1663                                 udp_tunnel->udp_port, bp->vxlan_port);
1664                         return -EINVAL;
1665                 }
1666                 if (--bp->vxlan_port_cnt)
1667                         return 0;
1668
1669                 tunnel_type =
1670                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1671                 port = bp->vxlan_fw_dst_port_id;
1672                 break;
1673         case RTE_TUNNEL_TYPE_GENEVE:
1674                 if (!bp->geneve_port_cnt) {
1675                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1676                         return -EINVAL;
1677                 }
1678                 if (bp->geneve_port != udp_tunnel->udp_port) {
1679                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1680                                 udp_tunnel->udp_port, bp->geneve_port);
1681                         return -EINVAL;
1682                 }
1683                 if (--bp->geneve_port_cnt)
1684                         return 0;
1685
1686                 tunnel_type =
1687                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1688                 port = bp->geneve_fw_dst_port_id;
1689                 break;
1690         default:
1691                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1692                 return -ENOTSUP;
1693         }
1694
1695         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1696         if (!rc) {
1697                 if (tunnel_type ==
1698                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1699                         bp->vxlan_port = 0;
1700                 if (tunnel_type ==
1701                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1702                         bp->geneve_port = 0;
1703         }
1704         return rc;
1705 }
1706
1707 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1708 {
1709         struct bnxt_filter_info *filter;
1710         struct bnxt_vnic_info *vnic;
1711         int rc = 0;
1712         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1713
1714         /* if VLAN exists && VLAN matches vlan_id
1715          *      remove the MAC+VLAN filter
1716          *      add a new MAC only filter
1717          * else
1718          *      VLAN filter doesn't exist, just skip and continue
1719          */
1720         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1721         filter = STAILQ_FIRST(&vnic->filter);
1722         while (filter) {
1723                 /* Search for this matching MAC+VLAN filter */
1724                 if ((filter->enables & chk) &&
1725                     (filter->l2_ivlan == vlan_id &&
1726                      filter->l2_ivlan_mask != 0) &&
1727                     !memcmp(filter->l2_addr, bp->mac_addr,
1728                             RTE_ETHER_ADDR_LEN)) {
1729                         /* Delete the filter */
1730                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1731                         if (rc)
1732                                 return rc;
1733                         STAILQ_REMOVE(&vnic->filter, filter,
1734                                       bnxt_filter_info, next);
1735                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1736
1737                         PMD_DRV_LOG(INFO,
1738                                     "Del Vlan filter for %d\n",
1739                                     vlan_id);
1740                         return rc;
1741                 }
1742                 filter = STAILQ_NEXT(filter, next);
1743         }
1744         return -ENOENT;
1745 }
1746
1747 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1748 {
1749         struct bnxt_filter_info *filter;
1750         struct bnxt_vnic_info *vnic;
1751         int rc = 0;
1752         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1753                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1754         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1755
1756         /* Implementation notes on the use of VNIC in this command:
1757          *
1758          * By default, these filters belong to default vnic for the function.
1759          * Once these filters are set up, only destination VNIC can be modified.
1760          * If the destination VNIC is not specified in this command,
1761          * then the HWRM shall only create an l2 context id.
1762          */
1763
1764         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1765         filter = STAILQ_FIRST(&vnic->filter);
1766         /* Check if the VLAN has already been added */
1767         while (filter) {
1768                 if ((filter->enables & chk) &&
1769                     (filter->l2_ivlan == vlan_id &&
1770                      filter->l2_ivlan_mask == 0x0FFF) &&
1771                      !memcmp(filter->l2_addr, bp->mac_addr,
1772                              RTE_ETHER_ADDR_LEN))
1773                         return -EEXIST;
1774
1775                 filter = STAILQ_NEXT(filter, next);
1776         }
1777
1778         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1779          * command to create MAC+VLAN filter with the right flags, enables set.
1780          */
1781         filter = bnxt_alloc_filter(bp);
1782         if (!filter) {
1783                 PMD_DRV_LOG(ERR,
1784                             "MAC/VLAN filter alloc failed\n");
1785                 return -ENOMEM;
1786         }
1787         /* MAC + VLAN ID filter */
1788         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1789          * untagged packets are received
1790          *
1791          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1792          * packets and only the programmed vlan's packets are received
1793          */
1794         filter->l2_ivlan = vlan_id;
1795         filter->l2_ivlan_mask = 0x0FFF;
1796         filter->enables |= en;
1797         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1798
1799         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1800         if (rc) {
1801                 /* Free the newly allocated filter as we were
1802                  * not able to create the filter in hardware.
1803                  */
1804                 filter->fw_l2_filter_id = UINT64_MAX;
1805                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1806                 return rc;
1807         } else {
1808                 /* Add this new filter to the list */
1809                 if (vlan_id == 0) {
1810                         filter->dflt = true;
1811                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1812                 } else {
1813                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1814                 }
1815         }
1816
1817         PMD_DRV_LOG(INFO,
1818                     "Added Vlan filter for %d\n", vlan_id);
1819         return rc;
1820 }
1821
1822 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1823                 uint16_t vlan_id, int on)
1824 {
1825         struct bnxt *bp = eth_dev->data->dev_private;
1826         int rc;
1827
1828         rc = is_bnxt_in_error(bp);
1829         if (rc)
1830                 return rc;
1831
1832         /* These operations apply to ALL existing MAC/VLAN filters */
1833         if (on)
1834                 return bnxt_add_vlan_filter(bp, vlan_id);
1835         else
1836                 return bnxt_del_vlan_filter(bp, vlan_id);
1837 }
1838
1839 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1840                                     struct bnxt_vnic_info *vnic)
1841 {
1842         struct bnxt_filter_info *filter;
1843         int rc;
1844
1845         filter = STAILQ_FIRST(&vnic->filter);
1846         while (filter) {
1847                 if (filter->dflt &&
1848                     !memcmp(filter->l2_addr, bp->mac_addr,
1849                             RTE_ETHER_ADDR_LEN)) {
1850                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1851                         if (rc)
1852                                 return rc;
1853                         filter->dflt = false;
1854                         STAILQ_REMOVE(&vnic->filter, filter,
1855                                       bnxt_filter_info, next);
1856                         STAILQ_INSERT_TAIL(&bp->free_filter_list,
1857                                            filter, next);
1858                         filter->fw_l2_filter_id = -1;
1859                         break;
1860                 }
1861                 filter = STAILQ_NEXT(filter, next);
1862         }
1863         return 0;
1864 }
1865
1866 static int
1867 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1868 {
1869         struct bnxt *bp = dev->data->dev_private;
1870         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1871         struct bnxt_vnic_info *vnic;
1872         unsigned int i;
1873         int rc;
1874
1875         rc = is_bnxt_in_error(bp);
1876         if (rc)
1877                 return rc;
1878
1879         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1880         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1881                 /* Remove any VLAN filters programmed */
1882                 for (i = 0; i < 4095; i++)
1883                         bnxt_del_vlan_filter(bp, i);
1884
1885                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0);
1886                 if (rc)
1887                         return rc;
1888         } else {
1889                 /* Default filter will allow packets that match the
1890                  * dest mac. So, it has to be deleted, otherwise, we
1891                  * will endup receiving vlan packets for which the
1892                  * filter is not programmed, when hw-vlan-filter
1893                  * configuration is ON
1894                  */
1895                 bnxt_del_dflt_mac_filter(bp, vnic);
1896                 /* This filter will allow only untagged packets */
1897                 bnxt_add_vlan_filter(bp, 0);
1898         }
1899         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1900                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1901
1902         if (mask & ETH_VLAN_STRIP_MASK) {
1903                 /* Enable or disable VLAN stripping */
1904                 for (i = 0; i < bp->nr_vnics; i++) {
1905                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1906                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1907                                 vnic->vlan_strip = true;
1908                         else
1909                                 vnic->vlan_strip = false;
1910                         bnxt_hwrm_vnic_cfg(bp, vnic);
1911                 }
1912                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1913                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1914         }
1915
1916         if (mask & ETH_VLAN_EXTEND_MASK) {
1917                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1918                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1919                 else
1920                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1921         }
1922
1923         return 0;
1924 }
1925
1926 static int
1927 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1928                       uint16_t tpid)
1929 {
1930         struct bnxt *bp = dev->data->dev_private;
1931         int qinq = dev->data->dev_conf.rxmode.offloads &
1932                    DEV_RX_OFFLOAD_VLAN_EXTEND;
1933
1934         if (vlan_type != ETH_VLAN_TYPE_INNER &&
1935             vlan_type != ETH_VLAN_TYPE_OUTER) {
1936                 PMD_DRV_LOG(ERR,
1937                             "Unsupported vlan type.");
1938                 return -EINVAL;
1939         }
1940         if (!qinq) {
1941                 PMD_DRV_LOG(ERR,
1942                             "QinQ not enabled. Needs to be ON as we can "
1943                             "accelerate only outer vlan\n");
1944                 return -EINVAL;
1945         }
1946
1947         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1948                 switch (tpid) {
1949                 case RTE_ETHER_TYPE_QINQ:
1950                         bp->outer_tpid_bd =
1951                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1952                                 break;
1953                 case RTE_ETHER_TYPE_VLAN:
1954                         bp->outer_tpid_bd =
1955                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1956                                 break;
1957                 case 0x9100:
1958                         bp->outer_tpid_bd =
1959                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1960                                 break;
1961                 case 0x9200:
1962                         bp->outer_tpid_bd =
1963                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1964                                 break;
1965                 case 0x9300:
1966                         bp->outer_tpid_bd =
1967                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1968                                 break;
1969                 default:
1970                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1971                         return -EINVAL;
1972                 }
1973                 bp->outer_tpid_bd |= tpid;
1974                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1975         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1976                 PMD_DRV_LOG(ERR,
1977                             "Can accelerate only outer vlan in QinQ\n");
1978                 return -EINVAL;
1979         }
1980
1981         return 0;
1982 }
1983
1984 static int
1985 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1986                              struct rte_ether_addr *addr)
1987 {
1988         struct bnxt *bp = dev->data->dev_private;
1989         /* Default Filter is tied to VNIC 0 */
1990         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1991         struct bnxt_filter_info *filter;
1992         int rc;
1993
1994         rc = is_bnxt_in_error(bp);
1995         if (rc)
1996                 return rc;
1997
1998         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1999                 return -EPERM;
2000
2001         if (rte_is_zero_ether_addr(addr))
2002                 return -EINVAL;
2003
2004         STAILQ_FOREACH(filter, &vnic->filter, next) {
2005                 /* Default Filter is at Index 0 */
2006                 if (filter->mac_index != 0)
2007                         continue;
2008
2009                 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
2010                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
2011                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
2012                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2013                 filter->enables |=
2014                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
2015                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
2016
2017                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2018                 if (rc) {
2019                         memcpy(filter->l2_addr, bp->mac_addr,
2020                                RTE_ETHER_ADDR_LEN);
2021                         return rc;
2022                 }
2023
2024                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2025                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2026                 return 0;
2027         }
2028
2029         return 0;
2030 }
2031
2032 static int
2033 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2034                           struct rte_ether_addr *mc_addr_set,
2035                           uint32_t nb_mc_addr)
2036 {
2037         struct bnxt *bp = eth_dev->data->dev_private;
2038         char *mc_addr_list = (char *)mc_addr_set;
2039         struct bnxt_vnic_info *vnic;
2040         uint32_t off = 0, i = 0;
2041         int rc;
2042
2043         rc = is_bnxt_in_error(bp);
2044         if (rc)
2045                 return rc;
2046
2047         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2048
2049         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2050                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2051                 goto allmulti;
2052         }
2053
2054         /* TODO Check for Duplicate mcast addresses */
2055         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2056         for (i = 0; i < nb_mc_addr; i++) {
2057                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2058                         RTE_ETHER_ADDR_LEN);
2059                 off += RTE_ETHER_ADDR_LEN;
2060         }
2061
2062         vnic->mc_addr_cnt = i;
2063         if (vnic->mc_addr_cnt)
2064                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2065         else
2066                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2067
2068 allmulti:
2069         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2070 }
2071
2072 static int
2073 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2074 {
2075         struct bnxt *bp = dev->data->dev_private;
2076         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2077         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2078         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2079         int ret;
2080
2081         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2082                         fw_major, fw_minor, fw_updt);
2083
2084         ret += 1; /* add the size of '\0' */
2085         if (fw_size < (uint32_t)ret)
2086                 return ret;
2087         else
2088                 return 0;
2089 }
2090
2091 static void
2092 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2093         struct rte_eth_rxq_info *qinfo)
2094 {
2095         struct bnxt_rx_queue *rxq;
2096
2097         rxq = dev->data->rx_queues[queue_id];
2098
2099         qinfo->mp = rxq->mb_pool;
2100         qinfo->scattered_rx = dev->data->scattered_rx;
2101         qinfo->nb_desc = rxq->nb_rx_desc;
2102
2103         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2104         qinfo->conf.rx_drop_en = 0;
2105         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2106 }
2107
2108 static void
2109 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2110         struct rte_eth_txq_info *qinfo)
2111 {
2112         struct bnxt_tx_queue *txq;
2113
2114         txq = dev->data->tx_queues[queue_id];
2115
2116         qinfo->nb_desc = txq->nb_tx_desc;
2117
2118         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2119         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2120         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2121
2122         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2123         qinfo->conf.tx_rs_thresh = 0;
2124         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2125 }
2126
2127 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2128 {
2129         struct bnxt *bp = eth_dev->data->dev_private;
2130         uint32_t new_pkt_size;
2131         uint32_t rc = 0;
2132         uint32_t i;
2133
2134         rc = is_bnxt_in_error(bp);
2135         if (rc)
2136                 return rc;
2137
2138         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2139                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2140
2141 #ifdef RTE_ARCH_X86
2142         /*
2143          * If vector-mode tx/rx is active, disallow any MTU change that would
2144          * require scattered receive support.
2145          */
2146         if (eth_dev->data->dev_started &&
2147             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2148              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2149             (new_pkt_size >
2150              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2151                 PMD_DRV_LOG(ERR,
2152                             "MTU change would require scattered rx support. ");
2153                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2154                 return -EINVAL;
2155         }
2156 #endif
2157
2158         if (new_mtu > RTE_ETHER_MTU) {
2159                 bp->flags |= BNXT_FLAG_JUMBO;
2160                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2161                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2162         } else {
2163                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2164                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2165                 bp->flags &= ~BNXT_FLAG_JUMBO;
2166         }
2167
2168         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2169
2170         for (i = 0; i < bp->nr_vnics; i++) {
2171                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2172                 uint16_t size = 0;
2173
2174                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2175                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2176                 if (rc)
2177                         break;
2178
2179                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2180                 size -= RTE_PKTMBUF_HEADROOM;
2181
2182                 if (size < new_mtu) {
2183                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2184                         if (rc)
2185                                 return rc;
2186                 }
2187         }
2188
2189         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2190
2191         return rc;
2192 }
2193
2194 static int
2195 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2196 {
2197         struct bnxt *bp = dev->data->dev_private;
2198         uint16_t vlan = bp->vlan;
2199         int rc;
2200
2201         rc = is_bnxt_in_error(bp);
2202         if (rc)
2203                 return rc;
2204
2205         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2206                 PMD_DRV_LOG(ERR,
2207                         "PVID cannot be modified for this function\n");
2208                 return -ENOTSUP;
2209         }
2210         bp->vlan = on ? pvid : 0;
2211
2212         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2213         if (rc)
2214                 bp->vlan = vlan;
2215         return rc;
2216 }
2217
2218 static int
2219 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2220 {
2221         struct bnxt *bp = dev->data->dev_private;
2222         int rc;
2223
2224         rc = is_bnxt_in_error(bp);
2225         if (rc)
2226                 return rc;
2227
2228         return bnxt_hwrm_port_led_cfg(bp, true);
2229 }
2230
2231 static int
2232 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2233 {
2234         struct bnxt *bp = dev->data->dev_private;
2235         int rc;
2236
2237         rc = is_bnxt_in_error(bp);
2238         if (rc)
2239                 return rc;
2240
2241         return bnxt_hwrm_port_led_cfg(bp, false);
2242 }
2243
2244 static uint32_t
2245 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2246 {
2247         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2248         uint32_t desc = 0, raw_cons = 0, cons;
2249         struct bnxt_cp_ring_info *cpr;
2250         struct bnxt_rx_queue *rxq;
2251         struct rx_pkt_cmpl *rxcmp;
2252         int rc;
2253
2254         rc = is_bnxt_in_error(bp);
2255         if (rc)
2256                 return rc;
2257
2258         rxq = dev->data->rx_queues[rx_queue_id];
2259         cpr = rxq->cp_ring;
2260         raw_cons = cpr->cp_raw_cons;
2261
2262         while (1) {
2263                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2264                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2265                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2266
2267                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2268                         break;
2269                 } else {
2270                         raw_cons++;
2271                         desc++;
2272                 }
2273         }
2274
2275         return desc;
2276 }
2277
2278 static int
2279 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2280 {
2281         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2282         struct bnxt_rx_ring_info *rxr;
2283         struct bnxt_cp_ring_info *cpr;
2284         struct bnxt_sw_rx_bd *rx_buf;
2285         struct rx_pkt_cmpl *rxcmp;
2286         uint32_t cons, cp_cons;
2287         int rc;
2288
2289         if (!rxq)
2290                 return -EINVAL;
2291
2292         rc = is_bnxt_in_error(rxq->bp);
2293         if (rc)
2294                 return rc;
2295
2296         cpr = rxq->cp_ring;
2297         rxr = rxq->rx_ring;
2298
2299         if (offset >= rxq->nb_rx_desc)
2300                 return -EINVAL;
2301
2302         cons = RING_CMP(cpr->cp_ring_struct, offset);
2303         cp_cons = cpr->cp_raw_cons;
2304         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2305
2306         if (cons > cp_cons) {
2307                 if (CMPL_VALID(rxcmp, cpr->valid))
2308                         return RTE_ETH_RX_DESC_DONE;
2309         } else {
2310                 if (CMPL_VALID(rxcmp, !cpr->valid))
2311                         return RTE_ETH_RX_DESC_DONE;
2312         }
2313         rx_buf = &rxr->rx_buf_ring[cons];
2314         if (rx_buf->mbuf == NULL)
2315                 return RTE_ETH_RX_DESC_UNAVAIL;
2316
2317
2318         return RTE_ETH_RX_DESC_AVAIL;
2319 }
2320
2321 static int
2322 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2323 {
2324         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2325         struct bnxt_tx_ring_info *txr;
2326         struct bnxt_cp_ring_info *cpr;
2327         struct bnxt_sw_tx_bd *tx_buf;
2328         struct tx_pkt_cmpl *txcmp;
2329         uint32_t cons, cp_cons;
2330         int rc;
2331
2332         if (!txq)
2333                 return -EINVAL;
2334
2335         rc = is_bnxt_in_error(txq->bp);
2336         if (rc)
2337                 return rc;
2338
2339         cpr = txq->cp_ring;
2340         txr = txq->tx_ring;
2341
2342         if (offset >= txq->nb_tx_desc)
2343                 return -EINVAL;
2344
2345         cons = RING_CMP(cpr->cp_ring_struct, offset);
2346         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2347         cp_cons = cpr->cp_raw_cons;
2348
2349         if (cons > cp_cons) {
2350                 if (CMPL_VALID(txcmp, cpr->valid))
2351                         return RTE_ETH_TX_DESC_UNAVAIL;
2352         } else {
2353                 if (CMPL_VALID(txcmp, !cpr->valid))
2354                         return RTE_ETH_TX_DESC_UNAVAIL;
2355         }
2356         tx_buf = &txr->tx_buf_ring[cons];
2357         if (tx_buf->mbuf == NULL)
2358                 return RTE_ETH_TX_DESC_DONE;
2359
2360         return RTE_ETH_TX_DESC_FULL;
2361 }
2362
2363 static struct bnxt_filter_info *
2364 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2365                                 struct rte_eth_ethertype_filter *efilter,
2366                                 struct bnxt_vnic_info *vnic0,
2367                                 struct bnxt_vnic_info *vnic,
2368                                 int *ret)
2369 {
2370         struct bnxt_filter_info *mfilter = NULL;
2371         int match = 0;
2372         *ret = 0;
2373
2374         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2375                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2376                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2377                         " ethertype filter.", efilter->ether_type);
2378                 *ret = -EINVAL;
2379                 goto exit;
2380         }
2381         if (efilter->queue >= bp->rx_nr_rings) {
2382                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2383                 *ret = -EINVAL;
2384                 goto exit;
2385         }
2386
2387         vnic0 = &bp->vnic_info[0];
2388         vnic = &bp->vnic_info[efilter->queue];
2389         if (vnic == NULL) {
2390                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2391                 *ret = -EINVAL;
2392                 goto exit;
2393         }
2394
2395         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2396                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2397                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2398                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2399                              mfilter->flags ==
2400                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2401                              mfilter->ethertype == efilter->ether_type)) {
2402                                 match = 1;
2403                                 break;
2404                         }
2405                 }
2406         } else {
2407                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2408                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2409                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2410                              mfilter->ethertype == efilter->ether_type &&
2411                              mfilter->flags ==
2412                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2413                                 match = 1;
2414                                 break;
2415                         }
2416         }
2417
2418         if (match)
2419                 *ret = -EEXIST;
2420
2421 exit:
2422         return mfilter;
2423 }
2424
2425 static int
2426 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2427                         enum rte_filter_op filter_op,
2428                         void *arg)
2429 {
2430         struct bnxt *bp = dev->data->dev_private;
2431         struct rte_eth_ethertype_filter *efilter =
2432                         (struct rte_eth_ethertype_filter *)arg;
2433         struct bnxt_filter_info *bfilter, *filter1;
2434         struct bnxt_vnic_info *vnic, *vnic0;
2435         int ret;
2436
2437         if (filter_op == RTE_ETH_FILTER_NOP)
2438                 return 0;
2439
2440         if (arg == NULL) {
2441                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2442                             filter_op);
2443                 return -EINVAL;
2444         }
2445
2446         vnic0 = &bp->vnic_info[0];
2447         vnic = &bp->vnic_info[efilter->queue];
2448
2449         switch (filter_op) {
2450         case RTE_ETH_FILTER_ADD:
2451                 bnxt_match_and_validate_ether_filter(bp, efilter,
2452                                                         vnic0, vnic, &ret);
2453                 if (ret < 0)
2454                         return ret;
2455
2456                 bfilter = bnxt_get_unused_filter(bp);
2457                 if (bfilter == NULL) {
2458                         PMD_DRV_LOG(ERR,
2459                                 "Not enough resources for a new filter.\n");
2460                         return -ENOMEM;
2461                 }
2462                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2463                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2464                        RTE_ETHER_ADDR_LEN);
2465                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2466                        RTE_ETHER_ADDR_LEN);
2467                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2468                 bfilter->ethertype = efilter->ether_type;
2469                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2470
2471                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2472                 if (filter1 == NULL) {
2473                         ret = -EINVAL;
2474                         goto cleanup;
2475                 }
2476                 bfilter->enables |=
2477                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2478                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2479
2480                 bfilter->dst_id = vnic->fw_vnic_id;
2481
2482                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2483                         bfilter->flags =
2484                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2485                 }
2486
2487                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2488                 if (ret)
2489                         goto cleanup;
2490                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2491                 break;
2492         case RTE_ETH_FILTER_DELETE:
2493                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2494                                                         vnic0, vnic, &ret);
2495                 if (ret == -EEXIST) {
2496                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2497
2498                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2499                                       next);
2500                         bnxt_free_filter(bp, filter1);
2501                 } else if (ret == 0) {
2502                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2503                 }
2504                 break;
2505         default:
2506                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2507                 ret = -EINVAL;
2508                 goto error;
2509         }
2510         return ret;
2511 cleanup:
2512         bnxt_free_filter(bp, bfilter);
2513 error:
2514         return ret;
2515 }
2516
2517 static inline int
2518 parse_ntuple_filter(struct bnxt *bp,
2519                     struct rte_eth_ntuple_filter *nfilter,
2520                     struct bnxt_filter_info *bfilter)
2521 {
2522         uint32_t en = 0;
2523
2524         if (nfilter->queue >= bp->rx_nr_rings) {
2525                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2526                 return -EINVAL;
2527         }
2528
2529         switch (nfilter->dst_port_mask) {
2530         case UINT16_MAX:
2531                 bfilter->dst_port_mask = -1;
2532                 bfilter->dst_port = nfilter->dst_port;
2533                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2534                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2535                 break;
2536         default:
2537                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2538                 return -EINVAL;
2539         }
2540
2541         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2542         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2543
2544         switch (nfilter->proto_mask) {
2545         case UINT8_MAX:
2546                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2547                         bfilter->ip_protocol = 17;
2548                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2549                         bfilter->ip_protocol = 6;
2550                 else
2551                         return -EINVAL;
2552                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2553                 break;
2554         default:
2555                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2556                 return -EINVAL;
2557         }
2558
2559         switch (nfilter->dst_ip_mask) {
2560         case UINT32_MAX:
2561                 bfilter->dst_ipaddr_mask[0] = -1;
2562                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2563                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2564                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2565                 break;
2566         default:
2567                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2568                 return -EINVAL;
2569         }
2570
2571         switch (nfilter->src_ip_mask) {
2572         case UINT32_MAX:
2573                 bfilter->src_ipaddr_mask[0] = -1;
2574                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2575                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2576                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2577                 break;
2578         default:
2579                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2580                 return -EINVAL;
2581         }
2582
2583         switch (nfilter->src_port_mask) {
2584         case UINT16_MAX:
2585                 bfilter->src_port_mask = -1;
2586                 bfilter->src_port = nfilter->src_port;
2587                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2588                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2589                 break;
2590         default:
2591                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2592                 return -EINVAL;
2593         }
2594
2595         //TODO Priority
2596         //nfilter->priority = (uint8_t)filter->priority;
2597
2598         bfilter->enables = en;
2599         return 0;
2600 }
2601
2602 static struct bnxt_filter_info*
2603 bnxt_match_ntuple_filter(struct bnxt *bp,
2604                          struct bnxt_filter_info *bfilter,
2605                          struct bnxt_vnic_info **mvnic)
2606 {
2607         struct bnxt_filter_info *mfilter = NULL;
2608         int i;
2609
2610         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2611                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2612                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2613                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2614                             bfilter->src_ipaddr_mask[0] ==
2615                             mfilter->src_ipaddr_mask[0] &&
2616                             bfilter->src_port == mfilter->src_port &&
2617                             bfilter->src_port_mask == mfilter->src_port_mask &&
2618                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2619                             bfilter->dst_ipaddr_mask[0] ==
2620                             mfilter->dst_ipaddr_mask[0] &&
2621                             bfilter->dst_port == mfilter->dst_port &&
2622                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2623                             bfilter->flags == mfilter->flags &&
2624                             bfilter->enables == mfilter->enables) {
2625                                 if (mvnic)
2626                                         *mvnic = vnic;
2627                                 return mfilter;
2628                         }
2629                 }
2630         }
2631         return NULL;
2632 }
2633
2634 static int
2635 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2636                        struct rte_eth_ntuple_filter *nfilter,
2637                        enum rte_filter_op filter_op)
2638 {
2639         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2640         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2641         int ret;
2642
2643         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2644                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2645                 return -EINVAL;
2646         }
2647
2648         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2649                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2650                 return -EINVAL;
2651         }
2652
2653         bfilter = bnxt_get_unused_filter(bp);
2654         if (bfilter == NULL) {
2655                 PMD_DRV_LOG(ERR,
2656                         "Not enough resources for a new filter.\n");
2657                 return -ENOMEM;
2658         }
2659         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2660         if (ret < 0)
2661                 goto free_filter;
2662
2663         vnic = &bp->vnic_info[nfilter->queue];
2664         vnic0 = &bp->vnic_info[0];
2665         filter1 = STAILQ_FIRST(&vnic0->filter);
2666         if (filter1 == NULL) {
2667                 ret = -EINVAL;
2668                 goto free_filter;
2669         }
2670
2671         bfilter->dst_id = vnic->fw_vnic_id;
2672         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2673         bfilter->enables |=
2674                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2675         bfilter->ethertype = 0x800;
2676         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2677
2678         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2679
2680         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2681             bfilter->dst_id == mfilter->dst_id) {
2682                 PMD_DRV_LOG(ERR, "filter exists.\n");
2683                 ret = -EEXIST;
2684                 goto free_filter;
2685         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2686                    bfilter->dst_id != mfilter->dst_id) {
2687                 mfilter->dst_id = vnic->fw_vnic_id;
2688                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2689                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2690                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2691                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2692                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2693                 goto free_filter;
2694         }
2695         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2696                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2697                 ret = -ENOENT;
2698                 goto free_filter;
2699         }
2700
2701         if (filter_op == RTE_ETH_FILTER_ADD) {
2702                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2703                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2704                 if (ret)
2705                         goto free_filter;
2706                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2707         } else {
2708                 if (mfilter == NULL) {
2709                         /* This should not happen. But for Coverity! */
2710                         ret = -ENOENT;
2711                         goto free_filter;
2712                 }
2713                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2714
2715                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2716                 bnxt_free_filter(bp, mfilter);
2717                 mfilter->fw_l2_filter_id = -1;
2718                 bnxt_free_filter(bp, bfilter);
2719                 bfilter->fw_l2_filter_id = -1;
2720         }
2721
2722         return 0;
2723 free_filter:
2724         bfilter->fw_l2_filter_id = -1;
2725         bnxt_free_filter(bp, bfilter);
2726         return ret;
2727 }
2728
2729 static int
2730 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2731                         enum rte_filter_op filter_op,
2732                         void *arg)
2733 {
2734         struct bnxt *bp = dev->data->dev_private;
2735         int ret;
2736
2737         if (filter_op == RTE_ETH_FILTER_NOP)
2738                 return 0;
2739
2740         if (arg == NULL) {
2741                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2742                             filter_op);
2743                 return -EINVAL;
2744         }
2745
2746         switch (filter_op) {
2747         case RTE_ETH_FILTER_ADD:
2748                 ret = bnxt_cfg_ntuple_filter(bp,
2749                         (struct rte_eth_ntuple_filter *)arg,
2750                         filter_op);
2751                 break;
2752         case RTE_ETH_FILTER_DELETE:
2753                 ret = bnxt_cfg_ntuple_filter(bp,
2754                         (struct rte_eth_ntuple_filter *)arg,
2755                         filter_op);
2756                 break;
2757         default:
2758                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2759                 ret = -EINVAL;
2760                 break;
2761         }
2762         return ret;
2763 }
2764
2765 static int
2766 bnxt_parse_fdir_filter(struct bnxt *bp,
2767                        struct rte_eth_fdir_filter *fdir,
2768                        struct bnxt_filter_info *filter)
2769 {
2770         enum rte_fdir_mode fdir_mode =
2771                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2772         struct bnxt_vnic_info *vnic0, *vnic;
2773         struct bnxt_filter_info *filter1;
2774         uint32_t en = 0;
2775         int i;
2776
2777         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2778                 return -EINVAL;
2779
2780         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2781         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2782
2783         switch (fdir->input.flow_type) {
2784         case RTE_ETH_FLOW_IPV4:
2785         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2786                 /* FALLTHROUGH */
2787                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2788                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2789                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2790                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2791                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2792                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2793                 filter->ip_addr_type =
2794                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2795                 filter->src_ipaddr_mask[0] = 0xffffffff;
2796                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2797                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2798                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2799                 filter->ethertype = 0x800;
2800                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2801                 break;
2802         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2803                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2804                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2805                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2806                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2807                 filter->dst_port_mask = 0xffff;
2808                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2809                 filter->src_port_mask = 0xffff;
2810                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2811                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2812                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2813                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2814                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2815                 filter->ip_protocol = 6;
2816                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2817                 filter->ip_addr_type =
2818                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2819                 filter->src_ipaddr_mask[0] = 0xffffffff;
2820                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2821                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2822                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2823                 filter->ethertype = 0x800;
2824                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2825                 break;
2826         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2827                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2828                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2829                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2830                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2831                 filter->dst_port_mask = 0xffff;
2832                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2833                 filter->src_port_mask = 0xffff;
2834                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2835                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2836                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2837                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2838                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2839                 filter->ip_protocol = 17;
2840                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2841                 filter->ip_addr_type =
2842                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2843                 filter->src_ipaddr_mask[0] = 0xffffffff;
2844                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2845                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2846                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2847                 filter->ethertype = 0x800;
2848                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2849                 break;
2850         case RTE_ETH_FLOW_IPV6:
2851         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2852                 /* FALLTHROUGH */
2853                 filter->ip_addr_type =
2854                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2855                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2856                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2857                 rte_memcpy(filter->src_ipaddr,
2858                            fdir->input.flow.ipv6_flow.src_ip, 16);
2859                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2860                 rte_memcpy(filter->dst_ipaddr,
2861                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2862                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2863                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2864                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2865                 memset(filter->src_ipaddr_mask, 0xff, 16);
2866                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2867                 filter->ethertype = 0x86dd;
2868                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2869                 break;
2870         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2871                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2872                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2873                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2874                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2875                 filter->dst_port_mask = 0xffff;
2876                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2877                 filter->src_port_mask = 0xffff;
2878                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2879                 filter->ip_addr_type =
2880                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2881                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2882                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2883                 rte_memcpy(filter->src_ipaddr,
2884                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2885                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2886                 rte_memcpy(filter->dst_ipaddr,
2887                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2888                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2889                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2890                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2891                 memset(filter->src_ipaddr_mask, 0xff, 16);
2892                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2893                 filter->ethertype = 0x86dd;
2894                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2895                 break;
2896         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2897                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2898                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2899                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2900                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2901                 filter->dst_port_mask = 0xffff;
2902                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2903                 filter->src_port_mask = 0xffff;
2904                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2905                 filter->ip_addr_type =
2906                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2907                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2908                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2909                 rte_memcpy(filter->src_ipaddr,
2910                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2911                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2912                 rte_memcpy(filter->dst_ipaddr,
2913                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2914                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2915                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2916                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2917                 memset(filter->src_ipaddr_mask, 0xff, 16);
2918                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2919                 filter->ethertype = 0x86dd;
2920                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2921                 break;
2922         case RTE_ETH_FLOW_L2_PAYLOAD:
2923                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2924                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2925                 break;
2926         case RTE_ETH_FLOW_VXLAN:
2927                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2928                         return -EINVAL;
2929                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2930                 filter->tunnel_type =
2931                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2932                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2933                 break;
2934         case RTE_ETH_FLOW_NVGRE:
2935                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2936                         return -EINVAL;
2937                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2938                 filter->tunnel_type =
2939                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2940                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2941                 break;
2942         case RTE_ETH_FLOW_UNKNOWN:
2943         case RTE_ETH_FLOW_RAW:
2944         case RTE_ETH_FLOW_FRAG_IPV4:
2945         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2946         case RTE_ETH_FLOW_FRAG_IPV6:
2947         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2948         case RTE_ETH_FLOW_IPV6_EX:
2949         case RTE_ETH_FLOW_IPV6_TCP_EX:
2950         case RTE_ETH_FLOW_IPV6_UDP_EX:
2951         case RTE_ETH_FLOW_GENEVE:
2952                 /* FALLTHROUGH */
2953         default:
2954                 return -EINVAL;
2955         }
2956
2957         vnic0 = &bp->vnic_info[0];
2958         vnic = &bp->vnic_info[fdir->action.rx_queue];
2959         if (vnic == NULL) {
2960                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2961                 return -EINVAL;
2962         }
2963
2964         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2965                 rte_memcpy(filter->dst_macaddr,
2966                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2967                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2968         }
2969
2970         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2971                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2972                 filter1 = STAILQ_FIRST(&vnic0->filter);
2973                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2974         } else {
2975                 filter->dst_id = vnic->fw_vnic_id;
2976                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2977                         if (filter->dst_macaddr[i] == 0x00)
2978                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2979                         else
2980                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2981         }
2982
2983         if (filter1 == NULL)
2984                 return -EINVAL;
2985
2986         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2987         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2988
2989         filter->enables = en;
2990
2991         return 0;
2992 }
2993
2994 static struct bnxt_filter_info *
2995 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2996                 struct bnxt_vnic_info **mvnic)
2997 {
2998         struct bnxt_filter_info *mf = NULL;
2999         int i;
3000
3001         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3002                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3003
3004                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3005                         if (mf->filter_type == nf->filter_type &&
3006                             mf->flags == nf->flags &&
3007                             mf->src_port == nf->src_port &&
3008                             mf->src_port_mask == nf->src_port_mask &&
3009                             mf->dst_port == nf->dst_port &&
3010                             mf->dst_port_mask == nf->dst_port_mask &&
3011                             mf->ip_protocol == nf->ip_protocol &&
3012                             mf->ip_addr_type == nf->ip_addr_type &&
3013                             mf->ethertype == nf->ethertype &&
3014                             mf->vni == nf->vni &&
3015                             mf->tunnel_type == nf->tunnel_type &&
3016                             mf->l2_ovlan == nf->l2_ovlan &&
3017                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3018                             mf->l2_ivlan == nf->l2_ivlan &&
3019                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3020                             !memcmp(mf->l2_addr, nf->l2_addr,
3021                                     RTE_ETHER_ADDR_LEN) &&
3022                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3023                                     RTE_ETHER_ADDR_LEN) &&
3024                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3025                                     RTE_ETHER_ADDR_LEN) &&
3026                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3027                                     RTE_ETHER_ADDR_LEN) &&
3028                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3029                                     sizeof(nf->src_ipaddr)) &&
3030                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3031                                     sizeof(nf->src_ipaddr_mask)) &&
3032                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3033                                     sizeof(nf->dst_ipaddr)) &&
3034                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3035                                     sizeof(nf->dst_ipaddr_mask))) {
3036                                 if (mvnic)
3037                                         *mvnic = vnic;
3038                                 return mf;
3039                         }
3040                 }
3041         }
3042         return NULL;
3043 }
3044
3045 static int
3046 bnxt_fdir_filter(struct rte_eth_dev *dev,
3047                  enum rte_filter_op filter_op,
3048                  void *arg)
3049 {
3050         struct bnxt *bp = dev->data->dev_private;
3051         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3052         struct bnxt_filter_info *filter, *match;
3053         struct bnxt_vnic_info *vnic, *mvnic;
3054         int ret = 0, i;
3055
3056         if (filter_op == RTE_ETH_FILTER_NOP)
3057                 return 0;
3058
3059         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3060                 return -EINVAL;
3061
3062         switch (filter_op) {
3063         case RTE_ETH_FILTER_ADD:
3064         case RTE_ETH_FILTER_DELETE:
3065                 /* FALLTHROUGH */
3066                 filter = bnxt_get_unused_filter(bp);
3067                 if (filter == NULL) {
3068                         PMD_DRV_LOG(ERR,
3069                                 "Not enough resources for a new flow.\n");
3070                         return -ENOMEM;
3071                 }
3072
3073                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3074                 if (ret != 0)
3075                         goto free_filter;
3076                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3077
3078                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3079                         vnic = &bp->vnic_info[0];
3080                 else
3081                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3082
3083                 match = bnxt_match_fdir(bp, filter, &mvnic);
3084                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3085                         if (match->dst_id == vnic->fw_vnic_id) {
3086                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3087                                 ret = -EEXIST;
3088                                 goto free_filter;
3089                         } else {
3090                                 match->dst_id = vnic->fw_vnic_id;
3091                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3092                                                                   match->dst_id,
3093                                                                   match);
3094                                 STAILQ_REMOVE(&mvnic->filter, match,
3095                                               bnxt_filter_info, next);
3096                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3097                                 PMD_DRV_LOG(ERR,
3098                                         "Filter with matching pattern exist\n");
3099                                 PMD_DRV_LOG(ERR,
3100                                         "Updated it to new destination q\n");
3101                                 goto free_filter;
3102                         }
3103                 }
3104                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3105                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3106                         ret = -ENOENT;
3107                         goto free_filter;
3108                 }
3109
3110                 if (filter_op == RTE_ETH_FILTER_ADD) {
3111                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3112                                                           filter->dst_id,
3113                                                           filter);
3114                         if (ret)
3115                                 goto free_filter;
3116                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3117                 } else {
3118                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3119                         STAILQ_REMOVE(&vnic->filter, match,
3120                                       bnxt_filter_info, next);
3121                         bnxt_free_filter(bp, match);
3122                         filter->fw_l2_filter_id = -1;
3123                         bnxt_free_filter(bp, filter);
3124                 }
3125                 break;
3126         case RTE_ETH_FILTER_FLUSH:
3127                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3128                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3129
3130                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3131                                 if (filter->filter_type ==
3132                                     HWRM_CFA_NTUPLE_FILTER) {
3133                                         ret =
3134                                         bnxt_hwrm_clear_ntuple_filter(bp,
3135                                                                       filter);
3136                                         STAILQ_REMOVE(&vnic->filter, filter,
3137                                                       bnxt_filter_info, next);
3138                                 }
3139                         }
3140                 }
3141                 return ret;
3142         case RTE_ETH_FILTER_UPDATE:
3143         case RTE_ETH_FILTER_STATS:
3144         case RTE_ETH_FILTER_INFO:
3145                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3146                 break;
3147         default:
3148                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3149                 ret = -EINVAL;
3150                 break;
3151         }
3152         return ret;
3153
3154 free_filter:
3155         filter->fw_l2_filter_id = -1;
3156         bnxt_free_filter(bp, filter);
3157         return ret;
3158 }
3159
3160 static int
3161 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3162                     enum rte_filter_type filter_type,
3163                     enum rte_filter_op filter_op, void *arg)
3164 {
3165         int ret = 0;
3166
3167         ret = is_bnxt_in_error(dev->data->dev_private);
3168         if (ret)
3169                 return ret;
3170
3171         switch (filter_type) {
3172         case RTE_ETH_FILTER_TUNNEL:
3173                 PMD_DRV_LOG(ERR,
3174                         "filter type: %d: To be implemented\n", filter_type);
3175                 break;
3176         case RTE_ETH_FILTER_FDIR:
3177                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3178                 break;
3179         case RTE_ETH_FILTER_NTUPLE:
3180                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3181                 break;
3182         case RTE_ETH_FILTER_ETHERTYPE:
3183                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3184                 break;
3185         case RTE_ETH_FILTER_GENERIC:
3186                 if (filter_op != RTE_ETH_FILTER_GET)
3187                         return -EINVAL;
3188                 *(const void **)arg = &bnxt_flow_ops;
3189                 break;
3190         default:
3191                 PMD_DRV_LOG(ERR,
3192                         "Filter type (%d) not supported", filter_type);
3193                 ret = -EINVAL;
3194                 break;
3195         }
3196         return ret;
3197 }
3198
3199 static const uint32_t *
3200 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3201 {
3202         static const uint32_t ptypes[] = {
3203                 RTE_PTYPE_L2_ETHER_VLAN,
3204                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3205                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3206                 RTE_PTYPE_L4_ICMP,
3207                 RTE_PTYPE_L4_TCP,
3208                 RTE_PTYPE_L4_UDP,
3209                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3210                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3211                 RTE_PTYPE_INNER_L4_ICMP,
3212                 RTE_PTYPE_INNER_L4_TCP,
3213                 RTE_PTYPE_INNER_L4_UDP,
3214                 RTE_PTYPE_UNKNOWN
3215         };
3216
3217         if (!dev->rx_pkt_burst)
3218                 return NULL;
3219
3220         return ptypes;
3221 }
3222
3223 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3224                          int reg_win)
3225 {
3226         uint32_t reg_base = *reg_arr & 0xfffff000;
3227         uint32_t win_off;
3228         int i;
3229
3230         for (i = 0; i < count; i++) {
3231                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3232                         return -ERANGE;
3233         }
3234         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3235         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3236         return 0;
3237 }
3238
3239 static int bnxt_map_ptp_regs(struct bnxt *bp)
3240 {
3241         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3242         uint32_t *reg_arr;
3243         int rc, i;
3244
3245         reg_arr = ptp->rx_regs;
3246         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3247         if (rc)
3248                 return rc;
3249
3250         reg_arr = ptp->tx_regs;
3251         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3252         if (rc)
3253                 return rc;
3254
3255         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3256                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3257
3258         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3259                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3260
3261         return 0;
3262 }
3263
3264 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3265 {
3266         rte_write32(0, (uint8_t *)bp->bar0 +
3267                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3268         rte_write32(0, (uint8_t *)bp->bar0 +
3269                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3270 }
3271
3272 static uint64_t bnxt_cc_read(struct bnxt *bp)
3273 {
3274         uint64_t ns;
3275
3276         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3277                               BNXT_GRCPF_REG_SYNC_TIME));
3278         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3279                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3280         return ns;
3281 }
3282
3283 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3284 {
3285         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3286         uint32_t fifo;
3287
3288         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3289                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3290         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3291                 return -EAGAIN;
3292
3293         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3294                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3295         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3296                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3297         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3298                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3299
3300         return 0;
3301 }
3302
3303 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3304 {
3305         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3306         struct bnxt_pf_info *pf = &bp->pf;
3307         uint16_t port_id;
3308         uint32_t fifo;
3309
3310         if (!ptp)
3311                 return -ENODEV;
3312
3313         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3314                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3315         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3316                 return -EAGAIN;
3317
3318         port_id = pf->port_id;
3319         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3320                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3321
3322         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3323                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3324         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3325 /*              bnxt_clr_rx_ts(bp);       TBD  */
3326                 return -EBUSY;
3327         }
3328
3329         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3330                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3331         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3332                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3333
3334         return 0;
3335 }
3336
3337 static int
3338 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3339 {
3340         uint64_t ns;
3341         struct bnxt *bp = dev->data->dev_private;
3342         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3343
3344         if (!ptp)
3345                 return 0;
3346
3347         ns = rte_timespec_to_ns(ts);
3348         /* Set the timecounters to a new value. */
3349         ptp->tc.nsec = ns;
3350
3351         return 0;
3352 }
3353
3354 static int
3355 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3356 {
3357         struct bnxt *bp = dev->data->dev_private;
3358         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3359         uint64_t ns, systime_cycles = 0;
3360         int rc = 0;
3361
3362         if (!ptp)
3363                 return 0;
3364
3365         if (BNXT_CHIP_THOR(bp))
3366                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3367                                              &systime_cycles);
3368         else
3369                 systime_cycles = bnxt_cc_read(bp);
3370
3371         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3372         *ts = rte_ns_to_timespec(ns);
3373
3374         return rc;
3375 }
3376 static int
3377 bnxt_timesync_enable(struct rte_eth_dev *dev)
3378 {
3379         struct bnxt *bp = dev->data->dev_private;
3380         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3381         uint32_t shift = 0;
3382         int rc;
3383
3384         if (!ptp)
3385                 return 0;
3386
3387         ptp->rx_filter = 1;
3388         ptp->tx_tstamp_en = 1;
3389         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3390
3391         rc = bnxt_hwrm_ptp_cfg(bp);
3392         if (rc)
3393                 return rc;
3394
3395         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3396         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3397         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3398
3399         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3400         ptp->tc.cc_shift = shift;
3401         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3402
3403         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3404         ptp->rx_tstamp_tc.cc_shift = shift;
3405         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3406
3407         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3408         ptp->tx_tstamp_tc.cc_shift = shift;
3409         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3410
3411         if (!BNXT_CHIP_THOR(bp))
3412                 bnxt_map_ptp_regs(bp);
3413
3414         return 0;
3415 }
3416
3417 static int
3418 bnxt_timesync_disable(struct rte_eth_dev *dev)
3419 {
3420         struct bnxt *bp = dev->data->dev_private;
3421         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3422
3423         if (!ptp)
3424                 return 0;
3425
3426         ptp->rx_filter = 0;
3427         ptp->tx_tstamp_en = 0;
3428         ptp->rxctl = 0;
3429
3430         bnxt_hwrm_ptp_cfg(bp);
3431
3432         if (!BNXT_CHIP_THOR(bp))
3433                 bnxt_unmap_ptp_regs(bp);
3434
3435         return 0;
3436 }
3437
3438 static int
3439 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3440                                  struct timespec *timestamp,
3441                                  uint32_t flags __rte_unused)
3442 {
3443         struct bnxt *bp = dev->data->dev_private;
3444         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3445         uint64_t rx_tstamp_cycles = 0;
3446         uint64_t ns;
3447
3448         if (!ptp)
3449                 return 0;
3450
3451         if (BNXT_CHIP_THOR(bp))
3452                 rx_tstamp_cycles = ptp->rx_timestamp;
3453         else
3454                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3455
3456         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3457         *timestamp = rte_ns_to_timespec(ns);
3458         return  0;
3459 }
3460
3461 static int
3462 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3463                                  struct timespec *timestamp)
3464 {
3465         struct bnxt *bp = dev->data->dev_private;
3466         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3467         uint64_t tx_tstamp_cycles = 0;
3468         uint64_t ns;
3469         int rc = 0;
3470
3471         if (!ptp)
3472                 return 0;
3473
3474         if (BNXT_CHIP_THOR(bp))
3475                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3476                                              &tx_tstamp_cycles);
3477         else
3478                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3479
3480         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3481         *timestamp = rte_ns_to_timespec(ns);
3482
3483         return rc;
3484 }
3485
3486 static int
3487 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3488 {
3489         struct bnxt *bp = dev->data->dev_private;
3490         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3491
3492         if (!ptp)
3493                 return 0;
3494
3495         ptp->tc.nsec += delta;
3496
3497         return 0;
3498 }
3499
3500 static int
3501 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3502 {
3503         struct bnxt *bp = dev->data->dev_private;
3504         int rc;
3505         uint32_t dir_entries;
3506         uint32_t entry_length;
3507
3508         rc = is_bnxt_in_error(bp);
3509         if (rc)
3510                 return rc;
3511
3512         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3513                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3514                 bp->pdev->addr.devid, bp->pdev->addr.function);
3515
3516         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3517         if (rc != 0)
3518                 return rc;
3519
3520         return dir_entries * entry_length;
3521 }
3522
3523 static int
3524 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3525                 struct rte_dev_eeprom_info *in_eeprom)
3526 {
3527         struct bnxt *bp = dev->data->dev_private;
3528         uint32_t index;
3529         uint32_t offset;
3530         int rc;
3531
3532         rc = is_bnxt_in_error(bp);
3533         if (rc)
3534                 return rc;
3535
3536         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3537                 "len = %d\n", bp->pdev->addr.domain,
3538                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3539                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3540
3541         if (in_eeprom->offset == 0) /* special offset value to get directory */
3542                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3543                                                 in_eeprom->data);
3544
3545         index = in_eeprom->offset >> 24;
3546         offset = in_eeprom->offset & 0xffffff;
3547
3548         if (index != 0)
3549                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3550                                            in_eeprom->length, in_eeprom->data);
3551
3552         return 0;
3553 }
3554
3555 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3556 {
3557         switch (dir_type) {
3558         case BNX_DIR_TYPE_CHIMP_PATCH:
3559         case BNX_DIR_TYPE_BOOTCODE:
3560         case BNX_DIR_TYPE_BOOTCODE_2:
3561         case BNX_DIR_TYPE_APE_FW:
3562         case BNX_DIR_TYPE_APE_PATCH:
3563         case BNX_DIR_TYPE_KONG_FW:
3564         case BNX_DIR_TYPE_KONG_PATCH:
3565         case BNX_DIR_TYPE_BONO_FW:
3566         case BNX_DIR_TYPE_BONO_PATCH:
3567                 /* FALLTHROUGH */
3568                 return true;
3569         }
3570
3571         return false;
3572 }
3573
3574 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3575 {
3576         switch (dir_type) {
3577         case BNX_DIR_TYPE_AVS:
3578         case BNX_DIR_TYPE_EXP_ROM_MBA:
3579         case BNX_DIR_TYPE_PCIE:
3580         case BNX_DIR_TYPE_TSCF_UCODE:
3581         case BNX_DIR_TYPE_EXT_PHY:
3582         case BNX_DIR_TYPE_CCM:
3583         case BNX_DIR_TYPE_ISCSI_BOOT:
3584         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3585         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3586                 /* FALLTHROUGH */
3587                 return true;
3588         }
3589
3590         return false;
3591 }
3592
3593 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3594 {
3595         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3596                 bnxt_dir_type_is_other_exec_format(dir_type);
3597 }
3598
3599 static int
3600 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3601                 struct rte_dev_eeprom_info *in_eeprom)
3602 {
3603         struct bnxt *bp = dev->data->dev_private;
3604         uint8_t index, dir_op;
3605         uint16_t type, ext, ordinal, attr;
3606         int rc;
3607
3608         rc = is_bnxt_in_error(bp);
3609         if (rc)
3610                 return rc;
3611
3612         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3613                 "len = %d\n", bp->pdev->addr.domain,
3614                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3615                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3616
3617         if (!BNXT_PF(bp)) {
3618                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3619                 return -EINVAL;
3620         }
3621
3622         type = in_eeprom->magic >> 16;
3623
3624         if (type == 0xffff) { /* special value for directory operations */
3625                 index = in_eeprom->magic & 0xff;
3626                 dir_op = in_eeprom->magic >> 8;
3627                 if (index == 0)
3628                         return -EINVAL;
3629                 switch (dir_op) {
3630                 case 0x0e: /* erase */
3631                         if (in_eeprom->offset != ~in_eeprom->magic)
3632                                 return -EINVAL;
3633                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3634                 default:
3635                         return -EINVAL;
3636                 }
3637         }
3638
3639         /* Create or re-write an NVM item: */
3640         if (bnxt_dir_type_is_executable(type) == true)
3641                 return -EOPNOTSUPP;
3642         ext = in_eeprom->magic & 0xffff;
3643         ordinal = in_eeprom->offset >> 16;
3644         attr = in_eeprom->offset & 0xffff;
3645
3646         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3647                                      in_eeprom->data, in_eeprom->length);
3648 }
3649
3650 /*
3651  * Initialization
3652  */
3653
3654 static const struct eth_dev_ops bnxt_dev_ops = {
3655         .dev_infos_get = bnxt_dev_info_get_op,
3656         .dev_close = bnxt_dev_close_op,
3657         .dev_configure = bnxt_dev_configure_op,
3658         .dev_start = bnxt_dev_start_op,
3659         .dev_stop = bnxt_dev_stop_op,
3660         .dev_set_link_up = bnxt_dev_set_link_up_op,
3661         .dev_set_link_down = bnxt_dev_set_link_down_op,
3662         .stats_get = bnxt_stats_get_op,
3663         .stats_reset = bnxt_stats_reset_op,
3664         .rx_queue_setup = bnxt_rx_queue_setup_op,
3665         .rx_queue_release = bnxt_rx_queue_release_op,
3666         .tx_queue_setup = bnxt_tx_queue_setup_op,
3667         .tx_queue_release = bnxt_tx_queue_release_op,
3668         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3669         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3670         .reta_update = bnxt_reta_update_op,
3671         .reta_query = bnxt_reta_query_op,
3672         .rss_hash_update = bnxt_rss_hash_update_op,
3673         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3674         .link_update = bnxt_link_update_op,
3675         .promiscuous_enable = bnxt_promiscuous_enable_op,
3676         .promiscuous_disable = bnxt_promiscuous_disable_op,
3677         .allmulticast_enable = bnxt_allmulticast_enable_op,
3678         .allmulticast_disable = bnxt_allmulticast_disable_op,
3679         .mac_addr_add = bnxt_mac_addr_add_op,
3680         .mac_addr_remove = bnxt_mac_addr_remove_op,
3681         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3682         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3683         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3684         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3685         .vlan_filter_set = bnxt_vlan_filter_set_op,
3686         .vlan_offload_set = bnxt_vlan_offload_set_op,
3687         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3688         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3689         .mtu_set = bnxt_mtu_set_op,
3690         .mac_addr_set = bnxt_set_default_mac_addr_op,
3691         .xstats_get = bnxt_dev_xstats_get_op,
3692         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3693         .xstats_reset = bnxt_dev_xstats_reset_op,
3694         .fw_version_get = bnxt_fw_version_get,
3695         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3696         .rxq_info_get = bnxt_rxq_info_get_op,
3697         .txq_info_get = bnxt_txq_info_get_op,
3698         .dev_led_on = bnxt_dev_led_on_op,
3699         .dev_led_off = bnxt_dev_led_off_op,
3700         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3701         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3702         .rx_queue_count = bnxt_rx_queue_count_op,
3703         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3704         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3705         .rx_queue_start = bnxt_rx_queue_start,
3706         .rx_queue_stop = bnxt_rx_queue_stop,
3707         .tx_queue_start = bnxt_tx_queue_start,
3708         .tx_queue_stop = bnxt_tx_queue_stop,
3709         .filter_ctrl = bnxt_filter_ctrl_op,
3710         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3711         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3712         .get_eeprom           = bnxt_get_eeprom_op,
3713         .set_eeprom           = bnxt_set_eeprom_op,
3714         .timesync_enable      = bnxt_timesync_enable,
3715         .timesync_disable     = bnxt_timesync_disable,
3716         .timesync_read_time   = bnxt_timesync_read_time,
3717         .timesync_write_time   = bnxt_timesync_write_time,
3718         .timesync_adjust_time = bnxt_timesync_adjust_time,
3719         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3720         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3721 };
3722
3723 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3724 {
3725         uint32_t offset;
3726
3727         /* Only pre-map the reset GRC registers using window 3 */
3728         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3729                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3730
3731         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3732
3733         return offset;
3734 }
3735
3736 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3737 {
3738         struct bnxt_error_recovery_info *info = bp->recovery_info;
3739         uint32_t reg_base = 0xffffffff;
3740         int i;
3741
3742         /* Only pre-map the monitoring GRC registers using window 2 */
3743         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3744                 uint32_t reg = info->status_regs[i];
3745
3746                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3747                         continue;
3748
3749                 if (reg_base == 0xffffffff)
3750                         reg_base = reg & 0xfffff000;
3751                 if ((reg & 0xfffff000) != reg_base)
3752                         return -ERANGE;
3753
3754                 /* Use mask 0xffc as the Lower 2 bits indicates
3755                  * address space location
3756                  */
3757                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3758                                                 (reg & 0xffc);
3759         }
3760
3761         if (reg_base == 0xffffffff)
3762                 return 0;
3763
3764         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3765                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3766
3767         return 0;
3768 }
3769
3770 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3771 {
3772         struct bnxt_error_recovery_info *info = bp->recovery_info;
3773         uint32_t delay = info->delay_after_reset[index];
3774         uint32_t val = info->reset_reg_val[index];
3775         uint32_t reg = info->reset_reg[index];
3776         uint32_t type, offset;
3777
3778         type = BNXT_FW_STATUS_REG_TYPE(reg);
3779         offset = BNXT_FW_STATUS_REG_OFF(reg);
3780
3781         switch (type) {
3782         case BNXT_FW_STATUS_REG_TYPE_CFG:
3783                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3784                 break;
3785         case BNXT_FW_STATUS_REG_TYPE_GRC:
3786                 offset = bnxt_map_reset_regs(bp, offset);
3787                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3788                 break;
3789         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3790                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3791                 break;
3792         }
3793         /* wait on a specific interval of time until core reset is complete */
3794         if (delay)
3795                 rte_delay_ms(delay);
3796 }
3797
3798 static void bnxt_dev_cleanup(struct bnxt *bp)
3799 {
3800         bnxt_set_hwrm_link_config(bp, false);
3801         bp->link_info.link_up = 0;
3802         if (bp->dev_stopped == 0)
3803                 bnxt_dev_stop_op(bp->eth_dev);
3804
3805         bnxt_uninit_resources(bp, true);
3806 }
3807
3808 static int bnxt_restore_filters(struct bnxt *bp)
3809 {
3810         struct rte_eth_dev *dev = bp->eth_dev;
3811         int ret = 0;
3812
3813         if (dev->data->all_multicast)
3814                 ret = bnxt_allmulticast_enable_op(dev);
3815         if (dev->data->promiscuous)
3816                 ret = bnxt_promiscuous_enable_op(dev);
3817
3818         /* TODO restore other filters as well */
3819         return ret;
3820 }
3821
3822 static void bnxt_dev_recover(void *arg)
3823 {
3824         struct bnxt *bp = arg;
3825         int timeout = bp->fw_reset_max_msecs;
3826         int rc = 0;
3827
3828         /* Clear Error flag so that device re-init should happen */
3829         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3830
3831         do {
3832                 rc = bnxt_hwrm_ver_get(bp);
3833                 if (rc == 0)
3834                         break;
3835                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3836                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3837         } while (rc && timeout);
3838
3839         if (rc) {
3840                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3841                 goto err;
3842         }
3843
3844         rc = bnxt_init_resources(bp, true);
3845         if (rc) {
3846                 PMD_DRV_LOG(ERR,
3847                             "Failed to initialize resources after reset\n");
3848                 goto err;
3849         }
3850         /* clear reset flag as the device is initialized now */
3851         bp->flags &= ~BNXT_FLAG_FW_RESET;
3852
3853         rc = bnxt_dev_start_op(bp->eth_dev);
3854         if (rc) {
3855                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3856                 goto err;
3857         }
3858
3859         rc = bnxt_restore_filters(bp);
3860         if (rc)
3861                 goto err;
3862
3863         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3864         return;
3865 err:
3866         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3867         bnxt_uninit_resources(bp, false);
3868         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3869 }
3870
3871 void bnxt_dev_reset_and_resume(void *arg)
3872 {
3873         struct bnxt *bp = arg;
3874         int rc;
3875
3876         bnxt_dev_cleanup(bp);
3877
3878         bnxt_wait_for_device_shutdown(bp);
3879
3880         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3881                                bnxt_dev_recover, (void *)bp);
3882         if (rc)
3883                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3884 }
3885
3886 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3887 {
3888         struct bnxt_error_recovery_info *info = bp->recovery_info;
3889         uint32_t reg = info->status_regs[index];
3890         uint32_t type, offset, val = 0;
3891
3892         type = BNXT_FW_STATUS_REG_TYPE(reg);
3893         offset = BNXT_FW_STATUS_REG_OFF(reg);
3894
3895         switch (type) {
3896         case BNXT_FW_STATUS_REG_TYPE_CFG:
3897                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3898                 break;
3899         case BNXT_FW_STATUS_REG_TYPE_GRC:
3900                 offset = info->mapped_status_regs[index];
3901                 /* FALLTHROUGH */
3902         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3903                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3904                                        offset));
3905                 break;
3906         }
3907
3908         return val;
3909 }
3910
3911 static int bnxt_fw_reset_all(struct bnxt *bp)
3912 {
3913         struct bnxt_error_recovery_info *info = bp->recovery_info;
3914         uint32_t i;
3915         int rc = 0;
3916
3917         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3918                 /* Reset through master function driver */
3919                 for (i = 0; i < info->reg_array_cnt; i++)
3920                         bnxt_write_fw_reset_reg(bp, i);
3921                 /* Wait for time specified by FW after triggering reset */
3922                 rte_delay_ms(info->master_func_wait_period_after_reset);
3923         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3924                 /* Reset with the help of Kong processor */
3925                 rc = bnxt_hwrm_fw_reset(bp);
3926                 if (rc)
3927                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3928         }
3929
3930         return rc;
3931 }
3932
3933 static void bnxt_fw_reset_cb(void *arg)
3934 {
3935         struct bnxt *bp = arg;
3936         struct bnxt_error_recovery_info *info = bp->recovery_info;
3937         int rc = 0;
3938
3939         /* Only Master function can do FW reset */
3940         if (bnxt_is_master_func(bp) &&
3941             bnxt_is_recovery_enabled(bp)) {
3942                 rc = bnxt_fw_reset_all(bp);
3943                 if (rc) {
3944                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3945                         return;
3946                 }
3947         }
3948
3949         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3950          * EXCEPTION_FATAL_ASYNC event to all the functions
3951          * (including MASTER FUNC). After receiving this Async, all the active
3952          * drivers should treat this case as FW initiated recovery
3953          */
3954         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3955                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3956                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3957
3958                 /* To recover from error */
3959                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3960                                   (void *)bp);
3961         }
3962 }
3963
3964 /* Driver should poll FW heartbeat, reset_counter with the frequency
3965  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3966  * When the driver detects heartbeat stop or change in reset_counter,
3967  * it has to trigger a reset to recover from the error condition.
3968  * A “master PF” is the function who will have the privilege to
3969  * initiate the chimp reset. The master PF will be elected by the
3970  * firmware and will be notified through async message.
3971  */
3972 static void bnxt_check_fw_health(void *arg)
3973 {
3974         struct bnxt *bp = arg;
3975         struct bnxt_error_recovery_info *info = bp->recovery_info;
3976         uint32_t val = 0, wait_msec;
3977
3978         if (!info || !bnxt_is_recovery_enabled(bp) ||
3979             is_bnxt_in_error(bp))
3980                 return;
3981
3982         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3983         if (val == info->last_heart_beat)
3984                 goto reset;
3985
3986         info->last_heart_beat = val;
3987
3988         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3989         if (val != info->last_reset_counter)
3990                 goto reset;
3991
3992         info->last_reset_counter = val;
3993
3994         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3995                           bnxt_check_fw_health, (void *)bp);
3996
3997         return;
3998 reset:
3999         /* Stop DMA to/from device */
4000         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4001         bp->flags |= BNXT_FLAG_FW_RESET;
4002
4003         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4004
4005         if (bnxt_is_master_func(bp))
4006                 wait_msec = info->master_func_wait_period;
4007         else
4008                 wait_msec = info->normal_func_wait_period;
4009
4010         rte_eal_alarm_set(US_PER_MS * wait_msec,
4011                           bnxt_fw_reset_cb, (void *)bp);
4012 }
4013
4014 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4015 {
4016         uint32_t polling_freq;
4017
4018         if (!bnxt_is_recovery_enabled(bp))
4019                 return;
4020
4021         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4022                 return;
4023
4024         polling_freq = bp->recovery_info->driver_polling_freq;
4025
4026         rte_eal_alarm_set(US_PER_MS * polling_freq,
4027                           bnxt_check_fw_health, (void *)bp);
4028         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4029 }
4030
4031 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4032 {
4033         if (!bnxt_is_recovery_enabled(bp))
4034                 return;
4035
4036         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4037         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4038 }
4039
4040 static bool bnxt_vf_pciid(uint16_t id)
4041 {
4042         if (id == BROADCOM_DEV_ID_57304_VF ||
4043             id == BROADCOM_DEV_ID_57406_VF ||
4044             id == BROADCOM_DEV_ID_5731X_VF ||
4045             id == BROADCOM_DEV_ID_5741X_VF ||
4046             id == BROADCOM_DEV_ID_57414_VF ||
4047             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4048             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
4049             id == BROADCOM_DEV_ID_58802_VF ||
4050             id == BROADCOM_DEV_ID_57500_VF1 ||
4051             id == BROADCOM_DEV_ID_57500_VF2)
4052                 return true;
4053         return false;
4054 }
4055
4056 bool bnxt_stratus_device(struct bnxt *bp)
4057 {
4058         uint16_t id = bp->pdev->id.device_id;
4059
4060         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
4061             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4062             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
4063                 return true;
4064         return false;
4065 }
4066
4067 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4068 {
4069         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4070         struct bnxt *bp = eth_dev->data->dev_private;
4071
4072         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4073         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4074         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4075         if (!bp->bar0 || !bp->doorbell_base) {
4076                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4077                 return -ENODEV;
4078         }
4079
4080         bp->eth_dev = eth_dev;
4081         bp->pdev = pci_dev;
4082
4083         return 0;
4084 }
4085
4086 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
4087                                   struct bnxt_ctx_pg_info *ctx_pg,
4088                                   uint32_t mem_size,
4089                                   const char *suffix,
4090                                   uint16_t idx)
4091 {
4092         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4093         const struct rte_memzone *mz = NULL;
4094         char mz_name[RTE_MEMZONE_NAMESIZE];
4095         rte_iova_t mz_phys_addr;
4096         uint64_t valid_bits = 0;
4097         uint32_t sz;
4098         int i;
4099
4100         if (!mem_size)
4101                 return 0;
4102
4103         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4104                          BNXT_PAGE_SIZE;
4105         rmem->page_size = BNXT_PAGE_SIZE;
4106         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4107         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4108         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4109
4110         valid_bits = PTU_PTE_VALID;
4111
4112         if (rmem->nr_pages > 1) {
4113                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4114                          "bnxt_ctx_pg_tbl%s_%x_%d",
4115                          suffix, idx, bp->eth_dev->data->port_id);
4116                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4117                 mz = rte_memzone_lookup(mz_name);
4118                 if (!mz) {
4119                         mz = rte_memzone_reserve_aligned(mz_name,
4120                                                 rmem->nr_pages * 8,
4121                                                 SOCKET_ID_ANY,
4122                                                 RTE_MEMZONE_2MB |
4123                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4124                                                 RTE_MEMZONE_IOVA_CONTIG,
4125                                                 BNXT_PAGE_SIZE);
4126                         if (mz == NULL)
4127                                 return -ENOMEM;
4128                 }
4129
4130                 memset(mz->addr, 0, mz->len);
4131                 mz_phys_addr = mz->iova;
4132                 if ((unsigned long)mz->addr == mz_phys_addr) {
4133                         PMD_DRV_LOG(DEBUG,
4134                                     "physical address same as virtual\n");
4135                         PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4136                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
4137                         if (mz_phys_addr == RTE_BAD_IOVA) {
4138                                 PMD_DRV_LOG(ERR,
4139                                         "unable to map addr to phys memory\n");
4140                                 return -ENOMEM;
4141                         }
4142                 }
4143                 rte_mem_lock_page(((char *)mz->addr));
4144
4145                 rmem->pg_tbl = mz->addr;
4146                 rmem->pg_tbl_map = mz_phys_addr;
4147                 rmem->pg_tbl_mz = mz;
4148         }
4149
4150         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4151                  suffix, idx, bp->eth_dev->data->port_id);
4152         mz = rte_memzone_lookup(mz_name);
4153         if (!mz) {
4154                 mz = rte_memzone_reserve_aligned(mz_name,
4155                                                  mem_size,
4156                                                  SOCKET_ID_ANY,
4157                                                  RTE_MEMZONE_1GB |
4158                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4159                                                  RTE_MEMZONE_IOVA_CONTIG,
4160                                                  BNXT_PAGE_SIZE);
4161                 if (mz == NULL)
4162                         return -ENOMEM;
4163         }
4164
4165         memset(mz->addr, 0, mz->len);
4166         mz_phys_addr = mz->iova;
4167         if ((unsigned long)mz->addr == mz_phys_addr) {
4168                 PMD_DRV_LOG(DEBUG,
4169                             "Memzone physical address same as virtual.\n");
4170                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4171                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4172                         rte_mem_lock_page(((char *)mz->addr) + sz);
4173                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4174                 if (mz_phys_addr == RTE_BAD_IOVA) {
4175                         PMD_DRV_LOG(ERR,
4176                                     "unable to map addr to phys memory\n");
4177                         return -ENOMEM;
4178                 }
4179         }
4180
4181         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4182                 rte_mem_lock_page(((char *)mz->addr) + sz);
4183                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4184                 rmem->dma_arr[i] = mz_phys_addr + sz;
4185
4186                 if (rmem->nr_pages > 1) {
4187                         if (i == rmem->nr_pages - 2 &&
4188                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4189                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4190                         else if (i == rmem->nr_pages - 1 &&
4191                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4192                                 valid_bits |= PTU_PTE_LAST;
4193
4194                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4195                                                            valid_bits);
4196                 }
4197         }
4198
4199         rmem->mz = mz;
4200         if (rmem->vmem_size)
4201                 rmem->vmem = (void **)mz->addr;
4202         rmem->dma_arr[0] = mz_phys_addr;
4203         return 0;
4204 }
4205
4206 static void bnxt_free_ctx_mem(struct bnxt *bp)
4207 {
4208         int i;
4209
4210         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4211                 return;
4212
4213         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4214         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4215         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4216         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4217         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4218         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4219         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4220         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4221         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4222         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4223         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4224
4225         for (i = 0; i < BNXT_MAX_Q; i++) {
4226                 if (bp->ctx->tqm_mem[i])
4227                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4228         }
4229
4230         rte_free(bp->ctx);
4231         bp->ctx = NULL;
4232 }
4233
4234 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4235
4236 #define min_t(type, x, y) ({                    \
4237         type __min1 = (x);                      \
4238         type __min2 = (y);                      \
4239         __min1 < __min2 ? __min1 : __min2; })
4240
4241 #define max_t(type, x, y) ({                    \
4242         type __max1 = (x);                      \
4243         type __max2 = (y);                      \
4244         __max1 > __max2 ? __max1 : __max2; })
4245
4246 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4247
4248 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4249 {
4250         struct bnxt_ctx_pg_info *ctx_pg;
4251         struct bnxt_ctx_mem_info *ctx;
4252         uint32_t mem_size, ena, entries;
4253         int i, rc;
4254
4255         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4256         if (rc) {
4257                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4258                 return rc;
4259         }
4260         ctx = bp->ctx;
4261         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4262                 return 0;
4263
4264         ctx_pg = &ctx->qp_mem;
4265         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4266         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4267         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4268         if (rc)
4269                 return rc;
4270
4271         ctx_pg = &ctx->srq_mem;
4272         ctx_pg->entries = ctx->srq_max_l2_entries;
4273         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4274         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4275         if (rc)
4276                 return rc;
4277
4278         ctx_pg = &ctx->cq_mem;
4279         ctx_pg->entries = ctx->cq_max_l2_entries;
4280         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4281         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4282         if (rc)
4283                 return rc;
4284
4285         ctx_pg = &ctx->vnic_mem;
4286         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4287                 ctx->vnic_max_ring_table_entries;
4288         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4289         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4290         if (rc)
4291                 return rc;
4292
4293         ctx_pg = &ctx->stat_mem;
4294         ctx_pg->entries = ctx->stat_max_entries;
4295         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4296         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4297         if (rc)
4298                 return rc;
4299
4300         entries = ctx->qp_max_l2_entries +
4301                   ctx->vnic_max_vnic_entries +
4302                   ctx->tqm_min_entries_per_ring;
4303         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4304         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4305                           ctx->tqm_max_entries_per_ring);
4306         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4307                 ctx_pg = ctx->tqm_mem[i];
4308                 /* use min tqm entries for now. */
4309                 ctx_pg->entries = entries;
4310                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4311                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4312                 if (rc)
4313                         return rc;
4314                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4315         }
4316
4317         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4318         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4319         if (rc)
4320                 PMD_DRV_LOG(ERR,
4321                             "Failed to configure context mem: rc = %d\n", rc);
4322         else
4323                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4324
4325         return rc;
4326 }
4327
4328 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4329 {
4330         struct rte_pci_device *pci_dev = bp->pdev;
4331         char mz_name[RTE_MEMZONE_NAMESIZE];
4332         const struct rte_memzone *mz = NULL;
4333         uint32_t total_alloc_len;
4334         rte_iova_t mz_phys_addr;
4335
4336         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4337                 return 0;
4338
4339         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4340                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4341                  pci_dev->addr.bus, pci_dev->addr.devid,
4342                  pci_dev->addr.function, "rx_port_stats");
4343         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4344         mz = rte_memzone_lookup(mz_name);
4345         total_alloc_len =
4346                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4347                                        sizeof(struct rx_port_stats_ext) + 512);
4348         if (!mz) {
4349                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4350                                          SOCKET_ID_ANY,
4351                                          RTE_MEMZONE_2MB |
4352                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4353                                          RTE_MEMZONE_IOVA_CONTIG);
4354                 if (mz == NULL)
4355                         return -ENOMEM;
4356         }
4357         memset(mz->addr, 0, mz->len);
4358         mz_phys_addr = mz->iova;
4359         if ((unsigned long)mz->addr == mz_phys_addr) {
4360                 PMD_DRV_LOG(DEBUG,
4361                             "Memzone physical address same as virtual.\n");
4362                 PMD_DRV_LOG(DEBUG,
4363                             "Using rte_mem_virt2iova()\n");
4364                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4365                 if (mz_phys_addr == RTE_BAD_IOVA) {
4366                         PMD_DRV_LOG(ERR,
4367                                     "Can't map address to physical memory\n");
4368                         return -ENOMEM;
4369                 }
4370         }
4371
4372         bp->rx_mem_zone = (const void *)mz;
4373         bp->hw_rx_port_stats = mz->addr;
4374         bp->hw_rx_port_stats_map = mz_phys_addr;
4375
4376         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4377                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4378                  pci_dev->addr.bus, pci_dev->addr.devid,
4379                  pci_dev->addr.function, "tx_port_stats");
4380         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4381         mz = rte_memzone_lookup(mz_name);
4382         total_alloc_len =
4383                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4384                                        sizeof(struct tx_port_stats_ext) + 512);
4385         if (!mz) {
4386                 mz = rte_memzone_reserve(mz_name,
4387                                          total_alloc_len,
4388                                          SOCKET_ID_ANY,
4389                                          RTE_MEMZONE_2MB |
4390                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4391                                          RTE_MEMZONE_IOVA_CONTIG);
4392                 if (mz == NULL)
4393                         return -ENOMEM;
4394         }
4395         memset(mz->addr, 0, mz->len);
4396         mz_phys_addr = mz->iova;
4397         if ((unsigned long)mz->addr == mz_phys_addr) {
4398                 PMD_DRV_LOG(DEBUG,
4399                             "Memzone physical address same as virtual\n");
4400                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4401                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4402                 if (mz_phys_addr == RTE_BAD_IOVA) {
4403                         PMD_DRV_LOG(ERR,
4404                                     "Can't map address to physical memory\n");
4405                         return -ENOMEM;
4406                 }
4407         }
4408
4409         bp->tx_mem_zone = (const void *)mz;
4410         bp->hw_tx_port_stats = mz->addr;
4411         bp->hw_tx_port_stats_map = mz_phys_addr;
4412         bp->flags |= BNXT_FLAG_PORT_STATS;
4413
4414         /* Display extended statistics if FW supports it */
4415         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4416             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4417             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4418                 return 0;
4419
4420         bp->hw_rx_port_stats_ext = (void *)
4421                 ((uint8_t *)bp->hw_rx_port_stats +
4422                  sizeof(struct rx_port_stats));
4423         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4424                 sizeof(struct rx_port_stats);
4425         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4426
4427         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4428             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4429                 bp->hw_tx_port_stats_ext = (void *)
4430                         ((uint8_t *)bp->hw_tx_port_stats +
4431                          sizeof(struct tx_port_stats));
4432                 bp->hw_tx_port_stats_ext_map =
4433                         bp->hw_tx_port_stats_map +
4434                         sizeof(struct tx_port_stats);
4435                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4436         }
4437
4438         return 0;
4439 }
4440
4441 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4442 {
4443         struct bnxt *bp = eth_dev->data->dev_private;
4444         int rc = 0;
4445
4446         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4447                                                RTE_ETHER_ADDR_LEN *
4448                                                bp->max_l2_ctx,
4449                                                0);
4450         if (eth_dev->data->mac_addrs == NULL) {
4451                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4452                 return -ENOMEM;
4453         }
4454
4455         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4456                 if (BNXT_PF(bp))
4457                         return -EINVAL;
4458
4459                 /* Generate a random MAC address, if none was assigned by PF */
4460                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4461                 bnxt_eth_hw_addr_random(bp->mac_addr);
4462                 PMD_DRV_LOG(INFO,
4463                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4464                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4465                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4466
4467                 rc = bnxt_hwrm_set_mac(bp);
4468                 if (!rc)
4469                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4470                                RTE_ETHER_ADDR_LEN);
4471                 return rc;
4472         }
4473
4474         /* Copy the permanent MAC from the FUNC_QCAPS response */
4475         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4476         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4477
4478         return rc;
4479 }
4480
4481 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4482 {
4483         int rc = 0;
4484
4485         /* MAC is already configured in FW */
4486         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4487                 return 0;
4488
4489         /* Restore the old MAC configured */
4490         rc = bnxt_hwrm_set_mac(bp);
4491         if (rc)
4492                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4493
4494         return rc;
4495 }
4496
4497 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4498 {
4499         if (!BNXT_PF(bp))
4500                 return;
4501
4502 #define ALLOW_FUNC(x)   \
4503         { \
4504                 uint32_t arg = (x); \
4505                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4506                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4507         }
4508
4509         /* Forward all requests if firmware is new enough */
4510         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4511              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4512             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4513                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4514         } else {
4515                 PMD_DRV_LOG(WARNING,
4516                             "Firmware too old for VF mailbox functionality\n");
4517                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4518         }
4519
4520         /*
4521          * The following are used for driver cleanup. If we disallow these,
4522          * VF drivers can't clean up cleanly.
4523          */
4524         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4525         ALLOW_FUNC(HWRM_VNIC_FREE);
4526         ALLOW_FUNC(HWRM_RING_FREE);
4527         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4528         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4529         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4530         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4531         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4532         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4533 }
4534
4535 static int bnxt_init_fw(struct bnxt *bp)
4536 {
4537         uint16_t mtu;
4538         int rc = 0;
4539
4540         rc = bnxt_hwrm_ver_get(bp);
4541         if (rc)
4542                 return rc;
4543
4544         rc = bnxt_hwrm_func_reset(bp);
4545         if (rc)
4546                 return -EIO;
4547
4548         rc = bnxt_hwrm_vnic_qcaps(bp);
4549         if (rc)
4550                 return rc;
4551
4552         rc = bnxt_hwrm_queue_qportcfg(bp);
4553         if (rc)
4554                 return rc;
4555
4556         /* Get the MAX capabilities for this function.
4557          * This function also allocates context memory for TQM rings and
4558          * informs the firmware about this allocated backing store memory.
4559          */
4560         rc = bnxt_hwrm_func_qcaps(bp);
4561         if (rc)
4562                 return rc;
4563
4564         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4565         if (rc)
4566                 return rc;
4567
4568         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4569         if (rc)
4570                 return rc;
4571
4572         /* Get the adapter error recovery support info */
4573         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4574         if (rc)
4575                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4576
4577         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4578             mtu != bp->eth_dev->data->mtu)
4579                 bp->eth_dev->data->mtu = mtu;
4580
4581         bnxt_hwrm_port_led_qcaps(bp);
4582
4583         return 0;
4584 }
4585
4586 static int
4587 bnxt_init_locks(struct bnxt *bp)
4588 {
4589         int err;
4590
4591         err = pthread_mutex_init(&bp->flow_lock, NULL);
4592         if (err) {
4593                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4594                 return err;
4595         }
4596
4597         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4598         if (err)
4599                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4600         return err;
4601 }
4602
4603 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4604 {
4605         int rc;
4606
4607         rc = bnxt_init_fw(bp);
4608         if (rc)
4609                 return rc;
4610
4611         if (!reconfig_dev) {
4612                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4613                 if (rc)
4614                         return rc;
4615         } else {
4616                 rc = bnxt_restore_dflt_mac(bp);
4617                 if (rc)
4618                         return rc;
4619         }
4620
4621         bnxt_config_vf_req_fwd(bp);
4622
4623         rc = bnxt_hwrm_func_driver_register(bp);
4624         if (rc) {
4625                 PMD_DRV_LOG(ERR, "Failed to register driver");
4626                 return -EBUSY;
4627         }
4628
4629         if (BNXT_PF(bp)) {
4630                 if (bp->pdev->max_vfs) {
4631                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4632                         if (rc) {
4633                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4634                                 return rc;
4635                         }
4636                 } else {
4637                         rc = bnxt_hwrm_allocate_pf_only(bp);
4638                         if (rc) {
4639                                 PMD_DRV_LOG(ERR,
4640                                             "Failed to allocate PF resources");
4641                                 return rc;
4642                         }
4643                 }
4644         }
4645
4646         rc = bnxt_alloc_mem(bp, reconfig_dev);
4647         if (rc)
4648                 return rc;
4649
4650         rc = bnxt_setup_int(bp);
4651         if (rc)
4652                 return rc;
4653
4654         bnxt_init_nic(bp);
4655
4656         rc = bnxt_request_int(bp);
4657         if (rc)
4658                 return rc;
4659
4660         rc = bnxt_init_locks(bp);
4661         if (rc)
4662                 return rc;
4663
4664         return 0;
4665 }
4666
4667 static int
4668 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4669 {
4670         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4671         static int version_printed;
4672         struct bnxt *bp;
4673         int rc;
4674
4675         if (version_printed++ == 0)
4676                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4677
4678         eth_dev->dev_ops = &bnxt_dev_ops;
4679         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4680         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4681
4682         /*
4683          * For secondary processes, we don't initialise any further
4684          * as primary has already done this work.
4685          */
4686         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4687                 return 0;
4688
4689         rte_eth_copy_pci_info(eth_dev, pci_dev);
4690
4691         bp = eth_dev->data->dev_private;
4692
4693         bp->dev_stopped = 1;
4694
4695         if (bnxt_vf_pciid(pci_dev->id.device_id))
4696                 bp->flags |= BNXT_FLAG_VF;
4697
4698         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4699             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4700             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4701             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4702             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4703                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4704
4705         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4706             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4707             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4708             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4709                 bp->flags |= BNXT_FLAG_STINGRAY;
4710
4711         rc = bnxt_init_board(eth_dev);
4712         if (rc) {
4713                 PMD_DRV_LOG(ERR,
4714                             "Failed to initialize board rc: %x\n", rc);
4715                 return rc;
4716         }
4717
4718         rc = bnxt_alloc_hwrm_resources(bp);
4719         if (rc) {
4720                 PMD_DRV_LOG(ERR,
4721                             "Failed to allocate hwrm resource rc: %x\n", rc);
4722                 goto error_free;
4723         }
4724         rc = bnxt_init_resources(bp, false);
4725         if (rc)
4726                 goto error_free;
4727
4728         rc = bnxt_alloc_stats_mem(bp);
4729         if (rc)
4730                 goto error_free;
4731
4732         PMD_DRV_LOG(INFO,
4733                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4734                     pci_dev->mem_resource[0].phys_addr,
4735                     pci_dev->mem_resource[0].addr);
4736
4737         return 0;
4738
4739 error_free:
4740         bnxt_dev_uninit(eth_dev);
4741         return rc;
4742 }
4743
4744 static void
4745 bnxt_uninit_locks(struct bnxt *bp)
4746 {
4747         pthread_mutex_destroy(&bp->flow_lock);
4748         pthread_mutex_destroy(&bp->def_cp_lock);
4749 }
4750
4751 static int
4752 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4753 {
4754         int rc;
4755
4756         bnxt_free_int(bp);
4757         bnxt_free_mem(bp, reconfig_dev);
4758         bnxt_hwrm_func_buf_unrgtr(bp);
4759         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4760         bp->flags &= ~BNXT_FLAG_REGISTERED;
4761         bnxt_free_ctx_mem(bp);
4762         if (!reconfig_dev) {
4763                 bnxt_free_hwrm_resources(bp);
4764
4765                 if (bp->recovery_info != NULL) {
4766                         rte_free(bp->recovery_info);
4767                         bp->recovery_info = NULL;
4768                 }
4769         }
4770
4771         rte_free(bp->ptp_cfg);
4772         bp->ptp_cfg = NULL;
4773         return rc;
4774 }
4775
4776 static int
4777 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4778 {
4779         struct bnxt *bp = eth_dev->data->dev_private;
4780         int rc;
4781
4782         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4783                 return -EPERM;
4784
4785         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4786
4787         rc = bnxt_uninit_resources(bp, false);
4788
4789         if (bp->grp_info != NULL) {
4790                 rte_free(bp->grp_info);
4791                 bp->grp_info = NULL;
4792         }
4793
4794         if (bp->tx_mem_zone) {
4795                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4796                 bp->tx_mem_zone = NULL;
4797         }
4798
4799         if (bp->rx_mem_zone) {
4800                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4801                 bp->rx_mem_zone = NULL;
4802         }
4803
4804         if (bp->dev_stopped == 0)
4805                 bnxt_dev_close_op(eth_dev);
4806         if (bp->pf.vf_info)
4807                 rte_free(bp->pf.vf_info);
4808         eth_dev->dev_ops = NULL;
4809         eth_dev->rx_pkt_burst = NULL;
4810         eth_dev->tx_pkt_burst = NULL;
4811
4812         bnxt_uninit_locks(bp);
4813
4814         return rc;
4815 }
4816
4817 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4818         struct rte_pci_device *pci_dev)
4819 {
4820         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4821                 bnxt_dev_init);
4822 }
4823
4824 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4825 {
4826         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4827                 return rte_eth_dev_pci_generic_remove(pci_dev,
4828                                 bnxt_dev_uninit);
4829         else
4830                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4831 }
4832
4833 static struct rte_pci_driver bnxt_rte_pmd = {
4834         .id_table = bnxt_pci_id_map,
4835         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4836         .probe = bnxt_pci_probe,
4837         .remove = bnxt_pci_remove,
4838 };
4839
4840 static bool
4841 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4842 {
4843         if (strcmp(dev->device->driver->name, drv->driver.name))
4844                 return false;
4845
4846         return true;
4847 }
4848
4849 bool is_bnxt_supported(struct rte_eth_dev *dev)
4850 {
4851         return is_device_supported(dev, &bnxt_rte_pmd);
4852 }
4853
4854 RTE_INIT(bnxt_init_log)
4855 {
4856         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4857         if (bnxt_logtype_driver >= 0)
4858                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4859 }
4860
4861 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4862 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4863 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");