drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29
  30 #define DRV_MODULE_NAME         "bnxt"
  31 static const char bnxt_version[] =
  32         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  33 int bnxt_logtype_driver;
  34
  35 /*
  36  * The set of PCI devices this driver supports
  37  */
  38 static const struct rte_pci_id bnxt_pci_id_map[] = {
  39         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  40                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  41         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  42                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  43         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  92         { .vendor_id = 0, /* sentinel */ },
  93 };
  94
  95 #define BNXT_ETH_RSS_SUPPORT (  \
  96         ETH_RSS_IPV4 |          \
  97         ETH_RSS_NONFRAG_IPV4_TCP |      \
  98         ETH_RSS_NONFRAG_IPV4_UDP |      \
  99         ETH_RSS_IPV6 |          \
 100         ETH_RSS_NONFRAG_IPV6_TCP |      \
 101         ETH_RSS_NONFRAG_IPV6_UDP)
 102
 103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 104                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 105                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 106                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_TCP_TSO | \
 108                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 109                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 110                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 114                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 115
 116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 117                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 118                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 119                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 120                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 122                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 123                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 124                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 125                                      DEV_RX_OFFLOAD_TCP_LRO | \
 126                                      DEV_RX_OFFLOAD_SCATTER | \
 127                                      DEV_RX_OFFLOAD_RSS_HASH)
 128
 129 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 130 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 131 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 132 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 133 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 134 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 135
 136 int is_bnxt_in_error(struct bnxt *bp)
 137 {
 138         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 139                 return -EIO;
 140         if (bp->flags & BNXT_FLAG_FW_RESET)
 141                 return -EBUSY;
 142
 143         return 0;
 144 }
 145
 146 /***********************/
 147
 148 /*
 149  * High level utility functions
 150  */
 151
 152 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 153 {
 154         if (!BNXT_CHIP_THOR(bp))
 155                 return 1;
 156
 157         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 158                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 159                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 160 }
 161
 162 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 163 {
 164         if (!BNXT_CHIP_THOR(bp))
 165                 return HW_HASH_INDEX_SIZE;
 166
 167         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 168 }
 169
 170 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 171 {
 172         bnxt_free_filter_mem(bp);
 173         bnxt_free_vnic_attributes(bp);
 174         bnxt_free_vnic_mem(bp);
 175
 176         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 177          * If the number of rings change across fw update,
 178          * we don't have much choice except to warn the user.
 179          */
 180         if (!reconfig) {
 181                 bnxt_free_stats(bp);
 182                 bnxt_free_tx_rings(bp);
 183                 bnxt_free_rx_rings(bp);
 184         }
 185         bnxt_free_async_cp_ring(bp);
 186         bnxt_free_rxtx_nq_ring(bp);
 187
 188         rte_free(bp->grp_info);
 189         bp->grp_info = NULL;
 190 }
 191
 192 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 193 {
 194         int rc;
 195
 196         rc = bnxt_alloc_ring_grps(bp);
 197         if (rc)
 198                 goto alloc_mem_err;
 199
 200         rc = bnxt_alloc_async_ring_struct(bp);
 201         if (rc)
 202                 goto alloc_mem_err;
 203
 204         rc = bnxt_alloc_vnic_mem(bp);
 205         if (rc)
 206                 goto alloc_mem_err;
 207
 208         rc = bnxt_alloc_vnic_attributes(bp);
 209         if (rc)
 210                 goto alloc_mem_err;
 211
 212         rc = bnxt_alloc_filter_mem(bp);
 213         if (rc)
 214                 goto alloc_mem_err;
 215
 216         rc = bnxt_alloc_async_cp_ring(bp);
 217         if (rc)
 218                 goto alloc_mem_err;
 219
 220         rc = bnxt_alloc_rxtx_nq_ring(bp);
 221         if (rc)
 222                 goto alloc_mem_err;
 223
 224         return 0;
 225
 226 alloc_mem_err:
 227         bnxt_free_mem(bp, reconfig);
 228         return rc;
 229 }
 230
 231 static int bnxt_init_chip(struct bnxt *bp)
 232 {
 233         struct bnxt_rx_queue *rxq;
 234         struct rte_eth_link new;
 235         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 236         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 237         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 238         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 239         uint32_t intr_vector = 0;
 240         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 241         uint32_t vec = BNXT_MISC_VEC_ID;
 242         unsigned int i, j;
 243         int rc;
 244
 245         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 246                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 247                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 248                 bp->flags |= BNXT_FLAG_JUMBO;
 249         } else {
 250                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 251                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 252                 bp->flags &= ~BNXT_FLAG_JUMBO;
 253         }
 254
 255         /* THOR does not support ring groups.
 256          * But we will use the array to save RSS context IDs.
 257          */
 258         if (BNXT_CHIP_THOR(bp))
 259                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 260
 261         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 262         if (rc) {
 263                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 264                 goto err_out;
 265         }
 266
 267         rc = bnxt_alloc_hwrm_rings(bp);
 268         if (rc) {
 269                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 270                 goto err_out;
 271         }
 272
 273         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 274         if (rc) {
 275                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 276                 goto err_out;
 277         }
 278
 279         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 280                 goto skip_cosq_cfg;
 281
 282         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 283                 if (bp->rx_cos_queue[i].id != 0xff) {
 284                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 285
 286                         if (!vnic) {
 287                                 PMD_DRV_LOG(ERR,
 288                                             "Num pools more than FW profile\n");
 289                                 rc = -EINVAL;
 290                                 goto err_out;
 291                         }
 292                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 293                         bp->rx_cosq_cnt++;
 294                 }
 295         }
 296
 297 skip_cosq_cfg:
 298         rc = bnxt_mq_rx_configure(bp);
 299         if (rc) {
 300                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 301                 goto err_out;
 302         }
 303
 304         /* VNIC configuration */
 305         for (i = 0; i < bp->nr_vnics; i++) {
 306                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 307                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 308
 309                 rc = bnxt_vnic_grp_alloc(bp, vnic);
 310                 if (rc)
 311                         goto err_out;
 312
 313                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 314                             i, vnic, vnic->fw_grp_ids);
 315
 316                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 317                 if (rc) {
 318                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 319                                 i, rc);
 320                         goto err_out;
 321                 }
 322
 323                 /* Alloc RSS context only if RSS mode is enabled */
 324                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 325                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 326
 327                         rc = 0;
 328                         for (j = 0; j < nr_ctxs; j++) {
 329                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 330                                 if (rc)
 331                                         break;
 332                         }
 333                         if (rc) {
 334                                 PMD_DRV_LOG(ERR,
 335                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 336                                   i, j, rc);
 337                                 goto err_out;
 338                         }
 339                         vnic->num_lb_ctxts = nr_ctxs;
 340                 }
 341
 342                 /*
 343                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 344                  * setting is not available at this time, it will not be
 345                  * configured correctly in the CFA.
 346                  */
 347                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 348                         vnic->vlan_strip = true;
 349                 else
 350                         vnic->vlan_strip = false;
 351
 352                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 353                 if (rc) {
 354                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 355                                 i, rc);
 356                         goto err_out;
 357                 }
 358
 359                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 360                 if (rc) {
 361                         PMD_DRV_LOG(ERR,
 362                                 "HWRM vnic %d filter failure rc: %x\n",
 363                                 i, rc);
 364                         goto err_out;
 365                 }
 366
 367                 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 368                         rxq = bp->eth_dev->data->rx_queues[j];
 369
 370                         PMD_DRV_LOG(DEBUG,
 371                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 372                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 373
 374                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 375                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 376                 }
 377
 378                 rc = bnxt_vnic_rss_configure(bp, vnic);
 379                 if (rc) {
 380                         PMD_DRV_LOG(ERR,
 381                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 382                         goto err_out;
 383                 }
 384
 385                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 386
 387                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 388                     DEV_RX_OFFLOAD_TCP_LRO)
 389                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 390                 else
 391                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 392         }
 393         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 394         if (rc) {
 395                 PMD_DRV_LOG(ERR,
 396                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 397                 goto err_out;
 398         }
 399
 400         /* check and configure queue intr-vector mapping */
 401         if ((rte_intr_cap_multiple(intr_handle) ||
 402              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 403             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 404                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 405                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 406                 if (intr_vector > bp->rx_cp_nr_rings) {
 407                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 408                                         bp->rx_cp_nr_rings);
 409                         return -ENOTSUP;
 410                 }
 411                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 412                 if (rc)
 413                         return rc;
 414         }
 415
 416         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 417                 intr_handle->intr_vec =
 418                         rte_zmalloc("intr_vec",
 419                                     bp->eth_dev->data->nb_rx_queues *
 420                                     sizeof(int), 0);
 421                 if (intr_handle->intr_vec == NULL) {
 422                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 423                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 424                         rc = -ENOMEM;
 425                         goto err_disable;
 426                 }
 427                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 428                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 429                          intr_handle->intr_vec, intr_handle->nb_efd,
 430                         intr_handle->max_intr);
 431                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 432                      queue_id++) {
 433                         intr_handle->intr_vec[queue_id] =
 434                                                         vec + BNXT_RX_VEC_START;
 435                         if (vec < base + intr_handle->nb_efd - 1)
 436                                 vec++;
 437                 }
 438         }
 439
 440         /* enable uio/vfio intr/eventfd mapping */
 441         rc = rte_intr_enable(intr_handle);
 442         if (rc)
 443                 goto err_free;
 444
 445         rc = bnxt_get_hwrm_link_config(bp, &new);
 446         if (rc) {
 447                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 448                 goto err_free;
 449         }
 450
 451         if (!bp->link_info.link_up) {
 452                 rc = bnxt_set_hwrm_link_config(bp, true);
 453                 if (rc) {
 454                         PMD_DRV_LOG(ERR,
 455                                 "HWRM link config failure rc: %x\n", rc);
 456                         goto err_free;
 457                 }
 458         }
 459         bnxt_print_link_info(bp->eth_dev);
 460
 461         return 0;
 462
 463 err_free:
 464         rte_free(intr_handle->intr_vec);
 465 err_disable:
 466         rte_intr_efd_disable(intr_handle);
 467 err_out:
 468         /* Some of the error status returned by FW may not be from errno.h */
 469         if (rc > 0)
 470                 rc = -EIO;
 471
 472         return rc;
 473 }
 474
 475 static int bnxt_shutdown_nic(struct bnxt *bp)
 476 {
 477         bnxt_free_all_hwrm_resources(bp);
 478         bnxt_free_all_filters(bp);
 479         bnxt_free_all_vnics(bp);
 480         return 0;
 481 }
 482
 483 /*
 484  * Device configuration and status function
 485  */
 486
 487 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 488                                 struct rte_eth_dev_info *dev_info)
 489 {
 490         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 491         struct bnxt *bp = eth_dev->data->dev_private;
 492         uint16_t max_vnics, i, j, vpool, vrxq;
 493         unsigned int max_rx_rings;
 494         int rc;
 495
 496         rc = is_bnxt_in_error(bp);
 497         if (rc)
 498                 return rc;
 499
 500         /* MAC Specifics */
 501         dev_info->max_mac_addrs = bp->max_l2_ctx;
 502         dev_info->max_hash_mac_addrs = 0;
 503
 504         /* PF/VF specifics */
 505         if (BNXT_PF(bp))
 506                 dev_info->max_vfs = pdev->max_vfs;
 507
 508         max_rx_rings = BNXT_MAX_RINGS(bp);
 509         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 510         dev_info->max_rx_queues = max_rx_rings;
 511         dev_info->max_tx_queues = max_rx_rings;
 512         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 513         dev_info->hash_key_size = 40;
 514         max_vnics = bp->max_vnics;
 515
 516         /* MTU specifics */
 517         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 518         dev_info->max_mtu = BNXT_MAX_MTU;
 519
 520         /* Fast path specifics */
 521         dev_info->min_rx_bufsize = 1;
 522         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 523
 524         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 525         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 526                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 527         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 528         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 529
 530         /* *INDENT-OFF* */
 531         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 532                 .rx_thresh = {
 533                         .pthresh = 8,
 534                         .hthresh = 8,
 535                         .wthresh = 0,
 536                 },
 537                 .rx_free_thresh = 32,
 538                 /* If no descriptors available, pkts are dropped by default */
 539                 .rx_drop_en = 1,
 540         };
 541
 542         dev_info->default_txconf = (struct rte_eth_txconf) {
 543                 .tx_thresh = {
 544                         .pthresh = 32,
 545                         .hthresh = 0,
 546                         .wthresh = 0,
 547                 },
 548                 .tx_free_thresh = 32,
 549                 .tx_rs_thresh = 32,
 550         };
 551         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 552
 553         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 554         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 555         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 556         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 557         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 558
 559         /* *INDENT-ON* */
 560
 561         /*
 562          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 563          *       need further investigation.
 564          */
 565
 566         /* VMDq resources */
 567         vpool = 64; /* ETH_64_POOLS */
 568         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 569         for (i = 0; i < 4; vpool >>= 1, i++) {
 570                 if (max_vnics > vpool) {
 571                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 572                                 if (dev_info->max_rx_queues > vrxq) {
 573                                         if (vpool > vrxq)
 574                                                 vpool = vrxq;
 575                                         goto found;
 576                                 }
 577                         }
 578                         /* Not enough resources to support VMDq */
 579                         break;
 580                 }
 581         }
 582         /* Not enough resources to support VMDq */
 583         vpool = 0;
 584         vrxq = 0;
 585 found:
 586         dev_info->max_vmdq_pools = vpool;
 587         dev_info->vmdq_queue_num = vrxq;
 588
 589         dev_info->vmdq_pool_base = 0;
 590         dev_info->vmdq_queue_base = 0;
 591
 592         return 0;
 593 }
 594
 595 /* Configure the device based on the configuration provided */
 596 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 597 {
 598         struct bnxt *bp = eth_dev->data->dev_private;
 599         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 600         int rc;
 601
 602         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 603         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 604         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 605         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 606
 607         rc = is_bnxt_in_error(bp);
 608         if (rc)
 609                 return rc;
 610
 611         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 612                 rc = bnxt_hwrm_check_vf_rings(bp);
 613                 if (rc) {
 614                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 615                         return -ENOSPC;
 616                 }
 617
 618                 /* If a resource has already been allocated - in this case
 619                  * it is the async completion ring, free it. Reallocate it after
 620                  * resource reservation. This will ensure the resource counts
 621                  * are calculated correctly.
 622                  */
 623
 624                 pthread_mutex_lock(&bp->def_cp_lock);
 625
 626                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 627                         bnxt_disable_int(bp);
 628                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 629                 }
 630
 631                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 632                 if (rc) {
 633                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 634                         pthread_mutex_unlock(&bp->def_cp_lock);
 635                         return -ENOSPC;
 636                 }
 637
 638                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 639                         rc = bnxt_alloc_async_cp_ring(bp);
 640                         if (rc) {
 641                                 pthread_mutex_unlock(&bp->def_cp_lock);
 642                                 return rc;
 643                         }
 644                         bnxt_enable_int(bp);
 645                 }
 646
 647                 pthread_mutex_unlock(&bp->def_cp_lock);
 648         } else {
 649                 /* legacy driver needs to get updated values */
 650                 rc = bnxt_hwrm_func_qcaps(bp);
 651                 if (rc) {
 652                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 653                         return rc;
 654                 }
 655         }
 656
 657         /* Inherit new configurations */
 658         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 659             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 660             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 661                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 662             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 663             bp->max_stat_ctx)
 664                 goto resource_error;
 665
 666         if (BNXT_HAS_RING_GRPS(bp) &&
 667             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 668                 goto resource_error;
 669
 670         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 671             bp->max_vnics < eth_dev->data->nb_rx_queues)
 672                 goto resource_error;
 673
 674         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 675         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 676
 677         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 678                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 679         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
 680
 681         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 682                 eth_dev->data->mtu =
 683                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 684                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 685                         BNXT_NUM_VLANS;
 686                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 687         }
 688         return 0;
 689
 690 resource_error:
 691         PMD_DRV_LOG(ERR,
 692                     "Insufficient resources to support requested config\n");
 693         PMD_DRV_LOG(ERR,
 694                     "Num Queues Requested: Tx %d, Rx %d\n",
 695                     eth_dev->data->nb_tx_queues,
 696                     eth_dev->data->nb_rx_queues);
 697         PMD_DRV_LOG(ERR,
 698                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 699                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 700                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 701         return -ENOSPC;
 702 }
 703
 704 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 705 {
 706         struct rte_eth_link *link = &eth_dev->data->dev_link;
 707
 708         if (link->link_status)
 709                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 710                         eth_dev->data->port_id,
 711                         (uint32_t)link->link_speed,
 712                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 713                         ("full-duplex") : ("half-duplex\n"));
 714         else
 715                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 716                         eth_dev->data->port_id);
 717 }
 718
 719 /*
 720  * Determine whether the current configuration requires support for scattered
 721  * receive; return 1 if scattered receive is required and 0 if not.
 722  */
 723 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 724 {
 725         uint16_t buf_size;
 726         int i;
 727
 728         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 729                 return 1;
 730
 731         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 732                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 733
 734                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 735                                       RTE_PKTMBUF_HEADROOM);
 736                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 737                         return 1;
 738         }
 739         return 0;
 740 }
 741
 742 static eth_rx_burst_t
 743 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 744 {
 745 #ifdef RTE_ARCH_X86
 746 #ifndef RTE_LIBRTE_IEEE1588
 747         /*
 748          * Vector mode receive can be enabled only if scatter rx is not
 749          * in use and rx offloads are limited to VLAN stripping and
 750          * CRC stripping.
 751          */
 752         if (!eth_dev->data->scattered_rx &&
 753             !(eth_dev->data->dev_conf.rxmode.offloads &
 754               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 755                 DEV_RX_OFFLOAD_KEEP_CRC |
 756                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 757                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 758                 DEV_RX_OFFLOAD_UDP_CKSUM |
 759                 DEV_RX_OFFLOAD_TCP_CKSUM |
 760                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 761                 DEV_RX_OFFLOAD_RSS_HASH |
 762                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 763                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 764                             eth_dev->data->port_id);
 765                 return bnxt_recv_pkts_vec;
 766         }
 767         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 768                     eth_dev->data->port_id);
 769         PMD_DRV_LOG(INFO,
 770                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 771                     eth_dev->data->port_id,
 772                     eth_dev->data->scattered_rx,
 773                     eth_dev->data->dev_conf.rxmode.offloads);
 774 #endif
 775 #endif
 776         return bnxt_recv_pkts;
 777 }
 778
 779 static eth_tx_burst_t
 780 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 781 {
 782 #ifdef RTE_ARCH_X86
 783 #ifndef RTE_LIBRTE_IEEE1588
 784         /*
 785          * Vector mode transmit can be enabled only if not using scatter rx
 786          * or tx offloads.
 787          */
 788         if (!eth_dev->data->scattered_rx &&
 789             !eth_dev->data->dev_conf.txmode.offloads) {
 790                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 791                             eth_dev->data->port_id);
 792                 return bnxt_xmit_pkts_vec;
 793         }
 794         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 795                     eth_dev->data->port_id);
 796         PMD_DRV_LOG(INFO,
 797                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 798                     eth_dev->data->port_id,
 799                     eth_dev->data->scattered_rx,
 800                     eth_dev->data->dev_conf.txmode.offloads);
 801 #endif
 802 #endif
 803         return bnxt_xmit_pkts;
 804 }
 805
 806 static int bnxt_handle_if_change_status(struct bnxt *bp)
 807 {
 808         int rc;
 809
 810         /* Since fw has undergone a reset and lost all contexts,
 811          * set fatal flag to not issue hwrm during cleanup
 812          */
 813         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 814         bnxt_uninit_resources(bp, true);
 815
 816         /* clear fatal flag so that re-init happens */
 817         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 818         rc = bnxt_init_resources(bp, true);
 819
 820         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 821
 822         return rc;
 823 }
 824
 825 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 826 {
 827         struct bnxt *bp = eth_dev->data->dev_private;
 828         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 829         int vlan_mask = 0;
 830         int rc;
 831
 832         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
 833                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
 834                 return -EINVAL;
 835         }
 836
 837         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 838                 PMD_DRV_LOG(ERR,
 839                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 840                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 841         }
 842
 843         rc = bnxt_hwrm_if_change(bp, 1);
 844         if (!rc) {
 845                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 846                         rc = bnxt_handle_if_change_status(bp);
 847                         if (rc)
 848                                 return rc;
 849                 }
 850         }
 851         bnxt_enable_int(bp);
 852
 853         rc = bnxt_init_chip(bp);
 854         if (rc)
 855                 goto error;
 856
 857         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 858
 859         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
 860
 861         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 862                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 863         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 864                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 865         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 866         if (rc)
 867                 goto error;
 868
 869         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 870         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 871
 872         bp->flags |= BNXT_FLAG_INIT_DONE;
 873         eth_dev->data->dev_started = 1;
 874         bp->dev_stopped = 0;
 875         pthread_mutex_lock(&bp->def_cp_lock);
 876         bnxt_schedule_fw_health_check(bp);
 877         pthread_mutex_unlock(&bp->def_cp_lock);
 878         return 0;
 879
 880 error:
 881         bnxt_hwrm_if_change(bp, 0);
 882         bnxt_shutdown_nic(bp);
 883         bnxt_free_tx_mbufs(bp);
 884         bnxt_free_rx_mbufs(bp);
 885         return rc;
 886 }
 887
 888 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 889 {
 890         struct bnxt *bp = eth_dev->data->dev_private;
 891         int rc = 0;
 892
 893         if (!bp->link_info.link_up)
 894                 rc = bnxt_set_hwrm_link_config(bp, true);
 895         if (!rc)
 896                 eth_dev->data->dev_link.link_status = 1;
 897
 898         bnxt_print_link_info(eth_dev);
 899         return rc;
 900 }
 901
 902 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 903 {
 904         struct bnxt *bp = eth_dev->data->dev_private;
 905
 906         eth_dev->data->dev_link.link_status = 0;
 907         bnxt_set_hwrm_link_config(bp, false);
 908         bp->link_info.link_up = 0;
 909
 910         return 0;
 911 }
 912
 913 /* Unload the driver, release resources */
 914 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 915 {
 916         struct bnxt *bp = eth_dev->data->dev_private;
 917         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 918         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 919
 920         eth_dev->data->dev_started = 0;
 921         /* Prevent crashes when queues are still in use */
 922         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 923         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 924
 925         bnxt_disable_int(bp);
 926
 927         /* disable uio/vfio intr/eventfd mapping */
 928         rte_intr_disable(intr_handle);
 929
 930         bnxt_cancel_fw_health_check(bp);
 931
 932         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 933         if (bp->eth_dev->data->dev_started) {
 934                 /* TBD: STOP HW queues DMA */
 935                 eth_dev->data->dev_link.link_status = 0;
 936         }
 937         bnxt_dev_set_link_down_op(eth_dev);
 938
 939         /* Wait for link to be reset and the async notification to process.
 940          * During reset recovery, there is no need to wait
 941          */
 942         if (!is_bnxt_in_error(bp))
 943                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
 944
 945         /* Clean queue intr-vector mapping */
 946         rte_intr_efd_disable(intr_handle);
 947         if (intr_handle->intr_vec != NULL) {
 948                 rte_free(intr_handle->intr_vec);
 949                 intr_handle->intr_vec = NULL;
 950         }
 951
 952         bnxt_hwrm_port_clr_stats(bp);
 953         bnxt_free_tx_mbufs(bp);
 954         bnxt_free_rx_mbufs(bp);
 955         /* Process any remaining notifications in default completion queue */
 956         bnxt_int_handler(eth_dev);
 957         bnxt_shutdown_nic(bp);
 958         bnxt_hwrm_if_change(bp, 0);
 959         bp->dev_stopped = 1;
 960         bp->rx_cosq_cnt = 0;
 961 }
 962
 963 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 964 {
 965         struct bnxt *bp = eth_dev->data->dev_private;
 966
 967         if (bp->dev_stopped == 0)
 968                 bnxt_dev_stop_op(eth_dev);
 969
 970         if (eth_dev->data->mac_addrs != NULL) {
 971                 rte_free(eth_dev->data->mac_addrs);
 972                 eth_dev->data->mac_addrs = NULL;
 973         }
 974         if (bp->grp_info != NULL) {
 975                 rte_free(bp->grp_info);
 976                 bp->grp_info = NULL;
 977         }
 978
 979         bnxt_dev_uninit(eth_dev);
 980 }
 981
 982 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 983                                     uint32_t index)
 984 {
 985         struct bnxt *bp = eth_dev->data->dev_private;
 986         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 987         struct bnxt_vnic_info *vnic;
 988         struct bnxt_filter_info *filter, *temp_filter;
 989         uint32_t i;
 990
 991         if (is_bnxt_in_error(bp))
 992                 return;
 993
 994         /*
 995          * Loop through all VNICs from the specified filter flow pools to
 996          * remove the corresponding MAC addr filter
 997          */
 998         for (i = 0; i < bp->nr_vnics; i++) {
 999                 if (!(pool_mask & (1ULL << i)))
1000                         continue;
1001
1002                 vnic = &bp->vnic_info[i];
1003                 filter = STAILQ_FIRST(&vnic->filter);
1004                 while (filter) {
1005                         temp_filter = STAILQ_NEXT(filter, next);
1006                         if (filter->mac_index == index) {
1007                                 STAILQ_REMOVE(&vnic->filter, filter,
1008                                                 bnxt_filter_info, next);
1009                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1010                                 bnxt_free_filter(bp, filter);
1011                         }
1012                         filter = temp_filter;
1013                 }
1014         }
1015 }
1016
1017 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1018                                struct rte_ether_addr *mac_addr, uint32_t index,
1019                                uint32_t pool)
1020 {
1021         struct bnxt_filter_info *filter;
1022         int rc = 0;
1023
1024         /* Attach requested MAC address to the new l2_filter */
1025         STAILQ_FOREACH(filter, &vnic->filter, next) {
1026                 if (filter->mac_index == index) {
1027                         PMD_DRV_LOG(DEBUG,
1028                                     "MAC addr already existed for pool %d\n",
1029                                     pool);
1030                         return 0;
1031                 }
1032         }
1033
1034         filter = bnxt_alloc_filter(bp);
1035         if (!filter) {
1036                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1037                 return -ENODEV;
1038         }
1039
1040         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1041          * if the MAC that's been programmed now is a different one, then,
1042          * copy that addr to filter->l2_addr
1043          */
1044         if (mac_addr)
1045                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1046         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1047
1048         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1049         if (!rc) {
1050                 filter->mac_index = index;
1051                 if (filter->mac_index == 0)
1052                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1053                 else
1054                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1055         } else {
1056                 bnxt_free_filter(bp, filter);
1057         }
1058
1059         return rc;
1060 }
1061
1062 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1063                                 struct rte_ether_addr *mac_addr,
1064                                 uint32_t index, uint32_t pool)
1065 {
1066         struct bnxt *bp = eth_dev->data->dev_private;
1067         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1068         int rc = 0;
1069
1070         rc = is_bnxt_in_error(bp);
1071         if (rc)
1072                 return rc;
1073
1074         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1075                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1076                 return -ENOTSUP;
1077         }
1078
1079         if (!vnic) {
1080                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1081                 return -EINVAL;
1082         }
1083
1084         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1085
1086         return rc;
1087 }
1088
1089 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1090                      bool exp_link_status)
1091 {
1092         int rc = 0;
1093         struct bnxt *bp = eth_dev->data->dev_private;
1094         struct rte_eth_link new;
1095         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1096                   BNXT_LINK_DOWN_WAIT_CNT;
1097
1098         rc = is_bnxt_in_error(bp);
1099         if (rc)
1100                 return rc;
1101
1102         memset(&new, 0, sizeof(new));
1103         do {
1104                 /* Retrieve link info from hardware */
1105                 rc = bnxt_get_hwrm_link_config(bp, &new);
1106                 if (rc) {
1107                         new.link_speed = ETH_LINK_SPEED_100M;
1108                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1109                         PMD_DRV_LOG(ERR,
1110                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1111                         goto out;
1112                 }
1113
1114                 if (!wait_to_complete || new.link_status == exp_link_status)
1115                         break;
1116
1117                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1118         } while (cnt--);
1119
1120 out:
1121         /* Timed out or success */
1122         if (new.link_status != eth_dev->data->dev_link.link_status ||
1123         new.link_speed != eth_dev->data->dev_link.link_speed) {
1124                 rte_eth_linkstatus_set(eth_dev, &new);
1125
1126                 _rte_eth_dev_callback_process(eth_dev,
1127                                               RTE_ETH_EVENT_INTR_LSC,
1128                                               NULL);
1129
1130                 bnxt_print_link_info(eth_dev);
1131         }
1132
1133         return rc;
1134 }
1135
1136 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1137                                int wait_to_complete)
1138 {
1139         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1140 }
1141
1142 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1143 {
1144         struct bnxt *bp = eth_dev->data->dev_private;
1145         struct bnxt_vnic_info *vnic;
1146         uint32_t old_flags;
1147         int rc;
1148
1149         rc = is_bnxt_in_error(bp);
1150         if (rc)
1151                 return rc;
1152
1153         if (bp->vnic_info == NULL)
1154                 return 0;
1155
1156         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1157
1158         old_flags = vnic->flags;
1159         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1160         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1161         if (rc != 0)
1162                 vnic->flags = old_flags;
1163
1164         return rc;
1165 }
1166
1167 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1168 {
1169         struct bnxt *bp = eth_dev->data->dev_private;
1170         struct bnxt_vnic_info *vnic;
1171         uint32_t old_flags;
1172         int rc;
1173
1174         rc = is_bnxt_in_error(bp);
1175         if (rc)
1176                 return rc;
1177
1178         if (bp->vnic_info == NULL)
1179                 return 0;
1180
1181         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1182
1183         old_flags = vnic->flags;
1184         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1185         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1186         if (rc != 0)
1187                 vnic->flags = old_flags;
1188
1189         return rc;
1190 }
1191
1192 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1193 {
1194         struct bnxt *bp = eth_dev->data->dev_private;
1195         struct bnxt_vnic_info *vnic;
1196         uint32_t old_flags;
1197         int rc;
1198
1199         rc = is_bnxt_in_error(bp);
1200         if (rc)
1201                 return rc;
1202
1203         if (bp->vnic_info == NULL)
1204                 return 0;
1205
1206         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1207
1208         old_flags = vnic->flags;
1209         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1210         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1211         if (rc != 0)
1212                 vnic->flags = old_flags;
1213
1214         return rc;
1215 }
1216
1217 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1218 {
1219         struct bnxt *bp = eth_dev->data->dev_private;
1220         struct bnxt_vnic_info *vnic;
1221         uint32_t old_flags;
1222         int rc;
1223
1224         rc = is_bnxt_in_error(bp);
1225         if (rc)
1226                 return rc;
1227
1228         if (bp->vnic_info == NULL)
1229                 return 0;
1230
1231         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1232
1233         old_flags = vnic->flags;
1234         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1235         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1236         if (rc != 0)
1237                 vnic->flags = old_flags;
1238
1239         return rc;
1240 }
1241
1242 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1243 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1244 {
1245         if (qid >= bp->rx_nr_rings)
1246                 return NULL;
1247
1248         return bp->eth_dev->data->rx_queues[qid];
1249 }
1250
1251 /* Return rxq corresponding to a given rss table ring/group ID. */
1252 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1253 {
1254         struct bnxt_rx_queue *rxq;
1255         unsigned int i;
1256
1257         if (!BNXT_HAS_RING_GRPS(bp)) {
1258                 for (i = 0; i < bp->rx_nr_rings; i++) {
1259                         rxq = bp->eth_dev->data->rx_queues[i];
1260                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1261                                 return rxq->index;
1262                 }
1263         } else {
1264                 for (i = 0; i < bp->rx_nr_rings; i++) {
1265                         if (bp->grp_info[i].fw_grp_id == fwr)
1266                                 return i;
1267                 }
1268         }
1269
1270         return INVALID_HW_RING_ID;
1271 }
1272
1273 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1274                             struct rte_eth_rss_reta_entry64 *reta_conf,
1275                             uint16_t reta_size)
1276 {
1277         struct bnxt *bp = eth_dev->data->dev_private;
1278         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1279         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1280         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1281         uint16_t idx, sft;
1282         int i, rc;
1283
1284         rc = is_bnxt_in_error(bp);
1285         if (rc)
1286                 return rc;
1287
1288         if (!vnic->rss_table)
1289                 return -EINVAL;
1290
1291         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1292                 return -EINVAL;
1293
1294         if (reta_size != tbl_size) {
1295                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1296                         "(%d) must equal the size supported by the hardware "
1297                         "(%d)\n", reta_size, tbl_size);
1298                 return -EINVAL;
1299         }
1300
1301         for (i = 0; i < reta_size; i++) {
1302                 struct bnxt_rx_queue *rxq;
1303
1304                 idx = i / RTE_RETA_GROUP_SIZE;
1305                 sft = i % RTE_RETA_GROUP_SIZE;
1306
1307                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1308                         continue;
1309
1310                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1311                 if (!rxq) {
1312                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1313                         return -EINVAL;
1314                 }
1315
1316                 if (BNXT_CHIP_THOR(bp)) {
1317                         vnic->rss_table[i * 2] =
1318                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1319                         vnic->rss_table[i * 2 + 1] =
1320                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1321                 } else {
1322                         vnic->rss_table[i] =
1323                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1324                 }
1325         }
1326
1327         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1328         return 0;
1329 }
1330
1331 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1332                               struct rte_eth_rss_reta_entry64 *reta_conf,
1333                               uint16_t reta_size)
1334 {
1335         struct bnxt *bp = eth_dev->data->dev_private;
1336         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1337         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1338         uint16_t idx, sft, i;
1339         int rc;
1340
1341         rc = is_bnxt_in_error(bp);
1342         if (rc)
1343                 return rc;
1344
1345         /* Retrieve from the default VNIC */
1346         if (!vnic)
1347                 return -EINVAL;
1348         if (!vnic->rss_table)
1349                 return -EINVAL;
1350
1351         if (reta_size != tbl_size) {
1352                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1353                         "(%d) must equal the size supported by the hardware "
1354                         "(%d)\n", reta_size, tbl_size);
1355                 return -EINVAL;
1356         }
1357
1358         for (idx = 0, i = 0; i < reta_size; i++) {
1359                 idx = i / RTE_RETA_GROUP_SIZE;
1360                 sft = i % RTE_RETA_GROUP_SIZE;
1361
1362                 if (reta_conf[idx].mask & (1ULL << sft)) {
1363                         uint16_t qid;
1364
1365                         if (BNXT_CHIP_THOR(bp))
1366                                 qid = bnxt_rss_to_qid(bp,
1367                                                       vnic->rss_table[i * 2]);
1368                         else
1369                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1370
1371                         if (qid == INVALID_HW_RING_ID) {
1372                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1373                                 return -EINVAL;
1374                         }
1375                         reta_conf[idx].reta[sft] = qid;
1376                 }
1377         }
1378
1379         return 0;
1380 }
1381
1382 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1383                                    struct rte_eth_rss_conf *rss_conf)
1384 {
1385         struct bnxt *bp = eth_dev->data->dev_private;
1386         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1387         struct bnxt_vnic_info *vnic;
1388         int rc;
1389
1390         rc = is_bnxt_in_error(bp);
1391         if (rc)
1392                 return rc;
1393
1394         /*
1395          * If RSS enablement were different than dev_configure,
1396          * then return -EINVAL
1397          */
1398         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1399                 if (!rss_conf->rss_hf)
1400                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1401         } else {
1402                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1403                         return -EINVAL;
1404         }
1405
1406         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1407         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1408
1409         /* Update the default RSS VNIC(s) */
1410         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1411         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1412
1413         /*
1414          * If hashkey is not specified, use the previously configured
1415          * hashkey
1416          */
1417         if (!rss_conf->rss_key)
1418                 goto rss_config;
1419
1420         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1421                 PMD_DRV_LOG(ERR,
1422                             "Invalid hashkey length, should be 16 bytes\n");
1423                 return -EINVAL;
1424         }
1425         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1426
1427 rss_config:
1428         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1429         return 0;
1430 }
1431
1432 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1433                                      struct rte_eth_rss_conf *rss_conf)
1434 {
1435         struct bnxt *bp = eth_dev->data->dev_private;
1436         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1437         int len, rc;
1438         uint32_t hash_types;
1439
1440         rc = is_bnxt_in_error(bp);
1441         if (rc)
1442                 return rc;
1443
1444         /* RSS configuration is the same for all VNICs */
1445         if (vnic && vnic->rss_hash_key) {
1446                 if (rss_conf->rss_key) {
1447                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1448                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1449                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1450                 }
1451
1452                 hash_types = vnic->hash_type;
1453                 rss_conf->rss_hf = 0;
1454                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1455                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1456                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1457                 }
1458                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1459                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1460                         hash_types &=
1461                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1462                 }
1463                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1464                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1465                         hash_types &=
1466                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1467                 }
1468                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1469                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1470                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1471                 }
1472                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1473                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1474                         hash_types &=
1475                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1476                 }
1477                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1478                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1479                         hash_types &=
1480                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1481                 }
1482                 if (hash_types) {
1483                         PMD_DRV_LOG(ERR,
1484                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1485                                 vnic->hash_type);
1486                         return -ENOTSUP;
1487                 }
1488         } else {
1489                 rss_conf->rss_hf = 0;
1490         }
1491         return 0;
1492 }
1493
1494 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1495                                struct rte_eth_fc_conf *fc_conf)
1496 {
1497         struct bnxt *bp = dev->data->dev_private;
1498         struct rte_eth_link link_info;
1499         int rc;
1500
1501         rc = is_bnxt_in_error(bp);
1502         if (rc)
1503                 return rc;
1504
1505         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1506         if (rc)
1507                 return rc;
1508
1509         memset(fc_conf, 0, sizeof(*fc_conf));
1510         if (bp->link_info.auto_pause)
1511                 fc_conf->autoneg = 1;
1512         switch (bp->link_info.pause) {
1513         case 0:
1514                 fc_conf->mode = RTE_FC_NONE;
1515                 break;
1516         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1517                 fc_conf->mode = RTE_FC_TX_PAUSE;
1518                 break;
1519         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1520                 fc_conf->mode = RTE_FC_RX_PAUSE;
1521                 break;
1522         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1523                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1524                 fc_conf->mode = RTE_FC_FULL;
1525                 break;
1526         }
1527         return 0;
1528 }
1529
1530 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1531                                struct rte_eth_fc_conf *fc_conf)
1532 {
1533         struct bnxt *bp = dev->data->dev_private;
1534         int rc;
1535
1536         rc = is_bnxt_in_error(bp);
1537         if (rc)
1538                 return rc;
1539
1540         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1541                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1542                 return -ENOTSUP;
1543         }
1544
1545         switch (fc_conf->mode) {
1546         case RTE_FC_NONE:
1547                 bp->link_info.auto_pause = 0;
1548                 bp->link_info.force_pause = 0;
1549                 break;
1550         case RTE_FC_RX_PAUSE:
1551                 if (fc_conf->autoneg) {
1552                         bp->link_info.auto_pause =
1553                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1554                         bp->link_info.force_pause = 0;
1555                 } else {
1556                         bp->link_info.auto_pause = 0;
1557                         bp->link_info.force_pause =
1558                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1559                 }
1560                 break;
1561         case RTE_FC_TX_PAUSE:
1562                 if (fc_conf->autoneg) {
1563                         bp->link_info.auto_pause =
1564                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1565                         bp->link_info.force_pause = 0;
1566                 } else {
1567                         bp->link_info.auto_pause = 0;
1568                         bp->link_info.force_pause =
1569                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1570                 }
1571                 break;
1572         case RTE_FC_FULL:
1573                 if (fc_conf->autoneg) {
1574                         bp->link_info.auto_pause =
1575                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1576                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1577                         bp->link_info.force_pause = 0;
1578                 } else {
1579                         bp->link_info.auto_pause = 0;
1580                         bp->link_info.force_pause =
1581                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1582                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1583                 }
1584                 break;
1585         }
1586         return bnxt_set_hwrm_link_config(bp, true);
1587 }
1588
1589 /* Add UDP tunneling port */
1590 static int
1591 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1592                          struct rte_eth_udp_tunnel *udp_tunnel)
1593 {
1594         struct bnxt *bp = eth_dev->data->dev_private;
1595         uint16_t tunnel_type = 0;
1596         int rc = 0;
1597
1598         rc = is_bnxt_in_error(bp);
1599         if (rc)
1600                 return rc;
1601
1602         switch (udp_tunnel->prot_type) {
1603         case RTE_TUNNEL_TYPE_VXLAN:
1604                 if (bp->vxlan_port_cnt) {
1605                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1606                                 udp_tunnel->udp_port);
1607                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1608                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1609                                 return -ENOSPC;
1610                         }
1611                         bp->vxlan_port_cnt++;
1612                         return 0;
1613                 }
1614                 tunnel_type =
1615                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1616                 bp->vxlan_port_cnt++;
1617                 break;
1618         case RTE_TUNNEL_TYPE_GENEVE:
1619                 if (bp->geneve_port_cnt) {
1620                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1621                                 udp_tunnel->udp_port);
1622                         if (bp->geneve_port != udp_tunnel->udp_port) {
1623                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1624                                 return -ENOSPC;
1625                         }
1626                         bp->geneve_port_cnt++;
1627                         return 0;
1628                 }
1629                 tunnel_type =
1630                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1631                 bp->geneve_port_cnt++;
1632                 break;
1633         default:
1634                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1635                 return -ENOTSUP;
1636         }
1637         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1638                                              tunnel_type);
1639         return rc;
1640 }
1641
1642 static int
1643 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1644                          struct rte_eth_udp_tunnel *udp_tunnel)
1645 {
1646         struct bnxt *bp = eth_dev->data->dev_private;
1647         uint16_t tunnel_type = 0;
1648         uint16_t port = 0;
1649         int rc = 0;
1650
1651         rc = is_bnxt_in_error(bp);
1652         if (rc)
1653                 return rc;
1654
1655         switch (udp_tunnel->prot_type) {
1656         case RTE_TUNNEL_TYPE_VXLAN:
1657                 if (!bp->vxlan_port_cnt) {
1658                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1659                         return -EINVAL;
1660                 }
1661                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1662                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1663                                 udp_tunnel->udp_port, bp->vxlan_port);
1664                         return -EINVAL;
1665                 }
1666                 if (--bp->vxlan_port_cnt)
1667                         return 0;
1668
1669                 tunnel_type =
1670                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1671                 port = bp->vxlan_fw_dst_port_id;
1672                 break;
1673         case RTE_TUNNEL_TYPE_GENEVE:
1674                 if (!bp->geneve_port_cnt) {
1675                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1676                         return -EINVAL;
1677                 }
1678                 if (bp->geneve_port != udp_tunnel->udp_port) {
1679                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1680                                 udp_tunnel->udp_port, bp->geneve_port);
1681                         return -EINVAL;
1682                 }
1683                 if (--bp->geneve_port_cnt)
1684                         return 0;
1685
1686                 tunnel_type =
1687                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1688                 port = bp->geneve_fw_dst_port_id;
1689                 break;
1690         default:
1691                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1692                 return -ENOTSUP;
1693         }
1694
1695         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1696         if (!rc) {
1697                 if (tunnel_type ==
1698                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1699                         bp->vxlan_port = 0;
1700                 if (tunnel_type ==
1701                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1702                         bp->geneve_port = 0;
1703         }
1704         return rc;
1705 }
1706
1707 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1708 {
1709         struct bnxt_filter_info *filter;
1710         struct bnxt_vnic_info *vnic;
1711         int rc = 0;
1712         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1713
1714         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1715         filter = STAILQ_FIRST(&vnic->filter);
1716         while (filter) {
1717                 /* Search for this matching MAC+VLAN filter */
1718                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1719                         /* Delete the filter */
1720                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1721                         if (rc)
1722                                 return rc;
1723                         STAILQ_REMOVE(&vnic->filter, filter,
1724                                       bnxt_filter_info, next);
1725                         bnxt_free_filter(bp, filter);
1726                         PMD_DRV_LOG(INFO,
1727                                     "Deleted vlan filter for %d\n",
1728                                     vlan_id);
1729                         return 0;
1730                 }
1731                 filter = STAILQ_NEXT(filter, next);
1732         }
1733         return -ENOENT;
1734 }
1735
1736 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1737 {
1738         struct bnxt_filter_info *filter;
1739         struct bnxt_vnic_info *vnic;
1740         int rc = 0;
1741         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1742                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1743         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1744
1745         /* Implementation notes on the use of VNIC in this command:
1746          *
1747          * By default, these filters belong to default vnic for the function.
1748          * Once these filters are set up, only destination VNIC can be modified.
1749          * If the destination VNIC is not specified in this command,
1750          * then the HWRM shall only create an l2 context id.
1751          */
1752
1753         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1754         filter = STAILQ_FIRST(&vnic->filter);
1755         /* Check if the VLAN has already been added */
1756         while (filter) {
1757                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1758                         return -EEXIST;
1759
1760                 filter = STAILQ_NEXT(filter, next);
1761         }
1762
1763         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1764          * command to create MAC+VLAN filter with the right flags, enables set.
1765          */
1766         filter = bnxt_alloc_filter(bp);
1767         if (!filter) {
1768                 PMD_DRV_LOG(ERR,
1769                             "MAC/VLAN filter alloc failed\n");
1770                 return -ENOMEM;
1771         }
1772         /* MAC + VLAN ID filter */
1773         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1774          * untagged packets are received
1775          *
1776          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1777          * packets and only the programmed vlan's packets are received
1778          */
1779         filter->l2_ivlan = vlan_id;
1780         filter->l2_ivlan_mask = 0x0FFF;
1781         filter->enables |= en;
1782         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1783
1784         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1785         if (rc) {
1786                 /* Free the newly allocated filter as we were
1787                  * not able to create the filter in hardware.
1788                  */
1789                 bnxt_free_filter(bp, filter);
1790                 return rc;
1791         }
1792
1793         filter->mac_index = 0;
1794         /* Add this new filter to the list */
1795         if (vlan_id == 0)
1796                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1797         else
1798                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1799
1800         PMD_DRV_LOG(INFO,
1801                     "Added Vlan filter for %d\n", vlan_id);
1802         return rc;
1803 }
1804
1805 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1806                 uint16_t vlan_id, int on)
1807 {
1808         struct bnxt *bp = eth_dev->data->dev_private;
1809         int rc;
1810
1811         rc = is_bnxt_in_error(bp);
1812         if (rc)
1813                 return rc;
1814
1815         /* These operations apply to ALL existing MAC/VLAN filters */
1816         if (on)
1817                 return bnxt_add_vlan_filter(bp, vlan_id);
1818         else
1819                 return bnxt_del_vlan_filter(bp, vlan_id);
1820 }
1821
1822 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1823                                     struct bnxt_vnic_info *vnic)
1824 {
1825         struct bnxt_filter_info *filter;
1826         int rc;
1827
1828         filter = STAILQ_FIRST(&vnic->filter);
1829         while (filter) {
1830                 if (filter->mac_index == 0 &&
1831                     !memcmp(filter->l2_addr, bp->mac_addr,
1832                             RTE_ETHER_ADDR_LEN)) {
1833                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1834                         if (!rc) {
1835                                 STAILQ_REMOVE(&vnic->filter, filter,
1836                                               bnxt_filter_info, next);
1837                                 bnxt_free_filter(bp, filter);
1838                         }
1839                         return rc;
1840                 }
1841                 filter = STAILQ_NEXT(filter, next);
1842         }
1843         return 0;
1844 }
1845
1846 static int
1847 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1848 {
1849         struct bnxt *bp = dev->data->dev_private;
1850         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1851         struct bnxt_vnic_info *vnic;
1852         unsigned int i;
1853         int rc;
1854
1855         rc = is_bnxt_in_error(bp);
1856         if (rc)
1857                 return rc;
1858
1859         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1860         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1861                 /* Remove any VLAN filters programmed */
1862                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1863                         bnxt_del_vlan_filter(bp, i);
1864
1865                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1866                 if (rc)
1867                         return rc;
1868         } else {
1869                 /* Default filter will allow packets that match the
1870                  * dest mac. So, it has to be deleted, otherwise, we
1871                  * will endup receiving vlan packets for which the
1872                  * filter is not programmed, when hw-vlan-filter
1873                  * configuration is ON
1874                  */
1875                 bnxt_del_dflt_mac_filter(bp, vnic);
1876                 /* This filter will allow only untagged packets */
1877                 bnxt_add_vlan_filter(bp, 0);
1878         }
1879         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1880                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1881
1882         if (mask & ETH_VLAN_STRIP_MASK) {
1883                 /* Enable or disable VLAN stripping */
1884                 for (i = 0; i < bp->nr_vnics; i++) {
1885                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1886                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1887                                 vnic->vlan_strip = true;
1888                         else
1889                                 vnic->vlan_strip = false;
1890                         bnxt_hwrm_vnic_cfg(bp, vnic);
1891                 }
1892                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1893                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1894         }
1895
1896         if (mask & ETH_VLAN_EXTEND_MASK) {
1897                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1898                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1899                 else
1900                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1901         }
1902
1903         return 0;
1904 }
1905
1906 static int
1907 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1908                       uint16_t tpid)
1909 {
1910         struct bnxt *bp = dev->data->dev_private;
1911         int qinq = dev->data->dev_conf.rxmode.offloads &
1912                    DEV_RX_OFFLOAD_VLAN_EXTEND;
1913
1914         if (vlan_type != ETH_VLAN_TYPE_INNER &&
1915             vlan_type != ETH_VLAN_TYPE_OUTER) {
1916                 PMD_DRV_LOG(ERR,
1917                             "Unsupported vlan type.");
1918                 return -EINVAL;
1919         }
1920         if (!qinq) {
1921                 PMD_DRV_LOG(ERR,
1922                             "QinQ not enabled. Needs to be ON as we can "
1923                             "accelerate only outer vlan\n");
1924                 return -EINVAL;
1925         }
1926
1927         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1928                 switch (tpid) {
1929                 case RTE_ETHER_TYPE_QINQ:
1930                         bp->outer_tpid_bd =
1931                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1932                                 break;
1933                 case RTE_ETHER_TYPE_VLAN:
1934                         bp->outer_tpid_bd =
1935                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1936                                 break;
1937                 case 0x9100:
1938                         bp->outer_tpid_bd =
1939                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1940                                 break;
1941                 case 0x9200:
1942                         bp->outer_tpid_bd =
1943                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1944                                 break;
1945                 case 0x9300:
1946                         bp->outer_tpid_bd =
1947                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1948                                 break;
1949                 default:
1950                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1951                         return -EINVAL;
1952                 }
1953                 bp->outer_tpid_bd |= tpid;
1954                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1955         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1956                 PMD_DRV_LOG(ERR,
1957                             "Can accelerate only outer vlan in QinQ\n");
1958                 return -EINVAL;
1959         }
1960
1961         return 0;
1962 }
1963
1964 static int
1965 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1966                              struct rte_ether_addr *addr)
1967 {
1968         struct bnxt *bp = dev->data->dev_private;
1969         /* Default Filter is tied to VNIC 0 */
1970         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1971         struct bnxt_filter_info *filter;
1972         int rc;
1973
1974         rc = is_bnxt_in_error(bp);
1975         if (rc)
1976                 return rc;
1977
1978         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1979                 return -EPERM;
1980
1981         if (rte_is_zero_ether_addr(addr))
1982                 return -EINVAL;
1983
1984         STAILQ_FOREACH(filter, &vnic->filter, next) {
1985                 /* Default Filter is at Index 0 */
1986                 if (filter->mac_index != 0)
1987                         continue;
1988
1989                 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
1990                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1991                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
1992                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1993                 filter->enables |=
1994                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1995                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1996
1997                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1998                 if (rc) {
1999                         memcpy(filter->l2_addr, bp->mac_addr,
2000                                RTE_ETHER_ADDR_LEN);
2001                         return rc;
2002                 }
2003
2004                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2005                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2006                 return 0;
2007         }
2008
2009         return 0;
2010 }
2011
2012 static int
2013 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2014                           struct rte_ether_addr *mc_addr_set,
2015                           uint32_t nb_mc_addr)
2016 {
2017         struct bnxt *bp = eth_dev->data->dev_private;
2018         char *mc_addr_list = (char *)mc_addr_set;
2019         struct bnxt_vnic_info *vnic;
2020         uint32_t off = 0, i = 0;
2021         int rc;
2022
2023         rc = is_bnxt_in_error(bp);
2024         if (rc)
2025                 return rc;
2026
2027         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2028
2029         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2030                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2031                 goto allmulti;
2032         }
2033
2034         /* TODO Check for Duplicate mcast addresses */
2035         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2036         for (i = 0; i < nb_mc_addr; i++) {
2037                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2038                         RTE_ETHER_ADDR_LEN);
2039                 off += RTE_ETHER_ADDR_LEN;
2040         }
2041
2042         vnic->mc_addr_cnt = i;
2043         if (vnic->mc_addr_cnt)
2044                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2045         else
2046                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2047
2048 allmulti:
2049         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2050 }
2051
2052 static int
2053 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2054 {
2055         struct bnxt *bp = dev->data->dev_private;
2056         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2057         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2058         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2059         int ret;
2060
2061         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2062                         fw_major, fw_minor, fw_updt);
2063
2064         ret += 1; /* add the size of '\0' */
2065         if (fw_size < (uint32_t)ret)
2066                 return ret;
2067         else
2068                 return 0;
2069 }
2070
2071 static void
2072 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2073         struct rte_eth_rxq_info *qinfo)
2074 {
2075         struct bnxt *bp = dev->data->dev_private;
2076         struct bnxt_rx_queue *rxq;
2077
2078         if (is_bnxt_in_error(bp))
2079                 return;
2080
2081         rxq = dev->data->rx_queues[queue_id];
2082
2083         qinfo->mp = rxq->mb_pool;
2084         qinfo->scattered_rx = dev->data->scattered_rx;
2085         qinfo->nb_desc = rxq->nb_rx_desc;
2086
2087         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2088         qinfo->conf.rx_drop_en = 0;
2089         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2090 }
2091
2092 static void
2093 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2094         struct rte_eth_txq_info *qinfo)
2095 {
2096         struct bnxt *bp = dev->data->dev_private;
2097         struct bnxt_tx_queue *txq;
2098
2099         if (is_bnxt_in_error(bp))
2100                 return;
2101
2102         txq = dev->data->tx_queues[queue_id];
2103
2104         qinfo->nb_desc = txq->nb_tx_desc;
2105
2106         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2107         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2108         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2109
2110         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2111         qinfo->conf.tx_rs_thresh = 0;
2112         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2113 }
2114
2115 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2116 {
2117         struct bnxt *bp = eth_dev->data->dev_private;
2118         uint32_t new_pkt_size;
2119         uint32_t rc = 0;
2120         uint32_t i;
2121
2122         rc = is_bnxt_in_error(bp);
2123         if (rc)
2124                 return rc;
2125
2126         /* Exit if receive queues are not configured yet */
2127         if (!eth_dev->data->nb_rx_queues)
2128                 return rc;
2129
2130         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2131                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2132
2133 #ifdef RTE_ARCH_X86
2134         /*
2135          * If vector-mode tx/rx is active, disallow any MTU change that would
2136          * require scattered receive support.
2137          */
2138         if (eth_dev->data->dev_started &&
2139             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2140              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2141             (new_pkt_size >
2142              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2143                 PMD_DRV_LOG(ERR,
2144                             "MTU change would require scattered rx support. ");
2145                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2146                 return -EINVAL;
2147         }
2148 #endif
2149
2150         if (new_mtu > RTE_ETHER_MTU) {
2151                 bp->flags |= BNXT_FLAG_JUMBO;
2152                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2153                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2154         } else {
2155                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2156                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2157                 bp->flags &= ~BNXT_FLAG_JUMBO;
2158         }
2159
2160         /* Is there a change in mtu setting? */
2161         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2162                 return rc;
2163
2164         for (i = 0; i < bp->nr_vnics; i++) {
2165                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2166                 uint16_t size = 0;
2167
2168                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2169                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2170                 if (rc)
2171                         break;
2172
2173                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2174                 size -= RTE_PKTMBUF_HEADROOM;
2175
2176                 if (size < new_mtu) {
2177                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2178                         if (rc)
2179                                 return rc;
2180                 }
2181         }
2182
2183         if (!rc)
2184                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2185
2186         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2187
2188         return rc;
2189 }
2190
2191 static int
2192 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2193 {
2194         struct bnxt *bp = dev->data->dev_private;
2195         uint16_t vlan = bp->vlan;
2196         int rc;
2197
2198         rc = is_bnxt_in_error(bp);
2199         if (rc)
2200                 return rc;
2201
2202         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2203                 PMD_DRV_LOG(ERR,
2204                         "PVID cannot be modified for this function\n");
2205                 return -ENOTSUP;
2206         }
2207         bp->vlan = on ? pvid : 0;
2208
2209         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2210         if (rc)
2211                 bp->vlan = vlan;
2212         return rc;
2213 }
2214
2215 static int
2216 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2217 {
2218         struct bnxt *bp = dev->data->dev_private;
2219         int rc;
2220
2221         rc = is_bnxt_in_error(bp);
2222         if (rc)
2223                 return rc;
2224
2225         return bnxt_hwrm_port_led_cfg(bp, true);
2226 }
2227
2228 static int
2229 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2230 {
2231         struct bnxt *bp = dev->data->dev_private;
2232         int rc;
2233
2234         rc = is_bnxt_in_error(bp);
2235         if (rc)
2236                 return rc;
2237
2238         return bnxt_hwrm_port_led_cfg(bp, false);
2239 }
2240
2241 static uint32_t
2242 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2243 {
2244         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2245         uint32_t desc = 0, raw_cons = 0, cons;
2246         struct bnxt_cp_ring_info *cpr;
2247         struct bnxt_rx_queue *rxq;
2248         struct rx_pkt_cmpl *rxcmp;
2249         int rc;
2250
2251         rc = is_bnxt_in_error(bp);
2252         if (rc)
2253                 return rc;
2254
2255         rxq = dev->data->rx_queues[rx_queue_id];
2256         cpr = rxq->cp_ring;
2257         raw_cons = cpr->cp_raw_cons;
2258
2259         while (1) {
2260                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2261                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2262                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2263
2264                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2265                         break;
2266                 } else {
2267                         raw_cons++;
2268                         desc++;
2269                 }
2270         }
2271
2272         return desc;
2273 }
2274
2275 static int
2276 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2277 {
2278         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2279         struct bnxt_rx_ring_info *rxr;
2280         struct bnxt_cp_ring_info *cpr;
2281         struct bnxt_sw_rx_bd *rx_buf;
2282         struct rx_pkt_cmpl *rxcmp;
2283         uint32_t cons, cp_cons;
2284         int rc;
2285
2286         if (!rxq)
2287                 return -EINVAL;
2288
2289         rc = is_bnxt_in_error(rxq->bp);
2290         if (rc)
2291                 return rc;
2292
2293         cpr = rxq->cp_ring;
2294         rxr = rxq->rx_ring;
2295
2296         if (offset >= rxq->nb_rx_desc)
2297                 return -EINVAL;
2298
2299         cons = RING_CMP(cpr->cp_ring_struct, offset);
2300         cp_cons = cpr->cp_raw_cons;
2301         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2302
2303         if (cons > cp_cons) {
2304                 if (CMPL_VALID(rxcmp, cpr->valid))
2305                         return RTE_ETH_RX_DESC_DONE;
2306         } else {
2307                 if (CMPL_VALID(rxcmp, !cpr->valid))
2308                         return RTE_ETH_RX_DESC_DONE;
2309         }
2310         rx_buf = &rxr->rx_buf_ring[cons];
2311         if (rx_buf->mbuf == NULL)
2312                 return RTE_ETH_RX_DESC_UNAVAIL;
2313
2314
2315         return RTE_ETH_RX_DESC_AVAIL;
2316 }
2317
2318 static int
2319 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2320 {
2321         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2322         struct bnxt_tx_ring_info *txr;
2323         struct bnxt_cp_ring_info *cpr;
2324         struct bnxt_sw_tx_bd *tx_buf;
2325         struct tx_pkt_cmpl *txcmp;
2326         uint32_t cons, cp_cons;
2327         int rc;
2328
2329         if (!txq)
2330                 return -EINVAL;
2331
2332         rc = is_bnxt_in_error(txq->bp);
2333         if (rc)
2334                 return rc;
2335
2336         cpr = txq->cp_ring;
2337         txr = txq->tx_ring;
2338
2339         if (offset >= txq->nb_tx_desc)
2340                 return -EINVAL;
2341
2342         cons = RING_CMP(cpr->cp_ring_struct, offset);
2343         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2344         cp_cons = cpr->cp_raw_cons;
2345
2346         if (cons > cp_cons) {
2347                 if (CMPL_VALID(txcmp, cpr->valid))
2348                         return RTE_ETH_TX_DESC_UNAVAIL;
2349         } else {
2350                 if (CMPL_VALID(txcmp, !cpr->valid))
2351                         return RTE_ETH_TX_DESC_UNAVAIL;
2352         }
2353         tx_buf = &txr->tx_buf_ring[cons];
2354         if (tx_buf->mbuf == NULL)
2355                 return RTE_ETH_TX_DESC_DONE;
2356
2357         return RTE_ETH_TX_DESC_FULL;
2358 }
2359
2360 static struct bnxt_filter_info *
2361 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2362                                 struct rte_eth_ethertype_filter *efilter,
2363                                 struct bnxt_vnic_info *vnic0,
2364                                 struct bnxt_vnic_info *vnic,
2365                                 int *ret)
2366 {
2367         struct bnxt_filter_info *mfilter = NULL;
2368         int match = 0;
2369         *ret = 0;
2370
2371         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2372                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2373                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2374                         " ethertype filter.", efilter->ether_type);
2375                 *ret = -EINVAL;
2376                 goto exit;
2377         }
2378         if (efilter->queue >= bp->rx_nr_rings) {
2379                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2380                 *ret = -EINVAL;
2381                 goto exit;
2382         }
2383
2384         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2385         vnic = &bp->vnic_info[efilter->queue];
2386         if (vnic == NULL) {
2387                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2388                 *ret = -EINVAL;
2389                 goto exit;
2390         }
2391
2392         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2393                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2394                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2395                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2396                              mfilter->flags ==
2397                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2398                              mfilter->ethertype == efilter->ether_type)) {
2399                                 match = 1;
2400                                 break;
2401                         }
2402                 }
2403         } else {
2404                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2405                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2406                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2407                              mfilter->ethertype == efilter->ether_type &&
2408                              mfilter->flags ==
2409                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2410                                 match = 1;
2411                                 break;
2412                         }
2413         }
2414
2415         if (match)
2416                 *ret = -EEXIST;
2417
2418 exit:
2419         return mfilter;
2420 }
2421
2422 static int
2423 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2424                         enum rte_filter_op filter_op,
2425                         void *arg)
2426 {
2427         struct bnxt *bp = dev->data->dev_private;
2428         struct rte_eth_ethertype_filter *efilter =
2429                         (struct rte_eth_ethertype_filter *)arg;
2430         struct bnxt_filter_info *bfilter, *filter1;
2431         struct bnxt_vnic_info *vnic, *vnic0;
2432         int ret;
2433
2434         if (filter_op == RTE_ETH_FILTER_NOP)
2435                 return 0;
2436
2437         if (arg == NULL) {
2438                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2439                             filter_op);
2440                 return -EINVAL;
2441         }
2442
2443         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2444         vnic = &bp->vnic_info[efilter->queue];
2445
2446         switch (filter_op) {
2447         case RTE_ETH_FILTER_ADD:
2448                 bnxt_match_and_validate_ether_filter(bp, efilter,
2449                                                         vnic0, vnic, &ret);
2450                 if (ret < 0)
2451                         return ret;
2452
2453                 bfilter = bnxt_get_unused_filter(bp);
2454                 if (bfilter == NULL) {
2455                         PMD_DRV_LOG(ERR,
2456                                 "Not enough resources for a new filter.\n");
2457                         return -ENOMEM;
2458                 }
2459                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2460                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2461                        RTE_ETHER_ADDR_LEN);
2462                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2463                        RTE_ETHER_ADDR_LEN);
2464                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2465                 bfilter->ethertype = efilter->ether_type;
2466                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2467
2468                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2469                 if (filter1 == NULL) {
2470                         ret = -EINVAL;
2471                         goto cleanup;
2472                 }
2473                 bfilter->enables |=
2474                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2475                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2476
2477                 bfilter->dst_id = vnic->fw_vnic_id;
2478
2479                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2480                         bfilter->flags =
2481                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2482                 }
2483
2484                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2485                 if (ret)
2486                         goto cleanup;
2487                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2488                 break;
2489         case RTE_ETH_FILTER_DELETE:
2490                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2491                                                         vnic0, vnic, &ret);
2492                 if (ret == -EEXIST) {
2493                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2494
2495                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2496                                       next);
2497                         bnxt_free_filter(bp, filter1);
2498                 } else if (ret == 0) {
2499                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2500                 }
2501                 break;
2502         default:
2503                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2504                 ret = -EINVAL;
2505                 goto error;
2506         }
2507         return ret;
2508 cleanup:
2509         bnxt_free_filter(bp, bfilter);
2510 error:
2511         return ret;
2512 }
2513
2514 static inline int
2515 parse_ntuple_filter(struct bnxt *bp,
2516                     struct rte_eth_ntuple_filter *nfilter,
2517                     struct bnxt_filter_info *bfilter)
2518 {
2519         uint32_t en = 0;
2520
2521         if (nfilter->queue >= bp->rx_nr_rings) {
2522                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2523                 return -EINVAL;
2524         }
2525
2526         switch (nfilter->dst_port_mask) {
2527         case UINT16_MAX:
2528                 bfilter->dst_port_mask = -1;
2529                 bfilter->dst_port = nfilter->dst_port;
2530                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2531                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2532                 break;
2533         default:
2534                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2535                 return -EINVAL;
2536         }
2537
2538         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2539         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2540
2541         switch (nfilter->proto_mask) {
2542         case UINT8_MAX:
2543                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2544                         bfilter->ip_protocol = 17;
2545                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2546                         bfilter->ip_protocol = 6;
2547                 else
2548                         return -EINVAL;
2549                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2550                 break;
2551         default:
2552                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2553                 return -EINVAL;
2554         }
2555
2556         switch (nfilter->dst_ip_mask) {
2557         case UINT32_MAX:
2558                 bfilter->dst_ipaddr_mask[0] = -1;
2559                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2560                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2561                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2562                 break;
2563         default:
2564                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2565                 return -EINVAL;
2566         }
2567
2568         switch (nfilter->src_ip_mask) {
2569         case UINT32_MAX:
2570                 bfilter->src_ipaddr_mask[0] = -1;
2571                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2572                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2573                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2574                 break;
2575         default:
2576                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2577                 return -EINVAL;
2578         }
2579
2580         switch (nfilter->src_port_mask) {
2581         case UINT16_MAX:
2582                 bfilter->src_port_mask = -1;
2583                 bfilter->src_port = nfilter->src_port;
2584                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2585                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2586                 break;
2587         default:
2588                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2589                 return -EINVAL;
2590         }
2591
2592         bfilter->enables = en;
2593         return 0;
2594 }
2595
2596 static struct bnxt_filter_info*
2597 bnxt_match_ntuple_filter(struct bnxt *bp,
2598                          struct bnxt_filter_info *bfilter,
2599                          struct bnxt_vnic_info **mvnic)
2600 {
2601         struct bnxt_filter_info *mfilter = NULL;
2602         int i;
2603
2604         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2605                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2606                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2607                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2608                             bfilter->src_ipaddr_mask[0] ==
2609                             mfilter->src_ipaddr_mask[0] &&
2610                             bfilter->src_port == mfilter->src_port &&
2611                             bfilter->src_port_mask == mfilter->src_port_mask &&
2612                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2613                             bfilter->dst_ipaddr_mask[0] ==
2614                             mfilter->dst_ipaddr_mask[0] &&
2615                             bfilter->dst_port == mfilter->dst_port &&
2616                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2617                             bfilter->flags == mfilter->flags &&
2618                             bfilter->enables == mfilter->enables) {
2619                                 if (mvnic)
2620                                         *mvnic = vnic;
2621                                 return mfilter;
2622                         }
2623                 }
2624         }
2625         return NULL;
2626 }
2627
2628 static int
2629 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2630                        struct rte_eth_ntuple_filter *nfilter,
2631                        enum rte_filter_op filter_op)
2632 {
2633         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2634         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2635         int ret;
2636
2637         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2638                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2639                 return -EINVAL;
2640         }
2641
2642         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2643                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2644                 return -EINVAL;
2645         }
2646
2647         bfilter = bnxt_get_unused_filter(bp);
2648         if (bfilter == NULL) {
2649                 PMD_DRV_LOG(ERR,
2650                         "Not enough resources for a new filter.\n");
2651                 return -ENOMEM;
2652         }
2653         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2654         if (ret < 0)
2655                 goto free_filter;
2656
2657         vnic = &bp->vnic_info[nfilter->queue];
2658         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2659         filter1 = STAILQ_FIRST(&vnic0->filter);
2660         if (filter1 == NULL) {
2661                 ret = -EINVAL;
2662                 goto free_filter;
2663         }
2664
2665         bfilter->dst_id = vnic->fw_vnic_id;
2666         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2667         bfilter->enables |=
2668                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2669         bfilter->ethertype = 0x800;
2670         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2671
2672         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2673
2674         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2675             bfilter->dst_id == mfilter->dst_id) {
2676                 PMD_DRV_LOG(ERR, "filter exists.\n");
2677                 ret = -EEXIST;
2678                 goto free_filter;
2679         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2680                    bfilter->dst_id != mfilter->dst_id) {
2681                 mfilter->dst_id = vnic->fw_vnic_id;
2682                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2683                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2684                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2685                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2686                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2687                 goto free_filter;
2688         }
2689         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2690                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2691                 ret = -ENOENT;
2692                 goto free_filter;
2693         }
2694
2695         if (filter_op == RTE_ETH_FILTER_ADD) {
2696                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2697                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2698                 if (ret)
2699                         goto free_filter;
2700                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2701         } else {
2702                 if (mfilter == NULL) {
2703                         /* This should not happen. But for Coverity! */
2704                         ret = -ENOENT;
2705                         goto free_filter;
2706                 }
2707                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2708
2709                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2710                 bnxt_free_filter(bp, mfilter);
2711                 bnxt_free_filter(bp, bfilter);
2712         }
2713
2714         return 0;
2715 free_filter:
2716         bnxt_free_filter(bp, bfilter);
2717         return ret;
2718 }
2719
2720 static int
2721 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2722                         enum rte_filter_op filter_op,
2723                         void *arg)
2724 {
2725         struct bnxt *bp = dev->data->dev_private;
2726         int ret;
2727
2728         if (filter_op == RTE_ETH_FILTER_NOP)
2729                 return 0;
2730
2731         if (arg == NULL) {
2732                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2733                             filter_op);
2734                 return -EINVAL;
2735         }
2736
2737         switch (filter_op) {
2738         case RTE_ETH_FILTER_ADD:
2739                 ret = bnxt_cfg_ntuple_filter(bp,
2740                         (struct rte_eth_ntuple_filter *)arg,
2741                         filter_op);
2742                 break;
2743         case RTE_ETH_FILTER_DELETE:
2744                 ret = bnxt_cfg_ntuple_filter(bp,
2745                         (struct rte_eth_ntuple_filter *)arg,
2746                         filter_op);
2747                 break;
2748         default:
2749                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2750                 ret = -EINVAL;
2751                 break;
2752         }
2753         return ret;
2754 }
2755
2756 static int
2757 bnxt_parse_fdir_filter(struct bnxt *bp,
2758                        struct rte_eth_fdir_filter *fdir,
2759                        struct bnxt_filter_info *filter)
2760 {
2761         enum rte_fdir_mode fdir_mode =
2762                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2763         struct bnxt_vnic_info *vnic0, *vnic;
2764         struct bnxt_filter_info *filter1;
2765         uint32_t en = 0;
2766         int i;
2767
2768         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2769                 return -EINVAL;
2770
2771         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2772         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2773
2774         switch (fdir->input.flow_type) {
2775         case RTE_ETH_FLOW_IPV4:
2776         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2777                 /* FALLTHROUGH */
2778                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2779                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2780                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2781                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2782                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2783                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2784                 filter->ip_addr_type =
2785                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2786                 filter->src_ipaddr_mask[0] = 0xffffffff;
2787                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2788                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2789                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2790                 filter->ethertype = 0x800;
2791                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2792                 break;
2793         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2794                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2795                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2796                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2797                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2798                 filter->dst_port_mask = 0xffff;
2799                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2800                 filter->src_port_mask = 0xffff;
2801                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2802                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2803                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2804                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2805                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2806                 filter->ip_protocol = 6;
2807                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2808                 filter->ip_addr_type =
2809                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2810                 filter->src_ipaddr_mask[0] = 0xffffffff;
2811                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2812                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2813                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2814                 filter->ethertype = 0x800;
2815                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2816                 break;
2817         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2818                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2819                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2820                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2821                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2822                 filter->dst_port_mask = 0xffff;
2823                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2824                 filter->src_port_mask = 0xffff;
2825                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2826                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2827                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2828                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2829                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2830                 filter->ip_protocol = 17;
2831                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2832                 filter->ip_addr_type =
2833                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2834                 filter->src_ipaddr_mask[0] = 0xffffffff;
2835                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2836                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2837                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2838                 filter->ethertype = 0x800;
2839                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2840                 break;
2841         case RTE_ETH_FLOW_IPV6:
2842         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2843                 /* FALLTHROUGH */
2844                 filter->ip_addr_type =
2845                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2846                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2847                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2848                 rte_memcpy(filter->src_ipaddr,
2849                            fdir->input.flow.ipv6_flow.src_ip, 16);
2850                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2851                 rte_memcpy(filter->dst_ipaddr,
2852                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2853                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2854                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2855                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2856                 memset(filter->src_ipaddr_mask, 0xff, 16);
2857                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2858                 filter->ethertype = 0x86dd;
2859                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2860                 break;
2861         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2862                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2863                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2864                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2865                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2866                 filter->dst_port_mask = 0xffff;
2867                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2868                 filter->src_port_mask = 0xffff;
2869                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2870                 filter->ip_addr_type =
2871                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2872                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2873                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2874                 rte_memcpy(filter->src_ipaddr,
2875                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2876                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2877                 rte_memcpy(filter->dst_ipaddr,
2878                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2879                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2880                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2881                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2882                 memset(filter->src_ipaddr_mask, 0xff, 16);
2883                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2884                 filter->ethertype = 0x86dd;
2885                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2886                 break;
2887         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2888                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2889                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2890                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2891                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2892                 filter->dst_port_mask = 0xffff;
2893                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2894                 filter->src_port_mask = 0xffff;
2895                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2896                 filter->ip_addr_type =
2897                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2898                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2899                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2900                 rte_memcpy(filter->src_ipaddr,
2901                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2902                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2903                 rte_memcpy(filter->dst_ipaddr,
2904                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2905                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2906                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2907                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2908                 memset(filter->src_ipaddr_mask, 0xff, 16);
2909                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2910                 filter->ethertype = 0x86dd;
2911                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2912                 break;
2913         case RTE_ETH_FLOW_L2_PAYLOAD:
2914                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2915                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2916                 break;
2917         case RTE_ETH_FLOW_VXLAN:
2918                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2919                         return -EINVAL;
2920                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2921                 filter->tunnel_type =
2922                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2923                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2924                 break;
2925         case RTE_ETH_FLOW_NVGRE:
2926                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2927                         return -EINVAL;
2928                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2929                 filter->tunnel_type =
2930                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2931                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2932                 break;
2933         case RTE_ETH_FLOW_UNKNOWN:
2934         case RTE_ETH_FLOW_RAW:
2935         case RTE_ETH_FLOW_FRAG_IPV4:
2936         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2937         case RTE_ETH_FLOW_FRAG_IPV6:
2938         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2939         case RTE_ETH_FLOW_IPV6_EX:
2940         case RTE_ETH_FLOW_IPV6_TCP_EX:
2941         case RTE_ETH_FLOW_IPV6_UDP_EX:
2942         case RTE_ETH_FLOW_GENEVE:
2943                 /* FALLTHROUGH */
2944         default:
2945                 return -EINVAL;
2946         }
2947
2948         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2949         vnic = &bp->vnic_info[fdir->action.rx_queue];
2950         if (vnic == NULL) {
2951                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2952                 return -EINVAL;
2953         }
2954
2955         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2956                 rte_memcpy(filter->dst_macaddr,
2957                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2958                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2959         }
2960
2961         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2962                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2963                 filter1 = STAILQ_FIRST(&vnic0->filter);
2964                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2965         } else {
2966                 filter->dst_id = vnic->fw_vnic_id;
2967                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2968                         if (filter->dst_macaddr[i] == 0x00)
2969                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2970                         else
2971                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2972         }
2973
2974         if (filter1 == NULL)
2975                 return -EINVAL;
2976
2977         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2978         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2979
2980         filter->enables = en;
2981
2982         return 0;
2983 }
2984
2985 static struct bnxt_filter_info *
2986 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2987                 struct bnxt_vnic_info **mvnic)
2988 {
2989         struct bnxt_filter_info *mf = NULL;
2990         int i;
2991
2992         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2993                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2994
2995                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2996                         if (mf->filter_type == nf->filter_type &&
2997                             mf->flags == nf->flags &&
2998                             mf->src_port == nf->src_port &&
2999                             mf->src_port_mask == nf->src_port_mask &&
3000                             mf->dst_port == nf->dst_port &&
3001                             mf->dst_port_mask == nf->dst_port_mask &&
3002                             mf->ip_protocol == nf->ip_protocol &&
3003                             mf->ip_addr_type == nf->ip_addr_type &&
3004                             mf->ethertype == nf->ethertype &&
3005                             mf->vni == nf->vni &&
3006                             mf->tunnel_type == nf->tunnel_type &&
3007                             mf->l2_ovlan == nf->l2_ovlan &&
3008                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3009                             mf->l2_ivlan == nf->l2_ivlan &&
3010                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3011                             !memcmp(mf->l2_addr, nf->l2_addr,
3012                                     RTE_ETHER_ADDR_LEN) &&
3013                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3014                                     RTE_ETHER_ADDR_LEN) &&
3015                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3016                                     RTE_ETHER_ADDR_LEN) &&
3017                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3018                                     RTE_ETHER_ADDR_LEN) &&
3019                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3020                                     sizeof(nf->src_ipaddr)) &&
3021                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3022                                     sizeof(nf->src_ipaddr_mask)) &&
3023                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3024                                     sizeof(nf->dst_ipaddr)) &&
3025                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3026                                     sizeof(nf->dst_ipaddr_mask))) {
3027                                 if (mvnic)
3028                                         *mvnic = vnic;
3029                                 return mf;
3030                         }
3031                 }
3032         }
3033         return NULL;
3034 }
3035
3036 static int
3037 bnxt_fdir_filter(struct rte_eth_dev *dev,
3038                  enum rte_filter_op filter_op,
3039                  void *arg)
3040 {
3041         struct bnxt *bp = dev->data->dev_private;
3042         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3043         struct bnxt_filter_info *filter, *match;
3044         struct bnxt_vnic_info *vnic, *mvnic;
3045         int ret = 0, i;
3046
3047         if (filter_op == RTE_ETH_FILTER_NOP)
3048                 return 0;
3049
3050         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3051                 return -EINVAL;
3052
3053         switch (filter_op) {
3054         case RTE_ETH_FILTER_ADD:
3055         case RTE_ETH_FILTER_DELETE:
3056                 /* FALLTHROUGH */
3057                 filter = bnxt_get_unused_filter(bp);
3058                 if (filter == NULL) {
3059                         PMD_DRV_LOG(ERR,
3060                                 "Not enough resources for a new flow.\n");
3061                         return -ENOMEM;
3062                 }
3063
3064                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3065                 if (ret != 0)
3066                         goto free_filter;
3067                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3068
3069                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3070                         vnic = &bp->vnic_info[0];
3071                 else
3072                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3073
3074                 match = bnxt_match_fdir(bp, filter, &mvnic);
3075                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3076                         if (match->dst_id == vnic->fw_vnic_id) {
3077                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3078                                 ret = -EEXIST;
3079                                 goto free_filter;
3080                         } else {
3081                                 match->dst_id = vnic->fw_vnic_id;
3082                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3083                                                                   match->dst_id,
3084                                                                   match);
3085                                 STAILQ_REMOVE(&mvnic->filter, match,
3086                                               bnxt_filter_info, next);
3087                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3088                                 PMD_DRV_LOG(ERR,
3089                                         "Filter with matching pattern exist\n");
3090                                 PMD_DRV_LOG(ERR,
3091                                         "Updated it to new destination q\n");
3092                                 goto free_filter;
3093                         }
3094                 }
3095                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3096                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3097                         ret = -ENOENT;
3098                         goto free_filter;
3099                 }
3100
3101                 if (filter_op == RTE_ETH_FILTER_ADD) {
3102                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3103                                                           filter->dst_id,
3104                                                           filter);
3105                         if (ret)
3106                                 goto free_filter;
3107                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3108                 } else {
3109                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3110                         STAILQ_REMOVE(&vnic->filter, match,
3111                                       bnxt_filter_info, next);
3112                         bnxt_free_filter(bp, match);
3113                         bnxt_free_filter(bp, filter);
3114                 }
3115                 break;
3116         case RTE_ETH_FILTER_FLUSH:
3117                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3118                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3119
3120                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3121                                 if (filter->filter_type ==
3122                                     HWRM_CFA_NTUPLE_FILTER) {
3123                                         ret =
3124                                         bnxt_hwrm_clear_ntuple_filter(bp,
3125                                                                       filter);
3126                                         STAILQ_REMOVE(&vnic->filter, filter,
3127                                                       bnxt_filter_info, next);
3128                                 }
3129                         }
3130                 }
3131                 return ret;
3132         case RTE_ETH_FILTER_UPDATE:
3133         case RTE_ETH_FILTER_STATS:
3134         case RTE_ETH_FILTER_INFO:
3135                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3136                 break;
3137         default:
3138                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3139                 ret = -EINVAL;
3140                 break;
3141         }
3142         return ret;
3143
3144 free_filter:
3145         bnxt_free_filter(bp, filter);
3146         return ret;
3147 }
3148
3149 static int
3150 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3151                     enum rte_filter_type filter_type,
3152                     enum rte_filter_op filter_op, void *arg)
3153 {
3154         int ret = 0;
3155
3156         ret = is_bnxt_in_error(dev->data->dev_private);
3157         if (ret)
3158                 return ret;
3159
3160         switch (filter_type) {
3161         case RTE_ETH_FILTER_TUNNEL:
3162                 PMD_DRV_LOG(ERR,
3163                         "filter type: %d: To be implemented\n", filter_type);
3164                 break;
3165         case RTE_ETH_FILTER_FDIR:
3166                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3167                 break;
3168         case RTE_ETH_FILTER_NTUPLE:
3169                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3170                 break;
3171         case RTE_ETH_FILTER_ETHERTYPE:
3172                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3173                 break;
3174         case RTE_ETH_FILTER_GENERIC:
3175                 if (filter_op != RTE_ETH_FILTER_GET)
3176                         return -EINVAL;
3177                 *(const void **)arg = &bnxt_flow_ops;
3178                 break;
3179         default:
3180                 PMD_DRV_LOG(ERR,
3181                         "Filter type (%d) not supported", filter_type);
3182                 ret = -EINVAL;
3183                 break;
3184         }
3185         return ret;
3186 }
3187
3188 static const uint32_t *
3189 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3190 {
3191         static const uint32_t ptypes[] = {
3192                 RTE_PTYPE_L2_ETHER_VLAN,
3193                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3194                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3195                 RTE_PTYPE_L4_ICMP,
3196                 RTE_PTYPE_L4_TCP,
3197                 RTE_PTYPE_L4_UDP,
3198                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3199                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3200                 RTE_PTYPE_INNER_L4_ICMP,
3201                 RTE_PTYPE_INNER_L4_TCP,
3202                 RTE_PTYPE_INNER_L4_UDP,
3203                 RTE_PTYPE_UNKNOWN
3204         };
3205
3206         if (!dev->rx_pkt_burst)
3207                 return NULL;
3208
3209         return ptypes;
3210 }
3211
3212 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3213                          int reg_win)
3214 {
3215         uint32_t reg_base = *reg_arr & 0xfffff000;
3216         uint32_t win_off;
3217         int i;
3218
3219         for (i = 0; i < count; i++) {
3220                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3221                         return -ERANGE;
3222         }
3223         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3224         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3225         return 0;
3226 }
3227
3228 static int bnxt_map_ptp_regs(struct bnxt *bp)
3229 {
3230         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3231         uint32_t *reg_arr;
3232         int rc, i;
3233
3234         reg_arr = ptp->rx_regs;
3235         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3236         if (rc)
3237                 return rc;
3238
3239         reg_arr = ptp->tx_regs;
3240         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3241         if (rc)
3242                 return rc;
3243
3244         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3245                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3246
3247         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3248                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3249
3250         return 0;
3251 }
3252
3253 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3254 {
3255         rte_write32(0, (uint8_t *)bp->bar0 +
3256                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3257         rte_write32(0, (uint8_t *)bp->bar0 +
3258                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3259 }
3260
3261 static uint64_t bnxt_cc_read(struct bnxt *bp)
3262 {
3263         uint64_t ns;
3264
3265         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3266                               BNXT_GRCPF_REG_SYNC_TIME));
3267         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3268                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3269         return ns;
3270 }
3271
3272 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3273 {
3274         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3275         uint32_t fifo;
3276
3277         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3278                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3279         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3280                 return -EAGAIN;
3281
3282         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3283                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3284         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3285                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3286         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3287                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3288
3289         return 0;
3290 }
3291
3292 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3293 {
3294         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3295         struct bnxt_pf_info *pf = &bp->pf;
3296         uint16_t port_id;
3297         uint32_t fifo;
3298
3299         if (!ptp)
3300                 return -ENODEV;
3301
3302         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3303                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3304         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3305                 return -EAGAIN;
3306
3307         port_id = pf->port_id;
3308         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3309                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3310
3311         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3312                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3313         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3314 /*              bnxt_clr_rx_ts(bp);       TBD  */
3315                 return -EBUSY;
3316         }
3317
3318         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3319                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3320         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3321                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3322
3323         return 0;
3324 }
3325
3326 static int
3327 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3328 {
3329         uint64_t ns;
3330         struct bnxt *bp = dev->data->dev_private;
3331         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3332
3333         if (!ptp)
3334                 return 0;
3335
3336         ns = rte_timespec_to_ns(ts);
3337         /* Set the timecounters to a new value. */
3338         ptp->tc.nsec = ns;
3339
3340         return 0;
3341 }
3342
3343 static int
3344 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3345 {
3346         struct bnxt *bp = dev->data->dev_private;
3347         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3348         uint64_t ns, systime_cycles = 0;
3349         int rc = 0;
3350
3351         if (!ptp)
3352                 return 0;
3353
3354         if (BNXT_CHIP_THOR(bp))
3355                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3356                                              &systime_cycles);
3357         else
3358                 systime_cycles = bnxt_cc_read(bp);
3359
3360         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3361         *ts = rte_ns_to_timespec(ns);
3362
3363         return rc;
3364 }
3365 static int
3366 bnxt_timesync_enable(struct rte_eth_dev *dev)
3367 {
3368         struct bnxt *bp = dev->data->dev_private;
3369         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3370         uint32_t shift = 0;
3371         int rc;
3372
3373         if (!ptp)
3374                 return 0;
3375
3376         ptp->rx_filter = 1;
3377         ptp->tx_tstamp_en = 1;
3378         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3379
3380         rc = bnxt_hwrm_ptp_cfg(bp);
3381         if (rc)
3382                 return rc;
3383
3384         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3385         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3386         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3387
3388         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3389         ptp->tc.cc_shift = shift;
3390         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3391
3392         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3393         ptp->rx_tstamp_tc.cc_shift = shift;
3394         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3395
3396         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3397         ptp->tx_tstamp_tc.cc_shift = shift;
3398         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3399
3400         if (!BNXT_CHIP_THOR(bp))
3401                 bnxt_map_ptp_regs(bp);
3402
3403         return 0;
3404 }
3405
3406 static int
3407 bnxt_timesync_disable(struct rte_eth_dev *dev)
3408 {
3409         struct bnxt *bp = dev->data->dev_private;
3410         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3411
3412         if (!ptp)
3413                 return 0;
3414
3415         ptp->rx_filter = 0;
3416         ptp->tx_tstamp_en = 0;
3417         ptp->rxctl = 0;
3418
3419         bnxt_hwrm_ptp_cfg(bp);
3420
3421         if (!BNXT_CHIP_THOR(bp))
3422                 bnxt_unmap_ptp_regs(bp);
3423
3424         return 0;
3425 }
3426
3427 static int
3428 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3429                                  struct timespec *timestamp,
3430                                  uint32_t flags __rte_unused)
3431 {
3432         struct bnxt *bp = dev->data->dev_private;
3433         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3434         uint64_t rx_tstamp_cycles = 0;
3435         uint64_t ns;
3436
3437         if (!ptp)
3438                 return 0;
3439
3440         if (BNXT_CHIP_THOR(bp))
3441                 rx_tstamp_cycles = ptp->rx_timestamp;
3442         else
3443                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3444
3445         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3446         *timestamp = rte_ns_to_timespec(ns);
3447         return  0;
3448 }
3449
3450 static int
3451 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3452                                  struct timespec *timestamp)
3453 {
3454         struct bnxt *bp = dev->data->dev_private;
3455         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3456         uint64_t tx_tstamp_cycles = 0;
3457         uint64_t ns;
3458         int rc = 0;
3459
3460         if (!ptp)
3461                 return 0;
3462
3463         if (BNXT_CHIP_THOR(bp))
3464                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3465                                              &tx_tstamp_cycles);
3466         else
3467                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3468
3469         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3470         *timestamp = rte_ns_to_timespec(ns);
3471
3472         return rc;
3473 }
3474
3475 static int
3476 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3477 {
3478         struct bnxt *bp = dev->data->dev_private;
3479         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3480
3481         if (!ptp)
3482                 return 0;
3483
3484         ptp->tc.nsec += delta;
3485
3486         return 0;
3487 }
3488
3489 static int
3490 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3491 {
3492         struct bnxt *bp = dev->data->dev_private;
3493         int rc;
3494         uint32_t dir_entries;
3495         uint32_t entry_length;
3496
3497         rc = is_bnxt_in_error(bp);
3498         if (rc)
3499                 return rc;
3500
3501         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3502                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3503                 bp->pdev->addr.devid, bp->pdev->addr.function);
3504
3505         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3506         if (rc != 0)
3507                 return rc;
3508
3509         return dir_entries * entry_length;
3510 }
3511
3512 static int
3513 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3514                 struct rte_dev_eeprom_info *in_eeprom)
3515 {
3516         struct bnxt *bp = dev->data->dev_private;
3517         uint32_t index;
3518         uint32_t offset;
3519         int rc;
3520
3521         rc = is_bnxt_in_error(bp);
3522         if (rc)
3523                 return rc;
3524
3525         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3526                 "len = %d\n", bp->pdev->addr.domain,
3527                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3528                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3529
3530         if (in_eeprom->offset == 0) /* special offset value to get directory */
3531                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3532                                                 in_eeprom->data);
3533
3534         index = in_eeprom->offset >> 24;
3535         offset = in_eeprom->offset & 0xffffff;
3536
3537         if (index != 0)
3538                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3539                                            in_eeprom->length, in_eeprom->data);
3540
3541         return 0;
3542 }
3543
3544 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3545 {
3546         switch (dir_type) {
3547         case BNX_DIR_TYPE_CHIMP_PATCH:
3548         case BNX_DIR_TYPE_BOOTCODE:
3549         case BNX_DIR_TYPE_BOOTCODE_2:
3550         case BNX_DIR_TYPE_APE_FW:
3551         case BNX_DIR_TYPE_APE_PATCH:
3552         case BNX_DIR_TYPE_KONG_FW:
3553         case BNX_DIR_TYPE_KONG_PATCH:
3554         case BNX_DIR_TYPE_BONO_FW:
3555         case BNX_DIR_TYPE_BONO_PATCH:
3556                 /* FALLTHROUGH */
3557                 return true;
3558         }
3559
3560         return false;
3561 }
3562
3563 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3564 {
3565         switch (dir_type) {
3566         case BNX_DIR_TYPE_AVS:
3567         case BNX_DIR_TYPE_EXP_ROM_MBA:
3568         case BNX_DIR_TYPE_PCIE:
3569         case BNX_DIR_TYPE_TSCF_UCODE:
3570         case BNX_DIR_TYPE_EXT_PHY:
3571         case BNX_DIR_TYPE_CCM:
3572         case BNX_DIR_TYPE_ISCSI_BOOT:
3573         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3574         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3575                 /* FALLTHROUGH */
3576                 return true;
3577         }
3578
3579         return false;
3580 }
3581
3582 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3583 {
3584         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3585                 bnxt_dir_type_is_other_exec_format(dir_type);
3586 }
3587
3588 static int
3589 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3590                 struct rte_dev_eeprom_info *in_eeprom)
3591 {
3592         struct bnxt *bp = dev->data->dev_private;
3593         uint8_t index, dir_op;
3594         uint16_t type, ext, ordinal, attr;
3595         int rc;
3596
3597         rc = is_bnxt_in_error(bp);
3598         if (rc)
3599                 return rc;
3600
3601         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3602                 "len = %d\n", bp->pdev->addr.domain,
3603                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3604                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3605
3606         if (!BNXT_PF(bp)) {
3607                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3608                 return -EINVAL;
3609         }
3610
3611         type = in_eeprom->magic >> 16;
3612
3613         if (type == 0xffff) { /* special value for directory operations */
3614                 index = in_eeprom->magic & 0xff;
3615                 dir_op = in_eeprom->magic >> 8;
3616                 if (index == 0)
3617                         return -EINVAL;
3618                 switch (dir_op) {
3619                 case 0x0e: /* erase */
3620                         if (in_eeprom->offset != ~in_eeprom->magic)
3621                                 return -EINVAL;
3622                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3623                 default:
3624                         return -EINVAL;
3625                 }
3626         }
3627
3628         /* Create or re-write an NVM item: */
3629         if (bnxt_dir_type_is_executable(type) == true)
3630                 return -EOPNOTSUPP;
3631         ext = in_eeprom->magic & 0xffff;
3632         ordinal = in_eeprom->offset >> 16;
3633         attr = in_eeprom->offset & 0xffff;
3634
3635         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3636                                      in_eeprom->data, in_eeprom->length);
3637 }
3638
3639 /*
3640  * Initialization
3641  */
3642
3643 static const struct eth_dev_ops bnxt_dev_ops = {
3644         .dev_infos_get = bnxt_dev_info_get_op,
3645         .dev_close = bnxt_dev_close_op,
3646         .dev_configure = bnxt_dev_configure_op,
3647         .dev_start = bnxt_dev_start_op,
3648         .dev_stop = bnxt_dev_stop_op,
3649         .dev_set_link_up = bnxt_dev_set_link_up_op,
3650         .dev_set_link_down = bnxt_dev_set_link_down_op,
3651         .stats_get = bnxt_stats_get_op,
3652         .stats_reset = bnxt_stats_reset_op,
3653         .rx_queue_setup = bnxt_rx_queue_setup_op,
3654         .rx_queue_release = bnxt_rx_queue_release_op,
3655         .tx_queue_setup = bnxt_tx_queue_setup_op,
3656         .tx_queue_release = bnxt_tx_queue_release_op,
3657         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3658         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3659         .reta_update = bnxt_reta_update_op,
3660         .reta_query = bnxt_reta_query_op,
3661         .rss_hash_update = bnxt_rss_hash_update_op,
3662         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3663         .link_update = bnxt_link_update_op,
3664         .promiscuous_enable = bnxt_promiscuous_enable_op,
3665         .promiscuous_disable = bnxt_promiscuous_disable_op,
3666         .allmulticast_enable = bnxt_allmulticast_enable_op,
3667         .allmulticast_disable = bnxt_allmulticast_disable_op,
3668         .mac_addr_add = bnxt_mac_addr_add_op,
3669         .mac_addr_remove = bnxt_mac_addr_remove_op,
3670         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3671         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3672         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3673         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3674         .vlan_filter_set = bnxt_vlan_filter_set_op,
3675         .vlan_offload_set = bnxt_vlan_offload_set_op,
3676         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3677         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3678         .mtu_set = bnxt_mtu_set_op,
3679         .mac_addr_set = bnxt_set_default_mac_addr_op,
3680         .xstats_get = bnxt_dev_xstats_get_op,
3681         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3682         .xstats_reset = bnxt_dev_xstats_reset_op,
3683         .fw_version_get = bnxt_fw_version_get,
3684         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3685         .rxq_info_get = bnxt_rxq_info_get_op,
3686         .txq_info_get = bnxt_txq_info_get_op,
3687         .dev_led_on = bnxt_dev_led_on_op,
3688         .dev_led_off = bnxt_dev_led_off_op,
3689         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3690         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3691         .rx_queue_count = bnxt_rx_queue_count_op,
3692         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3693         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3694         .rx_queue_start = bnxt_rx_queue_start,
3695         .rx_queue_stop = bnxt_rx_queue_stop,
3696         .tx_queue_start = bnxt_tx_queue_start,
3697         .tx_queue_stop = bnxt_tx_queue_stop,
3698         .filter_ctrl = bnxt_filter_ctrl_op,
3699         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3700         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3701         .get_eeprom           = bnxt_get_eeprom_op,
3702         .set_eeprom           = bnxt_set_eeprom_op,
3703         .timesync_enable      = bnxt_timesync_enable,
3704         .timesync_disable     = bnxt_timesync_disable,
3705         .timesync_read_time   = bnxt_timesync_read_time,
3706         .timesync_write_time   = bnxt_timesync_write_time,
3707         .timesync_adjust_time = bnxt_timesync_adjust_time,
3708         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3709         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3710 };
3711
3712 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3713 {
3714         uint32_t offset;
3715
3716         /* Only pre-map the reset GRC registers using window 3 */
3717         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3718                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3719
3720         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3721
3722         return offset;
3723 }
3724
3725 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3726 {
3727         struct bnxt_error_recovery_info *info = bp->recovery_info;
3728         uint32_t reg_base = 0xffffffff;
3729         int i;
3730
3731         /* Only pre-map the monitoring GRC registers using window 2 */
3732         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3733                 uint32_t reg = info->status_regs[i];
3734
3735                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3736                         continue;
3737
3738                 if (reg_base == 0xffffffff)
3739                         reg_base = reg & 0xfffff000;
3740                 if ((reg & 0xfffff000) != reg_base)
3741                         return -ERANGE;
3742
3743                 /* Use mask 0xffc as the Lower 2 bits indicates
3744                  * address space location
3745                  */
3746                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3747                                                 (reg & 0xffc);
3748         }
3749
3750         if (reg_base == 0xffffffff)
3751                 return 0;
3752
3753         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3754                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3755
3756         return 0;
3757 }
3758
3759 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3760 {
3761         struct bnxt_error_recovery_info *info = bp->recovery_info;
3762         uint32_t delay = info->delay_after_reset[index];
3763         uint32_t val = info->reset_reg_val[index];
3764         uint32_t reg = info->reset_reg[index];
3765         uint32_t type, offset;
3766
3767         type = BNXT_FW_STATUS_REG_TYPE(reg);
3768         offset = BNXT_FW_STATUS_REG_OFF(reg);
3769
3770         switch (type) {
3771         case BNXT_FW_STATUS_REG_TYPE_CFG:
3772                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3773                 break;
3774         case BNXT_FW_STATUS_REG_TYPE_GRC:
3775                 offset = bnxt_map_reset_regs(bp, offset);
3776                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3777                 break;
3778         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3779                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3780                 break;
3781         }
3782         /* wait on a specific interval of time until core reset is complete */
3783         if (delay)
3784                 rte_delay_ms(delay);
3785 }
3786
3787 static void bnxt_dev_cleanup(struct bnxt *bp)
3788 {
3789         bnxt_set_hwrm_link_config(bp, false);
3790         bp->link_info.link_up = 0;
3791         if (bp->dev_stopped == 0)
3792                 bnxt_dev_stop_op(bp->eth_dev);
3793
3794         bnxt_uninit_resources(bp, true);
3795 }
3796
3797 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3798 {
3799         struct rte_eth_dev *dev = bp->eth_dev;
3800         struct rte_vlan_filter_conf *vfc;
3801         int vidx, vbit, rc;
3802         uint16_t vlan_id;
3803
3804         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3805                 vfc = &dev->data->vlan_filter_conf;
3806                 vidx = vlan_id / 64;
3807                 vbit = vlan_id % 64;
3808
3809                 /* Each bit corresponds to a VLAN id */
3810                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3811                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3812                         if (rc)
3813                                 return rc;
3814                 }
3815         }
3816
3817         return 0;
3818 }
3819
3820 static int bnxt_restore_mac_filters(struct bnxt *bp)
3821 {
3822         struct rte_eth_dev *dev = bp->eth_dev;
3823         struct rte_eth_dev_info dev_info;
3824         struct rte_ether_addr *addr;
3825         uint64_t pool_mask;
3826         uint32_t pool = 0;
3827         uint16_t i;
3828         int rc;
3829
3830         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
3831                 return 0;
3832
3833         rc = bnxt_dev_info_get_op(dev, &dev_info);
3834         if (rc)
3835                 return rc;
3836
3837         /* replay MAC address configuration */
3838         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3839                 addr = &dev->data->mac_addrs[i];
3840
3841                 /* skip zero address */
3842                 if (rte_is_zero_ether_addr(addr))
3843                         continue;
3844
3845                 pool = 0;
3846                 pool_mask = dev->data->mac_pool_sel[i];
3847
3848                 do {
3849                         if (pool_mask & 1ULL) {
3850                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3851                                 if (rc)
3852                                         return rc;
3853                         }
3854                         pool_mask >>= 1;
3855                         pool++;
3856                 } while (pool_mask);
3857         }
3858
3859         return 0;
3860 }
3861
3862 static int bnxt_restore_filters(struct bnxt *bp)
3863 {
3864         struct rte_eth_dev *dev = bp->eth_dev;
3865         int ret = 0;
3866
3867         if (dev->data->all_multicast)
3868                 ret = bnxt_allmulticast_enable_op(dev);
3869         if (dev->data->promiscuous)
3870                 ret = bnxt_promiscuous_enable_op(dev);
3871
3872         ret = bnxt_restore_mac_filters(bp);
3873         if (ret)
3874                 return ret;
3875
3876         ret = bnxt_restore_vlan_filters(bp);
3877         /* TODO restore other filters as well */
3878         return ret;
3879 }
3880
3881 static void bnxt_dev_recover(void *arg)
3882 {
3883         struct bnxt *bp = arg;
3884         int timeout = bp->fw_reset_max_msecs;
3885         int rc = 0;
3886
3887         /* Clear Error flag so that device re-init should happen */
3888         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3889
3890         do {
3891                 rc = bnxt_hwrm_ver_get(bp);
3892                 if (rc == 0)
3893                         break;
3894                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3895                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3896         } while (rc && timeout);
3897
3898         if (rc) {
3899                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3900                 goto err;
3901         }
3902
3903         rc = bnxt_init_resources(bp, true);
3904         if (rc) {
3905                 PMD_DRV_LOG(ERR,
3906                             "Failed to initialize resources after reset\n");
3907                 goto err;
3908         }
3909         /* clear reset flag as the device is initialized now */
3910         bp->flags &= ~BNXT_FLAG_FW_RESET;
3911
3912         rc = bnxt_dev_start_op(bp->eth_dev);
3913         if (rc) {
3914                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3915                 goto err;
3916         }
3917
3918         rc = bnxt_restore_filters(bp);
3919         if (rc)
3920                 goto err;
3921
3922         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3923         return;
3924 err:
3925         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3926         bnxt_uninit_resources(bp, false);
3927         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3928 }
3929
3930 void bnxt_dev_reset_and_resume(void *arg)
3931 {
3932         struct bnxt *bp = arg;
3933         int rc;
3934
3935         bnxt_dev_cleanup(bp);
3936
3937         bnxt_wait_for_device_shutdown(bp);
3938
3939         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3940                                bnxt_dev_recover, (void *)bp);
3941         if (rc)
3942                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3943 }
3944
3945 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3946 {
3947         struct bnxt_error_recovery_info *info = bp->recovery_info;
3948         uint32_t reg = info->status_regs[index];
3949         uint32_t type, offset, val = 0;
3950
3951         type = BNXT_FW_STATUS_REG_TYPE(reg);
3952         offset = BNXT_FW_STATUS_REG_OFF(reg);
3953
3954         switch (type) {
3955         case BNXT_FW_STATUS_REG_TYPE_CFG:
3956                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3957                 break;
3958         case BNXT_FW_STATUS_REG_TYPE_GRC:
3959                 offset = info->mapped_status_regs[index];
3960                 /* FALLTHROUGH */
3961         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3962                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3963                                        offset));
3964                 break;
3965         }
3966
3967         return val;
3968 }
3969
3970 static int bnxt_fw_reset_all(struct bnxt *bp)
3971 {
3972         struct bnxt_error_recovery_info *info = bp->recovery_info;
3973         uint32_t i;
3974         int rc = 0;
3975
3976         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3977                 /* Reset through master function driver */
3978                 for (i = 0; i < info->reg_array_cnt; i++)
3979                         bnxt_write_fw_reset_reg(bp, i);
3980                 /* Wait for time specified by FW after triggering reset */
3981                 rte_delay_ms(info->master_func_wait_period_after_reset);
3982         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3983                 /* Reset with the help of Kong processor */
3984                 rc = bnxt_hwrm_fw_reset(bp);
3985                 if (rc)
3986                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3987         }
3988
3989         return rc;
3990 }
3991
3992 static void bnxt_fw_reset_cb(void *arg)
3993 {
3994         struct bnxt *bp = arg;
3995         struct bnxt_error_recovery_info *info = bp->recovery_info;
3996         int rc = 0;
3997
3998         /* Only Master function can do FW reset */
3999         if (bnxt_is_master_func(bp) &&
4000             bnxt_is_recovery_enabled(bp)) {
4001                 rc = bnxt_fw_reset_all(bp);
4002                 if (rc) {
4003                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4004                         return;
4005                 }
4006         }
4007
4008         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4009          * EXCEPTION_FATAL_ASYNC event to all the functions
4010          * (including MASTER FUNC). After receiving this Async, all the active
4011          * drivers should treat this case as FW initiated recovery
4012          */
4013         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4014                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4015                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4016
4017                 /* To recover from error */
4018                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4019                                   (void *)bp);
4020         }
4021 }
4022
4023 /* Driver should poll FW heartbeat, reset_counter with the frequency
4024  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4025  * When the driver detects heartbeat stop or change in reset_counter,
4026  * it has to trigger a reset to recover from the error condition.
4027  * A “master PF” is the function who will have the privilege to
4028  * initiate the chimp reset. The master PF will be elected by the
4029  * firmware and will be notified through async message.
4030  */
4031 static void bnxt_check_fw_health(void *arg)
4032 {
4033         struct bnxt *bp = arg;
4034         struct bnxt_error_recovery_info *info = bp->recovery_info;
4035         uint32_t val = 0, wait_msec;
4036
4037         if (!info || !bnxt_is_recovery_enabled(bp) ||
4038             is_bnxt_in_error(bp))
4039                 return;
4040
4041         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4042         if (val == info->last_heart_beat)
4043                 goto reset;
4044
4045         info->last_heart_beat = val;
4046
4047         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4048         if (val != info->last_reset_counter)
4049                 goto reset;
4050
4051         info->last_reset_counter = val;
4052
4053         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4054                           bnxt_check_fw_health, (void *)bp);
4055
4056         return;
4057 reset:
4058         /* Stop DMA to/from device */
4059         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4060         bp->flags |= BNXT_FLAG_FW_RESET;
4061
4062         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4063
4064         if (bnxt_is_master_func(bp))
4065                 wait_msec = info->master_func_wait_period;
4066         else
4067                 wait_msec = info->normal_func_wait_period;
4068
4069         rte_eal_alarm_set(US_PER_MS * wait_msec,
4070                           bnxt_fw_reset_cb, (void *)bp);
4071 }
4072
4073 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4074 {
4075         uint32_t polling_freq;
4076
4077         if (!bnxt_is_recovery_enabled(bp))
4078                 return;
4079
4080         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4081                 return;
4082
4083         polling_freq = bp->recovery_info->driver_polling_freq;
4084
4085         rte_eal_alarm_set(US_PER_MS * polling_freq,
4086                           bnxt_check_fw_health, (void *)bp);
4087         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4088 }
4089
4090 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4091 {
4092         if (!bnxt_is_recovery_enabled(bp))
4093                 return;
4094
4095         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4096         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4097 }
4098
4099 static bool bnxt_vf_pciid(uint16_t device_id)
4100 {
4101         switch (device_id) {
4102         case BROADCOM_DEV_ID_57304_VF:
4103         case BROADCOM_DEV_ID_57406_VF:
4104         case BROADCOM_DEV_ID_5731X_VF:
4105         case BROADCOM_DEV_ID_5741X_VF:
4106         case BROADCOM_DEV_ID_57414_VF:
4107         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4108         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4109         case BROADCOM_DEV_ID_58802_VF:
4110         case BROADCOM_DEV_ID_57500_VF1:
4111         case BROADCOM_DEV_ID_57500_VF2:
4112                 /* FALLTHROUGH */
4113                 return true;
4114         default:
4115                 return false;
4116         }
4117 }
4118
4119 static bool bnxt_thor_device(uint16_t device_id)
4120 {
4121         switch (device_id) {
4122         case BROADCOM_DEV_ID_57508:
4123         case BROADCOM_DEV_ID_57504:
4124         case BROADCOM_DEV_ID_57502:
4125         case BROADCOM_DEV_ID_57508_MF1:
4126         case BROADCOM_DEV_ID_57504_MF1:
4127         case BROADCOM_DEV_ID_57502_MF1:
4128         case BROADCOM_DEV_ID_57508_MF2:
4129         case BROADCOM_DEV_ID_57504_MF2:
4130         case BROADCOM_DEV_ID_57502_MF2:
4131         case BROADCOM_DEV_ID_57500_VF1:
4132         case BROADCOM_DEV_ID_57500_VF2:
4133                 /* FALLTHROUGH */
4134                 return true;
4135         default:
4136                 return false;
4137         }
4138 }
4139
4140 bool bnxt_stratus_device(struct bnxt *bp)
4141 {
4142         uint16_t device_id = bp->pdev->id.device_id;
4143
4144         switch (device_id) {
4145         case BROADCOM_DEV_ID_STRATUS_NIC:
4146         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4147         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4148                 /* FALLTHROUGH */
4149                 return true;
4150         default:
4151                 return false;
4152         }
4153 }
4154
4155 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4156 {
4157         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4158         struct bnxt *bp = eth_dev->data->dev_private;
4159
4160         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4161         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4162         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4163         if (!bp->bar0 || !bp->doorbell_base) {
4164                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4165                 return -ENODEV;
4166         }
4167
4168         bp->eth_dev = eth_dev;
4169         bp->pdev = pci_dev;
4170
4171         return 0;
4172 }
4173
4174 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4175                                   struct bnxt_ctx_pg_info *ctx_pg,
4176                                   uint32_t mem_size,
4177                                   const char *suffix,
4178                                   uint16_t idx)
4179 {
4180         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4181         const struct rte_memzone *mz = NULL;
4182         char mz_name[RTE_MEMZONE_NAMESIZE];
4183         rte_iova_t mz_phys_addr;
4184         uint64_t valid_bits = 0;
4185         uint32_t sz;
4186         int i;
4187
4188         if (!mem_size)
4189                 return 0;
4190
4191         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4192                          BNXT_PAGE_SIZE;
4193         rmem->page_size = BNXT_PAGE_SIZE;
4194         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4195         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4196         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4197
4198         valid_bits = PTU_PTE_VALID;
4199
4200         if (rmem->nr_pages > 1) {
4201                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4202                          "bnxt_ctx_pg_tbl%s_%x_%d",
4203                          suffix, idx, bp->eth_dev->data->port_id);
4204                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4205                 mz = rte_memzone_lookup(mz_name);
4206                 if (!mz) {
4207                         mz = rte_memzone_reserve_aligned(mz_name,
4208                                                 rmem->nr_pages * 8,
4209                                                 SOCKET_ID_ANY,
4210                                                 RTE_MEMZONE_2MB |
4211                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4212                                                 RTE_MEMZONE_IOVA_CONTIG,
4213                                                 BNXT_PAGE_SIZE);
4214                         if (mz == NULL)
4215                                 return -ENOMEM;
4216                 }
4217
4218                 memset(mz->addr, 0, mz->len);
4219                 mz_phys_addr = mz->iova;
4220                 if ((unsigned long)mz->addr == mz_phys_addr) {
4221                         PMD_DRV_LOG(DEBUG,
4222                                     "physical address same as virtual\n");
4223                         PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4224                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
4225                         if (mz_phys_addr == RTE_BAD_IOVA) {
4226                                 PMD_DRV_LOG(ERR,
4227                                         "unable to map addr to phys memory\n");
4228                                 return -ENOMEM;
4229                         }
4230                 }
4231                 rte_mem_lock_page(((char *)mz->addr));
4232
4233                 rmem->pg_tbl = mz->addr;
4234                 rmem->pg_tbl_map = mz_phys_addr;
4235                 rmem->pg_tbl_mz = mz;
4236         }
4237
4238         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4239                  suffix, idx, bp->eth_dev->data->port_id);
4240         mz = rte_memzone_lookup(mz_name);
4241         if (!mz) {
4242                 mz = rte_memzone_reserve_aligned(mz_name,
4243                                                  mem_size,
4244                                                  SOCKET_ID_ANY,
4245                                                  RTE_MEMZONE_1GB |
4246                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4247                                                  RTE_MEMZONE_IOVA_CONTIG,
4248                                                  BNXT_PAGE_SIZE);
4249                 if (mz == NULL)
4250                         return -ENOMEM;
4251         }
4252
4253         memset(mz->addr, 0, mz->len);
4254         mz_phys_addr = mz->iova;
4255         if ((unsigned long)mz->addr == mz_phys_addr) {
4256                 PMD_DRV_LOG(DEBUG,
4257                             "Memzone physical address same as virtual.\n");
4258                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4259                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4260                         rte_mem_lock_page(((char *)mz->addr) + sz);
4261                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4262                 if (mz_phys_addr == RTE_BAD_IOVA) {
4263                         PMD_DRV_LOG(ERR,
4264                                     "unable to map addr to phys memory\n");
4265                         return -ENOMEM;
4266                 }
4267         }
4268
4269         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4270                 rte_mem_lock_page(((char *)mz->addr) + sz);
4271                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4272                 rmem->dma_arr[i] = mz_phys_addr + sz;
4273
4274                 if (rmem->nr_pages > 1) {
4275                         if (i == rmem->nr_pages - 2 &&
4276                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4277                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4278                         else if (i == rmem->nr_pages - 1 &&
4279                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4280                                 valid_bits |= PTU_PTE_LAST;
4281
4282                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4283                                                            valid_bits);
4284                 }
4285         }
4286
4287         rmem->mz = mz;
4288         if (rmem->vmem_size)
4289                 rmem->vmem = (void **)mz->addr;
4290         rmem->dma_arr[0] = mz_phys_addr;
4291         return 0;
4292 }
4293
4294 static void bnxt_free_ctx_mem(struct bnxt *bp)
4295 {
4296         int i;
4297
4298         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4299                 return;
4300
4301         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4302         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4303         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4304         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4305         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4306         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4307         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4308         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4309         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4310         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4311         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4312
4313         for (i = 0; i < BNXT_MAX_Q; i++) {
4314                 if (bp->ctx->tqm_mem[i])
4315                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4316         }
4317
4318         rte_free(bp->ctx);
4319         bp->ctx = NULL;
4320 }
4321
4322 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4323
4324 #define min_t(type, x, y) ({                    \
4325         type __min1 = (x);                      \
4326         type __min2 = (y);                      \
4327         __min1 < __min2 ? __min1 : __min2; })
4328
4329 #define max_t(type, x, y) ({                    \
4330         type __max1 = (x);                      \
4331         type __max2 = (y);                      \
4332         __max1 > __max2 ? __max1 : __max2; })
4333
4334 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4335
4336 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4337 {
4338         struct bnxt_ctx_pg_info *ctx_pg;
4339         struct bnxt_ctx_mem_info *ctx;
4340         uint32_t mem_size, ena, entries;
4341         int i, rc;
4342
4343         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4344         if (rc) {
4345                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4346                 return rc;
4347         }
4348         ctx = bp->ctx;
4349         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4350                 return 0;
4351
4352         ctx_pg = &ctx->qp_mem;
4353         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4354         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4355         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4356         if (rc)
4357                 return rc;
4358
4359         ctx_pg = &ctx->srq_mem;
4360         ctx_pg->entries = ctx->srq_max_l2_entries;
4361         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4362         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4363         if (rc)
4364                 return rc;
4365
4366         ctx_pg = &ctx->cq_mem;
4367         ctx_pg->entries = ctx->cq_max_l2_entries;
4368         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4369         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4370         if (rc)
4371                 return rc;
4372
4373         ctx_pg = &ctx->vnic_mem;
4374         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4375                 ctx->vnic_max_ring_table_entries;
4376         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4377         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4378         if (rc)
4379                 return rc;
4380
4381         ctx_pg = &ctx->stat_mem;
4382         ctx_pg->entries = ctx->stat_max_entries;
4383         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4384         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4385         if (rc)
4386                 return rc;
4387
4388         entries = ctx->qp_max_l2_entries +
4389                   ctx->vnic_max_vnic_entries +
4390                   ctx->tqm_min_entries_per_ring;
4391         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4392         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4393                           ctx->tqm_max_entries_per_ring);
4394         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4395                 ctx_pg = ctx->tqm_mem[i];
4396                 /* use min tqm entries for now. */
4397                 ctx_pg->entries = entries;
4398                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4399                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4400                 if (rc)
4401                         return rc;
4402                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4403         }
4404
4405         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4406         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4407         if (rc)
4408                 PMD_DRV_LOG(ERR,
4409                             "Failed to configure context mem: rc = %d\n", rc);
4410         else
4411                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4412
4413         return rc;
4414 }
4415
4416 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4417 {
4418         struct rte_pci_device *pci_dev = bp->pdev;
4419         char mz_name[RTE_MEMZONE_NAMESIZE];
4420         const struct rte_memzone *mz = NULL;
4421         uint32_t total_alloc_len;
4422         rte_iova_t mz_phys_addr;
4423
4424         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4425                 return 0;
4426
4427         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4428                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4429                  pci_dev->addr.bus, pci_dev->addr.devid,
4430                  pci_dev->addr.function, "rx_port_stats");
4431         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4432         mz = rte_memzone_lookup(mz_name);
4433         total_alloc_len =
4434                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4435                                        sizeof(struct rx_port_stats_ext) + 512);
4436         if (!mz) {
4437                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4438                                          SOCKET_ID_ANY,
4439                                          RTE_MEMZONE_2MB |
4440                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4441                                          RTE_MEMZONE_IOVA_CONTIG);
4442                 if (mz == NULL)
4443                         return -ENOMEM;
4444         }
4445         memset(mz->addr, 0, mz->len);
4446         mz_phys_addr = mz->iova;
4447         if ((unsigned long)mz->addr == mz_phys_addr) {
4448                 PMD_DRV_LOG(DEBUG,
4449                             "Memzone physical address same as virtual.\n");
4450                 PMD_DRV_LOG(DEBUG,
4451                             "Using rte_mem_virt2iova()\n");
4452                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4453                 if (mz_phys_addr == RTE_BAD_IOVA) {
4454                         PMD_DRV_LOG(ERR,
4455                                     "Can't map address to physical memory\n");
4456                         return -ENOMEM;
4457                 }
4458         }
4459
4460         bp->rx_mem_zone = (const void *)mz;
4461         bp->hw_rx_port_stats = mz->addr;
4462         bp->hw_rx_port_stats_map = mz_phys_addr;
4463
4464         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4465                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4466                  pci_dev->addr.bus, pci_dev->addr.devid,
4467                  pci_dev->addr.function, "tx_port_stats");
4468         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4469         mz = rte_memzone_lookup(mz_name);
4470         total_alloc_len =
4471                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4472                                        sizeof(struct tx_port_stats_ext) + 512);
4473         if (!mz) {
4474                 mz = rte_memzone_reserve(mz_name,
4475                                          total_alloc_len,
4476                                          SOCKET_ID_ANY,
4477                                          RTE_MEMZONE_2MB |
4478                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4479                                          RTE_MEMZONE_IOVA_CONTIG);
4480                 if (mz == NULL)
4481                         return -ENOMEM;
4482         }
4483         memset(mz->addr, 0, mz->len);
4484         mz_phys_addr = mz->iova;
4485         if ((unsigned long)mz->addr == mz_phys_addr) {
4486                 PMD_DRV_LOG(DEBUG,
4487                             "Memzone physical address same as virtual\n");
4488                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4489                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4490                 if (mz_phys_addr == RTE_BAD_IOVA) {
4491                         PMD_DRV_LOG(ERR,
4492                                     "Can't map address to physical memory\n");
4493                         return -ENOMEM;
4494                 }
4495         }
4496
4497         bp->tx_mem_zone = (const void *)mz;
4498         bp->hw_tx_port_stats = mz->addr;
4499         bp->hw_tx_port_stats_map = mz_phys_addr;
4500         bp->flags |= BNXT_FLAG_PORT_STATS;
4501
4502         /* Display extended statistics if FW supports it */
4503         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4504             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4505             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4506                 return 0;
4507
4508         bp->hw_rx_port_stats_ext = (void *)
4509                 ((uint8_t *)bp->hw_rx_port_stats +
4510                  sizeof(struct rx_port_stats));
4511         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4512                 sizeof(struct rx_port_stats);
4513         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4514
4515         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4516             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4517                 bp->hw_tx_port_stats_ext = (void *)
4518                         ((uint8_t *)bp->hw_tx_port_stats +
4519                          sizeof(struct tx_port_stats));
4520                 bp->hw_tx_port_stats_ext_map =
4521                         bp->hw_tx_port_stats_map +
4522                         sizeof(struct tx_port_stats);
4523                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4524         }
4525
4526         return 0;
4527 }
4528
4529 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4530 {
4531         struct bnxt *bp = eth_dev->data->dev_private;
4532         int rc = 0;
4533
4534         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4535                                                RTE_ETHER_ADDR_LEN *
4536                                                bp->max_l2_ctx,
4537                                                0);
4538         if (eth_dev->data->mac_addrs == NULL) {
4539                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4540                 return -ENOMEM;
4541         }
4542
4543         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4544                 if (BNXT_PF(bp))
4545                         return -EINVAL;
4546
4547                 /* Generate a random MAC address, if none was assigned by PF */
4548                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4549                 bnxt_eth_hw_addr_random(bp->mac_addr);
4550                 PMD_DRV_LOG(INFO,
4551                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4552                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4553                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4554
4555                 rc = bnxt_hwrm_set_mac(bp);
4556                 if (!rc)
4557                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4558                                RTE_ETHER_ADDR_LEN);
4559                 return rc;
4560         }
4561
4562         /* Copy the permanent MAC from the FUNC_QCAPS response */
4563         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4564         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4565
4566         return rc;
4567 }
4568
4569 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4570 {
4571         int rc = 0;
4572
4573         /* MAC is already configured in FW */
4574         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4575                 return 0;
4576
4577         /* Restore the old MAC configured */
4578         rc = bnxt_hwrm_set_mac(bp);
4579         if (rc)
4580                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4581
4582         return rc;
4583 }
4584
4585 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4586 {
4587         if (!BNXT_PF(bp))
4588                 return;
4589
4590 #define ALLOW_FUNC(x)   \
4591         { \
4592                 uint32_t arg = (x); \
4593                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4594                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4595         }
4596
4597         /* Forward all requests if firmware is new enough */
4598         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4599              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4600             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4601                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4602         } else {
4603                 PMD_DRV_LOG(WARNING,
4604                             "Firmware too old for VF mailbox functionality\n");
4605                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4606         }
4607
4608         /*
4609          * The following are used for driver cleanup. If we disallow these,
4610          * VF drivers can't clean up cleanly.
4611          */
4612         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4613         ALLOW_FUNC(HWRM_VNIC_FREE);
4614         ALLOW_FUNC(HWRM_RING_FREE);
4615         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4616         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4617         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4618         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4619         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4620         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4621 }
4622
4623 static int bnxt_init_fw(struct bnxt *bp)
4624 {
4625         uint16_t mtu;
4626         int rc = 0;
4627
4628         bp->fw_cap = 0;
4629
4630         rc = bnxt_hwrm_ver_get(bp);
4631         if (rc)
4632                 return rc;
4633
4634         rc = bnxt_hwrm_func_reset(bp);
4635         if (rc)
4636                 return -EIO;
4637
4638         rc = bnxt_hwrm_vnic_qcaps(bp);
4639         if (rc)
4640                 return rc;
4641
4642         rc = bnxt_hwrm_queue_qportcfg(bp);
4643         if (rc)
4644                 return rc;
4645
4646         /* Get the MAX capabilities for this function.
4647          * This function also allocates context memory for TQM rings and
4648          * informs the firmware about this allocated backing store memory.
4649          */
4650         rc = bnxt_hwrm_func_qcaps(bp);
4651         if (rc)
4652                 return rc;
4653
4654         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4655         if (rc)
4656                 return rc;
4657
4658         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4659         if (rc)
4660                 return rc;
4661
4662         /* Get the adapter error recovery support info */
4663         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4664         if (rc)
4665                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4666
4667         bnxt_hwrm_port_led_qcaps(bp);
4668
4669         return 0;
4670 }
4671
4672 static int
4673 bnxt_init_locks(struct bnxt *bp)
4674 {
4675         int err;
4676
4677         err = pthread_mutex_init(&bp->flow_lock, NULL);
4678         if (err) {
4679                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4680                 return err;
4681         }
4682
4683         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4684         if (err)
4685                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4686         return err;
4687 }
4688
4689 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4690 {
4691         int rc;
4692
4693         rc = bnxt_init_fw(bp);
4694         if (rc)
4695                 return rc;
4696
4697         if (!reconfig_dev) {
4698                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4699                 if (rc)
4700                         return rc;
4701         } else {
4702                 rc = bnxt_restore_dflt_mac(bp);
4703                 if (rc)
4704                         return rc;
4705         }
4706
4707         bnxt_config_vf_req_fwd(bp);
4708
4709         rc = bnxt_hwrm_func_driver_register(bp);
4710         if (rc) {
4711                 PMD_DRV_LOG(ERR, "Failed to register driver");
4712                 return -EBUSY;
4713         }
4714
4715         if (BNXT_PF(bp)) {
4716                 if (bp->pdev->max_vfs) {
4717                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4718                         if (rc) {
4719                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4720                                 return rc;
4721                         }
4722                 } else {
4723                         rc = bnxt_hwrm_allocate_pf_only(bp);
4724                         if (rc) {
4725                                 PMD_DRV_LOG(ERR,
4726                                             "Failed to allocate PF resources");
4727                                 return rc;
4728                         }
4729                 }
4730         }
4731
4732         rc = bnxt_alloc_mem(bp, reconfig_dev);
4733         if (rc)
4734                 return rc;
4735
4736         rc = bnxt_setup_int(bp);
4737         if (rc)
4738                 return rc;
4739
4740         rc = bnxt_request_int(bp);
4741         if (rc)
4742                 return rc;
4743
4744         rc = bnxt_init_locks(bp);
4745         if (rc)
4746                 return rc;
4747
4748         return 0;
4749 }
4750
4751 static int
4752 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4753 {
4754         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4755         static int version_printed;
4756         struct bnxt *bp;
4757         int rc;
4758
4759         if (version_printed++ == 0)
4760                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4761
4762         eth_dev->dev_ops = &bnxt_dev_ops;
4763         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4764         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4765
4766         /*
4767          * For secondary processes, we don't initialise any further
4768          * as primary has already done this work.
4769          */
4770         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4771                 return 0;
4772
4773         rte_eth_copy_pci_info(eth_dev, pci_dev);
4774
4775         bp = eth_dev->data->dev_private;
4776
4777         bp->dev_stopped = 1;
4778
4779         if (bnxt_vf_pciid(pci_dev->id.device_id))
4780                 bp->flags |= BNXT_FLAG_VF;
4781
4782         if (bnxt_thor_device(pci_dev->id.device_id))
4783                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4784
4785         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4786             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4787             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4788             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4789                 bp->flags |= BNXT_FLAG_STINGRAY;
4790
4791         rc = bnxt_init_board(eth_dev);
4792         if (rc) {
4793                 PMD_DRV_LOG(ERR,
4794                             "Failed to initialize board rc: %x\n", rc);
4795                 return rc;
4796         }
4797
4798         rc = bnxt_alloc_hwrm_resources(bp);
4799         if (rc) {
4800                 PMD_DRV_LOG(ERR,
4801                             "Failed to allocate hwrm resource rc: %x\n", rc);
4802                 goto error_free;
4803         }
4804         rc = bnxt_init_resources(bp, false);
4805         if (rc)
4806                 goto error_free;
4807
4808         rc = bnxt_alloc_stats_mem(bp);
4809         if (rc)
4810                 goto error_free;
4811
4812         PMD_DRV_LOG(INFO,
4813                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4814                     pci_dev->mem_resource[0].phys_addr,
4815                     pci_dev->mem_resource[0].addr);
4816
4817         return 0;
4818
4819 error_free:
4820         bnxt_dev_uninit(eth_dev);
4821         return rc;
4822 }
4823
4824 static void
4825 bnxt_uninit_locks(struct bnxt *bp)
4826 {
4827         pthread_mutex_destroy(&bp->flow_lock);
4828         pthread_mutex_destroy(&bp->def_cp_lock);
4829 }
4830
4831 static int
4832 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4833 {
4834         int rc;
4835
4836         bnxt_free_int(bp);
4837         bnxt_free_mem(bp, reconfig_dev);
4838         bnxt_hwrm_func_buf_unrgtr(bp);
4839         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4840         bp->flags &= ~BNXT_FLAG_REGISTERED;
4841         bnxt_free_ctx_mem(bp);
4842         if (!reconfig_dev) {
4843                 bnxt_free_hwrm_resources(bp);
4844
4845                 if (bp->recovery_info != NULL) {
4846                         rte_free(bp->recovery_info);
4847                         bp->recovery_info = NULL;
4848                 }
4849         }
4850
4851         bnxt_uninit_locks(bp);
4852         rte_free(bp->ptp_cfg);
4853         bp->ptp_cfg = NULL;
4854         return rc;
4855 }
4856
4857 static int
4858 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4859 {
4860         struct bnxt *bp = eth_dev->data->dev_private;
4861         int rc;
4862
4863         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4864                 return -EPERM;
4865
4866         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4867
4868         rc = bnxt_uninit_resources(bp, false);
4869
4870         if (bp->tx_mem_zone) {
4871                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4872                 bp->tx_mem_zone = NULL;
4873         }
4874
4875         if (bp->rx_mem_zone) {
4876                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4877                 bp->rx_mem_zone = NULL;
4878         }
4879
4880         if (bp->dev_stopped == 0)
4881                 bnxt_dev_close_op(eth_dev);
4882         if (bp->pf.vf_info)
4883                 rte_free(bp->pf.vf_info);
4884         eth_dev->dev_ops = NULL;
4885         eth_dev->rx_pkt_burst = NULL;
4886         eth_dev->tx_pkt_burst = NULL;
4887
4888         return rc;
4889 }
4890
4891 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4892         struct rte_pci_device *pci_dev)
4893 {
4894         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4895                 bnxt_dev_init);
4896 }
4897
4898 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4899 {
4900         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4901                 return rte_eth_dev_pci_generic_remove(pci_dev,
4902                                 bnxt_dev_uninit);
4903         else
4904                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4905 }
4906
4907 static struct rte_pci_driver bnxt_rte_pmd = {
4908         .id_table = bnxt_pci_id_map,
4909         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4910         .probe = bnxt_pci_probe,
4911         .remove = bnxt_pci_remove,
4912 };
4913
4914 static bool
4915 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4916 {
4917         if (strcmp(dev->device->driver->name, drv->driver.name))
4918                 return false;
4919
4920         return true;
4921 }
4922
4923 bool is_bnxt_supported(struct rte_eth_dev *dev)
4924 {
4925         return is_device_supported(dev, &bnxt_rte_pmd);
4926 }
4927
4928 RTE_INIT(bnxt_init_log)
4929 {
4930         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4931         if (bnxt_logtype_driver >= 0)
4932                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4933 }
4934
4935 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4936 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4937 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");