drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31
  32 #define DRV_MODULE_NAME         "bnxt"
  33 static const char bnxt_version[] =
  34         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  35
  36 /*
  37  * The set of PCI devices this driver supports
  38  */
  39 static const struct rte_pci_id bnxt_pci_id_map[] = {
  40         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  41                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  93         { .vendor_id = 0, /* sentinel */ },
  94 };
  95
  96 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  97 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  98 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  99 static const char *const bnxt_dev_args[] = {
 100         BNXT_DEVARG_TRUFLOW,
 101         BNXT_DEVARG_FLOW_XSTAT,
 102         BNXT_DEVARG_MAX_NUM_KFLOWS,
 103         NULL
 104 };
 105
 106 /*
 107  * truflow == false to disable the feature
 108  * truflow == true to enable the feature
 109  */
 110 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 111
 112 /*
 113  * flow_xstat == false to disable the feature
 114  * flow_xstat == true to enable the feature
 115  */
 116 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 117
 118 /*
 119  * max_num_kflows must be >= 32
 120  * and must be a power-of-2 supported value
 121  * return: 1 -> invalid
 122  *         0 -> valid
 123  */
 124 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 125 {
 126         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 127                 return 1;
 128         return 0;
 129 }
 130
 131 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 132 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 133 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 134 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 135 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 136 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 137 static void bnxt_dev_recover(void *arg);
 138 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 139 static void bnxt_free_rep_info(struct bnxt *bp);
 140
 141 int is_bnxt_in_error(struct bnxt *bp)
 142 {
 143         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 144                 return -EIO;
 145         if (bp->flags & BNXT_FLAG_FW_RESET)
 146                 return -EBUSY;
 147
 148         return 0;
 149 }
 150
 151 /***********************/
 152
 153 /*
 154  * High level utility functions
 155  */
 156
 157 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 158 {
 159         if (!BNXT_CHIP_THOR(bp))
 160                 return 1;
 161
 162         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 163                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 164                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 165 }
 166
 167 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 168 {
 169         if (!BNXT_CHIP_THOR(bp))
 170                 return HW_HASH_INDEX_SIZE;
 171
 172         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 173 }
 174
 175 static void bnxt_free_pf_info(struct bnxt *bp)
 176 {
 177         rte_free(bp->pf);
 178 }
 179
 180 static void bnxt_free_link_info(struct bnxt *bp)
 181 {
 182         rte_free(bp->link_info);
 183 }
 184
 185 static void bnxt_free_leds_info(struct bnxt *bp)
 186 {
 187         rte_free(bp->leds);
 188         bp->leds = NULL;
 189 }
 190
 191 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 192 {
 193         rte_free(bp->flow_stat);
 194         bp->flow_stat = NULL;
 195 }
 196
 197 static void bnxt_free_cos_queues(struct bnxt *bp)
 198 {
 199         rte_free(bp->rx_cos_queue);
 200         rte_free(bp->tx_cos_queue);
 201 }
 202
 203 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 204 {
 205         bnxt_free_filter_mem(bp);
 206         bnxt_free_vnic_attributes(bp);
 207         bnxt_free_vnic_mem(bp);
 208
 209         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 210          * If the number of rings change across fw update,
 211          * we don't have much choice except to warn the user.
 212          */
 213         if (!reconfig) {
 214                 bnxt_free_stats(bp);
 215                 bnxt_free_tx_rings(bp);
 216                 bnxt_free_rx_rings(bp);
 217         }
 218         bnxt_free_async_cp_ring(bp);
 219         bnxt_free_rxtx_nq_ring(bp);
 220
 221         rte_free(bp->grp_info);
 222         bp->grp_info = NULL;
 223 }
 224
 225 static int bnxt_alloc_pf_info(struct bnxt *bp)
 226 {
 227         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 228         if (bp->pf == NULL)
 229                 return -ENOMEM;
 230
 231         return 0;
 232 }
 233
 234 static int bnxt_alloc_link_info(struct bnxt *bp)
 235 {
 236         bp->link_info =
 237                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 238         if (bp->link_info == NULL)
 239                 return -ENOMEM;
 240
 241         return 0;
 242 }
 243
 244 static int bnxt_alloc_leds_info(struct bnxt *bp)
 245 {
 246         bp->leds = rte_zmalloc("bnxt_leds",
 247                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 248                                0);
 249         if (bp->leds == NULL)
 250                 return -ENOMEM;
 251
 252         return 0;
 253 }
 254
 255 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 256 {
 257         bp->rx_cos_queue =
 258                 rte_zmalloc("bnxt_rx_cosq",
 259                             BNXT_COS_QUEUE_COUNT *
 260                             sizeof(struct bnxt_cos_queue_info),
 261                             0);
 262         if (bp->rx_cos_queue == NULL)
 263                 return -ENOMEM;
 264
 265         bp->tx_cos_queue =
 266                 rte_zmalloc("bnxt_tx_cosq",
 267                             BNXT_COS_QUEUE_COUNT *
 268                             sizeof(struct bnxt_cos_queue_info),
 269                             0);
 270         if (bp->tx_cos_queue == NULL)
 271                 return -ENOMEM;
 272
 273         return 0;
 274 }
 275
 276 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 277 {
 278         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 279                                     sizeof(struct bnxt_flow_stat_info), 0);
 280         if (bp->flow_stat == NULL)
 281                 return -ENOMEM;
 282
 283         return 0;
 284 }
 285
 286 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 287 {
 288         int rc;
 289
 290         rc = bnxt_alloc_ring_grps(bp);
 291         if (rc)
 292                 goto alloc_mem_err;
 293
 294         rc = bnxt_alloc_async_ring_struct(bp);
 295         if (rc)
 296                 goto alloc_mem_err;
 297
 298         rc = bnxt_alloc_vnic_mem(bp);
 299         if (rc)
 300                 goto alloc_mem_err;
 301
 302         rc = bnxt_alloc_vnic_attributes(bp);
 303         if (rc)
 304                 goto alloc_mem_err;
 305
 306         rc = bnxt_alloc_filter_mem(bp);
 307         if (rc)
 308                 goto alloc_mem_err;
 309
 310         rc = bnxt_alloc_async_cp_ring(bp);
 311         if (rc)
 312                 goto alloc_mem_err;
 313
 314         rc = bnxt_alloc_rxtx_nq_ring(bp);
 315         if (rc)
 316                 goto alloc_mem_err;
 317
 318         if (BNXT_FLOW_XSTATS_EN(bp)) {
 319                 rc = bnxt_alloc_flow_stats_info(bp);
 320                 if (rc)
 321                         goto alloc_mem_err;
 322         }
 323
 324         return 0;
 325
 326 alloc_mem_err:
 327         bnxt_free_mem(bp, reconfig);
 328         return rc;
 329 }
 330
 331 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 332 {
 333         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 334         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 335         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 336         struct bnxt_rx_queue *rxq;
 337         unsigned int j;
 338         int rc;
 339
 340         rc = bnxt_vnic_grp_alloc(bp, vnic);
 341         if (rc)
 342                 goto err_out;
 343
 344         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 345                     vnic_id, vnic, vnic->fw_grp_ids);
 346
 347         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 348         if (rc)
 349                 goto err_out;
 350
 351         /* Alloc RSS context only if RSS mode is enabled */
 352         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 353                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 354
 355                 rc = 0;
 356                 for (j = 0; j < nr_ctxs; j++) {
 357                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 358                         if (rc)
 359                                 break;
 360                 }
 361                 if (rc) {
 362                         PMD_DRV_LOG(ERR,
 363                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 364                                     vnic_id, j, rc);
 365                         goto err_out;
 366                 }
 367                 vnic->num_lb_ctxts = nr_ctxs;
 368         }
 369
 370         /*
 371          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 372          * setting is not available at this time, it will not be
 373          * configured correctly in the CFA.
 374          */
 375         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 376                 vnic->vlan_strip = true;
 377         else
 378                 vnic->vlan_strip = false;
 379
 380         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 381         if (rc)
 382                 goto err_out;
 383
 384         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 385         if (rc)
 386                 goto err_out;
 387
 388         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 389                 rxq = bp->eth_dev->data->rx_queues[j];
 390
 391                 PMD_DRV_LOG(DEBUG,
 392                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 393                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 394
 395                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 396                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 397                 else
 398                         vnic->rx_queue_cnt++;
 399         }
 400
 401         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 402
 403         rc = bnxt_vnic_rss_configure(bp, vnic);
 404         if (rc)
 405                 goto err_out;
 406
 407         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 408
 409         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 410                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 411         else
 412                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 413
 414         return 0;
 415 err_out:
 416         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 417                     vnic_id, rc);
 418         return rc;
 419 }
 420
 421 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 422 {
 423         int rc = 0;
 424
 425         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 426                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 427         if (rc)
 428                 return rc;
 429
 430         PMD_DRV_LOG(DEBUG,
 431                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 432                     " rx_fc_in_tbl.ctx_id = %d\n",
 433                     bp->flow_stat->rx_fc_in_tbl.va,
 434                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 435                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 436
 437         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 438                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 439         if (rc)
 440                 return rc;
 441
 442         PMD_DRV_LOG(DEBUG,
 443                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 444                     " rx_fc_out_tbl.ctx_id = %d\n",
 445                     bp->flow_stat->rx_fc_out_tbl.va,
 446                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 447                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 448
 449         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 450                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 451         if (rc)
 452                 return rc;
 453
 454         PMD_DRV_LOG(DEBUG,
 455                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 456                     " tx_fc_in_tbl.ctx_id = %d\n",
 457                     bp->flow_stat->tx_fc_in_tbl.va,
 458                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 459                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 460
 461         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 462                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 463         if (rc)
 464                 return rc;
 465
 466         PMD_DRV_LOG(DEBUG,
 467                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 468                     " tx_fc_out_tbl.ctx_id = %d\n",
 469                     bp->flow_stat->tx_fc_out_tbl.va,
 470                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 471                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 472
 473         memset(bp->flow_stat->rx_fc_out_tbl.va,
 474                0,
 475                bp->flow_stat->rx_fc_out_tbl.size);
 476         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 477                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 478                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 479                                        bp->flow_stat->max_fc,
 480                                        true);
 481         if (rc)
 482                 return rc;
 483
 484         memset(bp->flow_stat->tx_fc_out_tbl.va,
 485                0,
 486                bp->flow_stat->tx_fc_out_tbl.size);
 487         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 488                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 489                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 490                                        bp->flow_stat->max_fc,
 491                                        true);
 492
 493         return rc;
 494 }
 495
 496 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 497                                   struct bnxt_ctx_mem_buf_info *ctx)
 498 {
 499         if (!ctx)
 500                 return -EINVAL;
 501
 502         ctx->va = rte_zmalloc(type, size, 0);
 503         if (ctx->va == NULL)
 504                 return -ENOMEM;
 505         rte_mem_lock_page(ctx->va);
 506         ctx->size = size;
 507         ctx->dma = rte_mem_virt2iova(ctx->va);
 508         if (ctx->dma == RTE_BAD_IOVA)
 509                 return -ENOMEM;
 510
 511         return 0;
 512 }
 513
 514 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 515 {
 516         struct rte_pci_device *pdev = bp->pdev;
 517         char type[RTE_MEMZONE_NAMESIZE];
 518         uint16_t max_fc;
 519         int rc = 0;
 520
 521         max_fc = bp->flow_stat->max_fc;
 522
 523         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 524                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 525         /* 4 bytes for each counter-id */
 526         rc = bnxt_alloc_ctx_mem_buf(type,
 527                                     max_fc * 4,
 528                                     &bp->flow_stat->rx_fc_in_tbl);
 529         if (rc)
 530                 return rc;
 531
 532         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 533                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 534         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 535         rc = bnxt_alloc_ctx_mem_buf(type,
 536                                     max_fc * 16,
 537                                     &bp->flow_stat->rx_fc_out_tbl);
 538         if (rc)
 539                 return rc;
 540
 541         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 542                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 543         /* 4 bytes for each counter-id */
 544         rc = bnxt_alloc_ctx_mem_buf(type,
 545                                     max_fc * 4,
 546                                     &bp->flow_stat->tx_fc_in_tbl);
 547         if (rc)
 548                 return rc;
 549
 550         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 551                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 552         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 553         rc = bnxt_alloc_ctx_mem_buf(type,
 554                                     max_fc * 16,
 555                                     &bp->flow_stat->tx_fc_out_tbl);
 556         if (rc)
 557                 return rc;
 558
 559         rc = bnxt_register_fc_ctx_mem(bp);
 560
 561         return rc;
 562 }
 563
 564 static int bnxt_init_ctx_mem(struct bnxt *bp)
 565 {
 566         int rc = 0;
 567
 568         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 569             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 570             !BNXT_FLOW_XSTATS_EN(bp))
 571                 return 0;
 572
 573         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 574         if (rc)
 575                 return rc;
 576
 577         rc = bnxt_init_fc_ctx_mem(bp);
 578
 579         return rc;
 580 }
 581
 582 static int bnxt_init_chip(struct bnxt *bp)
 583 {
 584         struct rte_eth_link new;
 585         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 586         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 587         uint32_t intr_vector = 0;
 588         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 589         uint32_t vec = BNXT_MISC_VEC_ID;
 590         unsigned int i, j;
 591         int rc;
 592
 593         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 594                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 595                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 596                 bp->flags |= BNXT_FLAG_JUMBO;
 597         } else {
 598                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 599                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 600                 bp->flags &= ~BNXT_FLAG_JUMBO;
 601         }
 602
 603         /* THOR does not support ring groups.
 604          * But we will use the array to save RSS context IDs.
 605          */
 606         if (BNXT_CHIP_THOR(bp))
 607                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 608
 609         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 610         if (rc) {
 611                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 612                 goto err_out;
 613         }
 614
 615         rc = bnxt_alloc_hwrm_rings(bp);
 616         if (rc) {
 617                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 618                 goto err_out;
 619         }
 620
 621         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 622         if (rc) {
 623                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 624                 goto err_out;
 625         }
 626
 627         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 628                 goto skip_cosq_cfg;
 629
 630         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 631                 if (bp->rx_cos_queue[i].id != 0xff) {
 632                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 633
 634                         if (!vnic) {
 635                                 PMD_DRV_LOG(ERR,
 636                                             "Num pools more than FW profile\n");
 637                                 rc = -EINVAL;
 638                                 goto err_out;
 639                         }
 640                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 641                         bp->rx_cosq_cnt++;
 642                 }
 643         }
 644
 645 skip_cosq_cfg:
 646         rc = bnxt_mq_rx_configure(bp);
 647         if (rc) {
 648                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 649                 goto err_out;
 650         }
 651
 652         /* VNIC configuration */
 653         for (i = 0; i < bp->nr_vnics; i++) {
 654                 rc = bnxt_setup_one_vnic(bp, i);
 655                 if (rc)
 656                         goto err_out;
 657         }
 658
 659         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 660         if (rc) {
 661                 PMD_DRV_LOG(ERR,
 662                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 663                 goto err_out;
 664         }
 665
 666         /* check and configure queue intr-vector mapping */
 667         if ((rte_intr_cap_multiple(intr_handle) ||
 668              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 669             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 670                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 671                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 672                 if (intr_vector > bp->rx_cp_nr_rings) {
 673                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 674                                         bp->rx_cp_nr_rings);
 675                         return -ENOTSUP;
 676                 }
 677                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 678                 if (rc)
 679                         return rc;
 680         }
 681
 682         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 683                 intr_handle->intr_vec =
 684                         rte_zmalloc("intr_vec",
 685                                     bp->eth_dev->data->nb_rx_queues *
 686                                     sizeof(int), 0);
 687                 if (intr_handle->intr_vec == NULL) {
 688                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 689                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 690                         rc = -ENOMEM;
 691                         goto err_disable;
 692                 }
 693                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 694                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 695                          intr_handle->intr_vec, intr_handle->nb_efd,
 696                         intr_handle->max_intr);
 697                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 698                      queue_id++) {
 699                         intr_handle->intr_vec[queue_id] =
 700                                                         vec + BNXT_RX_VEC_START;
 701                         if (vec < base + intr_handle->nb_efd - 1)
 702                                 vec++;
 703                 }
 704         }
 705
 706         /* enable uio/vfio intr/eventfd mapping */
 707         rc = rte_intr_enable(intr_handle);
 708 #ifndef RTE_EXEC_ENV_FREEBSD
 709         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 710         if (rc)
 711                 goto err_free;
 712 #endif
 713
 714         rc = bnxt_get_hwrm_link_config(bp, &new);
 715         if (rc) {
 716                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 717                 goto err_free;
 718         }
 719
 720         if (!bp->link_info->link_up) {
 721                 rc = bnxt_set_hwrm_link_config(bp, true);
 722                 if (rc) {
 723                         PMD_DRV_LOG(ERR,
 724                                 "HWRM link config failure rc: %x\n", rc);
 725                         goto err_free;
 726                 }
 727         }
 728         bnxt_print_link_info(bp->eth_dev);
 729
 730         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 731         if (!bp->mark_table)
 732                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 733
 734         return 0;
 735
 736 err_free:
 737         rte_free(intr_handle->intr_vec);
 738 err_disable:
 739         rte_intr_efd_disable(intr_handle);
 740 err_out:
 741         /* Some of the error status returned by FW may not be from errno.h */
 742         if (rc > 0)
 743                 rc = -EIO;
 744
 745         return rc;
 746 }
 747
 748 static int bnxt_shutdown_nic(struct bnxt *bp)
 749 {
 750         bnxt_free_all_hwrm_resources(bp);
 751         bnxt_free_all_filters(bp);
 752         bnxt_free_all_vnics(bp);
 753         return 0;
 754 }
 755
 756 /*
 757  * Device configuration and status function
 758  */
 759
 760 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 761 {
 762         uint32_t link_speed = bp->link_info->support_speeds;
 763         uint32_t speed_capa = 0;
 764
 765         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 766                 speed_capa |= ETH_LINK_SPEED_100M;
 767         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 768                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 769         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 770                 speed_capa |= ETH_LINK_SPEED_1G;
 771         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 772                 speed_capa |= ETH_LINK_SPEED_2_5G;
 773         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 774                 speed_capa |= ETH_LINK_SPEED_10G;
 775         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 776                 speed_capa |= ETH_LINK_SPEED_20G;
 777         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 778                 speed_capa |= ETH_LINK_SPEED_25G;
 779         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 780                 speed_capa |= ETH_LINK_SPEED_40G;
 781         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 782                 speed_capa |= ETH_LINK_SPEED_50G;
 783         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 784                 speed_capa |= ETH_LINK_SPEED_100G;
 785         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
 786                 speed_capa |= ETH_LINK_SPEED_200G;
 787
 788         if (bp->link_info->auto_mode ==
 789             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 790                 speed_capa |= ETH_LINK_SPEED_FIXED;
 791         else
 792                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 793
 794         return speed_capa;
 795 }
 796
 797 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 798                                 struct rte_eth_dev_info *dev_info)
 799 {
 800         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 801         struct bnxt *bp = eth_dev->data->dev_private;
 802         uint16_t max_vnics, i, j, vpool, vrxq;
 803         unsigned int max_rx_rings;
 804         int rc;
 805
 806         rc = is_bnxt_in_error(bp);
 807         if (rc)
 808                 return rc;
 809
 810         /* MAC Specifics */
 811         dev_info->max_mac_addrs = bp->max_l2_ctx;
 812         dev_info->max_hash_mac_addrs = 0;
 813
 814         /* PF/VF specifics */
 815         if (BNXT_PF(bp))
 816                 dev_info->max_vfs = pdev->max_vfs;
 817
 818         max_rx_rings = BNXT_MAX_RINGS(bp);
 819         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 820         dev_info->max_rx_queues = max_rx_rings;
 821         dev_info->max_tx_queues = max_rx_rings;
 822         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 823         dev_info->hash_key_size = 40;
 824         max_vnics = bp->max_vnics;
 825
 826         /* MTU specifics */
 827         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 828         dev_info->max_mtu = BNXT_MAX_MTU;
 829
 830         /* Fast path specifics */
 831         dev_info->min_rx_bufsize = 1;
 832         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 833
 834         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 835         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 836                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 837         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 838         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 839
 840         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 841
 842         /* *INDENT-OFF* */
 843         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 844                 .rx_thresh = {
 845                         .pthresh = 8,
 846                         .hthresh = 8,
 847                         .wthresh = 0,
 848                 },
 849                 .rx_free_thresh = 32,
 850                 /* If no descriptors available, pkts are dropped by default */
 851                 .rx_drop_en = 1,
 852         };
 853
 854         dev_info->default_txconf = (struct rte_eth_txconf) {
 855                 .tx_thresh = {
 856                         .pthresh = 32,
 857                         .hthresh = 0,
 858                         .wthresh = 0,
 859                 },
 860                 .tx_free_thresh = 32,
 861                 .tx_rs_thresh = 32,
 862         };
 863         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 864
 865         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 866         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 867         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 868         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 869         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 870
 871         /* *INDENT-ON* */
 872
 873         /*
 874          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 875          *       need further investigation.
 876          */
 877
 878         /* VMDq resources */
 879         vpool = 64; /* ETH_64_POOLS */
 880         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 881         for (i = 0; i < 4; vpool >>= 1, i++) {
 882                 if (max_vnics > vpool) {
 883                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 884                                 if (dev_info->max_rx_queues > vrxq) {
 885                                         if (vpool > vrxq)
 886                                                 vpool = vrxq;
 887                                         goto found;
 888                                 }
 889                         }
 890                         /* Not enough resources to support VMDq */
 891                         break;
 892                 }
 893         }
 894         /* Not enough resources to support VMDq */
 895         vpool = 0;
 896         vrxq = 0;
 897 found:
 898         dev_info->max_vmdq_pools = vpool;
 899         dev_info->vmdq_queue_num = vrxq;
 900
 901         dev_info->vmdq_pool_base = 0;
 902         dev_info->vmdq_queue_base = 0;
 903
 904         return 0;
 905 }
 906
 907 /* Configure the device based on the configuration provided */
 908 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 909 {
 910         struct bnxt *bp = eth_dev->data->dev_private;
 911         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 912         int rc;
 913
 914         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 915         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 916         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 917         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 918
 919         rc = is_bnxt_in_error(bp);
 920         if (rc)
 921                 return rc;
 922
 923         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 924                 rc = bnxt_hwrm_check_vf_rings(bp);
 925                 if (rc) {
 926                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 927                         return -ENOSPC;
 928                 }
 929
 930                 /* If a resource has already been allocated - in this case
 931                  * it is the async completion ring, free it. Reallocate it after
 932                  * resource reservation. This will ensure the resource counts
 933                  * are calculated correctly.
 934                  */
 935
 936                 pthread_mutex_lock(&bp->def_cp_lock);
 937
 938                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 939                         bnxt_disable_int(bp);
 940                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 941                 }
 942
 943                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 944                 if (rc) {
 945                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 946                         pthread_mutex_unlock(&bp->def_cp_lock);
 947                         return -ENOSPC;
 948                 }
 949
 950                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 951                         rc = bnxt_alloc_async_cp_ring(bp);
 952                         if (rc) {
 953                                 pthread_mutex_unlock(&bp->def_cp_lock);
 954                                 return rc;
 955                         }
 956                         bnxt_enable_int(bp);
 957                 }
 958
 959                 pthread_mutex_unlock(&bp->def_cp_lock);
 960         } else {
 961                 /* legacy driver needs to get updated values */
 962                 rc = bnxt_hwrm_func_qcaps(bp);
 963                 if (rc) {
 964                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 965                         return rc;
 966                 }
 967         }
 968
 969         /* Inherit new configurations */
 970         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 971             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 972             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 973                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 974             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 975             bp->max_stat_ctx)
 976                 goto resource_error;
 977
 978         if (BNXT_HAS_RING_GRPS(bp) &&
 979             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 980                 goto resource_error;
 981
 982         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 983             bp->max_vnics < eth_dev->data->nb_rx_queues)
 984                 goto resource_error;
 985
 986         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 987         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 988
 989         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 990                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 991         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
 992
 993         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 994                 eth_dev->data->mtu =
 995                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 996                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 997                         BNXT_NUM_VLANS;
 998                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 999         }
1000         return 0;
1001
1002 resource_error:
1003         PMD_DRV_LOG(ERR,
1004                     "Insufficient resources to support requested config\n");
1005         PMD_DRV_LOG(ERR,
1006                     "Num Queues Requested: Tx %d, Rx %d\n",
1007                     eth_dev->data->nb_tx_queues,
1008                     eth_dev->data->nb_rx_queues);
1009         PMD_DRV_LOG(ERR,
1010                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1011                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1012                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1013         return -ENOSPC;
1014 }
1015
1016 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1017 {
1018         struct rte_eth_link *link = &eth_dev->data->dev_link;
1019
1020         if (link->link_status)
1021                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1022                         eth_dev->data->port_id,
1023                         (uint32_t)link->link_speed,
1024                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1025                         ("full-duplex") : ("half-duplex\n"));
1026         else
1027                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1028                         eth_dev->data->port_id);
1029 }
1030
1031 /*
1032  * Determine whether the current configuration requires support for scattered
1033  * receive; return 1 if scattered receive is required and 0 if not.
1034  */
1035 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1036 {
1037         uint16_t buf_size;
1038         int i;
1039
1040         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1041                 return 1;
1042
1043         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1044                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1045
1046                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1047                                       RTE_PKTMBUF_HEADROOM);
1048                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1049                         return 1;
1050         }
1051         return 0;
1052 }
1053
1054 static eth_rx_burst_t
1055 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1056 {
1057         struct bnxt *bp = eth_dev->data->dev_private;
1058
1059 #ifdef RTE_ARCH_X86
1060 #ifndef RTE_LIBRTE_IEEE1588
1061         /*
1062          * Vector mode receive can be enabled only if scatter rx is not
1063          * in use and rx offloads are limited to VLAN stripping and
1064          * CRC stripping.
1065          */
1066         if (!eth_dev->data->scattered_rx &&
1067             !(eth_dev->data->dev_conf.rxmode.offloads &
1068               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1069                 DEV_RX_OFFLOAD_KEEP_CRC |
1070                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1071                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1072                 DEV_RX_OFFLOAD_UDP_CKSUM |
1073                 DEV_RX_OFFLOAD_TCP_CKSUM |
1074                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1075                 DEV_RX_OFFLOAD_RSS_HASH |
1076                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1077             !BNXT_TRUFLOW_EN(bp)) {
1078                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1079                             eth_dev->data->port_id);
1080                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1081                 return bnxt_recv_pkts_vec;
1082         }
1083         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1084                     eth_dev->data->port_id);
1085         PMD_DRV_LOG(INFO,
1086                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1087                     eth_dev->data->port_id,
1088                     eth_dev->data->scattered_rx,
1089                     eth_dev->data->dev_conf.rxmode.offloads);
1090 #endif
1091 #endif
1092         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1093         return bnxt_recv_pkts;
1094 }
1095
1096 static eth_tx_burst_t
1097 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1098 {
1099 #ifdef RTE_ARCH_X86
1100 #ifndef RTE_LIBRTE_IEEE1588
1101         /*
1102          * Vector mode transmit can be enabled only if not using scatter rx
1103          * or tx offloads.
1104          */
1105         if (!eth_dev->data->scattered_rx &&
1106             !eth_dev->data->dev_conf.txmode.offloads) {
1107                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1108                             eth_dev->data->port_id);
1109                 return bnxt_xmit_pkts_vec;
1110         }
1111         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1112                     eth_dev->data->port_id);
1113         PMD_DRV_LOG(INFO,
1114                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1115                     eth_dev->data->port_id,
1116                     eth_dev->data->scattered_rx,
1117                     eth_dev->data->dev_conf.txmode.offloads);
1118 #endif
1119 #endif
1120         return bnxt_xmit_pkts;
1121 }
1122
1123 static int bnxt_handle_if_change_status(struct bnxt *bp)
1124 {
1125         int rc;
1126
1127         /* Since fw has undergone a reset and lost all contexts,
1128          * set fatal flag to not issue hwrm during cleanup
1129          */
1130         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1131         bnxt_uninit_resources(bp, true);
1132
1133         /* clear fatal flag so that re-init happens */
1134         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1135         rc = bnxt_init_resources(bp, true);
1136
1137         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1138
1139         return rc;
1140 }
1141
1142 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1143 {
1144         struct bnxt *bp = eth_dev->data->dev_private;
1145         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1146         int vlan_mask = 0;
1147         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1148
1149         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1150                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1151                 return -EINVAL;
1152         }
1153
1154         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1155                 PMD_DRV_LOG(ERR,
1156                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1157                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1158         }
1159
1160         do {
1161                 rc = bnxt_hwrm_if_change(bp, true);
1162                 if (rc == 0 || rc != -EAGAIN)
1163                         break;
1164
1165                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1166         } while (retry_cnt--);
1167
1168         if (rc)
1169                 return rc;
1170
1171         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1172                 rc = bnxt_handle_if_change_status(bp);
1173                 if (rc)
1174                         return rc;
1175         }
1176
1177         bnxt_enable_int(bp);
1178
1179         rc = bnxt_init_chip(bp);
1180         if (rc)
1181                 goto error;
1182
1183         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1184         eth_dev->data->dev_started = 1;
1185
1186         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1187
1188         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1189                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1190         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1191                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1192         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1193         if (rc)
1194                 goto error;
1195
1196         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1197         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1198
1199         pthread_mutex_lock(&bp->def_cp_lock);
1200         bnxt_schedule_fw_health_check(bp);
1201         pthread_mutex_unlock(&bp->def_cp_lock);
1202
1203         if (BNXT_TRUFLOW_EN(bp))
1204                 bnxt_ulp_init(bp);
1205
1206         return 0;
1207
1208 error:
1209         bnxt_shutdown_nic(bp);
1210         bnxt_free_tx_mbufs(bp);
1211         bnxt_free_rx_mbufs(bp);
1212         bnxt_hwrm_if_change(bp, false);
1213         eth_dev->data->dev_started = 0;
1214         return rc;
1215 }
1216
1217 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1218 {
1219         struct bnxt *bp = eth_dev->data->dev_private;
1220         int rc = 0;
1221
1222         if (!bp->link_info->link_up)
1223                 rc = bnxt_set_hwrm_link_config(bp, true);
1224         if (!rc)
1225                 eth_dev->data->dev_link.link_status = 1;
1226
1227         bnxt_print_link_info(eth_dev);
1228         return rc;
1229 }
1230
1231 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1232 {
1233         struct bnxt *bp = eth_dev->data->dev_private;
1234
1235         eth_dev->data->dev_link.link_status = 0;
1236         bnxt_set_hwrm_link_config(bp, false);
1237         bp->link_info->link_up = 0;
1238
1239         return 0;
1240 }
1241
1242 static void bnxt_free_switch_domain(struct bnxt *bp)
1243 {
1244         if (bp->switch_domain_id)
1245                 rte_eth_switch_domain_free(bp->switch_domain_id);
1246 }
1247
1248 /* Unload the driver, release resources */
1249 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1250 {
1251         struct bnxt *bp = eth_dev->data->dev_private;
1252         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1253         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1254
1255         if (BNXT_TRUFLOW_EN(bp))
1256                 bnxt_ulp_deinit(bp);
1257
1258         eth_dev->data->dev_started = 0;
1259         /* Prevent crashes when queues are still in use */
1260         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1261         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1262
1263         bnxt_disable_int(bp);
1264
1265         /* disable uio/vfio intr/eventfd mapping */
1266         rte_intr_disable(intr_handle);
1267
1268         bnxt_cancel_fw_health_check(bp);
1269
1270         bnxt_dev_set_link_down_op(eth_dev);
1271
1272         /* Wait for link to be reset and the async notification to process.
1273          * During reset recovery, there is no need to wait and
1274          * VF/NPAR functions do not have privilege to change PHY config.
1275          */
1276         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1277                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1278
1279         /* Clean queue intr-vector mapping */
1280         rte_intr_efd_disable(intr_handle);
1281         if (intr_handle->intr_vec != NULL) {
1282                 rte_free(intr_handle->intr_vec);
1283                 intr_handle->intr_vec = NULL;
1284         }
1285
1286         bnxt_hwrm_port_clr_stats(bp);
1287         bnxt_free_tx_mbufs(bp);
1288         bnxt_free_rx_mbufs(bp);
1289         /* Process any remaining notifications in default completion queue */
1290         bnxt_int_handler(eth_dev);
1291         bnxt_shutdown_nic(bp);
1292         bnxt_hwrm_if_change(bp, false);
1293
1294         rte_free(bp->mark_table);
1295         bp->mark_table = NULL;
1296
1297         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1298         bp->rx_cosq_cnt = 0;
1299         /* All filters are deleted on a port stop. */
1300         if (BNXT_FLOW_XSTATS_EN(bp))
1301                 bp->flow_stat->flow_count = 0;
1302 }
1303
1304 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1305 {
1306         struct bnxt *bp = eth_dev->data->dev_private;
1307
1308         /* cancel the recovery handler before remove dev */
1309         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1310         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1311         bnxt_cancel_fc_thread(bp);
1312
1313         if (eth_dev->data->dev_started)
1314                 bnxt_dev_stop_op(eth_dev);
1315
1316         bnxt_free_switch_domain(bp);
1317
1318         bnxt_uninit_resources(bp, false);
1319
1320         bnxt_free_leds_info(bp);
1321         bnxt_free_cos_queues(bp);
1322         bnxt_free_link_info(bp);
1323         bnxt_free_pf_info(bp);
1324
1325         eth_dev->dev_ops = NULL;
1326         eth_dev->rx_pkt_burst = NULL;
1327         eth_dev->tx_pkt_burst = NULL;
1328
1329         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1330         bp->tx_mem_zone = NULL;
1331         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1332         bp->rx_mem_zone = NULL;
1333
1334         rte_free(bp->pf->vf_info);
1335         bp->pf->vf_info = NULL;
1336
1337         rte_free(bp->grp_info);
1338         bp->grp_info = NULL;
1339 }
1340
1341 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1342                                     uint32_t index)
1343 {
1344         struct bnxt *bp = eth_dev->data->dev_private;
1345         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1346         struct bnxt_vnic_info *vnic;
1347         struct bnxt_filter_info *filter, *temp_filter;
1348         uint32_t i;
1349
1350         if (is_bnxt_in_error(bp))
1351                 return;
1352
1353         /*
1354          * Loop through all VNICs from the specified filter flow pools to
1355          * remove the corresponding MAC addr filter
1356          */
1357         for (i = 0; i < bp->nr_vnics; i++) {
1358                 if (!(pool_mask & (1ULL << i)))
1359                         continue;
1360
1361                 vnic = &bp->vnic_info[i];
1362                 filter = STAILQ_FIRST(&vnic->filter);
1363                 while (filter) {
1364                         temp_filter = STAILQ_NEXT(filter, next);
1365                         if (filter->mac_index == index) {
1366                                 STAILQ_REMOVE(&vnic->filter, filter,
1367                                                 bnxt_filter_info, next);
1368                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1369                                 bnxt_free_filter(bp, filter);
1370                         }
1371                         filter = temp_filter;
1372                 }
1373         }
1374 }
1375
1376 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1377                                struct rte_ether_addr *mac_addr, uint32_t index,
1378                                uint32_t pool)
1379 {
1380         struct bnxt_filter_info *filter;
1381         int rc = 0;
1382
1383         /* Attach requested MAC address to the new l2_filter */
1384         STAILQ_FOREACH(filter, &vnic->filter, next) {
1385                 if (filter->mac_index == index) {
1386                         PMD_DRV_LOG(DEBUG,
1387                                     "MAC addr already existed for pool %d\n",
1388                                     pool);
1389                         return 0;
1390                 }
1391         }
1392
1393         filter = bnxt_alloc_filter(bp);
1394         if (!filter) {
1395                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1396                 return -ENODEV;
1397         }
1398
1399         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1400          * if the MAC that's been programmed now is a different one, then,
1401          * copy that addr to filter->l2_addr
1402          */
1403         if (mac_addr)
1404                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1405         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1406
1407         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1408         if (!rc) {
1409                 filter->mac_index = index;
1410                 if (filter->mac_index == 0)
1411                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1412                 else
1413                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1414         } else {
1415                 bnxt_free_filter(bp, filter);
1416         }
1417
1418         return rc;
1419 }
1420
1421 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1422                                 struct rte_ether_addr *mac_addr,
1423                                 uint32_t index, uint32_t pool)
1424 {
1425         struct bnxt *bp = eth_dev->data->dev_private;
1426         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1427         int rc = 0;
1428
1429         rc = is_bnxt_in_error(bp);
1430         if (rc)
1431                 return rc;
1432
1433         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1434                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1435                 return -ENOTSUP;
1436         }
1437
1438         if (!vnic) {
1439                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1440                 return -EINVAL;
1441         }
1442
1443         /* Filter settings will get applied when port is started */
1444         if (!eth_dev->data->dev_started)
1445                 return 0;
1446
1447         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1448
1449         return rc;
1450 }
1451
1452 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1453                      bool exp_link_status)
1454 {
1455         int rc = 0;
1456         struct bnxt *bp = eth_dev->data->dev_private;
1457         struct rte_eth_link new;
1458         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1459                   BNXT_LINK_DOWN_WAIT_CNT;
1460
1461         rc = is_bnxt_in_error(bp);
1462         if (rc)
1463                 return rc;
1464
1465         memset(&new, 0, sizeof(new));
1466         do {
1467                 /* Retrieve link info from hardware */
1468                 rc = bnxt_get_hwrm_link_config(bp, &new);
1469                 if (rc) {
1470                         new.link_speed = ETH_LINK_SPEED_100M;
1471                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1472                         PMD_DRV_LOG(ERR,
1473                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1474                         goto out;
1475                 }
1476
1477                 if (!wait_to_complete || new.link_status == exp_link_status)
1478                         break;
1479
1480                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1481         } while (cnt--);
1482
1483 out:
1484         /* Timed out or success */
1485         if (new.link_status != eth_dev->data->dev_link.link_status ||
1486         new.link_speed != eth_dev->data->dev_link.link_speed) {
1487                 rte_eth_linkstatus_set(eth_dev, &new);
1488
1489                 _rte_eth_dev_callback_process(eth_dev,
1490                                               RTE_ETH_EVENT_INTR_LSC,
1491                                               NULL);
1492
1493                 bnxt_print_link_info(eth_dev);
1494         }
1495
1496         return rc;
1497 }
1498
1499 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1500                         int wait_to_complete)
1501 {
1502         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1503 }
1504
1505 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1506 {
1507         struct bnxt *bp = eth_dev->data->dev_private;
1508         struct bnxt_vnic_info *vnic;
1509         uint32_t old_flags;
1510         int rc;
1511
1512         rc = is_bnxt_in_error(bp);
1513         if (rc)
1514                 return rc;
1515
1516         /* Filter settings will get applied when port is started */
1517         if (!eth_dev->data->dev_started)
1518                 return 0;
1519
1520         if (bp->vnic_info == NULL)
1521                 return 0;
1522
1523         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1524
1525         old_flags = vnic->flags;
1526         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1527         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1528         if (rc != 0)
1529                 vnic->flags = old_flags;
1530
1531         return rc;
1532 }
1533
1534 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1535 {
1536         struct bnxt *bp = eth_dev->data->dev_private;
1537         struct bnxt_vnic_info *vnic;
1538         uint32_t old_flags;
1539         int rc;
1540
1541         rc = is_bnxt_in_error(bp);
1542         if (rc)
1543                 return rc;
1544
1545         /* Filter settings will get applied when port is started */
1546         if (!eth_dev->data->dev_started)
1547                 return 0;
1548
1549         if (bp->vnic_info == NULL)
1550                 return 0;
1551
1552         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1553
1554         old_flags = vnic->flags;
1555         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1556         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1557         if (rc != 0)
1558                 vnic->flags = old_flags;
1559
1560         return rc;
1561 }
1562
1563 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1564 {
1565         struct bnxt *bp = eth_dev->data->dev_private;
1566         struct bnxt_vnic_info *vnic;
1567         uint32_t old_flags;
1568         int rc;
1569
1570         rc = is_bnxt_in_error(bp);
1571         if (rc)
1572                 return rc;
1573
1574         /* Filter settings will get applied when port is started */
1575         if (!eth_dev->data->dev_started)
1576                 return 0;
1577
1578         if (bp->vnic_info == NULL)
1579                 return 0;
1580
1581         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1582
1583         old_flags = vnic->flags;
1584         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1585         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1586         if (rc != 0)
1587                 vnic->flags = old_flags;
1588
1589         return rc;
1590 }
1591
1592 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1593 {
1594         struct bnxt *bp = eth_dev->data->dev_private;
1595         struct bnxt_vnic_info *vnic;
1596         uint32_t old_flags;
1597         int rc;
1598
1599         rc = is_bnxt_in_error(bp);
1600         if (rc)
1601                 return rc;
1602
1603         /* Filter settings will get applied when port is started */
1604         if (!eth_dev->data->dev_started)
1605                 return 0;
1606
1607         if (bp->vnic_info == NULL)
1608                 return 0;
1609
1610         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1611
1612         old_flags = vnic->flags;
1613         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1614         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1615         if (rc != 0)
1616                 vnic->flags = old_flags;
1617
1618         return rc;
1619 }
1620
1621 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1622 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1623 {
1624         if (qid >= bp->rx_nr_rings)
1625                 return NULL;
1626
1627         return bp->eth_dev->data->rx_queues[qid];
1628 }
1629
1630 /* Return rxq corresponding to a given rss table ring/group ID. */
1631 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1632 {
1633         struct bnxt_rx_queue *rxq;
1634         unsigned int i;
1635
1636         if (!BNXT_HAS_RING_GRPS(bp)) {
1637                 for (i = 0; i < bp->rx_nr_rings; i++) {
1638                         rxq = bp->eth_dev->data->rx_queues[i];
1639                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1640                                 return rxq->index;
1641                 }
1642         } else {
1643                 for (i = 0; i < bp->rx_nr_rings; i++) {
1644                         if (bp->grp_info[i].fw_grp_id == fwr)
1645                                 return i;
1646                 }
1647         }
1648
1649         return INVALID_HW_RING_ID;
1650 }
1651
1652 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1653                             struct rte_eth_rss_reta_entry64 *reta_conf,
1654                             uint16_t reta_size)
1655 {
1656         struct bnxt *bp = eth_dev->data->dev_private;
1657         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1658         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1659         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1660         uint16_t idx, sft;
1661         int i, rc;
1662
1663         rc = is_bnxt_in_error(bp);
1664         if (rc)
1665                 return rc;
1666
1667         if (!vnic->rss_table)
1668                 return -EINVAL;
1669
1670         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1671                 return -EINVAL;
1672
1673         if (reta_size != tbl_size) {
1674                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1675                         "(%d) must equal the size supported by the hardware "
1676                         "(%d)\n", reta_size, tbl_size);
1677                 return -EINVAL;
1678         }
1679
1680         for (i = 0; i < reta_size; i++) {
1681                 struct bnxt_rx_queue *rxq;
1682
1683                 idx = i / RTE_RETA_GROUP_SIZE;
1684                 sft = i % RTE_RETA_GROUP_SIZE;
1685
1686                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1687                         continue;
1688
1689                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1690                 if (!rxq) {
1691                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1692                         return -EINVAL;
1693                 }
1694
1695                 if (BNXT_CHIP_THOR(bp)) {
1696                         vnic->rss_table[i * 2] =
1697                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1698                         vnic->rss_table[i * 2 + 1] =
1699                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1700                 } else {
1701                         vnic->rss_table[i] =
1702                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1703                 }
1704         }
1705
1706         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1707         return 0;
1708 }
1709
1710 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1711                               struct rte_eth_rss_reta_entry64 *reta_conf,
1712                               uint16_t reta_size)
1713 {
1714         struct bnxt *bp = eth_dev->data->dev_private;
1715         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1716         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1717         uint16_t idx, sft, i;
1718         int rc;
1719
1720         rc = is_bnxt_in_error(bp);
1721         if (rc)
1722                 return rc;
1723
1724         /* Retrieve from the default VNIC */
1725         if (!vnic)
1726                 return -EINVAL;
1727         if (!vnic->rss_table)
1728                 return -EINVAL;
1729
1730         if (reta_size != tbl_size) {
1731                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1732                         "(%d) must equal the size supported by the hardware "
1733                         "(%d)\n", reta_size, tbl_size);
1734                 return -EINVAL;
1735         }
1736
1737         for (idx = 0, i = 0; i < reta_size; i++) {
1738                 idx = i / RTE_RETA_GROUP_SIZE;
1739                 sft = i % RTE_RETA_GROUP_SIZE;
1740
1741                 if (reta_conf[idx].mask & (1ULL << sft)) {
1742                         uint16_t qid;
1743
1744                         if (BNXT_CHIP_THOR(bp))
1745                                 qid = bnxt_rss_to_qid(bp,
1746                                                       vnic->rss_table[i * 2]);
1747                         else
1748                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1749
1750                         if (qid == INVALID_HW_RING_ID) {
1751                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1752                                 return -EINVAL;
1753                         }
1754                         reta_conf[idx].reta[sft] = qid;
1755                 }
1756         }
1757
1758         return 0;
1759 }
1760
1761 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1762                                    struct rte_eth_rss_conf *rss_conf)
1763 {
1764         struct bnxt *bp = eth_dev->data->dev_private;
1765         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1766         struct bnxt_vnic_info *vnic;
1767         int rc;
1768
1769         rc = is_bnxt_in_error(bp);
1770         if (rc)
1771                 return rc;
1772
1773         /*
1774          * If RSS enablement were different than dev_configure,
1775          * then return -EINVAL
1776          */
1777         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1778                 if (!rss_conf->rss_hf)
1779                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1780         } else {
1781                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1782                         return -EINVAL;
1783         }
1784
1785         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1786         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1787                rss_conf,
1788                sizeof(*rss_conf));
1789
1790         /* Update the default RSS VNIC(s) */
1791         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1792         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1793
1794         /*
1795          * If hashkey is not specified, use the previously configured
1796          * hashkey
1797          */
1798         if (!rss_conf->rss_key)
1799                 goto rss_config;
1800
1801         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1802                 PMD_DRV_LOG(ERR,
1803                             "Invalid hashkey length, should be 16 bytes\n");
1804                 return -EINVAL;
1805         }
1806         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1807
1808 rss_config:
1809         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1810         return 0;
1811 }
1812
1813 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1814                                      struct rte_eth_rss_conf *rss_conf)
1815 {
1816         struct bnxt *bp = eth_dev->data->dev_private;
1817         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1818         int len, rc;
1819         uint32_t hash_types;
1820
1821         rc = is_bnxt_in_error(bp);
1822         if (rc)
1823                 return rc;
1824
1825         /* RSS configuration is the same for all VNICs */
1826         if (vnic && vnic->rss_hash_key) {
1827                 if (rss_conf->rss_key) {
1828                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1829                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1830                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1831                 }
1832
1833                 hash_types = vnic->hash_type;
1834                 rss_conf->rss_hf = 0;
1835                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1836                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1837                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1838                 }
1839                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1840                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1841                         hash_types &=
1842                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1843                 }
1844                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1845                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1846                         hash_types &=
1847                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1848                 }
1849                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1850                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1851                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1852                 }
1853                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1854                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1855                         hash_types &=
1856                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1857                 }
1858                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1859                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1860                         hash_types &=
1861                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1862                 }
1863                 if (hash_types) {
1864                         PMD_DRV_LOG(ERR,
1865                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1866                                 vnic->hash_type);
1867                         return -ENOTSUP;
1868                 }
1869         } else {
1870                 rss_conf->rss_hf = 0;
1871         }
1872         return 0;
1873 }
1874
1875 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1876                                struct rte_eth_fc_conf *fc_conf)
1877 {
1878         struct bnxt *bp = dev->data->dev_private;
1879         struct rte_eth_link link_info;
1880         int rc;
1881
1882         rc = is_bnxt_in_error(bp);
1883         if (rc)
1884                 return rc;
1885
1886         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1887         if (rc)
1888                 return rc;
1889
1890         memset(fc_conf, 0, sizeof(*fc_conf));
1891         if (bp->link_info->auto_pause)
1892                 fc_conf->autoneg = 1;
1893         switch (bp->link_info->pause) {
1894         case 0:
1895                 fc_conf->mode = RTE_FC_NONE;
1896                 break;
1897         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1898                 fc_conf->mode = RTE_FC_TX_PAUSE;
1899                 break;
1900         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1901                 fc_conf->mode = RTE_FC_RX_PAUSE;
1902                 break;
1903         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1904                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1905                 fc_conf->mode = RTE_FC_FULL;
1906                 break;
1907         }
1908         return 0;
1909 }
1910
1911 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1912                                struct rte_eth_fc_conf *fc_conf)
1913 {
1914         struct bnxt *bp = dev->data->dev_private;
1915         int rc;
1916
1917         rc = is_bnxt_in_error(bp);
1918         if (rc)
1919                 return rc;
1920
1921         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1922                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1923                 return -ENOTSUP;
1924         }
1925
1926         switch (fc_conf->mode) {
1927         case RTE_FC_NONE:
1928                 bp->link_info->auto_pause = 0;
1929                 bp->link_info->force_pause = 0;
1930                 break;
1931         case RTE_FC_RX_PAUSE:
1932                 if (fc_conf->autoneg) {
1933                         bp->link_info->auto_pause =
1934                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1935                         bp->link_info->force_pause = 0;
1936                 } else {
1937                         bp->link_info->auto_pause = 0;
1938                         bp->link_info->force_pause =
1939                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1940                 }
1941                 break;
1942         case RTE_FC_TX_PAUSE:
1943                 if (fc_conf->autoneg) {
1944                         bp->link_info->auto_pause =
1945                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1946                         bp->link_info->force_pause = 0;
1947                 } else {
1948                         bp->link_info->auto_pause = 0;
1949                         bp->link_info->force_pause =
1950                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1951                 }
1952                 break;
1953         case RTE_FC_FULL:
1954                 if (fc_conf->autoneg) {
1955                         bp->link_info->auto_pause =
1956                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1957                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1958                         bp->link_info->force_pause = 0;
1959                 } else {
1960                         bp->link_info->auto_pause = 0;
1961                         bp->link_info->force_pause =
1962                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1963                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1964                 }
1965                 break;
1966         }
1967         return bnxt_set_hwrm_link_config(bp, true);
1968 }
1969
1970 /* Add UDP tunneling port */
1971 static int
1972 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1973                          struct rte_eth_udp_tunnel *udp_tunnel)
1974 {
1975         struct bnxt *bp = eth_dev->data->dev_private;
1976         uint16_t tunnel_type = 0;
1977         int rc = 0;
1978
1979         rc = is_bnxt_in_error(bp);
1980         if (rc)
1981                 return rc;
1982
1983         switch (udp_tunnel->prot_type) {
1984         case RTE_TUNNEL_TYPE_VXLAN:
1985                 if (bp->vxlan_port_cnt) {
1986                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1987                                 udp_tunnel->udp_port);
1988                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1989                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1990                                 return -ENOSPC;
1991                         }
1992                         bp->vxlan_port_cnt++;
1993                         return 0;
1994                 }
1995                 tunnel_type =
1996                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1997                 bp->vxlan_port_cnt++;
1998                 break;
1999         case RTE_TUNNEL_TYPE_GENEVE:
2000                 if (bp->geneve_port_cnt) {
2001                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2002                                 udp_tunnel->udp_port);
2003                         if (bp->geneve_port != udp_tunnel->udp_port) {
2004                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2005                                 return -ENOSPC;
2006                         }
2007                         bp->geneve_port_cnt++;
2008                         return 0;
2009                 }
2010                 tunnel_type =
2011                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2012                 bp->geneve_port_cnt++;
2013                 break;
2014         default:
2015                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2016                 return -ENOTSUP;
2017         }
2018         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2019                                              tunnel_type);
2020         return rc;
2021 }
2022
2023 static int
2024 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2025                          struct rte_eth_udp_tunnel *udp_tunnel)
2026 {
2027         struct bnxt *bp = eth_dev->data->dev_private;
2028         uint16_t tunnel_type = 0;
2029         uint16_t port = 0;
2030         int rc = 0;
2031
2032         rc = is_bnxt_in_error(bp);
2033         if (rc)
2034                 return rc;
2035
2036         switch (udp_tunnel->prot_type) {
2037         case RTE_TUNNEL_TYPE_VXLAN:
2038                 if (!bp->vxlan_port_cnt) {
2039                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2040                         return -EINVAL;
2041                 }
2042                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2043                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2044                                 udp_tunnel->udp_port, bp->vxlan_port);
2045                         return -EINVAL;
2046                 }
2047                 if (--bp->vxlan_port_cnt)
2048                         return 0;
2049
2050                 tunnel_type =
2051                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2052                 port = bp->vxlan_fw_dst_port_id;
2053                 break;
2054         case RTE_TUNNEL_TYPE_GENEVE:
2055                 if (!bp->geneve_port_cnt) {
2056                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2057                         return -EINVAL;
2058                 }
2059                 if (bp->geneve_port != udp_tunnel->udp_port) {
2060                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2061                                 udp_tunnel->udp_port, bp->geneve_port);
2062                         return -EINVAL;
2063                 }
2064                 if (--bp->geneve_port_cnt)
2065                         return 0;
2066
2067                 tunnel_type =
2068                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2069                 port = bp->geneve_fw_dst_port_id;
2070                 break;
2071         default:
2072                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2073                 return -ENOTSUP;
2074         }
2075
2076         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2077         if (!rc) {
2078                 if (tunnel_type ==
2079                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2080                         bp->vxlan_port = 0;
2081                 if (tunnel_type ==
2082                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2083                         bp->geneve_port = 0;
2084         }
2085         return rc;
2086 }
2087
2088 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2089 {
2090         struct bnxt_filter_info *filter;
2091         struct bnxt_vnic_info *vnic;
2092         int rc = 0;
2093         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2094
2095         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2096         filter = STAILQ_FIRST(&vnic->filter);
2097         while (filter) {
2098                 /* Search for this matching MAC+VLAN filter */
2099                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2100                         /* Delete the filter */
2101                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2102                         if (rc)
2103                                 return rc;
2104                         STAILQ_REMOVE(&vnic->filter, filter,
2105                                       bnxt_filter_info, next);
2106                         bnxt_free_filter(bp, filter);
2107                         PMD_DRV_LOG(INFO,
2108                                     "Deleted vlan filter for %d\n",
2109                                     vlan_id);
2110                         return 0;
2111                 }
2112                 filter = STAILQ_NEXT(filter, next);
2113         }
2114         return -ENOENT;
2115 }
2116
2117 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2118 {
2119         struct bnxt_filter_info *filter;
2120         struct bnxt_vnic_info *vnic;
2121         int rc = 0;
2122         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2123                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2124         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2125
2126         /* Implementation notes on the use of VNIC in this command:
2127          *
2128          * By default, these filters belong to default vnic for the function.
2129          * Once these filters are set up, only destination VNIC can be modified.
2130          * If the destination VNIC is not specified in this command,
2131          * then the HWRM shall only create an l2 context id.
2132          */
2133
2134         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2135         filter = STAILQ_FIRST(&vnic->filter);
2136         /* Check if the VLAN has already been added */
2137         while (filter) {
2138                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2139                         return -EEXIST;
2140
2141                 filter = STAILQ_NEXT(filter, next);
2142         }
2143
2144         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2145          * command to create MAC+VLAN filter with the right flags, enables set.
2146          */
2147         filter = bnxt_alloc_filter(bp);
2148         if (!filter) {
2149                 PMD_DRV_LOG(ERR,
2150                             "MAC/VLAN filter alloc failed\n");
2151                 return -ENOMEM;
2152         }
2153         /* MAC + VLAN ID filter */
2154         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2155          * untagged packets are received
2156          *
2157          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2158          * packets and only the programmed vlan's packets are received
2159          */
2160         filter->l2_ivlan = vlan_id;
2161         filter->l2_ivlan_mask = 0x0FFF;
2162         filter->enables |= en;
2163         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2164
2165         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2166         if (rc) {
2167                 /* Free the newly allocated filter as we were
2168                  * not able to create the filter in hardware.
2169                  */
2170                 bnxt_free_filter(bp, filter);
2171                 return rc;
2172         }
2173
2174         filter->mac_index = 0;
2175         /* Add this new filter to the list */
2176         if (vlan_id == 0)
2177                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2178         else
2179                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2180
2181         PMD_DRV_LOG(INFO,
2182                     "Added Vlan filter for %d\n", vlan_id);
2183         return rc;
2184 }
2185
2186 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2187                 uint16_t vlan_id, int on)
2188 {
2189         struct bnxt *bp = eth_dev->data->dev_private;
2190         int rc;
2191
2192         rc = is_bnxt_in_error(bp);
2193         if (rc)
2194                 return rc;
2195
2196         if (!eth_dev->data->dev_started) {
2197                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2198                 return -EINVAL;
2199         }
2200
2201         /* These operations apply to ALL existing MAC/VLAN filters */
2202         if (on)
2203                 return bnxt_add_vlan_filter(bp, vlan_id);
2204         else
2205                 return bnxt_del_vlan_filter(bp, vlan_id);
2206 }
2207
2208 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2209                                     struct bnxt_vnic_info *vnic)
2210 {
2211         struct bnxt_filter_info *filter;
2212         int rc;
2213
2214         filter = STAILQ_FIRST(&vnic->filter);
2215         while (filter) {
2216                 if (filter->mac_index == 0 &&
2217                     !memcmp(filter->l2_addr, bp->mac_addr,
2218                             RTE_ETHER_ADDR_LEN)) {
2219                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2220                         if (!rc) {
2221                                 STAILQ_REMOVE(&vnic->filter, filter,
2222                                               bnxt_filter_info, next);
2223                                 bnxt_free_filter(bp, filter);
2224                         }
2225                         return rc;
2226                 }
2227                 filter = STAILQ_NEXT(filter, next);
2228         }
2229         return 0;
2230 }
2231
2232 static int
2233 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2234 {
2235         struct bnxt_vnic_info *vnic;
2236         unsigned int i;
2237         int rc;
2238
2239         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2240         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2241                 /* Remove any VLAN filters programmed */
2242                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2243                         bnxt_del_vlan_filter(bp, i);
2244
2245                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2246                 if (rc)
2247                         return rc;
2248         } else {
2249                 /* Default filter will allow packets that match the
2250                  * dest mac. So, it has to be deleted, otherwise, we
2251                  * will endup receiving vlan packets for which the
2252                  * filter is not programmed, when hw-vlan-filter
2253                  * configuration is ON
2254                  */
2255                 bnxt_del_dflt_mac_filter(bp, vnic);
2256                 /* This filter will allow only untagged packets */
2257                 bnxt_add_vlan_filter(bp, 0);
2258         }
2259         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2260                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2261
2262         return 0;
2263 }
2264
2265 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2266 {
2267         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2268         unsigned int i;
2269         int rc;
2270
2271         /* Destroy vnic filters and vnic */
2272         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2273             DEV_RX_OFFLOAD_VLAN_FILTER) {
2274                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2275                         bnxt_del_vlan_filter(bp, i);
2276         }
2277         bnxt_del_dflt_mac_filter(bp, vnic);
2278
2279         rc = bnxt_hwrm_vnic_free(bp, vnic);
2280         if (rc)
2281                 return rc;
2282
2283         rte_free(vnic->fw_grp_ids);
2284         vnic->fw_grp_ids = NULL;
2285
2286         vnic->rx_queue_cnt = 0;
2287
2288         return 0;
2289 }
2290
2291 static int
2292 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2293 {
2294         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2295         int rc;
2296
2297         /* Destroy, recreate and reconfigure the default vnic */
2298         rc = bnxt_free_one_vnic(bp, 0);
2299         if (rc)
2300                 return rc;
2301
2302         /* default vnic 0 */
2303         rc = bnxt_setup_one_vnic(bp, 0);
2304         if (rc)
2305                 return rc;
2306
2307         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2308             DEV_RX_OFFLOAD_VLAN_FILTER) {
2309                 rc = bnxt_add_vlan_filter(bp, 0);
2310                 if (rc)
2311                         return rc;
2312                 rc = bnxt_restore_vlan_filters(bp);
2313                 if (rc)
2314                         return rc;
2315         } else {
2316                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2317                 if (rc)
2318                         return rc;
2319         }
2320
2321         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2322         if (rc)
2323                 return rc;
2324
2325         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2326                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2327
2328         return rc;
2329 }
2330
2331 static int
2332 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2333 {
2334         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2335         struct bnxt *bp = dev->data->dev_private;
2336         int rc;
2337
2338         rc = is_bnxt_in_error(bp);
2339         if (rc)
2340                 return rc;
2341
2342         /* Filter settings will get applied when port is started */
2343         if (!dev->data->dev_started)
2344                 return 0;
2345
2346         if (mask & ETH_VLAN_FILTER_MASK) {
2347                 /* Enable or disable VLAN filtering */
2348                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2349                 if (rc)
2350                         return rc;
2351         }
2352
2353         if (mask & ETH_VLAN_STRIP_MASK) {
2354                 /* Enable or disable VLAN stripping */
2355                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2356                 if (rc)
2357                         return rc;
2358         }
2359
2360         if (mask & ETH_VLAN_EXTEND_MASK) {
2361                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2362                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2363                 else
2364                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2365         }
2366
2367         return 0;
2368 }
2369
2370 static int
2371 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2372                       uint16_t tpid)
2373 {
2374         struct bnxt *bp = dev->data->dev_private;
2375         int qinq = dev->data->dev_conf.rxmode.offloads &
2376                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2377
2378         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2379             vlan_type != ETH_VLAN_TYPE_OUTER) {
2380                 PMD_DRV_LOG(ERR,
2381                             "Unsupported vlan type.");
2382                 return -EINVAL;
2383         }
2384         if (!qinq) {
2385                 PMD_DRV_LOG(ERR,
2386                             "QinQ not enabled. Needs to be ON as we can "
2387                             "accelerate only outer vlan\n");
2388                 return -EINVAL;
2389         }
2390
2391         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2392                 switch (tpid) {
2393                 case RTE_ETHER_TYPE_QINQ:
2394                         bp->outer_tpid_bd =
2395                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2396                                 break;
2397                 case RTE_ETHER_TYPE_VLAN:
2398                         bp->outer_tpid_bd =
2399                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2400                                 break;
2401                 case 0x9100:
2402                         bp->outer_tpid_bd =
2403                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2404                                 break;
2405                 case 0x9200:
2406                         bp->outer_tpid_bd =
2407                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2408                                 break;
2409                 case 0x9300:
2410                         bp->outer_tpid_bd =
2411                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2412                                 break;
2413                 default:
2414                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2415                         return -EINVAL;
2416                 }
2417                 bp->outer_tpid_bd |= tpid;
2418                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2419         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2420                 PMD_DRV_LOG(ERR,
2421                             "Can accelerate only outer vlan in QinQ\n");
2422                 return -EINVAL;
2423         }
2424
2425         return 0;
2426 }
2427
2428 static int
2429 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2430                              struct rte_ether_addr *addr)
2431 {
2432         struct bnxt *bp = dev->data->dev_private;
2433         /* Default Filter is tied to VNIC 0 */
2434         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2435         int rc;
2436
2437         rc = is_bnxt_in_error(bp);
2438         if (rc)
2439                 return rc;
2440
2441         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2442                 return -EPERM;
2443
2444         if (rte_is_zero_ether_addr(addr))
2445                 return -EINVAL;
2446
2447         /* Filter settings will get applied when port is started */
2448         if (!dev->data->dev_started)
2449                 return 0;
2450
2451         /* Check if the requested MAC is already added */
2452         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2453                 return 0;
2454
2455         /* Destroy filter and re-create it */
2456         bnxt_del_dflt_mac_filter(bp, vnic);
2457
2458         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2459         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2460                 /* This filter will allow only untagged packets */
2461                 rc = bnxt_add_vlan_filter(bp, 0);
2462         } else {
2463                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2464         }
2465
2466         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2467         return rc;
2468 }
2469
2470 static int
2471 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2472                           struct rte_ether_addr *mc_addr_set,
2473                           uint32_t nb_mc_addr)
2474 {
2475         struct bnxt *bp = eth_dev->data->dev_private;
2476         char *mc_addr_list = (char *)mc_addr_set;
2477         struct bnxt_vnic_info *vnic;
2478         uint32_t off = 0, i = 0;
2479         int rc;
2480
2481         rc = is_bnxt_in_error(bp);
2482         if (rc)
2483                 return rc;
2484
2485         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2486
2487         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2488                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2489                 goto allmulti;
2490         }
2491
2492         /* TODO Check for Duplicate mcast addresses */
2493         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2494         for (i = 0; i < nb_mc_addr; i++) {
2495                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2496                         RTE_ETHER_ADDR_LEN);
2497                 off += RTE_ETHER_ADDR_LEN;
2498         }
2499
2500         vnic->mc_addr_cnt = i;
2501         if (vnic->mc_addr_cnt)
2502                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2503         else
2504                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2505
2506 allmulti:
2507         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2508 }
2509
2510 static int
2511 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2512 {
2513         struct bnxt *bp = dev->data->dev_private;
2514         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2515         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2516         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2517         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2518         int ret;
2519
2520         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2521                         fw_major, fw_minor, fw_updt, fw_rsvd);
2522
2523         ret += 1; /* add the size of '\0' */
2524         if (fw_size < (uint32_t)ret)
2525                 return ret;
2526         else
2527                 return 0;
2528 }
2529
2530 static void
2531 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2532         struct rte_eth_rxq_info *qinfo)
2533 {
2534         struct bnxt *bp = dev->data->dev_private;
2535         struct bnxt_rx_queue *rxq;
2536
2537         if (is_bnxt_in_error(bp))
2538                 return;
2539
2540         rxq = dev->data->rx_queues[queue_id];
2541
2542         qinfo->mp = rxq->mb_pool;
2543         qinfo->scattered_rx = dev->data->scattered_rx;
2544         qinfo->nb_desc = rxq->nb_rx_desc;
2545
2546         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2547         qinfo->conf.rx_drop_en = 0;
2548         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2549 }
2550
2551 static void
2552 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2553         struct rte_eth_txq_info *qinfo)
2554 {
2555         struct bnxt *bp = dev->data->dev_private;
2556         struct bnxt_tx_queue *txq;
2557
2558         if (is_bnxt_in_error(bp))
2559                 return;
2560
2561         txq = dev->data->tx_queues[queue_id];
2562
2563         qinfo->nb_desc = txq->nb_tx_desc;
2564
2565         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2566         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2567         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2568
2569         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2570         qinfo->conf.tx_rs_thresh = 0;
2571         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2572 }
2573
2574 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2575 {
2576         struct bnxt *bp = eth_dev->data->dev_private;
2577         uint32_t new_pkt_size;
2578         uint32_t rc = 0;
2579         uint32_t i;
2580
2581         rc = is_bnxt_in_error(bp);
2582         if (rc)
2583                 return rc;
2584
2585         /* Exit if receive queues are not configured yet */
2586         if (!eth_dev->data->nb_rx_queues)
2587                 return rc;
2588
2589         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2590                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2591
2592 #ifdef RTE_ARCH_X86
2593         /*
2594          * If vector-mode tx/rx is active, disallow any MTU change that would
2595          * require scattered receive support.
2596          */
2597         if (eth_dev->data->dev_started &&
2598             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2599              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2600             (new_pkt_size >
2601              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2602                 PMD_DRV_LOG(ERR,
2603                             "MTU change would require scattered rx support. ");
2604                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2605                 return -EINVAL;
2606         }
2607 #endif
2608
2609         if (new_mtu > RTE_ETHER_MTU) {
2610                 bp->flags |= BNXT_FLAG_JUMBO;
2611                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2612                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2613         } else {
2614                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2615                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2616                 bp->flags &= ~BNXT_FLAG_JUMBO;
2617         }
2618
2619         /* Is there a change in mtu setting? */
2620         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2621                 return rc;
2622
2623         for (i = 0; i < bp->nr_vnics; i++) {
2624                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2625                 uint16_t size = 0;
2626
2627                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2628                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2629                 if (rc)
2630                         break;
2631
2632                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2633                 size -= RTE_PKTMBUF_HEADROOM;
2634
2635                 if (size < new_mtu) {
2636                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2637                         if (rc)
2638                                 return rc;
2639                 }
2640         }
2641
2642         if (!rc)
2643                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2644
2645         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2646
2647         return rc;
2648 }
2649
2650 static int
2651 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2652 {
2653         struct bnxt *bp = dev->data->dev_private;
2654         uint16_t vlan = bp->vlan;
2655         int rc;
2656
2657         rc = is_bnxt_in_error(bp);
2658         if (rc)
2659                 return rc;
2660
2661         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2662                 PMD_DRV_LOG(ERR,
2663                         "PVID cannot be modified for this function\n");
2664                 return -ENOTSUP;
2665         }
2666         bp->vlan = on ? pvid : 0;
2667
2668         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2669         if (rc)
2670                 bp->vlan = vlan;
2671         return rc;
2672 }
2673
2674 static int
2675 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2676 {
2677         struct bnxt *bp = dev->data->dev_private;
2678         int rc;
2679
2680         rc = is_bnxt_in_error(bp);
2681         if (rc)
2682                 return rc;
2683
2684         return bnxt_hwrm_port_led_cfg(bp, true);
2685 }
2686
2687 static int
2688 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2689 {
2690         struct bnxt *bp = dev->data->dev_private;
2691         int rc;
2692
2693         rc = is_bnxt_in_error(bp);
2694         if (rc)
2695                 return rc;
2696
2697         return bnxt_hwrm_port_led_cfg(bp, false);
2698 }
2699
2700 static uint32_t
2701 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2702 {
2703         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2704         uint32_t desc = 0, raw_cons = 0, cons;
2705         struct bnxt_cp_ring_info *cpr;
2706         struct bnxt_rx_queue *rxq;
2707         struct rx_pkt_cmpl *rxcmp;
2708         int rc;
2709
2710         rc = is_bnxt_in_error(bp);
2711         if (rc)
2712                 return rc;
2713
2714         rxq = dev->data->rx_queues[rx_queue_id];
2715         cpr = rxq->cp_ring;
2716         raw_cons = cpr->cp_raw_cons;
2717
2718         while (1) {
2719                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2720                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2721                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2722
2723                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2724                         break;
2725                 } else {
2726                         raw_cons++;
2727                         desc++;
2728                 }
2729         }
2730
2731         return desc;
2732 }
2733
2734 static int
2735 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2736 {
2737         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2738         struct bnxt_rx_ring_info *rxr;
2739         struct bnxt_cp_ring_info *cpr;
2740         struct bnxt_sw_rx_bd *rx_buf;
2741         struct rx_pkt_cmpl *rxcmp;
2742         uint32_t cons, cp_cons;
2743         int rc;
2744
2745         if (!rxq)
2746                 return -EINVAL;
2747
2748         rc = is_bnxt_in_error(rxq->bp);
2749         if (rc)
2750                 return rc;
2751
2752         cpr = rxq->cp_ring;
2753         rxr = rxq->rx_ring;
2754
2755         if (offset >= rxq->nb_rx_desc)
2756                 return -EINVAL;
2757
2758         cons = RING_CMP(cpr->cp_ring_struct, offset);
2759         cp_cons = cpr->cp_raw_cons;
2760         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2761
2762         if (cons > cp_cons) {
2763                 if (CMPL_VALID(rxcmp, cpr->valid))
2764                         return RTE_ETH_RX_DESC_DONE;
2765         } else {
2766                 if (CMPL_VALID(rxcmp, !cpr->valid))
2767                         return RTE_ETH_RX_DESC_DONE;
2768         }
2769         rx_buf = &rxr->rx_buf_ring[cons];
2770         if (rx_buf->mbuf == NULL)
2771                 return RTE_ETH_RX_DESC_UNAVAIL;
2772
2773
2774         return RTE_ETH_RX_DESC_AVAIL;
2775 }
2776
2777 static int
2778 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2779 {
2780         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2781         struct bnxt_tx_ring_info *txr;
2782         struct bnxt_cp_ring_info *cpr;
2783         struct bnxt_sw_tx_bd *tx_buf;
2784         struct tx_pkt_cmpl *txcmp;
2785         uint32_t cons, cp_cons;
2786         int rc;
2787
2788         if (!txq)
2789                 return -EINVAL;
2790
2791         rc = is_bnxt_in_error(txq->bp);
2792         if (rc)
2793                 return rc;
2794
2795         cpr = txq->cp_ring;
2796         txr = txq->tx_ring;
2797
2798         if (offset >= txq->nb_tx_desc)
2799                 return -EINVAL;
2800
2801         cons = RING_CMP(cpr->cp_ring_struct, offset);
2802         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2803         cp_cons = cpr->cp_raw_cons;
2804
2805         if (cons > cp_cons) {
2806                 if (CMPL_VALID(txcmp, cpr->valid))
2807                         return RTE_ETH_TX_DESC_UNAVAIL;
2808         } else {
2809                 if (CMPL_VALID(txcmp, !cpr->valid))
2810                         return RTE_ETH_TX_DESC_UNAVAIL;
2811         }
2812         tx_buf = &txr->tx_buf_ring[cons];
2813         if (tx_buf->mbuf == NULL)
2814                 return RTE_ETH_TX_DESC_DONE;
2815
2816         return RTE_ETH_TX_DESC_FULL;
2817 }
2818
2819 static struct bnxt_filter_info *
2820 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2821                                 struct rte_eth_ethertype_filter *efilter,
2822                                 struct bnxt_vnic_info *vnic0,
2823                                 struct bnxt_vnic_info *vnic,
2824                                 int *ret)
2825 {
2826         struct bnxt_filter_info *mfilter = NULL;
2827         int match = 0;
2828         *ret = 0;
2829
2830         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2831                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2832                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2833                         " ethertype filter.", efilter->ether_type);
2834                 *ret = -EINVAL;
2835                 goto exit;
2836         }
2837         if (efilter->queue >= bp->rx_nr_rings) {
2838                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2839                 *ret = -EINVAL;
2840                 goto exit;
2841         }
2842
2843         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2844         vnic = &bp->vnic_info[efilter->queue];
2845         if (vnic == NULL) {
2846                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2847                 *ret = -EINVAL;
2848                 goto exit;
2849         }
2850
2851         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2852                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2853                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2854                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2855                              mfilter->flags ==
2856                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2857                              mfilter->ethertype == efilter->ether_type)) {
2858                                 match = 1;
2859                                 break;
2860                         }
2861                 }
2862         } else {
2863                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2864                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2865                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2866                              mfilter->ethertype == efilter->ether_type &&
2867                              mfilter->flags ==
2868                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2869                                 match = 1;
2870                                 break;
2871                         }
2872         }
2873
2874         if (match)
2875                 *ret = -EEXIST;
2876
2877 exit:
2878         return mfilter;
2879 }
2880
2881 static int
2882 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2883                         enum rte_filter_op filter_op,
2884                         void *arg)
2885 {
2886         struct bnxt *bp = dev->data->dev_private;
2887         struct rte_eth_ethertype_filter *efilter =
2888                         (struct rte_eth_ethertype_filter *)arg;
2889         struct bnxt_filter_info *bfilter, *filter1;
2890         struct bnxt_vnic_info *vnic, *vnic0;
2891         int ret;
2892
2893         if (filter_op == RTE_ETH_FILTER_NOP)
2894                 return 0;
2895
2896         if (arg == NULL) {
2897                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2898                             filter_op);
2899                 return -EINVAL;
2900         }
2901
2902         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2903         vnic = &bp->vnic_info[efilter->queue];
2904
2905         switch (filter_op) {
2906         case RTE_ETH_FILTER_ADD:
2907                 bnxt_match_and_validate_ether_filter(bp, efilter,
2908                                                         vnic0, vnic, &ret);
2909                 if (ret < 0)
2910                         return ret;
2911
2912                 bfilter = bnxt_get_unused_filter(bp);
2913                 if (bfilter == NULL) {
2914                         PMD_DRV_LOG(ERR,
2915                                 "Not enough resources for a new filter.\n");
2916                         return -ENOMEM;
2917                 }
2918                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2919                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2920                        RTE_ETHER_ADDR_LEN);
2921                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2922                        RTE_ETHER_ADDR_LEN);
2923                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2924                 bfilter->ethertype = efilter->ether_type;
2925                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2926
2927                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2928                 if (filter1 == NULL) {
2929                         ret = -EINVAL;
2930                         goto cleanup;
2931                 }
2932                 bfilter->enables |=
2933                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2934                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2935
2936                 bfilter->dst_id = vnic->fw_vnic_id;
2937
2938                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2939                         bfilter->flags =
2940                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2941                 }
2942
2943                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2944                 if (ret)
2945                         goto cleanup;
2946                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2947                 break;
2948         case RTE_ETH_FILTER_DELETE:
2949                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2950                                                         vnic0, vnic, &ret);
2951                 if (ret == -EEXIST) {
2952                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2953
2954                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2955                                       next);
2956                         bnxt_free_filter(bp, filter1);
2957                 } else if (ret == 0) {
2958                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2959                 }
2960                 break;
2961         default:
2962                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2963                 ret = -EINVAL;
2964                 goto error;
2965         }
2966         return ret;
2967 cleanup:
2968         bnxt_free_filter(bp, bfilter);
2969 error:
2970         return ret;
2971 }
2972
2973 static inline int
2974 parse_ntuple_filter(struct bnxt *bp,
2975                     struct rte_eth_ntuple_filter *nfilter,
2976                     struct bnxt_filter_info *bfilter)
2977 {
2978         uint32_t en = 0;
2979
2980         if (nfilter->queue >= bp->rx_nr_rings) {
2981                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2982                 return -EINVAL;
2983         }
2984
2985         switch (nfilter->dst_port_mask) {
2986         case UINT16_MAX:
2987                 bfilter->dst_port_mask = -1;
2988                 bfilter->dst_port = nfilter->dst_port;
2989                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2990                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2991                 break;
2992         default:
2993                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2994                 return -EINVAL;
2995         }
2996
2997         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2998         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2999
3000         switch (nfilter->proto_mask) {
3001         case UINT8_MAX:
3002                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3003                         bfilter->ip_protocol = 17;
3004                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3005                         bfilter->ip_protocol = 6;
3006                 else
3007                         return -EINVAL;
3008                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3009                 break;
3010         default:
3011                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3012                 return -EINVAL;
3013         }
3014
3015         switch (nfilter->dst_ip_mask) {
3016         case UINT32_MAX:
3017                 bfilter->dst_ipaddr_mask[0] = -1;
3018                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3019                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3020                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3021                 break;
3022         default:
3023                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3024                 return -EINVAL;
3025         }
3026
3027         switch (nfilter->src_ip_mask) {
3028         case UINT32_MAX:
3029                 bfilter->src_ipaddr_mask[0] = -1;
3030                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3031                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3032                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3033                 break;
3034         default:
3035                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3036                 return -EINVAL;
3037         }
3038
3039         switch (nfilter->src_port_mask) {
3040         case UINT16_MAX:
3041                 bfilter->src_port_mask = -1;
3042                 bfilter->src_port = nfilter->src_port;
3043                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3044                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3045                 break;
3046         default:
3047                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3048                 return -EINVAL;
3049         }
3050
3051         bfilter->enables = en;
3052         return 0;
3053 }
3054
3055 static struct bnxt_filter_info*
3056 bnxt_match_ntuple_filter(struct bnxt *bp,
3057                          struct bnxt_filter_info *bfilter,
3058                          struct bnxt_vnic_info **mvnic)
3059 {
3060         struct bnxt_filter_info *mfilter = NULL;
3061         int i;
3062
3063         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3064                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3065                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3066                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3067                             bfilter->src_ipaddr_mask[0] ==
3068                             mfilter->src_ipaddr_mask[0] &&
3069                             bfilter->src_port == mfilter->src_port &&
3070                             bfilter->src_port_mask == mfilter->src_port_mask &&
3071                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3072                             bfilter->dst_ipaddr_mask[0] ==
3073                             mfilter->dst_ipaddr_mask[0] &&
3074                             bfilter->dst_port == mfilter->dst_port &&
3075                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3076                             bfilter->flags == mfilter->flags &&
3077                             bfilter->enables == mfilter->enables) {
3078                                 if (mvnic)
3079                                         *mvnic = vnic;
3080                                 return mfilter;
3081                         }
3082                 }
3083         }
3084         return NULL;
3085 }
3086
3087 static int
3088 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3089                        struct rte_eth_ntuple_filter *nfilter,
3090                        enum rte_filter_op filter_op)
3091 {
3092         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3093         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3094         int ret;
3095
3096         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3097                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3098                 return -EINVAL;
3099         }
3100
3101         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3102                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3103                 return -EINVAL;
3104         }
3105
3106         bfilter = bnxt_get_unused_filter(bp);
3107         if (bfilter == NULL) {
3108                 PMD_DRV_LOG(ERR,
3109                         "Not enough resources for a new filter.\n");
3110                 return -ENOMEM;
3111         }
3112         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3113         if (ret < 0)
3114                 goto free_filter;
3115
3116         vnic = &bp->vnic_info[nfilter->queue];
3117         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3118         filter1 = STAILQ_FIRST(&vnic0->filter);
3119         if (filter1 == NULL) {
3120                 ret = -EINVAL;
3121                 goto free_filter;
3122         }
3123
3124         bfilter->dst_id = vnic->fw_vnic_id;
3125         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3126         bfilter->enables |=
3127                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3128         bfilter->ethertype = 0x800;
3129         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3130
3131         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3132
3133         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3134             bfilter->dst_id == mfilter->dst_id) {
3135                 PMD_DRV_LOG(ERR, "filter exists.\n");
3136                 ret = -EEXIST;
3137                 goto free_filter;
3138         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3139                    bfilter->dst_id != mfilter->dst_id) {
3140                 mfilter->dst_id = vnic->fw_vnic_id;
3141                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3142                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3143                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3144                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3145                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3146                 goto free_filter;
3147         }
3148         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3149                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3150                 ret = -ENOENT;
3151                 goto free_filter;
3152         }
3153
3154         if (filter_op == RTE_ETH_FILTER_ADD) {
3155                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3156                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3157                 if (ret)
3158                         goto free_filter;
3159                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3160         } else {
3161                 if (mfilter == NULL) {
3162                         /* This should not happen. But for Coverity! */
3163                         ret = -ENOENT;
3164                         goto free_filter;
3165                 }
3166                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3167
3168                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3169                 bnxt_free_filter(bp, mfilter);
3170                 bnxt_free_filter(bp, bfilter);
3171         }
3172
3173         return 0;
3174 free_filter:
3175         bnxt_free_filter(bp, bfilter);
3176         return ret;
3177 }
3178
3179 static int
3180 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3181                         enum rte_filter_op filter_op,
3182                         void *arg)
3183 {
3184         struct bnxt *bp = dev->data->dev_private;
3185         int ret;
3186
3187         if (filter_op == RTE_ETH_FILTER_NOP)
3188                 return 0;
3189
3190         if (arg == NULL) {
3191                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3192                             filter_op);
3193                 return -EINVAL;
3194         }
3195
3196         switch (filter_op) {
3197         case RTE_ETH_FILTER_ADD:
3198                 ret = bnxt_cfg_ntuple_filter(bp,
3199                         (struct rte_eth_ntuple_filter *)arg,
3200                         filter_op);
3201                 break;
3202         case RTE_ETH_FILTER_DELETE:
3203                 ret = bnxt_cfg_ntuple_filter(bp,
3204                         (struct rte_eth_ntuple_filter *)arg,
3205                         filter_op);
3206                 break;
3207         default:
3208                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3209                 ret = -EINVAL;
3210                 break;
3211         }
3212         return ret;
3213 }
3214
3215 static int
3216 bnxt_parse_fdir_filter(struct bnxt *bp,
3217                        struct rte_eth_fdir_filter *fdir,
3218                        struct bnxt_filter_info *filter)
3219 {
3220         enum rte_fdir_mode fdir_mode =
3221                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3222         struct bnxt_vnic_info *vnic0, *vnic;
3223         struct bnxt_filter_info *filter1;
3224         uint32_t en = 0;
3225         int i;
3226
3227         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3228                 return -EINVAL;
3229
3230         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3231         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3232
3233         switch (fdir->input.flow_type) {
3234         case RTE_ETH_FLOW_IPV4:
3235         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3236                 /* FALLTHROUGH */
3237                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3238                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3239                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3240                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3241                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3242                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3243                 filter->ip_addr_type =
3244                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3245                 filter->src_ipaddr_mask[0] = 0xffffffff;
3246                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3247                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3248                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3249                 filter->ethertype = 0x800;
3250                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3251                 break;
3252         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3253                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3254                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3255                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3256                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3257                 filter->dst_port_mask = 0xffff;
3258                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3259                 filter->src_port_mask = 0xffff;
3260                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3261                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3262                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3263                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3264                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3265                 filter->ip_protocol = 6;
3266                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3267                 filter->ip_addr_type =
3268                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3269                 filter->src_ipaddr_mask[0] = 0xffffffff;
3270                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3271                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3272                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3273                 filter->ethertype = 0x800;
3274                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3275                 break;
3276         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3277                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3278                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3279                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3280                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3281                 filter->dst_port_mask = 0xffff;
3282                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3283                 filter->src_port_mask = 0xffff;
3284                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3285                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3286                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3287                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3288                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3289                 filter->ip_protocol = 17;
3290                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3291                 filter->ip_addr_type =
3292                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3293                 filter->src_ipaddr_mask[0] = 0xffffffff;
3294                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3295                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3296                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3297                 filter->ethertype = 0x800;
3298                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3299                 break;
3300         case RTE_ETH_FLOW_IPV6:
3301         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3302                 /* FALLTHROUGH */
3303                 filter->ip_addr_type =
3304                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3305                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3306                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3307                 rte_memcpy(filter->src_ipaddr,
3308                            fdir->input.flow.ipv6_flow.src_ip, 16);
3309                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3310                 rte_memcpy(filter->dst_ipaddr,
3311                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3312                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3313                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3314                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3315                 memset(filter->src_ipaddr_mask, 0xff, 16);
3316                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3317                 filter->ethertype = 0x86dd;
3318                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3319                 break;
3320         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3321                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3322                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3323                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3324                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3325                 filter->dst_port_mask = 0xffff;
3326                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3327                 filter->src_port_mask = 0xffff;
3328                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3329                 filter->ip_addr_type =
3330                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3331                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3332                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3333                 rte_memcpy(filter->src_ipaddr,
3334                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3335                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3336                 rte_memcpy(filter->dst_ipaddr,
3337                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3338                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3339                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3340                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3341                 memset(filter->src_ipaddr_mask, 0xff, 16);
3342                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3343                 filter->ethertype = 0x86dd;
3344                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3345                 break;
3346         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3347                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3348                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3349                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3350                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3351                 filter->dst_port_mask = 0xffff;
3352                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3353                 filter->src_port_mask = 0xffff;
3354                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3355                 filter->ip_addr_type =
3356                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3357                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3358                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3359                 rte_memcpy(filter->src_ipaddr,
3360                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3361                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3362                 rte_memcpy(filter->dst_ipaddr,
3363                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3364                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3365                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3366                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3367                 memset(filter->src_ipaddr_mask, 0xff, 16);
3368                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3369                 filter->ethertype = 0x86dd;
3370                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3371                 break;
3372         case RTE_ETH_FLOW_L2_PAYLOAD:
3373                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3374                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3375                 break;
3376         case RTE_ETH_FLOW_VXLAN:
3377                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3378                         return -EINVAL;
3379                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3380                 filter->tunnel_type =
3381                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3382                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3383                 break;
3384         case RTE_ETH_FLOW_NVGRE:
3385                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3386                         return -EINVAL;
3387                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3388                 filter->tunnel_type =
3389                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3390                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3391                 break;
3392         case RTE_ETH_FLOW_UNKNOWN:
3393         case RTE_ETH_FLOW_RAW:
3394         case RTE_ETH_FLOW_FRAG_IPV4:
3395         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3396         case RTE_ETH_FLOW_FRAG_IPV6:
3397         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3398         case RTE_ETH_FLOW_IPV6_EX:
3399         case RTE_ETH_FLOW_IPV6_TCP_EX:
3400         case RTE_ETH_FLOW_IPV6_UDP_EX:
3401         case RTE_ETH_FLOW_GENEVE:
3402                 /* FALLTHROUGH */
3403         default:
3404                 return -EINVAL;
3405         }
3406
3407         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3408         vnic = &bp->vnic_info[fdir->action.rx_queue];
3409         if (vnic == NULL) {
3410                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3411                 return -EINVAL;
3412         }
3413
3414         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3415                 rte_memcpy(filter->dst_macaddr,
3416                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3417                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3418         }
3419
3420         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3421                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3422                 filter1 = STAILQ_FIRST(&vnic0->filter);
3423                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3424         } else {
3425                 filter->dst_id = vnic->fw_vnic_id;
3426                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3427                         if (filter->dst_macaddr[i] == 0x00)
3428                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3429                         else
3430                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3431         }
3432
3433         if (filter1 == NULL)
3434                 return -EINVAL;
3435
3436         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3437         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3438
3439         filter->enables = en;
3440
3441         return 0;
3442 }
3443
3444 static struct bnxt_filter_info *
3445 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3446                 struct bnxt_vnic_info **mvnic)
3447 {
3448         struct bnxt_filter_info *mf = NULL;
3449         int i;
3450
3451         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3452                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3453
3454                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3455                         if (mf->filter_type == nf->filter_type &&
3456                             mf->flags == nf->flags &&
3457                             mf->src_port == nf->src_port &&
3458                             mf->src_port_mask == nf->src_port_mask &&
3459                             mf->dst_port == nf->dst_port &&
3460                             mf->dst_port_mask == nf->dst_port_mask &&
3461                             mf->ip_protocol == nf->ip_protocol &&
3462                             mf->ip_addr_type == nf->ip_addr_type &&
3463                             mf->ethertype == nf->ethertype &&
3464                             mf->vni == nf->vni &&
3465                             mf->tunnel_type == nf->tunnel_type &&
3466                             mf->l2_ovlan == nf->l2_ovlan &&
3467                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3468                             mf->l2_ivlan == nf->l2_ivlan &&
3469                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3470                             !memcmp(mf->l2_addr, nf->l2_addr,
3471                                     RTE_ETHER_ADDR_LEN) &&
3472                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3473                                     RTE_ETHER_ADDR_LEN) &&
3474                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3475                                     RTE_ETHER_ADDR_LEN) &&
3476                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3477                                     RTE_ETHER_ADDR_LEN) &&
3478                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3479                                     sizeof(nf->src_ipaddr)) &&
3480                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3481                                     sizeof(nf->src_ipaddr_mask)) &&
3482                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3483                                     sizeof(nf->dst_ipaddr)) &&
3484                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3485                                     sizeof(nf->dst_ipaddr_mask))) {
3486                                 if (mvnic)
3487                                         *mvnic = vnic;
3488                                 return mf;
3489                         }
3490                 }
3491         }
3492         return NULL;
3493 }
3494
3495 static int
3496 bnxt_fdir_filter(struct rte_eth_dev *dev,
3497                  enum rte_filter_op filter_op,
3498                  void *arg)
3499 {
3500         struct bnxt *bp = dev->data->dev_private;
3501         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3502         struct bnxt_filter_info *filter, *match;
3503         struct bnxt_vnic_info *vnic, *mvnic;
3504         int ret = 0, i;
3505
3506         if (filter_op == RTE_ETH_FILTER_NOP)
3507                 return 0;
3508
3509         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3510                 return -EINVAL;
3511
3512         switch (filter_op) {
3513         case RTE_ETH_FILTER_ADD:
3514         case RTE_ETH_FILTER_DELETE:
3515                 /* FALLTHROUGH */
3516                 filter = bnxt_get_unused_filter(bp);
3517                 if (filter == NULL) {
3518                         PMD_DRV_LOG(ERR,
3519                                 "Not enough resources for a new flow.\n");
3520                         return -ENOMEM;
3521                 }
3522
3523                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3524                 if (ret != 0)
3525                         goto free_filter;
3526                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3527
3528                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3529                         vnic = &bp->vnic_info[0];
3530                 else
3531                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3532
3533                 match = bnxt_match_fdir(bp, filter, &mvnic);
3534                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3535                         if (match->dst_id == vnic->fw_vnic_id) {
3536                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3537                                 ret = -EEXIST;
3538                                 goto free_filter;
3539                         } else {
3540                                 match->dst_id = vnic->fw_vnic_id;
3541                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3542                                                                   match->dst_id,
3543                                                                   match);
3544                                 STAILQ_REMOVE(&mvnic->filter, match,
3545                                               bnxt_filter_info, next);
3546                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3547                                 PMD_DRV_LOG(ERR,
3548                                         "Filter with matching pattern exist\n");
3549                                 PMD_DRV_LOG(ERR,
3550                                         "Updated it to new destination q\n");
3551                                 goto free_filter;
3552                         }
3553                 }
3554                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3555                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3556                         ret = -ENOENT;
3557                         goto free_filter;
3558                 }
3559
3560                 if (filter_op == RTE_ETH_FILTER_ADD) {
3561                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3562                                                           filter->dst_id,
3563                                                           filter);
3564                         if (ret)
3565                                 goto free_filter;
3566                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3567                 } else {
3568                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3569                         STAILQ_REMOVE(&vnic->filter, match,
3570                                       bnxt_filter_info, next);
3571                         bnxt_free_filter(bp, match);
3572                         bnxt_free_filter(bp, filter);
3573                 }
3574                 break;
3575         case RTE_ETH_FILTER_FLUSH:
3576                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3577                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3578
3579                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3580                                 if (filter->filter_type ==
3581                                     HWRM_CFA_NTUPLE_FILTER) {
3582                                         ret =
3583                                         bnxt_hwrm_clear_ntuple_filter(bp,
3584                                                                       filter);
3585                                         STAILQ_REMOVE(&vnic->filter, filter,
3586                                                       bnxt_filter_info, next);
3587                                 }
3588                         }
3589                 }
3590                 return ret;
3591         case RTE_ETH_FILTER_UPDATE:
3592         case RTE_ETH_FILTER_STATS:
3593         case RTE_ETH_FILTER_INFO:
3594                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3595                 break;
3596         default:
3597                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3598                 ret = -EINVAL;
3599                 break;
3600         }
3601         return ret;
3602
3603 free_filter:
3604         bnxt_free_filter(bp, filter);
3605         return ret;
3606 }
3607
3608 static int
3609 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3610                     enum rte_filter_type filter_type,
3611                     enum rte_filter_op filter_op, void *arg)
3612 {
3613         struct bnxt *bp = dev->data->dev_private;
3614         int ret = 0;
3615
3616         ret = is_bnxt_in_error(dev->data->dev_private);
3617         if (ret)
3618                 return ret;
3619
3620         switch (filter_type) {
3621         case RTE_ETH_FILTER_TUNNEL:
3622                 PMD_DRV_LOG(ERR,
3623                         "filter type: %d: To be implemented\n", filter_type);
3624                 break;
3625         case RTE_ETH_FILTER_FDIR:
3626                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3627                 break;
3628         case RTE_ETH_FILTER_NTUPLE:
3629                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3630                 break;
3631         case RTE_ETH_FILTER_ETHERTYPE:
3632                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3633                 break;
3634         case RTE_ETH_FILTER_GENERIC:
3635                 if (filter_op != RTE_ETH_FILTER_GET)
3636                         return -EINVAL;
3637                 if (BNXT_TRUFLOW_EN(bp))
3638                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3639                 else
3640                         *(const void **)arg = &bnxt_flow_ops;
3641                 break;
3642         default:
3643                 PMD_DRV_LOG(ERR,
3644                         "Filter type (%d) not supported", filter_type);
3645                 ret = -EINVAL;
3646                 break;
3647         }
3648         return ret;
3649 }
3650
3651 static const uint32_t *
3652 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3653 {
3654         static const uint32_t ptypes[] = {
3655                 RTE_PTYPE_L2_ETHER_VLAN,
3656                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3657                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3658                 RTE_PTYPE_L4_ICMP,
3659                 RTE_PTYPE_L4_TCP,
3660                 RTE_PTYPE_L4_UDP,
3661                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3662                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3663                 RTE_PTYPE_INNER_L4_ICMP,
3664                 RTE_PTYPE_INNER_L4_TCP,
3665                 RTE_PTYPE_INNER_L4_UDP,
3666                 RTE_PTYPE_UNKNOWN
3667         };
3668
3669         if (!dev->rx_pkt_burst)
3670                 return NULL;
3671
3672         return ptypes;
3673 }
3674
3675 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3676                          int reg_win)
3677 {
3678         uint32_t reg_base = *reg_arr & 0xfffff000;
3679         uint32_t win_off;
3680         int i;
3681
3682         for (i = 0; i < count; i++) {
3683                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3684                         return -ERANGE;
3685         }
3686         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3687         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3688         return 0;
3689 }
3690
3691 static int bnxt_map_ptp_regs(struct bnxt *bp)
3692 {
3693         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3694         uint32_t *reg_arr;
3695         int rc, i;
3696
3697         reg_arr = ptp->rx_regs;
3698         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3699         if (rc)
3700                 return rc;
3701
3702         reg_arr = ptp->tx_regs;
3703         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3704         if (rc)
3705                 return rc;
3706
3707         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3708                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3709
3710         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3711                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3712
3713         return 0;
3714 }
3715
3716 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3717 {
3718         rte_write32(0, (uint8_t *)bp->bar0 +
3719                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3720         rte_write32(0, (uint8_t *)bp->bar0 +
3721                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3722 }
3723
3724 static uint64_t bnxt_cc_read(struct bnxt *bp)
3725 {
3726         uint64_t ns;
3727
3728         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3729                               BNXT_GRCPF_REG_SYNC_TIME));
3730         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3731                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3732         return ns;
3733 }
3734
3735 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3736 {
3737         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3738         uint32_t fifo;
3739
3740         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3741                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3742         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3743                 return -EAGAIN;
3744
3745         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3746                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3747         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3748                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3749         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3750                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3751
3752         return 0;
3753 }
3754
3755 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3756 {
3757         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3758         struct bnxt_pf_info *pf = bp->pf;
3759         uint16_t port_id;
3760         uint32_t fifo;
3761
3762         if (!ptp)
3763                 return -ENODEV;
3764
3765         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3766                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3767         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3768                 return -EAGAIN;
3769
3770         port_id = pf->port_id;
3771         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3772                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3773
3774         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3775                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3776         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3777 /*              bnxt_clr_rx_ts(bp);       TBD  */
3778                 return -EBUSY;
3779         }
3780
3781         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3782                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3783         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3784                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3785
3786         return 0;
3787 }
3788
3789 static int
3790 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3791 {
3792         uint64_t ns;
3793         struct bnxt *bp = dev->data->dev_private;
3794         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3795
3796         if (!ptp)
3797                 return 0;
3798
3799         ns = rte_timespec_to_ns(ts);
3800         /* Set the timecounters to a new value. */
3801         ptp->tc.nsec = ns;
3802
3803         return 0;
3804 }
3805
3806 static int
3807 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3808 {
3809         struct bnxt *bp = dev->data->dev_private;
3810         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3811         uint64_t ns, systime_cycles = 0;
3812         int rc = 0;
3813
3814         if (!ptp)
3815                 return 0;
3816
3817         if (BNXT_CHIP_THOR(bp))
3818                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3819                                              &systime_cycles);
3820         else
3821                 systime_cycles = bnxt_cc_read(bp);
3822
3823         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3824         *ts = rte_ns_to_timespec(ns);
3825
3826         return rc;
3827 }
3828 static int
3829 bnxt_timesync_enable(struct rte_eth_dev *dev)
3830 {
3831         struct bnxt *bp = dev->data->dev_private;
3832         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3833         uint32_t shift = 0;
3834         int rc;
3835
3836         if (!ptp)
3837                 return 0;
3838
3839         ptp->rx_filter = 1;
3840         ptp->tx_tstamp_en = 1;
3841         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3842
3843         rc = bnxt_hwrm_ptp_cfg(bp);
3844         if (rc)
3845                 return rc;
3846
3847         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3848         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3849         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3850
3851         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3852         ptp->tc.cc_shift = shift;
3853         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3854
3855         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3856         ptp->rx_tstamp_tc.cc_shift = shift;
3857         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3858
3859         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3860         ptp->tx_tstamp_tc.cc_shift = shift;
3861         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3862
3863         if (!BNXT_CHIP_THOR(bp))
3864                 bnxt_map_ptp_regs(bp);
3865
3866         return 0;
3867 }
3868
3869 static int
3870 bnxt_timesync_disable(struct rte_eth_dev *dev)
3871 {
3872         struct bnxt *bp = dev->data->dev_private;
3873         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3874
3875         if (!ptp)
3876                 return 0;
3877
3878         ptp->rx_filter = 0;
3879         ptp->tx_tstamp_en = 0;
3880         ptp->rxctl = 0;
3881
3882         bnxt_hwrm_ptp_cfg(bp);
3883
3884         if (!BNXT_CHIP_THOR(bp))
3885                 bnxt_unmap_ptp_regs(bp);
3886
3887         return 0;
3888 }
3889
3890 static int
3891 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3892                                  struct timespec *timestamp,
3893                                  uint32_t flags __rte_unused)
3894 {
3895         struct bnxt *bp = dev->data->dev_private;
3896         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3897         uint64_t rx_tstamp_cycles = 0;
3898         uint64_t ns;
3899
3900         if (!ptp)
3901                 return 0;
3902
3903         if (BNXT_CHIP_THOR(bp))
3904                 rx_tstamp_cycles = ptp->rx_timestamp;
3905         else
3906                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3907
3908         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3909         *timestamp = rte_ns_to_timespec(ns);
3910         return  0;
3911 }
3912
3913 static int
3914 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3915                                  struct timespec *timestamp)
3916 {
3917         struct bnxt *bp = dev->data->dev_private;
3918         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3919         uint64_t tx_tstamp_cycles = 0;
3920         uint64_t ns;
3921         int rc = 0;
3922
3923         if (!ptp)
3924                 return 0;
3925
3926         if (BNXT_CHIP_THOR(bp))
3927                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3928                                              &tx_tstamp_cycles);
3929         else
3930                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3931
3932         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3933         *timestamp = rte_ns_to_timespec(ns);
3934
3935         return rc;
3936 }
3937
3938 static int
3939 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3940 {
3941         struct bnxt *bp = dev->data->dev_private;
3942         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3943
3944         if (!ptp)
3945                 return 0;
3946
3947         ptp->tc.nsec += delta;
3948
3949         return 0;
3950 }
3951
3952 static int
3953 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3954 {
3955         struct bnxt *bp = dev->data->dev_private;
3956         int rc;
3957         uint32_t dir_entries;
3958         uint32_t entry_length;
3959
3960         rc = is_bnxt_in_error(bp);
3961         if (rc)
3962                 return rc;
3963
3964         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3965                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3966                     bp->pdev->addr.devid, bp->pdev->addr.function);
3967
3968         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3969         if (rc != 0)
3970                 return rc;
3971
3972         return dir_entries * entry_length;
3973 }
3974
3975 static int
3976 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3977                 struct rte_dev_eeprom_info *in_eeprom)
3978 {
3979         struct bnxt *bp = dev->data->dev_private;
3980         uint32_t index;
3981         uint32_t offset;
3982         int rc;
3983
3984         rc = is_bnxt_in_error(bp);
3985         if (rc)
3986                 return rc;
3987
3988         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3989                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3990                     bp->pdev->addr.devid, bp->pdev->addr.function,
3991                     in_eeprom->offset, in_eeprom->length);
3992
3993         if (in_eeprom->offset == 0) /* special offset value to get directory */
3994                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3995                                                 in_eeprom->data);
3996
3997         index = in_eeprom->offset >> 24;
3998         offset = in_eeprom->offset & 0xffffff;
3999
4000         if (index != 0)
4001                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4002                                            in_eeprom->length, in_eeprom->data);
4003
4004         return 0;
4005 }
4006
4007 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4008 {
4009         switch (dir_type) {
4010         case BNX_DIR_TYPE_CHIMP_PATCH:
4011         case BNX_DIR_TYPE_BOOTCODE:
4012         case BNX_DIR_TYPE_BOOTCODE_2:
4013         case BNX_DIR_TYPE_APE_FW:
4014         case BNX_DIR_TYPE_APE_PATCH:
4015         case BNX_DIR_TYPE_KONG_FW:
4016         case BNX_DIR_TYPE_KONG_PATCH:
4017         case BNX_DIR_TYPE_BONO_FW:
4018         case BNX_DIR_TYPE_BONO_PATCH:
4019                 /* FALLTHROUGH */
4020                 return true;
4021         }
4022
4023         return false;
4024 }
4025
4026 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4027 {
4028         switch (dir_type) {
4029         case BNX_DIR_TYPE_AVS:
4030         case BNX_DIR_TYPE_EXP_ROM_MBA:
4031         case BNX_DIR_TYPE_PCIE:
4032         case BNX_DIR_TYPE_TSCF_UCODE:
4033         case BNX_DIR_TYPE_EXT_PHY:
4034         case BNX_DIR_TYPE_CCM:
4035         case BNX_DIR_TYPE_ISCSI_BOOT:
4036         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4037         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4038                 /* FALLTHROUGH */
4039                 return true;
4040         }
4041
4042         return false;
4043 }
4044
4045 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4046 {
4047         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4048                 bnxt_dir_type_is_other_exec_format(dir_type);
4049 }
4050
4051 static int
4052 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4053                 struct rte_dev_eeprom_info *in_eeprom)
4054 {
4055         struct bnxt *bp = dev->data->dev_private;
4056         uint8_t index, dir_op;
4057         uint16_t type, ext, ordinal, attr;
4058         int rc;
4059
4060         rc = is_bnxt_in_error(bp);
4061         if (rc)
4062                 return rc;
4063
4064         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4065                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4066                     bp->pdev->addr.devid, bp->pdev->addr.function,
4067                     in_eeprom->offset, in_eeprom->length);
4068
4069         if (!BNXT_PF(bp)) {
4070                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4071                 return -EINVAL;
4072         }
4073
4074         type = in_eeprom->magic >> 16;
4075
4076         if (type == 0xffff) { /* special value for directory operations */
4077                 index = in_eeprom->magic & 0xff;
4078                 dir_op = in_eeprom->magic >> 8;
4079                 if (index == 0)
4080                         return -EINVAL;
4081                 switch (dir_op) {
4082                 case 0x0e: /* erase */
4083                         if (in_eeprom->offset != ~in_eeprom->magic)
4084                                 return -EINVAL;
4085                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4086                 default:
4087                         return -EINVAL;
4088                 }
4089         }
4090
4091         /* Create or re-write an NVM item: */
4092         if (bnxt_dir_type_is_executable(type) == true)
4093                 return -EOPNOTSUPP;
4094         ext = in_eeprom->magic & 0xffff;
4095         ordinal = in_eeprom->offset >> 16;
4096         attr = in_eeprom->offset & 0xffff;
4097
4098         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4099                                      in_eeprom->data, in_eeprom->length);
4100 }
4101
4102 /*
4103  * Initialization
4104  */
4105
4106 static const struct eth_dev_ops bnxt_dev_ops = {
4107         .dev_infos_get = bnxt_dev_info_get_op,
4108         .dev_close = bnxt_dev_close_op,
4109         .dev_configure = bnxt_dev_configure_op,
4110         .dev_start = bnxt_dev_start_op,
4111         .dev_stop = bnxt_dev_stop_op,
4112         .dev_set_link_up = bnxt_dev_set_link_up_op,
4113         .dev_set_link_down = bnxt_dev_set_link_down_op,
4114         .stats_get = bnxt_stats_get_op,
4115         .stats_reset = bnxt_stats_reset_op,
4116         .rx_queue_setup = bnxt_rx_queue_setup_op,
4117         .rx_queue_release = bnxt_rx_queue_release_op,
4118         .tx_queue_setup = bnxt_tx_queue_setup_op,
4119         .tx_queue_release = bnxt_tx_queue_release_op,
4120         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4121         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4122         .reta_update = bnxt_reta_update_op,
4123         .reta_query = bnxt_reta_query_op,
4124         .rss_hash_update = bnxt_rss_hash_update_op,
4125         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4126         .link_update = bnxt_link_update_op,
4127         .promiscuous_enable = bnxt_promiscuous_enable_op,
4128         .promiscuous_disable = bnxt_promiscuous_disable_op,
4129         .allmulticast_enable = bnxt_allmulticast_enable_op,
4130         .allmulticast_disable = bnxt_allmulticast_disable_op,
4131         .mac_addr_add = bnxt_mac_addr_add_op,
4132         .mac_addr_remove = bnxt_mac_addr_remove_op,
4133         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4134         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4135         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4136         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4137         .vlan_filter_set = bnxt_vlan_filter_set_op,
4138         .vlan_offload_set = bnxt_vlan_offload_set_op,
4139         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4140         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4141         .mtu_set = bnxt_mtu_set_op,
4142         .mac_addr_set = bnxt_set_default_mac_addr_op,
4143         .xstats_get = bnxt_dev_xstats_get_op,
4144         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4145         .xstats_reset = bnxt_dev_xstats_reset_op,
4146         .fw_version_get = bnxt_fw_version_get,
4147         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4148         .rxq_info_get = bnxt_rxq_info_get_op,
4149         .txq_info_get = bnxt_txq_info_get_op,
4150         .dev_led_on = bnxt_dev_led_on_op,
4151         .dev_led_off = bnxt_dev_led_off_op,
4152         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4153         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4154         .rx_queue_count = bnxt_rx_queue_count_op,
4155         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4156         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4157         .rx_queue_start = bnxt_rx_queue_start,
4158         .rx_queue_stop = bnxt_rx_queue_stop,
4159         .tx_queue_start = bnxt_tx_queue_start,
4160         .tx_queue_stop = bnxt_tx_queue_stop,
4161         .filter_ctrl = bnxt_filter_ctrl_op,
4162         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4163         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4164         .get_eeprom           = bnxt_get_eeprom_op,
4165         .set_eeprom           = bnxt_set_eeprom_op,
4166         .timesync_enable      = bnxt_timesync_enable,
4167         .timesync_disable     = bnxt_timesync_disable,
4168         .timesync_read_time   = bnxt_timesync_read_time,
4169         .timesync_write_time   = bnxt_timesync_write_time,
4170         .timesync_adjust_time = bnxt_timesync_adjust_time,
4171         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4172         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4173 };
4174
4175 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4176 {
4177         uint32_t offset;
4178
4179         /* Only pre-map the reset GRC registers using window 3 */
4180         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4181                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4182
4183         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4184
4185         return offset;
4186 }
4187
4188 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4189 {
4190         struct bnxt_error_recovery_info *info = bp->recovery_info;
4191         uint32_t reg_base = 0xffffffff;
4192         int i;
4193
4194         /* Only pre-map the monitoring GRC registers using window 2 */
4195         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4196                 uint32_t reg = info->status_regs[i];
4197
4198                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4199                         continue;
4200
4201                 if (reg_base == 0xffffffff)
4202                         reg_base = reg & 0xfffff000;
4203                 if ((reg & 0xfffff000) != reg_base)
4204                         return -ERANGE;
4205
4206                 /* Use mask 0xffc as the Lower 2 bits indicates
4207                  * address space location
4208                  */
4209                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4210                                                 (reg & 0xffc);
4211         }
4212
4213         if (reg_base == 0xffffffff)
4214                 return 0;
4215
4216         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4217                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4218
4219         return 0;
4220 }
4221
4222 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4223 {
4224         struct bnxt_error_recovery_info *info = bp->recovery_info;
4225         uint32_t delay = info->delay_after_reset[index];
4226         uint32_t val = info->reset_reg_val[index];
4227         uint32_t reg = info->reset_reg[index];
4228         uint32_t type, offset;
4229
4230         type = BNXT_FW_STATUS_REG_TYPE(reg);
4231         offset = BNXT_FW_STATUS_REG_OFF(reg);
4232
4233         switch (type) {
4234         case BNXT_FW_STATUS_REG_TYPE_CFG:
4235                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4236                 break;
4237         case BNXT_FW_STATUS_REG_TYPE_GRC:
4238                 offset = bnxt_map_reset_regs(bp, offset);
4239                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4240                 break;
4241         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4242                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4243                 break;
4244         }
4245         /* wait on a specific interval of time until core reset is complete */
4246         if (delay)
4247                 rte_delay_ms(delay);
4248 }
4249
4250 static void bnxt_dev_cleanup(struct bnxt *bp)
4251 {
4252         bnxt_set_hwrm_link_config(bp, false);
4253         bp->link_info->link_up = 0;
4254         if (bp->eth_dev->data->dev_started)
4255                 bnxt_dev_stop_op(bp->eth_dev);
4256
4257         bnxt_uninit_resources(bp, true);
4258 }
4259
4260 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4261 {
4262         struct rte_eth_dev *dev = bp->eth_dev;
4263         struct rte_vlan_filter_conf *vfc;
4264         int vidx, vbit, rc;
4265         uint16_t vlan_id;
4266
4267         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4268                 vfc = &dev->data->vlan_filter_conf;
4269                 vidx = vlan_id / 64;
4270                 vbit = vlan_id % 64;
4271
4272                 /* Each bit corresponds to a VLAN id */
4273                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4274                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4275                         if (rc)
4276                                 return rc;
4277                 }
4278         }
4279
4280         return 0;
4281 }
4282
4283 static int bnxt_restore_mac_filters(struct bnxt *bp)
4284 {
4285         struct rte_eth_dev *dev = bp->eth_dev;
4286         struct rte_eth_dev_info dev_info;
4287         struct rte_ether_addr *addr;
4288         uint64_t pool_mask;
4289         uint32_t pool = 0;
4290         uint16_t i;
4291         int rc;
4292
4293         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4294                 return 0;
4295
4296         rc = bnxt_dev_info_get_op(dev, &dev_info);
4297         if (rc)
4298                 return rc;
4299
4300         /* replay MAC address configuration */
4301         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4302                 addr = &dev->data->mac_addrs[i];
4303
4304                 /* skip zero address */
4305                 if (rte_is_zero_ether_addr(addr))
4306                         continue;
4307
4308                 pool = 0;
4309                 pool_mask = dev->data->mac_pool_sel[i];
4310
4311                 do {
4312                         if (pool_mask & 1ULL) {
4313                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4314                                 if (rc)
4315                                         return rc;
4316                         }
4317                         pool_mask >>= 1;
4318                         pool++;
4319                 } while (pool_mask);
4320         }
4321
4322         return 0;
4323 }
4324
4325 static int bnxt_restore_filters(struct bnxt *bp)
4326 {
4327         struct rte_eth_dev *dev = bp->eth_dev;
4328         int ret = 0;
4329
4330         if (dev->data->all_multicast) {
4331                 ret = bnxt_allmulticast_enable_op(dev);
4332                 if (ret)
4333                         return ret;
4334         }
4335         if (dev->data->promiscuous) {
4336                 ret = bnxt_promiscuous_enable_op(dev);
4337                 if (ret)
4338                         return ret;
4339         }
4340
4341         ret = bnxt_restore_mac_filters(bp);
4342         if (ret)
4343                 return ret;
4344
4345         ret = bnxt_restore_vlan_filters(bp);
4346         /* TODO restore other filters as well */
4347         return ret;
4348 }
4349
4350 static void bnxt_dev_recover(void *arg)
4351 {
4352         struct bnxt *bp = arg;
4353         int timeout = bp->fw_reset_max_msecs;
4354         int rc = 0;
4355
4356         /* Clear Error flag so that device re-init should happen */
4357         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4358
4359         do {
4360                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4361                 if (rc == 0)
4362                         break;
4363                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4364                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4365         } while (rc && timeout);
4366
4367         if (rc) {
4368                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4369                 goto err;
4370         }
4371
4372         rc = bnxt_init_resources(bp, true);
4373         if (rc) {
4374                 PMD_DRV_LOG(ERR,
4375                             "Failed to initialize resources after reset\n");
4376                 goto err;
4377         }
4378         /* clear reset flag as the device is initialized now */
4379         bp->flags &= ~BNXT_FLAG_FW_RESET;
4380
4381         rc = bnxt_dev_start_op(bp->eth_dev);
4382         if (rc) {
4383                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4384                 goto err_start;
4385         }
4386
4387         rc = bnxt_restore_filters(bp);
4388         if (rc)
4389                 goto err_start;
4390
4391         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4392         return;
4393 err_start:
4394         bnxt_dev_stop_op(bp->eth_dev);
4395 err:
4396         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4397         bnxt_uninit_resources(bp, false);
4398         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4399 }
4400
4401 void bnxt_dev_reset_and_resume(void *arg)
4402 {
4403         struct bnxt *bp = arg;
4404         int rc;
4405
4406         bnxt_dev_cleanup(bp);
4407
4408         bnxt_wait_for_device_shutdown(bp);
4409
4410         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4411                                bnxt_dev_recover, (void *)bp);
4412         if (rc)
4413                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4414 }
4415
4416 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4417 {
4418         struct bnxt_error_recovery_info *info = bp->recovery_info;
4419         uint32_t reg = info->status_regs[index];
4420         uint32_t type, offset, val = 0;
4421
4422         type = BNXT_FW_STATUS_REG_TYPE(reg);
4423         offset = BNXT_FW_STATUS_REG_OFF(reg);
4424
4425         switch (type) {
4426         case BNXT_FW_STATUS_REG_TYPE_CFG:
4427                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4428                 break;
4429         case BNXT_FW_STATUS_REG_TYPE_GRC:
4430                 offset = info->mapped_status_regs[index];
4431                 /* FALLTHROUGH */
4432         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4433                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4434                                        offset));
4435                 break;
4436         }
4437
4438         return val;
4439 }
4440
4441 static int bnxt_fw_reset_all(struct bnxt *bp)
4442 {
4443         struct bnxt_error_recovery_info *info = bp->recovery_info;
4444         uint32_t i;
4445         int rc = 0;
4446
4447         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4448                 /* Reset through master function driver */
4449                 for (i = 0; i < info->reg_array_cnt; i++)
4450                         bnxt_write_fw_reset_reg(bp, i);
4451                 /* Wait for time specified by FW after triggering reset */
4452                 rte_delay_ms(info->master_func_wait_period_after_reset);
4453         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4454                 /* Reset with the help of Kong processor */
4455                 rc = bnxt_hwrm_fw_reset(bp);
4456                 if (rc)
4457                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4458         }
4459
4460         return rc;
4461 }
4462
4463 static void bnxt_fw_reset_cb(void *arg)
4464 {
4465         struct bnxt *bp = arg;
4466         struct bnxt_error_recovery_info *info = bp->recovery_info;
4467         int rc = 0;
4468
4469         /* Only Master function can do FW reset */
4470         if (bnxt_is_master_func(bp) &&
4471             bnxt_is_recovery_enabled(bp)) {
4472                 rc = bnxt_fw_reset_all(bp);
4473                 if (rc) {
4474                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4475                         return;
4476                 }
4477         }
4478
4479         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4480          * EXCEPTION_FATAL_ASYNC event to all the functions
4481          * (including MASTER FUNC). After receiving this Async, all the active
4482          * drivers should treat this case as FW initiated recovery
4483          */
4484         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4485                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4486                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4487
4488                 /* To recover from error */
4489                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4490                                   (void *)bp);
4491         }
4492 }
4493
4494 /* Driver should poll FW heartbeat, reset_counter with the frequency
4495  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4496  * When the driver detects heartbeat stop or change in reset_counter,
4497  * it has to trigger a reset to recover from the error condition.
4498  * A “master PF” is the function who will have the privilege to
4499  * initiate the chimp reset. The master PF will be elected by the
4500  * firmware and will be notified through async message.
4501  */
4502 static void bnxt_check_fw_health(void *arg)
4503 {
4504         struct bnxt *bp = arg;
4505         struct bnxt_error_recovery_info *info = bp->recovery_info;
4506         uint32_t val = 0, wait_msec;
4507
4508         if (!info || !bnxt_is_recovery_enabled(bp) ||
4509             is_bnxt_in_error(bp))
4510                 return;
4511
4512         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4513         if (val == info->last_heart_beat)
4514                 goto reset;
4515
4516         info->last_heart_beat = val;
4517
4518         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4519         if (val != info->last_reset_counter)
4520                 goto reset;
4521
4522         info->last_reset_counter = val;
4523
4524         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4525                           bnxt_check_fw_health, (void *)bp);
4526
4527         return;
4528 reset:
4529         /* Stop DMA to/from device */
4530         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4531         bp->flags |= BNXT_FLAG_FW_RESET;
4532
4533         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4534
4535         if (bnxt_is_master_func(bp))
4536                 wait_msec = info->master_func_wait_period;
4537         else
4538                 wait_msec = info->normal_func_wait_period;
4539
4540         rte_eal_alarm_set(US_PER_MS * wait_msec,
4541                           bnxt_fw_reset_cb, (void *)bp);
4542 }
4543
4544 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4545 {
4546         uint32_t polling_freq;
4547
4548         if (!bnxt_is_recovery_enabled(bp))
4549                 return;
4550
4551         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4552                 return;
4553
4554         polling_freq = bp->recovery_info->driver_polling_freq;
4555
4556         rte_eal_alarm_set(US_PER_MS * polling_freq,
4557                           bnxt_check_fw_health, (void *)bp);
4558         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4559 }
4560
4561 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4562 {
4563         if (!bnxt_is_recovery_enabled(bp))
4564                 return;
4565
4566         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4567         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4568 }
4569
4570 static bool bnxt_vf_pciid(uint16_t device_id)
4571 {
4572         switch (device_id) {
4573         case BROADCOM_DEV_ID_57304_VF:
4574         case BROADCOM_DEV_ID_57406_VF:
4575         case BROADCOM_DEV_ID_5731X_VF:
4576         case BROADCOM_DEV_ID_5741X_VF:
4577         case BROADCOM_DEV_ID_57414_VF:
4578         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4579         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4580         case BROADCOM_DEV_ID_58802_VF:
4581         case BROADCOM_DEV_ID_57500_VF1:
4582         case BROADCOM_DEV_ID_57500_VF2:
4583                 /* FALLTHROUGH */
4584                 return true;
4585         default:
4586                 return false;
4587         }
4588 }
4589
4590 static bool bnxt_thor_device(uint16_t device_id)
4591 {
4592         switch (device_id) {
4593         case BROADCOM_DEV_ID_57508:
4594         case BROADCOM_DEV_ID_57504:
4595         case BROADCOM_DEV_ID_57502:
4596         case BROADCOM_DEV_ID_57508_MF1:
4597         case BROADCOM_DEV_ID_57504_MF1:
4598         case BROADCOM_DEV_ID_57502_MF1:
4599         case BROADCOM_DEV_ID_57508_MF2:
4600         case BROADCOM_DEV_ID_57504_MF2:
4601         case BROADCOM_DEV_ID_57502_MF2:
4602         case BROADCOM_DEV_ID_57500_VF1:
4603         case BROADCOM_DEV_ID_57500_VF2:
4604                 /* FALLTHROUGH */
4605                 return true;
4606         default:
4607                 return false;
4608         }
4609 }
4610
4611 bool bnxt_stratus_device(struct bnxt *bp)
4612 {
4613         uint16_t device_id = bp->pdev->id.device_id;
4614
4615         switch (device_id) {
4616         case BROADCOM_DEV_ID_STRATUS_NIC:
4617         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4618         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4619                 /* FALLTHROUGH */
4620                 return true;
4621         default:
4622                 return false;
4623         }
4624 }
4625
4626 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4627 {
4628         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4629         struct bnxt *bp = eth_dev->data->dev_private;
4630
4631         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4632         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4633         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4634         if (!bp->bar0 || !bp->doorbell_base) {
4635                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4636                 return -ENODEV;
4637         }
4638
4639         bp->eth_dev = eth_dev;
4640         bp->pdev = pci_dev;
4641
4642         return 0;
4643 }
4644
4645 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4646                                   struct bnxt_ctx_pg_info *ctx_pg,
4647                                   uint32_t mem_size,
4648                                   const char *suffix,
4649                                   uint16_t idx)
4650 {
4651         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4652         const struct rte_memzone *mz = NULL;
4653         char mz_name[RTE_MEMZONE_NAMESIZE];
4654         rte_iova_t mz_phys_addr;
4655         uint64_t valid_bits = 0;
4656         uint32_t sz;
4657         int i;
4658
4659         if (!mem_size)
4660                 return 0;
4661
4662         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4663                          BNXT_PAGE_SIZE;
4664         rmem->page_size = BNXT_PAGE_SIZE;
4665         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4666         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4667         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4668
4669         valid_bits = PTU_PTE_VALID;
4670
4671         if (rmem->nr_pages > 1) {
4672                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4673                          "bnxt_ctx_pg_tbl%s_%x_%d",
4674                          suffix, idx, bp->eth_dev->data->port_id);
4675                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4676                 mz = rte_memzone_lookup(mz_name);
4677                 if (!mz) {
4678                         mz = rte_memzone_reserve_aligned(mz_name,
4679                                                 rmem->nr_pages * 8,
4680                                                 SOCKET_ID_ANY,
4681                                                 RTE_MEMZONE_2MB |
4682                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4683                                                 RTE_MEMZONE_IOVA_CONTIG,
4684                                                 BNXT_PAGE_SIZE);
4685                         if (mz == NULL)
4686                                 return -ENOMEM;
4687                 }
4688
4689                 memset(mz->addr, 0, mz->len);
4690                 mz_phys_addr = mz->iova;
4691
4692                 rmem->pg_tbl = mz->addr;
4693                 rmem->pg_tbl_map = mz_phys_addr;
4694                 rmem->pg_tbl_mz = mz;
4695         }
4696
4697         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4698                  suffix, idx, bp->eth_dev->data->port_id);
4699         mz = rte_memzone_lookup(mz_name);
4700         if (!mz) {
4701                 mz = rte_memzone_reserve_aligned(mz_name,
4702                                                  mem_size,
4703                                                  SOCKET_ID_ANY,
4704                                                  RTE_MEMZONE_1GB |
4705                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4706                                                  RTE_MEMZONE_IOVA_CONTIG,
4707                                                  BNXT_PAGE_SIZE);
4708                 if (mz == NULL)
4709                         return -ENOMEM;
4710         }
4711
4712         memset(mz->addr, 0, mz->len);
4713         mz_phys_addr = mz->iova;
4714
4715         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4716                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4717                 rmem->dma_arr[i] = mz_phys_addr + sz;
4718
4719                 if (rmem->nr_pages > 1) {
4720                         if (i == rmem->nr_pages - 2 &&
4721                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4722                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4723                         else if (i == rmem->nr_pages - 1 &&
4724                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4725                                 valid_bits |= PTU_PTE_LAST;
4726
4727                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4728                                                            valid_bits);
4729                 }
4730         }
4731
4732         rmem->mz = mz;
4733         if (rmem->vmem_size)
4734                 rmem->vmem = (void **)mz->addr;
4735         rmem->dma_arr[0] = mz_phys_addr;
4736         return 0;
4737 }
4738
4739 static void bnxt_free_ctx_mem(struct bnxt *bp)
4740 {
4741         int i;
4742
4743         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4744                 return;
4745
4746         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4747         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4748         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4749         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4750         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4751         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4752         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4753         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4754         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4755         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4756         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4757
4758         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4759                 if (bp->ctx->tqm_mem[i])
4760                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4761         }
4762
4763         rte_free(bp->ctx);
4764         bp->ctx = NULL;
4765 }
4766
4767 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4768
4769 #define min_t(type, x, y) ({                    \
4770         type __min1 = (x);                      \
4771         type __min2 = (y);                      \
4772         __min1 < __min2 ? __min1 : __min2; })
4773
4774 #define max_t(type, x, y) ({                    \
4775         type __max1 = (x);                      \
4776         type __max2 = (y);                      \
4777         __max1 > __max2 ? __max1 : __max2; })
4778
4779 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4780
4781 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4782 {
4783         struct bnxt_ctx_pg_info *ctx_pg;
4784         struct bnxt_ctx_mem_info *ctx;
4785         uint32_t mem_size, ena, entries;
4786         uint32_t entries_sp, min;
4787         int i, rc;
4788
4789         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4790         if (rc) {
4791                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4792                 return rc;
4793         }
4794         ctx = bp->ctx;
4795         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4796                 return 0;
4797
4798         ctx_pg = &ctx->qp_mem;
4799         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4800         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4801         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4802         if (rc)
4803                 return rc;
4804
4805         ctx_pg = &ctx->srq_mem;
4806         ctx_pg->entries = ctx->srq_max_l2_entries;
4807         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4808         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4809         if (rc)
4810                 return rc;
4811
4812         ctx_pg = &ctx->cq_mem;
4813         ctx_pg->entries = ctx->cq_max_l2_entries;
4814         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4815         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4816         if (rc)
4817                 return rc;
4818
4819         ctx_pg = &ctx->vnic_mem;
4820         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4821                 ctx->vnic_max_ring_table_entries;
4822         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4823         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4824         if (rc)
4825                 return rc;
4826
4827         ctx_pg = &ctx->stat_mem;
4828         ctx_pg->entries = ctx->stat_max_entries;
4829         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4830         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4831         if (rc)
4832                 return rc;
4833
4834         min = ctx->tqm_min_entries_per_ring;
4835
4836         entries_sp = ctx->qp_max_l2_entries +
4837                      ctx->vnic_max_vnic_entries +
4838                      2 * ctx->qp_min_qp1_entries + min;
4839         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4840
4841         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4842         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4843         entries = clamp_t(uint32_t, entries, min,
4844                           ctx->tqm_max_entries_per_ring);
4845         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4846                 ctx_pg = ctx->tqm_mem[i];
4847                 ctx_pg->entries = i ? entries : entries_sp;
4848                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4849                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4850                 if (rc)
4851                         return rc;
4852                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4853         }
4854
4855         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4856         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4857         if (rc)
4858                 PMD_DRV_LOG(ERR,
4859                             "Failed to configure context mem: rc = %d\n", rc);
4860         else
4861                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4862
4863         return rc;
4864 }
4865
4866 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4867 {
4868         struct rte_pci_device *pci_dev = bp->pdev;
4869         char mz_name[RTE_MEMZONE_NAMESIZE];
4870         const struct rte_memzone *mz = NULL;
4871         uint32_t total_alloc_len;
4872         rte_iova_t mz_phys_addr;
4873
4874         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4875                 return 0;
4876
4877         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4878                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4879                  pci_dev->addr.bus, pci_dev->addr.devid,
4880                  pci_dev->addr.function, "rx_port_stats");
4881         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4882         mz = rte_memzone_lookup(mz_name);
4883         total_alloc_len =
4884                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4885                                        sizeof(struct rx_port_stats_ext) + 512);
4886         if (!mz) {
4887                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4888                                          SOCKET_ID_ANY,
4889                                          RTE_MEMZONE_2MB |
4890                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4891                                          RTE_MEMZONE_IOVA_CONTIG);
4892                 if (mz == NULL)
4893                         return -ENOMEM;
4894         }
4895         memset(mz->addr, 0, mz->len);
4896         mz_phys_addr = mz->iova;
4897
4898         bp->rx_mem_zone = (const void *)mz;
4899         bp->hw_rx_port_stats = mz->addr;
4900         bp->hw_rx_port_stats_map = mz_phys_addr;
4901
4902         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4903                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4904                  pci_dev->addr.bus, pci_dev->addr.devid,
4905                  pci_dev->addr.function, "tx_port_stats");
4906         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4907         mz = rte_memzone_lookup(mz_name);
4908         total_alloc_len =
4909                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4910                                        sizeof(struct tx_port_stats_ext) + 512);
4911         if (!mz) {
4912                 mz = rte_memzone_reserve(mz_name,
4913                                          total_alloc_len,
4914                                          SOCKET_ID_ANY,
4915                                          RTE_MEMZONE_2MB |
4916                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4917                                          RTE_MEMZONE_IOVA_CONTIG);
4918                 if (mz == NULL)
4919                         return -ENOMEM;
4920         }
4921         memset(mz->addr, 0, mz->len);
4922         mz_phys_addr = mz->iova;
4923
4924         bp->tx_mem_zone = (const void *)mz;
4925         bp->hw_tx_port_stats = mz->addr;
4926         bp->hw_tx_port_stats_map = mz_phys_addr;
4927         bp->flags |= BNXT_FLAG_PORT_STATS;
4928
4929         /* Display extended statistics if FW supports it */
4930         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4931             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4932             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4933                 return 0;
4934
4935         bp->hw_rx_port_stats_ext = (void *)
4936                 ((uint8_t *)bp->hw_rx_port_stats +
4937                  sizeof(struct rx_port_stats));
4938         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4939                 sizeof(struct rx_port_stats);
4940         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4941
4942         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4943             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4944                 bp->hw_tx_port_stats_ext = (void *)
4945                         ((uint8_t *)bp->hw_tx_port_stats +
4946                          sizeof(struct tx_port_stats));
4947                 bp->hw_tx_port_stats_ext_map =
4948                         bp->hw_tx_port_stats_map +
4949                         sizeof(struct tx_port_stats);
4950                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4951         }
4952
4953         return 0;
4954 }
4955
4956 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4957 {
4958         struct bnxt *bp = eth_dev->data->dev_private;
4959         int rc = 0;
4960
4961         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4962                                                RTE_ETHER_ADDR_LEN *
4963                                                bp->max_l2_ctx,
4964                                                0);
4965         if (eth_dev->data->mac_addrs == NULL) {
4966                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4967                 return -ENOMEM;
4968         }
4969
4970         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4971                 if (BNXT_PF(bp))
4972                         return -EINVAL;
4973
4974                 /* Generate a random MAC address, if none was assigned by PF */
4975                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4976                 bnxt_eth_hw_addr_random(bp->mac_addr);
4977                 PMD_DRV_LOG(INFO,
4978                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4979                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4980                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4981
4982                 rc = bnxt_hwrm_set_mac(bp);
4983                 if (rc)
4984                         return rc;
4985         }
4986
4987         /* Copy the permanent MAC from the FUNC_QCAPS response */
4988         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4989
4990         return rc;
4991 }
4992
4993 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4994 {
4995         int rc = 0;
4996
4997         /* MAC is already configured in FW */
4998         if (BNXT_HAS_DFLT_MAC_SET(bp))
4999                 return 0;
5000
5001         /* Restore the old MAC configured */
5002         rc = bnxt_hwrm_set_mac(bp);
5003         if (rc)
5004                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5005
5006         return rc;
5007 }
5008
5009 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5010 {
5011         if (!BNXT_PF(bp))
5012                 return;
5013
5014 #define ALLOW_FUNC(x)   \
5015         { \
5016                 uint32_t arg = (x); \
5017                 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5018                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5019         }
5020
5021         /* Forward all requests if firmware is new enough */
5022         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5023              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5024             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5025                 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5026         } else {
5027                 PMD_DRV_LOG(WARNING,
5028                             "Firmware too old for VF mailbox functionality\n");
5029                 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5030         }
5031
5032         /*
5033          * The following are used for driver cleanup. If we disallow these,
5034          * VF drivers can't clean up cleanly.
5035          */
5036         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5037         ALLOW_FUNC(HWRM_VNIC_FREE);
5038         ALLOW_FUNC(HWRM_RING_FREE);
5039         ALLOW_FUNC(HWRM_RING_GRP_FREE);
5040         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5041         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5042         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5043         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5044         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5045 }
5046
5047 uint16_t
5048 bnxt_get_svif(uint16_t port_id, bool func_svif)
5049 {
5050         struct rte_eth_dev *eth_dev;
5051         struct bnxt *bp;
5052
5053         eth_dev = &rte_eth_devices[port_id];
5054         bp = eth_dev->data->dev_private;
5055
5056         return func_svif ? bp->func_svif : bp->port_svif;
5057 }
5058
5059 uint16_t
5060 bnxt_get_vnic_id(uint16_t port)
5061 {
5062         struct rte_eth_dev *eth_dev;
5063         struct bnxt_vnic_info *vnic;
5064         struct bnxt *bp;
5065
5066         eth_dev = &rte_eth_devices[port];
5067         bp = eth_dev->data->dev_private;
5068
5069         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5070
5071         return vnic->fw_vnic_id;
5072 }
5073
5074 uint16_t
5075 bnxt_get_fw_func_id(uint16_t port)
5076 {
5077         struct rte_eth_dev *eth_dev;
5078         struct bnxt *bp;
5079
5080         eth_dev = &rte_eth_devices[port];
5081         bp = eth_dev->data->dev_private;
5082
5083         return bp->fw_fid;
5084 }
5085
5086 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5087 {
5088         struct bnxt_error_recovery_info *info = bp->recovery_info;
5089
5090         if (info) {
5091                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5092                         memset(info, 0, sizeof(*info));
5093                 return;
5094         }
5095
5096         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5097                 return;
5098
5099         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5100                            sizeof(*info), 0);
5101         if (!info)
5102                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5103
5104         bp->recovery_info = info;
5105 }
5106
5107 static void bnxt_check_fw_status(struct bnxt *bp)
5108 {
5109         uint32_t fw_status;
5110
5111         if (!(bp->recovery_info &&
5112               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5113                 return;
5114
5115         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5116         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5117                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5118                             fw_status);
5119 }
5120
5121 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5122 {
5123         struct bnxt_error_recovery_info *info = bp->recovery_info;
5124         uint32_t status_loc;
5125         uint32_t sig_ver;
5126
5127         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5128                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5129         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5130                                    BNXT_GRCP_WINDOW_2_BASE +
5131                                    offsetof(struct hcomm_status,
5132                                             sig_ver)));
5133         /* If the signature is absent, then FW does not support this feature */
5134         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5135             HCOMM_STATUS_SIGNATURE_VAL)
5136                 return 0;
5137
5138         if (!info) {
5139                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5140                                    sizeof(*info), 0);
5141                 if (!info)
5142                         return -ENOMEM;
5143                 bp->recovery_info = info;
5144         } else {
5145                 memset(info, 0, sizeof(*info));
5146         }
5147
5148         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5149                                       BNXT_GRCP_WINDOW_2_BASE +
5150                                       offsetof(struct hcomm_status,
5151                                                fw_status_loc)));
5152
5153         /* Only pre-map the FW health status GRC register */
5154         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5155                 return 0;
5156
5157         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5158         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5159                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5160
5161         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5162                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5163
5164         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5165
5166         return 0;
5167 }
5168
5169 static int bnxt_init_fw(struct bnxt *bp)
5170 {
5171         uint16_t mtu;
5172         int rc = 0;
5173
5174         bp->fw_cap = 0;
5175
5176         rc = bnxt_map_hcomm_fw_status_reg(bp);
5177         if (rc)
5178                 return rc;
5179
5180         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5181         if (rc) {
5182                 bnxt_check_fw_status(bp);
5183                 return rc;
5184         }
5185
5186         rc = bnxt_hwrm_func_reset(bp);
5187         if (rc)
5188                 return -EIO;
5189
5190         rc = bnxt_hwrm_vnic_qcaps(bp);
5191         if (rc)
5192                 return rc;
5193
5194         rc = bnxt_hwrm_queue_qportcfg(bp);
5195         if (rc)
5196                 return rc;
5197
5198         /* Get the MAX capabilities for this function.
5199          * This function also allocates context memory for TQM rings and
5200          * informs the firmware about this allocated backing store memory.
5201          */
5202         rc = bnxt_hwrm_func_qcaps(bp);
5203         if (rc)
5204                 return rc;
5205
5206         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5207         if (rc)
5208                 return rc;
5209
5210         bnxt_hwrm_port_mac_qcfg(bp);
5211
5212         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5213         if (rc)
5214                 return rc;
5215
5216         bnxt_alloc_error_recovery_info(bp);
5217         /* Get the adapter error recovery support info */
5218         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5219         if (rc)
5220                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5221
5222         bnxt_hwrm_port_led_qcaps(bp);
5223
5224         return 0;
5225 }
5226
5227 static int
5228 bnxt_init_locks(struct bnxt *bp)
5229 {
5230         int err;
5231
5232         err = pthread_mutex_init(&bp->flow_lock, NULL);
5233         if (err) {
5234                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5235                 return err;
5236         }
5237
5238         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5239         if (err)
5240                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5241         return err;
5242 }
5243
5244 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5245 {
5246         int rc = 0;
5247
5248         rc = bnxt_init_fw(bp);
5249         if (rc)
5250                 return rc;
5251
5252         if (!reconfig_dev) {
5253                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5254                 if (rc)
5255                         return rc;
5256         } else {
5257                 rc = bnxt_restore_dflt_mac(bp);
5258                 if (rc)
5259                         return rc;
5260         }
5261
5262         bnxt_config_vf_req_fwd(bp);
5263
5264         rc = bnxt_hwrm_func_driver_register(bp);
5265         if (rc) {
5266                 PMD_DRV_LOG(ERR, "Failed to register driver");
5267                 return -EBUSY;
5268         }
5269
5270         if (BNXT_PF(bp)) {
5271                 if (bp->pdev->max_vfs) {
5272                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5273                         if (rc) {
5274                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5275                                 return rc;
5276                         }
5277                 } else {
5278                         rc = bnxt_hwrm_allocate_pf_only(bp);
5279                         if (rc) {
5280                                 PMD_DRV_LOG(ERR,
5281                                             "Failed to allocate PF resources");
5282                                 return rc;
5283                         }
5284                 }
5285         }
5286
5287         rc = bnxt_alloc_mem(bp, reconfig_dev);
5288         if (rc)
5289                 return rc;
5290
5291         rc = bnxt_setup_int(bp);
5292         if (rc)
5293                 return rc;
5294
5295         rc = bnxt_request_int(bp);
5296         if (rc)
5297                 return rc;
5298
5299         rc = bnxt_init_ctx_mem(bp);
5300         if (rc) {
5301                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5302                 return rc;
5303         }
5304
5305         rc = bnxt_init_locks(bp);
5306         if (rc)
5307                 return rc;
5308
5309         return 0;
5310 }
5311
5312 static int
5313 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5314                           const char *value, void *opaque_arg)
5315 {
5316         struct bnxt *bp = opaque_arg;
5317         unsigned long truflow;
5318         char *end = NULL;
5319
5320         if (!value || !opaque_arg) {
5321                 PMD_DRV_LOG(ERR,
5322                             "Invalid parameter passed to truflow devargs.\n");
5323                 return -EINVAL;
5324         }
5325
5326         truflow = strtoul(value, &end, 10);
5327         if (end == NULL || *end != '\0' ||
5328             (truflow == ULONG_MAX && errno == ERANGE)) {
5329                 PMD_DRV_LOG(ERR,
5330                             "Invalid parameter passed to truflow devargs.\n");
5331                 return -EINVAL;
5332         }
5333
5334         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5335                 PMD_DRV_LOG(ERR,
5336                             "Invalid value passed to truflow devargs.\n");
5337                 return -EINVAL;
5338         }
5339
5340         bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5341         if (BNXT_TRUFLOW_EN(bp))
5342                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5343
5344         return 0;
5345 }
5346
5347 static int
5348 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5349                              const char *value, void *opaque_arg)
5350 {
5351         struct bnxt *bp = opaque_arg;
5352         unsigned long flow_xstat;
5353         char *end = NULL;
5354
5355         if (!value || !opaque_arg) {
5356                 PMD_DRV_LOG(ERR,
5357                             "Invalid parameter passed to flow_xstat devarg.\n");
5358                 return -EINVAL;
5359         }
5360
5361         flow_xstat = strtoul(value, &end, 10);
5362         if (end == NULL || *end != '\0' ||
5363             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5364                 PMD_DRV_LOG(ERR,
5365                             "Invalid parameter passed to flow_xstat devarg.\n");
5366                 return -EINVAL;
5367         }
5368
5369         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5370                 PMD_DRV_LOG(ERR,
5371                             "Invalid value passed to flow_xstat devarg.\n");
5372                 return -EINVAL;
5373         }
5374
5375         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5376         if (BNXT_FLOW_XSTATS_EN(bp))
5377                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5378
5379         return 0;
5380 }
5381
5382 static int
5383 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5384                                         const char *value, void *opaque_arg)
5385 {
5386         struct bnxt *bp = opaque_arg;
5387         unsigned long max_num_kflows;
5388         char *end = NULL;
5389
5390         if (!value || !opaque_arg) {
5391                 PMD_DRV_LOG(ERR,
5392                         "Invalid parameter passed to max_num_kflows devarg.\n");
5393                 return -EINVAL;
5394         }
5395
5396         max_num_kflows = strtoul(value, &end, 10);
5397         if (end == NULL || *end != '\0' ||
5398                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5399                 PMD_DRV_LOG(ERR,
5400                         "Invalid parameter passed to max_num_kflows devarg.\n");
5401                 return -EINVAL;
5402         }
5403
5404         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5405                 PMD_DRV_LOG(ERR,
5406                         "Invalid value passed to max_num_kflows devarg.\n");
5407                 return -EINVAL;
5408         }
5409
5410         bp->max_num_kflows = max_num_kflows;
5411         if (bp->max_num_kflows)
5412                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5413                                 max_num_kflows);
5414
5415         return 0;
5416 }
5417
5418 static void
5419 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5420 {
5421         struct rte_kvargs *kvlist;
5422
5423         if (devargs == NULL)
5424                 return;
5425
5426         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5427         if (kvlist == NULL)
5428                 return;
5429
5430         /*
5431          * Handler for "truflow" devarg.
5432          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5433          */
5434         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5435                            bnxt_parse_devarg_truflow, bp);
5436
5437         /*
5438          * Handler for "flow_xstat" devarg.
5439          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5440          */
5441         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5442                            bnxt_parse_devarg_flow_xstat, bp);
5443
5444         /*
5445          * Handler for "max_num_kflows" devarg.
5446          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5447          */
5448         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5449                            bnxt_parse_devarg_max_num_kflows, bp);
5450
5451         rte_kvargs_free(kvlist);
5452 }
5453
5454 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5455 {
5456         int rc = 0;
5457
5458         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5459                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5460                 if (rc)
5461                         PMD_DRV_LOG(ERR,
5462                                     "Failed to alloc switch domain: %d\n", rc);
5463                 else
5464                         PMD_DRV_LOG(INFO,
5465                                     "Switch domain allocated %d\n",
5466                                     bp->switch_domain_id);
5467         }
5468
5469         return rc;
5470 }
5471
5472 static int
5473 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5474 {
5475         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5476         static int version_printed;
5477         struct bnxt *bp;
5478         int rc;
5479
5480         if (version_printed++ == 0)
5481                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5482
5483         eth_dev->dev_ops = &bnxt_dev_ops;
5484         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5485         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5486
5487         /*
5488          * For secondary processes, we don't initialise any further
5489          * as primary has already done this work.
5490          */
5491         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5492                 return 0;
5493
5494         rte_eth_copy_pci_info(eth_dev, pci_dev);
5495
5496         bp = eth_dev->data->dev_private;
5497
5498         /* Parse dev arguments passed on when starting the DPDK application. */
5499         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5500
5501         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5502
5503         if (bnxt_vf_pciid(pci_dev->id.device_id))
5504                 bp->flags |= BNXT_FLAG_VF;
5505
5506         if (bnxt_thor_device(pci_dev->id.device_id))
5507                 bp->flags |= BNXT_FLAG_THOR_CHIP;
5508
5509         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5510             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5511             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5512             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5513                 bp->flags |= BNXT_FLAG_STINGRAY;
5514
5515         rc = bnxt_init_board(eth_dev);
5516         if (rc) {
5517                 PMD_DRV_LOG(ERR,
5518                             "Failed to initialize board rc: %x\n", rc);
5519                 return rc;
5520         }
5521
5522         rc = bnxt_alloc_pf_info(bp);
5523         if (rc)
5524                 goto error_free;
5525
5526         rc = bnxt_alloc_link_info(bp);
5527         if (rc)
5528                 goto error_free;
5529
5530         rc = bnxt_alloc_hwrm_resources(bp);
5531         if (rc) {
5532                 PMD_DRV_LOG(ERR,
5533                             "Failed to allocate hwrm resource rc: %x\n", rc);
5534                 goto error_free;
5535         }
5536         rc = bnxt_alloc_leds_info(bp);
5537         if (rc)
5538                 goto error_free;
5539
5540         rc = bnxt_alloc_cos_queues(bp);
5541         if (rc)
5542                 goto error_free;
5543
5544         rc = bnxt_init_resources(bp, false);
5545         if (rc)
5546                 goto error_free;
5547
5548         rc = bnxt_alloc_stats_mem(bp);
5549         if (rc)
5550                 goto error_free;
5551
5552         bnxt_alloc_switch_domain(bp);
5553
5554         /* Pass the information to the rte_eth_dev_close() that it should also
5555          * release the private port resources.
5556          */
5557         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5558
5559         PMD_DRV_LOG(INFO,
5560                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5561                     pci_dev->mem_resource[0].phys_addr,
5562                     pci_dev->mem_resource[0].addr);
5563
5564         return 0;
5565
5566 error_free:
5567         bnxt_dev_uninit(eth_dev);
5568         return rc;
5569 }
5570
5571
5572 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5573 {
5574         if (!ctx)
5575                 return;
5576
5577         if (ctx->va)
5578                 rte_free(ctx->va);
5579
5580         ctx->va = NULL;
5581         ctx->dma = RTE_BAD_IOVA;
5582         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5583 }
5584
5585 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5586 {
5587         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5588                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5589                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5590                                   bp->flow_stat->max_fc,
5591                                   false);
5592
5593         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5594                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5595                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5596                                   bp->flow_stat->max_fc,
5597                                   false);
5598
5599         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5600                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5601         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5602
5603         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5604                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5605         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5606
5607         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5608                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5609         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5610
5611         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5612                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5613         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5614 }
5615
5616 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5617 {
5618         bnxt_unregister_fc_ctx_mem(bp);
5619
5620         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5621         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5622         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5623         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5624 }
5625
5626 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5627 {
5628         if (BNXT_FLOW_XSTATS_EN(bp))
5629                 bnxt_uninit_fc_ctx_mem(bp);
5630 }
5631
5632 static void
5633 bnxt_free_error_recovery_info(struct bnxt *bp)
5634 {
5635         rte_free(bp->recovery_info);
5636         bp->recovery_info = NULL;
5637         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5638 }
5639
5640 static void
5641 bnxt_uninit_locks(struct bnxt *bp)
5642 {
5643         pthread_mutex_destroy(&bp->flow_lock);
5644         pthread_mutex_destroy(&bp->def_cp_lock);
5645         if (bp->rep_info)
5646                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5647 }
5648
5649 static int
5650 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5651 {
5652         int rc;
5653
5654         bnxt_free_int(bp);
5655         bnxt_free_mem(bp, reconfig_dev);
5656         bnxt_hwrm_func_buf_unrgtr(bp);
5657         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5658         bp->flags &= ~BNXT_FLAG_REGISTERED;
5659         bnxt_free_ctx_mem(bp);
5660         if (!reconfig_dev) {
5661                 bnxt_free_hwrm_resources(bp);
5662                 bnxt_free_error_recovery_info(bp);
5663         }
5664
5665         bnxt_uninit_ctx_mem(bp);
5666
5667         bnxt_uninit_locks(bp);
5668         bnxt_free_flow_stats_info(bp);
5669         bnxt_free_rep_info(bp);
5670         rte_free(bp->ptp_cfg);
5671         bp->ptp_cfg = NULL;
5672         return rc;
5673 }
5674
5675 static int
5676 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5677 {
5678         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5679                 return -EPERM;
5680
5681         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5682
5683         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5684                 bnxt_dev_close_op(eth_dev);
5685
5686         return 0;
5687 }
5688
5689 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5690 {
5691         struct bnxt *bp = eth_dev->data->dev_private;
5692         struct rte_eth_dev *vf_rep_eth_dev;
5693         int ret = 0, i;
5694
5695         if (!bp)
5696                 return -EINVAL;
5697
5698         for (i = 0; i < bp->num_reps; i++) {
5699                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5700                 if (!vf_rep_eth_dev)
5701                         continue;
5702                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit);
5703         }
5704         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5705
5706         return ret;
5707 }
5708
5709 static void bnxt_free_rep_info(struct bnxt *bp)
5710 {
5711         rte_free(bp->rep_info);
5712         bp->rep_info = NULL;
5713         rte_free(bp->cfa_code_map);
5714         bp->cfa_code_map = NULL;
5715 }
5716
5717 static int bnxt_init_rep_info(struct bnxt *bp)
5718 {
5719         int i = 0, rc;
5720
5721         if (bp->rep_info)
5722                 return 0;
5723
5724         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5725                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5726                                    0);
5727         if (!bp->rep_info) {
5728                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5729                 return -ENOMEM;
5730         }
5731         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5732                                        sizeof(*bp->cfa_code_map) *
5733                                        BNXT_MAX_CFA_CODE, 0);
5734         if (!bp->cfa_code_map) {
5735                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5736                 bnxt_free_rep_info(bp);
5737                 return -ENOMEM;
5738         }
5739
5740         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5741                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5742
5743         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5744         if (rc) {
5745                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5746                 bnxt_free_rep_info(bp);
5747                 return rc;
5748         }
5749         return rc;
5750 }
5751
5752 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5753                                struct rte_eth_devargs eth_da,
5754                                struct rte_eth_dev *backing_eth_dev)
5755 {
5756         struct rte_eth_dev *vf_rep_eth_dev;
5757         char name[RTE_ETH_NAME_MAX_LEN];
5758         struct bnxt *backing_bp;
5759         uint16_t num_rep;
5760         int i, ret = 0;
5761
5762         num_rep = eth_da.nb_representor_ports;
5763         if (num_rep > BNXT_MAX_VF_REPS) {
5764                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5765                             num_rep, BNXT_MAX_VF_REPS);
5766                 return -EINVAL;
5767         }
5768
5769         if (num_rep > RTE_MAX_ETHPORTS) {
5770                 PMD_DRV_LOG(ERR,
5771                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5772                             num_rep, RTE_MAX_ETHPORTS);
5773                 return -EINVAL;
5774         }
5775
5776         backing_bp = backing_eth_dev->data->dev_private;
5777
5778         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5779                 PMD_DRV_LOG(ERR,
5780                             "Not a PF or trusted VF. No Representor support\n");
5781                 /* Returning an error is not an option.
5782                  * Applications are not handling this correctly
5783                  */
5784                 return 0;
5785         }
5786
5787         if (bnxt_init_rep_info(backing_bp))
5788                 return 0;
5789
5790         for (i = 0; i < num_rep; i++) {
5791                 struct bnxt_vf_representor representor = {
5792                         .vf_id = eth_da.representor_ports[i],
5793                         .switch_domain_id = backing_bp->switch_domain_id,
5794                         .parent_dev = backing_eth_dev
5795                 };
5796
5797                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5798                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5799                                     representor.vf_id, BNXT_MAX_VF_REPS);
5800                         continue;
5801                 }
5802
5803                 /* representor port net_bdf_port */
5804                 snprintf(name, sizeof(name), "net_%s_representor_%d",
5805                          pci_dev->device.name, eth_da.representor_ports[i]);
5806
5807                 ret = rte_eth_dev_create(&pci_dev->device, name,
5808                                          sizeof(struct bnxt_vf_representor),
5809                                          NULL, NULL,
5810                                          bnxt_vf_representor_init,
5811                                          &representor);
5812
5813                 if (!ret) {
5814                         vf_rep_eth_dev = rte_eth_dev_allocated(name);
5815                         if (!vf_rep_eth_dev) {
5816                                 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5817                                             " for VF-Rep: %s.", name);
5818                                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5819                                 ret = -ENODEV;
5820                                 return ret;
5821                         }
5822                         backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
5823                                 vf_rep_eth_dev;
5824                         backing_bp->num_reps++;
5825                 } else {
5826                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5827                                     "representor %s.", name);
5828                         bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5829                 }
5830         }
5831
5832         return ret;
5833 }
5834
5835 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5836                           struct rte_pci_device *pci_dev)
5837 {
5838         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
5839         struct rte_eth_dev *backing_eth_dev;
5840         uint16_t num_rep;
5841         int ret = 0;
5842
5843         if (pci_dev->device.devargs) {
5844                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
5845                                             &eth_da);
5846                 if (ret)
5847                         return ret;
5848         }
5849
5850         num_rep = eth_da.nb_representor_ports;
5851         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
5852                     num_rep);
5853
5854         /* We could come here after first level of probe is already invoked
5855          * as part of an application bringup(OVS-DPDK vswitchd), so first check
5856          * for already allocated eth_dev for the backing device (PF/Trusted VF)
5857          */
5858         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5859         if (backing_eth_dev == NULL) {
5860                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
5861                                          sizeof(struct bnxt),
5862                                          eth_dev_pci_specific_init, pci_dev,
5863                                          bnxt_dev_init, NULL);
5864
5865                 if (ret || !num_rep)
5866                         return ret;
5867
5868                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5869         }
5870
5871         /* probe representor ports now */
5872         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
5873
5874         return ret;
5875 }
5876
5877 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5878 {
5879         struct rte_eth_dev *eth_dev;
5880
5881         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5882         if (!eth_dev)
5883                 return 0; /* Invoked typically only by OVS-DPDK, by the
5884                            * time it comes here the eth_dev is already
5885                            * deleted by rte_eth_dev_close(), so returning
5886                            * +ve value will at least help in proper cleanup
5887                            */
5888
5889         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
5890                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
5891                         return rte_eth_dev_destroy(eth_dev,
5892                                                    bnxt_vf_representor_uninit);
5893                 else
5894                         return rte_eth_dev_destroy(eth_dev,
5895                                                    bnxt_dev_uninit);
5896         } else {
5897                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5898         }
5899 }
5900
5901 static struct rte_pci_driver bnxt_rte_pmd = {
5902         .id_table = bnxt_pci_id_map,
5903         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
5904                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
5905                                                   * and OVS-DPDK
5906                                                   */
5907         .probe = bnxt_pci_probe,
5908         .remove = bnxt_pci_remove,
5909 };
5910
5911 static bool
5912 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5913 {
5914         if (strcmp(dev->device->driver->name, drv->driver.name))
5915                 return false;
5916
5917         return true;
5918 }
5919
5920 bool is_bnxt_supported(struct rte_eth_dev *dev)
5921 {
5922         return is_device_supported(dev, &bnxt_rte_pmd);
5923 }
5924
5925 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
5926 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5927 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5928 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");