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38 #include <rte_ethdev.h>
39 #include <rte_malloc.h>
40 #include <rte_cycles.h>
43 #include "bnxt_hwrm.h"
45 #define DRV_MODULE_NAME "bnxt"
46 static const char bnxt_version[] =
47 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
49 static struct rte_pci_id bnxt_pci_id_map[] = {
50 #define RTE_PCI_DEV_ID_DECL_BNXT(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
51 #include "rte_pci_dev_ids.h"
55 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
57 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
59 rte_free(eth_dev->data->mac_addrs);
60 bnxt_free_hwrm_resources(bp);
64 * Device configuration and status function
67 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
68 struct rte_eth_dev_info *dev_info)
70 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
71 uint16_t max_vnics, i, j, vpool, vrxq;
74 dev_info->max_mac_addrs = MAX_NUM_MAC_ADDR;
75 dev_info->max_hash_mac_addrs = 0;
79 dev_info->max_rx_queues = bp->pf.max_rx_rings;
80 dev_info->max_tx_queues = bp->pf.max_tx_rings;
81 dev_info->max_vfs = bp->pf.active_vfs;
82 dev_info->reta_size = bp->pf.max_rsscos_ctx;
83 max_vnics = bp->pf.max_vnics;
85 dev_info->max_rx_queues = bp->vf.max_rx_rings;
86 dev_info->max_tx_queues = bp->vf.max_tx_rings;
87 dev_info->reta_size = bp->vf.max_rsscos_ctx;
88 max_vnics = bp->vf.max_vnics;
91 /* Fast path specifics */
92 dev_info->min_rx_bufsize = 1;
93 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
95 dev_info->rx_offload_capa = 0;
96 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
97 DEV_TX_OFFLOAD_TCP_CKSUM |
98 DEV_TX_OFFLOAD_UDP_CKSUM |
99 DEV_TX_OFFLOAD_TCP_TSO;
102 dev_info->default_rxconf = (struct rte_eth_rxconf) {
108 .rx_free_thresh = 32,
112 dev_info->default_txconf = (struct rte_eth_txconf) {
118 .tx_free_thresh = 32,
120 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
121 ETH_TXQ_FLAGS_NOOFFLOADS,
126 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
127 * need further investigation.
131 vpool = 64; /* ETH_64_POOLS */
132 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
133 for (i = 0; i < 4; vpool >>= 1, i++) {
134 if (max_vnics > vpool) {
135 for (j = 0; j < 5; vrxq >>= 1, j++) {
136 if (dev_info->max_rx_queues > vrxq) {
142 /* Not enough resources to support VMDq */
146 /* Not enough resources to support VMDq */
150 dev_info->max_vmdq_pools = vpool;
151 dev_info->vmdq_queue_num = vrxq;
153 dev_info->vmdq_pool_base = 0;
154 dev_info->vmdq_queue_base = 0;
161 static struct eth_dev_ops bnxt_dev_ops = {
162 .dev_infos_get = bnxt_dev_info_get_op,
163 .dev_close = bnxt_dev_close_op,
166 static bool bnxt_vf_pciid(uint16_t id)
168 if (id == BROADCOM_DEV_ID_57304_VF ||
169 id == BROADCOM_DEV_ID_57406_VF)
174 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
177 struct bnxt *bp = eth_dev->data->dev_private;
179 /* enable device (incl. PCI PM wakeup), and bus-mastering */
180 if (!eth_dev->pci_dev->mem_resource[0].addr) {
182 "Cannot find PCI device base address, aborting\n");
184 goto init_err_disable;
187 bp->eth_dev = eth_dev;
188 bp->pdev = eth_dev->pci_dev;
190 bp->bar0 = (void *)eth_dev->pci_dev->mem_resource[0].addr;
192 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
194 goto init_err_release;
208 bnxt_dev_init(struct rte_eth_dev *eth_dev)
210 static int version_printed;
214 if (version_printed++ == 0)
215 RTE_LOG(INFO, PMD, "%s", bnxt_version);
217 if (eth_dev->pci_dev->addr.function >= 2 &&
218 eth_dev->pci_dev->addr.function < 4) {
219 RTE_LOG(ERR, PMD, "Function not enabled %x:\n",
220 eth_dev->pci_dev->addr.function);
225 rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
226 bp = eth_dev->data->dev_private;
228 if (bnxt_vf_pciid(eth_dev->pci_dev->id.device_id))
229 bp->flags |= BNXT_FLAG_VF;
231 rc = bnxt_init_board(eth_dev);
234 "Board initialization failed rc: %x\n", rc);
237 eth_dev->dev_ops = &bnxt_dev_ops;
238 /* eth_dev->rx_pkt_burst = &bnxt_recv_pkts; */
239 /* eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; */
241 rc = bnxt_alloc_hwrm_resources(bp);
244 "hwrm resource allocation failure rc: %x\n", rc);
247 rc = bnxt_hwrm_ver_get(bp);
250 bnxt_hwrm_queue_qportcfg(bp);
252 /* Get the MAX capabilities for this function */
253 rc = bnxt_hwrm_func_qcaps(bp);
255 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
258 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
259 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR, 0);
260 if (eth_dev->data->mac_addrs == NULL) {
262 "Failed to alloc %u bytes needed to store MAC addr tbl",
263 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR);
267 /* Copy the permanent MAC from the qcap response address now. */
269 memcpy(bp->mac_addr, bp->pf.mac_addr, sizeof(bp->mac_addr));
271 memcpy(bp->mac_addr, bp->vf.mac_addr, sizeof(bp->mac_addr));
272 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
274 rc = bnxt_hwrm_func_driver_register(bp, 0,
278 "Failed to register driver");
284 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
285 eth_dev->pci_dev->mem_resource[0].phys_addr,
286 eth_dev->pci_dev->mem_resource[0].addr);
291 eth_dev->driver->eth_dev_uninit(eth_dev);
297 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
298 struct bnxt *bp = eth_dev->data->dev_private;
301 if (eth_dev->data->mac_addrs)
302 rte_free(eth_dev->data->mac_addrs);
303 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
304 bnxt_free_hwrm_resources(bp);
308 static struct eth_driver bnxt_rte_pmd = {
310 .name = "rte_" DRV_MODULE_NAME "_pmd",
311 .id_table = bnxt_pci_id_map,
312 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
314 .eth_dev_init = bnxt_dev_init,
315 .eth_dev_uninit = bnxt_dev_uninit,
316 .dev_private_size = sizeof(struct bnxt),
319 static int bnxt_rte_pmd_init(const char *name, const char *params __rte_unused)
321 RTE_LOG(INFO, PMD, "bnxt_rte_pmd_init() called for %s\n", name);
322 rte_eth_driver_register(&bnxt_rte_pmd);
326 static struct rte_driver bnxt_pmd_drv = {
329 .init = bnxt_rte_pmd_init,
332 PMD_REGISTER_DRIVER(bnxt_pmd_drv);