drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_cpr.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30 #include "bnxt_util.h"
  31
  32 #define DRV_MODULE_NAME         "bnxt"
  33 static const char bnxt_version[] =
  34         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  35 int bnxt_logtype_driver;
  36
  37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  38
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  43 #define BROADCOM_DEV_ID_57301 0x16c8
  44 #define BROADCOM_DEV_ID_57302 0x16c9
  45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  48 #define BROADCOM_DEV_ID_NS2 0x16cd
  49 #define BROADCOM_DEV_ID_57311 0x16ce
  50 #define BROADCOM_DEV_ID_57312 0x16cf
  51 #define BROADCOM_DEV_ID_57402 0x16d0
  52 #define BROADCOM_DEV_ID_57404 0x16d1
  53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  57 #define BROADCOM_DEV_ID_57412 0x16d6
  58 #define BROADCOM_DEV_ID_57414 0x16d7
  59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  62 #define BROADCOM_DEV_ID_57412_MF 0x16de
  63 #define BROADCOM_DEV_ID_57314 0x16df
  64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  75 #define BROADCOM_DEV_ID_57508 0x1750
  76 #define BROADCOM_DEV_ID_57504 0x1751
  77 #define BROADCOM_DEV_ID_57502 0x1752
  78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
  79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
  80 #define BROADCOM_DEV_ID_58802 0xd802
  81 #define BROADCOM_DEV_ID_58804 0xd804
  82 #define BROADCOM_DEV_ID_58808 0x16f0
  83 #define BROADCOM_DEV_ID_58802_VF 0xd800
  84
  85 static const struct rte_pci_id bnxt_pci_id_map[] = {
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  87                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  89                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 130         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 131         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
 132         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
 133         { .vendor_id = 0, /* sentinel */ },
 134 };
 135
 136 #define BNXT_ETH_RSS_SUPPORT (  \
 137         ETH_RSS_IPV4 |          \
 138         ETH_RSS_NONFRAG_IPV4_TCP |      \
 139         ETH_RSS_NONFRAG_IPV4_UDP |      \
 140         ETH_RSS_IPV6 |          \
 141         ETH_RSS_NONFRAG_IPV6_TCP |      \
 142         ETH_RSS_NONFRAG_IPV6_UDP)
 143
 144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 145                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 146                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 147                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 148                                      DEV_TX_OFFLOAD_TCP_TSO | \
 149                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 150                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 152                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 153                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 154                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 155                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 156
 157 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 158                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 159                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 160                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 161                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 162                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 163                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 164                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 165                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 166                                      DEV_RX_OFFLOAD_TCP_LRO)
 167
 168 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 169 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 170 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 171 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 172 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 173 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 174 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 175
 176 int is_bnxt_in_error(struct bnxt *bp)
 177 {
 178         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 179                 return -EIO;
 180         if (bp->flags & BNXT_FLAG_FW_RESET)
 181                 return -EBUSY;
 182
 183         return 0;
 184 }
 185
 186 /***********************/
 187
 188 /*
 189  * High level utility functions
 190  */
 191
 192 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 193 {
 194         if (!BNXT_CHIP_THOR(bp))
 195                 return 1;
 196
 197         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 198                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 199                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 200 }
 201
 202 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 203 {
 204         if (!BNXT_CHIP_THOR(bp))
 205                 return HW_HASH_INDEX_SIZE;
 206
 207         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 208 }
 209
 210 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 211 {
 212         bnxt_free_filter_mem(bp);
 213         bnxt_free_vnic_attributes(bp);
 214         bnxt_free_vnic_mem(bp);
 215
 216         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 217          * If the number of rings change across fw update,
 218          * we don't have much choice except to warn the user.
 219          */
 220         if (!reconfig) {
 221                 bnxt_free_stats(bp);
 222                 bnxt_free_tx_rings(bp);
 223                 bnxt_free_rx_rings(bp);
 224         }
 225         bnxt_free_async_cp_ring(bp);
 226 }
 227
 228 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 229 {
 230         int rc;
 231
 232         rc = bnxt_alloc_ring_grps(bp);
 233         if (rc)
 234                 goto alloc_mem_err;
 235
 236         rc = bnxt_alloc_async_ring_struct(bp);
 237         if (rc)
 238                 goto alloc_mem_err;
 239
 240         rc = bnxt_alloc_vnic_mem(bp);
 241         if (rc)
 242                 goto alloc_mem_err;
 243
 244         rc = bnxt_alloc_vnic_attributes(bp);
 245         if (rc)
 246                 goto alloc_mem_err;
 247
 248         rc = bnxt_alloc_filter_mem(bp);
 249         if (rc)
 250                 goto alloc_mem_err;
 251
 252         rc = bnxt_alloc_async_cp_ring(bp);
 253         if (rc)
 254                 goto alloc_mem_err;
 255
 256         return 0;
 257
 258 alloc_mem_err:
 259         bnxt_free_mem(bp, reconfig);
 260         return rc;
 261 }
 262
 263 static int bnxt_init_chip(struct bnxt *bp)
 264 {
 265         struct bnxt_rx_queue *rxq;
 266         struct rte_eth_link new;
 267         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 268         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 269         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 270         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 271         uint32_t intr_vector = 0;
 272         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 273         uint32_t vec = BNXT_MISC_VEC_ID;
 274         unsigned int i, j;
 275         int rc;
 276
 277         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 278                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 279                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 280                 bp->flags |= BNXT_FLAG_JUMBO;
 281         } else {
 282                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 283                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 284                 bp->flags &= ~BNXT_FLAG_JUMBO;
 285         }
 286
 287         /* THOR does not support ring groups.
 288          * But we will use the array to save RSS context IDs.
 289          */
 290         if (BNXT_CHIP_THOR(bp))
 291                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 292
 293         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 294         if (rc) {
 295                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 296                 goto err_out;
 297         }
 298
 299         rc = bnxt_alloc_hwrm_rings(bp);
 300         if (rc) {
 301                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 302                 goto err_out;
 303         }
 304
 305         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 306         if (rc) {
 307                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 308                 goto err_out;
 309         }
 310
 311         rc = bnxt_mq_rx_configure(bp);
 312         if (rc) {
 313                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 314                 goto err_out;
 315         }
 316
 317         /* VNIC configuration */
 318         for (i = 0; i < bp->nr_vnics; i++) {
 319                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 320                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 321                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 322
 323                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 324                 if (!vnic->fw_grp_ids) {
 325                         PMD_DRV_LOG(ERR,
 326                                     "Failed to alloc %d bytes for group ids\n",
 327                                     size);
 328                         rc = -ENOMEM;
 329                         goto err_out;
 330                 }
 331                 memset(vnic->fw_grp_ids, -1, size);
 332
 333                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 334                             i, vnic, vnic->fw_grp_ids);
 335
 336                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 337                 if (rc) {
 338                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 339                                 i, rc);
 340                         goto err_out;
 341                 }
 342
 343                 /* Alloc RSS context only if RSS mode is enabled */
 344                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 345                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 346
 347                         rc = 0;
 348                         for (j = 0; j < nr_ctxs; j++) {
 349                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 350                                 if (rc)
 351                                         break;
 352                         }
 353                         if (rc) {
 354                                 PMD_DRV_LOG(ERR,
 355                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 356                                   i, j, rc);
 357                                 goto err_out;
 358                         }
 359                         vnic->num_lb_ctxts = nr_ctxs;
 360                 }
 361
 362                 /*
 363                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 364                  * setting is not available at this time, it will not be
 365                  * configured correctly in the CFA.
 366                  */
 367                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 368                         vnic->vlan_strip = true;
 369                 else
 370                         vnic->vlan_strip = false;
 371
 372                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 373                 if (rc) {
 374                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 375                                 i, rc);
 376                         goto err_out;
 377                 }
 378
 379                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 380                 if (rc) {
 381                         PMD_DRV_LOG(ERR,
 382                                 "HWRM vnic %d filter failure rc: %x\n",
 383                                 i, rc);
 384                         goto err_out;
 385                 }
 386
 387                 for (j = 0; j < bp->rx_nr_rings; j++) {
 388                         rxq = bp->eth_dev->data->rx_queues[j];
 389
 390                         PMD_DRV_LOG(DEBUG,
 391                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 392                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 393
 394                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 395                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 396                 }
 397
 398                 rc = bnxt_vnic_rss_configure(bp, vnic);
 399                 if (rc) {
 400                         PMD_DRV_LOG(ERR,
 401                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 402                         goto err_out;
 403                 }
 404
 405                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 406
 407                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 408                     DEV_RX_OFFLOAD_TCP_LRO)
 409                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 410                 else
 411                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 412         }
 413         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 414         if (rc) {
 415                 PMD_DRV_LOG(ERR,
 416                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 417                 goto err_out;
 418         }
 419
 420         /* check and configure queue intr-vector mapping */
 421         if ((rte_intr_cap_multiple(intr_handle) ||
 422              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 423             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 424                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 425                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 426                 if (intr_vector > bp->rx_cp_nr_rings) {
 427                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 428                                         bp->rx_cp_nr_rings);
 429                         return -ENOTSUP;
 430                 }
 431                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 432                 if (rc)
 433                         return rc;
 434         }
 435
 436         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 437                 intr_handle->intr_vec =
 438                         rte_zmalloc("intr_vec",
 439                                     bp->eth_dev->data->nb_rx_queues *
 440                                     sizeof(int), 0);
 441                 if (intr_handle->intr_vec == NULL) {
 442                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 443                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 444                         rc = -ENOMEM;
 445                         goto err_disable;
 446                 }
 447                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 448                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 449                          intr_handle->intr_vec, intr_handle->nb_efd,
 450                         intr_handle->max_intr);
 451                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 452                      queue_id++) {
 453                         intr_handle->intr_vec[queue_id] =
 454                                                         vec + BNXT_RX_VEC_START;
 455                         if (vec < base + intr_handle->nb_efd - 1)
 456                                 vec++;
 457                 }
 458         }
 459
 460         /* enable uio/vfio intr/eventfd mapping */
 461         rc = rte_intr_enable(intr_handle);
 462         if (rc)
 463                 goto err_free;
 464
 465         rc = bnxt_get_hwrm_link_config(bp, &new);
 466         if (rc) {
 467                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 468                 goto err_free;
 469         }
 470
 471         if (!bp->link_info.link_up) {
 472                 rc = bnxt_set_hwrm_link_config(bp, true);
 473                 if (rc) {
 474                         PMD_DRV_LOG(ERR,
 475                                 "HWRM link config failure rc: %x\n", rc);
 476                         goto err_free;
 477                 }
 478         }
 479         bnxt_print_link_info(bp->eth_dev);
 480
 481         return 0;
 482
 483 err_free:
 484         rte_free(intr_handle->intr_vec);
 485 err_disable:
 486         rte_intr_efd_disable(intr_handle);
 487 err_out:
 488         /* Some of the error status returned by FW may not be from errno.h */
 489         if (rc > 0)
 490                 rc = -EIO;
 491
 492         return rc;
 493 }
 494
 495 static int bnxt_shutdown_nic(struct bnxt *bp)
 496 {
 497         bnxt_free_all_hwrm_resources(bp);
 498         bnxt_free_all_filters(bp);
 499         bnxt_free_all_vnics(bp);
 500         return 0;
 501 }
 502
 503 static int bnxt_init_nic(struct bnxt *bp)
 504 {
 505         int rc;
 506
 507         if (BNXT_HAS_RING_GRPS(bp)) {
 508                 rc = bnxt_init_ring_grps(bp);
 509                 if (rc)
 510                         return rc;
 511         }
 512
 513         bnxt_init_vnics(bp);
 514         bnxt_init_filters(bp);
 515
 516         return 0;
 517 }
 518
 519 /*
 520  * Device configuration and status function
 521  */
 522
 523 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 524                                 struct rte_eth_dev_info *dev_info)
 525 {
 526         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 527         struct bnxt *bp = eth_dev->data->dev_private;
 528         uint16_t max_vnics, i, j, vpool, vrxq;
 529         unsigned int max_rx_rings;
 530         int rc;
 531
 532         rc = is_bnxt_in_error(bp);
 533         if (rc)
 534                 return rc;
 535
 536         /* MAC Specifics */
 537         dev_info->max_mac_addrs = bp->max_l2_ctx;
 538         dev_info->max_hash_mac_addrs = 0;
 539
 540         /* PF/VF specifics */
 541         if (BNXT_PF(bp))
 542                 dev_info->max_vfs = pdev->max_vfs;
 543
 544         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 545         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 546         dev_info->max_rx_queues = max_rx_rings;
 547         dev_info->max_tx_queues = max_rx_rings;
 548         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 549         dev_info->hash_key_size = 40;
 550         max_vnics = bp->max_vnics;
 551
 552         /* MTU specifics */
 553         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 554         dev_info->max_mtu = BNXT_MAX_MTU;
 555
 556         /* Fast path specifics */
 557         dev_info->min_rx_bufsize = 1;
 558         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 559
 560         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 561         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 562                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 563         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 564         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 565
 566         /* *INDENT-OFF* */
 567         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 568                 .rx_thresh = {
 569                         .pthresh = 8,
 570                         .hthresh = 8,
 571                         .wthresh = 0,
 572                 },
 573                 .rx_free_thresh = 32,
 574                 /* If no descriptors available, pkts are dropped by default */
 575                 .rx_drop_en = 1,
 576         };
 577
 578         dev_info->default_txconf = (struct rte_eth_txconf) {
 579                 .tx_thresh = {
 580                         .pthresh = 32,
 581                         .hthresh = 0,
 582                         .wthresh = 0,
 583                 },
 584                 .tx_free_thresh = 32,
 585                 .tx_rs_thresh = 32,
 586         };
 587         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 588
 589         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 590         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 591         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 592         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 593         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 594
 595         /* *INDENT-ON* */
 596
 597         /*
 598          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 599          *       need further investigation.
 600          */
 601
 602         /* VMDq resources */
 603         vpool = 64; /* ETH_64_POOLS */
 604         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 605         for (i = 0; i < 4; vpool >>= 1, i++) {
 606                 if (max_vnics > vpool) {
 607                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 608                                 if (dev_info->max_rx_queues > vrxq) {
 609                                         if (vpool > vrxq)
 610                                                 vpool = vrxq;
 611                                         goto found;
 612                                 }
 613                         }
 614                         /* Not enough resources to support VMDq */
 615                         break;
 616                 }
 617         }
 618         /* Not enough resources to support VMDq */
 619         vpool = 0;
 620         vrxq = 0;
 621 found:
 622         dev_info->max_vmdq_pools = vpool;
 623         dev_info->vmdq_queue_num = vrxq;
 624
 625         dev_info->vmdq_pool_base = 0;
 626         dev_info->vmdq_queue_base = 0;
 627
 628         return 0;
 629 }
 630
 631 /* Configure the device based on the configuration provided */
 632 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 633 {
 634         struct bnxt *bp = eth_dev->data->dev_private;
 635         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 636         int rc;
 637
 638         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 639         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 640         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 641         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 642
 643         rc = is_bnxt_in_error(bp);
 644         if (rc)
 645                 return rc;
 646
 647         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 648                 rc = bnxt_hwrm_check_vf_rings(bp);
 649                 if (rc) {
 650                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 651                         return -ENOSPC;
 652                 }
 653
 654                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 655                 if (rc) {
 656                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 657                         return -ENOSPC;
 658                 }
 659         } else {
 660                 /* legacy driver needs to get updated values */
 661                 rc = bnxt_hwrm_func_qcaps(bp);
 662                 if (rc) {
 663                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 664                         return rc;
 665                 }
 666         }
 667
 668         /* Inherit new configurations */
 669         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 670             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 671             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 672                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 673             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 674             bp->max_stat_ctx)
 675                 goto resource_error;
 676
 677         if (BNXT_HAS_RING_GRPS(bp) &&
 678             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 679                 goto resource_error;
 680
 681         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 682             bp->max_vnics < eth_dev->data->nb_rx_queues)
 683                 goto resource_error;
 684
 685         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 686         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 687
 688         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 689                 eth_dev->data->mtu =
 690                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 691                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 692                         BNXT_NUM_VLANS;
 693                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 694         }
 695         return 0;
 696
 697 resource_error:
 698         PMD_DRV_LOG(ERR,
 699                     "Insufficient resources to support requested config\n");
 700         PMD_DRV_LOG(ERR,
 701                     "Num Queues Requested: Tx %d, Rx %d\n",
 702                     eth_dev->data->nb_tx_queues,
 703                     eth_dev->data->nb_rx_queues);
 704         PMD_DRV_LOG(ERR,
 705                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 706                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 707                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 708         return -ENOSPC;
 709 }
 710
 711 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 712 {
 713         struct rte_eth_link *link = &eth_dev->data->dev_link;
 714
 715         if (link->link_status)
 716                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 717                         eth_dev->data->port_id,
 718                         (uint32_t)link->link_speed,
 719                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 720                         ("full-duplex") : ("half-duplex\n"));
 721         else
 722                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 723                         eth_dev->data->port_id);
 724 }
 725
 726 /*
 727  * Determine whether the current configuration requires support for scattered
 728  * receive; return 1 if scattered receive is required and 0 if not.
 729  */
 730 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 731 {
 732         uint16_t buf_size;
 733         int i;
 734
 735         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 736                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 737
 738                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 739                                       RTE_PKTMBUF_HEADROOM);
 740                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 741                         return 1;
 742         }
 743         return 0;
 744 }
 745
 746 static eth_rx_burst_t
 747 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 748 {
 749 #ifdef RTE_ARCH_X86
 750 #ifndef RTE_LIBRTE_IEEE1588
 751         /*
 752          * Vector mode receive can be enabled only if scatter rx is not
 753          * in use and rx offloads are limited to VLAN stripping and
 754          * CRC stripping.
 755          */
 756         if (!eth_dev->data->scattered_rx &&
 757             !(eth_dev->data->dev_conf.rxmode.offloads &
 758               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 759                 DEV_RX_OFFLOAD_KEEP_CRC |
 760                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 761                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 762                 DEV_RX_OFFLOAD_UDP_CKSUM |
 763                 DEV_RX_OFFLOAD_TCP_CKSUM |
 764                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 765                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 766                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 767                             eth_dev->data->port_id);
 768                 return bnxt_recv_pkts_vec;
 769         }
 770         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 771                     eth_dev->data->port_id);
 772         PMD_DRV_LOG(INFO,
 773                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 774                     eth_dev->data->port_id,
 775                     eth_dev->data->scattered_rx,
 776                     eth_dev->data->dev_conf.rxmode.offloads);
 777 #endif
 778 #endif
 779         return bnxt_recv_pkts;
 780 }
 781
 782 static eth_tx_burst_t
 783 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 784 {
 785 #ifdef RTE_ARCH_X86
 786 #ifndef RTE_LIBRTE_IEEE1588
 787         /*
 788          * Vector mode transmit can be enabled only if not using scatter rx
 789          * or tx offloads.
 790          */
 791         if (!eth_dev->data->scattered_rx &&
 792             !eth_dev->data->dev_conf.txmode.offloads) {
 793                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 794                             eth_dev->data->port_id);
 795                 return bnxt_xmit_pkts_vec;
 796         }
 797         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 798                     eth_dev->data->port_id);
 799         PMD_DRV_LOG(INFO,
 800                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 801                     eth_dev->data->port_id,
 802                     eth_dev->data->scattered_rx,
 803                     eth_dev->data->dev_conf.txmode.offloads);
 804 #endif
 805 #endif
 806         return bnxt_xmit_pkts;
 807 }
 808
 809 static int bnxt_handle_if_change_status(struct bnxt *bp)
 810 {
 811         int rc;
 812
 813         /* Since fw has undergone a reset and lost all contexts,
 814          * set fatal flag to not issue hwrm during cleanup
 815          */
 816         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 817         bnxt_uninit_resources(bp, true);
 818
 819         /* clear fatal flag so that re-init happens */
 820         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 821         rc = bnxt_init_resources(bp, true);
 822
 823         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 824
 825         return rc;
 826 }
 827
 828 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 829 {
 830         struct bnxt *bp = eth_dev->data->dev_private;
 831         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 832         int vlan_mask = 0;
 833         int rc;
 834
 835         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 836                 PMD_DRV_LOG(ERR,
 837                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 838                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 839         }
 840
 841         bnxt_enable_int(bp);
 842         rc = bnxt_hwrm_if_change(bp, 1);
 843         if (!rc) {
 844                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 845                         rc = bnxt_handle_if_change_status(bp);
 846                         if (rc)
 847                                 return rc;
 848                 }
 849         }
 850
 851         rc = bnxt_init_chip(bp);
 852         if (rc)
 853                 goto error;
 854
 855         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 856
 857         bnxt_link_update_op(eth_dev, 1);
 858
 859         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 860                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 861         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 862                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 863         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 864         if (rc)
 865                 goto error;
 866
 867         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 868         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 869
 870         bp->flags |= BNXT_FLAG_INIT_DONE;
 871         eth_dev->data->dev_started = 1;
 872         bp->dev_stopped = 0;
 873         bnxt_schedule_fw_health_check(bp);
 874         return 0;
 875
 876 error:
 877         bnxt_hwrm_if_change(bp, 0);
 878         bnxt_shutdown_nic(bp);
 879         bnxt_free_tx_mbufs(bp);
 880         bnxt_free_rx_mbufs(bp);
 881         return rc;
 882 }
 883
 884 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 885 {
 886         struct bnxt *bp = eth_dev->data->dev_private;
 887         int rc = 0;
 888
 889         if (!bp->link_info.link_up)
 890                 rc = bnxt_set_hwrm_link_config(bp, true);
 891         if (!rc)
 892                 eth_dev->data->dev_link.link_status = 1;
 893
 894         bnxt_print_link_info(eth_dev);
 895         return 0;
 896 }
 897
 898 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 899 {
 900         struct bnxt *bp = eth_dev->data->dev_private;
 901
 902         eth_dev->data->dev_link.link_status = 0;
 903         bnxt_set_hwrm_link_config(bp, false);
 904         bp->link_info.link_up = 0;
 905
 906         return 0;
 907 }
 908
 909 /* Unload the driver, release resources */
 910 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 911 {
 912         struct bnxt *bp = eth_dev->data->dev_private;
 913         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 914         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 915
 916         eth_dev->data->dev_started = 0;
 917         /* Prevent crashes when queues are still in use */
 918         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 919         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 920
 921         bnxt_disable_int(bp);
 922
 923         /* disable uio/vfio intr/eventfd mapping */
 924         rte_intr_disable(intr_handle);
 925
 926         bnxt_cancel_fw_health_check(bp);
 927
 928         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 929         if (bp->eth_dev->data->dev_started) {
 930                 /* TBD: STOP HW queues DMA */
 931                 eth_dev->data->dev_link.link_status = 0;
 932         }
 933         bnxt_dev_set_link_down_op(eth_dev);
 934         /* Wait for link to be reset and the async notification to process. */
 935         rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
 936
 937         /* Clean queue intr-vector mapping */
 938         rte_intr_efd_disable(intr_handle);
 939         if (intr_handle->intr_vec != NULL) {
 940                 rte_free(intr_handle->intr_vec);
 941                 intr_handle->intr_vec = NULL;
 942         }
 943
 944         bnxt_hwrm_port_clr_stats(bp);
 945         bnxt_free_tx_mbufs(bp);
 946         bnxt_free_rx_mbufs(bp);
 947         /* Process any remaining notifications in default completion queue */
 948         bnxt_int_handler(eth_dev);
 949         bnxt_shutdown_nic(bp);
 950         bnxt_hwrm_if_change(bp, 0);
 951         bp->dev_stopped = 1;
 952 }
 953
 954 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 955 {
 956         struct bnxt *bp = eth_dev->data->dev_private;
 957
 958         if (bp->dev_stopped == 0)
 959                 bnxt_dev_stop_op(eth_dev);
 960
 961         if (eth_dev->data->mac_addrs != NULL) {
 962                 rte_free(eth_dev->data->mac_addrs);
 963                 eth_dev->data->mac_addrs = NULL;
 964         }
 965         if (bp->grp_info != NULL) {
 966                 rte_free(bp->grp_info);
 967                 bp->grp_info = NULL;
 968         }
 969
 970         bnxt_dev_uninit(eth_dev);
 971 }
 972
 973 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 974                                     uint32_t index)
 975 {
 976         struct bnxt *bp = eth_dev->data->dev_private;
 977         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 978         struct bnxt_vnic_info *vnic;
 979         struct bnxt_filter_info *filter, *temp_filter;
 980         uint32_t i;
 981
 982         if (is_bnxt_in_error(bp))
 983                 return;
 984
 985         /*
 986          * Loop through all VNICs from the specified filter flow pools to
 987          * remove the corresponding MAC addr filter
 988          */
 989         for (i = 0; i < bp->nr_vnics; i++) {
 990                 if (!(pool_mask & (1ULL << i)))
 991                         continue;
 992
 993                 vnic = &bp->vnic_info[i];
 994                 filter = STAILQ_FIRST(&vnic->filter);
 995                 while (filter) {
 996                         temp_filter = STAILQ_NEXT(filter, next);
 997                         if (filter->mac_index == index) {
 998                                 STAILQ_REMOVE(&vnic->filter, filter,
 999                                                 bnxt_filter_info, next);
1000                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1001                                 filter->mac_index = INVALID_MAC_INDEX;
1002                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1003                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1004                                                    filter, next);
1005                         }
1006                         filter = temp_filter;
1007                 }
1008         }
1009 }
1010
1011 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1012                                 struct rte_ether_addr *mac_addr,
1013                                 uint32_t index, uint32_t pool)
1014 {
1015         struct bnxt *bp = eth_dev->data->dev_private;
1016         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1017         struct bnxt_filter_info *filter;
1018         int rc = 0;
1019
1020         rc = is_bnxt_in_error(bp);
1021         if (rc)
1022                 return rc;
1023
1024         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1025                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1026                 return -ENOTSUP;
1027         }
1028
1029         if (!vnic) {
1030                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1031                 return -EINVAL;
1032         }
1033         /* Attach requested MAC address to the new l2_filter */
1034         STAILQ_FOREACH(filter, &vnic->filter, next) {
1035                 if (filter->mac_index == index) {
1036                         PMD_DRV_LOG(ERR,
1037                                 "MAC addr already existed for pool %d\n", pool);
1038                         return 0;
1039                 }
1040         }
1041         filter = bnxt_alloc_filter(bp);
1042         if (!filter) {
1043                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1044                 return -ENODEV;
1045         }
1046
1047         filter->mac_index = index;
1048         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1049
1050         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1051         if (!rc) {
1052                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1053         } else {
1054                 filter->mac_index = INVALID_MAC_INDEX;
1055                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1056                 bnxt_free_filter(bp, filter);
1057         }
1058
1059         return rc;
1060 }
1061
1062 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1063 {
1064         int rc = 0;
1065         struct bnxt *bp = eth_dev->data->dev_private;
1066         struct rte_eth_link new;
1067         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1068
1069         rc = is_bnxt_in_error(bp);
1070         if (rc)
1071                 return rc;
1072
1073         memset(&new, 0, sizeof(new));
1074         do {
1075                 /* Retrieve link info from hardware */
1076                 rc = bnxt_get_hwrm_link_config(bp, &new);
1077                 if (rc) {
1078                         new.link_speed = ETH_LINK_SPEED_100M;
1079                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1080                         PMD_DRV_LOG(ERR,
1081                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1082                         goto out;
1083                 }
1084
1085                 if (!wait_to_complete || new.link_status)
1086                         break;
1087
1088                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1089         } while (cnt--);
1090
1091 out:
1092         /* Timed out or success */
1093         if (new.link_status != eth_dev->data->dev_link.link_status ||
1094         new.link_speed != eth_dev->data->dev_link.link_speed) {
1095                 rte_eth_linkstatus_set(eth_dev, &new);
1096
1097                 _rte_eth_dev_callback_process(eth_dev,
1098                                               RTE_ETH_EVENT_INTR_LSC,
1099                                               NULL);
1100
1101                 bnxt_print_link_info(eth_dev);
1102         }
1103
1104         return rc;
1105 }
1106
1107 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1108 {
1109         struct bnxt *bp = eth_dev->data->dev_private;
1110         struct bnxt_vnic_info *vnic;
1111         uint32_t old_flags;
1112         int rc;
1113
1114         rc = is_bnxt_in_error(bp);
1115         if (rc)
1116                 return rc;
1117
1118         if (bp->vnic_info == NULL)
1119                 return 0;
1120
1121         vnic = &bp->vnic_info[0];
1122
1123         old_flags = vnic->flags;
1124         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1125         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1126         if (rc != 0)
1127                 vnic->flags = old_flags;
1128
1129         return rc;
1130 }
1131
1132 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1133 {
1134         struct bnxt *bp = eth_dev->data->dev_private;
1135         struct bnxt_vnic_info *vnic;
1136         uint32_t old_flags;
1137         int rc;
1138
1139         rc = is_bnxt_in_error(bp);
1140         if (rc)
1141                 return rc;
1142
1143         if (bp->vnic_info == NULL)
1144                 return 0;
1145
1146         vnic = &bp->vnic_info[0];
1147
1148         old_flags = vnic->flags;
1149         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1150         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1151         if (rc != 0)
1152                 vnic->flags = old_flags;
1153
1154         return rc;
1155 }
1156
1157 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1158 {
1159         struct bnxt *bp = eth_dev->data->dev_private;
1160         struct bnxt_vnic_info *vnic;
1161         uint32_t old_flags;
1162         int rc;
1163
1164         rc = is_bnxt_in_error(bp);
1165         if (rc)
1166                 return rc;
1167
1168         if (bp->vnic_info == NULL)
1169                 return 0;
1170
1171         vnic = &bp->vnic_info[0];
1172
1173         old_flags = vnic->flags;
1174         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1175         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1176         if (rc != 0)
1177                 vnic->flags = old_flags;
1178
1179         return rc;
1180 }
1181
1182 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1183 {
1184         struct bnxt *bp = eth_dev->data->dev_private;
1185         struct bnxt_vnic_info *vnic;
1186         uint32_t old_flags;
1187         int rc;
1188
1189         rc = is_bnxt_in_error(bp);
1190         if (rc)
1191                 return rc;
1192
1193         if (bp->vnic_info == NULL)
1194                 return 0;
1195
1196         vnic = &bp->vnic_info[0];
1197
1198         old_flags = vnic->flags;
1199         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1200         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1201         if (rc != 0)
1202                 vnic->flags = old_flags;
1203
1204         return rc;
1205 }
1206
1207 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1208 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1209 {
1210         if (qid >= bp->rx_nr_rings)
1211                 return NULL;
1212
1213         return bp->eth_dev->data->rx_queues[qid];
1214 }
1215
1216 /* Return rxq corresponding to a given rss table ring/group ID. */
1217 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1218 {
1219         struct bnxt_rx_queue *rxq;
1220         unsigned int i;
1221
1222         if (!BNXT_HAS_RING_GRPS(bp)) {
1223                 for (i = 0; i < bp->rx_nr_rings; i++) {
1224                         rxq = bp->eth_dev->data->rx_queues[i];
1225                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1226                                 return rxq->index;
1227                 }
1228         } else {
1229                 for (i = 0; i < bp->rx_nr_rings; i++) {
1230                         if (bp->grp_info[i].fw_grp_id == fwr)
1231                                 return i;
1232                 }
1233         }
1234
1235         return INVALID_HW_RING_ID;
1236 }
1237
1238 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1239                             struct rte_eth_rss_reta_entry64 *reta_conf,
1240                             uint16_t reta_size)
1241 {
1242         struct bnxt *bp = eth_dev->data->dev_private;
1243         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1244         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1245         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1246         uint16_t idx, sft;
1247         int i, rc;
1248
1249         rc = is_bnxt_in_error(bp);
1250         if (rc)
1251                 return rc;
1252
1253         if (!vnic->rss_table)
1254                 return -EINVAL;
1255
1256         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1257                 return -EINVAL;
1258
1259         if (reta_size != tbl_size) {
1260                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1261                         "(%d) must equal the size supported by the hardware "
1262                         "(%d)\n", reta_size, tbl_size);
1263                 return -EINVAL;
1264         }
1265
1266         for (i = 0; i < reta_size; i++) {
1267                 struct bnxt_rx_queue *rxq;
1268
1269                 idx = i / RTE_RETA_GROUP_SIZE;
1270                 sft = i % RTE_RETA_GROUP_SIZE;
1271
1272                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1273                         continue;
1274
1275                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1276                 if (!rxq) {
1277                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1278                         return -EINVAL;
1279                 }
1280
1281                 if (BNXT_CHIP_THOR(bp)) {
1282                         vnic->rss_table[i * 2] =
1283                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1284                         vnic->rss_table[i * 2 + 1] =
1285                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1286                 } else {
1287                         vnic->rss_table[i] =
1288                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1289                 }
1290
1291                 vnic->rss_table[i] =
1292                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1293         }
1294
1295         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1296         return 0;
1297 }
1298
1299 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1300                               struct rte_eth_rss_reta_entry64 *reta_conf,
1301                               uint16_t reta_size)
1302 {
1303         struct bnxt *bp = eth_dev->data->dev_private;
1304         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1305         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1306         uint16_t idx, sft, i;
1307         int rc;
1308
1309         rc = is_bnxt_in_error(bp);
1310         if (rc)
1311                 return rc;
1312
1313         /* Retrieve from the default VNIC */
1314         if (!vnic)
1315                 return -EINVAL;
1316         if (!vnic->rss_table)
1317                 return -EINVAL;
1318
1319         if (reta_size != tbl_size) {
1320                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1321                         "(%d) must equal the size supported by the hardware "
1322                         "(%d)\n", reta_size, tbl_size);
1323                 return -EINVAL;
1324         }
1325
1326         for (idx = 0, i = 0; i < reta_size; i++) {
1327                 idx = i / RTE_RETA_GROUP_SIZE;
1328                 sft = i % RTE_RETA_GROUP_SIZE;
1329
1330                 if (reta_conf[idx].mask & (1ULL << sft)) {
1331                         uint16_t qid;
1332
1333                         if (BNXT_CHIP_THOR(bp))
1334                                 qid = bnxt_rss_to_qid(bp,
1335                                                       vnic->rss_table[i * 2]);
1336                         else
1337                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1338
1339                         if (qid == INVALID_HW_RING_ID) {
1340                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1341                                 return -EINVAL;
1342                         }
1343                         reta_conf[idx].reta[sft] = qid;
1344                 }
1345         }
1346
1347         return 0;
1348 }
1349
1350 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1351                                    struct rte_eth_rss_conf *rss_conf)
1352 {
1353         struct bnxt *bp = eth_dev->data->dev_private;
1354         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1355         struct bnxt_vnic_info *vnic;
1356         uint16_t hash_type = 0;
1357         unsigned int i;
1358         int rc;
1359
1360         rc = is_bnxt_in_error(bp);
1361         if (rc)
1362                 return rc;
1363
1364         /*
1365          * If RSS enablement were different than dev_configure,
1366          * then return -EINVAL
1367          */
1368         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1369                 if (!rss_conf->rss_hf)
1370                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1371         } else {
1372                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1373                         return -EINVAL;
1374         }
1375
1376         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1377         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1378
1379         if (rss_conf->rss_hf & ETH_RSS_IPV4)
1380                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1381         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1382                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1383         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1384                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1385         if (rss_conf->rss_hf & ETH_RSS_IPV6)
1386                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1387         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1388                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1389         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1390                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1391
1392         /* Update the RSS VNIC(s) */
1393         for (i = 0; i < bp->nr_vnics; i++) {
1394                 vnic = &bp->vnic_info[i];
1395                 vnic->hash_type = hash_type;
1396
1397                 /*
1398                  * Use the supplied key if the key length is
1399                  * acceptable and the rss_key is not NULL
1400                  */
1401                 if (rss_conf->rss_key &&
1402                     rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1403                         memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1404                                rss_conf->rss_key_len);
1405
1406                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1407         }
1408         return 0;
1409 }
1410
1411 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1412                                      struct rte_eth_rss_conf *rss_conf)
1413 {
1414         struct bnxt *bp = eth_dev->data->dev_private;
1415         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1416         int len, rc;
1417         uint32_t hash_types;
1418
1419         rc = is_bnxt_in_error(bp);
1420         if (rc)
1421                 return rc;
1422
1423         /* RSS configuration is the same for all VNICs */
1424         if (vnic && vnic->rss_hash_key) {
1425                 if (rss_conf->rss_key) {
1426                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1427                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1428                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1429                 }
1430
1431                 hash_types = vnic->hash_type;
1432                 rss_conf->rss_hf = 0;
1433                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1434                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1435                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1436                 }
1437                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1438                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1439                         hash_types &=
1440                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1441                 }
1442                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1443                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1444                         hash_types &=
1445                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1446                 }
1447                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1448                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1449                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1450                 }
1451                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1452                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1453                         hash_types &=
1454                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1455                 }
1456                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1457                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1458                         hash_types &=
1459                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1460                 }
1461                 if (hash_types) {
1462                         PMD_DRV_LOG(ERR,
1463                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1464                                 vnic->hash_type);
1465                         return -ENOTSUP;
1466                 }
1467         } else {
1468                 rss_conf->rss_hf = 0;
1469         }
1470         return 0;
1471 }
1472
1473 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1474                                struct rte_eth_fc_conf *fc_conf)
1475 {
1476         struct bnxt *bp = dev->data->dev_private;
1477         struct rte_eth_link link_info;
1478         int rc;
1479
1480         rc = is_bnxt_in_error(bp);
1481         if (rc)
1482                 return rc;
1483
1484         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1485         if (rc)
1486                 return rc;
1487
1488         memset(fc_conf, 0, sizeof(*fc_conf));
1489         if (bp->link_info.auto_pause)
1490                 fc_conf->autoneg = 1;
1491         switch (bp->link_info.pause) {
1492         case 0:
1493                 fc_conf->mode = RTE_FC_NONE;
1494                 break;
1495         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1496                 fc_conf->mode = RTE_FC_TX_PAUSE;
1497                 break;
1498         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1499                 fc_conf->mode = RTE_FC_RX_PAUSE;
1500                 break;
1501         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1502                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1503                 fc_conf->mode = RTE_FC_FULL;
1504                 break;
1505         }
1506         return 0;
1507 }
1508
1509 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1510                                struct rte_eth_fc_conf *fc_conf)
1511 {
1512         struct bnxt *bp = dev->data->dev_private;
1513         int rc;
1514
1515         rc = is_bnxt_in_error(bp);
1516         if (rc)
1517                 return rc;
1518
1519         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1520                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1521                 return -ENOTSUP;
1522         }
1523
1524         switch (fc_conf->mode) {
1525         case RTE_FC_NONE:
1526                 bp->link_info.auto_pause = 0;
1527                 bp->link_info.force_pause = 0;
1528                 break;
1529         case RTE_FC_RX_PAUSE:
1530                 if (fc_conf->autoneg) {
1531                         bp->link_info.auto_pause =
1532                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1533                         bp->link_info.force_pause = 0;
1534                 } else {
1535                         bp->link_info.auto_pause = 0;
1536                         bp->link_info.force_pause =
1537                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1538                 }
1539                 break;
1540         case RTE_FC_TX_PAUSE:
1541                 if (fc_conf->autoneg) {
1542                         bp->link_info.auto_pause =
1543                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1544                         bp->link_info.force_pause = 0;
1545                 } else {
1546                         bp->link_info.auto_pause = 0;
1547                         bp->link_info.force_pause =
1548                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1549                 }
1550                 break;
1551         case RTE_FC_FULL:
1552                 if (fc_conf->autoneg) {
1553                         bp->link_info.auto_pause =
1554                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1555                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1556                         bp->link_info.force_pause = 0;
1557                 } else {
1558                         bp->link_info.auto_pause = 0;
1559                         bp->link_info.force_pause =
1560                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1561                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1562                 }
1563                 break;
1564         }
1565         return bnxt_set_hwrm_link_config(bp, true);
1566 }
1567
1568 /* Add UDP tunneling port */
1569 static int
1570 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1571                          struct rte_eth_udp_tunnel *udp_tunnel)
1572 {
1573         struct bnxt *bp = eth_dev->data->dev_private;
1574         uint16_t tunnel_type = 0;
1575         int rc = 0;
1576
1577         rc = is_bnxt_in_error(bp);
1578         if (rc)
1579                 return rc;
1580
1581         switch (udp_tunnel->prot_type) {
1582         case RTE_TUNNEL_TYPE_VXLAN:
1583                 if (bp->vxlan_port_cnt) {
1584                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1585                                 udp_tunnel->udp_port);
1586                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1587                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1588                                 return -ENOSPC;
1589                         }
1590                         bp->vxlan_port_cnt++;
1591                         return 0;
1592                 }
1593                 tunnel_type =
1594                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1595                 bp->vxlan_port_cnt++;
1596                 break;
1597         case RTE_TUNNEL_TYPE_GENEVE:
1598                 if (bp->geneve_port_cnt) {
1599                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1600                                 udp_tunnel->udp_port);
1601                         if (bp->geneve_port != udp_tunnel->udp_port) {
1602                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1603                                 return -ENOSPC;
1604                         }
1605                         bp->geneve_port_cnt++;
1606                         return 0;
1607                 }
1608                 tunnel_type =
1609                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1610                 bp->geneve_port_cnt++;
1611                 break;
1612         default:
1613                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1614                 return -ENOTSUP;
1615         }
1616         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1617                                              tunnel_type);
1618         return rc;
1619 }
1620
1621 static int
1622 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1623                          struct rte_eth_udp_tunnel *udp_tunnel)
1624 {
1625         struct bnxt *bp = eth_dev->data->dev_private;
1626         uint16_t tunnel_type = 0;
1627         uint16_t port = 0;
1628         int rc = 0;
1629
1630         rc = is_bnxt_in_error(bp);
1631         if (rc)
1632                 return rc;
1633
1634         switch (udp_tunnel->prot_type) {
1635         case RTE_TUNNEL_TYPE_VXLAN:
1636                 if (!bp->vxlan_port_cnt) {
1637                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1638                         return -EINVAL;
1639                 }
1640                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1641                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1642                                 udp_tunnel->udp_port, bp->vxlan_port);
1643                         return -EINVAL;
1644                 }
1645                 if (--bp->vxlan_port_cnt)
1646                         return 0;
1647
1648                 tunnel_type =
1649                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1650                 port = bp->vxlan_fw_dst_port_id;
1651                 break;
1652         case RTE_TUNNEL_TYPE_GENEVE:
1653                 if (!bp->geneve_port_cnt) {
1654                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1655                         return -EINVAL;
1656                 }
1657                 if (bp->geneve_port != udp_tunnel->udp_port) {
1658                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1659                                 udp_tunnel->udp_port, bp->geneve_port);
1660                         return -EINVAL;
1661                 }
1662                 if (--bp->geneve_port_cnt)
1663                         return 0;
1664
1665                 tunnel_type =
1666                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1667                 port = bp->geneve_fw_dst_port_id;
1668                 break;
1669         default:
1670                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1671                 return -ENOTSUP;
1672         }
1673
1674         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1675         if (!rc) {
1676                 if (tunnel_type ==
1677                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1678                         bp->vxlan_port = 0;
1679                 if (tunnel_type ==
1680                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1681                         bp->geneve_port = 0;
1682         }
1683         return rc;
1684 }
1685
1686 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1687 {
1688         struct bnxt_filter_info *filter;
1689         struct bnxt_vnic_info *vnic;
1690         int rc = 0;
1691         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1692
1693         /* if VLAN exists && VLAN matches vlan_id
1694          *      remove the MAC+VLAN filter
1695          *      add a new MAC only filter
1696          * else
1697          *      VLAN filter doesn't exist, just skip and continue
1698          */
1699         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1700         filter = STAILQ_FIRST(&vnic->filter);
1701         while (filter) {
1702                 /* Search for this matching MAC+VLAN filter */
1703                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1704                     !memcmp(filter->l2_addr,
1705                             bp->mac_addr,
1706                             RTE_ETHER_ADDR_LEN)) {
1707                         /* Delete the filter */
1708                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1709                         if (rc)
1710                                 return rc;
1711                         STAILQ_REMOVE(&vnic->filter, filter,
1712                                       bnxt_filter_info, next);
1713                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1714
1715                         PMD_DRV_LOG(INFO,
1716                                     "Del Vlan filter for %d\n",
1717                                     vlan_id);
1718                         return rc;
1719                 }
1720                 filter = STAILQ_NEXT(filter, next);
1721         }
1722         return -ENOENT;
1723 }
1724
1725 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1726 {
1727         struct bnxt_filter_info *filter;
1728         struct bnxt_vnic_info *vnic;
1729         int rc = 0;
1730         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1731                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1732         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1733
1734         /* Implementation notes on the use of VNIC in this command:
1735          *
1736          * By default, these filters belong to default vnic for the function.
1737          * Once these filters are set up, only destination VNIC can be modified.
1738          * If the destination VNIC is not specified in this command,
1739          * then the HWRM shall only create an l2 context id.
1740          */
1741
1742         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1743         filter = STAILQ_FIRST(&vnic->filter);
1744         /* Check if the VLAN has already been added */
1745         while (filter) {
1746                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1747                     !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1748                         return -EEXIST;
1749
1750                 filter = STAILQ_NEXT(filter, next);
1751         }
1752
1753         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1754          * command to create MAC+VLAN filter with the right flags, enables set.
1755          */
1756         filter = bnxt_alloc_filter(bp);
1757         if (!filter) {
1758                 PMD_DRV_LOG(ERR,
1759                             "MAC/VLAN filter alloc failed\n");
1760                 return -ENOMEM;
1761         }
1762         /* MAC + VLAN ID filter */
1763         filter->l2_ivlan = vlan_id;
1764         filter->l2_ivlan_mask = 0x0FFF;
1765         filter->enables |= en;
1766         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1767         if (rc) {
1768                 /* Free the newly allocated filter as we were
1769                  * not able to create the filter in hardware.
1770                  */
1771                 filter->fw_l2_filter_id = UINT64_MAX;
1772                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1773                 return rc;
1774         }
1775
1776         /* Add this new filter to the list */
1777         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1778         PMD_DRV_LOG(INFO,
1779                     "Added Vlan filter for %d\n", vlan_id);
1780         return rc;
1781 }
1782
1783 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1784                 uint16_t vlan_id, int on)
1785 {
1786         struct bnxt *bp = eth_dev->data->dev_private;
1787         int rc;
1788
1789         rc = is_bnxt_in_error(bp);
1790         if (rc)
1791                 return rc;
1792
1793         /* These operations apply to ALL existing MAC/VLAN filters */
1794         if (on)
1795                 return bnxt_add_vlan_filter(bp, vlan_id);
1796         else
1797                 return bnxt_del_vlan_filter(bp, vlan_id);
1798 }
1799
1800 static int
1801 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1802 {
1803         struct bnxt *bp = dev->data->dev_private;
1804         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1805         unsigned int i;
1806         int rc;
1807
1808         rc = is_bnxt_in_error(bp);
1809         if (rc)
1810                 return rc;
1811
1812         if (mask & ETH_VLAN_FILTER_MASK) {
1813                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1814                         /* Remove any VLAN filters programmed */
1815                         for (i = 0; i < 4095; i++)
1816                                 bnxt_del_vlan_filter(bp, i);
1817                 }
1818                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1819                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1820         }
1821
1822         if (mask & ETH_VLAN_STRIP_MASK) {
1823                 /* Enable or disable VLAN stripping */
1824                 for (i = 0; i < bp->nr_vnics; i++) {
1825                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1826                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1827                                 vnic->vlan_strip = true;
1828                         else
1829                                 vnic->vlan_strip = false;
1830                         bnxt_hwrm_vnic_cfg(bp, vnic);
1831                 }
1832                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1833                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1834         }
1835
1836         if (mask & ETH_VLAN_EXTEND_MASK) {
1837                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1838                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1839                 else
1840                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1841         }
1842
1843         return 0;
1844 }
1845
1846 static int
1847 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1848                       uint16_t tpid)
1849 {
1850         struct bnxt *bp = dev->data->dev_private;
1851         int qinq = dev->data->dev_conf.rxmode.offloads &
1852                    DEV_RX_OFFLOAD_VLAN_EXTEND;
1853
1854         if (vlan_type != ETH_VLAN_TYPE_INNER &&
1855             vlan_type != ETH_VLAN_TYPE_OUTER) {
1856                 PMD_DRV_LOG(ERR,
1857                             "Unsupported vlan type.");
1858                 return -EINVAL;
1859         }
1860         if (!qinq) {
1861                 PMD_DRV_LOG(ERR,
1862                             "QinQ not enabled. Needs to be ON as we can "
1863                             "accelerate only outer vlan\n");
1864                 return -EINVAL;
1865         }
1866
1867         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1868                 switch (tpid) {
1869                 case RTE_ETHER_TYPE_QINQ:
1870                         bp->outer_tpid_bd =
1871                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1872                                 break;
1873                 case RTE_ETHER_TYPE_VLAN:
1874                         bp->outer_tpid_bd =
1875                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1876                                 break;
1877                 case 0x9100:
1878                         bp->outer_tpid_bd =
1879                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1880                                 break;
1881                 case 0x9200:
1882                         bp->outer_tpid_bd =
1883                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1884                                 break;
1885                 case 0x9300:
1886                         bp->outer_tpid_bd =
1887                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1888                                 break;
1889                 default:
1890                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1891                         return -EINVAL;
1892                 }
1893                 bp->outer_tpid_bd |= tpid;
1894                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1895         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1896                 PMD_DRV_LOG(ERR,
1897                             "Can accelerate only outer vlan in QinQ\n");
1898                 return -EINVAL;
1899         }
1900
1901         return 0;
1902 }
1903
1904 static int
1905 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1906                              struct rte_ether_addr *addr)
1907 {
1908         struct bnxt *bp = dev->data->dev_private;
1909         /* Default Filter is tied to VNIC 0 */
1910         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1911         struct bnxt_filter_info *filter;
1912         int rc;
1913
1914         rc = is_bnxt_in_error(bp);
1915         if (rc)
1916                 return rc;
1917
1918         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1919                 return -EPERM;
1920
1921         if (rte_is_zero_ether_addr(addr))
1922                 return -EINVAL;
1923
1924         STAILQ_FOREACH(filter, &vnic->filter, next) {
1925                 /* Default Filter is at Index 0 */
1926                 if (filter->mac_index != 0)
1927                         continue;
1928
1929                 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1930                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1931                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1932                 filter->enables |=
1933                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1934                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1935
1936                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1937                 if (rc)
1938                         return rc;
1939
1940                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1941                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1942                 return 0;
1943         }
1944
1945         return 0;
1946 }
1947
1948 static int
1949 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1950                           struct rte_ether_addr *mc_addr_set,
1951                           uint32_t nb_mc_addr)
1952 {
1953         struct bnxt *bp = eth_dev->data->dev_private;
1954         char *mc_addr_list = (char *)mc_addr_set;
1955         struct bnxt_vnic_info *vnic;
1956         uint32_t off = 0, i = 0;
1957         int rc;
1958
1959         rc = is_bnxt_in_error(bp);
1960         if (rc)
1961                 return rc;
1962
1963         vnic = &bp->vnic_info[0];
1964
1965         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1966                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1967                 goto allmulti;
1968         }
1969
1970         /* TODO Check for Duplicate mcast addresses */
1971         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1972         for (i = 0; i < nb_mc_addr; i++) {
1973                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1974                         RTE_ETHER_ADDR_LEN);
1975                 off += RTE_ETHER_ADDR_LEN;
1976         }
1977
1978         vnic->mc_addr_cnt = i;
1979
1980 allmulti:
1981         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1982 }
1983
1984 static int
1985 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1986 {
1987         struct bnxt *bp = dev->data->dev_private;
1988         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1989         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1990         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1991         int ret;
1992
1993         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1994                         fw_major, fw_minor, fw_updt);
1995
1996         ret += 1; /* add the size of '\0' */
1997         if (fw_size < (uint32_t)ret)
1998                 return ret;
1999         else
2000                 return 0;
2001 }
2002
2003 static void
2004 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2005         struct rte_eth_rxq_info *qinfo)
2006 {
2007         struct bnxt_rx_queue *rxq;
2008
2009         rxq = dev->data->rx_queues[queue_id];
2010
2011         qinfo->mp = rxq->mb_pool;
2012         qinfo->scattered_rx = dev->data->scattered_rx;
2013         qinfo->nb_desc = rxq->nb_rx_desc;
2014
2015         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2016         qinfo->conf.rx_drop_en = 0;
2017         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2018 }
2019
2020 static void
2021 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2022         struct rte_eth_txq_info *qinfo)
2023 {
2024         struct bnxt_tx_queue *txq;
2025
2026         txq = dev->data->tx_queues[queue_id];
2027
2028         qinfo->nb_desc = txq->nb_tx_desc;
2029
2030         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2031         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2032         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2033
2034         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2035         qinfo->conf.tx_rs_thresh = 0;
2036         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2037 }
2038
2039 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2040 {
2041         struct bnxt *bp = eth_dev->data->dev_private;
2042         uint32_t new_pkt_size;
2043         uint32_t rc = 0;
2044         uint32_t i;
2045
2046         rc = is_bnxt_in_error(bp);
2047         if (rc)
2048                 return rc;
2049
2050         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2051                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2052
2053 #ifdef RTE_ARCH_X86
2054         /*
2055          * If vector-mode tx/rx is active, disallow any MTU change that would
2056          * require scattered receive support.
2057          */
2058         if (eth_dev->data->dev_started &&
2059             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2060              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2061             (new_pkt_size >
2062              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2063                 PMD_DRV_LOG(ERR,
2064                             "MTU change would require scattered rx support. ");
2065                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2066                 return -EINVAL;
2067         }
2068 #endif
2069
2070         if (new_mtu > RTE_ETHER_MTU) {
2071                 bp->flags |= BNXT_FLAG_JUMBO;
2072                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2073                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2074         } else {
2075                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2076                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2077                 bp->flags &= ~BNXT_FLAG_JUMBO;
2078         }
2079
2080         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2081
2082         for (i = 0; i < bp->nr_vnics; i++) {
2083                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2084                 uint16_t size = 0;
2085
2086                 vnic->mru = new_mtu + RTE_ETHER_HDR_LEN +
2087                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2088                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2089                 if (rc)
2090                         break;
2091
2092                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2093                 size -= RTE_PKTMBUF_HEADROOM;
2094
2095                 if (size < new_mtu) {
2096                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2097                         if (rc)
2098                                 return rc;
2099                 }
2100         }
2101
2102         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2103
2104         return rc;
2105 }
2106
2107 static int
2108 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2109 {
2110         struct bnxt *bp = dev->data->dev_private;
2111         uint16_t vlan = bp->vlan;
2112         int rc;
2113
2114         rc = is_bnxt_in_error(bp);
2115         if (rc)
2116                 return rc;
2117
2118         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2119                 PMD_DRV_LOG(ERR,
2120                         "PVID cannot be modified for this function\n");
2121                 return -ENOTSUP;
2122         }
2123         bp->vlan = on ? pvid : 0;
2124
2125         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2126         if (rc)
2127                 bp->vlan = vlan;
2128         return rc;
2129 }
2130
2131 static int
2132 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2133 {
2134         struct bnxt *bp = dev->data->dev_private;
2135         int rc;
2136
2137         rc = is_bnxt_in_error(bp);
2138         if (rc)
2139                 return rc;
2140
2141         return bnxt_hwrm_port_led_cfg(bp, true);
2142 }
2143
2144 static int
2145 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2146 {
2147         struct bnxt *bp = dev->data->dev_private;
2148         int rc;
2149
2150         rc = is_bnxt_in_error(bp);
2151         if (rc)
2152                 return rc;
2153
2154         return bnxt_hwrm_port_led_cfg(bp, false);
2155 }
2156
2157 static uint32_t
2158 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2159 {
2160         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2161         uint32_t desc = 0, raw_cons = 0, cons;
2162         struct bnxt_cp_ring_info *cpr;
2163         struct bnxt_rx_queue *rxq;
2164         struct rx_pkt_cmpl *rxcmp;
2165         int rc;
2166
2167         rc = is_bnxt_in_error(bp);
2168         if (rc)
2169                 return rc;
2170
2171         rxq = dev->data->rx_queues[rx_queue_id];
2172         cpr = rxq->cp_ring;
2173         raw_cons = cpr->cp_raw_cons;
2174
2175         while (1) {
2176                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2177                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2178                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2179
2180                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2181                         break;
2182                 } else {
2183                         raw_cons++;
2184                         desc++;
2185                 }
2186         }
2187
2188         return desc;
2189 }
2190
2191 static int
2192 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2193 {
2194         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2195         struct bnxt_rx_ring_info *rxr;
2196         struct bnxt_cp_ring_info *cpr;
2197         struct bnxt_sw_rx_bd *rx_buf;
2198         struct rx_pkt_cmpl *rxcmp;
2199         uint32_t cons, cp_cons;
2200         int rc;
2201
2202         if (!rxq)
2203                 return -EINVAL;
2204
2205         rc = is_bnxt_in_error(rxq->bp);
2206         if (rc)
2207                 return rc;
2208
2209         cpr = rxq->cp_ring;
2210         rxr = rxq->rx_ring;
2211
2212         if (offset >= rxq->nb_rx_desc)
2213                 return -EINVAL;
2214
2215         cons = RING_CMP(cpr->cp_ring_struct, offset);
2216         cp_cons = cpr->cp_raw_cons;
2217         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2218
2219         if (cons > cp_cons) {
2220                 if (CMPL_VALID(rxcmp, cpr->valid))
2221                         return RTE_ETH_RX_DESC_DONE;
2222         } else {
2223                 if (CMPL_VALID(rxcmp, !cpr->valid))
2224                         return RTE_ETH_RX_DESC_DONE;
2225         }
2226         rx_buf = &rxr->rx_buf_ring[cons];
2227         if (rx_buf->mbuf == NULL)
2228                 return RTE_ETH_RX_DESC_UNAVAIL;
2229
2230
2231         return RTE_ETH_RX_DESC_AVAIL;
2232 }
2233
2234 static int
2235 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2236 {
2237         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2238         struct bnxt_tx_ring_info *txr;
2239         struct bnxt_cp_ring_info *cpr;
2240         struct bnxt_sw_tx_bd *tx_buf;
2241         struct tx_pkt_cmpl *txcmp;
2242         uint32_t cons, cp_cons;
2243         int rc;
2244
2245         if (!txq)
2246                 return -EINVAL;
2247
2248         rc = is_bnxt_in_error(txq->bp);
2249         if (rc)
2250                 return rc;
2251
2252         cpr = txq->cp_ring;
2253         txr = txq->tx_ring;
2254
2255         if (offset >= txq->nb_tx_desc)
2256                 return -EINVAL;
2257
2258         cons = RING_CMP(cpr->cp_ring_struct, offset);
2259         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2260         cp_cons = cpr->cp_raw_cons;
2261
2262         if (cons > cp_cons) {
2263                 if (CMPL_VALID(txcmp, cpr->valid))
2264                         return RTE_ETH_TX_DESC_UNAVAIL;
2265         } else {
2266                 if (CMPL_VALID(txcmp, !cpr->valid))
2267                         return RTE_ETH_TX_DESC_UNAVAIL;
2268         }
2269         tx_buf = &txr->tx_buf_ring[cons];
2270         if (tx_buf->mbuf == NULL)
2271                 return RTE_ETH_TX_DESC_DONE;
2272
2273         return RTE_ETH_TX_DESC_FULL;
2274 }
2275
2276 static struct bnxt_filter_info *
2277 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2278                                 struct rte_eth_ethertype_filter *efilter,
2279                                 struct bnxt_vnic_info *vnic0,
2280                                 struct bnxt_vnic_info *vnic,
2281                                 int *ret)
2282 {
2283         struct bnxt_filter_info *mfilter = NULL;
2284         int match = 0;
2285         *ret = 0;
2286
2287         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2288                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2289                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2290                         " ethertype filter.", efilter->ether_type);
2291                 *ret = -EINVAL;
2292                 goto exit;
2293         }
2294         if (efilter->queue >= bp->rx_nr_rings) {
2295                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2296                 *ret = -EINVAL;
2297                 goto exit;
2298         }
2299
2300         vnic0 = &bp->vnic_info[0];
2301         vnic = &bp->vnic_info[efilter->queue];
2302         if (vnic == NULL) {
2303                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2304                 *ret = -EINVAL;
2305                 goto exit;
2306         }
2307
2308         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2309                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2310                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2311                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2312                              mfilter->flags ==
2313                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2314                              mfilter->ethertype == efilter->ether_type)) {
2315                                 match = 1;
2316                                 break;
2317                         }
2318                 }
2319         } else {
2320                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2321                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2322                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2323                              mfilter->ethertype == efilter->ether_type &&
2324                              mfilter->flags ==
2325                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2326                                 match = 1;
2327                                 break;
2328                         }
2329         }
2330
2331         if (match)
2332                 *ret = -EEXIST;
2333
2334 exit:
2335         return mfilter;
2336 }
2337
2338 static int
2339 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2340                         enum rte_filter_op filter_op,
2341                         void *arg)
2342 {
2343         struct bnxt *bp = dev->data->dev_private;
2344         struct rte_eth_ethertype_filter *efilter =
2345                         (struct rte_eth_ethertype_filter *)arg;
2346         struct bnxt_filter_info *bfilter, *filter1;
2347         struct bnxt_vnic_info *vnic, *vnic0;
2348         int ret;
2349
2350         if (filter_op == RTE_ETH_FILTER_NOP)
2351                 return 0;
2352
2353         if (arg == NULL) {
2354                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2355                             filter_op);
2356                 return -EINVAL;
2357         }
2358
2359         vnic0 = &bp->vnic_info[0];
2360         vnic = &bp->vnic_info[efilter->queue];
2361
2362         switch (filter_op) {
2363         case RTE_ETH_FILTER_ADD:
2364                 bnxt_match_and_validate_ether_filter(bp, efilter,
2365                                                         vnic0, vnic, &ret);
2366                 if (ret < 0)
2367                         return ret;
2368
2369                 bfilter = bnxt_get_unused_filter(bp);
2370                 if (bfilter == NULL) {
2371                         PMD_DRV_LOG(ERR,
2372                                 "Not enough resources for a new filter.\n");
2373                         return -ENOMEM;
2374                 }
2375                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2376                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2377                        RTE_ETHER_ADDR_LEN);
2378                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2379                        RTE_ETHER_ADDR_LEN);
2380                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2381                 bfilter->ethertype = efilter->ether_type;
2382                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2383
2384                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2385                 if (filter1 == NULL) {
2386                         ret = -EINVAL;
2387                         goto cleanup;
2388                 }
2389                 bfilter->enables |=
2390                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2391                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2392
2393                 bfilter->dst_id = vnic->fw_vnic_id;
2394
2395                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2396                         bfilter->flags =
2397                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2398                 }
2399
2400                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2401                 if (ret)
2402                         goto cleanup;
2403                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2404                 break;
2405         case RTE_ETH_FILTER_DELETE:
2406                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2407                                                         vnic0, vnic, &ret);
2408                 if (ret == -EEXIST) {
2409                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2410
2411                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2412                                       next);
2413                         bnxt_free_filter(bp, filter1);
2414                 } else if (ret == 0) {
2415                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2416                 }
2417                 break;
2418         default:
2419                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2420                 ret = -EINVAL;
2421                 goto error;
2422         }
2423         return ret;
2424 cleanup:
2425         bnxt_free_filter(bp, bfilter);
2426 error:
2427         return ret;
2428 }
2429
2430 static inline int
2431 parse_ntuple_filter(struct bnxt *bp,
2432                     struct rte_eth_ntuple_filter *nfilter,
2433                     struct bnxt_filter_info *bfilter)
2434 {
2435         uint32_t en = 0;
2436
2437         if (nfilter->queue >= bp->rx_nr_rings) {
2438                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2439                 return -EINVAL;
2440         }
2441
2442         switch (nfilter->dst_port_mask) {
2443         case UINT16_MAX:
2444                 bfilter->dst_port_mask = -1;
2445                 bfilter->dst_port = nfilter->dst_port;
2446                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2447                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2448                 break;
2449         default:
2450                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2451                 return -EINVAL;
2452         }
2453
2454         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2455         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2456
2457         switch (nfilter->proto_mask) {
2458         case UINT8_MAX:
2459                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2460                         bfilter->ip_protocol = 17;
2461                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2462                         bfilter->ip_protocol = 6;
2463                 else
2464                         return -EINVAL;
2465                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2466                 break;
2467         default:
2468                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2469                 return -EINVAL;
2470         }
2471
2472         switch (nfilter->dst_ip_mask) {
2473         case UINT32_MAX:
2474                 bfilter->dst_ipaddr_mask[0] = -1;
2475                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2476                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2477                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2478                 break;
2479         default:
2480                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2481                 return -EINVAL;
2482         }
2483
2484         switch (nfilter->src_ip_mask) {
2485         case UINT32_MAX:
2486                 bfilter->src_ipaddr_mask[0] = -1;
2487                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2488                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2489                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2490                 break;
2491         default:
2492                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2493                 return -EINVAL;
2494         }
2495
2496         switch (nfilter->src_port_mask) {
2497         case UINT16_MAX:
2498                 bfilter->src_port_mask = -1;
2499                 bfilter->src_port = nfilter->src_port;
2500                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2501                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2502                 break;
2503         default:
2504                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2505                 return -EINVAL;
2506         }
2507
2508         //TODO Priority
2509         //nfilter->priority = (uint8_t)filter->priority;
2510
2511         bfilter->enables = en;
2512         return 0;
2513 }
2514
2515 static struct bnxt_filter_info*
2516 bnxt_match_ntuple_filter(struct bnxt *bp,
2517                          struct bnxt_filter_info *bfilter,
2518                          struct bnxt_vnic_info **mvnic)
2519 {
2520         struct bnxt_filter_info *mfilter = NULL;
2521         int i;
2522
2523         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2524                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2525                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2526                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2527                             bfilter->src_ipaddr_mask[0] ==
2528                             mfilter->src_ipaddr_mask[0] &&
2529                             bfilter->src_port == mfilter->src_port &&
2530                             bfilter->src_port_mask == mfilter->src_port_mask &&
2531                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2532                             bfilter->dst_ipaddr_mask[0] ==
2533                             mfilter->dst_ipaddr_mask[0] &&
2534                             bfilter->dst_port == mfilter->dst_port &&
2535                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2536                             bfilter->flags == mfilter->flags &&
2537                             bfilter->enables == mfilter->enables) {
2538                                 if (mvnic)
2539                                         *mvnic = vnic;
2540                                 return mfilter;
2541                         }
2542                 }
2543         }
2544         return NULL;
2545 }
2546
2547 static int
2548 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2549                        struct rte_eth_ntuple_filter *nfilter,
2550                        enum rte_filter_op filter_op)
2551 {
2552         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2553         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2554         int ret;
2555
2556         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2557                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2558                 return -EINVAL;
2559         }
2560
2561         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2562                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2563                 return -EINVAL;
2564         }
2565
2566         bfilter = bnxt_get_unused_filter(bp);
2567         if (bfilter == NULL) {
2568                 PMD_DRV_LOG(ERR,
2569                         "Not enough resources for a new filter.\n");
2570                 return -ENOMEM;
2571         }
2572         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2573         if (ret < 0)
2574                 goto free_filter;
2575
2576         vnic = &bp->vnic_info[nfilter->queue];
2577         vnic0 = &bp->vnic_info[0];
2578         filter1 = STAILQ_FIRST(&vnic0->filter);
2579         if (filter1 == NULL) {
2580                 ret = -EINVAL;
2581                 goto free_filter;
2582         }
2583
2584         bfilter->dst_id = vnic->fw_vnic_id;
2585         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2586         bfilter->enables |=
2587                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2588         bfilter->ethertype = 0x800;
2589         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2590
2591         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2592
2593         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2594             bfilter->dst_id == mfilter->dst_id) {
2595                 PMD_DRV_LOG(ERR, "filter exists.\n");
2596                 ret = -EEXIST;
2597                 goto free_filter;
2598         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2599                    bfilter->dst_id != mfilter->dst_id) {
2600                 mfilter->dst_id = vnic->fw_vnic_id;
2601                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2602                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2603                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2604                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2605                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2606                 goto free_filter;
2607         }
2608         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2609                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2610                 ret = -ENOENT;
2611                 goto free_filter;
2612         }
2613
2614         if (filter_op == RTE_ETH_FILTER_ADD) {
2615                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2616                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2617                 if (ret)
2618                         goto free_filter;
2619                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2620         } else {
2621                 if (mfilter == NULL) {
2622                         /* This should not happen. But for Coverity! */
2623                         ret = -ENOENT;
2624                         goto free_filter;
2625                 }
2626                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2627
2628                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2629                 bnxt_free_filter(bp, mfilter);
2630                 mfilter->fw_l2_filter_id = -1;
2631                 bnxt_free_filter(bp, bfilter);
2632                 bfilter->fw_l2_filter_id = -1;
2633         }
2634
2635         return 0;
2636 free_filter:
2637         bfilter->fw_l2_filter_id = -1;
2638         bnxt_free_filter(bp, bfilter);
2639         return ret;
2640 }
2641
2642 static int
2643 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2644                         enum rte_filter_op filter_op,
2645                         void *arg)
2646 {
2647         struct bnxt *bp = dev->data->dev_private;
2648         int ret;
2649
2650         if (filter_op == RTE_ETH_FILTER_NOP)
2651                 return 0;
2652
2653         if (arg == NULL) {
2654                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2655                             filter_op);
2656                 return -EINVAL;
2657         }
2658
2659         switch (filter_op) {
2660         case RTE_ETH_FILTER_ADD:
2661                 ret = bnxt_cfg_ntuple_filter(bp,
2662                         (struct rte_eth_ntuple_filter *)arg,
2663                         filter_op);
2664                 break;
2665         case RTE_ETH_FILTER_DELETE:
2666                 ret = bnxt_cfg_ntuple_filter(bp,
2667                         (struct rte_eth_ntuple_filter *)arg,
2668                         filter_op);
2669                 break;
2670         default:
2671                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2672                 ret = -EINVAL;
2673                 break;
2674         }
2675         return ret;
2676 }
2677
2678 static int
2679 bnxt_parse_fdir_filter(struct bnxt *bp,
2680                        struct rte_eth_fdir_filter *fdir,
2681                        struct bnxt_filter_info *filter)
2682 {
2683         enum rte_fdir_mode fdir_mode =
2684                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2685         struct bnxt_vnic_info *vnic0, *vnic;
2686         struct bnxt_filter_info *filter1;
2687         uint32_t en = 0;
2688         int i;
2689
2690         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2691                 return -EINVAL;
2692
2693         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2694         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2695
2696         switch (fdir->input.flow_type) {
2697         case RTE_ETH_FLOW_IPV4:
2698         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2699                 /* FALLTHROUGH */
2700                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2701                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2702                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2703                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2704                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2705                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2706                 filter->ip_addr_type =
2707                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2708                 filter->src_ipaddr_mask[0] = 0xffffffff;
2709                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2710                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2711                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2712                 filter->ethertype = 0x800;
2713                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2714                 break;
2715         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2716                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2717                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2718                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2719                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2720                 filter->dst_port_mask = 0xffff;
2721                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2722                 filter->src_port_mask = 0xffff;
2723                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2724                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2725                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2726                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2727                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2728                 filter->ip_protocol = 6;
2729                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2730                 filter->ip_addr_type =
2731                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2732                 filter->src_ipaddr_mask[0] = 0xffffffff;
2733                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2734                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2735                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2736                 filter->ethertype = 0x800;
2737                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2738                 break;
2739         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2740                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2741                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2742                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2743                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2744                 filter->dst_port_mask = 0xffff;
2745                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2746                 filter->src_port_mask = 0xffff;
2747                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2748                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2749                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2750                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2751                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2752                 filter->ip_protocol = 17;
2753                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2754                 filter->ip_addr_type =
2755                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2756                 filter->src_ipaddr_mask[0] = 0xffffffff;
2757                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2758                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2759                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2760                 filter->ethertype = 0x800;
2761                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2762                 break;
2763         case RTE_ETH_FLOW_IPV6:
2764         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2765                 /* FALLTHROUGH */
2766                 filter->ip_addr_type =
2767                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2768                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2769                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2770                 rte_memcpy(filter->src_ipaddr,
2771                            fdir->input.flow.ipv6_flow.src_ip, 16);
2772                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2773                 rte_memcpy(filter->dst_ipaddr,
2774                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2775                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2776                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2777                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2778                 memset(filter->src_ipaddr_mask, 0xff, 16);
2779                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2780                 filter->ethertype = 0x86dd;
2781                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2782                 break;
2783         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2784                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2785                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2786                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2787                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2788                 filter->dst_port_mask = 0xffff;
2789                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2790                 filter->src_port_mask = 0xffff;
2791                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2792                 filter->ip_addr_type =
2793                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2794                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2795                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2796                 rte_memcpy(filter->src_ipaddr,
2797                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2798                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2799                 rte_memcpy(filter->dst_ipaddr,
2800                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2801                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2802                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2803                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2804                 memset(filter->src_ipaddr_mask, 0xff, 16);
2805                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2806                 filter->ethertype = 0x86dd;
2807                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2808                 break;
2809         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2810                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2811                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2812                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2813                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2814                 filter->dst_port_mask = 0xffff;
2815                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2816                 filter->src_port_mask = 0xffff;
2817                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2818                 filter->ip_addr_type =
2819                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2820                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2821                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2822                 rte_memcpy(filter->src_ipaddr,
2823                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2824                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2825                 rte_memcpy(filter->dst_ipaddr,
2826                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2827                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2828                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2829                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2830                 memset(filter->src_ipaddr_mask, 0xff, 16);
2831                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2832                 filter->ethertype = 0x86dd;
2833                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2834                 break;
2835         case RTE_ETH_FLOW_L2_PAYLOAD:
2836                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2837                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2838                 break;
2839         case RTE_ETH_FLOW_VXLAN:
2840                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2841                         return -EINVAL;
2842                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2843                 filter->tunnel_type =
2844                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2845                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2846                 break;
2847         case RTE_ETH_FLOW_NVGRE:
2848                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2849                         return -EINVAL;
2850                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2851                 filter->tunnel_type =
2852                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2853                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2854                 break;
2855         case RTE_ETH_FLOW_UNKNOWN:
2856         case RTE_ETH_FLOW_RAW:
2857         case RTE_ETH_FLOW_FRAG_IPV4:
2858         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2859         case RTE_ETH_FLOW_FRAG_IPV6:
2860         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2861         case RTE_ETH_FLOW_IPV6_EX:
2862         case RTE_ETH_FLOW_IPV6_TCP_EX:
2863         case RTE_ETH_FLOW_IPV6_UDP_EX:
2864         case RTE_ETH_FLOW_GENEVE:
2865                 /* FALLTHROUGH */
2866         default:
2867                 return -EINVAL;
2868         }
2869
2870         vnic0 = &bp->vnic_info[0];
2871         vnic = &bp->vnic_info[fdir->action.rx_queue];
2872         if (vnic == NULL) {
2873                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2874                 return -EINVAL;
2875         }
2876
2877
2878         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2879                 rte_memcpy(filter->dst_macaddr,
2880                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2881                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2882         }
2883
2884         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2885                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2886                 filter1 = STAILQ_FIRST(&vnic0->filter);
2887                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2888         } else {
2889                 filter->dst_id = vnic->fw_vnic_id;
2890                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2891                         if (filter->dst_macaddr[i] == 0x00)
2892                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2893                         else
2894                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2895         }
2896
2897         if (filter1 == NULL)
2898                 return -EINVAL;
2899
2900         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2901         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2902
2903         filter->enables = en;
2904
2905         return 0;
2906 }
2907
2908 static struct bnxt_filter_info *
2909 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2910                 struct bnxt_vnic_info **mvnic)
2911 {
2912         struct bnxt_filter_info *mf = NULL;
2913         int i;
2914
2915         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2916                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2917
2918                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2919                         if (mf->filter_type == nf->filter_type &&
2920                             mf->flags == nf->flags &&
2921                             mf->src_port == nf->src_port &&
2922                             mf->src_port_mask == nf->src_port_mask &&
2923                             mf->dst_port == nf->dst_port &&
2924                             mf->dst_port_mask == nf->dst_port_mask &&
2925                             mf->ip_protocol == nf->ip_protocol &&
2926                             mf->ip_addr_type == nf->ip_addr_type &&
2927                             mf->ethertype == nf->ethertype &&
2928                             mf->vni == nf->vni &&
2929                             mf->tunnel_type == nf->tunnel_type &&
2930                             mf->l2_ovlan == nf->l2_ovlan &&
2931                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2932                             mf->l2_ivlan == nf->l2_ivlan &&
2933                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2934                             !memcmp(mf->l2_addr, nf->l2_addr,
2935                                     RTE_ETHER_ADDR_LEN) &&
2936                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2937                                     RTE_ETHER_ADDR_LEN) &&
2938                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2939                                     RTE_ETHER_ADDR_LEN) &&
2940                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2941                                     RTE_ETHER_ADDR_LEN) &&
2942                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2943                                     sizeof(nf->src_ipaddr)) &&
2944                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2945                                     sizeof(nf->src_ipaddr_mask)) &&
2946                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2947                                     sizeof(nf->dst_ipaddr)) &&
2948                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2949                                     sizeof(nf->dst_ipaddr_mask))) {
2950                                 if (mvnic)
2951                                         *mvnic = vnic;
2952                                 return mf;
2953                         }
2954                 }
2955         }
2956         return NULL;
2957 }
2958
2959 static int
2960 bnxt_fdir_filter(struct rte_eth_dev *dev,
2961                  enum rte_filter_op filter_op,
2962                  void *arg)
2963 {
2964         struct bnxt *bp = dev->data->dev_private;
2965         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2966         struct bnxt_filter_info *filter, *match;
2967         struct bnxt_vnic_info *vnic, *mvnic;
2968         int ret = 0, i;
2969
2970         if (filter_op == RTE_ETH_FILTER_NOP)
2971                 return 0;
2972
2973         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2974                 return -EINVAL;
2975
2976         switch (filter_op) {
2977         case RTE_ETH_FILTER_ADD:
2978         case RTE_ETH_FILTER_DELETE:
2979                 /* FALLTHROUGH */
2980                 filter = bnxt_get_unused_filter(bp);
2981                 if (filter == NULL) {
2982                         PMD_DRV_LOG(ERR,
2983                                 "Not enough resources for a new flow.\n");
2984                         return -ENOMEM;
2985                 }
2986
2987                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2988                 if (ret != 0)
2989                         goto free_filter;
2990                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2991
2992                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2993                         vnic = &bp->vnic_info[0];
2994                 else
2995                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2996
2997                 match = bnxt_match_fdir(bp, filter, &mvnic);
2998                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2999                         if (match->dst_id == vnic->fw_vnic_id) {
3000                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3001                                 ret = -EEXIST;
3002                                 goto free_filter;
3003                         } else {
3004                                 match->dst_id = vnic->fw_vnic_id;
3005                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3006                                                                   match->dst_id,
3007                                                                   match);
3008                                 STAILQ_REMOVE(&mvnic->filter, match,
3009                                               bnxt_filter_info, next);
3010                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3011                                 PMD_DRV_LOG(ERR,
3012                                         "Filter with matching pattern exist\n");
3013                                 PMD_DRV_LOG(ERR,
3014                                         "Updated it to new destination q\n");
3015                                 goto free_filter;
3016                         }
3017                 }
3018                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3019                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3020                         ret = -ENOENT;
3021                         goto free_filter;
3022                 }
3023
3024                 if (filter_op == RTE_ETH_FILTER_ADD) {
3025                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3026                                                           filter->dst_id,
3027                                                           filter);
3028                         if (ret)
3029                                 goto free_filter;
3030                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3031                 } else {
3032                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3033                         STAILQ_REMOVE(&vnic->filter, match,
3034                                       bnxt_filter_info, next);
3035                         bnxt_free_filter(bp, match);
3036                         filter->fw_l2_filter_id = -1;
3037                         bnxt_free_filter(bp, filter);
3038                 }
3039                 break;
3040         case RTE_ETH_FILTER_FLUSH:
3041                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3042                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3043
3044                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3045                                 if (filter->filter_type ==
3046                                     HWRM_CFA_NTUPLE_FILTER) {
3047                                         ret =
3048                                         bnxt_hwrm_clear_ntuple_filter(bp,
3049                                                                       filter);
3050                                         STAILQ_REMOVE(&vnic->filter, filter,
3051                                                       bnxt_filter_info, next);
3052                                 }
3053                         }
3054                 }
3055                 return ret;
3056         case RTE_ETH_FILTER_UPDATE:
3057         case RTE_ETH_FILTER_STATS:
3058         case RTE_ETH_FILTER_INFO:
3059                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3060                 break;
3061         default:
3062                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3063                 ret = -EINVAL;
3064                 break;
3065         }
3066         return ret;
3067
3068 free_filter:
3069         filter->fw_l2_filter_id = -1;
3070         bnxt_free_filter(bp, filter);
3071         return ret;
3072 }
3073
3074 static int
3075 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3076                     enum rte_filter_type filter_type,
3077                     enum rte_filter_op filter_op, void *arg)
3078 {
3079         int ret = 0;
3080
3081         ret = is_bnxt_in_error(dev->data->dev_private);
3082         if (ret)
3083                 return ret;
3084
3085         switch (filter_type) {
3086         case RTE_ETH_FILTER_TUNNEL:
3087                 PMD_DRV_LOG(ERR,
3088                         "filter type: %d: To be implemented\n", filter_type);
3089                 break;
3090         case RTE_ETH_FILTER_FDIR:
3091                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3092                 break;
3093         case RTE_ETH_FILTER_NTUPLE:
3094                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3095                 break;
3096         case RTE_ETH_FILTER_ETHERTYPE:
3097                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3098                 break;
3099         case RTE_ETH_FILTER_GENERIC:
3100                 if (filter_op != RTE_ETH_FILTER_GET)
3101                         return -EINVAL;
3102                 *(const void **)arg = &bnxt_flow_ops;
3103                 break;
3104         default:
3105                 PMD_DRV_LOG(ERR,
3106                         "Filter type (%d) not supported", filter_type);
3107                 ret = -EINVAL;
3108                 break;
3109         }
3110         return ret;
3111 }
3112
3113 static const uint32_t *
3114 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3115 {
3116         static const uint32_t ptypes[] = {
3117                 RTE_PTYPE_L2_ETHER_VLAN,
3118                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3119                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3120                 RTE_PTYPE_L4_ICMP,
3121                 RTE_PTYPE_L4_TCP,
3122                 RTE_PTYPE_L4_UDP,
3123                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3124                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3125                 RTE_PTYPE_INNER_L4_ICMP,
3126                 RTE_PTYPE_INNER_L4_TCP,
3127                 RTE_PTYPE_INNER_L4_UDP,
3128                 RTE_PTYPE_UNKNOWN
3129         };
3130
3131         if (!dev->rx_pkt_burst)
3132                 return NULL;
3133
3134         return ptypes;
3135 }
3136
3137 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3138                          int reg_win)
3139 {
3140         uint32_t reg_base = *reg_arr & 0xfffff000;
3141         uint32_t win_off;
3142         int i;
3143
3144         for (i = 0; i < count; i++) {
3145                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3146                         return -ERANGE;
3147         }
3148         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3149         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3150         return 0;
3151 }
3152
3153 static int bnxt_map_ptp_regs(struct bnxt *bp)
3154 {
3155         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3156         uint32_t *reg_arr;
3157         int rc, i;
3158
3159         reg_arr = ptp->rx_regs;
3160         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3161         if (rc)
3162                 return rc;
3163
3164         reg_arr = ptp->tx_regs;
3165         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3166         if (rc)
3167                 return rc;
3168
3169         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3170                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3171
3172         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3173                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3174
3175         return 0;
3176 }
3177
3178 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3179 {
3180         rte_write32(0, (uint8_t *)bp->bar0 +
3181                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3182         rte_write32(0, (uint8_t *)bp->bar0 +
3183                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3184 }
3185
3186 static uint64_t bnxt_cc_read(struct bnxt *bp)
3187 {
3188         uint64_t ns;
3189
3190         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3191                               BNXT_GRCPF_REG_SYNC_TIME));
3192         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3193                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3194         return ns;
3195 }
3196
3197 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3198 {
3199         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3200         uint32_t fifo;
3201
3202         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3203                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3204         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3205                 return -EAGAIN;
3206
3207         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3208                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3209         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3210                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3211         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3212                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3213
3214         return 0;
3215 }
3216
3217 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3218 {
3219         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3220         struct bnxt_pf_info *pf = &bp->pf;
3221         uint16_t port_id;
3222         uint32_t fifo;
3223
3224         if (!ptp)
3225                 return -ENODEV;
3226
3227         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3228                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3229         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3230                 return -EAGAIN;
3231
3232         port_id = pf->port_id;
3233         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3234                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3235
3236         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3237                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3238         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3239 /*              bnxt_clr_rx_ts(bp);       TBD  */
3240                 return -EBUSY;
3241         }
3242
3243         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3244                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3245         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3246                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3247
3248         return 0;
3249 }
3250
3251 static int
3252 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3253 {
3254         uint64_t ns;
3255         struct bnxt *bp = dev->data->dev_private;
3256         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3257
3258         if (!ptp)
3259                 return 0;
3260
3261         ns = rte_timespec_to_ns(ts);
3262         /* Set the timecounters to a new value. */
3263         ptp->tc.nsec = ns;
3264
3265         return 0;
3266 }
3267
3268 static int
3269 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3270 {
3271         struct bnxt *bp = dev->data->dev_private;
3272         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3273         uint64_t ns, systime_cycles = 0;
3274         int rc = 0;
3275
3276         if (!ptp)
3277                 return 0;
3278
3279         if (BNXT_CHIP_THOR(bp))
3280                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3281                                              &systime_cycles);
3282         else
3283                 systime_cycles = bnxt_cc_read(bp);
3284
3285         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3286         *ts = rte_ns_to_timespec(ns);
3287
3288         return rc;
3289 }
3290 static int
3291 bnxt_timesync_enable(struct rte_eth_dev *dev)
3292 {
3293         struct bnxt *bp = dev->data->dev_private;
3294         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3295         uint32_t shift = 0;
3296         int rc;
3297
3298         if (!ptp)
3299                 return 0;
3300
3301         ptp->rx_filter = 1;
3302         ptp->tx_tstamp_en = 1;
3303         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3304
3305         rc = bnxt_hwrm_ptp_cfg(bp);
3306         if (rc)
3307                 return rc;
3308
3309         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3310         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3311         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3312
3313         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3314         ptp->tc.cc_shift = shift;
3315         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3316
3317         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3318         ptp->rx_tstamp_tc.cc_shift = shift;
3319         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3320
3321         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3322         ptp->tx_tstamp_tc.cc_shift = shift;
3323         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3324
3325         if (!BNXT_CHIP_THOR(bp))
3326                 bnxt_map_ptp_regs(bp);
3327
3328         return 0;
3329 }
3330
3331 static int
3332 bnxt_timesync_disable(struct rte_eth_dev *dev)
3333 {
3334         struct bnxt *bp = dev->data->dev_private;
3335         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3336
3337         if (!ptp)
3338                 return 0;
3339
3340         ptp->rx_filter = 0;
3341         ptp->tx_tstamp_en = 0;
3342         ptp->rxctl = 0;
3343
3344         bnxt_hwrm_ptp_cfg(bp);
3345
3346         if (!BNXT_CHIP_THOR(bp))
3347                 bnxt_unmap_ptp_regs(bp);
3348
3349         return 0;
3350 }
3351
3352 static int
3353 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3354                                  struct timespec *timestamp,
3355                                  uint32_t flags __rte_unused)
3356 {
3357         struct bnxt *bp = dev->data->dev_private;
3358         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3359         uint64_t rx_tstamp_cycles = 0;
3360         uint64_t ns;
3361
3362         if (!ptp)
3363                 return 0;
3364
3365         if (BNXT_CHIP_THOR(bp))
3366                 rx_tstamp_cycles = ptp->rx_timestamp;
3367         else
3368                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3369
3370         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3371         *timestamp = rte_ns_to_timespec(ns);
3372         return  0;
3373 }
3374
3375 static int
3376 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3377                                  struct timespec *timestamp)
3378 {
3379         struct bnxt *bp = dev->data->dev_private;
3380         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3381         uint64_t tx_tstamp_cycles = 0;
3382         uint64_t ns;
3383         int rc = 0;
3384
3385         if (!ptp)
3386                 return 0;
3387
3388         if (BNXT_CHIP_THOR(bp))
3389                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3390                                              &tx_tstamp_cycles);
3391         else
3392                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3393
3394         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3395         *timestamp = rte_ns_to_timespec(ns);
3396
3397         return rc;
3398 }
3399
3400 static int
3401 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3402 {
3403         struct bnxt *bp = dev->data->dev_private;
3404         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3405
3406         if (!ptp)
3407                 return 0;
3408
3409         ptp->tc.nsec += delta;
3410
3411         return 0;
3412 }
3413
3414 static int
3415 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3416 {
3417         struct bnxt *bp = dev->data->dev_private;
3418         int rc;
3419         uint32_t dir_entries;
3420         uint32_t entry_length;
3421
3422         rc = is_bnxt_in_error(bp);
3423         if (rc)
3424                 return rc;
3425
3426         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3427                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3428                 bp->pdev->addr.devid, bp->pdev->addr.function);
3429
3430         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3431         if (rc != 0)
3432                 return rc;
3433
3434         return dir_entries * entry_length;
3435 }
3436
3437 static int
3438 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3439                 struct rte_dev_eeprom_info *in_eeprom)
3440 {
3441         struct bnxt *bp = dev->data->dev_private;
3442         uint32_t index;
3443         uint32_t offset;
3444         int rc;
3445
3446         rc = is_bnxt_in_error(bp);
3447         if (rc)
3448                 return rc;
3449
3450         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3451                 "len = %d\n", bp->pdev->addr.domain,
3452                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3453                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3454
3455         if (in_eeprom->offset == 0) /* special offset value to get directory */
3456                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3457                                                 in_eeprom->data);
3458
3459         index = in_eeprom->offset >> 24;
3460         offset = in_eeprom->offset & 0xffffff;
3461
3462         if (index != 0)
3463                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3464                                            in_eeprom->length, in_eeprom->data);
3465
3466         return 0;
3467 }
3468
3469 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3470 {
3471         switch (dir_type) {
3472         case BNX_DIR_TYPE_CHIMP_PATCH:
3473         case BNX_DIR_TYPE_BOOTCODE:
3474         case BNX_DIR_TYPE_BOOTCODE_2:
3475         case BNX_DIR_TYPE_APE_FW:
3476         case BNX_DIR_TYPE_APE_PATCH:
3477         case BNX_DIR_TYPE_KONG_FW:
3478         case BNX_DIR_TYPE_KONG_PATCH:
3479         case BNX_DIR_TYPE_BONO_FW:
3480         case BNX_DIR_TYPE_BONO_PATCH:
3481                 /* FALLTHROUGH */
3482                 return true;
3483         }
3484
3485         return false;
3486 }
3487
3488 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3489 {
3490         switch (dir_type) {
3491         case BNX_DIR_TYPE_AVS:
3492         case BNX_DIR_TYPE_EXP_ROM_MBA:
3493         case BNX_DIR_TYPE_PCIE:
3494         case BNX_DIR_TYPE_TSCF_UCODE:
3495         case BNX_DIR_TYPE_EXT_PHY:
3496         case BNX_DIR_TYPE_CCM:
3497         case BNX_DIR_TYPE_ISCSI_BOOT:
3498         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3499         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3500                 /* FALLTHROUGH */
3501                 return true;
3502         }
3503
3504         return false;
3505 }
3506
3507 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3508 {
3509         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3510                 bnxt_dir_type_is_other_exec_format(dir_type);
3511 }
3512
3513 static int
3514 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3515                 struct rte_dev_eeprom_info *in_eeprom)
3516 {
3517         struct bnxt *bp = dev->data->dev_private;
3518         uint8_t index, dir_op;
3519         uint16_t type, ext, ordinal, attr;
3520         int rc;
3521
3522         rc = is_bnxt_in_error(bp);
3523         if (rc)
3524                 return rc;
3525
3526         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3527                 "len = %d\n", bp->pdev->addr.domain,
3528                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3529                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3530
3531         if (!BNXT_PF(bp)) {
3532                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3533                 return -EINVAL;
3534         }
3535
3536         type = in_eeprom->magic >> 16;
3537
3538         if (type == 0xffff) { /* special value for directory operations */
3539                 index = in_eeprom->magic & 0xff;
3540                 dir_op = in_eeprom->magic >> 8;
3541                 if (index == 0)
3542                         return -EINVAL;
3543                 switch (dir_op) {
3544                 case 0x0e: /* erase */
3545                         if (in_eeprom->offset != ~in_eeprom->magic)
3546                                 return -EINVAL;
3547                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3548                 default:
3549                         return -EINVAL;
3550                 }
3551         }
3552
3553         /* Create or re-write an NVM item: */
3554         if (bnxt_dir_type_is_executable(type) == true)
3555                 return -EOPNOTSUPP;
3556         ext = in_eeprom->magic & 0xffff;
3557         ordinal = in_eeprom->offset >> 16;
3558         attr = in_eeprom->offset & 0xffff;
3559
3560         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3561                                      in_eeprom->data, in_eeprom->length);
3562 }
3563
3564 /*
3565  * Initialization
3566  */
3567
3568 static const struct eth_dev_ops bnxt_dev_ops = {
3569         .dev_infos_get = bnxt_dev_info_get_op,
3570         .dev_close = bnxt_dev_close_op,
3571         .dev_configure = bnxt_dev_configure_op,
3572         .dev_start = bnxt_dev_start_op,
3573         .dev_stop = bnxt_dev_stop_op,
3574         .dev_set_link_up = bnxt_dev_set_link_up_op,
3575         .dev_set_link_down = bnxt_dev_set_link_down_op,
3576         .stats_get = bnxt_stats_get_op,
3577         .stats_reset = bnxt_stats_reset_op,
3578         .rx_queue_setup = bnxt_rx_queue_setup_op,
3579         .rx_queue_release = bnxt_rx_queue_release_op,
3580         .tx_queue_setup = bnxt_tx_queue_setup_op,
3581         .tx_queue_release = bnxt_tx_queue_release_op,
3582         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3583         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3584         .reta_update = bnxt_reta_update_op,
3585         .reta_query = bnxt_reta_query_op,
3586         .rss_hash_update = bnxt_rss_hash_update_op,
3587         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3588         .link_update = bnxt_link_update_op,
3589         .promiscuous_enable = bnxt_promiscuous_enable_op,
3590         .promiscuous_disable = bnxt_promiscuous_disable_op,
3591         .allmulticast_enable = bnxt_allmulticast_enable_op,
3592         .allmulticast_disable = bnxt_allmulticast_disable_op,
3593         .mac_addr_add = bnxt_mac_addr_add_op,
3594         .mac_addr_remove = bnxt_mac_addr_remove_op,
3595         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3596         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3597         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3598         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3599         .vlan_filter_set = bnxt_vlan_filter_set_op,
3600         .vlan_offload_set = bnxt_vlan_offload_set_op,
3601         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3602         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3603         .mtu_set = bnxt_mtu_set_op,
3604         .mac_addr_set = bnxt_set_default_mac_addr_op,
3605         .xstats_get = bnxt_dev_xstats_get_op,
3606         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3607         .xstats_reset = bnxt_dev_xstats_reset_op,
3608         .fw_version_get = bnxt_fw_version_get,
3609         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3610         .rxq_info_get = bnxt_rxq_info_get_op,
3611         .txq_info_get = bnxt_txq_info_get_op,
3612         .dev_led_on = bnxt_dev_led_on_op,
3613         .dev_led_off = bnxt_dev_led_off_op,
3614         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3615         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3616         .rx_queue_count = bnxt_rx_queue_count_op,
3617         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3618         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3619         .rx_queue_start = bnxt_rx_queue_start,
3620         .rx_queue_stop = bnxt_rx_queue_stop,
3621         .tx_queue_start = bnxt_tx_queue_start,
3622         .tx_queue_stop = bnxt_tx_queue_stop,
3623         .filter_ctrl = bnxt_filter_ctrl_op,
3624         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3625         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3626         .get_eeprom           = bnxt_get_eeprom_op,
3627         .set_eeprom           = bnxt_set_eeprom_op,
3628         .timesync_enable      = bnxt_timesync_enable,
3629         .timesync_disable     = bnxt_timesync_disable,
3630         .timesync_read_time   = bnxt_timesync_read_time,
3631         .timesync_write_time   = bnxt_timesync_write_time,
3632         .timesync_adjust_time = bnxt_timesync_adjust_time,
3633         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3634         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3635 };
3636
3637 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3638 {
3639         uint32_t offset;
3640
3641         /* Only pre-map the reset GRC registers using window 3 */
3642         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3643                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3644
3645         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3646
3647         return offset;
3648 }
3649
3650 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3651 {
3652         struct bnxt_error_recovery_info *info = bp->recovery_info;
3653         uint32_t reg_base = 0xffffffff;
3654         int i;
3655
3656         /* Only pre-map the monitoring GRC registers using window 2 */
3657         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3658                 uint32_t reg = info->status_regs[i];
3659
3660                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3661                         continue;
3662
3663                 if (reg_base == 0xffffffff)
3664                         reg_base = reg & 0xfffff000;
3665                 if ((reg & 0xfffff000) != reg_base)
3666                         return -ERANGE;
3667
3668                 /* Use mask 0xffc as the Lower 2 bits indicates
3669                  * address space location
3670                  */
3671                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3672                                                 (reg & 0xffc);
3673         }
3674
3675         if (reg_base == 0xffffffff)
3676                 return 0;
3677
3678         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3679                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3680
3681         return 0;
3682 }
3683
3684 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3685 {
3686         struct bnxt_error_recovery_info *info = bp->recovery_info;
3687         uint32_t delay = info->delay_after_reset[index];
3688         uint32_t val = info->reset_reg_val[index];
3689         uint32_t reg = info->reset_reg[index];
3690         uint32_t type, offset;
3691
3692         type = BNXT_FW_STATUS_REG_TYPE(reg);
3693         offset = BNXT_FW_STATUS_REG_OFF(reg);
3694
3695         switch (type) {
3696         case BNXT_FW_STATUS_REG_TYPE_CFG:
3697                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3698                 break;
3699         case BNXT_FW_STATUS_REG_TYPE_GRC:
3700                 offset = bnxt_map_reset_regs(bp, offset);
3701                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3702                 break;
3703         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3704                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3705                 break;
3706         }
3707         /* wait on a specific interval of time until core reset is complete */
3708         if (delay)
3709                 rte_delay_ms(delay);
3710 }
3711
3712 static void bnxt_dev_cleanup(struct bnxt *bp)
3713 {
3714         bnxt_set_hwrm_link_config(bp, false);
3715         bp->link_info.link_up = 0;
3716         if (bp->dev_stopped == 0)
3717                 bnxt_dev_stop_op(bp->eth_dev);
3718
3719         bnxt_uninit_resources(bp, true);
3720 }
3721
3722 static int bnxt_restore_filters(struct bnxt *bp)
3723 {
3724         struct rte_eth_dev *dev = bp->eth_dev;
3725         int ret = 0;
3726
3727         if (dev->data->all_multicast)
3728                 ret = bnxt_allmulticast_enable_op(dev);
3729         if (dev->data->promiscuous)
3730                 ret = bnxt_promiscuous_enable_op(dev);
3731
3732         /* TODO restore other filters as well */
3733         return ret;
3734 }
3735
3736 static void bnxt_dev_recover(void *arg)
3737 {
3738         struct bnxt *bp = arg;
3739         int timeout = bp->fw_reset_max_msecs;
3740         int rc = 0;
3741
3742         /* Clear Error flag so that device re-init should happen */
3743         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3744
3745         do {
3746                 rc = bnxt_hwrm_ver_get(bp);
3747                 if (rc == 0)
3748                         break;
3749                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3750                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3751         } while (rc && timeout);
3752
3753         if (rc) {
3754                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3755                 goto err;
3756         }
3757
3758         rc = bnxt_init_resources(bp, true);
3759         if (rc) {
3760                 PMD_DRV_LOG(ERR,
3761                             "Failed to initialize resources after reset\n");
3762                 goto err;
3763         }
3764         /* clear reset flag as the device is initialized now */
3765         bp->flags &= ~BNXT_FLAG_FW_RESET;
3766
3767         rc = bnxt_dev_start_op(bp->eth_dev);
3768         if (rc) {
3769                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3770                 goto err;
3771         }
3772
3773         rc = bnxt_restore_filters(bp);
3774         if (rc)
3775                 goto err;
3776
3777         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3778         return;
3779 err:
3780         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3781         bnxt_uninit_resources(bp, false);
3782         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3783 }
3784
3785 void bnxt_dev_reset_and_resume(void *arg)
3786 {
3787         struct bnxt *bp = arg;
3788         int rc;
3789
3790         bnxt_dev_cleanup(bp);
3791
3792         bnxt_wait_for_device_shutdown(bp);
3793
3794         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3795                                bnxt_dev_recover, (void *)bp);
3796         if (rc)
3797                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3798 }
3799
3800 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3801 {
3802         struct bnxt_error_recovery_info *info = bp->recovery_info;
3803         uint32_t reg = info->status_regs[index];
3804         uint32_t type, offset, val = 0;
3805
3806         type = BNXT_FW_STATUS_REG_TYPE(reg);
3807         offset = BNXT_FW_STATUS_REG_OFF(reg);
3808
3809         switch (type) {
3810         case BNXT_FW_STATUS_REG_TYPE_CFG:
3811                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3812                 break;
3813         case BNXT_FW_STATUS_REG_TYPE_GRC:
3814                 offset = info->mapped_status_regs[index];
3815                 /* FALLTHROUGH */
3816         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3817                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3818                                        offset));
3819                 break;
3820         }
3821
3822         return val;
3823 }
3824
3825 static int bnxt_fw_reset_all(struct bnxt *bp)
3826 {
3827         struct bnxt_error_recovery_info *info = bp->recovery_info;
3828         uint32_t i;
3829         int rc = 0;
3830
3831         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3832                 /* Reset through master function driver */
3833                 for (i = 0; i < info->reg_array_cnt; i++)
3834                         bnxt_write_fw_reset_reg(bp, i);
3835                 /* Wait for time specified by FW after triggering reset */
3836                 rte_delay_ms(info->master_func_wait_period_after_reset);
3837         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3838                 /* Reset with the help of Kong processor */
3839                 rc = bnxt_hwrm_fw_reset(bp);
3840                 if (rc)
3841                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3842         }
3843
3844         return rc;
3845 }
3846
3847 static void bnxt_fw_reset_cb(void *arg)
3848 {
3849         struct bnxt *bp = arg;
3850         struct bnxt_error_recovery_info *info = bp->recovery_info;
3851         int rc = 0;
3852
3853         /* Only Master function can do FW reset */
3854         if (bnxt_is_master_func(bp) &&
3855             bnxt_is_recovery_enabled(bp)) {
3856                 rc = bnxt_fw_reset_all(bp);
3857                 if (rc) {
3858                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3859                         return;
3860                 }
3861         }
3862
3863         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3864          * EXCEPTION_FATAL_ASYNC event to all the functions
3865          * (including MASTER FUNC). After receiving this Async, all the active
3866          * drivers should treat this case as FW initiated recovery
3867          */
3868         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3869                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3870                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3871
3872                 /* To recover from error */
3873                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3874                                   (void *)bp);
3875         }
3876 }
3877
3878 /* Driver should poll FW heartbeat, reset_counter with the frequency
3879  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3880  * When the driver detects heartbeat stop or change in reset_counter,
3881  * it has to trigger a reset to recover from the error condition.
3882  * A “master PF” is the function who will have the privilege to
3883  * initiate the chimp reset. The master PF will be elected by the
3884  * firmware and will be notified through async message.
3885  */
3886 static void bnxt_check_fw_health(void *arg)
3887 {
3888         struct bnxt *bp = arg;
3889         struct bnxt_error_recovery_info *info = bp->recovery_info;
3890         uint32_t val = 0, wait_msec;
3891
3892         if (!info || !bnxt_is_recovery_enabled(bp) ||
3893             is_bnxt_in_error(bp))
3894                 return;
3895
3896         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3897         if (val == info->last_heart_beat)
3898                 goto reset;
3899
3900         info->last_heart_beat = val;
3901
3902         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3903         if (val != info->last_reset_counter)
3904                 goto reset;
3905
3906         info->last_reset_counter = val;
3907
3908         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3909                           bnxt_check_fw_health, (void *)bp);
3910
3911         return;
3912 reset:
3913         /* Stop DMA to/from device */
3914         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3915         bp->flags |= BNXT_FLAG_FW_RESET;
3916
3917         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3918
3919         if (bnxt_is_master_func(bp))
3920                 wait_msec = info->master_func_wait_period;
3921         else
3922                 wait_msec = info->normal_func_wait_period;
3923
3924         rte_eal_alarm_set(US_PER_MS * wait_msec,
3925                           bnxt_fw_reset_cb, (void *)bp);
3926 }
3927
3928 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3929 {
3930         uint32_t polling_freq;
3931
3932         if (!bnxt_is_recovery_enabled(bp))
3933                 return;
3934
3935         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3936                 return;
3937
3938         polling_freq = bp->recovery_info->driver_polling_freq;
3939
3940         rte_eal_alarm_set(US_PER_MS * polling_freq,
3941                           bnxt_check_fw_health, (void *)bp);
3942         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3943 }
3944
3945 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3946 {
3947         if (!bnxt_is_recovery_enabled(bp))
3948                 return;
3949
3950         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3951         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3952 }
3953
3954 static bool bnxt_vf_pciid(uint16_t id)
3955 {
3956         if (id == BROADCOM_DEV_ID_57304_VF ||
3957             id == BROADCOM_DEV_ID_57406_VF ||
3958             id == BROADCOM_DEV_ID_5731X_VF ||
3959             id == BROADCOM_DEV_ID_5741X_VF ||
3960             id == BROADCOM_DEV_ID_57414_VF ||
3961             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3962             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3963             id == BROADCOM_DEV_ID_58802_VF ||
3964             id == BROADCOM_DEV_ID_57500_VF1 ||
3965             id == BROADCOM_DEV_ID_57500_VF2)
3966                 return true;
3967         return false;
3968 }
3969
3970 bool bnxt_stratus_device(struct bnxt *bp)
3971 {
3972         uint16_t id = bp->pdev->id.device_id;
3973
3974         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3975             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3976             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3977                 return true;
3978         return false;
3979 }
3980
3981 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3982 {
3983         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3984         struct bnxt *bp = eth_dev->data->dev_private;
3985
3986         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3987         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3988         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3989         if (!bp->bar0 || !bp->doorbell_base) {
3990                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3991                 return -ENODEV;
3992         }
3993
3994         bp->eth_dev = eth_dev;
3995         bp->pdev = pci_dev;
3996
3997         return 0;
3998 }
3999
4000 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
4001                                   struct bnxt_ctx_pg_info *ctx_pg,
4002                                   uint32_t mem_size,
4003                                   const char *suffix,
4004                                   uint16_t idx)
4005 {
4006         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4007         const struct rte_memzone *mz = NULL;
4008         char mz_name[RTE_MEMZONE_NAMESIZE];
4009         rte_iova_t mz_phys_addr;
4010         uint64_t valid_bits = 0;
4011         uint32_t sz;
4012         int i;
4013
4014         if (!mem_size)
4015                 return 0;
4016
4017         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4018                          BNXT_PAGE_SIZE;
4019         rmem->page_size = BNXT_PAGE_SIZE;
4020         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4021         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4022         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4023
4024         valid_bits = PTU_PTE_VALID;
4025
4026         if (rmem->nr_pages > 1) {
4027                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4028                          "bnxt_ctx_pg_tbl%s_%x_%d",
4029                          suffix, idx, bp->eth_dev->data->port_id);
4030                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4031                 mz = rte_memzone_lookup(mz_name);
4032                 if (!mz) {
4033                         mz = rte_memzone_reserve_aligned(mz_name,
4034                                                 rmem->nr_pages * 8,
4035                                                 SOCKET_ID_ANY,
4036                                                 RTE_MEMZONE_2MB |
4037                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4038                                                 RTE_MEMZONE_IOVA_CONTIG,
4039                                                 BNXT_PAGE_SIZE);
4040                         if (mz == NULL)
4041                                 return -ENOMEM;
4042                 }
4043
4044                 memset(mz->addr, 0, mz->len);
4045                 mz_phys_addr = mz->iova;
4046                 if ((unsigned long)mz->addr == mz_phys_addr) {
4047                         PMD_DRV_LOG(DEBUG,
4048                                     "physical address same as virtual\n");
4049                         PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4050                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
4051                         if (mz_phys_addr == RTE_BAD_IOVA) {
4052                                 PMD_DRV_LOG(ERR,
4053                                         "unable to map addr to phys memory\n");
4054                                 return -ENOMEM;
4055                         }
4056                 }
4057                 rte_mem_lock_page(((char *)mz->addr));
4058
4059                 rmem->pg_tbl = mz->addr;
4060                 rmem->pg_tbl_map = mz_phys_addr;
4061                 rmem->pg_tbl_mz = mz;
4062         }
4063
4064         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4065                  suffix, idx, bp->eth_dev->data->port_id);
4066         mz = rte_memzone_lookup(mz_name);
4067         if (!mz) {
4068                 mz = rte_memzone_reserve_aligned(mz_name,
4069                                                  mem_size,
4070                                                  SOCKET_ID_ANY,
4071                                                  RTE_MEMZONE_1GB |
4072                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4073                                                  RTE_MEMZONE_IOVA_CONTIG,
4074                                                  BNXT_PAGE_SIZE);
4075                 if (mz == NULL)
4076                         return -ENOMEM;
4077         }
4078
4079         memset(mz->addr, 0, mz->len);
4080         mz_phys_addr = mz->iova;
4081         if ((unsigned long)mz->addr == mz_phys_addr) {
4082                 PMD_DRV_LOG(DEBUG,
4083                             "Memzone physical address same as virtual.\n");
4084                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4085                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4086                         rte_mem_lock_page(((char *)mz->addr) + sz);
4087                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4088                 if (mz_phys_addr == RTE_BAD_IOVA) {
4089                         PMD_DRV_LOG(ERR,
4090                                     "unable to map addr to phys memory\n");
4091                         return -ENOMEM;
4092                 }
4093         }
4094
4095         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4096                 rte_mem_lock_page(((char *)mz->addr) + sz);
4097                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4098                 rmem->dma_arr[i] = mz_phys_addr + sz;
4099
4100                 if (rmem->nr_pages > 1) {
4101                         if (i == rmem->nr_pages - 2 &&
4102                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4103                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4104                         else if (i == rmem->nr_pages - 1 &&
4105                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4106                                 valid_bits |= PTU_PTE_LAST;
4107
4108                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4109                                                            valid_bits);
4110                 }
4111         }
4112
4113         rmem->mz = mz;
4114         if (rmem->vmem_size)
4115                 rmem->vmem = (void **)mz->addr;
4116         rmem->dma_arr[0] = mz_phys_addr;
4117         return 0;
4118 }
4119
4120 static void bnxt_free_ctx_mem(struct bnxt *bp)
4121 {
4122         int i;
4123
4124         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4125                 return;
4126
4127         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4128         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4129         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4130         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4131         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4132         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4133         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4134         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4135         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4136         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4137         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4138
4139         for (i = 0; i < BNXT_MAX_Q; i++) {
4140                 if (bp->ctx->tqm_mem[i])
4141                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4142         }
4143
4144         rte_free(bp->ctx);
4145         bp->ctx = NULL;
4146 }
4147
4148 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4149
4150 #define min_t(type, x, y) ({                    \
4151         type __min1 = (x);                      \
4152         type __min2 = (y);                      \
4153         __min1 < __min2 ? __min1 : __min2; })
4154
4155 #define max_t(type, x, y) ({                    \
4156         type __max1 = (x);                      \
4157         type __max2 = (y);                      \
4158         __max1 > __max2 ? __max1 : __max2; })
4159
4160 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4161
4162 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4163 {
4164         struct bnxt_ctx_pg_info *ctx_pg;
4165         struct bnxt_ctx_mem_info *ctx;
4166         uint32_t mem_size, ena, entries;
4167         int i, rc;
4168
4169         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4170         if (rc) {
4171                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4172                 return rc;
4173         }
4174         ctx = bp->ctx;
4175         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4176                 return 0;
4177
4178         ctx_pg = &ctx->qp_mem;
4179         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4180         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4181         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4182         if (rc)
4183                 return rc;
4184
4185         ctx_pg = &ctx->srq_mem;
4186         ctx_pg->entries = ctx->srq_max_l2_entries;
4187         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4188         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4189         if (rc)
4190                 return rc;
4191
4192         ctx_pg = &ctx->cq_mem;
4193         ctx_pg->entries = ctx->cq_max_l2_entries;
4194         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4195         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4196         if (rc)
4197                 return rc;
4198
4199         ctx_pg = &ctx->vnic_mem;
4200         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4201                 ctx->vnic_max_ring_table_entries;
4202         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4203         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4204         if (rc)
4205                 return rc;
4206
4207         ctx_pg = &ctx->stat_mem;
4208         ctx_pg->entries = ctx->stat_max_entries;
4209         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4210         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4211         if (rc)
4212                 return rc;
4213
4214         entries = ctx->qp_max_l2_entries;
4215         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4216         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4217                           ctx->tqm_max_entries_per_ring);
4218         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4219                 ctx_pg = ctx->tqm_mem[i];
4220                 /* use min tqm entries for now. */
4221                 ctx_pg->entries = entries;
4222                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4223                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4224                 if (rc)
4225                         return rc;
4226                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4227         }
4228
4229         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4230         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4231         if (rc)
4232                 PMD_DRV_LOG(ERR,
4233                             "Failed to configure context mem: rc = %d\n", rc);
4234         else
4235                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4236
4237         return rc;
4238 }
4239
4240 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4241 {
4242         struct rte_pci_device *pci_dev = bp->pdev;
4243         char mz_name[RTE_MEMZONE_NAMESIZE];
4244         const struct rte_memzone *mz = NULL;
4245         uint32_t total_alloc_len;
4246         rte_iova_t mz_phys_addr;
4247
4248         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4249                 return 0;
4250
4251         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4252                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4253                  pci_dev->addr.bus, pci_dev->addr.devid,
4254                  pci_dev->addr.function, "rx_port_stats");
4255         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4256         mz = rte_memzone_lookup(mz_name);
4257         total_alloc_len =
4258                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4259                                        sizeof(struct rx_port_stats_ext) + 512);
4260         if (!mz) {
4261                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4262                                          SOCKET_ID_ANY,
4263                                          RTE_MEMZONE_2MB |
4264                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4265                                          RTE_MEMZONE_IOVA_CONTIG);
4266                 if (mz == NULL)
4267                         return -ENOMEM;
4268         }
4269         memset(mz->addr, 0, mz->len);
4270         mz_phys_addr = mz->iova;
4271         if ((unsigned long)mz->addr == mz_phys_addr) {
4272                 PMD_DRV_LOG(DEBUG,
4273                             "Memzone physical address same as virtual.\n");
4274                 PMD_DRV_LOG(DEBUG,
4275                             "Using rte_mem_virt2iova()\n");
4276                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4277                 if (mz_phys_addr == RTE_BAD_IOVA) {
4278                         PMD_DRV_LOG(ERR,
4279                                     "Can't map address to physical memory\n");
4280                         return -ENOMEM;
4281                 }
4282         }
4283
4284         bp->rx_mem_zone = (const void *)mz;
4285         bp->hw_rx_port_stats = mz->addr;
4286         bp->hw_rx_port_stats_map = mz_phys_addr;
4287
4288         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4289                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4290                  pci_dev->addr.bus, pci_dev->addr.devid,
4291                  pci_dev->addr.function, "tx_port_stats");
4292         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4293         mz = rte_memzone_lookup(mz_name);
4294         total_alloc_len =
4295                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4296                                        sizeof(struct tx_port_stats_ext) + 512);
4297         if (!mz) {
4298                 mz = rte_memzone_reserve(mz_name,
4299                                          total_alloc_len,
4300                                          SOCKET_ID_ANY,
4301                                          RTE_MEMZONE_2MB |
4302                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4303                                          RTE_MEMZONE_IOVA_CONTIG);
4304                 if (mz == NULL)
4305                         return -ENOMEM;
4306         }
4307         memset(mz->addr, 0, mz->len);
4308         mz_phys_addr = mz->iova;
4309         if ((unsigned long)mz->addr == mz_phys_addr) {
4310                 PMD_DRV_LOG(DEBUG,
4311                             "Memzone physical address same as virtual\n");
4312                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4313                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4314                 if (mz_phys_addr == RTE_BAD_IOVA) {
4315                         PMD_DRV_LOG(ERR,
4316                                     "Can't map address to physical memory\n");
4317                         return -ENOMEM;
4318                 }
4319         }
4320
4321         bp->tx_mem_zone = (const void *)mz;
4322         bp->hw_tx_port_stats = mz->addr;
4323         bp->hw_tx_port_stats_map = mz_phys_addr;
4324         bp->flags |= BNXT_FLAG_PORT_STATS;
4325
4326         /* Display extended statistics if FW supports it */
4327         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4328             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4329             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4330                 return 0;
4331
4332         bp->hw_rx_port_stats_ext = (void *)
4333                 ((uint8_t *)bp->hw_rx_port_stats +
4334                  sizeof(struct rx_port_stats));
4335         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4336                 sizeof(struct rx_port_stats);
4337         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4338
4339         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4340             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4341                 bp->hw_tx_port_stats_ext = (void *)
4342                         ((uint8_t *)bp->hw_tx_port_stats +
4343                          sizeof(struct tx_port_stats));
4344                 bp->hw_tx_port_stats_ext_map =
4345                         bp->hw_tx_port_stats_map +
4346                         sizeof(struct tx_port_stats);
4347                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4348         }
4349
4350         return 0;
4351 }
4352
4353 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4354 {
4355         struct bnxt *bp = eth_dev->data->dev_private;
4356         int rc = 0;
4357
4358         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4359                                                RTE_ETHER_ADDR_LEN *
4360                                                bp->max_l2_ctx,
4361                                                0);
4362         if (eth_dev->data->mac_addrs == NULL) {
4363                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4364                 return -ENOMEM;
4365         }
4366
4367         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4368                 if (BNXT_PF(bp))
4369                         return -EINVAL;
4370
4371                 /* Generate a random MAC address, if none was assigned by PF */
4372                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4373                 bnxt_eth_hw_addr_random(bp->mac_addr);
4374                 PMD_DRV_LOG(INFO,
4375                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4376                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4377                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4378
4379                 rc = bnxt_hwrm_set_mac(bp);
4380                 if (!rc)
4381                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4382                                RTE_ETHER_ADDR_LEN);
4383                 return rc;
4384         }
4385
4386         /* Copy the permanent MAC from the FUNC_QCAPS response */
4387         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4388         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4389
4390         return rc;
4391 }
4392
4393 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4394 {
4395         int rc = 0;
4396
4397         /* MAC is already configured in FW */
4398         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4399                 return 0;
4400
4401         /* Restore the old MAC configured */
4402         rc = bnxt_hwrm_set_mac(bp);
4403         if (rc)
4404                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4405
4406         return rc;
4407 }
4408
4409 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4410 {
4411         if (!BNXT_PF(bp))
4412                 return;
4413
4414 #define ALLOW_FUNC(x)   \
4415         { \
4416                 uint32_t arg = (x); \
4417                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4418                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4419         }
4420
4421         /* Forward all requests if firmware is new enough */
4422         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4423              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4424             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4425                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4426         } else {
4427                 PMD_DRV_LOG(WARNING,
4428                             "Firmware too old for VF mailbox functionality\n");
4429                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4430         }
4431
4432         /*
4433          * The following are used for driver cleanup. If we disallow these,
4434          * VF drivers can't clean up cleanly.
4435          */
4436         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4437         ALLOW_FUNC(HWRM_VNIC_FREE);
4438         ALLOW_FUNC(HWRM_RING_FREE);
4439         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4440         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4441         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4442         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4443         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4444         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4445 }
4446
4447 static int bnxt_init_fw(struct bnxt *bp)
4448 {
4449         uint16_t mtu;
4450         int rc = 0;
4451
4452         rc = bnxt_hwrm_ver_get(bp);
4453         if (rc)
4454                 return rc;
4455
4456         rc = bnxt_hwrm_func_reset(bp);
4457         if (rc)
4458                 return -EIO;
4459
4460         rc = bnxt_hwrm_queue_qportcfg(bp);
4461         if (rc)
4462                 return rc;
4463
4464         /* Get the MAX capabilities for this function */
4465         rc = bnxt_hwrm_func_qcaps(bp);
4466         if (rc)
4467                 return rc;
4468
4469         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4470         if (rc)
4471                 return rc;
4472
4473         /* Get the adapter error recovery support info */
4474         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4475         if (rc)
4476                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4477
4478         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4479             mtu != bp->eth_dev->data->mtu)
4480                 bp->eth_dev->data->mtu = mtu;
4481
4482         bnxt_hwrm_port_led_qcaps(bp);
4483
4484         return 0;
4485 }
4486
4487 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4488 {
4489         int rc;
4490
4491         rc = bnxt_init_fw(bp);
4492         if (rc)
4493                 return rc;
4494
4495         if (!reconfig_dev) {
4496                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4497                 if (rc)
4498                         return rc;
4499         } else {
4500                 rc = bnxt_restore_dflt_mac(bp);
4501                 if (rc)
4502                         return rc;
4503         }
4504
4505         bnxt_config_vf_req_fwd(bp);
4506
4507         rc = bnxt_hwrm_func_driver_register(bp);
4508         if (rc) {
4509                 PMD_DRV_LOG(ERR, "Failed to register driver");
4510                 return -EBUSY;
4511         }
4512
4513         if (BNXT_PF(bp)) {
4514                 if (bp->pdev->max_vfs) {
4515                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4516                         if (rc) {
4517                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4518                                 return rc;
4519                         }
4520                 } else {
4521                         rc = bnxt_hwrm_allocate_pf_only(bp);
4522                         if (rc) {
4523                                 PMD_DRV_LOG(ERR,
4524                                             "Failed to allocate PF resources");
4525                                 return rc;
4526                         }
4527                 }
4528         }
4529
4530         rc = bnxt_alloc_mem(bp, reconfig_dev);
4531         if (rc)
4532                 return rc;
4533
4534         rc = bnxt_setup_int(bp);
4535         if (rc)
4536                 return rc;
4537
4538         bnxt_init_nic(bp);
4539
4540         rc = bnxt_request_int(bp);
4541         if (rc)
4542                 return rc;
4543
4544         return 0;
4545 }
4546
4547 static int
4548 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4549 {
4550         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4551         static int version_printed;
4552         struct bnxt *bp;
4553         int rc;
4554
4555         if (version_printed++ == 0)
4556                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4557
4558         eth_dev->dev_ops = &bnxt_dev_ops;
4559         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4560         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4561
4562         /*
4563          * For secondary processes, we don't initialise any further
4564          * as primary has already done this work.
4565          */
4566         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4567                 return 0;
4568
4569         rte_eth_copy_pci_info(eth_dev, pci_dev);
4570
4571         bp = eth_dev->data->dev_private;
4572
4573         bp->dev_stopped = 1;
4574
4575         if (bnxt_vf_pciid(pci_dev->id.device_id))
4576                 bp->flags |= BNXT_FLAG_VF;
4577
4578         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4579             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4580             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4581             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4582             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4583                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4584
4585         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4586             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4587             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4588             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4589                 bp->flags |= BNXT_FLAG_STINGRAY;
4590
4591         rc = bnxt_init_board(eth_dev);
4592         if (rc) {
4593                 PMD_DRV_LOG(ERR,
4594                             "Failed to initialize board rc: %x\n", rc);
4595                 return rc;
4596         }
4597
4598         rc = bnxt_alloc_hwrm_resources(bp);
4599         if (rc) {
4600                 PMD_DRV_LOG(ERR,
4601                             "Failed to allocate hwrm resource rc: %x\n", rc);
4602                 goto error_free;
4603         }
4604         rc = bnxt_init_resources(bp, false);
4605         if (rc)
4606                 goto error_free;
4607
4608         rc = bnxt_alloc_stats_mem(bp);
4609         if (rc)
4610                 goto error_free;
4611
4612         PMD_DRV_LOG(INFO,
4613                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4614                     pci_dev->mem_resource[0].phys_addr,
4615                     pci_dev->mem_resource[0].addr);
4616
4617         return 0;
4618
4619 error_free:
4620         bnxt_dev_uninit(eth_dev);
4621         return rc;
4622 }
4623
4624 static int
4625 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4626 {
4627         int rc;
4628
4629         bnxt_free_int(bp);
4630         bnxt_free_mem(bp, reconfig_dev);
4631         bnxt_hwrm_func_buf_unrgtr(bp);
4632         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4633         bp->flags &= ~BNXT_FLAG_REGISTERED;
4634         bnxt_free_ctx_mem(bp);
4635         if (!reconfig_dev) {
4636                 bnxt_free_hwrm_resources(bp);
4637
4638                 if (bp->recovery_info != NULL) {
4639                         rte_free(bp->recovery_info);
4640                         bp->recovery_info = NULL;
4641                 }
4642         }
4643
4644         rte_free(bp->ptp_cfg);
4645         bp->ptp_cfg = NULL;
4646         return rc;
4647 }
4648
4649 static int
4650 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4651 {
4652         struct bnxt *bp = eth_dev->data->dev_private;
4653         int rc;
4654
4655         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4656                 return -EPERM;
4657
4658         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4659
4660         rc = bnxt_uninit_resources(bp, false);
4661
4662         if (bp->grp_info != NULL) {
4663                 rte_free(bp->grp_info);
4664                 bp->grp_info = NULL;
4665         }
4666
4667         if (bp->tx_mem_zone) {
4668                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4669                 bp->tx_mem_zone = NULL;
4670         }
4671
4672         if (bp->rx_mem_zone) {
4673                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4674                 bp->rx_mem_zone = NULL;
4675         }
4676
4677         if (bp->dev_stopped == 0)
4678                 bnxt_dev_close_op(eth_dev);
4679         if (bp->pf.vf_info)
4680                 rte_free(bp->pf.vf_info);
4681         eth_dev->dev_ops = NULL;
4682         eth_dev->rx_pkt_burst = NULL;
4683         eth_dev->tx_pkt_burst = NULL;
4684
4685         return rc;
4686 }
4687
4688 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4689         struct rte_pci_device *pci_dev)
4690 {
4691         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4692                 bnxt_dev_init);
4693 }
4694
4695 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4696 {
4697         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4698                 return rte_eth_dev_pci_generic_remove(pci_dev,
4699                                 bnxt_dev_uninit);
4700         else
4701                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4702 }
4703
4704 static struct rte_pci_driver bnxt_rte_pmd = {
4705         .id_table = bnxt_pci_id_map,
4706         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4707         .probe = bnxt_pci_probe,
4708         .remove = bnxt_pci_remove,
4709 };
4710
4711 static bool
4712 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4713 {
4714         if (strcmp(dev->device->driver->name, drv->driver.name))
4715                 return false;
4716
4717         return true;
4718 }
4719
4720 bool is_bnxt_supported(struct rte_eth_dev *dev)
4721 {
4722         return is_device_supported(dev, &bnxt_rte_pmd);
4723 }
4724
4725 RTE_INIT(bnxt_init_log)
4726 {
4727         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4728         if (bnxt_logtype_driver >= 0)
4729                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4730 }
4731
4732 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4733 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4734 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");