drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  91 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  92 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  93 #define BNXT_DEVARG_REPRESENTOR "representor"
  94 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  95 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  96 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  97 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  98 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  99 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 100
 101 static const char *const bnxt_dev_args[] = {
 102         BNXT_DEVARG_REPRESENTOR,
 103         BNXT_DEVARG_TRUFLOW,
 104         BNXT_DEVARG_FLOW_XSTAT,
 105         BNXT_DEVARG_MAX_NUM_KFLOWS,
 106         BNXT_DEVARG_REP_BASED_PF,
 107         BNXT_DEVARG_REP_IS_PF,
 108         BNXT_DEVARG_REP_Q_R2F,
 109         BNXT_DEVARG_REP_Q_F2R,
 110         BNXT_DEVARG_REP_FC_R2F,
 111         BNXT_DEVARG_REP_FC_F2R,
 112         NULL
 113 };
 114
 115 /*
 116  * truflow == false to disable the feature
 117  * truflow == true to enable the feature
 118  */
 119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 120
 121 /*
 122  * flow_xstat == false to disable the feature
 123  * flow_xstat == true to enable the feature
 124  */
 125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 126
 127 /*
 128  * rep_is_pf == false to indicate VF representor
 129  * rep_is_pf == true to indicate PF representor
 130  */
 131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 132
 133 /*
 134  * rep_based_pf == Physical index of the PF
 135  */
 136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 137 /*
 138  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 139  */
 140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 141
 142 /*
 143  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 144  */
 145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 146
 147 /*
 148  * rep_fc_r2f == Flow control for the representor to endpoint direction
 149  */
 150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 151
 152 /*
 153  * rep_fc_f2r == Flow control for the endpoint to representor direction
 154  */
 155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 156
 157 int bnxt_cfa_code_dynfield_offset = -1;
 158
 159 /*
 160  * max_num_kflows must be >= 32
 161  * and must be a power-of-2 supported value
 162  * return: 1 -> invalid
 163  *         0 -> valid
 164  */
 165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 166 {
 167         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 168                 return 1;
 169         return 0;
 170 }
 171
 172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 178 static void bnxt_dev_recover(void *arg);
 179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 180 static void bnxt_free_rep_info(struct bnxt *bp);
 181
 182 int is_bnxt_in_error(struct bnxt *bp)
 183 {
 184         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 185                 return -EIO;
 186         if (bp->flags & BNXT_FLAG_FW_RESET)
 187                 return -EBUSY;
 188
 189         return 0;
 190 }
 191
 192 /***********************/
 193
 194 /*
 195  * High level utility functions
 196  */
 197
 198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 199 {
 200         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 201                                              BNXT_RSS_TBL_SIZE_P5);
 202
 203         if (!BNXT_CHIP_P5(bp))
 204                 return 1;
 205
 206         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 207                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 208                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 209 }
 210
 211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 212 {
 213         if (!BNXT_CHIP_P5(bp))
 214                 return HW_HASH_INDEX_SIZE;
 215
 216         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 217 }
 218
 219 static void bnxt_free_parent_info(struct bnxt *bp)
 220 {
 221         rte_free(bp->parent);
 222         bp->parent = NULL;
 223 }
 224
 225 static void bnxt_free_pf_info(struct bnxt *bp)
 226 {
 227         rte_free(bp->pf);
 228         bp->pf = NULL;
 229 }
 230
 231 static void bnxt_free_link_info(struct bnxt *bp)
 232 {
 233         rte_free(bp->link_info);
 234         bp->link_info = NULL;
 235 }
 236
 237 static void bnxt_free_leds_info(struct bnxt *bp)
 238 {
 239         if (BNXT_VF(bp))
 240                 return;
 241
 242         rte_free(bp->leds);
 243         bp->leds = NULL;
 244 }
 245
 246 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 247 {
 248         rte_free(bp->flow_stat);
 249         bp->flow_stat = NULL;
 250 }
 251
 252 static void bnxt_free_cos_queues(struct bnxt *bp)
 253 {
 254         rte_free(bp->rx_cos_queue);
 255         bp->rx_cos_queue = NULL;
 256         rte_free(bp->tx_cos_queue);
 257         bp->tx_cos_queue = NULL;
 258 }
 259
 260 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 261 {
 262         bnxt_free_filter_mem(bp);
 263         bnxt_free_vnic_attributes(bp);
 264         bnxt_free_vnic_mem(bp);
 265
 266         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 267          * If the number of rings change across fw update,
 268          * we don't have much choice except to warn the user.
 269          */
 270         if (!reconfig) {
 271                 bnxt_free_stats(bp);
 272                 bnxt_free_tx_rings(bp);
 273                 bnxt_free_rx_rings(bp);
 274         }
 275         bnxt_free_async_cp_ring(bp);
 276         bnxt_free_rxtx_nq_ring(bp);
 277
 278         rte_free(bp->grp_info);
 279         bp->grp_info = NULL;
 280 }
 281
 282 static int bnxt_alloc_parent_info(struct bnxt *bp)
 283 {
 284         bp->parent = rte_zmalloc("bnxt_parent_info",
 285                                  sizeof(struct bnxt_parent_info), 0);
 286         if (bp->parent == NULL)
 287                 return -ENOMEM;
 288
 289         return 0;
 290 }
 291
 292 static int bnxt_alloc_pf_info(struct bnxt *bp)
 293 {
 294         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 295         if (bp->pf == NULL)
 296                 return -ENOMEM;
 297
 298         return 0;
 299 }
 300
 301 static int bnxt_alloc_link_info(struct bnxt *bp)
 302 {
 303         bp->link_info =
 304                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 305         if (bp->link_info == NULL)
 306                 return -ENOMEM;
 307
 308         return 0;
 309 }
 310
 311 static int bnxt_alloc_leds_info(struct bnxt *bp)
 312 {
 313         if (BNXT_VF(bp))
 314                 return 0;
 315
 316         bp->leds = rte_zmalloc("bnxt_leds",
 317                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 318                                0);
 319         if (bp->leds == NULL)
 320                 return -ENOMEM;
 321
 322         return 0;
 323 }
 324
 325 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 326 {
 327         bp->rx_cos_queue =
 328                 rte_zmalloc("bnxt_rx_cosq",
 329                             BNXT_COS_QUEUE_COUNT *
 330                             sizeof(struct bnxt_cos_queue_info),
 331                             0);
 332         if (bp->rx_cos_queue == NULL)
 333                 return -ENOMEM;
 334
 335         bp->tx_cos_queue =
 336                 rte_zmalloc("bnxt_tx_cosq",
 337                             BNXT_COS_QUEUE_COUNT *
 338                             sizeof(struct bnxt_cos_queue_info),
 339                             0);
 340         if (bp->tx_cos_queue == NULL)
 341                 return -ENOMEM;
 342
 343         return 0;
 344 }
 345
 346 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 347 {
 348         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 349                                     sizeof(struct bnxt_flow_stat_info), 0);
 350         if (bp->flow_stat == NULL)
 351                 return -ENOMEM;
 352
 353         return 0;
 354 }
 355
 356 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 357 {
 358         int rc;
 359
 360         rc = bnxt_alloc_ring_grps(bp);
 361         if (rc)
 362                 goto alloc_mem_err;
 363
 364         rc = bnxt_alloc_async_ring_struct(bp);
 365         if (rc)
 366                 goto alloc_mem_err;
 367
 368         rc = bnxt_alloc_vnic_mem(bp);
 369         if (rc)
 370                 goto alloc_mem_err;
 371
 372         rc = bnxt_alloc_vnic_attributes(bp);
 373         if (rc)
 374                 goto alloc_mem_err;
 375
 376         rc = bnxt_alloc_filter_mem(bp);
 377         if (rc)
 378                 goto alloc_mem_err;
 379
 380         rc = bnxt_alloc_async_cp_ring(bp);
 381         if (rc)
 382                 goto alloc_mem_err;
 383
 384         rc = bnxt_alloc_rxtx_nq_ring(bp);
 385         if (rc)
 386                 goto alloc_mem_err;
 387
 388         if (BNXT_FLOW_XSTATS_EN(bp)) {
 389                 rc = bnxt_alloc_flow_stats_info(bp);
 390                 if (rc)
 391                         goto alloc_mem_err;
 392         }
 393
 394         return 0;
 395
 396 alloc_mem_err:
 397         bnxt_free_mem(bp, reconfig);
 398         return rc;
 399 }
 400
 401 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 402 {
 403         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 404         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 405         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 406         struct bnxt_rx_queue *rxq;
 407         unsigned int j;
 408         int rc;
 409
 410         rc = bnxt_vnic_grp_alloc(bp, vnic);
 411         if (rc)
 412                 goto err_out;
 413
 414         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 415                     vnic_id, vnic, vnic->fw_grp_ids);
 416
 417         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 418         if (rc)
 419                 goto err_out;
 420
 421         /* Alloc RSS context only if RSS mode is enabled */
 422         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 423                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 424
 425                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 426                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 427                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 428                         PMD_DRV_LOG(ERR,
 429                                     "Only queues 0-%d will be in RSS table\n",
 430                                     BNXT_RSS_TBL_SIZE_P5 - 1);
 431                 }
 432
 433                 rc = 0;
 434                 for (j = 0; j < nr_ctxs; j++) {
 435                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 436                         if (rc)
 437                                 break;
 438                 }
 439                 if (rc) {
 440                         PMD_DRV_LOG(ERR,
 441                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 442                                     vnic_id, j, rc);
 443                         goto err_out;
 444                 }
 445                 vnic->num_lb_ctxts = nr_ctxs;
 446         }
 447
 448         /*
 449          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 450          * setting is not available at this time, it will not be
 451          * configured correctly in the CFA.
 452          */
 453         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 454                 vnic->vlan_strip = true;
 455         else
 456                 vnic->vlan_strip = false;
 457
 458         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 459         if (rc)
 460                 goto err_out;
 461
 462         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 463         if (rc)
 464                 goto err_out;
 465
 466         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 467                 rxq = bp->eth_dev->data->rx_queues[j];
 468
 469                 PMD_DRV_LOG(DEBUG,
 470                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 471                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 472
 473                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 474                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 475                 else
 476                         vnic->rx_queue_cnt++;
 477         }
 478
 479         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 480
 481         rc = bnxt_vnic_rss_configure(bp, vnic);
 482         if (rc)
 483                 goto err_out;
 484
 485         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 486
 487         rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
 488                                     (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) ?
 489                                     true : false);
 490         if (rc)
 491                 goto err_out;
 492
 493         return 0;
 494 err_out:
 495         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 496                     vnic_id, rc);
 497         return rc;
 498 }
 499
 500 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 501 {
 502         int rc = 0;
 503
 504         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 505                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 506         if (rc)
 507                 return rc;
 508
 509         PMD_DRV_LOG(DEBUG,
 510                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 511                     " rx_fc_in_tbl.ctx_id = %d\n",
 512                     bp->flow_stat->rx_fc_in_tbl.va,
 513                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 514                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 515
 516         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 517                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 518         if (rc)
 519                 return rc;
 520
 521         PMD_DRV_LOG(DEBUG,
 522                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 523                     " rx_fc_out_tbl.ctx_id = %d\n",
 524                     bp->flow_stat->rx_fc_out_tbl.va,
 525                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 526                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 527
 528         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 529                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 530         if (rc)
 531                 return rc;
 532
 533         PMD_DRV_LOG(DEBUG,
 534                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 535                     " tx_fc_in_tbl.ctx_id = %d\n",
 536                     bp->flow_stat->tx_fc_in_tbl.va,
 537                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 538                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 539
 540         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 541                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 542         if (rc)
 543                 return rc;
 544
 545         PMD_DRV_LOG(DEBUG,
 546                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 547                     " tx_fc_out_tbl.ctx_id = %d\n",
 548                     bp->flow_stat->tx_fc_out_tbl.va,
 549                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 550                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 551
 552         memset(bp->flow_stat->rx_fc_out_tbl.va,
 553                0,
 554                bp->flow_stat->rx_fc_out_tbl.size);
 555         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 556                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 557                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 558                                        bp->flow_stat->max_fc,
 559                                        true);
 560         if (rc)
 561                 return rc;
 562
 563         memset(bp->flow_stat->tx_fc_out_tbl.va,
 564                0,
 565                bp->flow_stat->tx_fc_out_tbl.size);
 566         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 567                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 568                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 569                                        bp->flow_stat->max_fc,
 570                                        true);
 571
 572         return rc;
 573 }
 574
 575 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 576                                   struct bnxt_ctx_mem_buf_info *ctx)
 577 {
 578         if (!ctx)
 579                 return -EINVAL;
 580
 581         ctx->va = rte_zmalloc(type, size, 0);
 582         if (ctx->va == NULL)
 583                 return -ENOMEM;
 584         rte_mem_lock_page(ctx->va);
 585         ctx->size = size;
 586         ctx->dma = rte_mem_virt2iova(ctx->va);
 587         if (ctx->dma == RTE_BAD_IOVA)
 588                 return -ENOMEM;
 589
 590         return 0;
 591 }
 592
 593 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 594 {
 595         struct rte_pci_device *pdev = bp->pdev;
 596         char type[RTE_MEMZONE_NAMESIZE];
 597         uint16_t max_fc;
 598         int rc = 0;
 599
 600         max_fc = bp->flow_stat->max_fc;
 601
 602         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 603                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 604         /* 4 bytes for each counter-id */
 605         rc = bnxt_alloc_ctx_mem_buf(type,
 606                                     max_fc * 4,
 607                                     &bp->flow_stat->rx_fc_in_tbl);
 608         if (rc)
 609                 return rc;
 610
 611         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 612                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 613         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 614         rc = bnxt_alloc_ctx_mem_buf(type,
 615                                     max_fc * 16,
 616                                     &bp->flow_stat->rx_fc_out_tbl);
 617         if (rc)
 618                 return rc;
 619
 620         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 621                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 622         /* 4 bytes for each counter-id */
 623         rc = bnxt_alloc_ctx_mem_buf(type,
 624                                     max_fc * 4,
 625                                     &bp->flow_stat->tx_fc_in_tbl);
 626         if (rc)
 627                 return rc;
 628
 629         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 630                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 631         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 632         rc = bnxt_alloc_ctx_mem_buf(type,
 633                                     max_fc * 16,
 634                                     &bp->flow_stat->tx_fc_out_tbl);
 635         if (rc)
 636                 return rc;
 637
 638         rc = bnxt_register_fc_ctx_mem(bp);
 639
 640         return rc;
 641 }
 642
 643 static int bnxt_init_ctx_mem(struct bnxt *bp)
 644 {
 645         int rc = 0;
 646
 647         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 648             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 649             !BNXT_FLOW_XSTATS_EN(bp))
 650                 return 0;
 651
 652         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 653         if (rc)
 654                 return rc;
 655
 656         rc = bnxt_init_fc_ctx_mem(bp);
 657
 658         return rc;
 659 }
 660
 661 static int bnxt_update_phy_setting(struct bnxt *bp)
 662 {
 663         struct rte_eth_link new;
 664         int rc;
 665
 666         rc = bnxt_get_hwrm_link_config(bp, &new);
 667         if (rc) {
 668                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 669                 return rc;
 670         }
 671
 672         /*
 673          * On BCM957508-N2100 adapters, FW will not allow any user other
 674          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 675          * always returns link up. Force phy update always in that case.
 676          */
 677         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 678                 rc = bnxt_set_hwrm_link_config(bp, true);
 679                 if (rc) {
 680                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 681                         return rc;
 682                 }
 683         }
 684
 685         return rc;
 686 }
 687
 688 static int bnxt_start_nic(struct bnxt *bp)
 689 {
 690         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 691         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 692         uint32_t intr_vector = 0;
 693         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 694         uint32_t vec = BNXT_MISC_VEC_ID;
 695         unsigned int i, j;
 696         int rc;
 697
 698         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 699                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 700                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 701                 bp->flags |= BNXT_FLAG_JUMBO;
 702         } else {
 703                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 704                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 705                 bp->flags &= ~BNXT_FLAG_JUMBO;
 706         }
 707
 708         /* THOR does not support ring groups.
 709          * But we will use the array to save RSS context IDs.
 710          */
 711         if (BNXT_CHIP_P5(bp))
 712                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 713
 714         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 715         if (rc) {
 716                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 717                 goto err_out;
 718         }
 719
 720         rc = bnxt_alloc_hwrm_rings(bp);
 721         if (rc) {
 722                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 723                 goto err_out;
 724         }
 725
 726         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 727         if (rc) {
 728                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 729                 goto err_out;
 730         }
 731
 732         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 733                 goto skip_cosq_cfg;
 734
 735         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 736                 if (bp->rx_cos_queue[i].id != 0xff) {
 737                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 738
 739                         if (!vnic) {
 740                                 PMD_DRV_LOG(ERR,
 741                                             "Num pools more than FW profile\n");
 742                                 rc = -EINVAL;
 743                                 goto err_out;
 744                         }
 745                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 746                         bp->rx_cosq_cnt++;
 747                 }
 748         }
 749
 750 skip_cosq_cfg:
 751         rc = bnxt_mq_rx_configure(bp);
 752         if (rc) {
 753                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 754                 goto err_out;
 755         }
 756
 757         /* default vnic 0 */
 758         rc = bnxt_setup_one_vnic(bp, 0);
 759         if (rc)
 760                 goto err_out;
 761         /* VNIC configuration */
 762         if (BNXT_RFS_NEEDS_VNIC(bp)) {
 763                 for (i = 1; i < bp->nr_vnics; i++) {
 764                         rc = bnxt_setup_one_vnic(bp, i);
 765                         if (rc)
 766                                 goto err_out;
 767                 }
 768         }
 769
 770         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 771         if (rc) {
 772                 PMD_DRV_LOG(ERR,
 773                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 774                 goto err_out;
 775         }
 776
 777         /* check and configure queue intr-vector mapping */
 778         if ((rte_intr_cap_multiple(intr_handle) ||
 779              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 780             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 781                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 782                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 783                 if (intr_vector > bp->rx_cp_nr_rings) {
 784                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 785                                         bp->rx_cp_nr_rings);
 786                         return -ENOTSUP;
 787                 }
 788                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 789                 if (rc)
 790                         return rc;
 791         }
 792
 793         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 794                 intr_handle->intr_vec =
 795                         rte_zmalloc("intr_vec",
 796                                     bp->eth_dev->data->nb_rx_queues *
 797                                     sizeof(int), 0);
 798                 if (intr_handle->intr_vec == NULL) {
 799                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 800                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 801                         rc = -ENOMEM;
 802                         goto err_out;
 803                 }
 804                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 805                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 806                          intr_handle->intr_vec, intr_handle->nb_efd,
 807                         intr_handle->max_intr);
 808                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 809                      queue_id++) {
 810                         intr_handle->intr_vec[queue_id] =
 811                                                         vec + BNXT_RX_VEC_START;
 812                         if (vec < base + intr_handle->nb_efd - 1)
 813                                 vec++;
 814                 }
 815         }
 816
 817         /* enable uio/vfio intr/eventfd mapping */
 818         rc = rte_intr_enable(intr_handle);
 819 #ifndef RTE_EXEC_ENV_FREEBSD
 820         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 821         if (rc)
 822                 goto err_out;
 823 #endif
 824
 825         rc = bnxt_update_phy_setting(bp);
 826         if (rc)
 827                 goto err_out;
 828
 829         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 830         if (!bp->mark_table)
 831                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 832
 833         return 0;
 834
 835 err_out:
 836         /* Some of the error status returned by FW may not be from errno.h */
 837         if (rc > 0)
 838                 rc = -EIO;
 839
 840         return rc;
 841 }
 842
 843 static int bnxt_shutdown_nic(struct bnxt *bp)
 844 {
 845         bnxt_free_all_hwrm_resources(bp);
 846         bnxt_free_all_filters(bp);
 847         bnxt_free_all_vnics(bp);
 848         return 0;
 849 }
 850
 851 /*
 852  * Device configuration and status function
 853  */
 854
 855 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 856 {
 857         uint32_t link_speed = 0;
 858         uint32_t speed_capa = 0;
 859
 860         if (bp->link_info == NULL)
 861                 return 0;
 862
 863         link_speed = bp->link_info->support_speeds;
 864
 865         /* If PAM4 is configured, use PAM4 supported speed */
 866         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 867                 link_speed = bp->link_info->support_pam4_speeds;
 868
 869         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 870                 speed_capa |= ETH_LINK_SPEED_100M;
 871         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 872                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 873         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 874                 speed_capa |= ETH_LINK_SPEED_1G;
 875         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 876                 speed_capa |= ETH_LINK_SPEED_2_5G;
 877         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 878                 speed_capa |= ETH_LINK_SPEED_10G;
 879         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 880                 speed_capa |= ETH_LINK_SPEED_20G;
 881         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 882                 speed_capa |= ETH_LINK_SPEED_25G;
 883         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 884                 speed_capa |= ETH_LINK_SPEED_40G;
 885         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 886                 speed_capa |= ETH_LINK_SPEED_50G;
 887         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 888                 speed_capa |= ETH_LINK_SPEED_100G;
 889         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 890                 speed_capa |= ETH_LINK_SPEED_50G;
 891         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 892                 speed_capa |= ETH_LINK_SPEED_100G;
 893         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 894                 speed_capa |= ETH_LINK_SPEED_200G;
 895
 896         if (bp->link_info->auto_mode ==
 897             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 898                 speed_capa |= ETH_LINK_SPEED_FIXED;
 899
 900         return speed_capa;
 901 }
 902
 903 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 904                                 struct rte_eth_dev_info *dev_info)
 905 {
 906         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 907         struct bnxt *bp = eth_dev->data->dev_private;
 908         uint16_t max_vnics, i, j, vpool, vrxq;
 909         unsigned int max_rx_rings;
 910         int rc;
 911
 912         rc = is_bnxt_in_error(bp);
 913         if (rc)
 914                 return rc;
 915
 916         /* MAC Specifics */
 917         dev_info->max_mac_addrs = bp->max_l2_ctx;
 918         dev_info->max_hash_mac_addrs = 0;
 919
 920         /* PF/VF specifics */
 921         if (BNXT_PF(bp))
 922                 dev_info->max_vfs = pdev->max_vfs;
 923
 924         max_rx_rings = bnxt_max_rings(bp);
 925         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 926         dev_info->max_rx_queues = max_rx_rings;
 927         dev_info->max_tx_queues = max_rx_rings;
 928         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 929         dev_info->hash_key_size = 40;
 930         max_vnics = bp->max_vnics;
 931
 932         /* MTU specifics */
 933         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 934         dev_info->max_mtu = BNXT_MAX_MTU;
 935
 936         /* Fast path specifics */
 937         dev_info->min_rx_bufsize = 1;
 938         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 939
 940         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 941         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 942                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 943         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 944         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 945                                     dev_info->tx_queue_offload_capa;
 946         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 947
 948         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 949
 950         /* *INDENT-OFF* */
 951         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 952                 .rx_thresh = {
 953                         .pthresh = 8,
 954                         .hthresh = 8,
 955                         .wthresh = 0,
 956                 },
 957                 .rx_free_thresh = 32,
 958                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 959         };
 960
 961         dev_info->default_txconf = (struct rte_eth_txconf) {
 962                 .tx_thresh = {
 963                         .pthresh = 32,
 964                         .hthresh = 0,
 965                         .wthresh = 0,
 966                 },
 967                 .tx_free_thresh = 32,
 968                 .tx_rs_thresh = 32,
 969         };
 970         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 971
 972         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 973         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 974         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 975         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 976         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 977
 978         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 979                 dev_info->switch_info.name = eth_dev->device->name;
 980                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 981                 dev_info->switch_info.port_id =
 982                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 983                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 984         }
 985
 986         /* *INDENT-ON* */
 987
 988         /*
 989          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 990          *       need further investigation.
 991          */
 992
 993         /* VMDq resources */
 994         vpool = 64; /* ETH_64_POOLS */
 995         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 996         for (i = 0; i < 4; vpool >>= 1, i++) {
 997                 if (max_vnics > vpool) {
 998                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 999                                 if (dev_info->max_rx_queues > vrxq) {
1000                                         if (vpool > vrxq)
1001                                                 vpool = vrxq;
1002                                         goto found;
1003                                 }
1004                         }
1005                         /* Not enough resources to support VMDq */
1006                         break;
1007                 }
1008         }
1009         /* Not enough resources to support VMDq */
1010         vpool = 0;
1011         vrxq = 0;
1012 found:
1013         dev_info->max_vmdq_pools = vpool;
1014         dev_info->vmdq_queue_num = vrxq;
1015
1016         dev_info->vmdq_pool_base = 0;
1017         dev_info->vmdq_queue_base = 0;
1018
1019         return 0;
1020 }
1021
1022 /* Configure the device based on the configuration provided */
1023 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1024 {
1025         struct bnxt *bp = eth_dev->data->dev_private;
1026         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1027         int rc;
1028
1029         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1030         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1031         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1032         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1033
1034         rc = is_bnxt_in_error(bp);
1035         if (rc)
1036                 return rc;
1037
1038         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1039                 rc = bnxt_hwrm_check_vf_rings(bp);
1040                 if (rc) {
1041                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1042                         return -ENOSPC;
1043                 }
1044
1045                 /* If a resource has already been allocated - in this case
1046                  * it is the async completion ring, free it. Reallocate it after
1047                  * resource reservation. This will ensure the resource counts
1048                  * are calculated correctly.
1049                  */
1050
1051                 pthread_mutex_lock(&bp->def_cp_lock);
1052
1053                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1054                         bnxt_disable_int(bp);
1055                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1056                 }
1057
1058                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1059                 if (rc) {
1060                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1061                         pthread_mutex_unlock(&bp->def_cp_lock);
1062                         return -ENOSPC;
1063                 }
1064
1065                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1066                         rc = bnxt_alloc_async_cp_ring(bp);
1067                         if (rc) {
1068                                 pthread_mutex_unlock(&bp->def_cp_lock);
1069                                 return rc;
1070                         }
1071                         bnxt_enable_int(bp);
1072                 }
1073
1074                 pthread_mutex_unlock(&bp->def_cp_lock);
1075         }
1076
1077         /* Inherit new configurations */
1078         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1079             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1080             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1081                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1082             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1083             bp->max_stat_ctx)
1084                 goto resource_error;
1085
1086         if (BNXT_HAS_RING_GRPS(bp) &&
1087             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1088                 goto resource_error;
1089
1090         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1091             bp->max_vnics < eth_dev->data->nb_rx_queues)
1092                 goto resource_error;
1093
1094         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1095         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1096
1097         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1098                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1099         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1100
1101         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1102                 eth_dev->data->mtu =
1103                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1104                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1105                         BNXT_NUM_VLANS;
1106                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1107         }
1108         return 0;
1109
1110 resource_error:
1111         PMD_DRV_LOG(ERR,
1112                     "Insufficient resources to support requested config\n");
1113         PMD_DRV_LOG(ERR,
1114                     "Num Queues Requested: Tx %d, Rx %d\n",
1115                     eth_dev->data->nb_tx_queues,
1116                     eth_dev->data->nb_rx_queues);
1117         PMD_DRV_LOG(ERR,
1118                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1119                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1120                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1121         return -ENOSPC;
1122 }
1123
1124 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1125 {
1126         struct rte_eth_link *link = &eth_dev->data->dev_link;
1127
1128         if (link->link_status)
1129                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1130                         eth_dev->data->port_id,
1131                         (uint32_t)link->link_speed,
1132                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1133                         ("full-duplex") : ("half-duplex\n"));
1134         else
1135                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1136                         eth_dev->data->port_id);
1137 }
1138
1139 /*
1140  * Determine whether the current configuration requires support for scattered
1141  * receive; return 1 if scattered receive is required and 0 if not.
1142  */
1143 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1144 {
1145         uint16_t buf_size;
1146         int i;
1147
1148         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1149                 return 1;
1150
1151         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1152                 return 1;
1153
1154         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1155                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1156
1157                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1158                                       RTE_PKTMBUF_HEADROOM);
1159                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1160                         return 1;
1161         }
1162         return 0;
1163 }
1164
1165 static eth_rx_burst_t
1166 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1167 {
1168         struct bnxt *bp = eth_dev->data->dev_private;
1169
1170         /* Disable vector mode RX for Stingray2 for now */
1171         if (BNXT_CHIP_SR2(bp)) {
1172                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1173                 return bnxt_recv_pkts;
1174         }
1175
1176 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1177 #ifndef RTE_LIBRTE_IEEE1588
1178         /*
1179          * Vector mode receive can be enabled only if scatter rx is not
1180          * in use and rx offloads are limited to VLAN stripping and
1181          * CRC stripping.
1182          */
1183         if (!eth_dev->data->scattered_rx &&
1184             !(eth_dev->data->dev_conf.rxmode.offloads &
1185               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1186                 DEV_RX_OFFLOAD_KEEP_CRC |
1187                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1188                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1189                 DEV_RX_OFFLOAD_UDP_CKSUM |
1190                 DEV_RX_OFFLOAD_TCP_CKSUM |
1191                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1192                 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1193                 DEV_RX_OFFLOAD_RSS_HASH |
1194                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1195             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1196             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1197                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1198                             eth_dev->data->port_id);
1199                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1200                 return bnxt_recv_pkts_vec;
1201         }
1202         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1203                     eth_dev->data->port_id);
1204         PMD_DRV_LOG(INFO,
1205                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1206                     eth_dev->data->port_id,
1207                     eth_dev->data->scattered_rx,
1208                     eth_dev->data->dev_conf.rxmode.offloads);
1209 #endif
1210 #endif
1211         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1212         return bnxt_recv_pkts;
1213 }
1214
1215 static eth_tx_burst_t
1216 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1217 {
1218         struct bnxt *bp = eth_dev->data->dev_private;
1219
1220         /* Disable vector mode TX for Stingray2 for now */
1221         if (BNXT_CHIP_SR2(bp))
1222                 return bnxt_xmit_pkts;
1223
1224 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1225 #ifndef RTE_LIBRTE_IEEE1588
1226         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1227
1228         /*
1229          * Vector mode transmit can be enabled only if not using scatter rx
1230          * or tx offloads.
1231          */
1232         if (!eth_dev->data->scattered_rx &&
1233             !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1234             !BNXT_TRUFLOW_EN(bp) &&
1235             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1236                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1237                             eth_dev->data->port_id);
1238                 return bnxt_xmit_pkts_vec;
1239         }
1240         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1241                     eth_dev->data->port_id);
1242         PMD_DRV_LOG(INFO,
1243                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1244                     eth_dev->data->port_id,
1245                     eth_dev->data->scattered_rx,
1246                     offloads);
1247 #endif
1248 #endif
1249         return bnxt_xmit_pkts;
1250 }
1251
1252 static int bnxt_handle_if_change_status(struct bnxt *bp)
1253 {
1254         int rc;
1255
1256         /* Since fw has undergone a reset and lost all contexts,
1257          * set fatal flag to not issue hwrm during cleanup
1258          */
1259         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1260         bnxt_uninit_resources(bp, true);
1261
1262         /* clear fatal flag so that re-init happens */
1263         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1264         rc = bnxt_init_resources(bp, true);
1265
1266         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1267
1268         return rc;
1269 }
1270
1271 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1272 {
1273         struct bnxt *bp = eth_dev->data->dev_private;
1274         int rc = 0;
1275
1276         if (!BNXT_SINGLE_PF(bp))
1277                 return -ENOTSUP;
1278
1279         if (!bp->link_info->link_up)
1280                 rc = bnxt_set_hwrm_link_config(bp, true);
1281         if (!rc)
1282                 eth_dev->data->dev_link.link_status = 1;
1283
1284         bnxt_print_link_info(eth_dev);
1285         return rc;
1286 }
1287
1288 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1289 {
1290         struct bnxt *bp = eth_dev->data->dev_private;
1291
1292         if (!BNXT_SINGLE_PF(bp))
1293                 return -ENOTSUP;
1294
1295         eth_dev->data->dev_link.link_status = 0;
1296         bnxt_set_hwrm_link_config(bp, false);
1297         bp->link_info->link_up = 0;
1298
1299         return 0;
1300 }
1301
1302 static void bnxt_free_switch_domain(struct bnxt *bp)
1303 {
1304         int rc = 0;
1305
1306         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1307                 return;
1308
1309         rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1310         if (rc)
1311                 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1312                             bp->switch_domain_id, rc);
1313 }
1314
1315 static void bnxt_ptp_get_current_time(void *arg)
1316 {
1317         struct bnxt *bp = arg;
1318         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1319         int rc;
1320
1321         rc = is_bnxt_in_error(bp);
1322         if (rc)
1323                 return;
1324
1325         if (!ptp)
1326                 return;
1327
1328         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1329                                 &ptp->current_time);
1330
1331         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1332         if (rc != 0) {
1333                 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1334                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1335         }
1336 }
1337
1338 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1339 {
1340         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1341         int rc;
1342
1343         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1344                 return 0;
1345
1346         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1347                                 &ptp->current_time);
1348
1349         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1350         return rc;
1351 }
1352
1353 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1354 {
1355         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1356                 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1357                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1358         }
1359 }
1360
1361 static void bnxt_ptp_stop(struct bnxt *bp)
1362 {
1363         bnxt_cancel_ptp_alarm(bp);
1364         bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1365 }
1366
1367 static int bnxt_ptp_start(struct bnxt *bp)
1368 {
1369         int rc;
1370
1371         rc = bnxt_schedule_ptp_alarm(bp);
1372         if (rc != 0) {
1373                 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1374         } else {
1375                 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1376                 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1377         }
1378
1379         return rc;
1380 }
1381
1382 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1383 {
1384         struct bnxt *bp = eth_dev->data->dev_private;
1385         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1386         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1387         struct rte_eth_link link;
1388         int ret;
1389
1390         eth_dev->data->dev_started = 0;
1391         eth_dev->data->scattered_rx = 0;
1392
1393         /* Prevent crashes when queues are still in use */
1394         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1395         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1396
1397         bnxt_disable_int(bp);
1398
1399         /* disable uio/vfio intr/eventfd mapping */
1400         rte_intr_disable(intr_handle);
1401
1402         /* Stop the child representors for this device */
1403         ret = bnxt_rep_stop_all(bp);
1404         if (ret != 0)
1405                 return ret;
1406
1407         /* delete the bnxt ULP port details */
1408         bnxt_ulp_port_deinit(bp);
1409
1410         bnxt_cancel_fw_health_check(bp);
1411
1412         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1413                 bnxt_cancel_ptp_alarm(bp);
1414
1415         /* Do not bring link down during reset recovery */
1416         if (!is_bnxt_in_error(bp)) {
1417                 bnxt_dev_set_link_down_op(eth_dev);
1418                 /* Wait for link to be reset */
1419                 if (BNXT_SINGLE_PF(bp))
1420                         rte_delay_ms(500);
1421                 /* clear the recorded link status */
1422                 memset(&link, 0, sizeof(link));
1423                 rte_eth_linkstatus_set(eth_dev, &link);
1424         }
1425
1426         /* Clean queue intr-vector mapping */
1427         rte_intr_efd_disable(intr_handle);
1428         if (intr_handle->intr_vec != NULL) {
1429                 rte_free(intr_handle->intr_vec);
1430                 intr_handle->intr_vec = NULL;
1431         }
1432
1433         bnxt_hwrm_port_clr_stats(bp);
1434         bnxt_free_tx_mbufs(bp);
1435         bnxt_free_rx_mbufs(bp);
1436         /* Process any remaining notifications in default completion queue */
1437         bnxt_int_handler(eth_dev);
1438         bnxt_shutdown_nic(bp);
1439         bnxt_hwrm_if_change(bp, false);
1440
1441         rte_free(bp->mark_table);
1442         bp->mark_table = NULL;
1443
1444         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1445         bp->rx_cosq_cnt = 0;
1446         /* All filters are deleted on a port stop. */
1447         if (BNXT_FLOW_XSTATS_EN(bp))
1448                 bp->flow_stat->flow_count = 0;
1449
1450         return 0;
1451 }
1452
1453 /* Unload the driver, release resources */
1454 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1455 {
1456         struct bnxt *bp = eth_dev->data->dev_private;
1457
1458         pthread_mutex_lock(&bp->err_recovery_lock);
1459         if (bp->flags & BNXT_FLAG_FW_RESET) {
1460                 PMD_DRV_LOG(ERR,
1461                             "Adapter recovering from error..Please retry\n");
1462                 pthread_mutex_unlock(&bp->err_recovery_lock);
1463                 return -EAGAIN;
1464         }
1465         pthread_mutex_unlock(&bp->err_recovery_lock);
1466
1467         return bnxt_dev_stop(eth_dev);
1468 }
1469
1470 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1471 {
1472         struct bnxt *bp = eth_dev->data->dev_private;
1473         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1474         int vlan_mask = 0;
1475         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1476
1477         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1478                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1479                 return -EINVAL;
1480         }
1481
1482         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1483                 PMD_DRV_LOG(ERR,
1484                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1485                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1486
1487         do {
1488                 rc = bnxt_hwrm_if_change(bp, true);
1489                 if (rc == 0 || rc != -EAGAIN)
1490                         break;
1491
1492                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1493         } while (retry_cnt--);
1494
1495         if (rc)
1496                 return rc;
1497
1498         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1499                 rc = bnxt_handle_if_change_status(bp);
1500                 if (rc)
1501                         return rc;
1502         }
1503
1504         bnxt_enable_int(bp);
1505
1506         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1507
1508         rc = bnxt_start_nic(bp);
1509         if (rc)
1510                 goto error;
1511
1512         eth_dev->data->dev_started = 1;
1513
1514         bnxt_link_update_op(eth_dev, 1);
1515
1516         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1517                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1518         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1519                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1520         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1521         if (rc)
1522                 goto error;
1523
1524         /* Initialize bnxt ULP port details */
1525         rc = bnxt_ulp_port_init(bp);
1526         if (rc)
1527                 goto error;
1528
1529         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1530         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1531
1532         bnxt_schedule_fw_health_check(bp);
1533
1534         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1535                 bnxt_schedule_ptp_alarm(bp);
1536
1537         return 0;
1538
1539 error:
1540         bnxt_dev_stop(eth_dev);
1541         return rc;
1542 }
1543
1544 static void
1545 bnxt_uninit_locks(struct bnxt *bp)
1546 {
1547         pthread_mutex_destroy(&bp->flow_lock);
1548         pthread_mutex_destroy(&bp->def_cp_lock);
1549         pthread_mutex_destroy(&bp->health_check_lock);
1550         pthread_mutex_destroy(&bp->err_recovery_lock);
1551         if (bp->rep_info) {
1552                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1553                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1554         }
1555 }
1556
1557 static void bnxt_drv_uninit(struct bnxt *bp)
1558 {
1559         bnxt_free_leds_info(bp);
1560         bnxt_free_cos_queues(bp);
1561         bnxt_free_link_info(bp);
1562         bnxt_free_parent_info(bp);
1563         bnxt_uninit_locks(bp);
1564
1565         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1566         bp->tx_mem_zone = NULL;
1567         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1568         bp->rx_mem_zone = NULL;
1569
1570         bnxt_free_vf_info(bp);
1571         bnxt_free_pf_info(bp);
1572
1573         rte_free(bp->grp_info);
1574         bp->grp_info = NULL;
1575 }
1576
1577 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1578 {
1579         struct bnxt *bp = eth_dev->data->dev_private;
1580         int ret = 0;
1581
1582         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1583                 return 0;
1584
1585         pthread_mutex_lock(&bp->err_recovery_lock);
1586         if (bp->flags & BNXT_FLAG_FW_RESET) {
1587                 PMD_DRV_LOG(ERR,
1588                             "Adapter recovering from error...Please retry\n");
1589                 pthread_mutex_unlock(&bp->err_recovery_lock);
1590                 return -EAGAIN;
1591         }
1592         pthread_mutex_unlock(&bp->err_recovery_lock);
1593
1594         /* cancel the recovery handler before remove dev */
1595         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1596         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1597         bnxt_cancel_fc_thread(bp);
1598
1599         if (eth_dev->data->dev_started)
1600                 ret = bnxt_dev_stop(eth_dev);
1601
1602         bnxt_uninit_resources(bp, false);
1603
1604         bnxt_drv_uninit(bp);
1605
1606         return ret;
1607 }
1608
1609 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1610                                     uint32_t index)
1611 {
1612         struct bnxt *bp = eth_dev->data->dev_private;
1613         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1614         struct bnxt_vnic_info *vnic;
1615         struct bnxt_filter_info *filter, *temp_filter;
1616         uint32_t i;
1617
1618         if (is_bnxt_in_error(bp))
1619                 return;
1620
1621         /*
1622          * Loop through all VNICs from the specified filter flow pools to
1623          * remove the corresponding MAC addr filter
1624          */
1625         for (i = 0; i < bp->nr_vnics; i++) {
1626                 if (!(pool_mask & (1ULL << i)))
1627                         continue;
1628
1629                 vnic = &bp->vnic_info[i];
1630                 filter = STAILQ_FIRST(&vnic->filter);
1631                 while (filter) {
1632                         temp_filter = STAILQ_NEXT(filter, next);
1633                         if (filter->mac_index == index) {
1634                                 STAILQ_REMOVE(&vnic->filter, filter,
1635                                                 bnxt_filter_info, next);
1636                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1637                                 bnxt_free_filter(bp, filter);
1638                         }
1639                         filter = temp_filter;
1640                 }
1641         }
1642 }
1643
1644 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1645                                struct rte_ether_addr *mac_addr, uint32_t index,
1646                                uint32_t pool)
1647 {
1648         struct bnxt_filter_info *filter;
1649         int rc = 0;
1650
1651         /* Attach requested MAC address to the new l2_filter */
1652         STAILQ_FOREACH(filter, &vnic->filter, next) {
1653                 if (filter->mac_index == index) {
1654                         PMD_DRV_LOG(DEBUG,
1655                                     "MAC addr already existed for pool %d\n",
1656                                     pool);
1657                         return 0;
1658                 }
1659         }
1660
1661         filter = bnxt_alloc_filter(bp);
1662         if (!filter) {
1663                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1664                 return -ENODEV;
1665         }
1666
1667         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1668          * if the MAC that's been programmed now is a different one, then,
1669          * copy that addr to filter->l2_addr
1670          */
1671         if (mac_addr)
1672                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1673         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1674
1675         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1676         if (!rc) {
1677                 filter->mac_index = index;
1678                 if (filter->mac_index == 0)
1679                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1680                 else
1681                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1682         } else {
1683                 bnxt_free_filter(bp, filter);
1684         }
1685
1686         return rc;
1687 }
1688
1689 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1690                                 struct rte_ether_addr *mac_addr,
1691                                 uint32_t index, uint32_t pool)
1692 {
1693         struct bnxt *bp = eth_dev->data->dev_private;
1694         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1695         int rc = 0;
1696
1697         rc = is_bnxt_in_error(bp);
1698         if (rc)
1699                 return rc;
1700
1701         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1702                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1703                 return -ENOTSUP;
1704         }
1705
1706         if (!vnic) {
1707                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1708                 return -EINVAL;
1709         }
1710
1711         /* Filter settings will get applied when port is started */
1712         if (!eth_dev->data->dev_started)
1713                 return 0;
1714
1715         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1716
1717         return rc;
1718 }
1719
1720 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1721 {
1722         int rc = 0;
1723         struct bnxt *bp = eth_dev->data->dev_private;
1724         struct rte_eth_link new;
1725         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1726                         BNXT_MIN_LINK_WAIT_CNT;
1727
1728         rc = is_bnxt_in_error(bp);
1729         if (rc)
1730                 return rc;
1731
1732         memset(&new, 0, sizeof(new));
1733
1734         if (bp->link_info == NULL)
1735                 goto out;
1736
1737         do {
1738                 /* Retrieve link info from hardware */
1739                 rc = bnxt_get_hwrm_link_config(bp, &new);
1740                 if (rc) {
1741                         new.link_speed = ETH_LINK_SPEED_100M;
1742                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1743                         PMD_DRV_LOG(ERR,
1744                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1745                         goto out;
1746                 }
1747
1748                 if (!wait_to_complete || new.link_status)
1749                         break;
1750
1751                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1752         } while (cnt--);
1753
1754         /* Only single function PF can bring phy down.
1755          * When port is stopped, report link down for VF/MH/NPAR functions.
1756          */
1757         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1758                 memset(&new, 0, sizeof(new));
1759
1760 out:
1761         /* Timed out or success */
1762         if (new.link_status != eth_dev->data->dev_link.link_status ||
1763             new.link_speed != eth_dev->data->dev_link.link_speed) {
1764                 rte_eth_linkstatus_set(eth_dev, &new);
1765
1766                 rte_eth_dev_callback_process(eth_dev,
1767                                              RTE_ETH_EVENT_INTR_LSC,
1768                                              NULL);
1769
1770                 bnxt_print_link_info(eth_dev);
1771         }
1772
1773         return rc;
1774 }
1775
1776 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1777 {
1778         struct bnxt *bp = eth_dev->data->dev_private;
1779         struct bnxt_vnic_info *vnic;
1780         uint32_t old_flags;
1781         int rc;
1782
1783         rc = is_bnxt_in_error(bp);
1784         if (rc)
1785                 return rc;
1786
1787         /* Filter settings will get applied when port is started */
1788         if (!eth_dev->data->dev_started)
1789                 return 0;
1790
1791         if (bp->vnic_info == NULL)
1792                 return 0;
1793
1794         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1795
1796         old_flags = vnic->flags;
1797         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1798         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1799         if (rc != 0)
1800                 vnic->flags = old_flags;
1801
1802         return rc;
1803 }
1804
1805 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1806 {
1807         struct bnxt *bp = eth_dev->data->dev_private;
1808         struct bnxt_vnic_info *vnic;
1809         uint32_t old_flags;
1810         int rc;
1811
1812         rc = is_bnxt_in_error(bp);
1813         if (rc)
1814                 return rc;
1815
1816         /* Filter settings will get applied when port is started */
1817         if (!eth_dev->data->dev_started)
1818                 return 0;
1819
1820         if (bp->vnic_info == NULL)
1821                 return 0;
1822
1823         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1824
1825         old_flags = vnic->flags;
1826         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1827         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1828         if (rc != 0)
1829                 vnic->flags = old_flags;
1830
1831         return rc;
1832 }
1833
1834 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1835 {
1836         struct bnxt *bp = eth_dev->data->dev_private;
1837         struct bnxt_vnic_info *vnic;
1838         uint32_t old_flags;
1839         int rc;
1840
1841         rc = is_bnxt_in_error(bp);
1842         if (rc)
1843                 return rc;
1844
1845         /* Filter settings will get applied when port is started */
1846         if (!eth_dev->data->dev_started)
1847                 return 0;
1848
1849         if (bp->vnic_info == NULL)
1850                 return 0;
1851
1852         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1853
1854         old_flags = vnic->flags;
1855         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1856         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1857         if (rc != 0)
1858                 vnic->flags = old_flags;
1859
1860         return rc;
1861 }
1862
1863 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1864 {
1865         struct bnxt *bp = eth_dev->data->dev_private;
1866         struct bnxt_vnic_info *vnic;
1867         uint32_t old_flags;
1868         int rc;
1869
1870         rc = is_bnxt_in_error(bp);
1871         if (rc)
1872                 return rc;
1873
1874         /* Filter settings will get applied when port is started */
1875         if (!eth_dev->data->dev_started)
1876                 return 0;
1877
1878         if (bp->vnic_info == NULL)
1879                 return 0;
1880
1881         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1882
1883         old_flags = vnic->flags;
1884         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1885         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1886         if (rc != 0)
1887                 vnic->flags = old_flags;
1888
1889         return rc;
1890 }
1891
1892 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1893 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1894 {
1895         if (qid >= bp->rx_nr_rings)
1896                 return NULL;
1897
1898         return bp->eth_dev->data->rx_queues[qid];
1899 }
1900
1901 /* Return rxq corresponding to a given rss table ring/group ID. */
1902 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1903 {
1904         struct bnxt_rx_queue *rxq;
1905         unsigned int i;
1906
1907         if (!BNXT_HAS_RING_GRPS(bp)) {
1908                 for (i = 0; i < bp->rx_nr_rings; i++) {
1909                         rxq = bp->eth_dev->data->rx_queues[i];
1910                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1911                                 return rxq->index;
1912                 }
1913         } else {
1914                 for (i = 0; i < bp->rx_nr_rings; i++) {
1915                         if (bp->grp_info[i].fw_grp_id == fwr)
1916                                 return i;
1917                 }
1918         }
1919
1920         return INVALID_HW_RING_ID;
1921 }
1922
1923 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1924                             struct rte_eth_rss_reta_entry64 *reta_conf,
1925                             uint16_t reta_size)
1926 {
1927         struct bnxt *bp = eth_dev->data->dev_private;
1928         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1929         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1930         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1931         uint16_t idx, sft;
1932         int i, rc;
1933
1934         rc = is_bnxt_in_error(bp);
1935         if (rc)
1936                 return rc;
1937
1938         if (!vnic->rss_table)
1939                 return -EINVAL;
1940
1941         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1942                 return -EINVAL;
1943
1944         if (reta_size != tbl_size) {
1945                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1946                         "(%d) must equal the size supported by the hardware "
1947                         "(%d)\n", reta_size, tbl_size);
1948                 return -EINVAL;
1949         }
1950
1951         for (i = 0; i < reta_size; i++) {
1952                 struct bnxt_rx_queue *rxq;
1953
1954                 idx = i / RTE_RETA_GROUP_SIZE;
1955                 sft = i % RTE_RETA_GROUP_SIZE;
1956
1957                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1958                         continue;
1959
1960                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1961                 if (!rxq) {
1962                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1963                         return -EINVAL;
1964                 }
1965
1966                 if (BNXT_CHIP_P5(bp)) {
1967                         vnic->rss_table[i * 2] =
1968                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1969                         vnic->rss_table[i * 2 + 1] =
1970                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1971                 } else {
1972                         vnic->rss_table[i] =
1973                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1974                 }
1975         }
1976
1977         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1978         return rc;
1979 }
1980
1981 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1982                               struct rte_eth_rss_reta_entry64 *reta_conf,
1983                               uint16_t reta_size)
1984 {
1985         struct bnxt *bp = eth_dev->data->dev_private;
1986         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1987         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1988         uint16_t idx, sft, i;
1989         int rc;
1990
1991         rc = is_bnxt_in_error(bp);
1992         if (rc)
1993                 return rc;
1994
1995         /* Retrieve from the default VNIC */
1996         if (!vnic)
1997                 return -EINVAL;
1998         if (!vnic->rss_table)
1999                 return -EINVAL;
2000
2001         if (reta_size != tbl_size) {
2002                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2003                         "(%d) must equal the size supported by the hardware "
2004                         "(%d)\n", reta_size, tbl_size);
2005                 return -EINVAL;
2006         }
2007
2008         for (idx = 0, i = 0; i < reta_size; i++) {
2009                 idx = i / RTE_RETA_GROUP_SIZE;
2010                 sft = i % RTE_RETA_GROUP_SIZE;
2011
2012                 if (reta_conf[idx].mask & (1ULL << sft)) {
2013                         uint16_t qid;
2014
2015                         if (BNXT_CHIP_P5(bp))
2016                                 qid = bnxt_rss_to_qid(bp,
2017                                                       vnic->rss_table[i * 2]);
2018                         else
2019                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2020
2021                         if (qid == INVALID_HW_RING_ID) {
2022                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2023                                 return -EINVAL;
2024                         }
2025                         reta_conf[idx].reta[sft] = qid;
2026                 }
2027         }
2028
2029         return 0;
2030 }
2031
2032 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2033                                    struct rte_eth_rss_conf *rss_conf)
2034 {
2035         struct bnxt *bp = eth_dev->data->dev_private;
2036         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2037         struct bnxt_vnic_info *vnic;
2038         int rc;
2039
2040         rc = is_bnxt_in_error(bp);
2041         if (rc)
2042                 return rc;
2043
2044         /*
2045          * If RSS enablement were different than dev_configure,
2046          * then return -EINVAL
2047          */
2048         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2049                 if (!rss_conf->rss_hf)
2050                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
2051         } else {
2052                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2053                         return -EINVAL;
2054         }
2055
2056         bp->flags |= BNXT_FLAG_UPDATE_HASH;
2057         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
2058                rss_conf,
2059                sizeof(*rss_conf));
2060
2061         /* Update the default RSS VNIC(s) */
2062         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2063         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2064         vnic->hash_mode =
2065                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2066                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
2067
2068         /*
2069          * If hashkey is not specified, use the previously configured
2070          * hashkey
2071          */
2072         if (!rss_conf->rss_key)
2073                 goto rss_config;
2074
2075         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2076                 PMD_DRV_LOG(ERR,
2077                             "Invalid hashkey length, should be 16 bytes\n");
2078                 return -EINVAL;
2079         }
2080         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2081
2082 rss_config:
2083         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2084         return rc;
2085 }
2086
2087 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2088                                      struct rte_eth_rss_conf *rss_conf)
2089 {
2090         struct bnxt *bp = eth_dev->data->dev_private;
2091         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2092         int len, rc;
2093         uint32_t hash_types;
2094
2095         rc = is_bnxt_in_error(bp);
2096         if (rc)
2097                 return rc;
2098
2099         /* RSS configuration is the same for all VNICs */
2100         if (vnic && vnic->rss_hash_key) {
2101                 if (rss_conf->rss_key) {
2102                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2103                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2104                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2105                 }
2106
2107                 hash_types = vnic->hash_type;
2108                 rss_conf->rss_hf = 0;
2109                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2110                         rss_conf->rss_hf |= ETH_RSS_IPV4;
2111                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2112                 }
2113                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2114                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2115                         hash_types &=
2116                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2117                 }
2118                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2119                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2120                         hash_types &=
2121                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2122                 }
2123                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2124                         rss_conf->rss_hf |= ETH_RSS_IPV6;
2125                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2126                 }
2127                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2128                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2129                         hash_types &=
2130                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2131                 }
2132                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2133                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2134                         hash_types &=
2135                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2136                 }
2137
2138                 rss_conf->rss_hf |=
2139                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2140
2141                 if (hash_types) {
2142                         PMD_DRV_LOG(ERR,
2143                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2144                                 vnic->hash_type);
2145                         return -ENOTSUP;
2146                 }
2147         } else {
2148                 rss_conf->rss_hf = 0;
2149         }
2150         return 0;
2151 }
2152
2153 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2154                                struct rte_eth_fc_conf *fc_conf)
2155 {
2156         struct bnxt *bp = dev->data->dev_private;
2157         struct rte_eth_link link_info;
2158         int rc;
2159
2160         rc = is_bnxt_in_error(bp);
2161         if (rc)
2162                 return rc;
2163
2164         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2165         if (rc)
2166                 return rc;
2167
2168         memset(fc_conf, 0, sizeof(*fc_conf));
2169         if (bp->link_info->auto_pause)
2170                 fc_conf->autoneg = 1;
2171         switch (bp->link_info->pause) {
2172         case 0:
2173                 fc_conf->mode = RTE_FC_NONE;
2174                 break;
2175         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2176                 fc_conf->mode = RTE_FC_TX_PAUSE;
2177                 break;
2178         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2179                 fc_conf->mode = RTE_FC_RX_PAUSE;
2180                 break;
2181         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2182                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2183                 fc_conf->mode = RTE_FC_FULL;
2184                 break;
2185         }
2186         return 0;
2187 }
2188
2189 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2190                                struct rte_eth_fc_conf *fc_conf)
2191 {
2192         struct bnxt *bp = dev->data->dev_private;
2193         int rc;
2194
2195         rc = is_bnxt_in_error(bp);
2196         if (rc)
2197                 return rc;
2198
2199         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2200                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2201                 return -ENOTSUP;
2202         }
2203
2204         switch (fc_conf->mode) {
2205         case RTE_FC_NONE:
2206                 bp->link_info->auto_pause = 0;
2207                 bp->link_info->force_pause = 0;
2208                 break;
2209         case RTE_FC_RX_PAUSE:
2210                 if (fc_conf->autoneg) {
2211                         bp->link_info->auto_pause =
2212                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2213                         bp->link_info->force_pause = 0;
2214                 } else {
2215                         bp->link_info->auto_pause = 0;
2216                         bp->link_info->force_pause =
2217                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2218                 }
2219                 break;
2220         case RTE_FC_TX_PAUSE:
2221                 if (fc_conf->autoneg) {
2222                         bp->link_info->auto_pause =
2223                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2224                         bp->link_info->force_pause = 0;
2225                 } else {
2226                         bp->link_info->auto_pause = 0;
2227                         bp->link_info->force_pause =
2228                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2229                 }
2230                 break;
2231         case RTE_FC_FULL:
2232                 if (fc_conf->autoneg) {
2233                         bp->link_info->auto_pause =
2234                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2235                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2236                         bp->link_info->force_pause = 0;
2237                 } else {
2238                         bp->link_info->auto_pause = 0;
2239                         bp->link_info->force_pause =
2240                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2241                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2242                 }
2243                 break;
2244         }
2245         return bnxt_set_hwrm_link_config(bp, true);
2246 }
2247
2248 /* Add UDP tunneling port */
2249 static int
2250 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2251                          struct rte_eth_udp_tunnel *udp_tunnel)
2252 {
2253         struct bnxt *bp = eth_dev->data->dev_private;
2254         uint16_t tunnel_type = 0;
2255         int rc = 0;
2256
2257         rc = is_bnxt_in_error(bp);
2258         if (rc)
2259                 return rc;
2260
2261         switch (udp_tunnel->prot_type) {
2262         case RTE_TUNNEL_TYPE_VXLAN:
2263                 if (bp->vxlan_port_cnt) {
2264                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2265                                 udp_tunnel->udp_port);
2266                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2267                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2268                                 return -ENOSPC;
2269                         }
2270                         bp->vxlan_port_cnt++;
2271                         return 0;
2272                 }
2273                 tunnel_type =
2274                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2275                 bp->vxlan_port_cnt++;
2276                 break;
2277         case RTE_TUNNEL_TYPE_GENEVE:
2278                 if (bp->geneve_port_cnt) {
2279                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2280                                 udp_tunnel->udp_port);
2281                         if (bp->geneve_port != udp_tunnel->udp_port) {
2282                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2283                                 return -ENOSPC;
2284                         }
2285                         bp->geneve_port_cnt++;
2286                         return 0;
2287                 }
2288                 tunnel_type =
2289                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2290                 bp->geneve_port_cnt++;
2291                 break;
2292         default:
2293                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2294                 return -ENOTSUP;
2295         }
2296         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2297                                              tunnel_type);
2298         return rc;
2299 }
2300
2301 static int
2302 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2303                          struct rte_eth_udp_tunnel *udp_tunnel)
2304 {
2305         struct bnxt *bp = eth_dev->data->dev_private;
2306         uint16_t tunnel_type = 0;
2307         uint16_t port = 0;
2308         int rc = 0;
2309
2310         rc = is_bnxt_in_error(bp);
2311         if (rc)
2312                 return rc;
2313
2314         switch (udp_tunnel->prot_type) {
2315         case RTE_TUNNEL_TYPE_VXLAN:
2316                 if (!bp->vxlan_port_cnt) {
2317                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2318                         return -EINVAL;
2319                 }
2320                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2321                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2322                                 udp_tunnel->udp_port, bp->vxlan_port);
2323                         return -EINVAL;
2324                 }
2325                 if (--bp->vxlan_port_cnt)
2326                         return 0;
2327
2328                 tunnel_type =
2329                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2330                 port = bp->vxlan_fw_dst_port_id;
2331                 break;
2332         case RTE_TUNNEL_TYPE_GENEVE:
2333                 if (!bp->geneve_port_cnt) {
2334                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2335                         return -EINVAL;
2336                 }
2337                 if (bp->geneve_port != udp_tunnel->udp_port) {
2338                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2339                                 udp_tunnel->udp_port, bp->geneve_port);
2340                         return -EINVAL;
2341                 }
2342                 if (--bp->geneve_port_cnt)
2343                         return 0;
2344
2345                 tunnel_type =
2346                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2347                 port = bp->geneve_fw_dst_port_id;
2348                 break;
2349         default:
2350                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2351                 return -ENOTSUP;
2352         }
2353
2354         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2355         return rc;
2356 }
2357
2358 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2359 {
2360         struct bnxt_filter_info *filter;
2361         struct bnxt_vnic_info *vnic;
2362         int rc = 0;
2363         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2364
2365         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2366         filter = STAILQ_FIRST(&vnic->filter);
2367         while (filter) {
2368                 /* Search for this matching MAC+VLAN filter */
2369                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2370                         /* Delete the filter */
2371                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2372                         if (rc)
2373                                 return rc;
2374                         STAILQ_REMOVE(&vnic->filter, filter,
2375                                       bnxt_filter_info, next);
2376                         bnxt_free_filter(bp, filter);
2377                         PMD_DRV_LOG(INFO,
2378                                     "Deleted vlan filter for %d\n",
2379                                     vlan_id);
2380                         return 0;
2381                 }
2382                 filter = STAILQ_NEXT(filter, next);
2383         }
2384         return -ENOENT;
2385 }
2386
2387 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2388 {
2389         struct bnxt_filter_info *filter;
2390         struct bnxt_vnic_info *vnic;
2391         int rc = 0;
2392         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2393                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2394         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2395
2396         /* Implementation notes on the use of VNIC in this command:
2397          *
2398          * By default, these filters belong to default vnic for the function.
2399          * Once these filters are set up, only destination VNIC can be modified.
2400          * If the destination VNIC is not specified in this command,
2401          * then the HWRM shall only create an l2 context id.
2402          */
2403
2404         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2405         filter = STAILQ_FIRST(&vnic->filter);
2406         /* Check if the VLAN has already been added */
2407         while (filter) {
2408                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2409                         return -EEXIST;
2410
2411                 filter = STAILQ_NEXT(filter, next);
2412         }
2413
2414         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2415          * command to create MAC+VLAN filter with the right flags, enables set.
2416          */
2417         filter = bnxt_alloc_filter(bp);
2418         if (!filter) {
2419                 PMD_DRV_LOG(ERR,
2420                             "MAC/VLAN filter alloc failed\n");
2421                 return -ENOMEM;
2422         }
2423         /* MAC + VLAN ID filter */
2424         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2425          * untagged packets are received
2426          *
2427          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2428          * packets and only the programmed vlan's packets are received
2429          */
2430         filter->l2_ivlan = vlan_id;
2431         filter->l2_ivlan_mask = 0x0FFF;
2432         filter->enables |= en;
2433         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2434
2435         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2436         if (rc) {
2437                 /* Free the newly allocated filter as we were
2438                  * not able to create the filter in hardware.
2439                  */
2440                 bnxt_free_filter(bp, filter);
2441                 return rc;
2442         }
2443
2444         filter->mac_index = 0;
2445         /* Add this new filter to the list */
2446         if (vlan_id == 0)
2447                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2448         else
2449                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2450
2451         PMD_DRV_LOG(INFO,
2452                     "Added Vlan filter for %d\n", vlan_id);
2453         return rc;
2454 }
2455
2456 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2457                 uint16_t vlan_id, int on)
2458 {
2459         struct bnxt *bp = eth_dev->data->dev_private;
2460         int rc;
2461
2462         rc = is_bnxt_in_error(bp);
2463         if (rc)
2464                 return rc;
2465
2466         if (!eth_dev->data->dev_started) {
2467                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2468                 return -EINVAL;
2469         }
2470
2471         /* These operations apply to ALL existing MAC/VLAN filters */
2472         if (on)
2473                 return bnxt_add_vlan_filter(bp, vlan_id);
2474         else
2475                 return bnxt_del_vlan_filter(bp, vlan_id);
2476 }
2477
2478 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2479                                     struct bnxt_vnic_info *vnic)
2480 {
2481         struct bnxt_filter_info *filter;
2482         int rc;
2483
2484         filter = STAILQ_FIRST(&vnic->filter);
2485         while (filter) {
2486                 if (filter->mac_index == 0 &&
2487                     !memcmp(filter->l2_addr, bp->mac_addr,
2488                             RTE_ETHER_ADDR_LEN)) {
2489                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2490                         if (!rc) {
2491                                 STAILQ_REMOVE(&vnic->filter, filter,
2492                                               bnxt_filter_info, next);
2493                                 bnxt_free_filter(bp, filter);
2494                         }
2495                         return rc;
2496                 }
2497                 filter = STAILQ_NEXT(filter, next);
2498         }
2499         return 0;
2500 }
2501
2502 static int
2503 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2504 {
2505         struct bnxt_vnic_info *vnic;
2506         unsigned int i;
2507         int rc;
2508
2509         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2510         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2511                 /* Remove any VLAN filters programmed */
2512                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2513                         bnxt_del_vlan_filter(bp, i);
2514
2515                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2516                 if (rc)
2517                         return rc;
2518         } else {
2519                 /* Default filter will allow packets that match the
2520                  * dest mac. So, it has to be deleted, otherwise, we
2521                  * will endup receiving vlan packets for which the
2522                  * filter is not programmed, when hw-vlan-filter
2523                  * configuration is ON
2524                  */
2525                 bnxt_del_dflt_mac_filter(bp, vnic);
2526                 /* This filter will allow only untagged packets */
2527                 bnxt_add_vlan_filter(bp, 0);
2528         }
2529         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2530                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2531
2532         return 0;
2533 }
2534
2535 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2536 {
2537         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2538         unsigned int i;
2539         int rc;
2540
2541         /* Destroy vnic filters and vnic */
2542         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2543             DEV_RX_OFFLOAD_VLAN_FILTER) {
2544                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2545                         bnxt_del_vlan_filter(bp, i);
2546         }
2547         bnxt_del_dflt_mac_filter(bp, vnic);
2548
2549         rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2550         if (rc)
2551                 return rc;
2552
2553         rc = bnxt_hwrm_vnic_free(bp, vnic);
2554         if (rc)
2555                 return rc;
2556
2557         rte_free(vnic->fw_grp_ids);
2558         vnic->fw_grp_ids = NULL;
2559
2560         vnic->rx_queue_cnt = 0;
2561
2562         return 0;
2563 }
2564
2565 static int
2566 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2567 {
2568         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2569         int rc;
2570
2571         /* Destroy, recreate and reconfigure the default vnic */
2572         rc = bnxt_free_one_vnic(bp, 0);
2573         if (rc)
2574                 return rc;
2575
2576         /* default vnic 0 */
2577         rc = bnxt_setup_one_vnic(bp, 0);
2578         if (rc)
2579                 return rc;
2580
2581         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2582             DEV_RX_OFFLOAD_VLAN_FILTER) {
2583                 rc = bnxt_add_vlan_filter(bp, 0);
2584                 if (rc)
2585                         return rc;
2586                 rc = bnxt_restore_vlan_filters(bp);
2587                 if (rc)
2588                         return rc;
2589         } else {
2590                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2591                 if (rc)
2592                         return rc;
2593         }
2594
2595         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2596         if (rc)
2597                 return rc;
2598
2599         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2600                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2601
2602         return rc;
2603 }
2604
2605 static int
2606 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2607 {
2608         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2609         struct bnxt *bp = dev->data->dev_private;
2610         int rc;
2611
2612         rc = is_bnxt_in_error(bp);
2613         if (rc)
2614                 return rc;
2615
2616         /* Filter settings will get applied when port is started */
2617         if (!dev->data->dev_started)
2618                 return 0;
2619
2620         if (mask & ETH_VLAN_FILTER_MASK) {
2621                 /* Enable or disable VLAN filtering */
2622                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2623                 if (rc)
2624                         return rc;
2625         }
2626
2627         if (mask & ETH_VLAN_STRIP_MASK) {
2628                 /* Enable or disable VLAN stripping */
2629                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2630                 if (rc)
2631                         return rc;
2632         }
2633
2634         if (mask & ETH_VLAN_EXTEND_MASK) {
2635                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2636                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2637                 else
2638                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2639         }
2640
2641         return 0;
2642 }
2643
2644 static int
2645 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2646                       uint16_t tpid)
2647 {
2648         struct bnxt *bp = dev->data->dev_private;
2649         int qinq = dev->data->dev_conf.rxmode.offloads &
2650                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2651
2652         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2653             vlan_type != ETH_VLAN_TYPE_OUTER) {
2654                 PMD_DRV_LOG(ERR,
2655                             "Unsupported vlan type.");
2656                 return -EINVAL;
2657         }
2658         if (!qinq) {
2659                 PMD_DRV_LOG(ERR,
2660                             "QinQ not enabled. Needs to be ON as we can "
2661                             "accelerate only outer vlan\n");
2662                 return -EINVAL;
2663         }
2664
2665         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2666                 switch (tpid) {
2667                 case RTE_ETHER_TYPE_QINQ:
2668                         bp->outer_tpid_bd =
2669                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2670                                 break;
2671                 case RTE_ETHER_TYPE_VLAN:
2672                         bp->outer_tpid_bd =
2673                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2674                                 break;
2675                 case RTE_ETHER_TYPE_QINQ1:
2676                         bp->outer_tpid_bd =
2677                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2678                                 break;
2679                 case RTE_ETHER_TYPE_QINQ2:
2680                         bp->outer_tpid_bd =
2681                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2682                                 break;
2683                 case RTE_ETHER_TYPE_QINQ3:
2684                         bp->outer_tpid_bd =
2685                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2686                                 break;
2687                 default:
2688                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2689                         return -EINVAL;
2690                 }
2691                 bp->outer_tpid_bd |= tpid;
2692                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2693         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2694                 PMD_DRV_LOG(ERR,
2695                             "Can accelerate only outer vlan in QinQ\n");
2696                 return -EINVAL;
2697         }
2698
2699         return 0;
2700 }
2701
2702 static int
2703 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2704                              struct rte_ether_addr *addr)
2705 {
2706         struct bnxt *bp = dev->data->dev_private;
2707         /* Default Filter is tied to VNIC 0 */
2708         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2709         int rc;
2710
2711         rc = is_bnxt_in_error(bp);
2712         if (rc)
2713                 return rc;
2714
2715         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2716                 return -EPERM;
2717
2718         if (rte_is_zero_ether_addr(addr))
2719                 return -EINVAL;
2720
2721         /* Filter settings will get applied when port is started */
2722         if (!dev->data->dev_started)
2723                 return 0;
2724
2725         /* Check if the requested MAC is already added */
2726         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2727                 return 0;
2728
2729         /* Destroy filter and re-create it */
2730         bnxt_del_dflt_mac_filter(bp, vnic);
2731
2732         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2733         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2734                 /* This filter will allow only untagged packets */
2735                 rc = bnxt_add_vlan_filter(bp, 0);
2736         } else {
2737                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2738         }
2739
2740         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2741         return rc;
2742 }
2743
2744 static int
2745 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2746                           struct rte_ether_addr *mc_addr_set,
2747                           uint32_t nb_mc_addr)
2748 {
2749         struct bnxt *bp = eth_dev->data->dev_private;
2750         char *mc_addr_list = (char *)mc_addr_set;
2751         struct bnxt_vnic_info *vnic;
2752         uint32_t off = 0, i = 0;
2753         int rc;
2754
2755         rc = is_bnxt_in_error(bp);
2756         if (rc)
2757                 return rc;
2758
2759         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2760
2761         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2762                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2763                 goto allmulti;
2764         }
2765
2766         /* TODO Check for Duplicate mcast addresses */
2767         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2768         for (i = 0; i < nb_mc_addr; i++) {
2769                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2770                         RTE_ETHER_ADDR_LEN);
2771                 off += RTE_ETHER_ADDR_LEN;
2772         }
2773
2774         vnic->mc_addr_cnt = i;
2775         if (vnic->mc_addr_cnt)
2776                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2777         else
2778                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2779
2780 allmulti:
2781         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2782 }
2783
2784 static int
2785 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2786 {
2787         struct bnxt *bp = dev->data->dev_private;
2788         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2789         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2790         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2791         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2792         int ret;
2793
2794         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2795                         fw_major, fw_minor, fw_updt, fw_rsvd);
2796
2797         ret += 1; /* add the size of '\0' */
2798         if (fw_size < (uint32_t)ret)
2799                 return ret;
2800         else
2801                 return 0;
2802 }
2803
2804 static void
2805 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2806         struct rte_eth_rxq_info *qinfo)
2807 {
2808         struct bnxt *bp = dev->data->dev_private;
2809         struct bnxt_rx_queue *rxq;
2810
2811         if (is_bnxt_in_error(bp))
2812                 return;
2813
2814         rxq = dev->data->rx_queues[queue_id];
2815
2816         qinfo->mp = rxq->mb_pool;
2817         qinfo->scattered_rx = dev->data->scattered_rx;
2818         qinfo->nb_desc = rxq->nb_rx_desc;
2819
2820         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2821         qinfo->conf.rx_drop_en = rxq->drop_en;
2822         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2823         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2824 }
2825
2826 static void
2827 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2828         struct rte_eth_txq_info *qinfo)
2829 {
2830         struct bnxt *bp = dev->data->dev_private;
2831         struct bnxt_tx_queue *txq;
2832
2833         if (is_bnxt_in_error(bp))
2834                 return;
2835
2836         txq = dev->data->tx_queues[queue_id];
2837
2838         qinfo->nb_desc = txq->nb_tx_desc;
2839
2840         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2841         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2842         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2843
2844         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2845         qinfo->conf.tx_rs_thresh = 0;
2846         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2847         qinfo->conf.offloads = txq->offloads;
2848 }
2849
2850 static const struct {
2851         eth_rx_burst_t pkt_burst;
2852         const char *info;
2853 } bnxt_rx_burst_info[] = {
2854         {bnxt_recv_pkts,        "Scalar"},
2855 #if defined(RTE_ARCH_X86)
2856         {bnxt_recv_pkts_vec,    "Vector SSE"},
2857 #elif defined(RTE_ARCH_ARM64)
2858         {bnxt_recv_pkts_vec,    "Vector Neon"},
2859 #endif
2860 };
2861
2862 static int
2863 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2864                        struct rte_eth_burst_mode *mode)
2865 {
2866         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2867         size_t i;
2868
2869         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2870                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2871                         snprintf(mode->info, sizeof(mode->info), "%s",
2872                                  bnxt_rx_burst_info[i].info);
2873                         return 0;
2874                 }
2875         }
2876
2877         return -EINVAL;
2878 }
2879
2880 static const struct {
2881         eth_tx_burst_t pkt_burst;
2882         const char *info;
2883 } bnxt_tx_burst_info[] = {
2884         {bnxt_xmit_pkts,        "Scalar"},
2885 #if defined(RTE_ARCH_X86)
2886         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2887 #elif defined(RTE_ARCH_ARM64)
2888         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2889 #endif
2890 };
2891
2892 static int
2893 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2894                        struct rte_eth_burst_mode *mode)
2895 {
2896         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2897         size_t i;
2898
2899         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2900                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2901                         snprintf(mode->info, sizeof(mode->info), "%s",
2902                                  bnxt_tx_burst_info[i].info);
2903                         return 0;
2904                 }
2905         }
2906
2907         return -EINVAL;
2908 }
2909
2910 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2911 {
2912         struct bnxt *bp = eth_dev->data->dev_private;
2913         uint32_t new_pkt_size;
2914         uint32_t rc = 0;
2915         uint32_t i;
2916
2917         rc = is_bnxt_in_error(bp);
2918         if (rc)
2919                 return rc;
2920
2921         /* Exit if receive queues are not configured yet */
2922         if (!eth_dev->data->nb_rx_queues)
2923                 return rc;
2924
2925         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2926                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2927
2928         /*
2929          * Disallow any MTU change that would require scattered receive support
2930          * if it is not already enabled.
2931          */
2932         if (eth_dev->data->dev_started &&
2933             !eth_dev->data->scattered_rx &&
2934             (new_pkt_size >
2935              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2936                 PMD_DRV_LOG(ERR,
2937                             "MTU change would require scattered rx support. ");
2938                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2939                 return -EINVAL;
2940         }
2941
2942         if (new_mtu > RTE_ETHER_MTU) {
2943                 bp->flags |= BNXT_FLAG_JUMBO;
2944                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2945                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2946         } else {
2947                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2948                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2949                 bp->flags &= ~BNXT_FLAG_JUMBO;
2950         }
2951
2952         /* Is there a change in mtu setting? */
2953         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2954                 return rc;
2955
2956         for (i = 0; i < bp->nr_vnics; i++) {
2957                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2958                 uint16_t size = 0;
2959
2960                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2961                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2962                 if (rc)
2963                         break;
2964
2965                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2966                 size -= RTE_PKTMBUF_HEADROOM;
2967
2968                 if (size < new_mtu) {
2969                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2970                         if (rc)
2971                                 return rc;
2972                 }
2973         }
2974
2975         if (!rc)
2976                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2977
2978         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2979
2980         return rc;
2981 }
2982
2983 static int
2984 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2985 {
2986         struct bnxt *bp = dev->data->dev_private;
2987         uint16_t vlan = bp->vlan;
2988         int rc;
2989
2990         rc = is_bnxt_in_error(bp);
2991         if (rc)
2992                 return rc;
2993
2994         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2995                 PMD_DRV_LOG(ERR,
2996                         "PVID cannot be modified for this function\n");
2997                 return -ENOTSUP;
2998         }
2999         bp->vlan = on ? pvid : 0;
3000
3001         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3002         if (rc)
3003                 bp->vlan = vlan;
3004         return rc;
3005 }
3006
3007 static int
3008 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3009 {
3010         struct bnxt *bp = dev->data->dev_private;
3011         int rc;
3012
3013         rc = is_bnxt_in_error(bp);
3014         if (rc)
3015                 return rc;
3016
3017         return bnxt_hwrm_port_led_cfg(bp, true);
3018 }
3019
3020 static int
3021 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3022 {
3023         struct bnxt *bp = dev->data->dev_private;
3024         int rc;
3025
3026         rc = is_bnxt_in_error(bp);
3027         if (rc)
3028                 return rc;
3029
3030         return bnxt_hwrm_port_led_cfg(bp, false);
3031 }
3032
3033 static uint32_t
3034 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3035 {
3036         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3037         struct bnxt_cp_ring_info *cpr;
3038         uint32_t desc = 0, raw_cons;
3039         struct bnxt_rx_queue *rxq;
3040         struct rx_pkt_cmpl *rxcmp;
3041         int rc;
3042
3043         rc = is_bnxt_in_error(bp);
3044         if (rc)
3045                 return rc;
3046
3047         rxq = dev->data->rx_queues[rx_queue_id];
3048         cpr = rxq->cp_ring;
3049         raw_cons = cpr->cp_raw_cons;
3050
3051         while (1) {
3052                 uint32_t agg_cnt, cons, cmpl_type;
3053
3054                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3055                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3056
3057                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3058                         break;
3059
3060                 cmpl_type = CMP_TYPE(rxcmp);
3061
3062                 switch (cmpl_type) {
3063                 case CMPL_BASE_TYPE_RX_L2:
3064                 case CMPL_BASE_TYPE_RX_L2_V2:
3065                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3066                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3067                         desc++;
3068                         break;
3069
3070                 case CMPL_BASE_TYPE_RX_TPA_END:
3071                         if (BNXT_CHIP_P5(rxq->bp)) {
3072                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3073
3074                                 p5_tpa_end = (void *)rxcmp;
3075                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3076                         } else {
3077                                 struct rx_tpa_end_cmpl *tpa_end;
3078
3079                                 tpa_end = (void *)rxcmp;
3080                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3081                         }
3082
3083                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3084                         desc++;
3085                         break;
3086
3087                 default:
3088                         raw_cons += CMP_LEN(cmpl_type);
3089                 }
3090         }
3091
3092         return desc;
3093 }
3094
3095 static int
3096 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3097 {
3098         struct bnxt_rx_queue *rxq = rx_queue;
3099         struct bnxt_cp_ring_info *cpr;
3100         struct bnxt_rx_ring_info *rxr;
3101         uint32_t desc, raw_cons;
3102         struct bnxt *bp = rxq->bp;
3103         struct rx_pkt_cmpl *rxcmp;
3104         int rc;
3105
3106         rc = is_bnxt_in_error(bp);
3107         if (rc)
3108                 return rc;
3109
3110         if (offset >= rxq->nb_rx_desc)
3111                 return -EINVAL;
3112
3113         rxr = rxq->rx_ring;
3114         cpr = rxq->cp_ring;
3115
3116         /*
3117          * For the vector receive case, the completion at the requested
3118          * offset can be indexed directly.
3119          */
3120 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3121         if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3122                 struct rx_pkt_cmpl *rxcmp;
3123                 uint32_t cons;
3124
3125                 /* Check status of completion descriptor. */
3126                 raw_cons = cpr->cp_raw_cons +
3127                            offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3128                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3129                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3130
3131                 if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3132                         return RTE_ETH_RX_DESC_DONE;
3133
3134                 /* Check whether rx desc has an mbuf attached. */
3135                 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3136                 if (cons >= rxq->rxrearm_start &&
3137                     cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3138                         return RTE_ETH_RX_DESC_UNAVAIL;
3139                 }
3140
3141                 return RTE_ETH_RX_DESC_AVAIL;
3142         }
3143 #endif
3144
3145         /*
3146          * For the non-vector receive case, scan the completion ring to
3147          * locate the completion descriptor for the requested offset.
3148          */
3149         raw_cons = cpr->cp_raw_cons;
3150         desc = 0;
3151         while (1) {
3152                 uint32_t agg_cnt, cons, cmpl_type;
3153
3154                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3155                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3156
3157                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3158                         break;
3159
3160                 cmpl_type = CMP_TYPE(rxcmp);
3161
3162                 switch (cmpl_type) {
3163                 case CMPL_BASE_TYPE_RX_L2:
3164                 case CMPL_BASE_TYPE_RX_L2_V2:
3165                         if (desc == offset) {
3166                                 cons = rxcmp->opaque;
3167                                 if (rxr->rx_buf_ring[cons])
3168                                         return RTE_ETH_RX_DESC_DONE;
3169                                 else
3170                                         return RTE_ETH_RX_DESC_UNAVAIL;
3171                         }
3172                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3173                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3174                         desc++;
3175                         break;
3176
3177                 case CMPL_BASE_TYPE_RX_TPA_END:
3178                         if (desc == offset)
3179                                 return RTE_ETH_RX_DESC_DONE;
3180
3181                         if (BNXT_CHIP_P5(rxq->bp)) {
3182                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3183
3184                                 p5_tpa_end = (void *)rxcmp;
3185                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3186                         } else {
3187                                 struct rx_tpa_end_cmpl *tpa_end;
3188
3189                                 tpa_end = (void *)rxcmp;
3190                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3191                         }
3192
3193                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3194                         desc++;
3195                         break;
3196
3197                 default:
3198                         raw_cons += CMP_LEN(cmpl_type);
3199                 }
3200         }
3201
3202         return RTE_ETH_RX_DESC_AVAIL;
3203 }
3204
3205 static int
3206 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3207 {
3208         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3209         struct bnxt_tx_ring_info *txr;
3210         struct bnxt_cp_ring_info *cpr;
3211         struct rte_mbuf **tx_buf;
3212         struct tx_pkt_cmpl *txcmp;
3213         uint32_t cons, cp_cons;
3214         int rc;
3215
3216         if (!txq)
3217                 return -EINVAL;
3218
3219         rc = is_bnxt_in_error(txq->bp);
3220         if (rc)
3221                 return rc;
3222
3223         cpr = txq->cp_ring;
3224         txr = txq->tx_ring;
3225
3226         if (offset >= txq->nb_tx_desc)
3227                 return -EINVAL;
3228
3229         cons = RING_CMP(cpr->cp_ring_struct, offset);
3230         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3231         cp_cons = cpr->cp_raw_cons;
3232
3233         if (cons > cp_cons) {
3234                 if (CMPL_VALID(txcmp, cpr->valid))
3235                         return RTE_ETH_TX_DESC_UNAVAIL;
3236         } else {
3237                 if (CMPL_VALID(txcmp, !cpr->valid))
3238                         return RTE_ETH_TX_DESC_UNAVAIL;
3239         }
3240         tx_buf = &txr->tx_buf_ring[cons];
3241         if (*tx_buf == NULL)
3242                 return RTE_ETH_TX_DESC_DONE;
3243
3244         return RTE_ETH_TX_DESC_FULL;
3245 }
3246
3247 int
3248 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3249                      const struct rte_flow_ops **ops)
3250 {
3251         struct bnxt *bp = dev->data->dev_private;
3252         int ret = 0;
3253
3254         if (!bp)
3255                 return -EIO;
3256
3257         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3258                 struct bnxt_representor *vfr = dev->data->dev_private;
3259                 bp = vfr->parent_dev->data->dev_private;
3260                 /* parent is deleted while children are still valid */
3261                 if (!bp) {
3262                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3263                                     dev->data->port_id);
3264                         return -EIO;
3265                 }
3266         }
3267
3268         ret = is_bnxt_in_error(bp);
3269         if (ret)
3270                 return ret;
3271
3272         /* PMD supports thread-safe flow operations.  rte_flow API
3273          * functions can avoid mutex for multi-thread safety.
3274          */
3275         dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3276
3277         if (BNXT_TRUFLOW_EN(bp))
3278                 *ops = &bnxt_ulp_rte_flow_ops;
3279         else
3280                 *ops = &bnxt_flow_ops;
3281
3282         return ret;
3283 }
3284
3285 static const uint32_t *
3286 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3287 {
3288         static const uint32_t ptypes[] = {
3289                 RTE_PTYPE_L2_ETHER_VLAN,
3290                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3291                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3292                 RTE_PTYPE_L4_ICMP,
3293                 RTE_PTYPE_L4_TCP,
3294                 RTE_PTYPE_L4_UDP,
3295                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3296                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3297                 RTE_PTYPE_INNER_L4_ICMP,
3298                 RTE_PTYPE_INNER_L4_TCP,
3299                 RTE_PTYPE_INNER_L4_UDP,
3300                 RTE_PTYPE_UNKNOWN
3301         };
3302
3303         if (!dev->rx_pkt_burst)
3304                 return NULL;
3305
3306         return ptypes;
3307 }
3308
3309 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3310                          int reg_win)
3311 {
3312         uint32_t reg_base = *reg_arr & 0xfffff000;
3313         uint32_t win_off;
3314         int i;
3315
3316         for (i = 0; i < count; i++) {
3317                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3318                         return -ERANGE;
3319         }
3320         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3321         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3322         return 0;
3323 }
3324
3325 static int bnxt_map_ptp_regs(struct bnxt *bp)
3326 {
3327         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3328         uint32_t *reg_arr;
3329         int rc, i;
3330
3331         reg_arr = ptp->rx_regs;
3332         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3333         if (rc)
3334                 return rc;
3335
3336         reg_arr = ptp->tx_regs;
3337         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3338         if (rc)
3339                 return rc;
3340
3341         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3342                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3343
3344         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3345                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3346
3347         return 0;
3348 }
3349
3350 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3351 {
3352         rte_write32(0, (uint8_t *)bp->bar0 +
3353                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3354         rte_write32(0, (uint8_t *)bp->bar0 +
3355                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3356 }
3357
3358 static uint64_t bnxt_cc_read(struct bnxt *bp)
3359 {
3360         uint64_t ns;
3361
3362         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3363                               BNXT_GRCPF_REG_SYNC_TIME));
3364         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3365                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3366         return ns;
3367 }
3368
3369 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3370 {
3371         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3372         uint32_t fifo;
3373
3374         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3375                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3376         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3377                 return -EAGAIN;
3378
3379         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3380                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3381         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3382                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3383         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3384                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3385         rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3386
3387         return 0;
3388 }
3389
3390 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3391 {
3392         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3393         struct bnxt_pf_info *pf = bp->pf;
3394         uint16_t port_id;
3395         uint32_t fifo;
3396
3397         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3398                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3399         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3400                 return -EAGAIN;
3401
3402         port_id = pf->port_id;
3403         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3404                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3405
3406         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3407                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3408         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3409 /*              bnxt_clr_rx_ts(bp);       TBD  */
3410                 return -EBUSY;
3411         }
3412
3413         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3414                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3415         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3416                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3417
3418         return 0;
3419 }
3420
3421 static int
3422 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3423 {
3424         uint64_t ns;
3425         struct bnxt *bp = dev->data->dev_private;
3426         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3427
3428         if (!ptp)
3429                 return -ENOTSUP;
3430
3431         ns = rte_timespec_to_ns(ts);
3432         /* Set the timecounters to a new value. */
3433         ptp->tc.nsec = ns;
3434         ptp->tx_tstamp_tc.nsec = ns;
3435         ptp->rx_tstamp_tc.nsec = ns;
3436
3437         return 0;
3438 }
3439
3440 static int
3441 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3442 {
3443         struct bnxt *bp = dev->data->dev_private;
3444         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3445         uint64_t ns, systime_cycles = 0;
3446         int rc = 0;
3447
3448         if (!ptp)
3449                 return -ENOTSUP;
3450
3451         if (BNXT_CHIP_P5(bp))
3452                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3453                                              &systime_cycles);
3454         else
3455                 systime_cycles = bnxt_cc_read(bp);
3456
3457         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3458         *ts = rte_ns_to_timespec(ns);
3459
3460         return rc;
3461 }
3462 static int
3463 bnxt_timesync_enable(struct rte_eth_dev *dev)
3464 {
3465         struct bnxt *bp = dev->data->dev_private;
3466         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3467         uint32_t shift = 0;
3468         int rc;
3469
3470         if (!ptp)
3471                 return -ENOTSUP;
3472
3473         ptp->rx_filter = 1;
3474         ptp->tx_tstamp_en = 1;
3475         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3476
3477         rc = bnxt_hwrm_ptp_cfg(bp);
3478         if (rc)
3479                 return rc;
3480
3481         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3482         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3483         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3484
3485         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3486         ptp->tc.cc_shift = shift;
3487         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3488
3489         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3490         ptp->rx_tstamp_tc.cc_shift = shift;
3491         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3492
3493         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3494         ptp->tx_tstamp_tc.cc_shift = shift;
3495         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3496
3497         if (!BNXT_CHIP_P5(bp))
3498                 bnxt_map_ptp_regs(bp);
3499         else
3500                 rc = bnxt_ptp_start(bp);
3501
3502         return rc;
3503 }
3504
3505 static int
3506 bnxt_timesync_disable(struct rte_eth_dev *dev)
3507 {
3508         struct bnxt *bp = dev->data->dev_private;
3509         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3510
3511         if (!ptp)
3512                 return -ENOTSUP;
3513
3514         ptp->rx_filter = 0;
3515         ptp->tx_tstamp_en = 0;
3516         ptp->rxctl = 0;
3517
3518         bnxt_hwrm_ptp_cfg(bp);
3519
3520         if (!BNXT_CHIP_P5(bp))
3521                 bnxt_unmap_ptp_regs(bp);
3522         else
3523                 bnxt_ptp_stop(bp);
3524
3525         return 0;
3526 }
3527
3528 static int
3529 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3530                                  struct timespec *timestamp,
3531                                  uint32_t flags __rte_unused)
3532 {
3533         struct bnxt *bp = dev->data->dev_private;
3534         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3535         uint64_t rx_tstamp_cycles = 0;
3536         uint64_t ns;
3537
3538         if (!ptp)
3539                 return -ENOTSUP;
3540
3541         if (BNXT_CHIP_P5(bp))
3542                 rx_tstamp_cycles = ptp->rx_timestamp;
3543         else
3544                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3545
3546         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3547         *timestamp = rte_ns_to_timespec(ns);
3548         return  0;
3549 }
3550
3551 static int
3552 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3553                                  struct timespec *timestamp)
3554 {
3555         struct bnxt *bp = dev->data->dev_private;
3556         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3557         uint64_t tx_tstamp_cycles = 0;
3558         uint64_t ns;
3559         int rc = 0;
3560
3561         if (!ptp)
3562                 return -ENOTSUP;
3563
3564         if (BNXT_CHIP_P5(bp))
3565                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3566                                              &tx_tstamp_cycles);
3567         else
3568                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3569
3570         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3571         *timestamp = rte_ns_to_timespec(ns);
3572
3573         return rc;
3574 }
3575
3576 static int
3577 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3578 {
3579         struct bnxt *bp = dev->data->dev_private;
3580         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3581
3582         if (!ptp)
3583                 return -ENOTSUP;
3584
3585         ptp->tc.nsec += delta;
3586         ptp->tx_tstamp_tc.nsec += delta;
3587         ptp->rx_tstamp_tc.nsec += delta;
3588
3589         return 0;
3590 }
3591
3592 static int
3593 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3594 {
3595         struct bnxt *bp = dev->data->dev_private;
3596         int rc;
3597         uint32_t dir_entries;
3598         uint32_t entry_length;
3599
3600         rc = is_bnxt_in_error(bp);
3601         if (rc)
3602                 return rc;
3603
3604         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3605                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3606                     bp->pdev->addr.devid, bp->pdev->addr.function);
3607
3608         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3609         if (rc != 0)
3610                 return rc;
3611
3612         return dir_entries * entry_length;
3613 }
3614
3615 static int
3616 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3617                 struct rte_dev_eeprom_info *in_eeprom)
3618 {
3619         struct bnxt *bp = dev->data->dev_private;
3620         uint32_t index;
3621         uint32_t offset;
3622         int rc;
3623
3624         rc = is_bnxt_in_error(bp);
3625         if (rc)
3626                 return rc;
3627
3628         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3629                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3630                     bp->pdev->addr.devid, bp->pdev->addr.function,
3631                     in_eeprom->offset, in_eeprom->length);
3632
3633         if (in_eeprom->offset == 0) /* special offset value to get directory */
3634                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3635                                                 in_eeprom->data);
3636
3637         index = in_eeprom->offset >> 24;
3638         offset = in_eeprom->offset & 0xffffff;
3639
3640         if (index != 0)
3641                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3642                                            in_eeprom->length, in_eeprom->data);
3643
3644         return 0;
3645 }
3646
3647 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3648 {
3649         switch (dir_type) {
3650         case BNX_DIR_TYPE_CHIMP_PATCH:
3651         case BNX_DIR_TYPE_BOOTCODE:
3652         case BNX_DIR_TYPE_BOOTCODE_2:
3653         case BNX_DIR_TYPE_APE_FW:
3654         case BNX_DIR_TYPE_APE_PATCH:
3655         case BNX_DIR_TYPE_KONG_FW:
3656         case BNX_DIR_TYPE_KONG_PATCH:
3657         case BNX_DIR_TYPE_BONO_FW:
3658         case BNX_DIR_TYPE_BONO_PATCH:
3659                 /* FALLTHROUGH */
3660                 return true;
3661         }
3662
3663         return false;
3664 }
3665
3666 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3667 {
3668         switch (dir_type) {
3669         case BNX_DIR_TYPE_AVS:
3670         case BNX_DIR_TYPE_EXP_ROM_MBA:
3671         case BNX_DIR_TYPE_PCIE:
3672         case BNX_DIR_TYPE_TSCF_UCODE:
3673         case BNX_DIR_TYPE_EXT_PHY:
3674         case BNX_DIR_TYPE_CCM:
3675         case BNX_DIR_TYPE_ISCSI_BOOT:
3676         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3677         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3678                 /* FALLTHROUGH */
3679                 return true;
3680         }
3681
3682         return false;
3683 }
3684
3685 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3686 {
3687         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3688                 bnxt_dir_type_is_other_exec_format(dir_type);
3689 }
3690
3691 static int
3692 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3693                 struct rte_dev_eeprom_info *in_eeprom)
3694 {
3695         struct bnxt *bp = dev->data->dev_private;
3696         uint8_t index, dir_op;
3697         uint16_t type, ext, ordinal, attr;
3698         int rc;
3699
3700         rc = is_bnxt_in_error(bp);
3701         if (rc)
3702                 return rc;
3703
3704         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3705                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3706                     bp->pdev->addr.devid, bp->pdev->addr.function,
3707                     in_eeprom->offset, in_eeprom->length);
3708
3709         if (!BNXT_PF(bp)) {
3710                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3711                 return -EINVAL;
3712         }
3713
3714         type = in_eeprom->magic >> 16;
3715
3716         if (type == 0xffff) { /* special value for directory operations */
3717                 index = in_eeprom->magic & 0xff;
3718                 dir_op = in_eeprom->magic >> 8;
3719                 if (index == 0)
3720                         return -EINVAL;
3721                 switch (dir_op) {
3722                 case 0x0e: /* erase */
3723                         if (in_eeprom->offset != ~in_eeprom->magic)
3724                                 return -EINVAL;
3725                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3726                 default:
3727                         return -EINVAL;
3728                 }
3729         }
3730
3731         /* Create or re-write an NVM item: */
3732         if (bnxt_dir_type_is_executable(type) == true)
3733                 return -EOPNOTSUPP;
3734         ext = in_eeprom->magic & 0xffff;
3735         ordinal = in_eeprom->offset >> 16;
3736         attr = in_eeprom->offset & 0xffff;
3737
3738         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3739                                      in_eeprom->data, in_eeprom->length);
3740 }
3741
3742 /*
3743  * Initialization
3744  */
3745
3746 static const struct eth_dev_ops bnxt_dev_ops = {
3747         .dev_infos_get = bnxt_dev_info_get_op,
3748         .dev_close = bnxt_dev_close_op,
3749         .dev_configure = bnxt_dev_configure_op,
3750         .dev_start = bnxt_dev_start_op,
3751         .dev_stop = bnxt_dev_stop_op,
3752         .dev_set_link_up = bnxt_dev_set_link_up_op,
3753         .dev_set_link_down = bnxt_dev_set_link_down_op,
3754         .stats_get = bnxt_stats_get_op,
3755         .stats_reset = bnxt_stats_reset_op,
3756         .rx_queue_setup = bnxt_rx_queue_setup_op,
3757         .rx_queue_release = bnxt_rx_queue_release_op,
3758         .tx_queue_setup = bnxt_tx_queue_setup_op,
3759         .tx_queue_release = bnxt_tx_queue_release_op,
3760         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3761         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3762         .reta_update = bnxt_reta_update_op,
3763         .reta_query = bnxt_reta_query_op,
3764         .rss_hash_update = bnxt_rss_hash_update_op,
3765         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3766         .link_update = bnxt_link_update_op,
3767         .promiscuous_enable = bnxt_promiscuous_enable_op,
3768         .promiscuous_disable = bnxt_promiscuous_disable_op,
3769         .allmulticast_enable = bnxt_allmulticast_enable_op,
3770         .allmulticast_disable = bnxt_allmulticast_disable_op,
3771         .mac_addr_add = bnxt_mac_addr_add_op,
3772         .mac_addr_remove = bnxt_mac_addr_remove_op,
3773         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3774         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3775         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3776         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3777         .vlan_filter_set = bnxt_vlan_filter_set_op,
3778         .vlan_offload_set = bnxt_vlan_offload_set_op,
3779         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3780         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3781         .mtu_set = bnxt_mtu_set_op,
3782         .mac_addr_set = bnxt_set_default_mac_addr_op,
3783         .xstats_get = bnxt_dev_xstats_get_op,
3784         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3785         .xstats_reset = bnxt_dev_xstats_reset_op,
3786         .fw_version_get = bnxt_fw_version_get,
3787         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3788         .rxq_info_get = bnxt_rxq_info_get_op,
3789         .txq_info_get = bnxt_txq_info_get_op,
3790         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3791         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3792         .dev_led_on = bnxt_dev_led_on_op,
3793         .dev_led_off = bnxt_dev_led_off_op,
3794         .rx_queue_start = bnxt_rx_queue_start,
3795         .rx_queue_stop = bnxt_rx_queue_stop,
3796         .tx_queue_start = bnxt_tx_queue_start,
3797         .tx_queue_stop = bnxt_tx_queue_stop,
3798         .flow_ops_get = bnxt_flow_ops_get_op,
3799         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3800         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3801         .get_eeprom           = bnxt_get_eeprom_op,
3802         .set_eeprom           = bnxt_set_eeprom_op,
3803         .timesync_enable      = bnxt_timesync_enable,
3804         .timesync_disable     = bnxt_timesync_disable,
3805         .timesync_read_time   = bnxt_timesync_read_time,
3806         .timesync_write_time   = bnxt_timesync_write_time,
3807         .timesync_adjust_time = bnxt_timesync_adjust_time,
3808         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3809         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3810 };
3811
3812 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3813 {
3814         uint32_t offset;
3815
3816         /* Only pre-map the reset GRC registers using window 3 */
3817         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3818                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3819
3820         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3821
3822         return offset;
3823 }
3824
3825 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3826 {
3827         struct bnxt_error_recovery_info *info = bp->recovery_info;
3828         uint32_t reg_base = 0xffffffff;
3829         int i;
3830
3831         /* Only pre-map the monitoring GRC registers using window 2 */
3832         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3833                 uint32_t reg = info->status_regs[i];
3834
3835                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3836                         continue;
3837
3838                 if (reg_base == 0xffffffff)
3839                         reg_base = reg & 0xfffff000;
3840                 if ((reg & 0xfffff000) != reg_base)
3841                         return -ERANGE;
3842
3843                 /* Use mask 0xffc as the Lower 2 bits indicates
3844                  * address space location
3845                  */
3846                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3847                                                 (reg & 0xffc);
3848         }
3849
3850         if (reg_base == 0xffffffff)
3851                 return 0;
3852
3853         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3854                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3855
3856         return 0;
3857 }
3858
3859 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3860 {
3861         struct bnxt_error_recovery_info *info = bp->recovery_info;
3862         uint32_t delay = info->delay_after_reset[index];
3863         uint32_t val = info->reset_reg_val[index];
3864         uint32_t reg = info->reset_reg[index];
3865         uint32_t type, offset;
3866         int ret;
3867
3868         type = BNXT_FW_STATUS_REG_TYPE(reg);
3869         offset = BNXT_FW_STATUS_REG_OFF(reg);
3870
3871         switch (type) {
3872         case BNXT_FW_STATUS_REG_TYPE_CFG:
3873                 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3874                 if (ret < 0) {
3875                         PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
3876                                     val, offset);
3877                         return;
3878                 }
3879                 break;
3880         case BNXT_FW_STATUS_REG_TYPE_GRC:
3881                 offset = bnxt_map_reset_regs(bp, offset);
3882                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3883                 break;
3884         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3885                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3886                 break;
3887         }
3888         /* wait on a specific interval of time until core reset is complete */
3889         if (delay)
3890                 rte_delay_ms(delay);
3891 }
3892
3893 static void bnxt_dev_cleanup(struct bnxt *bp)
3894 {
3895         bp->eth_dev->data->dev_link.link_status = 0;
3896         bp->link_info->link_up = 0;
3897         if (bp->eth_dev->data->dev_started)
3898                 bnxt_dev_stop(bp->eth_dev);
3899
3900         bnxt_uninit_resources(bp, true);
3901 }
3902
3903 static int
3904 bnxt_check_fw_reset_done(struct bnxt *bp)
3905 {
3906         int timeout = bp->fw_reset_max_msecs;
3907         uint16_t val = 0;
3908         int rc;
3909
3910         do {
3911                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
3912                 if (rc < 0) {
3913                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
3914                         return rc;
3915                 }
3916                 if (val != 0xffff)
3917                         break;
3918                 rte_delay_ms(1);
3919         } while (timeout--);
3920
3921         if (val == 0xffff) {
3922                 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
3923                 return -1;
3924         }
3925
3926         return 0;
3927 }
3928
3929 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3930 {
3931         struct rte_eth_dev *dev = bp->eth_dev;
3932         struct rte_vlan_filter_conf *vfc;
3933         int vidx, vbit, rc;
3934         uint16_t vlan_id;
3935
3936         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3937                 vfc = &dev->data->vlan_filter_conf;
3938                 vidx = vlan_id / 64;
3939                 vbit = vlan_id % 64;
3940
3941                 /* Each bit corresponds to a VLAN id */
3942                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3943                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3944                         if (rc)
3945                                 return rc;
3946                 }
3947         }
3948
3949         return 0;
3950 }
3951
3952 static int bnxt_restore_mac_filters(struct bnxt *bp)
3953 {
3954         struct rte_eth_dev *dev = bp->eth_dev;
3955         struct rte_eth_dev_info dev_info;
3956         struct rte_ether_addr *addr;
3957         uint64_t pool_mask;
3958         uint32_t pool = 0;
3959         uint16_t i;
3960         int rc;
3961
3962         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3963                 return 0;
3964
3965         rc = bnxt_dev_info_get_op(dev, &dev_info);
3966         if (rc)
3967                 return rc;
3968
3969         /* replay MAC address configuration */
3970         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3971                 addr = &dev->data->mac_addrs[i];
3972
3973                 /* skip zero address */
3974                 if (rte_is_zero_ether_addr(addr))
3975                         continue;
3976
3977                 pool = 0;
3978                 pool_mask = dev->data->mac_pool_sel[i];
3979
3980                 do {
3981                         if (pool_mask & 1ULL) {
3982                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3983                                 if (rc)
3984                                         return rc;
3985                         }
3986                         pool_mask >>= 1;
3987                         pool++;
3988                 } while (pool_mask);
3989         }
3990
3991         return 0;
3992 }
3993
3994 static int bnxt_restore_filters(struct bnxt *bp)
3995 {
3996         struct rte_eth_dev *dev = bp->eth_dev;
3997         int ret = 0;
3998
3999         if (dev->data->all_multicast) {
4000                 ret = bnxt_allmulticast_enable_op(dev);
4001                 if (ret)
4002                         return ret;
4003         }
4004         if (dev->data->promiscuous) {
4005                 ret = bnxt_promiscuous_enable_op(dev);
4006                 if (ret)
4007                         return ret;
4008         }
4009
4010         ret = bnxt_restore_mac_filters(bp);
4011         if (ret)
4012                 return ret;
4013
4014         ret = bnxt_restore_vlan_filters(bp);
4015         /* TODO restore other filters as well */
4016         return ret;
4017 }
4018
4019 static int bnxt_check_fw_ready(struct bnxt *bp)
4020 {
4021         int timeout = bp->fw_reset_max_msecs;
4022         int rc = 0;
4023
4024         do {
4025                 rc = bnxt_hwrm_poll_ver_get(bp);
4026                 if (rc == 0)
4027                         break;
4028                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4029                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4030         } while (rc && timeout > 0);
4031
4032         if (rc)
4033                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4034
4035         return rc;
4036 }
4037
4038 static void bnxt_dev_recover(void *arg)
4039 {
4040         struct bnxt *bp = arg;
4041         int rc = 0;
4042
4043         pthread_mutex_lock(&bp->err_recovery_lock);
4044
4045         if (!bp->fw_reset_min_msecs) {
4046                 rc = bnxt_check_fw_reset_done(bp);
4047                 if (rc)
4048                         goto err;
4049         }
4050
4051         /* Clear Error flag so that device re-init should happen */
4052         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4053
4054         rc = bnxt_check_fw_ready(bp);
4055         if (rc)
4056                 goto err;
4057
4058         rc = bnxt_init_resources(bp, true);
4059         if (rc) {
4060                 PMD_DRV_LOG(ERR,
4061                             "Failed to initialize resources after reset\n");
4062                 goto err;
4063         }
4064         /* clear reset flag as the device is initialized now */
4065         bp->flags &= ~BNXT_FLAG_FW_RESET;
4066
4067         rc = bnxt_dev_start_op(bp->eth_dev);
4068         if (rc) {
4069                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4070                 goto err_start;
4071         }
4072
4073         rc = bnxt_restore_filters(bp);
4074         if (rc)
4075                 goto err_start;
4076
4077         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4078         pthread_mutex_unlock(&bp->err_recovery_lock);
4079
4080         return;
4081 err_start:
4082         bnxt_dev_stop(bp->eth_dev);
4083 err:
4084         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4085         bnxt_uninit_resources(bp, false);
4086         pthread_mutex_unlock(&bp->err_recovery_lock);
4087         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4088 }
4089
4090 void bnxt_dev_reset_and_resume(void *arg)
4091 {
4092         struct bnxt *bp = arg;
4093         uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4094         uint16_t val = 0;
4095         int rc;
4096
4097         bnxt_dev_cleanup(bp);
4098
4099         bnxt_wait_for_device_shutdown(bp);
4100
4101         /* During some fatal firmware error conditions, the PCI config space
4102          * register 0x2e which normally contains the subsystem ID will become
4103          * 0xffff. This register will revert back to the normal value after
4104          * the chip has completed core reset. If we detect this condition,
4105          * we can poll this config register immediately for the value to revert.
4106          */
4107         if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4108                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4109                 if (rc < 0) {
4110                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4111                         return;
4112                 }
4113                 if (val == 0xffff) {
4114                         bp->fw_reset_min_msecs = 0;
4115                         us = 1;
4116                 }
4117         }
4118
4119         rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4120         if (rc)
4121                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4122 }
4123
4124 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4125 {
4126         struct bnxt_error_recovery_info *info = bp->recovery_info;
4127         uint32_t reg = info->status_regs[index];
4128         uint32_t type, offset, val = 0;
4129
4130         type = BNXT_FW_STATUS_REG_TYPE(reg);
4131         offset = BNXT_FW_STATUS_REG_OFF(reg);
4132
4133         switch (type) {
4134         case BNXT_FW_STATUS_REG_TYPE_CFG:
4135                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4136                 break;
4137         case BNXT_FW_STATUS_REG_TYPE_GRC:
4138                 offset = info->mapped_status_regs[index];
4139                 /* FALLTHROUGH */
4140         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4141                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4142                                        offset));
4143                 break;
4144         }
4145
4146         return val;
4147 }
4148
4149 static int bnxt_fw_reset_all(struct bnxt *bp)
4150 {
4151         struct bnxt_error_recovery_info *info = bp->recovery_info;
4152         uint32_t i;
4153         int rc = 0;
4154
4155         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4156                 /* Reset through master function driver */
4157                 for (i = 0; i < info->reg_array_cnt; i++)
4158                         bnxt_write_fw_reset_reg(bp, i);
4159                 /* Wait for time specified by FW after triggering reset */
4160                 rte_delay_ms(info->master_func_wait_period_after_reset);
4161         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4162                 /* Reset with the help of Kong processor */
4163                 rc = bnxt_hwrm_fw_reset(bp);
4164                 if (rc)
4165                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4166         }
4167
4168         return rc;
4169 }
4170
4171 static void bnxt_fw_reset_cb(void *arg)
4172 {
4173         struct bnxt *bp = arg;
4174         struct bnxt_error_recovery_info *info = bp->recovery_info;
4175         int rc = 0;
4176
4177         /* Only Master function can do FW reset */
4178         if (bnxt_is_master_func(bp) &&
4179             bnxt_is_recovery_enabled(bp)) {
4180                 rc = bnxt_fw_reset_all(bp);
4181                 if (rc) {
4182                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4183                         return;
4184                 }
4185         }
4186
4187         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4188          * EXCEPTION_FATAL_ASYNC event to all the functions
4189          * (including MASTER FUNC). After receiving this Async, all the active
4190          * drivers should treat this case as FW initiated recovery
4191          */
4192         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4193                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4194                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4195
4196                 /* To recover from error */
4197                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4198                                   (void *)bp);
4199         }
4200 }
4201
4202 /* Driver should poll FW heartbeat, reset_counter with the frequency
4203  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4204  * When the driver detects heartbeat stop or change in reset_counter,
4205  * it has to trigger a reset to recover from the error condition.
4206  * A “master PF” is the function who will have the privilege to
4207  * initiate the chimp reset. The master PF will be elected by the
4208  * firmware and will be notified through async message.
4209  */
4210 static void bnxt_check_fw_health(void *arg)
4211 {
4212         struct bnxt *bp = arg;
4213         struct bnxt_error_recovery_info *info = bp->recovery_info;
4214         uint32_t val = 0, wait_msec;
4215
4216         if (!info || !bnxt_is_recovery_enabled(bp) ||
4217             is_bnxt_in_error(bp))
4218                 return;
4219
4220         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4221         if (val == info->last_heart_beat)
4222                 goto reset;
4223
4224         info->last_heart_beat = val;
4225
4226         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4227         if (val != info->last_reset_counter)
4228                 goto reset;
4229
4230         info->last_reset_counter = val;
4231
4232         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4233                           bnxt_check_fw_health, (void *)bp);
4234
4235         return;
4236 reset:
4237         /* Stop DMA to/from device */
4238         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4239         bp->flags |= BNXT_FLAG_FW_RESET;
4240
4241         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4242
4243         if (bnxt_is_master_func(bp))
4244                 wait_msec = info->master_func_wait_period;
4245         else
4246                 wait_msec = info->normal_func_wait_period;
4247
4248         rte_eal_alarm_set(US_PER_MS * wait_msec,
4249                           bnxt_fw_reset_cb, (void *)bp);
4250 }
4251
4252 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4253 {
4254         uint32_t polling_freq;
4255
4256         pthread_mutex_lock(&bp->health_check_lock);
4257
4258         if (!bnxt_is_recovery_enabled(bp))
4259                 goto done;
4260
4261         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4262                 goto done;
4263
4264         polling_freq = bp->recovery_info->driver_polling_freq;
4265
4266         rte_eal_alarm_set(US_PER_MS * polling_freq,
4267                           bnxt_check_fw_health, (void *)bp);
4268         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4269
4270 done:
4271         pthread_mutex_unlock(&bp->health_check_lock);
4272 }
4273
4274 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4275 {
4276         if (!bnxt_is_recovery_enabled(bp))
4277                 return;
4278
4279         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4280         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4281 }
4282
4283 static bool bnxt_vf_pciid(uint16_t device_id)
4284 {
4285         switch (device_id) {
4286         case BROADCOM_DEV_ID_57304_VF:
4287         case BROADCOM_DEV_ID_57406_VF:
4288         case BROADCOM_DEV_ID_5731X_VF:
4289         case BROADCOM_DEV_ID_5741X_VF:
4290         case BROADCOM_DEV_ID_57414_VF:
4291         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4292         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4293         case BROADCOM_DEV_ID_58802_VF:
4294         case BROADCOM_DEV_ID_57500_VF1:
4295         case BROADCOM_DEV_ID_57500_VF2:
4296         case BROADCOM_DEV_ID_58818_VF:
4297                 /* FALLTHROUGH */
4298                 return true;
4299         default:
4300                 return false;
4301         }
4302 }
4303
4304 /* Phase 5 device */
4305 static bool bnxt_p5_device(uint16_t device_id)
4306 {
4307         switch (device_id) {
4308         case BROADCOM_DEV_ID_57508:
4309         case BROADCOM_DEV_ID_57504:
4310         case BROADCOM_DEV_ID_57502:
4311         case BROADCOM_DEV_ID_57508_MF1:
4312         case BROADCOM_DEV_ID_57504_MF1:
4313         case BROADCOM_DEV_ID_57502_MF1:
4314         case BROADCOM_DEV_ID_57508_MF2:
4315         case BROADCOM_DEV_ID_57504_MF2:
4316         case BROADCOM_DEV_ID_57502_MF2:
4317         case BROADCOM_DEV_ID_57500_VF1:
4318         case BROADCOM_DEV_ID_57500_VF2:
4319         case BROADCOM_DEV_ID_58812:
4320         case BROADCOM_DEV_ID_58814:
4321         case BROADCOM_DEV_ID_58818:
4322         case BROADCOM_DEV_ID_58818_VF:
4323                 /* FALLTHROUGH */
4324                 return true;
4325         default:
4326                 return false;
4327         }
4328 }
4329
4330 bool bnxt_stratus_device(struct bnxt *bp)
4331 {
4332         uint16_t device_id = bp->pdev->id.device_id;
4333
4334         switch (device_id) {
4335         case BROADCOM_DEV_ID_STRATUS_NIC:
4336         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4337         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4338                 /* FALLTHROUGH */
4339                 return true;
4340         default:
4341                 return false;
4342         }
4343 }
4344
4345 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4346 {
4347         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4348         struct bnxt *bp = eth_dev->data->dev_private;
4349
4350         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4351         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4352         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4353         if (!bp->bar0 || !bp->doorbell_base) {
4354                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4355                 return -ENODEV;
4356         }
4357
4358         bp->eth_dev = eth_dev;
4359         bp->pdev = pci_dev;
4360
4361         return 0;
4362 }
4363
4364 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4365                                   struct bnxt_ctx_pg_info *ctx_pg,
4366                                   uint32_t mem_size,
4367                                   const char *suffix,
4368                                   uint16_t idx)
4369 {
4370         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4371         const struct rte_memzone *mz = NULL;
4372         char mz_name[RTE_MEMZONE_NAMESIZE];
4373         rte_iova_t mz_phys_addr;
4374         uint64_t valid_bits = 0;
4375         uint32_t sz;
4376         int i;
4377
4378         if (!mem_size)
4379                 return 0;
4380
4381         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4382                          BNXT_PAGE_SIZE;
4383         rmem->page_size = BNXT_PAGE_SIZE;
4384         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4385         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4386         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4387
4388         valid_bits = PTU_PTE_VALID;
4389
4390         if (rmem->nr_pages > 1) {
4391                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4392                          "bnxt_ctx_pg_tbl%s_%x_%d",
4393                          suffix, idx, bp->eth_dev->data->port_id);
4394                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4395                 mz = rte_memzone_lookup(mz_name);
4396                 if (!mz) {
4397                         mz = rte_memzone_reserve_aligned(mz_name,
4398                                                 rmem->nr_pages * 8,
4399                                                 SOCKET_ID_ANY,
4400                                                 RTE_MEMZONE_2MB |
4401                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4402                                                 RTE_MEMZONE_IOVA_CONTIG,
4403                                                 BNXT_PAGE_SIZE);
4404                         if (mz == NULL)
4405                                 return -ENOMEM;
4406                 }
4407
4408                 memset(mz->addr, 0, mz->len);
4409                 mz_phys_addr = mz->iova;
4410
4411                 rmem->pg_tbl = mz->addr;
4412                 rmem->pg_tbl_map = mz_phys_addr;
4413                 rmem->pg_tbl_mz = mz;
4414         }
4415
4416         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4417                  suffix, idx, bp->eth_dev->data->port_id);
4418         mz = rte_memzone_lookup(mz_name);
4419         if (!mz) {
4420                 mz = rte_memzone_reserve_aligned(mz_name,
4421                                                  mem_size,
4422                                                  SOCKET_ID_ANY,
4423                                                  RTE_MEMZONE_1GB |
4424                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4425                                                  RTE_MEMZONE_IOVA_CONTIG,
4426                                                  BNXT_PAGE_SIZE);
4427                 if (mz == NULL)
4428                         return -ENOMEM;
4429         }
4430
4431         memset(mz->addr, 0, mz->len);
4432         mz_phys_addr = mz->iova;
4433
4434         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4435                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4436                 rmem->dma_arr[i] = mz_phys_addr + sz;
4437
4438                 if (rmem->nr_pages > 1) {
4439                         if (i == rmem->nr_pages - 2 &&
4440                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4441                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4442                         else if (i == rmem->nr_pages - 1 &&
4443                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4444                                 valid_bits |= PTU_PTE_LAST;
4445
4446                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4447                                                            valid_bits);
4448                 }
4449         }
4450
4451         rmem->mz = mz;
4452         if (rmem->vmem_size)
4453                 rmem->vmem = (void **)mz->addr;
4454         rmem->dma_arr[0] = mz_phys_addr;
4455         return 0;
4456 }
4457
4458 static void bnxt_free_ctx_mem(struct bnxt *bp)
4459 {
4460         int i;
4461
4462         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4463                 return;
4464
4465         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4466         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4467         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4468         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4469         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4470         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4471         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4472         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4473         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4474         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4475         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4476
4477         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4478                 if (bp->ctx->tqm_mem[i])
4479                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4480         }
4481
4482         rte_free(bp->ctx);
4483         bp->ctx = NULL;
4484 }
4485
4486 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4487
4488 #define min_t(type, x, y) ({                    \
4489         type __min1 = (x);                      \
4490         type __min2 = (y);                      \
4491         __min1 < __min2 ? __min1 : __min2; })
4492
4493 #define max_t(type, x, y) ({                    \
4494         type __max1 = (x);                      \
4495         type __max2 = (y);                      \
4496         __max1 > __max2 ? __max1 : __max2; })
4497
4498 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4499
4500 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4501 {
4502         struct bnxt_ctx_pg_info *ctx_pg;
4503         struct bnxt_ctx_mem_info *ctx;
4504         uint32_t mem_size, ena, entries;
4505         uint32_t entries_sp, min;
4506         int i, rc;
4507
4508         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4509         if (rc) {
4510                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4511                 return rc;
4512         }
4513         ctx = bp->ctx;
4514         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4515                 return 0;
4516
4517         ctx_pg = &ctx->qp_mem;
4518         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4519         if (ctx->qp_entry_size) {
4520                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4521                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4522                 if (rc)
4523                         return rc;
4524         }
4525
4526         ctx_pg = &ctx->srq_mem;
4527         ctx_pg->entries = ctx->srq_max_l2_entries;
4528         if (ctx->srq_entry_size) {
4529                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4530                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4531                 if (rc)
4532                         return rc;
4533         }
4534
4535         ctx_pg = &ctx->cq_mem;
4536         ctx_pg->entries = ctx->cq_max_l2_entries;
4537         if (ctx->cq_entry_size) {
4538                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4539                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4540                 if (rc)
4541                         return rc;
4542         }
4543
4544         ctx_pg = &ctx->vnic_mem;
4545         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4546                 ctx->vnic_max_ring_table_entries;
4547         if (ctx->vnic_entry_size) {
4548                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4549                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4550                 if (rc)
4551                         return rc;
4552         }
4553
4554         ctx_pg = &ctx->stat_mem;
4555         ctx_pg->entries = ctx->stat_max_entries;
4556         if (ctx->stat_entry_size) {
4557                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4558                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4559                 if (rc)
4560                         return rc;
4561         }
4562
4563         min = ctx->tqm_min_entries_per_ring;
4564
4565         entries_sp = ctx->qp_max_l2_entries +
4566                      ctx->vnic_max_vnic_entries +
4567                      2 * ctx->qp_min_qp1_entries + min;
4568         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4569
4570         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4571         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4572         entries = clamp_t(uint32_t, entries, min,
4573                           ctx->tqm_max_entries_per_ring);
4574         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4575                 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4576                  * i > 8 is other ext rings.
4577                  */
4578                 ctx_pg = ctx->tqm_mem[i];
4579                 ctx_pg->entries = i ? entries : entries_sp;
4580                 if (ctx->tqm_entry_size) {
4581                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4582                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4583                                                     "tqm_mem", i);
4584                         if (rc)
4585                                 return rc;
4586                 }
4587                 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4588                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4589                 else
4590                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4591         }
4592
4593         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4594         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4595         if (rc)
4596                 PMD_DRV_LOG(ERR,
4597                             "Failed to configure context mem: rc = %d\n", rc);
4598         else
4599                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4600
4601         return rc;
4602 }
4603
4604 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4605 {
4606         struct rte_pci_device *pci_dev = bp->pdev;
4607         char mz_name[RTE_MEMZONE_NAMESIZE];
4608         const struct rte_memzone *mz = NULL;
4609         uint32_t total_alloc_len;
4610         rte_iova_t mz_phys_addr;
4611
4612         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4613                 return 0;
4614
4615         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4616                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4617                  pci_dev->addr.bus, pci_dev->addr.devid,
4618                  pci_dev->addr.function, "rx_port_stats");
4619         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4620         mz = rte_memzone_lookup(mz_name);
4621         total_alloc_len =
4622                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4623                                        sizeof(struct rx_port_stats_ext) + 512);
4624         if (!mz) {
4625                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4626                                          SOCKET_ID_ANY,
4627                                          RTE_MEMZONE_2MB |
4628                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4629                                          RTE_MEMZONE_IOVA_CONTIG);
4630                 if (mz == NULL)
4631                         return -ENOMEM;
4632         }
4633         memset(mz->addr, 0, mz->len);
4634         mz_phys_addr = mz->iova;
4635
4636         bp->rx_mem_zone = (const void *)mz;
4637         bp->hw_rx_port_stats = mz->addr;
4638         bp->hw_rx_port_stats_map = mz_phys_addr;
4639
4640         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4641                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4642                  pci_dev->addr.bus, pci_dev->addr.devid,
4643                  pci_dev->addr.function, "tx_port_stats");
4644         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4645         mz = rte_memzone_lookup(mz_name);
4646         total_alloc_len =
4647                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4648                                        sizeof(struct tx_port_stats_ext) + 512);
4649         if (!mz) {
4650                 mz = rte_memzone_reserve(mz_name,
4651                                          total_alloc_len,
4652                                          SOCKET_ID_ANY,
4653                                          RTE_MEMZONE_2MB |
4654                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4655                                          RTE_MEMZONE_IOVA_CONTIG);
4656                 if (mz == NULL)
4657                         return -ENOMEM;
4658         }
4659         memset(mz->addr, 0, mz->len);
4660         mz_phys_addr = mz->iova;
4661
4662         bp->tx_mem_zone = (const void *)mz;
4663         bp->hw_tx_port_stats = mz->addr;
4664         bp->hw_tx_port_stats_map = mz_phys_addr;
4665         bp->flags |= BNXT_FLAG_PORT_STATS;
4666
4667         /* Display extended statistics if FW supports it */
4668         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4669             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4670             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4671                 return 0;
4672
4673         bp->hw_rx_port_stats_ext = (void *)
4674                 ((uint8_t *)bp->hw_rx_port_stats +
4675                  sizeof(struct rx_port_stats));
4676         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4677                 sizeof(struct rx_port_stats);
4678         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4679
4680         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4681             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4682                 bp->hw_tx_port_stats_ext = (void *)
4683                         ((uint8_t *)bp->hw_tx_port_stats +
4684                          sizeof(struct tx_port_stats));
4685                 bp->hw_tx_port_stats_ext_map =
4686                         bp->hw_tx_port_stats_map +
4687                         sizeof(struct tx_port_stats);
4688                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4689         }
4690
4691         return 0;
4692 }
4693
4694 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4695 {
4696         struct bnxt *bp = eth_dev->data->dev_private;
4697         int rc = 0;
4698
4699         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4700                                                RTE_ETHER_ADDR_LEN *
4701                                                bp->max_l2_ctx,
4702                                                0);
4703         if (eth_dev->data->mac_addrs == NULL) {
4704                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4705                 return -ENOMEM;
4706         }
4707
4708         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4709                 if (BNXT_PF(bp))
4710                         return -EINVAL;
4711
4712                 /* Generate a random MAC address, if none was assigned by PF */
4713                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4714                 bnxt_eth_hw_addr_random(bp->mac_addr);
4715                 PMD_DRV_LOG(INFO,
4716                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4717                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4718                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4719
4720                 rc = bnxt_hwrm_set_mac(bp);
4721                 if (rc)
4722                         return rc;
4723         }
4724
4725         /* Copy the permanent MAC from the FUNC_QCAPS response */
4726         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4727
4728         return rc;
4729 }
4730
4731 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4732 {
4733         int rc = 0;
4734
4735         /* MAC is already configured in FW */
4736         if (BNXT_HAS_DFLT_MAC_SET(bp))
4737                 return 0;
4738
4739         /* Restore the old MAC configured */
4740         rc = bnxt_hwrm_set_mac(bp);
4741         if (rc)
4742                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4743
4744         return rc;
4745 }
4746
4747 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4748 {
4749         if (!BNXT_PF(bp))
4750                 return;
4751
4752         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4753
4754         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4755                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4756         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4757         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4758         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4759         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4760 }
4761
4762 uint16_t
4763 bnxt_get_svif(uint16_t port_id, bool func_svif,
4764               enum bnxt_ulp_intf_type type)
4765 {
4766         struct rte_eth_dev *eth_dev;
4767         struct bnxt *bp;
4768
4769         eth_dev = &rte_eth_devices[port_id];
4770         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4771                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4772                 if (!vfr)
4773                         return 0;
4774
4775                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4776                         return vfr->svif;
4777
4778                 eth_dev = vfr->parent_dev;
4779         }
4780
4781         bp = eth_dev->data->dev_private;
4782
4783         return func_svif ? bp->func_svif : bp->port_svif;
4784 }
4785
4786 uint16_t
4787 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4788 {
4789         struct rte_eth_dev *eth_dev;
4790         struct bnxt_vnic_info *vnic;
4791         struct bnxt *bp;
4792
4793         eth_dev = &rte_eth_devices[port];
4794         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4795                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4796                 if (!vfr)
4797                         return 0;
4798
4799                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4800                         return vfr->dflt_vnic_id;
4801
4802                 eth_dev = vfr->parent_dev;
4803         }
4804
4805         bp = eth_dev->data->dev_private;
4806
4807         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4808
4809         return vnic->fw_vnic_id;
4810 }
4811
4812 uint16_t
4813 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4814 {
4815         struct rte_eth_dev *eth_dev;
4816         struct bnxt *bp;
4817
4818         eth_dev = &rte_eth_devices[port];
4819         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4820                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4821                 if (!vfr)
4822                         return 0;
4823
4824                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4825                         return vfr->fw_fid;
4826
4827                 eth_dev = vfr->parent_dev;
4828         }
4829
4830         bp = eth_dev->data->dev_private;
4831
4832         return bp->fw_fid;
4833 }
4834
4835 enum bnxt_ulp_intf_type
4836 bnxt_get_interface_type(uint16_t port)
4837 {
4838         struct rte_eth_dev *eth_dev;
4839         struct bnxt *bp;
4840
4841         eth_dev = &rte_eth_devices[port];
4842         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4843                 return BNXT_ULP_INTF_TYPE_VF_REP;
4844
4845         bp = eth_dev->data->dev_private;
4846         if (BNXT_PF(bp))
4847                 return BNXT_ULP_INTF_TYPE_PF;
4848         else if (BNXT_VF_IS_TRUSTED(bp))
4849                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4850         else if (BNXT_VF(bp))
4851                 return BNXT_ULP_INTF_TYPE_VF;
4852
4853         return BNXT_ULP_INTF_TYPE_INVALID;
4854 }
4855
4856 uint16_t
4857 bnxt_get_phy_port_id(uint16_t port_id)
4858 {
4859         struct bnxt_representor *vfr;
4860         struct rte_eth_dev *eth_dev;
4861         struct bnxt *bp;
4862
4863         eth_dev = &rte_eth_devices[port_id];
4864         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4865                 vfr = eth_dev->data->dev_private;
4866                 if (!vfr)
4867                         return 0;
4868
4869                 eth_dev = vfr->parent_dev;
4870         }
4871
4872         bp = eth_dev->data->dev_private;
4873
4874         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4875 }
4876
4877 uint16_t
4878 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4879 {
4880         struct rte_eth_dev *eth_dev;
4881         struct bnxt *bp;
4882
4883         eth_dev = &rte_eth_devices[port_id];
4884         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4885                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4886                 if (!vfr)
4887                         return 0;
4888
4889                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4890                         return vfr->fw_fid - 1;
4891
4892                 eth_dev = vfr->parent_dev;
4893         }
4894
4895         bp = eth_dev->data->dev_private;
4896
4897         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4898 }
4899
4900 uint16_t
4901 bnxt_get_vport(uint16_t port_id)
4902 {
4903         return (1 << bnxt_get_phy_port_id(port_id));
4904 }
4905
4906 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4907 {
4908         struct bnxt_error_recovery_info *info = bp->recovery_info;
4909
4910         if (info) {
4911                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4912                         memset(info, 0, sizeof(*info));
4913                 return;
4914         }
4915
4916         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4917                 return;
4918
4919         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4920                            sizeof(*info), 0);
4921         if (!info)
4922                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4923
4924         bp->recovery_info = info;
4925 }
4926
4927 static void bnxt_check_fw_status(struct bnxt *bp)
4928 {
4929         uint32_t fw_status;
4930
4931         if (!(bp->recovery_info &&
4932               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4933                 return;
4934
4935         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4936         if (fw_status != BNXT_FW_STATUS_HEALTHY)
4937                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4938                             fw_status);
4939 }
4940
4941 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4942 {
4943         struct bnxt_error_recovery_info *info = bp->recovery_info;
4944         uint32_t status_loc;
4945         uint32_t sig_ver;
4946
4947         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4948                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4949         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4950                                    BNXT_GRCP_WINDOW_2_BASE +
4951                                    offsetof(struct hcomm_status,
4952                                             sig_ver)));
4953         /* If the signature is absent, then FW does not support this feature */
4954         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4955             HCOMM_STATUS_SIGNATURE_VAL)
4956                 return 0;
4957
4958         if (!info) {
4959                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4960                                    sizeof(*info), 0);
4961                 if (!info)
4962                         return -ENOMEM;
4963                 bp->recovery_info = info;
4964         } else {
4965                 memset(info, 0, sizeof(*info));
4966         }
4967
4968         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4969                                       BNXT_GRCP_WINDOW_2_BASE +
4970                                       offsetof(struct hcomm_status,
4971                                                fw_status_loc)));
4972
4973         /* Only pre-map the FW health status GRC register */
4974         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4975                 return 0;
4976
4977         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4978         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4979                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4980
4981         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4982                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4983
4984         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4985
4986         return 0;
4987 }
4988
4989 /* This function gets the FW version along with the
4990  * capabilities(MAX and current) of the function, vnic,
4991  * error recovery, phy and other chip related info
4992  */
4993 static int bnxt_get_config(struct bnxt *bp)
4994 {
4995         uint16_t mtu;
4996         int rc = 0;
4997
4998         bp->fw_cap = 0;
4999
5000         rc = bnxt_map_hcomm_fw_status_reg(bp);
5001         if (rc)
5002                 return rc;
5003
5004         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5005         if (rc) {
5006                 bnxt_check_fw_status(bp);
5007                 return rc;
5008         }
5009
5010         rc = bnxt_hwrm_func_reset(bp);
5011         if (rc)
5012                 return -EIO;
5013
5014         rc = bnxt_hwrm_vnic_qcaps(bp);
5015         if (rc)
5016                 return rc;
5017
5018         rc = bnxt_hwrm_queue_qportcfg(bp);
5019         if (rc)
5020                 return rc;
5021
5022         /* Get the MAX capabilities for this function.
5023          * This function also allocates context memory for TQM rings and
5024          * informs the firmware about this allocated backing store memory.
5025          */
5026         rc = bnxt_hwrm_func_qcaps(bp);
5027         if (rc)
5028                 return rc;
5029
5030         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5031         if (rc)
5032                 return rc;
5033
5034         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5035         if (rc)
5036                 return rc;
5037
5038         bnxt_hwrm_port_mac_qcfg(bp);
5039
5040         bnxt_hwrm_parent_pf_qcfg(bp);
5041
5042         bnxt_hwrm_port_phy_qcaps(bp);
5043
5044         bnxt_alloc_error_recovery_info(bp);
5045         /* Get the adapter error recovery support info */
5046         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5047         if (rc)
5048                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5049
5050         bnxt_hwrm_port_led_qcaps(bp);
5051
5052         return 0;
5053 }
5054
5055 static int
5056 bnxt_init_locks(struct bnxt *bp)
5057 {
5058         int err;
5059
5060         err = pthread_mutex_init(&bp->flow_lock, NULL);
5061         if (err) {
5062                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5063                 return err;
5064         }
5065
5066         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5067         if (err) {
5068                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5069                 return err;
5070         }
5071
5072         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5073         if (err) {
5074                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5075                 return err;
5076         }
5077
5078         err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5079         if (err)
5080                 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5081
5082         return err;
5083 }
5084
5085 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5086 {
5087         int rc = 0;
5088
5089         rc = bnxt_get_config(bp);
5090         if (rc)
5091                 return rc;
5092
5093         if (!reconfig_dev) {
5094                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5095                 if (rc)
5096                         return rc;
5097         } else {
5098                 rc = bnxt_restore_dflt_mac(bp);
5099                 if (rc)
5100                         return rc;
5101         }
5102
5103         bnxt_config_vf_req_fwd(bp);
5104
5105         rc = bnxt_hwrm_func_driver_register(bp);
5106         if (rc) {
5107                 PMD_DRV_LOG(ERR, "Failed to register driver");
5108                 return -EBUSY;
5109         }
5110
5111         if (BNXT_PF(bp)) {
5112                 if (bp->pdev->max_vfs) {
5113                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5114                         if (rc) {
5115                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5116                                 return rc;
5117                         }
5118                 } else {
5119                         rc = bnxt_hwrm_allocate_pf_only(bp);
5120                         if (rc) {
5121                                 PMD_DRV_LOG(ERR,
5122                                             "Failed to allocate PF resources");
5123                                 return rc;
5124                         }
5125                 }
5126         }
5127
5128         rc = bnxt_alloc_mem(bp, reconfig_dev);
5129         if (rc)
5130                 return rc;
5131
5132         rc = bnxt_setup_int(bp);
5133         if (rc)
5134                 return rc;
5135
5136         rc = bnxt_request_int(bp);
5137         if (rc)
5138                 return rc;
5139
5140         rc = bnxt_init_ctx_mem(bp);
5141         if (rc) {
5142                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5143                 return rc;
5144         }
5145
5146         return 0;
5147 }
5148
5149 static int
5150 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5151                           const char *value, void *opaque_arg)
5152 {
5153         struct bnxt *bp = opaque_arg;
5154         unsigned long truflow;
5155         char *end = NULL;
5156
5157         if (!value || !opaque_arg) {
5158                 PMD_DRV_LOG(ERR,
5159                             "Invalid parameter passed to truflow devargs.\n");
5160                 return -EINVAL;
5161         }
5162
5163         truflow = strtoul(value, &end, 10);
5164         if (end == NULL || *end != '\0' ||
5165             (truflow == ULONG_MAX && errno == ERANGE)) {
5166                 PMD_DRV_LOG(ERR,
5167                             "Invalid parameter passed to truflow devargs.\n");
5168                 return -EINVAL;
5169         }
5170
5171         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5172                 PMD_DRV_LOG(ERR,
5173                             "Invalid value passed to truflow devargs.\n");
5174                 return -EINVAL;
5175         }
5176
5177         if (truflow) {
5178                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5179                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5180         } else {
5181                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5182                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5183         }
5184
5185         return 0;
5186 }
5187
5188 static int
5189 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5190                              const char *value, void *opaque_arg)
5191 {
5192         struct bnxt *bp = opaque_arg;
5193         unsigned long flow_xstat;
5194         char *end = NULL;
5195
5196         if (!value || !opaque_arg) {
5197                 PMD_DRV_LOG(ERR,
5198                             "Invalid parameter passed to flow_xstat devarg.\n");
5199                 return -EINVAL;
5200         }
5201
5202         flow_xstat = strtoul(value, &end, 10);
5203         if (end == NULL || *end != '\0' ||
5204             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5205                 PMD_DRV_LOG(ERR,
5206                             "Invalid parameter passed to flow_xstat devarg.\n");
5207                 return -EINVAL;
5208         }
5209
5210         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5211                 PMD_DRV_LOG(ERR,
5212                             "Invalid value passed to flow_xstat devarg.\n");
5213                 return -EINVAL;
5214         }
5215
5216         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5217         if (BNXT_FLOW_XSTATS_EN(bp))
5218                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5219
5220         return 0;
5221 }
5222
5223 static int
5224 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5225                                         const char *value, void *opaque_arg)
5226 {
5227         struct bnxt *bp = opaque_arg;
5228         unsigned long max_num_kflows;
5229         char *end = NULL;
5230
5231         if (!value || !opaque_arg) {
5232                 PMD_DRV_LOG(ERR,
5233                         "Invalid parameter passed to max_num_kflows devarg.\n");
5234                 return -EINVAL;
5235         }
5236
5237         max_num_kflows = strtoul(value, &end, 10);
5238         if (end == NULL || *end != '\0' ||
5239                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5240                 PMD_DRV_LOG(ERR,
5241                         "Invalid parameter passed to max_num_kflows devarg.\n");
5242                 return -EINVAL;
5243         }
5244
5245         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5246                 PMD_DRV_LOG(ERR,
5247                         "Invalid value passed to max_num_kflows devarg.\n");
5248                 return -EINVAL;
5249         }
5250
5251         bp->max_num_kflows = max_num_kflows;
5252         if (bp->max_num_kflows)
5253                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5254                                 max_num_kflows);
5255
5256         return 0;
5257 }
5258
5259 static int
5260 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5261                             const char *value, void *opaque_arg)
5262 {
5263         struct bnxt_representor *vfr_bp = opaque_arg;
5264         unsigned long rep_is_pf;
5265         char *end = NULL;
5266
5267         if (!value || !opaque_arg) {
5268                 PMD_DRV_LOG(ERR,
5269                             "Invalid parameter passed to rep_is_pf devargs.\n");
5270                 return -EINVAL;
5271         }
5272
5273         rep_is_pf = strtoul(value, &end, 10);
5274         if (end == NULL || *end != '\0' ||
5275             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5276                 PMD_DRV_LOG(ERR,
5277                             "Invalid parameter passed to rep_is_pf devargs.\n");
5278                 return -EINVAL;
5279         }
5280
5281         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5282                 PMD_DRV_LOG(ERR,
5283                             "Invalid value passed to rep_is_pf devargs.\n");
5284                 return -EINVAL;
5285         }
5286
5287         vfr_bp->flags |= rep_is_pf;
5288         if (BNXT_REP_PF(vfr_bp))
5289                 PMD_DRV_LOG(INFO, "PF representor\n");
5290         else
5291                 PMD_DRV_LOG(INFO, "VF representor\n");
5292
5293         return 0;
5294 }
5295
5296 static int
5297 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5298                                const char *value, void *opaque_arg)
5299 {
5300         struct bnxt_representor *vfr_bp = opaque_arg;
5301         unsigned long rep_based_pf;
5302         char *end = NULL;
5303
5304         if (!value || !opaque_arg) {
5305                 PMD_DRV_LOG(ERR,
5306                             "Invalid parameter passed to rep_based_pf "
5307                             "devargs.\n");
5308                 return -EINVAL;
5309         }
5310
5311         rep_based_pf = strtoul(value, &end, 10);
5312         if (end == NULL || *end != '\0' ||
5313             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5314                 PMD_DRV_LOG(ERR,
5315                             "Invalid parameter passed to rep_based_pf "
5316                             "devargs.\n");
5317                 return -EINVAL;
5318         }
5319
5320         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5321                 PMD_DRV_LOG(ERR,
5322                             "Invalid value passed to rep_based_pf devargs.\n");
5323                 return -EINVAL;
5324         }
5325
5326         vfr_bp->rep_based_pf = rep_based_pf;
5327         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5328
5329         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5330
5331         return 0;
5332 }
5333
5334 static int
5335 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5336                             const char *value, void *opaque_arg)
5337 {
5338         struct bnxt_representor *vfr_bp = opaque_arg;
5339         unsigned long rep_q_r2f;
5340         char *end = NULL;
5341
5342         if (!value || !opaque_arg) {
5343                 PMD_DRV_LOG(ERR,
5344                             "Invalid parameter passed to rep_q_r2f "
5345                             "devargs.\n");
5346                 return -EINVAL;
5347         }
5348
5349         rep_q_r2f = strtoul(value, &end, 10);
5350         if (end == NULL || *end != '\0' ||
5351             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5352                 PMD_DRV_LOG(ERR,
5353                             "Invalid parameter passed to rep_q_r2f "
5354                             "devargs.\n");
5355                 return -EINVAL;
5356         }
5357
5358         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5359                 PMD_DRV_LOG(ERR,
5360                             "Invalid value passed to rep_q_r2f devargs.\n");
5361                 return -EINVAL;
5362         }
5363
5364         vfr_bp->rep_q_r2f = rep_q_r2f;
5365         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5366         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5367
5368         return 0;
5369 }
5370
5371 static int
5372 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5373                             const char *value, void *opaque_arg)
5374 {
5375         struct bnxt_representor *vfr_bp = opaque_arg;
5376         unsigned long rep_q_f2r;
5377         char *end = NULL;
5378
5379         if (!value || !opaque_arg) {
5380                 PMD_DRV_LOG(ERR,
5381                             "Invalid parameter passed to rep_q_f2r "
5382                             "devargs.\n");
5383                 return -EINVAL;
5384         }
5385
5386         rep_q_f2r = strtoul(value, &end, 10);
5387         if (end == NULL || *end != '\0' ||
5388             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5389                 PMD_DRV_LOG(ERR,
5390                             "Invalid parameter passed to rep_q_f2r "
5391                             "devargs.\n");
5392                 return -EINVAL;
5393         }
5394
5395         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5396                 PMD_DRV_LOG(ERR,
5397                             "Invalid value passed to rep_q_f2r devargs.\n");
5398                 return -EINVAL;
5399         }
5400
5401         vfr_bp->rep_q_f2r = rep_q_f2r;
5402         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5403         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5404
5405         return 0;
5406 }
5407
5408 static int
5409 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5410                              const char *value, void *opaque_arg)
5411 {
5412         struct bnxt_representor *vfr_bp = opaque_arg;
5413         unsigned long rep_fc_r2f;
5414         char *end = NULL;
5415
5416         if (!value || !opaque_arg) {
5417                 PMD_DRV_LOG(ERR,
5418                             "Invalid parameter passed to rep_fc_r2f "
5419                             "devargs.\n");
5420                 return -EINVAL;
5421         }
5422
5423         rep_fc_r2f = strtoul(value, &end, 10);
5424         if (end == NULL || *end != '\0' ||
5425             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5426                 PMD_DRV_LOG(ERR,
5427                             "Invalid parameter passed to rep_fc_r2f "
5428                             "devargs.\n");
5429                 return -EINVAL;
5430         }
5431
5432         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5433                 PMD_DRV_LOG(ERR,
5434                             "Invalid value passed to rep_fc_r2f devargs.\n");
5435                 return -EINVAL;
5436         }
5437
5438         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5439         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5440         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5441
5442         return 0;
5443 }
5444
5445 static int
5446 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5447                              const char *value, void *opaque_arg)
5448 {
5449         struct bnxt_representor *vfr_bp = opaque_arg;
5450         unsigned long rep_fc_f2r;
5451         char *end = NULL;
5452
5453         if (!value || !opaque_arg) {
5454                 PMD_DRV_LOG(ERR,
5455                             "Invalid parameter passed to rep_fc_f2r "
5456                             "devargs.\n");
5457                 return -EINVAL;
5458         }
5459
5460         rep_fc_f2r = strtoul(value, &end, 10);
5461         if (end == NULL || *end != '\0' ||
5462             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5463                 PMD_DRV_LOG(ERR,
5464                             "Invalid parameter passed to rep_fc_f2r "
5465                             "devargs.\n");
5466                 return -EINVAL;
5467         }
5468
5469         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5470                 PMD_DRV_LOG(ERR,
5471                             "Invalid value passed to rep_fc_f2r devargs.\n");
5472                 return -EINVAL;
5473         }
5474
5475         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5476         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5477         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5478
5479         return 0;
5480 }
5481
5482 static int
5483 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5484 {
5485         struct rte_kvargs *kvlist;
5486         int ret;
5487
5488         if (devargs == NULL)
5489                 return 0;
5490
5491         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5492         if (kvlist == NULL)
5493                 return -EINVAL;
5494
5495         /*
5496          * Handler for "truflow" devarg.
5497          * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5498          */
5499         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5500                                  bnxt_parse_devarg_truflow, bp);
5501         if (ret)
5502                 goto err;
5503
5504         /*
5505          * Handler for "flow_xstat" devarg.
5506          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5507          */
5508         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5509                                  bnxt_parse_devarg_flow_xstat, bp);
5510         if (ret)
5511                 goto err;
5512
5513         /*
5514          * Handler for "max_num_kflows" devarg.
5515          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5516          */
5517         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5518                                  bnxt_parse_devarg_max_num_kflows, bp);
5519         if (ret)
5520                 goto err;
5521
5522 err:
5523         rte_kvargs_free(kvlist);
5524         return ret;
5525 }
5526
5527 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5528 {
5529         int rc = 0;
5530
5531         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5532                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5533                 if (rc)
5534                         PMD_DRV_LOG(ERR,
5535                                     "Failed to alloc switch domain: %d\n", rc);
5536                 else
5537                         PMD_DRV_LOG(INFO,
5538                                     "Switch domain allocated %d\n",
5539                                     bp->switch_domain_id);
5540         }
5541
5542         return rc;
5543 }
5544
5545 /* Allocate and initialize various fields in bnxt struct that
5546  * need to be allocated/destroyed only once in the lifetime of the driver
5547  */
5548 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5549 {
5550         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5551         struct bnxt *bp = eth_dev->data->dev_private;
5552         int rc = 0;
5553
5554         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5555
5556         if (bnxt_vf_pciid(pci_dev->id.device_id))
5557                 bp->flags |= BNXT_FLAG_VF;
5558
5559         if (bnxt_p5_device(pci_dev->id.device_id))
5560                 bp->flags |= BNXT_FLAG_CHIP_P5;
5561
5562         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5563             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5564             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5565             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5566                 bp->flags |= BNXT_FLAG_STINGRAY;
5567
5568         if (BNXT_TRUFLOW_EN(bp)) {
5569                 /* extra mbuf field is required to store CFA code from mark */
5570                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5571                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5572                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5573                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5574                 };
5575                 bnxt_cfa_code_dynfield_offset =
5576                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5577                 if (bnxt_cfa_code_dynfield_offset < 0) {
5578                         PMD_DRV_LOG(ERR,
5579                             "Failed to register mbuf field for TruFlow mark\n");
5580                         return -rte_errno;
5581                 }
5582         }
5583
5584         rc = bnxt_map_pci_bars(eth_dev);
5585         if (rc) {
5586                 PMD_DRV_LOG(ERR,
5587                             "Failed to initialize board rc: %x\n", rc);
5588                 return rc;
5589         }
5590
5591         rc = bnxt_alloc_pf_info(bp);
5592         if (rc)
5593                 return rc;
5594
5595         rc = bnxt_alloc_link_info(bp);
5596         if (rc)
5597                 return rc;
5598
5599         rc = bnxt_alloc_parent_info(bp);
5600         if (rc)
5601                 return rc;
5602
5603         rc = bnxt_alloc_hwrm_resources(bp);
5604         if (rc) {
5605                 PMD_DRV_LOG(ERR,
5606                             "Failed to allocate response buffer rc: %x\n", rc);
5607                 return rc;
5608         }
5609         rc = bnxt_alloc_leds_info(bp);
5610         if (rc)
5611                 return rc;
5612
5613         rc = bnxt_alloc_cos_queues(bp);
5614         if (rc)
5615                 return rc;
5616
5617         rc = bnxt_init_locks(bp);
5618         if (rc)
5619                 return rc;
5620
5621         rc = bnxt_alloc_switch_domain(bp);
5622         if (rc)
5623                 return rc;
5624
5625         return rc;
5626 }
5627
5628 static int
5629 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5630 {
5631         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5632         static int version_printed;
5633         struct bnxt *bp;
5634         int rc;
5635
5636         if (version_printed++ == 0)
5637                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5638
5639         eth_dev->dev_ops = &bnxt_dev_ops;
5640         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5641         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5642         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5643         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5644         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5645
5646         /*
5647          * For secondary processes, we don't initialise any further
5648          * as primary has already done this work.
5649          */
5650         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5651                 return 0;
5652
5653         rte_eth_copy_pci_info(eth_dev, pci_dev);
5654         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5655
5656         bp = eth_dev->data->dev_private;
5657
5658         /* Parse dev arguments passed on when starting the DPDK application. */
5659         rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5660         if (rc)
5661                 goto error_free;
5662
5663         rc = bnxt_drv_init(eth_dev);
5664         if (rc)
5665                 goto error_free;
5666
5667         rc = bnxt_init_resources(bp, false);
5668         if (rc)
5669                 goto error_free;
5670
5671         rc = bnxt_alloc_stats_mem(bp);
5672         if (rc)
5673                 goto error_free;
5674
5675         PMD_DRV_LOG(INFO,
5676                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5677                     pci_dev->mem_resource[0].phys_addr,
5678                     pci_dev->mem_resource[0].addr);
5679
5680         return 0;
5681
5682 error_free:
5683         bnxt_dev_uninit(eth_dev);
5684         return rc;
5685 }
5686
5687
5688 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5689 {
5690         if (!ctx)
5691                 return;
5692
5693         if (ctx->va)
5694                 rte_free(ctx->va);
5695
5696         ctx->va = NULL;
5697         ctx->dma = RTE_BAD_IOVA;
5698         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5699 }
5700
5701 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5702 {
5703         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5704                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5705                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5706                                   bp->flow_stat->max_fc,
5707                                   false);
5708
5709         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5710                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5711                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5712                                   bp->flow_stat->max_fc,
5713                                   false);
5714
5715         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5716                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5717         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5718
5719         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5720                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5721         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5722
5723         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5724                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5725         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5726
5727         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5728                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5729         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5730 }
5731
5732 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5733 {
5734         bnxt_unregister_fc_ctx_mem(bp);
5735
5736         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5737         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5738         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5739         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5740 }
5741
5742 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5743 {
5744         if (BNXT_FLOW_XSTATS_EN(bp))
5745                 bnxt_uninit_fc_ctx_mem(bp);
5746 }
5747
5748 static void
5749 bnxt_free_error_recovery_info(struct bnxt *bp)
5750 {
5751         rte_free(bp->recovery_info);
5752         bp->recovery_info = NULL;
5753         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5754 }
5755
5756 static int
5757 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5758 {
5759         int rc;
5760
5761         bnxt_free_int(bp);
5762         bnxt_free_mem(bp, reconfig_dev);
5763
5764         bnxt_hwrm_func_buf_unrgtr(bp);
5765         if (bp->pf != NULL) {
5766                 rte_free(bp->pf->vf_req_buf);
5767                 bp->pf->vf_req_buf = NULL;
5768         }
5769
5770         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5771         bp->flags &= ~BNXT_FLAG_REGISTERED;
5772         bnxt_free_ctx_mem(bp);
5773         if (!reconfig_dev) {
5774                 bnxt_free_hwrm_resources(bp);
5775                 bnxt_free_error_recovery_info(bp);
5776         }
5777
5778         bnxt_uninit_ctx_mem(bp);
5779
5780         bnxt_free_flow_stats_info(bp);
5781         if (bp->rep_info != NULL)
5782                 bnxt_free_switch_domain(bp);
5783         bnxt_free_rep_info(bp);
5784         rte_free(bp->ptp_cfg);
5785         bp->ptp_cfg = NULL;
5786         return rc;
5787 }
5788
5789 static int
5790 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5791 {
5792         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5793                 return -EPERM;
5794
5795         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5796
5797         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5798                 bnxt_dev_close_op(eth_dev);
5799
5800         return 0;
5801 }
5802
5803 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5804 {
5805         struct bnxt *bp = eth_dev->data->dev_private;
5806         struct rte_eth_dev *vf_rep_eth_dev;
5807         int ret = 0, i;
5808
5809         if (!bp)
5810                 return -EINVAL;
5811
5812         for (i = 0; i < bp->num_reps; i++) {
5813                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5814                 if (!vf_rep_eth_dev)
5815                         continue;
5816                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5817                             vf_rep_eth_dev->data->port_id);
5818                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5819         }
5820         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5821                     eth_dev->data->port_id);
5822         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5823
5824         return ret;
5825 }
5826
5827 static void bnxt_free_rep_info(struct bnxt *bp)
5828 {
5829         rte_free(bp->rep_info);
5830         bp->rep_info = NULL;
5831         rte_free(bp->cfa_code_map);
5832         bp->cfa_code_map = NULL;
5833 }
5834
5835 static int bnxt_init_rep_info(struct bnxt *bp)
5836 {
5837         int i = 0, rc;
5838
5839         if (bp->rep_info)
5840                 return 0;
5841
5842         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5843                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5844                                    0);
5845         if (!bp->rep_info) {
5846                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5847                 return -ENOMEM;
5848         }
5849         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5850                                        sizeof(*bp->cfa_code_map) *
5851                                        BNXT_MAX_CFA_CODE, 0);
5852         if (!bp->cfa_code_map) {
5853                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5854                 bnxt_free_rep_info(bp);
5855                 return -ENOMEM;
5856         }
5857
5858         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5859                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5860
5861         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5862         if (rc) {
5863                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5864                 bnxt_free_rep_info(bp);
5865                 return rc;
5866         }
5867
5868         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5869         if (rc) {
5870                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5871                 bnxt_free_rep_info(bp);
5872                 return rc;
5873         }
5874
5875         return rc;
5876 }
5877
5878 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5879                                struct rte_eth_devargs *eth_da,
5880                                struct rte_eth_dev *backing_eth_dev,
5881                                const char *dev_args)
5882 {
5883         struct rte_eth_dev *vf_rep_eth_dev;
5884         char name[RTE_ETH_NAME_MAX_LEN];
5885         struct bnxt *backing_bp;
5886         uint16_t num_rep;
5887         int i, ret = 0;
5888         struct rte_kvargs *kvlist = NULL;
5889
5890         if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
5891                 return 0;
5892         if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
5893                 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
5894                             eth_da->type);
5895                 return -ENOTSUP;
5896         }
5897         num_rep = eth_da->nb_representor_ports;
5898         if (num_rep > BNXT_MAX_VF_REPS) {
5899                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5900                             num_rep, BNXT_MAX_VF_REPS);
5901                 return -EINVAL;
5902         }
5903
5904         if (num_rep >= RTE_MAX_ETHPORTS) {
5905                 PMD_DRV_LOG(ERR,
5906                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5907                             num_rep, RTE_MAX_ETHPORTS);
5908                 return -EINVAL;
5909         }
5910
5911         backing_bp = backing_eth_dev->data->dev_private;
5912
5913         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5914                 PMD_DRV_LOG(ERR,
5915                             "Not a PF or trusted VF. No Representor support\n");
5916                 /* Returning an error is not an option.
5917                  * Applications are not handling this correctly
5918                  */
5919                 return 0;
5920         }
5921
5922         if (bnxt_init_rep_info(backing_bp))
5923                 return 0;
5924
5925         for (i = 0; i < num_rep; i++) {
5926                 struct bnxt_representor representor = {
5927                         .vf_id = eth_da->representor_ports[i],
5928                         .switch_domain_id = backing_bp->switch_domain_id,
5929                         .parent_dev = backing_eth_dev
5930                 };
5931
5932                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5933                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5934                                     representor.vf_id, BNXT_MAX_VF_REPS);
5935                         continue;
5936                 }
5937
5938                 /* representor port net_bdf_port */
5939                 snprintf(name, sizeof(name), "net_%s_representor_%d",
5940                          pci_dev->device.name, eth_da->representor_ports[i]);
5941
5942                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5943                 if (kvlist) {
5944                         /*
5945                          * Handler for "rep_is_pf" devarg.
5946                          * Invoked as for ex: "-a 000:00:0d.0,
5947                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5948                          */
5949                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5950                                                  bnxt_parse_devarg_rep_is_pf,
5951                                                  (void *)&representor);
5952                         if (ret) {
5953                                 ret = -EINVAL;
5954                                 goto err;
5955                         }
5956                         /*
5957                          * Handler for "rep_based_pf" devarg.
5958                          * Invoked as for ex: "-a 000:00:0d.0,
5959                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5960                          */
5961                         ret = rte_kvargs_process(kvlist,
5962                                                  BNXT_DEVARG_REP_BASED_PF,
5963                                                  bnxt_parse_devarg_rep_based_pf,
5964                                                  (void *)&representor);
5965                         if (ret) {
5966                                 ret = -EINVAL;
5967                                 goto err;
5968                         }
5969                         /*
5970                          * Handler for "rep_based_pf" devarg.
5971                          * Invoked as for ex: "-a 000:00:0d.0,
5972                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5973                          */
5974                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5975                                                  bnxt_parse_devarg_rep_q_r2f,
5976                                                  (void *)&representor);
5977                         if (ret) {
5978                                 ret = -EINVAL;
5979                                 goto err;
5980                         }
5981                         /*
5982                          * Handler for "rep_based_pf" devarg.
5983                          * Invoked as for ex: "-a 000:00:0d.0,
5984                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5985                          */
5986                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5987                                                  bnxt_parse_devarg_rep_q_f2r,
5988                                                  (void *)&representor);
5989                         if (ret) {
5990                                 ret = -EINVAL;
5991                                 goto err;
5992                         }
5993                         /*
5994                          * Handler for "rep_based_pf" devarg.
5995                          * Invoked as for ex: "-a 000:00:0d.0,
5996                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5997                          */
5998                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5999                                                  bnxt_parse_devarg_rep_fc_r2f,
6000                                                  (void *)&representor);
6001                         if (ret) {
6002                                 ret = -EINVAL;
6003                                 goto err;
6004                         }
6005                         /*
6006                          * Handler for "rep_based_pf" devarg.
6007                          * Invoked as for ex: "-a 000:00:0d.0,
6008                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6009                          */
6010                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6011                                                  bnxt_parse_devarg_rep_fc_f2r,
6012                                                  (void *)&representor);
6013                         if (ret) {
6014                                 ret = -EINVAL;
6015                                 goto err;
6016                         }
6017                 }
6018
6019                 ret = rte_eth_dev_create(&pci_dev->device, name,
6020                                          sizeof(struct bnxt_representor),
6021                                          NULL, NULL,
6022                                          bnxt_representor_init,
6023                                          &representor);
6024                 if (ret) {
6025                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6026                                     "representor %s.", name);
6027                         goto err;
6028                 }
6029
6030                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6031                 if (!vf_rep_eth_dev) {
6032                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6033                                     " for VF-Rep: %s.", name);
6034                         ret = -ENODEV;
6035                         goto err;
6036                 }
6037
6038                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6039                             backing_eth_dev->data->port_id);
6040                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6041                                                          vf_rep_eth_dev;
6042                 backing_bp->num_reps++;
6043
6044         }
6045
6046         rte_kvargs_free(kvlist);
6047         return 0;
6048
6049 err:
6050         /* If num_rep > 1, then rollback already created
6051          * ports, since we'll be failing the probe anyway
6052          */
6053         if (num_rep > 1)
6054                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6055         rte_errno = -ret;
6056         rte_kvargs_free(kvlist);
6057
6058         return ret;
6059 }
6060
6061 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6062                           struct rte_pci_device *pci_dev)
6063 {
6064         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6065         struct rte_eth_dev *backing_eth_dev;
6066         uint16_t num_rep;
6067         int ret = 0;
6068
6069         if (pci_dev->device.devargs) {
6070                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6071                                             &eth_da);
6072                 if (ret)
6073                         return ret;
6074         }
6075
6076         num_rep = eth_da.nb_representor_ports;
6077         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6078                     num_rep);
6079
6080         /* We could come here after first level of probe is already invoked
6081          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6082          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6083          */
6084         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6085         if (backing_eth_dev == NULL) {
6086                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6087                                          sizeof(struct bnxt),
6088                                          eth_dev_pci_specific_init, pci_dev,
6089                                          bnxt_dev_init, NULL);
6090
6091                 if (ret || !num_rep)
6092                         return ret;
6093
6094                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6095         }
6096         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6097                     backing_eth_dev->data->port_id);
6098
6099         if (!num_rep)
6100                 return ret;
6101
6102         /* probe representor ports now */
6103         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
6104                                   pci_dev->device.devargs->args);
6105
6106         return ret;
6107 }
6108
6109 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6110 {
6111         struct rte_eth_dev *eth_dev;
6112
6113         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6114         if (!eth_dev)
6115                 return 0; /* Invoked typically only by OVS-DPDK, by the
6116                            * time it comes here the eth_dev is already
6117                            * deleted by rte_eth_dev_close(), so returning
6118                            * +ve value will at least help in proper cleanup
6119                            */
6120
6121         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6122         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6123                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6124                         return rte_eth_dev_destroy(eth_dev,
6125                                                    bnxt_representor_uninit);
6126                 else
6127                         return rte_eth_dev_destroy(eth_dev,
6128                                                    bnxt_dev_uninit);
6129         } else {
6130                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6131         }
6132 }
6133
6134 static struct rte_pci_driver bnxt_rte_pmd = {
6135         .id_table = bnxt_pci_id_map,
6136         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6137                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6138                                                   * and OVS-DPDK
6139                                                   */
6140         .probe = bnxt_pci_probe,
6141         .remove = bnxt_pci_remove,
6142 };
6143
6144 static bool
6145 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6146 {
6147         if (strcmp(dev->device->driver->name, drv->driver.name))
6148                 return false;
6149
6150         return true;
6151 }
6152
6153 bool is_bnxt_supported(struct rte_eth_dev *dev)
6154 {
6155         return is_device_supported(dev, &bnxt_rte_pmd);
6156 }
6157
6158 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6159 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6160 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6161 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");