drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29 #include "bnxt_util.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  37
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  42 #define BROADCOM_DEV_ID_57301 0x16c8
  43 #define BROADCOM_DEV_ID_57302 0x16c9
  44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  47 #define BROADCOM_DEV_ID_NS2 0x16cd
  48 #define BROADCOM_DEV_ID_57311 0x16ce
  49 #define BROADCOM_DEV_ID_57312 0x16cf
  50 #define BROADCOM_DEV_ID_57402 0x16d0
  51 #define BROADCOM_DEV_ID_57404 0x16d1
  52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  56 #define BROADCOM_DEV_ID_57412 0x16d6
  57 #define BROADCOM_DEV_ID_57414 0x16d7
  58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  61 #define BROADCOM_DEV_ID_57412_MF 0x16de
  62 #define BROADCOM_DEV_ID_57314 0x16df
  63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  74 #define BROADCOM_DEV_ID_57508 0x1750
  75 #define BROADCOM_DEV_ID_57504 0x1751
  76 #define BROADCOM_DEV_ID_57502 0x1752
  77 #define BROADCOM_DEV_ID_57500_VF1 0x1806
  78 #define BROADCOM_DEV_ID_57500_VF2 0x1807
  79 #define BROADCOM_DEV_ID_58802 0xd802
  80 #define BROADCOM_DEV_ID_58804 0xd804
  81 #define BROADCOM_DEV_ID_58808 0x16f0
  82 #define BROADCOM_DEV_ID_58802_VF 0xd800
  83
  84 static const struct rte_pci_id bnxt_pci_id_map[] = {
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  86                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  88                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 130         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
 131         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
 132         { .vendor_id = 0, /* sentinel */ },
 133 };
 134
 135 #define BNXT_ETH_RSS_SUPPORT (  \
 136         ETH_RSS_IPV4 |          \
 137         ETH_RSS_NONFRAG_IPV4_TCP |      \
 138         ETH_RSS_NONFRAG_IPV4_UDP |      \
 139         ETH_RSS_IPV6 |          \
 140         ETH_RSS_NONFRAG_IPV6_TCP |      \
 141         ETH_RSS_NONFRAG_IPV6_UDP)
 142
 143 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 144                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 145                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 146                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 147                                      DEV_TX_OFFLOAD_TCP_TSO | \
 148                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 149                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 150                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 152                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 153                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 154
 155 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 156                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 157                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 158                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 159                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 160                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 161                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 162                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 163                                      DEV_RX_OFFLOAD_TCP_LRO)
 164
 165 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 166 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 167 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 168 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 169
 170 /***********************/
 171
 172 /*
 173  * High level utility functions
 174  */
 175
 176 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 177 {
 178         if (!BNXT_CHIP_THOR(bp))
 179                 return 1;
 180
 181         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 182                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 183                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 184 }
 185
 186 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 187 {
 188         if (!BNXT_CHIP_THOR(bp))
 189                 return HW_HASH_INDEX_SIZE;
 190
 191         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 192 }
 193
 194 static void bnxt_free_mem(struct bnxt *bp)
 195 {
 196         bnxt_free_filter_mem(bp);
 197         bnxt_free_vnic_attributes(bp);
 198         bnxt_free_vnic_mem(bp);
 199
 200         bnxt_free_stats(bp);
 201         bnxt_free_tx_rings(bp);
 202         bnxt_free_rx_rings(bp);
 203 }
 204
 205 static int bnxt_alloc_mem(struct bnxt *bp)
 206 {
 207         int rc;
 208
 209         rc = bnxt_alloc_vnic_mem(bp);
 210         if (rc)
 211                 goto alloc_mem_err;
 212
 213         rc = bnxt_alloc_vnic_attributes(bp);
 214         if (rc)
 215                 goto alloc_mem_err;
 216
 217         rc = bnxt_alloc_filter_mem(bp);
 218         if (rc)
 219                 goto alloc_mem_err;
 220
 221         return 0;
 222
 223 alloc_mem_err:
 224         bnxt_free_mem(bp);
 225         return rc;
 226 }
 227
 228 static int bnxt_init_chip(struct bnxt *bp)
 229 {
 230         struct bnxt_rx_queue *rxq;
 231         struct rte_eth_link new;
 232         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 233         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 234         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 235         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 236         uint32_t intr_vector = 0;
 237         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 238         uint32_t vec = BNXT_MISC_VEC_ID;
 239         unsigned int i, j;
 240         int rc;
 241
 242         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 243                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 244                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 245                 bp->flags |= BNXT_FLAG_JUMBO;
 246         } else {
 247                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 248                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 249                 bp->flags &= ~BNXT_FLAG_JUMBO;
 250         }
 251
 252         /* THOR does not support ring groups.
 253          * But we will use the array to save RSS context IDs.
 254          */
 255         if (BNXT_CHIP_THOR(bp))
 256                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 257
 258         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 259         if (rc) {
 260                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 261                 goto err_out;
 262         }
 263
 264         rc = bnxt_alloc_hwrm_rings(bp);
 265         if (rc) {
 266                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 267                 goto err_out;
 268         }
 269
 270         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 271         if (rc) {
 272                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 273                 goto err_out;
 274         }
 275
 276         rc = bnxt_mq_rx_configure(bp);
 277         if (rc) {
 278                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 279                 goto err_out;
 280         }
 281
 282         /* VNIC configuration */
 283         for (i = 0; i < bp->nr_vnics; i++) {
 284                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 285                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 286                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 287
 288                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 289                 if (!vnic->fw_grp_ids) {
 290                         PMD_DRV_LOG(ERR,
 291                                     "Failed to alloc %d bytes for group ids\n",
 292                                     size);
 293                         rc = -ENOMEM;
 294                         goto err_out;
 295                 }
 296                 memset(vnic->fw_grp_ids, -1, size);
 297
 298                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 299                             i, vnic, vnic->fw_grp_ids);
 300
 301                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 302                 if (rc) {
 303                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 304                                 i, rc);
 305                         goto err_out;
 306                 }
 307
 308                 /* Alloc RSS context only if RSS mode is enabled */
 309                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 310                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 311
 312                         rc = 0;
 313                         for (j = 0; j < nr_ctxs; j++) {
 314                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 315                                 if (rc)
 316                                         break;
 317                         }
 318                         if (rc) {
 319                                 PMD_DRV_LOG(ERR,
 320                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 321                                   i, j, rc);
 322                                 goto err_out;
 323                         }
 324                         vnic->num_lb_ctxts = nr_ctxs;
 325                 }
 326
 327                 /*
 328                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 329                  * setting is not available at this time, it will not be
 330                  * configured correctly in the CFA.
 331                  */
 332                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 333                         vnic->vlan_strip = true;
 334                 else
 335                         vnic->vlan_strip = false;
 336
 337                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 338                 if (rc) {
 339                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 340                                 i, rc);
 341                         goto err_out;
 342                 }
 343
 344                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 345                 if (rc) {
 346                         PMD_DRV_LOG(ERR,
 347                                 "HWRM vnic %d filter failure rc: %x\n",
 348                                 i, rc);
 349                         goto err_out;
 350                 }
 351
 352                 for (j = 0; j < bp->rx_nr_rings; j++) {
 353                         rxq = bp->eth_dev->data->rx_queues[j];
 354
 355                         PMD_DRV_LOG(DEBUG,
 356                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 357                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 358
 359                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 360                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 361                 }
 362
 363                 rc = bnxt_vnic_rss_configure(bp, vnic);
 364                 if (rc) {
 365                         PMD_DRV_LOG(ERR,
 366                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 367                         goto err_out;
 368                 }
 369
 370                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 371
 372                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 373                     DEV_RX_OFFLOAD_TCP_LRO)
 374                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 375                 else
 376                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 377         }
 378         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 379         if (rc) {
 380                 PMD_DRV_LOG(ERR,
 381                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 382                 goto err_out;
 383         }
 384
 385         /* check and configure queue intr-vector mapping */
 386         if ((rte_intr_cap_multiple(intr_handle) ||
 387              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 388             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 389                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 390                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 391                 if (intr_vector > bp->rx_cp_nr_rings) {
 392                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 393                                         bp->rx_cp_nr_rings);
 394                         return -ENOTSUP;
 395                 }
 396                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 397                 if (rc)
 398                         return rc;
 399         }
 400
 401         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 402                 intr_handle->intr_vec =
 403                         rte_zmalloc("intr_vec",
 404                                     bp->eth_dev->data->nb_rx_queues *
 405                                     sizeof(int), 0);
 406                 if (intr_handle->intr_vec == NULL) {
 407                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 408                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 409                         rc = -ENOMEM;
 410                         goto err_disable;
 411                 }
 412                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 413                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 414                          intr_handle->intr_vec, intr_handle->nb_efd,
 415                         intr_handle->max_intr);
 416                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 417                      queue_id++) {
 418                         intr_handle->intr_vec[queue_id] =
 419                                                         vec + BNXT_RX_VEC_START;
 420                         if (vec < base + intr_handle->nb_efd - 1)
 421                                 vec++;
 422                 }
 423         }
 424
 425         /* enable uio/vfio intr/eventfd mapping */
 426         rc = rte_intr_enable(intr_handle);
 427         if (rc)
 428                 goto err_free;
 429
 430         rc = bnxt_get_hwrm_link_config(bp, &new);
 431         if (rc) {
 432                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 433                 goto err_free;
 434         }
 435
 436         if (!bp->link_info.link_up) {
 437                 rc = bnxt_set_hwrm_link_config(bp, true);
 438                 if (rc) {
 439                         PMD_DRV_LOG(ERR,
 440                                 "HWRM link config failure rc: %x\n", rc);
 441                         goto err_free;
 442                 }
 443         }
 444         bnxt_print_link_info(bp->eth_dev);
 445
 446         return 0;
 447
 448 err_free:
 449         rte_free(intr_handle->intr_vec);
 450 err_disable:
 451         rte_intr_efd_disable(intr_handle);
 452 err_out:
 453         /* Some of the error status returned by FW may not be from errno.h */
 454         if (rc > 0)
 455                 rc = -EIO;
 456
 457         return rc;
 458 }
 459
 460 static int bnxt_shutdown_nic(struct bnxt *bp)
 461 {
 462         bnxt_free_all_hwrm_resources(bp);
 463         bnxt_free_all_filters(bp);
 464         bnxt_free_all_vnics(bp);
 465         return 0;
 466 }
 467
 468 static int bnxt_init_nic(struct bnxt *bp)
 469 {
 470         int rc;
 471
 472         if (BNXT_HAS_RING_GRPS(bp)) {
 473                 rc = bnxt_init_ring_grps(bp);
 474                 if (rc)
 475                         return rc;
 476         }
 477
 478         bnxt_init_vnics(bp);
 479         bnxt_init_filters(bp);
 480
 481         return 0;
 482 }
 483
 484 /*
 485  * Device configuration and status function
 486  */
 487
 488 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 489                                   struct rte_eth_dev_info *dev_info)
 490 {
 491         struct bnxt *bp = eth_dev->data->dev_private;
 492         uint16_t max_vnics, i, j, vpool, vrxq;
 493         unsigned int max_rx_rings;
 494
 495         /* MAC Specifics */
 496         dev_info->max_mac_addrs = bp->max_l2_ctx;
 497         dev_info->max_hash_mac_addrs = 0;
 498
 499         /* PF/VF specifics */
 500         if (BNXT_PF(bp))
 501                 dev_info->max_vfs = bp->pdev->max_vfs;
 502         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 503         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 504         dev_info->max_rx_queues = max_rx_rings;
 505         dev_info->max_tx_queues = max_rx_rings;
 506         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 507         dev_info->hash_key_size = 40;
 508         max_vnics = bp->max_vnics;
 509
 510         /* Fast path specifics */
 511         dev_info->min_rx_bufsize = 1;
 512         dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
 513                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
 514
 515         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 516         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 517                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 518         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 519         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 520
 521         /* *INDENT-OFF* */
 522         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 523                 .rx_thresh = {
 524                         .pthresh = 8,
 525                         .hthresh = 8,
 526                         .wthresh = 0,
 527                 },
 528                 .rx_free_thresh = 32,
 529                 /* If no descriptors available, pkts are dropped by default */
 530                 .rx_drop_en = 1,
 531         };
 532
 533         dev_info->default_txconf = (struct rte_eth_txconf) {
 534                 .tx_thresh = {
 535                         .pthresh = 32,
 536                         .hthresh = 0,
 537                         .wthresh = 0,
 538                 },
 539                 .tx_free_thresh = 32,
 540                 .tx_rs_thresh = 32,
 541         };
 542         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 543
 544         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 545         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 546         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 547         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 548         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 549
 550         /* *INDENT-ON* */
 551
 552         /*
 553          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 554          *       need further investigation.
 555          */
 556
 557         /* VMDq resources */
 558         vpool = 64; /* ETH_64_POOLS */
 559         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 560         for (i = 0; i < 4; vpool >>= 1, i++) {
 561                 if (max_vnics > vpool) {
 562                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 563                                 if (dev_info->max_rx_queues > vrxq) {
 564                                         if (vpool > vrxq)
 565                                                 vpool = vrxq;
 566                                         goto found;
 567                                 }
 568                         }
 569                         /* Not enough resources to support VMDq */
 570                         break;
 571                 }
 572         }
 573         /* Not enough resources to support VMDq */
 574         vpool = 0;
 575         vrxq = 0;
 576 found:
 577         dev_info->max_vmdq_pools = vpool;
 578         dev_info->vmdq_queue_num = vrxq;
 579
 580         dev_info->vmdq_pool_base = 0;
 581         dev_info->vmdq_queue_base = 0;
 582 }
 583
 584 /* Configure the device based on the configuration provided */
 585 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 586 {
 587         struct bnxt *bp = eth_dev->data->dev_private;
 588         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 589         int rc;
 590
 591         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 592         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 593         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 594         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 595
 596         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 597                 rc = bnxt_hwrm_check_vf_rings(bp);
 598                 if (rc) {
 599                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 600                         return -ENOSPC;
 601                 }
 602
 603                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 604                 if (rc) {
 605                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 606                         return -ENOSPC;
 607                 }
 608         } else {
 609                 /* legacy driver needs to get updated values */
 610                 rc = bnxt_hwrm_func_qcaps(bp);
 611                 if (rc) {
 612                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 613                         return rc;
 614                 }
 615         }
 616
 617         /* Inherit new configurations */
 618         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 619             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 620             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 621             bp->max_cp_rings ||
 622             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 623             bp->max_stat_ctx)
 624                 goto resource_error;
 625
 626         if (BNXT_HAS_RING_GRPS(bp) &&
 627             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 628                 goto resource_error;
 629
 630         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 631             bp->max_vnics < eth_dev->data->nb_rx_queues)
 632                 goto resource_error;
 633
 634         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 635         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 636
 637         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 638                 eth_dev->data->mtu =
 639                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 640                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 641                         BNXT_NUM_VLANS;
 642                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 643         }
 644         return 0;
 645
 646 resource_error:
 647         PMD_DRV_LOG(ERR,
 648                     "Insufficient resources to support requested config\n");
 649         PMD_DRV_LOG(ERR,
 650                     "Num Queues Requested: Tx %d, Rx %d\n",
 651                     eth_dev->data->nb_tx_queues,
 652                     eth_dev->data->nb_rx_queues);
 653         PMD_DRV_LOG(ERR,
 654                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 655                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 656                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 657         return -ENOSPC;
 658 }
 659
 660 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 661 {
 662         struct rte_eth_link *link = &eth_dev->data->dev_link;
 663
 664         if (link->link_status)
 665                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 666                         eth_dev->data->port_id,
 667                         (uint32_t)link->link_speed,
 668                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 669                         ("full-duplex") : ("half-duplex\n"));
 670         else
 671                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 672                         eth_dev->data->port_id);
 673 }
 674
 675 /*
 676  * Determine whether the current configuration requires support for scattered
 677  * receive; return 1 if scattered receive is required and 0 if not.
 678  */
 679 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 680 {
 681         uint16_t buf_size;
 682         int i;
 683
 684         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 685                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 686
 687                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 688                                       RTE_PKTMBUF_HEADROOM);
 689                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 690                         return 1;
 691         }
 692         return 0;
 693 }
 694
 695 static eth_rx_burst_t
 696 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 697 {
 698 #ifdef RTE_ARCH_X86
 699         /*
 700          * Vector mode receive can be enabled only if scatter rx is not
 701          * in use and rx offloads are limited to VLAN stripping and
 702          * CRC stripping.
 703          */
 704         if (!eth_dev->data->scattered_rx &&
 705             !(eth_dev->data->dev_conf.rxmode.offloads &
 706               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 707                 DEV_RX_OFFLOAD_KEEP_CRC |
 708                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 709                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 710                 DEV_RX_OFFLOAD_UDP_CKSUM |
 711                 DEV_RX_OFFLOAD_TCP_CKSUM |
 712                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 713                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 714                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 715                             eth_dev->data->port_id);
 716                 return bnxt_recv_pkts_vec;
 717         }
 718         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 719                     eth_dev->data->port_id);
 720         PMD_DRV_LOG(INFO,
 721                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 722                     eth_dev->data->port_id,
 723                     eth_dev->data->scattered_rx,
 724                     eth_dev->data->dev_conf.rxmode.offloads);
 725 #endif
 726         return bnxt_recv_pkts;
 727 }
 728
 729 static eth_tx_burst_t
 730 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 731 {
 732 #ifdef RTE_ARCH_X86
 733         /*
 734          * Vector mode transmit can be enabled only if not using scatter rx
 735          * or tx offloads.
 736          */
 737         if (!eth_dev->data->scattered_rx &&
 738             !eth_dev->data->dev_conf.txmode.offloads) {
 739                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 740                             eth_dev->data->port_id);
 741                 return bnxt_xmit_pkts_vec;
 742         }
 743         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 744                     eth_dev->data->port_id);
 745         PMD_DRV_LOG(INFO,
 746                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 747                     eth_dev->data->port_id,
 748                     eth_dev->data->scattered_rx,
 749                     eth_dev->data->dev_conf.txmode.offloads);
 750 #endif
 751         return bnxt_xmit_pkts;
 752 }
 753
 754 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 755 {
 756         struct bnxt *bp = eth_dev->data->dev_private;
 757         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 758         int vlan_mask = 0;
 759         int rc;
 760
 761         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 762                 PMD_DRV_LOG(ERR,
 763                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 764                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 765         }
 766
 767         rc = bnxt_init_chip(bp);
 768         if (rc)
 769                 goto error;
 770
 771         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 772
 773         bnxt_link_update_op(eth_dev, 1);
 774
 775         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 776                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 777         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 778                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 779         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 780         if (rc)
 781                 goto error;
 782
 783         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 784         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 785         bnxt_enable_int(bp);
 786         bp->flags |= BNXT_FLAG_INIT_DONE;
 787         bp->dev_stopped = 0;
 788         return 0;
 789
 790 error:
 791         bnxt_shutdown_nic(bp);
 792         bnxt_free_tx_mbufs(bp);
 793         bnxt_free_rx_mbufs(bp);
 794         return rc;
 795 }
 796
 797 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 798 {
 799         struct bnxt *bp = eth_dev->data->dev_private;
 800         int rc = 0;
 801
 802         if (!bp->link_info.link_up)
 803                 rc = bnxt_set_hwrm_link_config(bp, true);
 804         if (!rc)
 805                 eth_dev->data->dev_link.link_status = 1;
 806
 807         bnxt_print_link_info(eth_dev);
 808         return 0;
 809 }
 810
 811 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 812 {
 813         struct bnxt *bp = eth_dev->data->dev_private;
 814
 815         eth_dev->data->dev_link.link_status = 0;
 816         bnxt_set_hwrm_link_config(bp, false);
 817         bp->link_info.link_up = 0;
 818
 819         return 0;
 820 }
 821
 822 /* Unload the driver, release resources */
 823 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 824 {
 825         struct bnxt *bp = eth_dev->data->dev_private;
 826         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 827         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 828
 829         bnxt_disable_int(bp);
 830
 831         /* disable uio/vfio intr/eventfd mapping */
 832         rte_intr_disable(intr_handle);
 833
 834         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 835         if (bp->eth_dev->data->dev_started) {
 836                 /* TBD: STOP HW queues DMA */
 837                 eth_dev->data->dev_link.link_status = 0;
 838         }
 839         bnxt_set_hwrm_link_config(bp, false);
 840
 841         /* Clean queue intr-vector mapping */
 842         rte_intr_efd_disable(intr_handle);
 843         if (intr_handle->intr_vec != NULL) {
 844                 rte_free(intr_handle->intr_vec);
 845                 intr_handle->intr_vec = NULL;
 846         }
 847
 848         bnxt_hwrm_port_clr_stats(bp);
 849         bnxt_free_tx_mbufs(bp);
 850         bnxt_free_rx_mbufs(bp);
 851         bnxt_shutdown_nic(bp);
 852         bp->dev_stopped = 1;
 853 }
 854
 855 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 856 {
 857         struct bnxt *bp = eth_dev->data->dev_private;
 858
 859         if (bp->dev_stopped == 0)
 860                 bnxt_dev_stop_op(eth_dev);
 861
 862         if (eth_dev->data->mac_addrs != NULL) {
 863                 rte_free(eth_dev->data->mac_addrs);
 864                 eth_dev->data->mac_addrs = NULL;
 865         }
 866         if (bp->grp_info != NULL) {
 867                 rte_free(bp->grp_info);
 868                 bp->grp_info = NULL;
 869         }
 870
 871         bnxt_dev_uninit(eth_dev);
 872 }
 873
 874 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 875                                     uint32_t index)
 876 {
 877         struct bnxt *bp = eth_dev->data->dev_private;
 878         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 879         struct bnxt_vnic_info *vnic;
 880         struct bnxt_filter_info *filter, *temp_filter;
 881         uint32_t i;
 882
 883         /*
 884          * Loop through all VNICs from the specified filter flow pools to
 885          * remove the corresponding MAC addr filter
 886          */
 887         for (i = 0; i < bp->nr_vnics; i++) {
 888                 if (!(pool_mask & (1ULL << i)))
 889                         continue;
 890
 891                 vnic = &bp->vnic_info[i];
 892                 filter = STAILQ_FIRST(&vnic->filter);
 893                 while (filter) {
 894                         temp_filter = STAILQ_NEXT(filter, next);
 895                         if (filter->mac_index == index) {
 896                                 STAILQ_REMOVE(&vnic->filter, filter,
 897                                                 bnxt_filter_info, next);
 898                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 899                                 filter->mac_index = INVALID_MAC_INDEX;
 900                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 901                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 902                                                    filter, next);
 903                         }
 904                         filter = temp_filter;
 905                 }
 906         }
 907 }
 908
 909 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 910                                 struct rte_ether_addr *mac_addr,
 911                                 uint32_t index, uint32_t pool)
 912 {
 913         struct bnxt *bp = eth_dev->data->dev_private;
 914         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
 915         struct bnxt_filter_info *filter;
 916         int rc = 0;
 917
 918         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
 919                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
 920                 return -ENOTSUP;
 921         }
 922
 923         if (!vnic) {
 924                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
 925                 return -EINVAL;
 926         }
 927         /* Attach requested MAC address to the new l2_filter */
 928         STAILQ_FOREACH(filter, &vnic->filter, next) {
 929                 if (filter->mac_index == index) {
 930                         PMD_DRV_LOG(ERR,
 931                                 "MAC addr already existed for pool %d\n", pool);
 932                         return 0;
 933                 }
 934         }
 935         filter = bnxt_alloc_filter(bp);
 936         if (!filter) {
 937                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
 938                 return -ENODEV;
 939         }
 940
 941         filter->mac_index = index;
 942         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
 943
 944         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 945         if (!rc) {
 946                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 947         } else {
 948                 filter->mac_index = INVALID_MAC_INDEX;
 949                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 950                 bnxt_free_filter(bp, filter);
 951         }
 952
 953         return rc;
 954 }
 955
 956 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 957 {
 958         int rc = 0;
 959         struct bnxt *bp = eth_dev->data->dev_private;
 960         struct rte_eth_link new;
 961         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 962
 963         memset(&new, 0, sizeof(new));
 964         do {
 965                 /* Retrieve link info from hardware */
 966                 rc = bnxt_get_hwrm_link_config(bp, &new);
 967                 if (rc) {
 968                         new.link_speed = ETH_LINK_SPEED_100M;
 969                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 970                         PMD_DRV_LOG(ERR,
 971                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 972                         goto out;
 973                 }
 974
 975                 if (!wait_to_complete || new.link_status)
 976                         break;
 977
 978                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 979         } while (cnt--);
 980
 981 out:
 982         /* Timed out or success */
 983         if (new.link_status != eth_dev->data->dev_link.link_status ||
 984         new.link_speed != eth_dev->data->dev_link.link_speed) {
 985                 memcpy(&eth_dev->data->dev_link, &new,
 986                         sizeof(struct rte_eth_link));
 987
 988                 _rte_eth_dev_callback_process(eth_dev,
 989                                               RTE_ETH_EVENT_INTR_LSC,
 990                                               NULL);
 991
 992                 bnxt_print_link_info(eth_dev);
 993         }
 994
 995         return rc;
 996 }
 997
 998 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
 999 {
1000         struct bnxt *bp = eth_dev->data->dev_private;
1001         struct bnxt_vnic_info *vnic;
1002
1003         if (bp->vnic_info == NULL)
1004                 return;
1005
1006         vnic = &bp->vnic_info[0];
1007
1008         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1009         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1010 }
1011
1012 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1013 {
1014         struct bnxt *bp = eth_dev->data->dev_private;
1015         struct bnxt_vnic_info *vnic;
1016
1017         if (bp->vnic_info == NULL)
1018                 return;
1019
1020         vnic = &bp->vnic_info[0];
1021
1022         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1023         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1024 }
1025
1026 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1027 {
1028         struct bnxt *bp = eth_dev->data->dev_private;
1029         struct bnxt_vnic_info *vnic;
1030
1031         if (bp->vnic_info == NULL)
1032                 return;
1033
1034         vnic = &bp->vnic_info[0];
1035
1036         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1037         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1038 }
1039
1040 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1041 {
1042         struct bnxt *bp = eth_dev->data->dev_private;
1043         struct bnxt_vnic_info *vnic;
1044
1045         if (bp->vnic_info == NULL)
1046                 return;
1047
1048         vnic = &bp->vnic_info[0];
1049
1050         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1051         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1052 }
1053
1054 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1055 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1056 {
1057         if (qid >= bp->rx_nr_rings)
1058                 return NULL;
1059
1060         return bp->eth_dev->data->rx_queues[qid];
1061 }
1062
1063 /* Return rxq corresponding to a given rss table ring/group ID. */
1064 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1065 {
1066         struct bnxt_rx_queue *rxq;
1067         unsigned int i;
1068
1069         if (!BNXT_HAS_RING_GRPS(bp)) {
1070                 for (i = 0; i < bp->rx_nr_rings; i++) {
1071                         rxq = bp->eth_dev->data->rx_queues[i];
1072                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1073                                 return rxq->index;
1074                 }
1075         } else {
1076                 for (i = 0; i < bp->rx_nr_rings; i++) {
1077                         if (bp->grp_info[i].fw_grp_id == fwr)
1078                                 return i;
1079                 }
1080         }
1081
1082         return INVALID_HW_RING_ID;
1083 }
1084
1085 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1086                             struct rte_eth_rss_reta_entry64 *reta_conf,
1087                             uint16_t reta_size)
1088 {
1089         struct bnxt *bp = eth_dev->data->dev_private;
1090         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1091         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1092         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1093         uint16_t idx, sft;
1094         int i;
1095
1096         if (!vnic->rss_table)
1097                 return -EINVAL;
1098
1099         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1100                 return -EINVAL;
1101
1102         if (reta_size != tbl_size) {
1103                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1104                         "(%d) must equal the size supported by the hardware "
1105                         "(%d)\n", reta_size, tbl_size);
1106                 return -EINVAL;
1107         }
1108
1109         for (i = 0; i < reta_size; i++) {
1110                 struct bnxt_rx_queue *rxq;
1111
1112                 idx = i / RTE_RETA_GROUP_SIZE;
1113                 sft = i % RTE_RETA_GROUP_SIZE;
1114
1115                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1116                         continue;
1117
1118                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1119                 if (!rxq) {
1120                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1121                         return -EINVAL;
1122                 }
1123
1124                 if (BNXT_CHIP_THOR(bp)) {
1125                         vnic->rss_table[i * 2] =
1126                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1127                         vnic->rss_table[i * 2 + 1] =
1128                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1129                 } else {
1130                         vnic->rss_table[i] =
1131                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1132                 }
1133
1134                 vnic->rss_table[i] =
1135                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1136         }
1137
1138         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1139         return 0;
1140 }
1141
1142 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1143                               struct rte_eth_rss_reta_entry64 *reta_conf,
1144                               uint16_t reta_size)
1145 {
1146         struct bnxt *bp = eth_dev->data->dev_private;
1147         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1148         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1149         uint16_t idx, sft, i;
1150
1151         /* Retrieve from the default VNIC */
1152         if (!vnic)
1153                 return -EINVAL;
1154         if (!vnic->rss_table)
1155                 return -EINVAL;
1156
1157         if (reta_size != tbl_size) {
1158                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1159                         "(%d) must equal the size supported by the hardware "
1160                         "(%d)\n", reta_size, tbl_size);
1161                 return -EINVAL;
1162         }
1163
1164         for (idx = 0, i = 0; i < reta_size; i++) {
1165                 idx = i / RTE_RETA_GROUP_SIZE;
1166                 sft = i % RTE_RETA_GROUP_SIZE;
1167
1168                 if (reta_conf[idx].mask & (1ULL << sft)) {
1169                         uint16_t qid;
1170
1171                         if (BNXT_CHIP_THOR(bp))
1172                                 qid = bnxt_rss_to_qid(bp,
1173                                                       vnic->rss_table[i * 2]);
1174                         else
1175                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1176
1177                         if (qid == INVALID_HW_RING_ID) {
1178                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1179                                 return -EINVAL;
1180                         }
1181                         reta_conf[idx].reta[sft] = qid;
1182                 }
1183         }
1184
1185         return 0;
1186 }
1187
1188 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1189                                    struct rte_eth_rss_conf *rss_conf)
1190 {
1191         struct bnxt *bp = eth_dev->data->dev_private;
1192         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1193         struct bnxt_vnic_info *vnic;
1194         uint16_t hash_type = 0;
1195         unsigned int i;
1196
1197         /*
1198          * If RSS enablement were different than dev_configure,
1199          * then return -EINVAL
1200          */
1201         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1202                 if (!rss_conf->rss_hf)
1203                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1204         } else {
1205                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1206                         return -EINVAL;
1207         }
1208
1209         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1210         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1211
1212         if (rss_conf->rss_hf & ETH_RSS_IPV4)
1213                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1214         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1215                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1216         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1217                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1218         if (rss_conf->rss_hf & ETH_RSS_IPV6)
1219                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1220         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1221                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1222         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1223                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1224
1225         /* Update the RSS VNIC(s) */
1226         for (i = 0; i < bp->nr_vnics; i++) {
1227                 vnic = &bp->vnic_info[i];
1228                 vnic->hash_type = hash_type;
1229
1230                 /*
1231                  * Use the supplied key if the key length is
1232                  * acceptable and the rss_key is not NULL
1233                  */
1234                 if (rss_conf->rss_key &&
1235                     rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1236                         memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1237                                rss_conf->rss_key_len);
1238
1239                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1240         }
1241         return 0;
1242 }
1243
1244 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1245                                      struct rte_eth_rss_conf *rss_conf)
1246 {
1247         struct bnxt *bp = eth_dev->data->dev_private;
1248         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1249         int len;
1250         uint32_t hash_types;
1251
1252         /* RSS configuration is the same for all VNICs */
1253         if (vnic && vnic->rss_hash_key) {
1254                 if (rss_conf->rss_key) {
1255                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1256                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1257                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1258                 }
1259
1260                 hash_types = vnic->hash_type;
1261                 rss_conf->rss_hf = 0;
1262                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1263                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1264                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1265                 }
1266                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1267                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1268                         hash_types &=
1269                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1270                 }
1271                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1272                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1273                         hash_types &=
1274                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1275                 }
1276                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1277                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1278                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1279                 }
1280                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1281                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1282                         hash_types &=
1283                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1284                 }
1285                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1286                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1287                         hash_types &=
1288                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1289                 }
1290                 if (hash_types) {
1291                         PMD_DRV_LOG(ERR,
1292                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1293                                 vnic->hash_type);
1294                         return -ENOTSUP;
1295                 }
1296         } else {
1297                 rss_conf->rss_hf = 0;
1298         }
1299         return 0;
1300 }
1301
1302 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1303                                struct rte_eth_fc_conf *fc_conf)
1304 {
1305         struct bnxt *bp = dev->data->dev_private;
1306         struct rte_eth_link link_info;
1307         int rc;
1308
1309         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1310         if (rc)
1311                 return rc;
1312
1313         memset(fc_conf, 0, sizeof(*fc_conf));
1314         if (bp->link_info.auto_pause)
1315                 fc_conf->autoneg = 1;
1316         switch (bp->link_info.pause) {
1317         case 0:
1318                 fc_conf->mode = RTE_FC_NONE;
1319                 break;
1320         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1321                 fc_conf->mode = RTE_FC_TX_PAUSE;
1322                 break;
1323         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1324                 fc_conf->mode = RTE_FC_RX_PAUSE;
1325                 break;
1326         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1327                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1328                 fc_conf->mode = RTE_FC_FULL;
1329                 break;
1330         }
1331         return 0;
1332 }
1333
1334 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1335                                struct rte_eth_fc_conf *fc_conf)
1336 {
1337         struct bnxt *bp = dev->data->dev_private;
1338
1339         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1340                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1341                 return -ENOTSUP;
1342         }
1343
1344         switch (fc_conf->mode) {
1345         case RTE_FC_NONE:
1346                 bp->link_info.auto_pause = 0;
1347                 bp->link_info.force_pause = 0;
1348                 break;
1349         case RTE_FC_RX_PAUSE:
1350                 if (fc_conf->autoneg) {
1351                         bp->link_info.auto_pause =
1352                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1353                         bp->link_info.force_pause = 0;
1354                 } else {
1355                         bp->link_info.auto_pause = 0;
1356                         bp->link_info.force_pause =
1357                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1358                 }
1359                 break;
1360         case RTE_FC_TX_PAUSE:
1361                 if (fc_conf->autoneg) {
1362                         bp->link_info.auto_pause =
1363                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1364                         bp->link_info.force_pause = 0;
1365                 } else {
1366                         bp->link_info.auto_pause = 0;
1367                         bp->link_info.force_pause =
1368                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1369                 }
1370                 break;
1371         case RTE_FC_FULL:
1372                 if (fc_conf->autoneg) {
1373                         bp->link_info.auto_pause =
1374                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1375                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1376                         bp->link_info.force_pause = 0;
1377                 } else {
1378                         bp->link_info.auto_pause = 0;
1379                         bp->link_info.force_pause =
1380                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1381                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1382                 }
1383                 break;
1384         }
1385         return bnxt_set_hwrm_link_config(bp, true);
1386 }
1387
1388 /* Add UDP tunneling port */
1389 static int
1390 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1391                          struct rte_eth_udp_tunnel *udp_tunnel)
1392 {
1393         struct bnxt *bp = eth_dev->data->dev_private;
1394         uint16_t tunnel_type = 0;
1395         int rc = 0;
1396
1397         switch (udp_tunnel->prot_type) {
1398         case RTE_TUNNEL_TYPE_VXLAN:
1399                 if (bp->vxlan_port_cnt) {
1400                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1401                                 udp_tunnel->udp_port);
1402                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1403                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1404                                 return -ENOSPC;
1405                         }
1406                         bp->vxlan_port_cnt++;
1407                         return 0;
1408                 }
1409                 tunnel_type =
1410                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1411                 bp->vxlan_port_cnt++;
1412                 break;
1413         case RTE_TUNNEL_TYPE_GENEVE:
1414                 if (bp->geneve_port_cnt) {
1415                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1416                                 udp_tunnel->udp_port);
1417                         if (bp->geneve_port != udp_tunnel->udp_port) {
1418                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1419                                 return -ENOSPC;
1420                         }
1421                         bp->geneve_port_cnt++;
1422                         return 0;
1423                 }
1424                 tunnel_type =
1425                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1426                 bp->geneve_port_cnt++;
1427                 break;
1428         default:
1429                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1430                 return -ENOTSUP;
1431         }
1432         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1433                                              tunnel_type);
1434         return rc;
1435 }
1436
1437 static int
1438 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1439                          struct rte_eth_udp_tunnel *udp_tunnel)
1440 {
1441         struct bnxt *bp = eth_dev->data->dev_private;
1442         uint16_t tunnel_type = 0;
1443         uint16_t port = 0;
1444         int rc = 0;
1445
1446         switch (udp_tunnel->prot_type) {
1447         case RTE_TUNNEL_TYPE_VXLAN:
1448                 if (!bp->vxlan_port_cnt) {
1449                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1450                         return -EINVAL;
1451                 }
1452                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1453                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1454                                 udp_tunnel->udp_port, bp->vxlan_port);
1455                         return -EINVAL;
1456                 }
1457                 if (--bp->vxlan_port_cnt)
1458                         return 0;
1459
1460                 tunnel_type =
1461                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1462                 port = bp->vxlan_fw_dst_port_id;
1463                 break;
1464         case RTE_TUNNEL_TYPE_GENEVE:
1465                 if (!bp->geneve_port_cnt) {
1466                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1467                         return -EINVAL;
1468                 }
1469                 if (bp->geneve_port != udp_tunnel->udp_port) {
1470                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1471                                 udp_tunnel->udp_port, bp->geneve_port);
1472                         return -EINVAL;
1473                 }
1474                 if (--bp->geneve_port_cnt)
1475                         return 0;
1476
1477                 tunnel_type =
1478                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1479                 port = bp->geneve_fw_dst_port_id;
1480                 break;
1481         default:
1482                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1483                 return -ENOTSUP;
1484         }
1485
1486         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1487         if (!rc) {
1488                 if (tunnel_type ==
1489                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1490                         bp->vxlan_port = 0;
1491                 if (tunnel_type ==
1492                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1493                         bp->geneve_port = 0;
1494         }
1495         return rc;
1496 }
1497
1498 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1499 {
1500         struct bnxt_filter_info *filter;
1501         struct bnxt_vnic_info *vnic;
1502         int rc = 0;
1503         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1504
1505         /* if VLAN exists && VLAN matches vlan_id
1506          *      remove the MAC+VLAN filter
1507          *      add a new MAC only filter
1508          * else
1509          *      VLAN filter doesn't exist, just skip and continue
1510          */
1511         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1512         filter = STAILQ_FIRST(&vnic->filter);
1513         while (filter) {
1514                 /* Search for this matching MAC+VLAN filter */
1515                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1516                     !memcmp(filter->l2_addr,
1517                             bp->mac_addr,
1518                             RTE_ETHER_ADDR_LEN)) {
1519                         /* Delete the filter */
1520                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1521                         if (rc)
1522                                 return rc;
1523                         STAILQ_REMOVE(&vnic->filter, filter,
1524                                       bnxt_filter_info, next);
1525                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1526
1527                         PMD_DRV_LOG(INFO,
1528                                     "Del Vlan filter for %d\n",
1529                                     vlan_id);
1530                         return rc;
1531                 }
1532                 filter = STAILQ_NEXT(filter, next);
1533         }
1534         return -ENOENT;
1535 }
1536
1537 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1538 {
1539         struct bnxt_filter_info *filter;
1540         struct bnxt_vnic_info *vnic;
1541         int rc = 0;
1542         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1543                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1544         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1545
1546         /* Implementation notes on the use of VNIC in this command:
1547          *
1548          * By default, these filters belong to default vnic for the function.
1549          * Once these filters are set up, only destination VNIC can be modified.
1550          * If the destination VNIC is not specified in this command,
1551          * then the HWRM shall only create an l2 context id.
1552          */
1553
1554         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1555         filter = STAILQ_FIRST(&vnic->filter);
1556         /* Check if the VLAN has already been added */
1557         while (filter) {
1558                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1559                     !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1560                         return -EEXIST;
1561
1562                 filter = STAILQ_NEXT(filter, next);
1563         }
1564
1565         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1566          * command to create MAC+VLAN filter with the right flags, enables set.
1567          */
1568         filter = bnxt_alloc_filter(bp);
1569         if (!filter) {
1570                 PMD_DRV_LOG(ERR,
1571                             "MAC/VLAN filter alloc failed\n");
1572                 return -ENOMEM;
1573         }
1574         /* MAC + VLAN ID filter */
1575         filter->l2_ivlan = vlan_id;
1576         filter->l2_ivlan_mask = 0x0FFF;
1577         filter->enables |= en;
1578         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1579         if (rc) {
1580                 /* Free the newly allocated filter as we were
1581                  * not able to create the filter in hardware.
1582                  */
1583                 filter->fw_l2_filter_id = UINT64_MAX;
1584                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1585                 return rc;
1586         }
1587
1588         /* Add this new filter to the list */
1589         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1590         PMD_DRV_LOG(INFO,
1591                     "Added Vlan filter for %d\n", vlan_id);
1592         return rc;
1593 }
1594
1595 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1596                 uint16_t vlan_id, int on)
1597 {
1598         struct bnxt *bp = eth_dev->data->dev_private;
1599
1600         /* These operations apply to ALL existing MAC/VLAN filters */
1601         if (on)
1602                 return bnxt_add_vlan_filter(bp, vlan_id);
1603         else
1604                 return bnxt_del_vlan_filter(bp, vlan_id);
1605 }
1606
1607 static int
1608 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1609 {
1610         struct bnxt *bp = dev->data->dev_private;
1611         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1612         unsigned int i;
1613
1614         if (mask & ETH_VLAN_FILTER_MASK) {
1615                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1616                         /* Remove any VLAN filters programmed */
1617                         for (i = 0; i < 4095; i++)
1618                                 bnxt_del_vlan_filter(bp, i);
1619                 }
1620                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1621                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1622         }
1623
1624         if (mask & ETH_VLAN_STRIP_MASK) {
1625                 /* Enable or disable VLAN stripping */
1626                 for (i = 0; i < bp->nr_vnics; i++) {
1627                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1628                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1629                                 vnic->vlan_strip = true;
1630                         else
1631                                 vnic->vlan_strip = false;
1632                         bnxt_hwrm_vnic_cfg(bp, vnic);
1633                 }
1634                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1635                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1636         }
1637
1638         if (mask & ETH_VLAN_EXTEND_MASK)
1639                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1640
1641         return 0;
1642 }
1643
1644 static int
1645 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1646                         struct rte_ether_addr *addr)
1647 {
1648         struct bnxt *bp = dev->data->dev_private;
1649         /* Default Filter is tied to VNIC 0 */
1650         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1651         struct bnxt_filter_info *filter;
1652         int rc;
1653
1654         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1655                 return -EPERM;
1656
1657         if (rte_is_zero_ether_addr(addr))
1658                 return -EINVAL;
1659
1660         STAILQ_FOREACH(filter, &vnic->filter, next) {
1661                 /* Default Filter is at Index 0 */
1662                 if (filter->mac_index != 0)
1663                         continue;
1664
1665                 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1666                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1667                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1668                 filter->enables |=
1669                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1670                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1671
1672                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1673                 if (rc)
1674                         return rc;
1675
1676                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1677                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1678                 return 0;
1679         }
1680
1681         return 0;
1682 }
1683
1684 static int
1685 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1686                           struct rte_ether_addr *mc_addr_set,
1687                           uint32_t nb_mc_addr)
1688 {
1689         struct bnxt *bp = eth_dev->data->dev_private;
1690         char *mc_addr_list = (char *)mc_addr_set;
1691         struct bnxt_vnic_info *vnic;
1692         uint32_t off = 0, i = 0;
1693
1694         vnic = &bp->vnic_info[0];
1695
1696         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1697                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1698                 goto allmulti;
1699         }
1700
1701         /* TODO Check for Duplicate mcast addresses */
1702         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1703         for (i = 0; i < nb_mc_addr; i++) {
1704                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1705                         RTE_ETHER_ADDR_LEN);
1706                 off += RTE_ETHER_ADDR_LEN;
1707         }
1708
1709         vnic->mc_addr_cnt = i;
1710
1711 allmulti:
1712         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1713 }
1714
1715 static int
1716 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1717 {
1718         struct bnxt *bp = dev->data->dev_private;
1719         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1720         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1721         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1722         int ret;
1723
1724         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1725                         fw_major, fw_minor, fw_updt);
1726
1727         ret += 1; /* add the size of '\0' */
1728         if (fw_size < (uint32_t)ret)
1729                 return ret;
1730         else
1731                 return 0;
1732 }
1733
1734 static void
1735 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1736         struct rte_eth_rxq_info *qinfo)
1737 {
1738         struct bnxt_rx_queue *rxq;
1739
1740         rxq = dev->data->rx_queues[queue_id];
1741
1742         qinfo->mp = rxq->mb_pool;
1743         qinfo->scattered_rx = dev->data->scattered_rx;
1744         qinfo->nb_desc = rxq->nb_rx_desc;
1745
1746         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1747         qinfo->conf.rx_drop_en = 0;
1748         qinfo->conf.rx_deferred_start = 0;
1749 }
1750
1751 static void
1752 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1753         struct rte_eth_txq_info *qinfo)
1754 {
1755         struct bnxt_tx_queue *txq;
1756
1757         txq = dev->data->tx_queues[queue_id];
1758
1759         qinfo->nb_desc = txq->nb_tx_desc;
1760
1761         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1762         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1763         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1764
1765         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1766         qinfo->conf.tx_rs_thresh = 0;
1767         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1768 }
1769
1770 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1771 {
1772         struct bnxt *bp = eth_dev->data->dev_private;
1773         struct rte_eth_dev_info dev_info;
1774         uint32_t new_pkt_size;
1775         uint32_t rc = 0;
1776         uint32_t i;
1777
1778         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1779                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1780
1781         bnxt_dev_info_get_op(eth_dev, &dev_info);
1782
1783         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1784                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1785                         RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1786                 return -EINVAL;
1787         }
1788
1789 #ifdef RTE_ARCH_X86
1790         /*
1791          * If vector-mode tx/rx is active, disallow any MTU change that would
1792          * require scattered receive support.
1793          */
1794         if (eth_dev->data->dev_started &&
1795             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1796              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1797             (new_pkt_size >
1798              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1799                 PMD_DRV_LOG(ERR,
1800                             "MTU change would require scattered rx support. ");
1801                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1802                 return -EINVAL;
1803         }
1804 #endif
1805
1806         if (new_mtu > RTE_ETHER_MTU) {
1807                 bp->flags |= BNXT_FLAG_JUMBO;
1808                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1809                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1810         } else {
1811                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1812                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1813                 bp->flags &= ~BNXT_FLAG_JUMBO;
1814         }
1815
1816         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
1817
1818         eth_dev->data->mtu = new_mtu;
1819         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1820
1821         for (i = 0; i < bp->nr_vnics; i++) {
1822                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1823                 uint16_t size = 0;
1824
1825                 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1826                                         RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1827                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1828                 if (rc)
1829                         break;
1830
1831                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1832                 size -= RTE_PKTMBUF_HEADROOM;
1833
1834                 if (size < new_mtu) {
1835                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1836                         if (rc)
1837                                 return rc;
1838                 }
1839         }
1840
1841         return rc;
1842 }
1843
1844 static int
1845 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1846 {
1847         struct bnxt *bp = dev->data->dev_private;
1848         uint16_t vlan = bp->vlan;
1849         int rc;
1850
1851         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1852                 PMD_DRV_LOG(ERR,
1853                         "PVID cannot be modified for this function\n");
1854                 return -ENOTSUP;
1855         }
1856         bp->vlan = on ? pvid : 0;
1857
1858         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1859         if (rc)
1860                 bp->vlan = vlan;
1861         return rc;
1862 }
1863
1864 static int
1865 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1866 {
1867         struct bnxt *bp = dev->data->dev_private;
1868
1869         return bnxt_hwrm_port_led_cfg(bp, true);
1870 }
1871
1872 static int
1873 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1874 {
1875         struct bnxt *bp = dev->data->dev_private;
1876
1877         return bnxt_hwrm_port_led_cfg(bp, false);
1878 }
1879
1880 static uint32_t
1881 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1882 {
1883         uint32_t desc = 0, raw_cons = 0, cons;
1884         struct bnxt_cp_ring_info *cpr;
1885         struct bnxt_rx_queue *rxq;
1886         struct rx_pkt_cmpl *rxcmp;
1887         uint16_t cmp_type;
1888         uint8_t cmp = 1;
1889         bool valid;
1890
1891         rxq = dev->data->rx_queues[rx_queue_id];
1892         cpr = rxq->cp_ring;
1893         valid = cpr->valid;
1894
1895         while (raw_cons < rxq->nb_rx_desc) {
1896                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1897                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1898
1899                 if (!CMPL_VALID(rxcmp, valid))
1900                         goto nothing_to_do;
1901                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1902                 cmp_type = CMP_TYPE(rxcmp);
1903                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1904                         cmp = (rte_le_to_cpu_32(
1905                                         ((struct rx_tpa_end_cmpl *)
1906                                          (rxcmp))->agg_bufs_v1) &
1907                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1908                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1909                         desc++;
1910                 } else if (cmp_type == 0x11) {
1911                         desc++;
1912                         cmp = (rxcmp->agg_bufs_v1 &
1913                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1914                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1915                 } else {
1916                         cmp = 1;
1917                 }
1918 nothing_to_do:
1919                 raw_cons += cmp ? cmp : 2;
1920         }
1921
1922         return desc;
1923 }
1924
1925 static int
1926 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1927 {
1928         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1929         struct bnxt_rx_ring_info *rxr;
1930         struct bnxt_cp_ring_info *cpr;
1931         struct bnxt_sw_rx_bd *rx_buf;
1932         struct rx_pkt_cmpl *rxcmp;
1933         uint32_t cons, cp_cons;
1934
1935         if (!rxq)
1936                 return -EINVAL;
1937
1938         cpr = rxq->cp_ring;
1939         rxr = rxq->rx_ring;
1940
1941         if (offset >= rxq->nb_rx_desc)
1942                 return -EINVAL;
1943
1944         cons = RING_CMP(cpr->cp_ring_struct, offset);
1945         cp_cons = cpr->cp_raw_cons;
1946         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1947
1948         if (cons > cp_cons) {
1949                 if (CMPL_VALID(rxcmp, cpr->valid))
1950                         return RTE_ETH_RX_DESC_DONE;
1951         } else {
1952                 if (CMPL_VALID(rxcmp, !cpr->valid))
1953                         return RTE_ETH_RX_DESC_DONE;
1954         }
1955         rx_buf = &rxr->rx_buf_ring[cons];
1956         if (rx_buf->mbuf == NULL)
1957                 return RTE_ETH_RX_DESC_UNAVAIL;
1958
1959
1960         return RTE_ETH_RX_DESC_AVAIL;
1961 }
1962
1963 static int
1964 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1965 {
1966         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1967         struct bnxt_tx_ring_info *txr;
1968         struct bnxt_cp_ring_info *cpr;
1969         struct bnxt_sw_tx_bd *tx_buf;
1970         struct tx_pkt_cmpl *txcmp;
1971         uint32_t cons, cp_cons;
1972
1973         if (!txq)
1974                 return -EINVAL;
1975
1976         cpr = txq->cp_ring;
1977         txr = txq->tx_ring;
1978
1979         if (offset >= txq->nb_tx_desc)
1980                 return -EINVAL;
1981
1982         cons = RING_CMP(cpr->cp_ring_struct, offset);
1983         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1984         cp_cons = cpr->cp_raw_cons;
1985
1986         if (cons > cp_cons) {
1987                 if (CMPL_VALID(txcmp, cpr->valid))
1988                         return RTE_ETH_TX_DESC_UNAVAIL;
1989         } else {
1990                 if (CMPL_VALID(txcmp, !cpr->valid))
1991                         return RTE_ETH_TX_DESC_UNAVAIL;
1992         }
1993         tx_buf = &txr->tx_buf_ring[cons];
1994         if (tx_buf->mbuf == NULL)
1995                 return RTE_ETH_TX_DESC_DONE;
1996
1997         return RTE_ETH_TX_DESC_FULL;
1998 }
1999
2000 static struct bnxt_filter_info *
2001 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2002                                 struct rte_eth_ethertype_filter *efilter,
2003                                 struct bnxt_vnic_info *vnic0,
2004                                 struct bnxt_vnic_info *vnic,
2005                                 int *ret)
2006 {
2007         struct bnxt_filter_info *mfilter = NULL;
2008         int match = 0;
2009         *ret = 0;
2010
2011         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2012                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2013                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2014                         " ethertype filter.", efilter->ether_type);
2015                 *ret = -EINVAL;
2016                 goto exit;
2017         }
2018         if (efilter->queue >= bp->rx_nr_rings) {
2019                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2020                 *ret = -EINVAL;
2021                 goto exit;
2022         }
2023
2024         vnic0 = &bp->vnic_info[0];
2025         vnic = &bp->vnic_info[efilter->queue];
2026         if (vnic == NULL) {
2027                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2028                 *ret = -EINVAL;
2029                 goto exit;
2030         }
2031
2032         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2033                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2034                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2035                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2036                              mfilter->flags ==
2037                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2038                              mfilter->ethertype == efilter->ether_type)) {
2039                                 match = 1;
2040                                 break;
2041                         }
2042                 }
2043         } else {
2044                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2045                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2046                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2047                              mfilter->ethertype == efilter->ether_type &&
2048                              mfilter->flags ==
2049                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2050                                 match = 1;
2051                                 break;
2052                         }
2053         }
2054
2055         if (match)
2056                 *ret = -EEXIST;
2057
2058 exit:
2059         return mfilter;
2060 }
2061
2062 static int
2063 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2064                         enum rte_filter_op filter_op,
2065                         void *arg)
2066 {
2067         struct bnxt *bp = dev->data->dev_private;
2068         struct rte_eth_ethertype_filter *efilter =
2069                         (struct rte_eth_ethertype_filter *)arg;
2070         struct bnxt_filter_info *bfilter, *filter1;
2071         struct bnxt_vnic_info *vnic, *vnic0;
2072         int ret;
2073
2074         if (filter_op == RTE_ETH_FILTER_NOP)
2075                 return 0;
2076
2077         if (arg == NULL) {
2078                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2079                             filter_op);
2080                 return -EINVAL;
2081         }
2082
2083         vnic0 = &bp->vnic_info[0];
2084         vnic = &bp->vnic_info[efilter->queue];
2085
2086         switch (filter_op) {
2087         case RTE_ETH_FILTER_ADD:
2088                 bnxt_match_and_validate_ether_filter(bp, efilter,
2089                                                         vnic0, vnic, &ret);
2090                 if (ret < 0)
2091                         return ret;
2092
2093                 bfilter = bnxt_get_unused_filter(bp);
2094                 if (bfilter == NULL) {
2095                         PMD_DRV_LOG(ERR,
2096                                 "Not enough resources for a new filter.\n");
2097                         return -ENOMEM;
2098                 }
2099                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2100                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2101                        RTE_ETHER_ADDR_LEN);
2102                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2103                        RTE_ETHER_ADDR_LEN);
2104                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2105                 bfilter->ethertype = efilter->ether_type;
2106                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2107
2108                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2109                 if (filter1 == NULL) {
2110                         ret = -EINVAL;
2111                         goto cleanup;
2112                 }
2113                 bfilter->enables |=
2114                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2115                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2116
2117                 bfilter->dst_id = vnic->fw_vnic_id;
2118
2119                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2120                         bfilter->flags =
2121                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2122                 }
2123
2124                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2125                 if (ret)
2126                         goto cleanup;
2127                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2128                 break;
2129         case RTE_ETH_FILTER_DELETE:
2130                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2131                                                         vnic0, vnic, &ret);
2132                 if (ret == -EEXIST) {
2133                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2134
2135                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2136                                       next);
2137                         bnxt_free_filter(bp, filter1);
2138                 } else if (ret == 0) {
2139                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2140                 }
2141                 break;
2142         default:
2143                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2144                 ret = -EINVAL;
2145                 goto error;
2146         }
2147         return ret;
2148 cleanup:
2149         bnxt_free_filter(bp, bfilter);
2150 error:
2151         return ret;
2152 }
2153
2154 static inline int
2155 parse_ntuple_filter(struct bnxt *bp,
2156                     struct rte_eth_ntuple_filter *nfilter,
2157                     struct bnxt_filter_info *bfilter)
2158 {
2159         uint32_t en = 0;
2160
2161         if (nfilter->queue >= bp->rx_nr_rings) {
2162                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2163                 return -EINVAL;
2164         }
2165
2166         switch (nfilter->dst_port_mask) {
2167         case UINT16_MAX:
2168                 bfilter->dst_port_mask = -1;
2169                 bfilter->dst_port = nfilter->dst_port;
2170                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2171                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2172                 break;
2173         default:
2174                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2175                 return -EINVAL;
2176         }
2177
2178         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2179         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2180
2181         switch (nfilter->proto_mask) {
2182         case UINT8_MAX:
2183                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2184                         bfilter->ip_protocol = 17;
2185                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2186                         bfilter->ip_protocol = 6;
2187                 else
2188                         return -EINVAL;
2189                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2190                 break;
2191         default:
2192                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2193                 return -EINVAL;
2194         }
2195
2196         switch (nfilter->dst_ip_mask) {
2197         case UINT32_MAX:
2198                 bfilter->dst_ipaddr_mask[0] = -1;
2199                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2200                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2201                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2202                 break;
2203         default:
2204                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2205                 return -EINVAL;
2206         }
2207
2208         switch (nfilter->src_ip_mask) {
2209         case UINT32_MAX:
2210                 bfilter->src_ipaddr_mask[0] = -1;
2211                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2212                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2213                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2214                 break;
2215         default:
2216                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2217                 return -EINVAL;
2218         }
2219
2220         switch (nfilter->src_port_mask) {
2221         case UINT16_MAX:
2222                 bfilter->src_port_mask = -1;
2223                 bfilter->src_port = nfilter->src_port;
2224                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2225                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2226                 break;
2227         default:
2228                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2229                 return -EINVAL;
2230         }
2231
2232         //TODO Priority
2233         //nfilter->priority = (uint8_t)filter->priority;
2234
2235         bfilter->enables = en;
2236         return 0;
2237 }
2238
2239 static struct bnxt_filter_info*
2240 bnxt_match_ntuple_filter(struct bnxt *bp,
2241                          struct bnxt_filter_info *bfilter,
2242                          struct bnxt_vnic_info **mvnic)
2243 {
2244         struct bnxt_filter_info *mfilter = NULL;
2245         int i;
2246
2247         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2248                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2249                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2250                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2251                             bfilter->src_ipaddr_mask[0] ==
2252                             mfilter->src_ipaddr_mask[0] &&
2253                             bfilter->src_port == mfilter->src_port &&
2254                             bfilter->src_port_mask == mfilter->src_port_mask &&
2255                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2256                             bfilter->dst_ipaddr_mask[0] ==
2257                             mfilter->dst_ipaddr_mask[0] &&
2258                             bfilter->dst_port == mfilter->dst_port &&
2259                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2260                             bfilter->flags == mfilter->flags &&
2261                             bfilter->enables == mfilter->enables) {
2262                                 if (mvnic)
2263                                         *mvnic = vnic;
2264                                 return mfilter;
2265                         }
2266                 }
2267         }
2268         return NULL;
2269 }
2270
2271 static int
2272 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2273                        struct rte_eth_ntuple_filter *nfilter,
2274                        enum rte_filter_op filter_op)
2275 {
2276         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2277         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2278         int ret;
2279
2280         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2281                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2282                 return -EINVAL;
2283         }
2284
2285         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2286                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2287                 return -EINVAL;
2288         }
2289
2290         bfilter = bnxt_get_unused_filter(bp);
2291         if (bfilter == NULL) {
2292                 PMD_DRV_LOG(ERR,
2293                         "Not enough resources for a new filter.\n");
2294                 return -ENOMEM;
2295         }
2296         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2297         if (ret < 0)
2298                 goto free_filter;
2299
2300         vnic = &bp->vnic_info[nfilter->queue];
2301         vnic0 = &bp->vnic_info[0];
2302         filter1 = STAILQ_FIRST(&vnic0->filter);
2303         if (filter1 == NULL) {
2304                 ret = -EINVAL;
2305                 goto free_filter;
2306         }
2307
2308         bfilter->dst_id = vnic->fw_vnic_id;
2309         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2310         bfilter->enables |=
2311                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2312         bfilter->ethertype = 0x800;
2313         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2314
2315         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2316
2317         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2318             bfilter->dst_id == mfilter->dst_id) {
2319                 PMD_DRV_LOG(ERR, "filter exists.\n");
2320                 ret = -EEXIST;
2321                 goto free_filter;
2322         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2323                    bfilter->dst_id != mfilter->dst_id) {
2324                 mfilter->dst_id = vnic->fw_vnic_id;
2325                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2326                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2327                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2328                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2329                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2330                 goto free_filter;
2331         }
2332         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2333                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2334                 ret = -ENOENT;
2335                 goto free_filter;
2336         }
2337
2338         if (filter_op == RTE_ETH_FILTER_ADD) {
2339                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2340                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2341                 if (ret)
2342                         goto free_filter;
2343                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2344         } else {
2345                 if (mfilter == NULL) {
2346                         /* This should not happen. But for Coverity! */
2347                         ret = -ENOENT;
2348                         goto free_filter;
2349                 }
2350                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2351
2352                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2353                 bnxt_free_filter(bp, mfilter);
2354                 mfilter->fw_l2_filter_id = -1;
2355                 bnxt_free_filter(bp, bfilter);
2356                 bfilter->fw_l2_filter_id = -1;
2357         }
2358
2359         return 0;
2360 free_filter:
2361         bfilter->fw_l2_filter_id = -1;
2362         bnxt_free_filter(bp, bfilter);
2363         return ret;
2364 }
2365
2366 static int
2367 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2368                         enum rte_filter_op filter_op,
2369                         void *arg)
2370 {
2371         struct bnxt *bp = dev->data->dev_private;
2372         int ret;
2373
2374         if (filter_op == RTE_ETH_FILTER_NOP)
2375                 return 0;
2376
2377         if (arg == NULL) {
2378                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2379                             filter_op);
2380                 return -EINVAL;
2381         }
2382
2383         switch (filter_op) {
2384         case RTE_ETH_FILTER_ADD:
2385                 ret = bnxt_cfg_ntuple_filter(bp,
2386                         (struct rte_eth_ntuple_filter *)arg,
2387                         filter_op);
2388                 break;
2389         case RTE_ETH_FILTER_DELETE:
2390                 ret = bnxt_cfg_ntuple_filter(bp,
2391                         (struct rte_eth_ntuple_filter *)arg,
2392                         filter_op);
2393                 break;
2394         default:
2395                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2396                 ret = -EINVAL;
2397                 break;
2398         }
2399         return ret;
2400 }
2401
2402 static int
2403 bnxt_parse_fdir_filter(struct bnxt *bp,
2404                        struct rte_eth_fdir_filter *fdir,
2405                        struct bnxt_filter_info *filter)
2406 {
2407         enum rte_fdir_mode fdir_mode =
2408                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2409         struct bnxt_vnic_info *vnic0, *vnic;
2410         struct bnxt_filter_info *filter1;
2411         uint32_t en = 0;
2412         int i;
2413
2414         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2415                 return -EINVAL;
2416
2417         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2418         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2419
2420         switch (fdir->input.flow_type) {
2421         case RTE_ETH_FLOW_IPV4:
2422         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2423                 /* FALLTHROUGH */
2424                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2425                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2426                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2427                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2428                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2429                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2430                 filter->ip_addr_type =
2431                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2432                 filter->src_ipaddr_mask[0] = 0xffffffff;
2433                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2434                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2435                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2436                 filter->ethertype = 0x800;
2437                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2438                 break;
2439         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2440                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2441                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2442                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2443                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2444                 filter->dst_port_mask = 0xffff;
2445                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2446                 filter->src_port_mask = 0xffff;
2447                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2448                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2449                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2450                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2451                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2452                 filter->ip_protocol = 6;
2453                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2454                 filter->ip_addr_type =
2455                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2456                 filter->src_ipaddr_mask[0] = 0xffffffff;
2457                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2458                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2459                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2460                 filter->ethertype = 0x800;
2461                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2462                 break;
2463         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2464                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2465                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2466                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2467                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2468                 filter->dst_port_mask = 0xffff;
2469                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2470                 filter->src_port_mask = 0xffff;
2471                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2472                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2473                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2474                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2475                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2476                 filter->ip_protocol = 17;
2477                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2478                 filter->ip_addr_type =
2479                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2480                 filter->src_ipaddr_mask[0] = 0xffffffff;
2481                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2482                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2483                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2484                 filter->ethertype = 0x800;
2485                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2486                 break;
2487         case RTE_ETH_FLOW_IPV6:
2488         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2489                 /* FALLTHROUGH */
2490                 filter->ip_addr_type =
2491                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2492                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2493                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2494                 rte_memcpy(filter->src_ipaddr,
2495                            fdir->input.flow.ipv6_flow.src_ip, 16);
2496                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2497                 rte_memcpy(filter->dst_ipaddr,
2498                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2499                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2500                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2501                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2502                 memset(filter->src_ipaddr_mask, 0xff, 16);
2503                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2504                 filter->ethertype = 0x86dd;
2505                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2506                 break;
2507         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2508                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2509                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2510                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2511                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2512                 filter->dst_port_mask = 0xffff;
2513                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2514                 filter->src_port_mask = 0xffff;
2515                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2516                 filter->ip_addr_type =
2517                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2518                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2519                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2520                 rte_memcpy(filter->src_ipaddr,
2521                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2522                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2523                 rte_memcpy(filter->dst_ipaddr,
2524                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2525                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2526                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2527                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2528                 memset(filter->src_ipaddr_mask, 0xff, 16);
2529                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2530                 filter->ethertype = 0x86dd;
2531                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2532                 break;
2533         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2534                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2535                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2536                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2537                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2538                 filter->dst_port_mask = 0xffff;
2539                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2540                 filter->src_port_mask = 0xffff;
2541                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2542                 filter->ip_addr_type =
2543                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2544                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2545                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2546                 rte_memcpy(filter->src_ipaddr,
2547                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2548                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2549                 rte_memcpy(filter->dst_ipaddr,
2550                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2551                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2552                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2553                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2554                 memset(filter->src_ipaddr_mask, 0xff, 16);
2555                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2556                 filter->ethertype = 0x86dd;
2557                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2558                 break;
2559         case RTE_ETH_FLOW_L2_PAYLOAD:
2560                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2561                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2562                 break;
2563         case RTE_ETH_FLOW_VXLAN:
2564                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2565                         return -EINVAL;
2566                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2567                 filter->tunnel_type =
2568                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2569                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2570                 break;
2571         case RTE_ETH_FLOW_NVGRE:
2572                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2573                         return -EINVAL;
2574                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2575                 filter->tunnel_type =
2576                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2577                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2578                 break;
2579         case RTE_ETH_FLOW_UNKNOWN:
2580         case RTE_ETH_FLOW_RAW:
2581         case RTE_ETH_FLOW_FRAG_IPV4:
2582         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2583         case RTE_ETH_FLOW_FRAG_IPV6:
2584         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2585         case RTE_ETH_FLOW_IPV6_EX:
2586         case RTE_ETH_FLOW_IPV6_TCP_EX:
2587         case RTE_ETH_FLOW_IPV6_UDP_EX:
2588         case RTE_ETH_FLOW_GENEVE:
2589                 /* FALLTHROUGH */
2590         default:
2591                 return -EINVAL;
2592         }
2593
2594         vnic0 = &bp->vnic_info[0];
2595         vnic = &bp->vnic_info[fdir->action.rx_queue];
2596         if (vnic == NULL) {
2597                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2598                 return -EINVAL;
2599         }
2600
2601
2602         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2603                 rte_memcpy(filter->dst_macaddr,
2604                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2605                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2606         }
2607
2608         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2609                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2610                 filter1 = STAILQ_FIRST(&vnic0->filter);
2611                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2612         } else {
2613                 filter->dst_id = vnic->fw_vnic_id;
2614                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2615                         if (filter->dst_macaddr[i] == 0x00)
2616                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2617                         else
2618                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2619         }
2620
2621         if (filter1 == NULL)
2622                 return -EINVAL;
2623
2624         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2625         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2626
2627         filter->enables = en;
2628
2629         return 0;
2630 }
2631
2632 static struct bnxt_filter_info *
2633 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2634                 struct bnxt_vnic_info **mvnic)
2635 {
2636         struct bnxt_filter_info *mf = NULL;
2637         int i;
2638
2639         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2640                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2641
2642                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2643                         if (mf->filter_type == nf->filter_type &&
2644                             mf->flags == nf->flags &&
2645                             mf->src_port == nf->src_port &&
2646                             mf->src_port_mask == nf->src_port_mask &&
2647                             mf->dst_port == nf->dst_port &&
2648                             mf->dst_port_mask == nf->dst_port_mask &&
2649                             mf->ip_protocol == nf->ip_protocol &&
2650                             mf->ip_addr_type == nf->ip_addr_type &&
2651                             mf->ethertype == nf->ethertype &&
2652                             mf->vni == nf->vni &&
2653                             mf->tunnel_type == nf->tunnel_type &&
2654                             mf->l2_ovlan == nf->l2_ovlan &&
2655                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2656                             mf->l2_ivlan == nf->l2_ivlan &&
2657                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2658                             !memcmp(mf->l2_addr, nf->l2_addr,
2659                                     RTE_ETHER_ADDR_LEN) &&
2660                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2661                                     RTE_ETHER_ADDR_LEN) &&
2662                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2663                                     RTE_ETHER_ADDR_LEN) &&
2664                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2665                                     RTE_ETHER_ADDR_LEN) &&
2666                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2667                                     sizeof(nf->src_ipaddr)) &&
2668                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2669                                     sizeof(nf->src_ipaddr_mask)) &&
2670                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2671                                     sizeof(nf->dst_ipaddr)) &&
2672                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2673                                     sizeof(nf->dst_ipaddr_mask))) {
2674                                 if (mvnic)
2675                                         *mvnic = vnic;
2676                                 return mf;
2677                         }
2678                 }
2679         }
2680         return NULL;
2681 }
2682
2683 static int
2684 bnxt_fdir_filter(struct rte_eth_dev *dev,
2685                  enum rte_filter_op filter_op,
2686                  void *arg)
2687 {
2688         struct bnxt *bp = dev->data->dev_private;
2689         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2690         struct bnxt_filter_info *filter, *match;
2691         struct bnxt_vnic_info *vnic, *mvnic;
2692         int ret = 0, i;
2693
2694         if (filter_op == RTE_ETH_FILTER_NOP)
2695                 return 0;
2696
2697         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2698                 return -EINVAL;
2699
2700         switch (filter_op) {
2701         case RTE_ETH_FILTER_ADD:
2702         case RTE_ETH_FILTER_DELETE:
2703                 /* FALLTHROUGH */
2704                 filter = bnxt_get_unused_filter(bp);
2705                 if (filter == NULL) {
2706                         PMD_DRV_LOG(ERR,
2707                                 "Not enough resources for a new flow.\n");
2708                         return -ENOMEM;
2709                 }
2710
2711                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2712                 if (ret != 0)
2713                         goto free_filter;
2714                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2715
2716                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2717                         vnic = &bp->vnic_info[0];
2718                 else
2719                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2720
2721                 match = bnxt_match_fdir(bp, filter, &mvnic);
2722                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2723                         if (match->dst_id == vnic->fw_vnic_id) {
2724                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2725                                 ret = -EEXIST;
2726                                 goto free_filter;
2727                         } else {
2728                                 match->dst_id = vnic->fw_vnic_id;
2729                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2730                                                                   match->dst_id,
2731                                                                   match);
2732                                 STAILQ_REMOVE(&mvnic->filter, match,
2733                                               bnxt_filter_info, next);
2734                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2735                                 PMD_DRV_LOG(ERR,
2736                                         "Filter with matching pattern exist\n");
2737                                 PMD_DRV_LOG(ERR,
2738                                         "Updated it to new destination q\n");
2739                                 goto free_filter;
2740                         }
2741                 }
2742                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2743                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2744                         ret = -ENOENT;
2745                         goto free_filter;
2746                 }
2747
2748                 if (filter_op == RTE_ETH_FILTER_ADD) {
2749                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2750                                                           filter->dst_id,
2751                                                           filter);
2752                         if (ret)
2753                                 goto free_filter;
2754                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2755                 } else {
2756                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2757                         STAILQ_REMOVE(&vnic->filter, match,
2758                                       bnxt_filter_info, next);
2759                         bnxt_free_filter(bp, match);
2760                         filter->fw_l2_filter_id = -1;
2761                         bnxt_free_filter(bp, filter);
2762                 }
2763                 break;
2764         case RTE_ETH_FILTER_FLUSH:
2765                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2766                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2767
2768                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2769                                 if (filter->filter_type ==
2770                                     HWRM_CFA_NTUPLE_FILTER) {
2771                                         ret =
2772                                         bnxt_hwrm_clear_ntuple_filter(bp,
2773                                                                       filter);
2774                                         STAILQ_REMOVE(&vnic->filter, filter,
2775                                                       bnxt_filter_info, next);
2776                                 }
2777                         }
2778                 }
2779                 return ret;
2780         case RTE_ETH_FILTER_UPDATE:
2781         case RTE_ETH_FILTER_STATS:
2782         case RTE_ETH_FILTER_INFO:
2783                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2784                 break;
2785         default:
2786                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2787                 ret = -EINVAL;
2788                 break;
2789         }
2790         return ret;
2791
2792 free_filter:
2793         filter->fw_l2_filter_id = -1;
2794         bnxt_free_filter(bp, filter);
2795         return ret;
2796 }
2797
2798 static int
2799 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2800                     enum rte_filter_type filter_type,
2801                     enum rte_filter_op filter_op, void *arg)
2802 {
2803         int ret = 0;
2804
2805         switch (filter_type) {
2806         case RTE_ETH_FILTER_TUNNEL:
2807                 PMD_DRV_LOG(ERR,
2808                         "filter type: %d: To be implemented\n", filter_type);
2809                 break;
2810         case RTE_ETH_FILTER_FDIR:
2811                 ret = bnxt_fdir_filter(dev, filter_op, arg);
2812                 break;
2813         case RTE_ETH_FILTER_NTUPLE:
2814                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2815                 break;
2816         case RTE_ETH_FILTER_ETHERTYPE:
2817                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2818                 break;
2819         case RTE_ETH_FILTER_GENERIC:
2820                 if (filter_op != RTE_ETH_FILTER_GET)
2821                         return -EINVAL;
2822                 *(const void **)arg = &bnxt_flow_ops;
2823                 break;
2824         default:
2825                 PMD_DRV_LOG(ERR,
2826                         "Filter type (%d) not supported", filter_type);
2827                 ret = -EINVAL;
2828                 break;
2829         }
2830         return ret;
2831 }
2832
2833 static const uint32_t *
2834 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2835 {
2836         static const uint32_t ptypes[] = {
2837                 RTE_PTYPE_L2_ETHER_VLAN,
2838                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2839                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2840                 RTE_PTYPE_L4_ICMP,
2841                 RTE_PTYPE_L4_TCP,
2842                 RTE_PTYPE_L4_UDP,
2843                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2844                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2845                 RTE_PTYPE_INNER_L4_ICMP,
2846                 RTE_PTYPE_INNER_L4_TCP,
2847                 RTE_PTYPE_INNER_L4_UDP,
2848                 RTE_PTYPE_UNKNOWN
2849         };
2850
2851         if (!dev->rx_pkt_burst)
2852                 return NULL;
2853
2854         return ptypes;
2855 }
2856
2857 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2858                          int reg_win)
2859 {
2860         uint32_t reg_base = *reg_arr & 0xfffff000;
2861         uint32_t win_off;
2862         int i;
2863
2864         for (i = 0; i < count; i++) {
2865                 if ((reg_arr[i] & 0xfffff000) != reg_base)
2866                         return -ERANGE;
2867         }
2868         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2869         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
2870         return 0;
2871 }
2872
2873 static int bnxt_map_ptp_regs(struct bnxt *bp)
2874 {
2875         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2876         uint32_t *reg_arr;
2877         int rc, i;
2878
2879         reg_arr = ptp->rx_regs;
2880         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2881         if (rc)
2882                 return rc;
2883
2884         reg_arr = ptp->tx_regs;
2885         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2886         if (rc)
2887                 return rc;
2888
2889         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2890                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2891
2892         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2893                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2894
2895         return 0;
2896 }
2897
2898 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2899 {
2900         rte_write32(0, (uint8_t *)bp->bar0 +
2901                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
2902         rte_write32(0, (uint8_t *)bp->bar0 +
2903                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
2904 }
2905
2906 static uint64_t bnxt_cc_read(struct bnxt *bp)
2907 {
2908         uint64_t ns;
2909
2910         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2911                               BNXT_GRCPF_REG_SYNC_TIME));
2912         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2913                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2914         return ns;
2915 }
2916
2917 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2918 {
2919         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2920         uint32_t fifo;
2921
2922         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2923                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2924         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2925                 return -EAGAIN;
2926
2927         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2928                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2929         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2930                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2931         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2932                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2933
2934         return 0;
2935 }
2936
2937 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2938 {
2939         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2940         struct bnxt_pf_info *pf = &bp->pf;
2941         uint16_t port_id;
2942         uint32_t fifo;
2943
2944         if (!ptp)
2945                 return -ENODEV;
2946
2947         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2948                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2949         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2950                 return -EAGAIN;
2951
2952         port_id = pf->port_id;
2953         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2954                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
2955
2956         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2957                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2958         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2959 /*              bnxt_clr_rx_ts(bp);       TBD  */
2960                 return -EBUSY;
2961         }
2962
2963         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2964                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2965         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2966                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2967
2968         return 0;
2969 }
2970
2971 static int
2972 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2973 {
2974         uint64_t ns;
2975         struct bnxt *bp = dev->data->dev_private;
2976         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2977
2978         if (!ptp)
2979                 return 0;
2980
2981         ns = rte_timespec_to_ns(ts);
2982         /* Set the timecounters to a new value. */
2983         ptp->tc.nsec = ns;
2984
2985         return 0;
2986 }
2987
2988 static int
2989 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2990 {
2991         uint64_t ns, systime_cycles;
2992         struct bnxt *bp = dev->data->dev_private;
2993         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2994
2995         if (!ptp)
2996                 return 0;
2997
2998         systime_cycles = bnxt_cc_read(bp);
2999         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3000         *ts = rte_ns_to_timespec(ns);
3001
3002         return 0;
3003 }
3004 static int
3005 bnxt_timesync_enable(struct rte_eth_dev *dev)
3006 {
3007         struct bnxt *bp = dev->data->dev_private;
3008         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3009         uint32_t shift = 0;
3010
3011         if (!ptp)
3012                 return 0;
3013
3014         ptp->rx_filter = 1;
3015         ptp->tx_tstamp_en = 1;
3016         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3017
3018         if (!bnxt_hwrm_ptp_cfg(bp))
3019                 bnxt_map_ptp_regs(bp);
3020
3021         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3022         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3023         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3024
3025         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3026         ptp->tc.cc_shift = shift;
3027         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3028
3029         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3030         ptp->rx_tstamp_tc.cc_shift = shift;
3031         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3032
3033         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3034         ptp->tx_tstamp_tc.cc_shift = shift;
3035         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3036
3037         return 0;
3038 }
3039
3040 static int
3041 bnxt_timesync_disable(struct rte_eth_dev *dev)
3042 {
3043         struct bnxt *bp = dev->data->dev_private;
3044         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3045
3046         if (!ptp)
3047                 return 0;
3048
3049         ptp->rx_filter = 0;
3050         ptp->tx_tstamp_en = 0;
3051         ptp->rxctl = 0;
3052
3053         bnxt_hwrm_ptp_cfg(bp);
3054
3055         bnxt_unmap_ptp_regs(bp);
3056
3057         return 0;
3058 }
3059
3060 static int
3061 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3062                                  struct timespec *timestamp,
3063                                  uint32_t flags __rte_unused)
3064 {
3065         struct bnxt *bp = dev->data->dev_private;
3066         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3067         uint64_t rx_tstamp_cycles = 0;
3068         uint64_t ns;
3069
3070         if (!ptp)
3071                 return 0;
3072
3073         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3074         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3075         *timestamp = rte_ns_to_timespec(ns);
3076         return  0;
3077 }
3078
3079 static int
3080 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3081                                  struct timespec *timestamp)
3082 {
3083         struct bnxt *bp = dev->data->dev_private;
3084         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3085         uint64_t tx_tstamp_cycles = 0;
3086         uint64_t ns;
3087
3088         if (!ptp)
3089                 return 0;
3090
3091         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3092         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3093         *timestamp = rte_ns_to_timespec(ns);
3094
3095         return 0;
3096 }
3097
3098 static int
3099 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3100 {
3101         struct bnxt *bp = dev->data->dev_private;
3102         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3103
3104         if (!ptp)
3105                 return 0;
3106
3107         ptp->tc.nsec += delta;
3108
3109         return 0;
3110 }
3111
3112 static int
3113 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3114 {
3115         struct bnxt *bp = dev->data->dev_private;
3116         int rc;
3117         uint32_t dir_entries;
3118         uint32_t entry_length;
3119
3120         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3121                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3122                 bp->pdev->addr.devid, bp->pdev->addr.function);
3123
3124         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3125         if (rc != 0)
3126                 return rc;
3127
3128         return dir_entries * entry_length;
3129 }
3130
3131 static int
3132 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3133                 struct rte_dev_eeprom_info *in_eeprom)
3134 {
3135         struct bnxt *bp = dev->data->dev_private;
3136         uint32_t index;
3137         uint32_t offset;
3138
3139         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3140                 "len = %d\n", bp->pdev->addr.domain,
3141                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3142                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3143
3144         if (in_eeprom->offset == 0) /* special offset value to get directory */
3145                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3146                                                 in_eeprom->data);
3147
3148         index = in_eeprom->offset >> 24;
3149         offset = in_eeprom->offset & 0xffffff;
3150
3151         if (index != 0)
3152                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3153                                            in_eeprom->length, in_eeprom->data);
3154
3155         return 0;
3156 }
3157
3158 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3159 {
3160         switch (dir_type) {
3161         case BNX_DIR_TYPE_CHIMP_PATCH:
3162         case BNX_DIR_TYPE_BOOTCODE:
3163         case BNX_DIR_TYPE_BOOTCODE_2:
3164         case BNX_DIR_TYPE_APE_FW:
3165         case BNX_DIR_TYPE_APE_PATCH:
3166         case BNX_DIR_TYPE_KONG_FW:
3167         case BNX_DIR_TYPE_KONG_PATCH:
3168         case BNX_DIR_TYPE_BONO_FW:
3169         case BNX_DIR_TYPE_BONO_PATCH:
3170                 /* FALLTHROUGH */
3171                 return true;
3172         }
3173
3174         return false;
3175 }
3176
3177 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3178 {
3179         switch (dir_type) {
3180         case BNX_DIR_TYPE_AVS:
3181         case BNX_DIR_TYPE_EXP_ROM_MBA:
3182         case BNX_DIR_TYPE_PCIE:
3183         case BNX_DIR_TYPE_TSCF_UCODE:
3184         case BNX_DIR_TYPE_EXT_PHY:
3185         case BNX_DIR_TYPE_CCM:
3186         case BNX_DIR_TYPE_ISCSI_BOOT:
3187         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3188         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3189                 /* FALLTHROUGH */
3190                 return true;
3191         }
3192
3193         return false;
3194 }
3195
3196 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3197 {
3198         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3199                 bnxt_dir_type_is_other_exec_format(dir_type);
3200 }
3201
3202 static int
3203 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3204                 struct rte_dev_eeprom_info *in_eeprom)
3205 {
3206         struct bnxt *bp = dev->data->dev_private;
3207         uint8_t index, dir_op;
3208         uint16_t type, ext, ordinal, attr;
3209
3210         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3211                 "len = %d\n", bp->pdev->addr.domain,
3212                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3213                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3214
3215         if (!BNXT_PF(bp)) {
3216                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3217                 return -EINVAL;
3218         }
3219
3220         type = in_eeprom->magic >> 16;
3221
3222         if (type == 0xffff) { /* special value for directory operations */
3223                 index = in_eeprom->magic & 0xff;
3224                 dir_op = in_eeprom->magic >> 8;
3225                 if (index == 0)
3226                         return -EINVAL;
3227                 switch (dir_op) {
3228                 case 0x0e: /* erase */
3229                         if (in_eeprom->offset != ~in_eeprom->magic)
3230                                 return -EINVAL;
3231                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3232                 default:
3233                         return -EINVAL;
3234                 }
3235         }
3236
3237         /* Create or re-write an NVM item: */
3238         if (bnxt_dir_type_is_executable(type) == true)
3239                 return -EOPNOTSUPP;
3240         ext = in_eeprom->magic & 0xffff;
3241         ordinal = in_eeprom->offset >> 16;
3242         attr = in_eeprom->offset & 0xffff;
3243
3244         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3245                                      in_eeprom->data, in_eeprom->length);
3246 }
3247
3248 /*
3249  * Initialization
3250  */
3251
3252 static const struct eth_dev_ops bnxt_dev_ops = {
3253         .dev_infos_get = bnxt_dev_info_get_op,
3254         .dev_close = bnxt_dev_close_op,
3255         .dev_configure = bnxt_dev_configure_op,
3256         .dev_start = bnxt_dev_start_op,
3257         .dev_stop = bnxt_dev_stop_op,
3258         .dev_set_link_up = bnxt_dev_set_link_up_op,
3259         .dev_set_link_down = bnxt_dev_set_link_down_op,
3260         .stats_get = bnxt_stats_get_op,
3261         .stats_reset = bnxt_stats_reset_op,
3262         .rx_queue_setup = bnxt_rx_queue_setup_op,
3263         .rx_queue_release = bnxt_rx_queue_release_op,
3264         .tx_queue_setup = bnxt_tx_queue_setup_op,
3265         .tx_queue_release = bnxt_tx_queue_release_op,
3266         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3267         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3268         .reta_update = bnxt_reta_update_op,
3269         .reta_query = bnxt_reta_query_op,
3270         .rss_hash_update = bnxt_rss_hash_update_op,
3271         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3272         .link_update = bnxt_link_update_op,
3273         .promiscuous_enable = bnxt_promiscuous_enable_op,
3274         .promiscuous_disable = bnxt_promiscuous_disable_op,
3275         .allmulticast_enable = bnxt_allmulticast_enable_op,
3276         .allmulticast_disable = bnxt_allmulticast_disable_op,
3277         .mac_addr_add = bnxt_mac_addr_add_op,
3278         .mac_addr_remove = bnxt_mac_addr_remove_op,
3279         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3280         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3281         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3282         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3283         .vlan_filter_set = bnxt_vlan_filter_set_op,
3284         .vlan_offload_set = bnxt_vlan_offload_set_op,
3285         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3286         .mtu_set = bnxt_mtu_set_op,
3287         .mac_addr_set = bnxt_set_default_mac_addr_op,
3288         .xstats_get = bnxt_dev_xstats_get_op,
3289         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3290         .xstats_reset = bnxt_dev_xstats_reset_op,
3291         .fw_version_get = bnxt_fw_version_get,
3292         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3293         .rxq_info_get = bnxt_rxq_info_get_op,
3294         .txq_info_get = bnxt_txq_info_get_op,
3295         .dev_led_on = bnxt_dev_led_on_op,
3296         .dev_led_off = bnxt_dev_led_off_op,
3297         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3298         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3299         .rx_queue_count = bnxt_rx_queue_count_op,
3300         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3301         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3302         .rx_queue_start = bnxt_rx_queue_start,
3303         .rx_queue_stop = bnxt_rx_queue_stop,
3304         .tx_queue_start = bnxt_tx_queue_start,
3305         .tx_queue_stop = bnxt_tx_queue_stop,
3306         .filter_ctrl = bnxt_filter_ctrl_op,
3307         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3308         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3309         .get_eeprom           = bnxt_get_eeprom_op,
3310         .set_eeprom           = bnxt_set_eeprom_op,
3311         .timesync_enable      = bnxt_timesync_enable,
3312         .timesync_disable     = bnxt_timesync_disable,
3313         .timesync_read_time   = bnxt_timesync_read_time,
3314         .timesync_write_time   = bnxt_timesync_write_time,
3315         .timesync_adjust_time = bnxt_timesync_adjust_time,
3316         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3317         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3318 };
3319
3320 static bool bnxt_vf_pciid(uint16_t id)
3321 {
3322         if (id == BROADCOM_DEV_ID_57304_VF ||
3323             id == BROADCOM_DEV_ID_57406_VF ||
3324             id == BROADCOM_DEV_ID_5731X_VF ||
3325             id == BROADCOM_DEV_ID_5741X_VF ||
3326             id == BROADCOM_DEV_ID_57414_VF ||
3327             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3328             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3329             id == BROADCOM_DEV_ID_58802_VF ||
3330             id == BROADCOM_DEV_ID_57500_VF1 ||
3331             id == BROADCOM_DEV_ID_57500_VF2)
3332                 return true;
3333         return false;
3334 }
3335
3336 bool bnxt_stratus_device(struct bnxt *bp)
3337 {
3338         uint16_t id = bp->pdev->id.device_id;
3339
3340         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3341             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3342             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3343                 return true;
3344         return false;
3345 }
3346
3347 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3348 {
3349         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3350         struct bnxt *bp = eth_dev->data->dev_private;
3351
3352         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3353         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3354         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3355         if (!bp->bar0 || !bp->doorbell_base) {
3356                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3357                 return -ENODEV;
3358         }
3359
3360         bp->eth_dev = eth_dev;
3361         bp->pdev = pci_dev;
3362
3363         return 0;
3364 }
3365
3366 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3367                                   struct bnxt_ctx_pg_info *ctx_pg,
3368                                   uint32_t mem_size,
3369                                   const char *suffix,
3370                                   uint16_t idx)
3371 {
3372         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3373         const struct rte_memzone *mz = NULL;
3374         char mz_name[RTE_MEMZONE_NAMESIZE];
3375         rte_iova_t mz_phys_addr;
3376         uint64_t valid_bits = 0;
3377         uint32_t sz;
3378         int i;
3379
3380         if (!mem_size)
3381                 return 0;
3382
3383         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3384                          BNXT_PAGE_SIZE;
3385         rmem->page_size = BNXT_PAGE_SIZE;
3386         rmem->pg_arr = ctx_pg->ctx_pg_arr;
3387         rmem->dma_arr = ctx_pg->ctx_dma_arr;
3388         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3389
3390         valid_bits = PTU_PTE_VALID;
3391
3392         if (rmem->nr_pages > 1) {
3393                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_pg_tbl%s_%x",
3394                          suffix, idx);
3395                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3396                 mz = rte_memzone_lookup(mz_name);
3397                 if (!mz) {
3398                         mz = rte_memzone_reserve_aligned(mz_name,
3399                                                 rmem->nr_pages * 8,
3400                                                 SOCKET_ID_ANY,
3401                                                 RTE_MEMZONE_2MB |
3402                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
3403                                                 RTE_MEMZONE_IOVA_CONTIG,
3404                                                 BNXT_PAGE_SIZE);
3405                         if (mz == NULL)
3406                                 return -ENOMEM;
3407                 }
3408
3409                 memset(mz->addr, 0, mz->len);
3410                 mz_phys_addr = mz->iova;
3411                 if ((unsigned long)mz->addr == mz_phys_addr) {
3412                         PMD_DRV_LOG(WARNING,
3413                                 "Memzone physical address same as virtual.\n");
3414                         PMD_DRV_LOG(WARNING,
3415                                     "Using rte_mem_virt2iova()\n");
3416                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3417                         if (mz_phys_addr == RTE_BAD_IOVA) {
3418                                 PMD_DRV_LOG(ERR,
3419                                         "unable to map addr to phys memory\n");
3420                                 return -ENOMEM;
3421                         }
3422                 }
3423                 rte_mem_lock_page(((char *)mz->addr));
3424
3425                 rmem->pg_tbl = mz->addr;
3426                 rmem->pg_tbl_map = mz_phys_addr;
3427                 rmem->pg_tbl_mz = mz;
3428         }
3429
3430         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x", suffix, idx);
3431         mz = rte_memzone_lookup(mz_name);
3432         if (!mz) {
3433                 mz = rte_memzone_reserve_aligned(mz_name,
3434                                                  mem_size,
3435                                                  SOCKET_ID_ANY,
3436                                                  RTE_MEMZONE_1GB |
3437                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
3438                                                  RTE_MEMZONE_IOVA_CONTIG,
3439                                                  BNXT_PAGE_SIZE);
3440                 if (mz == NULL)
3441                         return -ENOMEM;
3442         }
3443
3444         memset(mz->addr, 0, mz->len);
3445         mz_phys_addr = mz->iova;
3446         if ((unsigned long)mz->addr == mz_phys_addr) {
3447                 PMD_DRV_LOG(WARNING,
3448                             "Memzone physical address same as virtual.\n");
3449                 PMD_DRV_LOG(WARNING,
3450                             "Using rte_mem_virt2iova()\n");
3451                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
3452                         rte_mem_lock_page(((char *)mz->addr) + sz);
3453                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3454                 if (mz_phys_addr == RTE_BAD_IOVA) {
3455                         PMD_DRV_LOG(ERR,
3456                                     "unable to map addr to phys memory\n");
3457                         return -ENOMEM;
3458                 }
3459         }
3460
3461         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
3462                 rte_mem_lock_page(((char *)mz->addr) + sz);
3463                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
3464                 rmem->dma_arr[i] = mz_phys_addr + sz;
3465
3466                 if (rmem->nr_pages > 1) {
3467                         if (i == rmem->nr_pages - 2 &&
3468                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3469                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
3470                         else if (i == rmem->nr_pages - 1 &&
3471                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3472                                 valid_bits |= PTU_PTE_LAST;
3473
3474                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
3475                                                            valid_bits);
3476                 }
3477         }
3478
3479         rmem->mz = mz;
3480         if (rmem->vmem_size)
3481                 rmem->vmem = (void **)mz->addr;
3482         rmem->dma_arr[0] = mz_phys_addr;
3483         return 0;
3484 }
3485
3486 static void bnxt_free_ctx_mem(struct bnxt *bp)
3487 {
3488         int i;
3489
3490         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
3491                 return;
3492
3493         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
3494         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
3495         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
3496         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
3497         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
3498         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
3499         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
3500         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
3501         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
3502         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
3503         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
3504
3505         for (i = 0; i < BNXT_MAX_Q; i++) {
3506                 if (bp->ctx->tqm_mem[i])
3507                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
3508         }
3509
3510         rte_free(bp->ctx);
3511         bp->ctx = NULL;
3512 }
3513
3514 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
3515
3516 #define min_t(type, x, y) ({                    \
3517         type __min1 = (x);                      \
3518         type __min2 = (y);                      \
3519         __min1 < __min2 ? __min1 : __min2; })
3520
3521 #define max_t(type, x, y) ({                    \
3522         type __max1 = (x);                      \
3523         type __max2 = (y);                      \
3524         __max1 > __max2 ? __max1 : __max2; })
3525
3526 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
3527
3528 int bnxt_alloc_ctx_mem(struct bnxt *bp)
3529 {
3530         struct bnxt_ctx_pg_info *ctx_pg;
3531         struct bnxt_ctx_mem_info *ctx;
3532         uint32_t mem_size, ena, entries;
3533         int i, rc;
3534
3535         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
3536         if (rc) {
3537                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
3538                 return rc;
3539         }
3540         ctx = bp->ctx;
3541         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
3542                 return 0;
3543
3544         ctx_pg = &ctx->qp_mem;
3545         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
3546         mem_size = ctx->qp_entry_size * ctx_pg->entries;
3547         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
3548         if (rc)
3549                 return rc;
3550
3551         ctx_pg = &ctx->srq_mem;
3552         ctx_pg->entries = ctx->srq_max_l2_entries;
3553         mem_size = ctx->srq_entry_size * ctx_pg->entries;
3554         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
3555         if (rc)
3556                 return rc;
3557
3558         ctx_pg = &ctx->cq_mem;
3559         ctx_pg->entries = ctx->cq_max_l2_entries;
3560         mem_size = ctx->cq_entry_size * ctx_pg->entries;
3561         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
3562         if (rc)
3563                 return rc;
3564
3565         ctx_pg = &ctx->vnic_mem;
3566         ctx_pg->entries = ctx->vnic_max_vnic_entries +
3567                 ctx->vnic_max_ring_table_entries;
3568         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
3569         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
3570         if (rc)
3571                 return rc;
3572
3573         ctx_pg = &ctx->stat_mem;
3574         ctx_pg->entries = ctx->stat_max_entries;
3575         mem_size = ctx->stat_entry_size * ctx_pg->entries;
3576         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
3577         if (rc)
3578                 return rc;
3579
3580         entries = ctx->qp_max_l2_entries;
3581         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
3582         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
3583                           ctx->tqm_max_entries_per_ring);
3584         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
3585                 ctx_pg = ctx->tqm_mem[i];
3586                 /* use min tqm entries for now. */
3587                 ctx_pg->entries = entries;
3588                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
3589                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
3590                 if (rc)
3591                         return rc;
3592                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
3593         }
3594
3595         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
3596         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
3597         if (rc)
3598                 PMD_DRV_LOG(ERR,
3599                             "Failed to configure context mem: rc = %d\n", rc);
3600         else
3601                 ctx->flags |= BNXT_CTX_FLAG_INITED;
3602
3603         return rc;
3604 }
3605
3606 static int bnxt_alloc_stats_mem(struct bnxt *bp)
3607 {
3608         struct rte_pci_device *pci_dev = bp->pdev;
3609         char mz_name[RTE_MEMZONE_NAMESIZE];
3610         const struct rte_memzone *mz = NULL;
3611         uint32_t total_alloc_len;
3612         rte_iova_t mz_phys_addr;
3613
3614         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
3615                 return 0;
3616
3617         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3618                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3619                  pci_dev->addr.bus, pci_dev->addr.devid,
3620                  pci_dev->addr.function, "rx_port_stats");
3621         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3622         mz = rte_memzone_lookup(mz_name);
3623         total_alloc_len =
3624                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
3625                                        sizeof(struct rx_port_stats_ext) + 512);
3626         if (!mz) {
3627                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3628                                          SOCKET_ID_ANY,
3629                                          RTE_MEMZONE_2MB |
3630                                          RTE_MEMZONE_SIZE_HINT_ONLY |
3631                                          RTE_MEMZONE_IOVA_CONTIG);
3632                 if (mz == NULL)
3633                         return -ENOMEM;
3634         }
3635         memset(mz->addr, 0, mz->len);
3636         mz_phys_addr = mz->iova;
3637         if ((unsigned long)mz->addr == mz_phys_addr) {
3638                 PMD_DRV_LOG(WARNING,
3639                             "Memzone physical address same as virtual.\n");
3640                 PMD_DRV_LOG(WARNING,
3641                             "Using rte_mem_virt2iova()\n");
3642                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3643                 if (mz_phys_addr == RTE_BAD_IOVA) {
3644                         PMD_DRV_LOG(ERR,
3645                                     "Can't map address to physical memory\n");
3646                         return -ENOMEM;
3647                 }
3648         }
3649
3650         bp->rx_mem_zone = (const void *)mz;
3651         bp->hw_rx_port_stats = mz->addr;
3652         bp->hw_rx_port_stats_map = mz_phys_addr;
3653
3654         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3655                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3656                  pci_dev->addr.bus, pci_dev->addr.devid,
3657                  pci_dev->addr.function, "tx_port_stats");
3658         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3659         mz = rte_memzone_lookup(mz_name);
3660         total_alloc_len =
3661                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
3662                                        sizeof(struct tx_port_stats_ext) + 512);
3663         if (!mz) {
3664                 mz = rte_memzone_reserve(mz_name,
3665                                          total_alloc_len,
3666                                          SOCKET_ID_ANY,
3667                                          RTE_MEMZONE_2MB |
3668                                          RTE_MEMZONE_SIZE_HINT_ONLY |
3669                                          RTE_MEMZONE_IOVA_CONTIG);
3670                 if (mz == NULL)
3671                         return -ENOMEM;
3672         }
3673         memset(mz->addr, 0, mz->len);
3674         mz_phys_addr = mz->iova;
3675         if ((unsigned long)mz->addr == mz_phys_addr) {
3676                 PMD_DRV_LOG(WARNING,
3677                             "Memzone physical address same as virtual\n");
3678                 PMD_DRV_LOG(WARNING,
3679                             "Using rte_mem_virt2iova()\n");
3680                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3681                 if (mz_phys_addr == RTE_BAD_IOVA) {
3682                         PMD_DRV_LOG(ERR,
3683                                     "Can't map address to physical memory\n");
3684                         return -ENOMEM;
3685                 }
3686         }
3687
3688         bp->tx_mem_zone = (const void *)mz;
3689         bp->hw_tx_port_stats = mz->addr;
3690         bp->hw_tx_port_stats_map = mz_phys_addr;
3691         bp->flags |= BNXT_FLAG_PORT_STATS;
3692
3693         /* Display extended statistics if FW supports it */
3694         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3695             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
3696             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
3697                 return 0;
3698
3699         bp->hw_rx_port_stats_ext = (void *)
3700                 ((uint8_t *)bp->hw_rx_port_stats +
3701                  sizeof(struct rx_port_stats));
3702         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3703                 sizeof(struct rx_port_stats);
3704         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3705
3706         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
3707             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
3708                 bp->hw_tx_port_stats_ext = (void *)
3709                         ((uint8_t *)bp->hw_tx_port_stats +
3710                          sizeof(struct tx_port_stats));
3711                 bp->hw_tx_port_stats_ext_map =
3712                         bp->hw_tx_port_stats_map +
3713                         sizeof(struct tx_port_stats);
3714                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3715         }
3716
3717         return 0;
3718 }
3719
3720 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
3721 {
3722         struct bnxt *bp = eth_dev->data->dev_private;
3723         int rc = 0;
3724
3725         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3726                                                RTE_ETHER_ADDR_LEN *
3727                                                bp->max_l2_ctx,
3728                                                0);
3729         if (eth_dev->data->mac_addrs == NULL) {
3730                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
3731                 return -ENOMEM;
3732         }
3733
3734         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
3735                 if (BNXT_PF(bp))
3736                         return -EINVAL;
3737
3738                 /* Generate a random MAC address, if none was assigned by PF */
3739                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
3740                 bnxt_eth_hw_addr_random(bp->mac_addr);
3741                 PMD_DRV_LOG(INFO,
3742                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
3743                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
3744                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
3745
3746                 rc = bnxt_hwrm_set_mac(bp);
3747                 if (!rc)
3748                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
3749                                RTE_ETHER_ADDR_LEN);
3750                 return rc;
3751         }
3752
3753         /* Copy the permanent MAC from the FUNC_QCAPS response */
3754         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
3755         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
3756
3757         return rc;
3758 }
3759
3760 #define ALLOW_FUNC(x)   \
3761         { \
3762                 uint32_t arg = (x); \
3763                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3764                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3765         }
3766 static int
3767 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3768 {
3769         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3770         static int version_printed;
3771         struct bnxt *bp;
3772         uint16_t mtu;
3773         int rc;
3774
3775         if (version_printed++ == 0)
3776                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3777
3778         rte_eth_copy_pci_info(eth_dev, pci_dev);
3779
3780         bp = eth_dev->data->dev_private;
3781
3782         bp->dev_stopped = 1;
3783
3784         eth_dev->dev_ops = &bnxt_dev_ops;
3785         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3786         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3787
3788         /*
3789          * For secondary processes, we don't initialise any further
3790          * as primary has already done this work.
3791          */
3792         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3793                 return 0;
3794
3795         if (bnxt_vf_pciid(pci_dev->id.device_id))
3796                 bp->flags |= BNXT_FLAG_VF;
3797
3798         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
3799             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
3800             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
3801             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
3802             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
3803                 bp->flags |= BNXT_FLAG_THOR_CHIP;
3804
3805         rc = bnxt_init_board(eth_dev);
3806         if (rc) {
3807                 PMD_DRV_LOG(ERR,
3808                         "Board initialization failed rc: %x\n", rc);
3809                 goto error;
3810         }
3811
3812         rc = bnxt_alloc_hwrm_resources(bp);
3813         if (rc) {
3814                 PMD_DRV_LOG(ERR,
3815                         "hwrm resource allocation failure rc: %x\n", rc);
3816                 goto error_free;
3817         }
3818         rc = bnxt_hwrm_ver_get(bp);
3819         if (rc)
3820                 goto error_free;
3821
3822         rc = bnxt_hwrm_func_reset(bp);
3823         if (rc) {
3824                 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3825                 rc = -EIO;
3826                 goto error_free;
3827         }
3828
3829         rc = bnxt_hwrm_queue_qportcfg(bp);
3830         if (rc) {
3831                 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3832                 goto error_free;
3833         }
3834         /* Get the MAX capabilities for this function */
3835         rc = bnxt_hwrm_func_qcaps(bp);
3836         if (rc) {
3837                 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3838                 goto error_free;
3839         }
3840
3841         rc = bnxt_alloc_stats_mem(bp);
3842         if (rc)
3843                 goto error_free;
3844
3845         if (bp->max_tx_rings == 0) {
3846                 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3847                 rc = -EBUSY;
3848                 goto error_free;
3849         }
3850
3851         rc = bnxt_setup_mac_addr(eth_dev);
3852         if (rc)
3853                 goto error_free;
3854
3855         /* THOR does not support ring groups.
3856          * But we will use the array to save RSS context IDs.
3857          */
3858         if (BNXT_CHIP_THOR(bp)) {
3859                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
3860         } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3861                 /* 1 ring is for default completion ring */
3862                 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3863                 rc = -ENOSPC;
3864                 goto error_free;
3865         }
3866
3867         if (BNXT_HAS_RING_GRPS(bp)) {
3868                 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3869                                         sizeof(*bp->grp_info) *
3870                                                 bp->max_ring_grps, 0);
3871                 if (!bp->grp_info) {
3872                         PMD_DRV_LOG(ERR,
3873                                 "Failed to alloc %zu bytes for grp info tbl.\n",
3874                                 sizeof(*bp->grp_info) * bp->max_ring_grps);
3875                         rc = -ENOMEM;
3876                         goto error_free;
3877                 }
3878         }
3879
3880         /* Forward all requests if firmware is new enough */
3881         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3882             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3883             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3884                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3885         } else {
3886                 PMD_DRV_LOG(WARNING,
3887                         "Firmware too old for VF mailbox functionality\n");
3888                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3889         }
3890
3891         /*
3892          * The following are used for driver cleanup.  If we disallow these,
3893          * VF drivers can't clean up cleanly.
3894          */
3895         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3896         ALLOW_FUNC(HWRM_VNIC_FREE);
3897         ALLOW_FUNC(HWRM_RING_FREE);
3898         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3899         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3900         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3901         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3902         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3903         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3904         rc = bnxt_hwrm_func_driver_register(bp);
3905         if (rc) {
3906                 PMD_DRV_LOG(ERR,
3907                         "Failed to register driver");
3908                 rc = -EBUSY;
3909                 goto error_free;
3910         }
3911
3912         PMD_DRV_LOG(INFO,
3913                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3914                 pci_dev->mem_resource[0].phys_addr,
3915                 pci_dev->mem_resource[0].addr);
3916
3917         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
3918         if (rc) {
3919                 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3920                 goto error_free;
3921         }
3922
3923         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
3924             mtu != eth_dev->data->mtu)
3925                 eth_dev->data->mtu = mtu;
3926
3927         if (BNXT_PF(bp)) {
3928                 //if (bp->pf.active_vfs) {
3929                         // TODO: Deallocate VF resources?
3930                 //}
3931                 if (bp->pdev->max_vfs) {
3932                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3933                         if (rc) {
3934                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3935                                 goto error_free;
3936                         }
3937                 } else {
3938                         rc = bnxt_hwrm_allocate_pf_only(bp);
3939                         if (rc) {
3940                                 PMD_DRV_LOG(ERR,
3941                                         "Failed to allocate PF resources\n");
3942                                 goto error_free;
3943                         }
3944                 }
3945         }
3946
3947         bnxt_hwrm_port_led_qcaps(bp);
3948
3949         rc = bnxt_setup_int(bp);
3950         if (rc)
3951                 goto error_free;
3952
3953         rc = bnxt_alloc_mem(bp);
3954         if (rc)
3955                 goto error_free;
3956
3957         bnxt_init_nic(bp);
3958
3959         rc = bnxt_request_int(bp);
3960         if (rc)
3961                 goto error_free;
3962
3963         return 0;
3964
3965 error_free:
3966         bnxt_dev_uninit(eth_dev);
3967 error:
3968         return rc;
3969 }
3970
3971 static int
3972 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3973 {
3974         struct bnxt *bp = eth_dev->data->dev_private;
3975         int rc;
3976
3977         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3978                 return -EPERM;
3979
3980         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
3981         bnxt_disable_int(bp);
3982         bnxt_free_int(bp);
3983         bnxt_free_mem(bp);
3984
3985         bnxt_hwrm_func_buf_unrgtr(bp);
3986
3987         if (bp->grp_info != NULL) {
3988                 rte_free(bp->grp_info);
3989                 bp->grp_info = NULL;
3990         }
3991         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3992         bnxt_free_hwrm_resources(bp);
3993
3994         if (bp->tx_mem_zone) {
3995                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3996                 bp->tx_mem_zone = NULL;
3997         }
3998
3999         if (bp->rx_mem_zone) {
4000                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4001                 bp->rx_mem_zone = NULL;
4002         }
4003
4004         if (bp->dev_stopped == 0)
4005                 bnxt_dev_close_op(eth_dev);
4006         if (bp->pf.vf_info)
4007                 rte_free(bp->pf.vf_info);
4008         bnxt_free_ctx_mem(bp);
4009         eth_dev->dev_ops = NULL;
4010         eth_dev->rx_pkt_burst = NULL;
4011         eth_dev->tx_pkt_burst = NULL;
4012
4013         return rc;
4014 }
4015
4016 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4017         struct rte_pci_device *pci_dev)
4018 {
4019         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4020                 bnxt_dev_init);
4021 }
4022
4023 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4024 {
4025         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4026                 return rte_eth_dev_pci_generic_remove(pci_dev,
4027                                 bnxt_dev_uninit);
4028         else
4029                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4030 }
4031
4032 static struct rte_pci_driver bnxt_rte_pmd = {
4033         .id_table = bnxt_pci_id_map,
4034         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4035         .probe = bnxt_pci_probe,
4036         .remove = bnxt_pci_remove,
4037 };
4038
4039 static bool
4040 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4041 {
4042         if (strcmp(dev->device->driver->name, drv->driver.name))
4043                 return false;
4044
4045         return true;
4046 }
4047
4048 bool is_bnxt_supported(struct rte_eth_dev *dev)
4049 {
4050         return is_device_supported(dev, &bnxt_rte_pmd);
4051 }
4052
4053 RTE_INIT(bnxt_init_log)
4054 {
4055         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4056         if (bnxt_logtype_driver >= 0)
4057                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4058 }
4059
4060 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4061 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4062 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");