drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29 #include "bnxt_util.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  37
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  42 #define BROADCOM_DEV_ID_57301 0x16c8
  43 #define BROADCOM_DEV_ID_57302 0x16c9
  44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  47 #define BROADCOM_DEV_ID_NS2 0x16cd
  48 #define BROADCOM_DEV_ID_57311 0x16ce
  49 #define BROADCOM_DEV_ID_57312 0x16cf
  50 #define BROADCOM_DEV_ID_57402 0x16d0
  51 #define BROADCOM_DEV_ID_57404 0x16d1
  52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  56 #define BROADCOM_DEV_ID_57412 0x16d6
  57 #define BROADCOM_DEV_ID_57414 0x16d7
  58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  61 #define BROADCOM_DEV_ID_57412_MF 0x16de
  62 #define BROADCOM_DEV_ID_57314 0x16df
  63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  74 #define BROADCOM_DEV_ID_57508 0x1750
  75 #define BROADCOM_DEV_ID_57504 0x1751
  76 #define BROADCOM_DEV_ID_57502 0x1752
  77 #define BROADCOM_DEV_ID_57500_VF 0x1807
  78 #define BROADCOM_DEV_ID_58802 0xd802
  79 #define BROADCOM_DEV_ID_58804 0xd804
  80 #define BROADCOM_DEV_ID_58808 0x16f0
  81 #define BROADCOM_DEV_ID_58802_VF 0xd800
  82
  83 static const struct rte_pci_id bnxt_pci_id_map[] = {
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  85                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  87                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF) },
 130         { .vendor_id = 0, /* sentinel */ },
 131 };
 132
 133 #define BNXT_ETH_RSS_SUPPORT (  \
 134         ETH_RSS_IPV4 |          \
 135         ETH_RSS_NONFRAG_IPV4_TCP |      \
 136         ETH_RSS_NONFRAG_IPV4_UDP |      \
 137         ETH_RSS_IPV6 |          \
 138         ETH_RSS_NONFRAG_IPV6_TCP |      \
 139         ETH_RSS_NONFRAG_IPV6_UDP)
 140
 141 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 142                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 143                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 144                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 145                                      DEV_TX_OFFLOAD_TCP_TSO | \
 146                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 147                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 148                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 149                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 150                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 152
 153 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 154                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 155                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 156                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 157                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 158                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 159                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 160                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 161                                      DEV_RX_OFFLOAD_TCP_LRO)
 162
 163 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 164 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 165 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 166 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 167
 168 /***********************/
 169
 170 /*
 171  * High level utility functions
 172  */
 173
 174 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 175 {
 176         if (!BNXT_CHIP_THOR(bp))
 177                 return 1;
 178
 179         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 180                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 181                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 182 }
 183
 184 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 185 {
 186         if (!BNXT_CHIP_THOR(bp))
 187                 return HW_HASH_INDEX_SIZE;
 188
 189         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 190 }
 191
 192 static void bnxt_free_mem(struct bnxt *bp)
 193 {
 194         bnxt_free_filter_mem(bp);
 195         bnxt_free_vnic_attributes(bp);
 196         bnxt_free_vnic_mem(bp);
 197
 198         bnxt_free_stats(bp);
 199         bnxt_free_tx_rings(bp);
 200         bnxt_free_rx_rings(bp);
 201 }
 202
 203 static int bnxt_alloc_mem(struct bnxt *bp)
 204 {
 205         int rc;
 206
 207         rc = bnxt_alloc_vnic_mem(bp);
 208         if (rc)
 209                 goto alloc_mem_err;
 210
 211         rc = bnxt_alloc_vnic_attributes(bp);
 212         if (rc)
 213                 goto alloc_mem_err;
 214
 215         rc = bnxt_alloc_filter_mem(bp);
 216         if (rc)
 217                 goto alloc_mem_err;
 218
 219         return 0;
 220
 221 alloc_mem_err:
 222         bnxt_free_mem(bp);
 223         return rc;
 224 }
 225
 226 static int bnxt_init_chip(struct bnxt *bp)
 227 {
 228         struct bnxt_rx_queue *rxq;
 229         struct rte_eth_link new;
 230         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 231         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 232         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 233         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 234         uint32_t intr_vector = 0;
 235         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 236         uint32_t vec = BNXT_MISC_VEC_ID;
 237         unsigned int i, j;
 238         int rc;
 239
 240         /* disable uio/vfio intr/eventfd mapping */
 241         rte_intr_disable(intr_handle);
 242
 243         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 244                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 245                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 246                 bp->flags |= BNXT_FLAG_JUMBO;
 247         } else {
 248                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 249                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 250                 bp->flags &= ~BNXT_FLAG_JUMBO;
 251         }
 252
 253         /* THOR does not support ring groups.
 254          * But we will use the array to save RSS context IDs.
 255          */
 256         if (BNXT_CHIP_THOR(bp))
 257                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 258
 259         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 260         if (rc) {
 261                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 262                 goto err_out;
 263         }
 264
 265         rc = bnxt_alloc_hwrm_rings(bp);
 266         if (rc) {
 267                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 268                 goto err_out;
 269         }
 270
 271         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 272         if (rc) {
 273                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 274                 goto err_out;
 275         }
 276
 277         rc = bnxt_mq_rx_configure(bp);
 278         if (rc) {
 279                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 280                 goto err_out;
 281         }
 282
 283         /* VNIC configuration */
 284         for (i = 0; i < bp->nr_vnics; i++) {
 285                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 286                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 287                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 288
 289                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 290                 if (!vnic->fw_grp_ids) {
 291                         PMD_DRV_LOG(ERR,
 292                                     "Failed to alloc %d bytes for group ids\n",
 293                                     size);
 294                         rc = -ENOMEM;
 295                         goto err_out;
 296                 }
 297                 memset(vnic->fw_grp_ids, -1, size);
 298
 299                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 300                             i, vnic, vnic->fw_grp_ids);
 301
 302                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 303                 if (rc) {
 304                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 305                                 i, rc);
 306                         goto err_out;
 307                 }
 308
 309                 /* Alloc RSS context only if RSS mode is enabled */
 310                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 311                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 312
 313                         rc = 0;
 314                         for (j = 0; j < nr_ctxs; j++) {
 315                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 316                                 if (rc)
 317                                         break;
 318                         }
 319                         if (rc) {
 320                                 PMD_DRV_LOG(ERR,
 321                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 322                                   i, j, rc);
 323                                 goto err_out;
 324                         }
 325                         vnic->num_lb_ctxts = nr_ctxs;
 326                 }
 327
 328                 /*
 329                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 330                  * setting is not available at this time, it will not be
 331                  * configured correctly in the CFA.
 332                  */
 333                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 334                         vnic->vlan_strip = true;
 335                 else
 336                         vnic->vlan_strip = false;
 337
 338                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 339                 if (rc) {
 340                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 341                                 i, rc);
 342                         goto err_out;
 343                 }
 344
 345                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 346                 if (rc) {
 347                         PMD_DRV_LOG(ERR,
 348                                 "HWRM vnic %d filter failure rc: %x\n",
 349                                 i, rc);
 350                         goto err_out;
 351                 }
 352
 353                 for (j = 0; j < bp->rx_nr_rings; j++) {
 354                         rxq = bp->eth_dev->data->rx_queues[j];
 355
 356                         PMD_DRV_LOG(DEBUG,
 357                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 358                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 359
 360                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 361                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 362                 }
 363
 364                 rc = bnxt_vnic_rss_configure(bp, vnic);
 365                 if (rc) {
 366                         PMD_DRV_LOG(ERR,
 367                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 368                         goto err_out;
 369                 }
 370
 371                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 372
 373                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 374                     DEV_RX_OFFLOAD_TCP_LRO)
 375                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 376                 else
 377                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 378         }
 379         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 380         if (rc) {
 381                 PMD_DRV_LOG(ERR,
 382                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 383                 goto err_out;
 384         }
 385
 386         /* check and configure queue intr-vector mapping */
 387         if ((rte_intr_cap_multiple(intr_handle) ||
 388              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 389             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 390                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 391                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 392                 if (intr_vector > bp->rx_cp_nr_rings) {
 393                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 394                                         bp->rx_cp_nr_rings);
 395                         return -ENOTSUP;
 396                 }
 397                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 398                         return -1;
 399         }
 400
 401         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 402                 intr_handle->intr_vec =
 403                         rte_zmalloc("intr_vec",
 404                                     bp->eth_dev->data->nb_rx_queues *
 405                                     sizeof(int), 0);
 406                 if (intr_handle->intr_vec == NULL) {
 407                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 408                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 409                         return -ENOMEM;
 410                 }
 411                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 412                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 413                          intr_handle->intr_vec, intr_handle->nb_efd,
 414                         intr_handle->max_intr);
 415         }
 416
 417         for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 418              queue_id++) {
 419                 intr_handle->intr_vec[queue_id] = vec;
 420                 if (vec < base + intr_handle->nb_efd - 1)
 421                         vec++;
 422         }
 423
 424         /* enable uio/vfio intr/eventfd mapping */
 425         rte_intr_enable(intr_handle);
 426
 427         rc = bnxt_get_hwrm_link_config(bp, &new);
 428         if (rc) {
 429                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 430                 goto err_out;
 431         }
 432
 433         if (!bp->link_info.link_up) {
 434                 rc = bnxt_set_hwrm_link_config(bp, true);
 435                 if (rc) {
 436                         PMD_DRV_LOG(ERR,
 437                                 "HWRM link config failure rc: %x\n", rc);
 438                         goto err_out;
 439                 }
 440         }
 441         bnxt_print_link_info(bp->eth_dev);
 442
 443         return 0;
 444
 445 err_out:
 446         bnxt_free_all_hwrm_resources(bp);
 447
 448         /* Some of the error status returned by FW may not be from errno.h */
 449         if (rc > 0)
 450                 rc = -EIO;
 451
 452         return rc;
 453 }
 454
 455 static int bnxt_shutdown_nic(struct bnxt *bp)
 456 {
 457         bnxt_free_all_hwrm_resources(bp);
 458         bnxt_free_all_filters(bp);
 459         bnxt_free_all_vnics(bp);
 460         return 0;
 461 }
 462
 463 static int bnxt_init_nic(struct bnxt *bp)
 464 {
 465         int rc;
 466
 467         rc = bnxt_init_ring_grps(bp);
 468         if (rc)
 469                 return rc;
 470
 471         bnxt_init_vnics(bp);
 472         bnxt_init_filters(bp);
 473
 474         return 0;
 475 }
 476
 477 /*
 478  * Device configuration and status function
 479  */
 480
 481 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 482                                   struct rte_eth_dev_info *dev_info)
 483 {
 484         struct bnxt *bp = eth_dev->data->dev_private;
 485         uint16_t max_vnics, i, j, vpool, vrxq;
 486         unsigned int max_rx_rings;
 487
 488         /* MAC Specifics */
 489         dev_info->max_mac_addrs = bp->max_l2_ctx;
 490         dev_info->max_hash_mac_addrs = 0;
 491
 492         /* PF/VF specifics */
 493         if (BNXT_PF(bp))
 494                 dev_info->max_vfs = bp->pdev->max_vfs;
 495         max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx);
 496         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 497         dev_info->max_rx_queues = max_rx_rings;
 498         dev_info->max_tx_queues = max_rx_rings;
 499         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 500         dev_info->hash_key_size = 40;
 501         max_vnics = bp->max_vnics;
 502
 503         /* Fast path specifics */
 504         dev_info->min_rx_bufsize = 1;
 505         dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
 506                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
 507
 508         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 509         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 510                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 511         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 512         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 513
 514         /* *INDENT-OFF* */
 515         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 516                 .rx_thresh = {
 517                         .pthresh = 8,
 518                         .hthresh = 8,
 519                         .wthresh = 0,
 520                 },
 521                 .rx_free_thresh = 32,
 522                 /* If no descriptors available, pkts are dropped by default */
 523                 .rx_drop_en = 1,
 524         };
 525
 526         dev_info->default_txconf = (struct rte_eth_txconf) {
 527                 .tx_thresh = {
 528                         .pthresh = 32,
 529                         .hthresh = 0,
 530                         .wthresh = 0,
 531                 },
 532                 .tx_free_thresh = 32,
 533                 .tx_rs_thresh = 32,
 534         };
 535         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 536
 537         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 538         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 539         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 540         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 541         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 542
 543         /* *INDENT-ON* */
 544
 545         /*
 546          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 547          *       need further investigation.
 548          */
 549
 550         /* VMDq resources */
 551         vpool = 64; /* ETH_64_POOLS */
 552         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 553         for (i = 0; i < 4; vpool >>= 1, i++) {
 554                 if (max_vnics > vpool) {
 555                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 556                                 if (dev_info->max_rx_queues > vrxq) {
 557                                         if (vpool > vrxq)
 558                                                 vpool = vrxq;
 559                                         goto found;
 560                                 }
 561                         }
 562                         /* Not enough resources to support VMDq */
 563                         break;
 564                 }
 565         }
 566         /* Not enough resources to support VMDq */
 567         vpool = 0;
 568         vrxq = 0;
 569 found:
 570         dev_info->max_vmdq_pools = vpool;
 571         dev_info->vmdq_queue_num = vrxq;
 572
 573         dev_info->vmdq_pool_base = 0;
 574         dev_info->vmdq_queue_base = 0;
 575 }
 576
 577 /* Configure the device based on the configuration provided */
 578 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 579 {
 580         struct bnxt *bp = eth_dev->data->dev_private;
 581         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 582         int rc;
 583
 584         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 585         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 586         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 587         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 588
 589         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 590                 rc = bnxt_hwrm_check_vf_rings(bp);
 591                 if (rc) {
 592                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 593                         return -ENOSPC;
 594                 }
 595
 596                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 597                 if (rc) {
 598                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 599                         return -ENOSPC;
 600                 }
 601         } else {
 602                 /* legacy driver needs to get updated values */
 603                 rc = bnxt_hwrm_func_qcaps(bp);
 604                 if (rc) {
 605                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 606                         return rc;
 607                 }
 608         }
 609
 610         /* Inherit new configurations */
 611         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 612             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 613             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 614             bp->max_cp_rings ||
 615             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 616             bp->max_stat_ctx)
 617                 goto resource_error;
 618
 619         if (BNXT_HAS_RING_GRPS(bp) &&
 620             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 621                 goto resource_error;
 622
 623         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 624             bp->max_vnics < eth_dev->data->nb_rx_queues)
 625                 goto resource_error;
 626
 627         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 628         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 629
 630         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 631                 eth_dev->data->mtu =
 632                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 633                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 634                         BNXT_NUM_VLANS;
 635                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 636         }
 637         return 0;
 638
 639 resource_error:
 640         PMD_DRV_LOG(ERR,
 641                     "Insufficient resources to support requested config\n");
 642         PMD_DRV_LOG(ERR,
 643                     "Num Queues Requested: Tx %d, Rx %d\n",
 644                     eth_dev->data->nb_tx_queues,
 645                     eth_dev->data->nb_rx_queues);
 646         PMD_DRV_LOG(ERR,
 647                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 648                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 649                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 650         return -ENOSPC;
 651 }
 652
 653 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 654 {
 655         struct rte_eth_link *link = &eth_dev->data->dev_link;
 656
 657         if (link->link_status)
 658                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 659                         eth_dev->data->port_id,
 660                         (uint32_t)link->link_speed,
 661                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 662                         ("full-duplex") : ("half-duplex\n"));
 663         else
 664                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 665                         eth_dev->data->port_id);
 666 }
 667
 668 /*
 669  * Determine whether the current configuration requires support for scattered
 670  * receive; return 1 if scattered receive is required and 0 if not.
 671  */
 672 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 673 {
 674         uint16_t buf_size;
 675         int i;
 676
 677         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 678                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 679
 680                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 681                                       RTE_PKTMBUF_HEADROOM);
 682                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 683                         return 1;
 684         }
 685         return 0;
 686 }
 687
 688 static eth_rx_burst_t
 689 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 690 {
 691 #ifdef RTE_ARCH_X86
 692         /*
 693          * Vector mode receive can be enabled only if scatter rx is not
 694          * in use and rx offloads are limited to VLAN stripping and
 695          * CRC stripping.
 696          */
 697         if (!eth_dev->data->scattered_rx &&
 698             !(eth_dev->data->dev_conf.rxmode.offloads &
 699               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 700                 DEV_RX_OFFLOAD_KEEP_CRC |
 701                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 702                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 703                 DEV_RX_OFFLOAD_UDP_CKSUM |
 704                 DEV_RX_OFFLOAD_TCP_CKSUM |
 705                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 706                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 707                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 708                             eth_dev->data->port_id);
 709                 return bnxt_recv_pkts_vec;
 710         }
 711         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 712                     eth_dev->data->port_id);
 713         PMD_DRV_LOG(INFO,
 714                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 715                     eth_dev->data->port_id,
 716                     eth_dev->data->scattered_rx,
 717                     eth_dev->data->dev_conf.rxmode.offloads);
 718 #endif
 719         return bnxt_recv_pkts;
 720 }
 721
 722 static eth_tx_burst_t
 723 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 724 {
 725 #ifdef RTE_ARCH_X86
 726         /*
 727          * Vector mode receive can be enabled only if scatter tx is not
 728          * in use and tx offloads other than VLAN insertion are not
 729          * in use.
 730          */
 731         if (!eth_dev->data->scattered_rx &&
 732             !(eth_dev->data->dev_conf.txmode.offloads &
 733               ~DEV_TX_OFFLOAD_VLAN_INSERT)) {
 734                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 735                             eth_dev->data->port_id);
 736                 return bnxt_xmit_pkts_vec;
 737         }
 738         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 739                     eth_dev->data->port_id);
 740         PMD_DRV_LOG(INFO,
 741                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 742                     eth_dev->data->port_id,
 743                     eth_dev->data->scattered_rx,
 744                     eth_dev->data->dev_conf.txmode.offloads);
 745 #endif
 746         return bnxt_xmit_pkts;
 747 }
 748
 749 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 750 {
 751         struct bnxt *bp = eth_dev->data->dev_private;
 752         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 753         int vlan_mask = 0;
 754         int rc;
 755
 756         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 757                 PMD_DRV_LOG(ERR,
 758                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 759                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 760         }
 761         bp->dev_stopped = 0;
 762
 763         rc = bnxt_init_chip(bp);
 764         if (rc)
 765                 goto error;
 766
 767         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 768
 769         bnxt_link_update_op(eth_dev, 1);
 770
 771         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 772                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 773         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 774                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 775         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 776         if (rc)
 777                 goto error;
 778
 779         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 780         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 781         bp->flags |= BNXT_FLAG_INIT_DONE;
 782         return 0;
 783
 784 error:
 785         bnxt_shutdown_nic(bp);
 786         bnxt_free_tx_mbufs(bp);
 787         bnxt_free_rx_mbufs(bp);
 788         return rc;
 789 }
 790
 791 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 792 {
 793         struct bnxt *bp = eth_dev->data->dev_private;
 794         int rc = 0;
 795
 796         if (!bp->link_info.link_up)
 797                 rc = bnxt_set_hwrm_link_config(bp, true);
 798         if (!rc)
 799                 eth_dev->data->dev_link.link_status = 1;
 800
 801         bnxt_print_link_info(eth_dev);
 802         return 0;
 803 }
 804
 805 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 806 {
 807         struct bnxt *bp = eth_dev->data->dev_private;
 808
 809         eth_dev->data->dev_link.link_status = 0;
 810         bnxt_set_hwrm_link_config(bp, false);
 811         bp->link_info.link_up = 0;
 812
 813         return 0;
 814 }
 815
 816 /* Unload the driver, release resources */
 817 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 818 {
 819         struct bnxt *bp = eth_dev->data->dev_private;
 820
 821         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 822         if (bp->eth_dev->data->dev_started) {
 823                 /* TBD: STOP HW queues DMA */
 824                 eth_dev->data->dev_link.link_status = 0;
 825         }
 826         bnxt_set_hwrm_link_config(bp, false);
 827         bnxt_hwrm_port_clr_stats(bp);
 828         bnxt_free_tx_mbufs(bp);
 829         bnxt_free_rx_mbufs(bp);
 830         bnxt_shutdown_nic(bp);
 831         bp->dev_stopped = 1;
 832 }
 833
 834 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 835 {
 836         struct bnxt *bp = eth_dev->data->dev_private;
 837
 838         if (bp->dev_stopped == 0)
 839                 bnxt_dev_stop_op(eth_dev);
 840
 841         if (eth_dev->data->mac_addrs != NULL) {
 842                 rte_free(eth_dev->data->mac_addrs);
 843                 eth_dev->data->mac_addrs = NULL;
 844         }
 845         if (bp->grp_info != NULL) {
 846                 rte_free(bp->grp_info);
 847                 bp->grp_info = NULL;
 848         }
 849
 850         bnxt_dev_uninit(eth_dev);
 851 }
 852
 853 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 854                                     uint32_t index)
 855 {
 856         struct bnxt *bp = eth_dev->data->dev_private;
 857         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 858         struct bnxt_vnic_info *vnic;
 859         struct bnxt_filter_info *filter, *temp_filter;
 860         uint32_t i;
 861
 862         /*
 863          * Loop through all VNICs from the specified filter flow pools to
 864          * remove the corresponding MAC addr filter
 865          */
 866         for (i = 0; i < bp->nr_vnics; i++) {
 867                 if (!(pool_mask & (1ULL << i)))
 868                         continue;
 869
 870                 vnic = &bp->vnic_info[i];
 871                 filter = STAILQ_FIRST(&vnic->filter);
 872                 while (filter) {
 873                         temp_filter = STAILQ_NEXT(filter, next);
 874                         if (filter->mac_index == index) {
 875                                 STAILQ_REMOVE(&vnic->filter, filter,
 876                                                 bnxt_filter_info, next);
 877                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 878                                 filter->mac_index = INVALID_MAC_INDEX;
 879                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 880                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 881                                                    filter, next);
 882                         }
 883                         filter = temp_filter;
 884                 }
 885         }
 886 }
 887
 888 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 889                                 struct rte_ether_addr *mac_addr,
 890                                 uint32_t index, uint32_t pool)
 891 {
 892         struct bnxt *bp = eth_dev->data->dev_private;
 893         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
 894         struct bnxt_filter_info *filter;
 895
 896         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
 897                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
 898                 return -ENOTSUP;
 899         }
 900
 901         if (!vnic) {
 902                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
 903                 return -EINVAL;
 904         }
 905         /* Attach requested MAC address to the new l2_filter */
 906         STAILQ_FOREACH(filter, &vnic->filter, next) {
 907                 if (filter->mac_index == index) {
 908                         PMD_DRV_LOG(ERR,
 909                                 "MAC addr already existed for pool %d\n", pool);
 910                         return 0;
 911                 }
 912         }
 913         filter = bnxt_alloc_filter(bp);
 914         if (!filter) {
 915                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
 916                 return -ENODEV;
 917         }
 918         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 919         filter->mac_index = index;
 920         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
 921         return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 922 }
 923
 924 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 925 {
 926         int rc = 0;
 927         struct bnxt *bp = eth_dev->data->dev_private;
 928         struct rte_eth_link new;
 929         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 930
 931         memset(&new, 0, sizeof(new));
 932         do {
 933                 /* Retrieve link info from hardware */
 934                 rc = bnxt_get_hwrm_link_config(bp, &new);
 935                 if (rc) {
 936                         new.link_speed = ETH_LINK_SPEED_100M;
 937                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 938                         PMD_DRV_LOG(ERR,
 939                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 940                         goto out;
 941                 }
 942                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 943
 944                 if (!wait_to_complete)
 945                         break;
 946         } while (!new.link_status && cnt--);
 947
 948 out:
 949         /* Timed out or success */
 950         if (new.link_status != eth_dev->data->dev_link.link_status ||
 951         new.link_speed != eth_dev->data->dev_link.link_speed) {
 952                 memcpy(&eth_dev->data->dev_link, &new,
 953                         sizeof(struct rte_eth_link));
 954
 955                 _rte_eth_dev_callback_process(eth_dev,
 956                                               RTE_ETH_EVENT_INTR_LSC,
 957                                               NULL);
 958
 959                 bnxt_print_link_info(eth_dev);
 960         }
 961
 962         return rc;
 963 }
 964
 965 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
 966 {
 967         struct bnxt *bp = eth_dev->data->dev_private;
 968         struct bnxt_vnic_info *vnic;
 969
 970         if (bp->vnic_info == NULL)
 971                 return;
 972
 973         vnic = &bp->vnic_info[0];
 974
 975         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
 976         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 977 }
 978
 979 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
 980 {
 981         struct bnxt *bp = eth_dev->data->dev_private;
 982         struct bnxt_vnic_info *vnic;
 983
 984         if (bp->vnic_info == NULL)
 985                 return;
 986
 987         vnic = &bp->vnic_info[0];
 988
 989         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
 990         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 991 }
 992
 993 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
 994 {
 995         struct bnxt *bp = eth_dev->data->dev_private;
 996         struct bnxt_vnic_info *vnic;
 997
 998         if (bp->vnic_info == NULL)
 999                 return;
1000
1001         vnic = &bp->vnic_info[0];
1002
1003         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1004         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1005 }
1006
1007 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1008 {
1009         struct bnxt *bp = eth_dev->data->dev_private;
1010         struct bnxt_vnic_info *vnic;
1011
1012         if (bp->vnic_info == NULL)
1013                 return;
1014
1015         vnic = &bp->vnic_info[0];
1016
1017         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1018         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1019 }
1020
1021 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1022 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1023 {
1024         if (qid >= bp->rx_nr_rings)
1025                 return NULL;
1026
1027         return bp->eth_dev->data->rx_queues[qid];
1028 }
1029
1030 /* Return rxq corresponding to a given rss table ring/group ID. */
1031 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1032 {
1033         struct bnxt_rx_queue *rxq;
1034         unsigned int i;
1035
1036         if (!BNXT_HAS_RING_GRPS(bp)) {
1037                 for (i = 0; i < bp->rx_nr_rings; i++) {
1038                         rxq = bp->eth_dev->data->rx_queues[i];
1039                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1040                                 return rxq->index;
1041                 }
1042         } else {
1043                 for (i = 0; i < bp->rx_nr_rings; i++) {
1044                         if (bp->grp_info[i].fw_grp_id == fwr)
1045                                 return i;
1046                 }
1047         }
1048
1049         return INVALID_HW_RING_ID;
1050 }
1051
1052 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1053                             struct rte_eth_rss_reta_entry64 *reta_conf,
1054                             uint16_t reta_size)
1055 {
1056         struct bnxt *bp = eth_dev->data->dev_private;
1057         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1058         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1059         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1060         uint16_t idx, sft;
1061         int i;
1062
1063         if (!vnic->rss_table)
1064                 return -EINVAL;
1065
1066         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1067                 return -EINVAL;
1068
1069         if (reta_size != tbl_size) {
1070                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1071                         "(%d) must equal the size supported by the hardware "
1072                         "(%d)\n", reta_size, tbl_size);
1073                 return -EINVAL;
1074         }
1075
1076         for (i = 0; i < reta_size; i++) {
1077                 struct bnxt_rx_queue *rxq;
1078
1079                 idx = i / RTE_RETA_GROUP_SIZE;
1080                 sft = i % RTE_RETA_GROUP_SIZE;
1081
1082                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1083                         continue;
1084
1085                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1086                 if (!rxq) {
1087                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1088                         return -EINVAL;
1089                 }
1090
1091                 if (BNXT_CHIP_THOR(bp)) {
1092                         vnic->rss_table[i * 2] =
1093                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1094                         vnic->rss_table[i * 2 + 1] =
1095                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1096                 } else {
1097                         vnic->rss_table[i] =
1098                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1099                 }
1100
1101                 vnic->rss_table[i] =
1102                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1103         }
1104
1105         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1106         return 0;
1107 }
1108
1109 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1110                               struct rte_eth_rss_reta_entry64 *reta_conf,
1111                               uint16_t reta_size)
1112 {
1113         struct bnxt *bp = eth_dev->data->dev_private;
1114         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1115         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1116         uint16_t idx, sft, i;
1117
1118         /* Retrieve from the default VNIC */
1119         if (!vnic)
1120                 return -EINVAL;
1121         if (!vnic->rss_table)
1122                 return -EINVAL;
1123
1124         if (reta_size != tbl_size) {
1125                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1126                         "(%d) must equal the size supported by the hardware "
1127                         "(%d)\n", reta_size, tbl_size);
1128                 return -EINVAL;
1129         }
1130
1131         for (idx = 0, i = 0; i < reta_size; i++) {
1132                 idx = i / RTE_RETA_GROUP_SIZE;
1133                 sft = i % RTE_RETA_GROUP_SIZE;
1134
1135                 if (reta_conf[idx].mask & (1ULL << sft)) {
1136                         uint16_t qid;
1137
1138                         if (BNXT_CHIP_THOR(bp))
1139                                 qid = bnxt_rss_to_qid(bp,
1140                                                       vnic->rss_table[i * 2]);
1141                         else
1142                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1143
1144                         if (qid == INVALID_HW_RING_ID) {
1145                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1146                                 return -EINVAL;
1147                         }
1148                         reta_conf[idx].reta[sft] = qid;
1149                 }
1150         }
1151
1152         return 0;
1153 }
1154
1155 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1156                                    struct rte_eth_rss_conf *rss_conf)
1157 {
1158         struct bnxt *bp = eth_dev->data->dev_private;
1159         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1160         struct bnxt_vnic_info *vnic;
1161         uint16_t hash_type = 0;
1162         unsigned int i;
1163
1164         /*
1165          * If RSS enablement were different than dev_configure,
1166          * then return -EINVAL
1167          */
1168         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1169                 if (!rss_conf->rss_hf)
1170                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1171         } else {
1172                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1173                         return -EINVAL;
1174         }
1175
1176         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1177         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1178
1179         if (rss_conf->rss_hf & ETH_RSS_IPV4)
1180                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1181         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1182                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1183         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1184                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1185         if (rss_conf->rss_hf & ETH_RSS_IPV6)
1186                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1187         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1188                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1189         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1190                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1191
1192         /* Update the RSS VNIC(s) */
1193         for (i = 0; i < bp->nr_vnics; i++) {
1194                 vnic = &bp->vnic_info[i];
1195                 vnic->hash_type = hash_type;
1196
1197                 /*
1198                  * Use the supplied key if the key length is
1199                  * acceptable and the rss_key is not NULL
1200                  */
1201                 if (rss_conf->rss_key &&
1202                     rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1203                         memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1204                                rss_conf->rss_key_len);
1205
1206                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1207         }
1208         return 0;
1209 }
1210
1211 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1212                                      struct rte_eth_rss_conf *rss_conf)
1213 {
1214         struct bnxt *bp = eth_dev->data->dev_private;
1215         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1216         int len;
1217         uint32_t hash_types;
1218
1219         /* RSS configuration is the same for all VNICs */
1220         if (vnic && vnic->rss_hash_key) {
1221                 if (rss_conf->rss_key) {
1222                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1223                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1224                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1225                 }
1226
1227                 hash_types = vnic->hash_type;
1228                 rss_conf->rss_hf = 0;
1229                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1230                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1231                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1232                 }
1233                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1234                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1235                         hash_types &=
1236                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1237                 }
1238                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1239                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1240                         hash_types &=
1241                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1242                 }
1243                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1244                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1245                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1246                 }
1247                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1248                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1249                         hash_types &=
1250                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1251                 }
1252                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1253                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1254                         hash_types &=
1255                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1256                 }
1257                 if (hash_types) {
1258                         PMD_DRV_LOG(ERR,
1259                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1260                                 vnic->hash_type);
1261                         return -ENOTSUP;
1262                 }
1263         } else {
1264                 rss_conf->rss_hf = 0;
1265         }
1266         return 0;
1267 }
1268
1269 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1270                                struct rte_eth_fc_conf *fc_conf)
1271 {
1272         struct bnxt *bp = dev->data->dev_private;
1273         struct rte_eth_link link_info;
1274         int rc;
1275
1276         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1277         if (rc)
1278                 return rc;
1279
1280         memset(fc_conf, 0, sizeof(*fc_conf));
1281         if (bp->link_info.auto_pause)
1282                 fc_conf->autoneg = 1;
1283         switch (bp->link_info.pause) {
1284         case 0:
1285                 fc_conf->mode = RTE_FC_NONE;
1286                 break;
1287         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1288                 fc_conf->mode = RTE_FC_TX_PAUSE;
1289                 break;
1290         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1291                 fc_conf->mode = RTE_FC_RX_PAUSE;
1292                 break;
1293         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1294                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1295                 fc_conf->mode = RTE_FC_FULL;
1296                 break;
1297         }
1298         return 0;
1299 }
1300
1301 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1302                                struct rte_eth_fc_conf *fc_conf)
1303 {
1304         struct bnxt *bp = dev->data->dev_private;
1305
1306         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1307                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1308                 return -ENOTSUP;
1309         }
1310
1311         switch (fc_conf->mode) {
1312         case RTE_FC_NONE:
1313                 bp->link_info.auto_pause = 0;
1314                 bp->link_info.force_pause = 0;
1315                 break;
1316         case RTE_FC_RX_PAUSE:
1317                 if (fc_conf->autoneg) {
1318                         bp->link_info.auto_pause =
1319                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1320                         bp->link_info.force_pause = 0;
1321                 } else {
1322                         bp->link_info.auto_pause = 0;
1323                         bp->link_info.force_pause =
1324                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1325                 }
1326                 break;
1327         case RTE_FC_TX_PAUSE:
1328                 if (fc_conf->autoneg) {
1329                         bp->link_info.auto_pause =
1330                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1331                         bp->link_info.force_pause = 0;
1332                 } else {
1333                         bp->link_info.auto_pause = 0;
1334                         bp->link_info.force_pause =
1335                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1336                 }
1337                 break;
1338         case RTE_FC_FULL:
1339                 if (fc_conf->autoneg) {
1340                         bp->link_info.auto_pause =
1341                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1342                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1343                         bp->link_info.force_pause = 0;
1344                 } else {
1345                         bp->link_info.auto_pause = 0;
1346                         bp->link_info.force_pause =
1347                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1348                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1349                 }
1350                 break;
1351         }
1352         return bnxt_set_hwrm_link_config(bp, true);
1353 }
1354
1355 /* Add UDP tunneling port */
1356 static int
1357 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1358                          struct rte_eth_udp_tunnel *udp_tunnel)
1359 {
1360         struct bnxt *bp = eth_dev->data->dev_private;
1361         uint16_t tunnel_type = 0;
1362         int rc = 0;
1363
1364         switch (udp_tunnel->prot_type) {
1365         case RTE_TUNNEL_TYPE_VXLAN:
1366                 if (bp->vxlan_port_cnt) {
1367                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1368                                 udp_tunnel->udp_port);
1369                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1370                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1371                                 return -ENOSPC;
1372                         }
1373                         bp->vxlan_port_cnt++;
1374                         return 0;
1375                 }
1376                 tunnel_type =
1377                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1378                 bp->vxlan_port_cnt++;
1379                 break;
1380         case RTE_TUNNEL_TYPE_GENEVE:
1381                 if (bp->geneve_port_cnt) {
1382                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1383                                 udp_tunnel->udp_port);
1384                         if (bp->geneve_port != udp_tunnel->udp_port) {
1385                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1386                                 return -ENOSPC;
1387                         }
1388                         bp->geneve_port_cnt++;
1389                         return 0;
1390                 }
1391                 tunnel_type =
1392                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1393                 bp->geneve_port_cnt++;
1394                 break;
1395         default:
1396                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1397                 return -ENOTSUP;
1398         }
1399         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1400                                              tunnel_type);
1401         return rc;
1402 }
1403
1404 static int
1405 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1406                          struct rte_eth_udp_tunnel *udp_tunnel)
1407 {
1408         struct bnxt *bp = eth_dev->data->dev_private;
1409         uint16_t tunnel_type = 0;
1410         uint16_t port = 0;
1411         int rc = 0;
1412
1413         switch (udp_tunnel->prot_type) {
1414         case RTE_TUNNEL_TYPE_VXLAN:
1415                 if (!bp->vxlan_port_cnt) {
1416                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1417                         return -EINVAL;
1418                 }
1419                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1420                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1421                                 udp_tunnel->udp_port, bp->vxlan_port);
1422                         return -EINVAL;
1423                 }
1424                 if (--bp->vxlan_port_cnt)
1425                         return 0;
1426
1427                 tunnel_type =
1428                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1429                 port = bp->vxlan_fw_dst_port_id;
1430                 break;
1431         case RTE_TUNNEL_TYPE_GENEVE:
1432                 if (!bp->geneve_port_cnt) {
1433                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1434                         return -EINVAL;
1435                 }
1436                 if (bp->geneve_port != udp_tunnel->udp_port) {
1437                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1438                                 udp_tunnel->udp_port, bp->geneve_port);
1439                         return -EINVAL;
1440                 }
1441                 if (--bp->geneve_port_cnt)
1442                         return 0;
1443
1444                 tunnel_type =
1445                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1446                 port = bp->geneve_fw_dst_port_id;
1447                 break;
1448         default:
1449                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1450                 return -ENOTSUP;
1451         }
1452
1453         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1454         if (!rc) {
1455                 if (tunnel_type ==
1456                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1457                         bp->vxlan_port = 0;
1458                 if (tunnel_type ==
1459                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1460                         bp->geneve_port = 0;
1461         }
1462         return rc;
1463 }
1464
1465 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1466 {
1467         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1468         struct bnxt_vnic_info *vnic;
1469         unsigned int i;
1470         int rc = 0;
1471         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1472
1473         /* Cycle through all VNICs */
1474         for (i = 0; i < bp->nr_vnics; i++) {
1475                 /*
1476                  * For each VNIC and each associated filter(s)
1477                  * if VLAN exists && VLAN matches vlan_id
1478                  *      remove the MAC+VLAN filter
1479                  *      add a new MAC only filter
1480                  * else
1481                  *      VLAN filter doesn't exist, just skip and continue
1482                  */
1483                 vnic = &bp->vnic_info[i];
1484                 filter = STAILQ_FIRST(&vnic->filter);
1485                 while (filter) {
1486                         temp_filter = STAILQ_NEXT(filter, next);
1487
1488                         if (filter->enables & chk &&
1489                             filter->l2_ovlan == vlan_id) {
1490                                 /* Must delete the filter */
1491                                 STAILQ_REMOVE(&vnic->filter, filter,
1492                                               bnxt_filter_info, next);
1493                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1494                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1495                                                    filter, next);
1496
1497                                 /*
1498                                  * Need to examine to see if the MAC
1499                                  * filter already existed or not before
1500                                  * allocating a new one
1501                                  */
1502
1503                                 new_filter = bnxt_alloc_filter(bp);
1504                                 if (!new_filter) {
1505                                         PMD_DRV_LOG(ERR,
1506                                                         "MAC/VLAN filter alloc failed\n");
1507                                         rc = -ENOMEM;
1508                                         goto exit;
1509                                 }
1510                                 STAILQ_INSERT_TAIL(&vnic->filter,
1511                                                 new_filter, next);
1512                                 /* Inherit MAC from previous filter */
1513                                 new_filter->mac_index =
1514                                         filter->mac_index;
1515                                 memcpy(new_filter->l2_addr, filter->l2_addr,
1516                                        RTE_ETHER_ADDR_LEN);
1517                                 /* MAC only filter */
1518                                 rc = bnxt_hwrm_set_l2_filter(bp,
1519                                                              vnic->fw_vnic_id,
1520                                                              new_filter);
1521                                 if (rc)
1522                                         goto exit;
1523                                 PMD_DRV_LOG(INFO,
1524                                             "Del Vlan filter for %d\n",
1525                                             vlan_id);
1526                         }
1527                         filter = temp_filter;
1528                 }
1529         }
1530 exit:
1531         return rc;
1532 }
1533
1534 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1535 {
1536         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1537         struct bnxt_vnic_info *vnic;
1538         unsigned int i;
1539         int rc = 0;
1540         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1541                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1542         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1543
1544         /* Cycle through all VNICs */
1545         for (i = 0; i < bp->nr_vnics; i++) {
1546                 /*
1547                  * For each VNIC and each associated filter(s)
1548                  * if VLAN exists:
1549                  *   if VLAN matches vlan_id
1550                  *      VLAN filter already exists, just skip and continue
1551                  *   else
1552                  *      add a new MAC+VLAN filter
1553                  * else
1554                  *   Remove the old MAC only filter
1555                  *    Add a new MAC+VLAN filter
1556                  */
1557                 vnic = &bp->vnic_info[i];
1558                 filter = STAILQ_FIRST(&vnic->filter);
1559                 while (filter) {
1560                         temp_filter = STAILQ_NEXT(filter, next);
1561
1562                         if (filter->enables & chk) {
1563                                 if (filter->l2_ivlan == vlan_id)
1564                                         goto cont;
1565                         } else {
1566                                 /* Must delete the MAC filter */
1567                                 STAILQ_REMOVE(&vnic->filter, filter,
1568                                                 bnxt_filter_info, next);
1569                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1570                                 filter->l2_ovlan = 0;
1571                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1572                                                    filter, next);
1573                         }
1574                         new_filter = bnxt_alloc_filter(bp);
1575                         if (!new_filter) {
1576                                 PMD_DRV_LOG(ERR,
1577                                                 "MAC/VLAN filter alloc failed\n");
1578                                 rc = -ENOMEM;
1579                                 goto exit;
1580                         }
1581                         STAILQ_INSERT_TAIL(&vnic->filter, new_filter, next);
1582                         /* Inherit MAC from the previous filter */
1583                         new_filter->mac_index = filter->mac_index;
1584                         memcpy(new_filter->l2_addr, filter->l2_addr,
1585                                RTE_ETHER_ADDR_LEN);
1586                         /* MAC + VLAN ID filter */
1587                         new_filter->l2_ivlan = vlan_id;
1588                         new_filter->l2_ivlan_mask = 0xF000;
1589                         new_filter->enables |= en;
1590                         rc = bnxt_hwrm_set_l2_filter(bp,
1591                                         vnic->fw_vnic_id,
1592                                         new_filter);
1593                         if (rc)
1594                                 goto exit;
1595                         PMD_DRV_LOG(INFO,
1596                                     "Added Vlan filter for %d\n", vlan_id);
1597 cont:
1598                         filter = temp_filter;
1599                 }
1600         }
1601 exit:
1602         return rc;
1603 }
1604
1605 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1606                 uint16_t vlan_id, int on)
1607 {
1608         struct bnxt *bp = eth_dev->data->dev_private;
1609
1610         /* These operations apply to ALL existing MAC/VLAN filters */
1611         if (on)
1612                 return bnxt_add_vlan_filter(bp, vlan_id);
1613         else
1614                 return bnxt_del_vlan_filter(bp, vlan_id);
1615 }
1616
1617 static int
1618 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1619 {
1620         struct bnxt *bp = dev->data->dev_private;
1621         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1622         unsigned int i;
1623
1624         if (mask & ETH_VLAN_FILTER_MASK) {
1625                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1626                         /* Remove any VLAN filters programmed */
1627                         for (i = 0; i < 4095; i++)
1628                                 bnxt_del_vlan_filter(bp, i);
1629                 }
1630                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1631                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1632         }
1633
1634         if (mask & ETH_VLAN_STRIP_MASK) {
1635                 /* Enable or disable VLAN stripping */
1636                 for (i = 0; i < bp->nr_vnics; i++) {
1637                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1638                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1639                                 vnic->vlan_strip = true;
1640                         else
1641                                 vnic->vlan_strip = false;
1642                         bnxt_hwrm_vnic_cfg(bp, vnic);
1643                 }
1644                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1645                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1646         }
1647
1648         if (mask & ETH_VLAN_EXTEND_MASK)
1649                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1650
1651         return 0;
1652 }
1653
1654 static int
1655 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1656                         struct rte_ether_addr *addr)
1657 {
1658         struct bnxt *bp = dev->data->dev_private;
1659         /* Default Filter is tied to VNIC 0 */
1660         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1661         struct bnxt_filter_info *filter;
1662         int rc;
1663
1664         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1665                 return -EPERM;
1666
1667         memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1668
1669         STAILQ_FOREACH(filter, &vnic->filter, next) {
1670                 /* Default Filter is at Index 0 */
1671                 if (filter->mac_index != 0)
1672                         continue;
1673                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1674                 if (rc)
1675                         return rc;
1676                 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1677                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1678                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1679                 filter->enables |=
1680                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1681                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1682                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1683                 if (rc)
1684                         return rc;
1685                 filter->mac_index = 0;
1686                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1687         }
1688
1689         return 0;
1690 }
1691
1692 static int
1693 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1694                           struct rte_ether_addr *mc_addr_set,
1695                           uint32_t nb_mc_addr)
1696 {
1697         struct bnxt *bp = eth_dev->data->dev_private;
1698         char *mc_addr_list = (char *)mc_addr_set;
1699         struct bnxt_vnic_info *vnic;
1700         uint32_t off = 0, i = 0;
1701
1702         vnic = &bp->vnic_info[0];
1703
1704         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1705                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1706                 goto allmulti;
1707         }
1708
1709         /* TODO Check for Duplicate mcast addresses */
1710         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1711         for (i = 0; i < nb_mc_addr; i++) {
1712                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1713                         RTE_ETHER_ADDR_LEN);
1714                 off += RTE_ETHER_ADDR_LEN;
1715         }
1716
1717         vnic->mc_addr_cnt = i;
1718
1719 allmulti:
1720         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1721 }
1722
1723 static int
1724 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1725 {
1726         struct bnxt *bp = dev->data->dev_private;
1727         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1728         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1729         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1730         int ret;
1731
1732         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1733                         fw_major, fw_minor, fw_updt);
1734
1735         ret += 1; /* add the size of '\0' */
1736         if (fw_size < (uint32_t)ret)
1737                 return ret;
1738         else
1739                 return 0;
1740 }
1741
1742 static void
1743 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1744         struct rte_eth_rxq_info *qinfo)
1745 {
1746         struct bnxt_rx_queue *rxq;
1747
1748         rxq = dev->data->rx_queues[queue_id];
1749
1750         qinfo->mp = rxq->mb_pool;
1751         qinfo->scattered_rx = dev->data->scattered_rx;
1752         qinfo->nb_desc = rxq->nb_rx_desc;
1753
1754         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1755         qinfo->conf.rx_drop_en = 0;
1756         qinfo->conf.rx_deferred_start = 0;
1757 }
1758
1759 static void
1760 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1761         struct rte_eth_txq_info *qinfo)
1762 {
1763         struct bnxt_tx_queue *txq;
1764
1765         txq = dev->data->tx_queues[queue_id];
1766
1767         qinfo->nb_desc = txq->nb_tx_desc;
1768
1769         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1770         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1771         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1772
1773         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1774         qinfo->conf.tx_rs_thresh = 0;
1775         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1776 }
1777
1778 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1779 {
1780         struct bnxt *bp = eth_dev->data->dev_private;
1781         struct rte_eth_dev_info dev_info;
1782         uint32_t new_pkt_size;
1783         uint32_t rc = 0;
1784         uint32_t i;
1785
1786         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1787                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1788
1789         bnxt_dev_info_get_op(eth_dev, &dev_info);
1790
1791         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1792                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1793                         RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1794                 return -EINVAL;
1795         }
1796
1797 #ifdef RTE_ARCH_X86
1798         /*
1799          * If vector-mode tx/rx is active, disallow any MTU change that would
1800          * require scattered receive support.
1801          */
1802         if (eth_dev->data->dev_started &&
1803             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1804              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1805             (new_pkt_size >
1806              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1807                 PMD_DRV_LOG(ERR,
1808                             "MTU change would require scattered rx support. ");
1809                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1810                 return -EINVAL;
1811         }
1812 #endif
1813
1814         if (new_mtu > RTE_ETHER_MTU) {
1815                 bp->flags |= BNXT_FLAG_JUMBO;
1816                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1817                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1818         } else {
1819                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1820                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1821                 bp->flags &= ~BNXT_FLAG_JUMBO;
1822         }
1823
1824         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
1825
1826         eth_dev->data->mtu = new_mtu;
1827         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1828
1829         for (i = 0; i < bp->nr_vnics; i++) {
1830                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1831                 uint16_t size = 0;
1832
1833                 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1834                                         RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1835                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1836                 if (rc)
1837                         break;
1838
1839                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1840                 size -= RTE_PKTMBUF_HEADROOM;
1841
1842                 if (size < new_mtu) {
1843                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1844                         if (rc)
1845                                 return rc;
1846                 }
1847         }
1848
1849         return rc;
1850 }
1851
1852 static int
1853 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1854 {
1855         struct bnxt *bp = dev->data->dev_private;
1856         uint16_t vlan = bp->vlan;
1857         int rc;
1858
1859         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1860                 PMD_DRV_LOG(ERR,
1861                         "PVID cannot be modified for this function\n");
1862                 return -ENOTSUP;
1863         }
1864         bp->vlan = on ? pvid : 0;
1865
1866         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1867         if (rc)
1868                 bp->vlan = vlan;
1869         return rc;
1870 }
1871
1872 static int
1873 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1874 {
1875         struct bnxt *bp = dev->data->dev_private;
1876
1877         return bnxt_hwrm_port_led_cfg(bp, true);
1878 }
1879
1880 static int
1881 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1882 {
1883         struct bnxt *bp = dev->data->dev_private;
1884
1885         return bnxt_hwrm_port_led_cfg(bp, false);
1886 }
1887
1888 static uint32_t
1889 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1890 {
1891         uint32_t desc = 0, raw_cons = 0, cons;
1892         struct bnxt_cp_ring_info *cpr;
1893         struct bnxt_rx_queue *rxq;
1894         struct rx_pkt_cmpl *rxcmp;
1895         uint16_t cmp_type;
1896         uint8_t cmp = 1;
1897         bool valid;
1898
1899         rxq = dev->data->rx_queues[rx_queue_id];
1900         cpr = rxq->cp_ring;
1901         valid = cpr->valid;
1902
1903         while (raw_cons < rxq->nb_rx_desc) {
1904                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1905                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1906
1907                 if (!CMPL_VALID(rxcmp, valid))
1908                         goto nothing_to_do;
1909                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1910                 cmp_type = CMP_TYPE(rxcmp);
1911                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1912                         cmp = (rte_le_to_cpu_32(
1913                                         ((struct rx_tpa_end_cmpl *)
1914                                          (rxcmp))->agg_bufs_v1) &
1915                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1916                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1917                         desc++;
1918                 } else if (cmp_type == 0x11) {
1919                         desc++;
1920                         cmp = (rxcmp->agg_bufs_v1 &
1921                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1922                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1923                 } else {
1924                         cmp = 1;
1925                 }
1926 nothing_to_do:
1927                 raw_cons += cmp ? cmp : 2;
1928         }
1929
1930         return desc;
1931 }
1932
1933 static int
1934 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1935 {
1936         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1937         struct bnxt_rx_ring_info *rxr;
1938         struct bnxt_cp_ring_info *cpr;
1939         struct bnxt_sw_rx_bd *rx_buf;
1940         struct rx_pkt_cmpl *rxcmp;
1941         uint32_t cons, cp_cons;
1942
1943         if (!rxq)
1944                 return -EINVAL;
1945
1946         cpr = rxq->cp_ring;
1947         rxr = rxq->rx_ring;
1948
1949         if (offset >= rxq->nb_rx_desc)
1950                 return -EINVAL;
1951
1952         cons = RING_CMP(cpr->cp_ring_struct, offset);
1953         cp_cons = cpr->cp_raw_cons;
1954         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1955
1956         if (cons > cp_cons) {
1957                 if (CMPL_VALID(rxcmp, cpr->valid))
1958                         return RTE_ETH_RX_DESC_DONE;
1959         } else {
1960                 if (CMPL_VALID(rxcmp, !cpr->valid))
1961                         return RTE_ETH_RX_DESC_DONE;
1962         }
1963         rx_buf = &rxr->rx_buf_ring[cons];
1964         if (rx_buf->mbuf == NULL)
1965                 return RTE_ETH_RX_DESC_UNAVAIL;
1966
1967
1968         return RTE_ETH_RX_DESC_AVAIL;
1969 }
1970
1971 static int
1972 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1973 {
1974         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1975         struct bnxt_tx_ring_info *txr;
1976         struct bnxt_cp_ring_info *cpr;
1977         struct bnxt_sw_tx_bd *tx_buf;
1978         struct tx_pkt_cmpl *txcmp;
1979         uint32_t cons, cp_cons;
1980
1981         if (!txq)
1982                 return -EINVAL;
1983
1984         cpr = txq->cp_ring;
1985         txr = txq->tx_ring;
1986
1987         if (offset >= txq->nb_tx_desc)
1988                 return -EINVAL;
1989
1990         cons = RING_CMP(cpr->cp_ring_struct, offset);
1991         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1992         cp_cons = cpr->cp_raw_cons;
1993
1994         if (cons > cp_cons) {
1995                 if (CMPL_VALID(txcmp, cpr->valid))
1996                         return RTE_ETH_TX_DESC_UNAVAIL;
1997         } else {
1998                 if (CMPL_VALID(txcmp, !cpr->valid))
1999                         return RTE_ETH_TX_DESC_UNAVAIL;
2000         }
2001         tx_buf = &txr->tx_buf_ring[cons];
2002         if (tx_buf->mbuf == NULL)
2003                 return RTE_ETH_TX_DESC_DONE;
2004
2005         return RTE_ETH_TX_DESC_FULL;
2006 }
2007
2008 static struct bnxt_filter_info *
2009 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2010                                 struct rte_eth_ethertype_filter *efilter,
2011                                 struct bnxt_vnic_info *vnic0,
2012                                 struct bnxt_vnic_info *vnic,
2013                                 int *ret)
2014 {
2015         struct bnxt_filter_info *mfilter = NULL;
2016         int match = 0;
2017         *ret = 0;
2018
2019         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2020                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2021                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2022                         " ethertype filter.", efilter->ether_type);
2023                 *ret = -EINVAL;
2024                 goto exit;
2025         }
2026         if (efilter->queue >= bp->rx_nr_rings) {
2027                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2028                 *ret = -EINVAL;
2029                 goto exit;
2030         }
2031
2032         vnic0 = &bp->vnic_info[0];
2033         vnic = &bp->vnic_info[efilter->queue];
2034         if (vnic == NULL) {
2035                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2036                 *ret = -EINVAL;
2037                 goto exit;
2038         }
2039
2040         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2041                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2042                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2043                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2044                              mfilter->flags ==
2045                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2046                              mfilter->ethertype == efilter->ether_type)) {
2047                                 match = 1;
2048                                 break;
2049                         }
2050                 }
2051         } else {
2052                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2053                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2054                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2055                              mfilter->ethertype == efilter->ether_type &&
2056                              mfilter->flags ==
2057                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2058                                 match = 1;
2059                                 break;
2060                         }
2061         }
2062
2063         if (match)
2064                 *ret = -EEXIST;
2065
2066 exit:
2067         return mfilter;
2068 }
2069
2070 static int
2071 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2072                         enum rte_filter_op filter_op,
2073                         void *arg)
2074 {
2075         struct bnxt *bp = dev->data->dev_private;
2076         struct rte_eth_ethertype_filter *efilter =
2077                         (struct rte_eth_ethertype_filter *)arg;
2078         struct bnxt_filter_info *bfilter, *filter1;
2079         struct bnxt_vnic_info *vnic, *vnic0;
2080         int ret;
2081
2082         if (filter_op == RTE_ETH_FILTER_NOP)
2083                 return 0;
2084
2085         if (arg == NULL) {
2086                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2087                             filter_op);
2088                 return -EINVAL;
2089         }
2090
2091         vnic0 = &bp->vnic_info[0];
2092         vnic = &bp->vnic_info[efilter->queue];
2093
2094         switch (filter_op) {
2095         case RTE_ETH_FILTER_ADD:
2096                 bnxt_match_and_validate_ether_filter(bp, efilter,
2097                                                         vnic0, vnic, &ret);
2098                 if (ret < 0)
2099                         return ret;
2100
2101                 bfilter = bnxt_get_unused_filter(bp);
2102                 if (bfilter == NULL) {
2103                         PMD_DRV_LOG(ERR,
2104                                 "Not enough resources for a new filter.\n");
2105                         return -ENOMEM;
2106                 }
2107                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2108                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2109                        RTE_ETHER_ADDR_LEN);
2110                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2111                        RTE_ETHER_ADDR_LEN);
2112                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2113                 bfilter->ethertype = efilter->ether_type;
2114                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2115
2116                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2117                 if (filter1 == NULL) {
2118                         ret = -1;
2119                         goto cleanup;
2120                 }
2121                 bfilter->enables |=
2122                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2123                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2124
2125                 bfilter->dst_id = vnic->fw_vnic_id;
2126
2127                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2128                         bfilter->flags =
2129                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2130                 }
2131
2132                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2133                 if (ret)
2134                         goto cleanup;
2135                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2136                 break;
2137         case RTE_ETH_FILTER_DELETE:
2138                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2139                                                         vnic0, vnic, &ret);
2140                 if (ret == -EEXIST) {
2141                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2142
2143                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2144                                       next);
2145                         bnxt_free_filter(bp, filter1);
2146                 } else if (ret == 0) {
2147                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2148                 }
2149                 break;
2150         default:
2151                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2152                 ret = -EINVAL;
2153                 goto error;
2154         }
2155         return ret;
2156 cleanup:
2157         bnxt_free_filter(bp, bfilter);
2158 error:
2159         return ret;
2160 }
2161
2162 static inline int
2163 parse_ntuple_filter(struct bnxt *bp,
2164                     struct rte_eth_ntuple_filter *nfilter,
2165                     struct bnxt_filter_info *bfilter)
2166 {
2167         uint32_t en = 0;
2168
2169         if (nfilter->queue >= bp->rx_nr_rings) {
2170                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2171                 return -EINVAL;
2172         }
2173
2174         switch (nfilter->dst_port_mask) {
2175         case UINT16_MAX:
2176                 bfilter->dst_port_mask = -1;
2177                 bfilter->dst_port = nfilter->dst_port;
2178                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2179                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2180                 break;
2181         default:
2182                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2183                 return -EINVAL;
2184         }
2185
2186         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2187         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2188
2189         switch (nfilter->proto_mask) {
2190         case UINT8_MAX:
2191                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2192                         bfilter->ip_protocol = 17;
2193                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2194                         bfilter->ip_protocol = 6;
2195                 else
2196                         return -EINVAL;
2197                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2198                 break;
2199         default:
2200                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2201                 return -EINVAL;
2202         }
2203
2204         switch (nfilter->dst_ip_mask) {
2205         case UINT32_MAX:
2206                 bfilter->dst_ipaddr_mask[0] = -1;
2207                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2208                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2209                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2210                 break;
2211         default:
2212                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2213                 return -EINVAL;
2214         }
2215
2216         switch (nfilter->src_ip_mask) {
2217         case UINT32_MAX:
2218                 bfilter->src_ipaddr_mask[0] = -1;
2219                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2220                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2221                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2222                 break;
2223         default:
2224                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2225                 return -EINVAL;
2226         }
2227
2228         switch (nfilter->src_port_mask) {
2229         case UINT16_MAX:
2230                 bfilter->src_port_mask = -1;
2231                 bfilter->src_port = nfilter->src_port;
2232                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2233                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2234                 break;
2235         default:
2236                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2237                 return -EINVAL;
2238         }
2239
2240         //TODO Priority
2241         //nfilter->priority = (uint8_t)filter->priority;
2242
2243         bfilter->enables = en;
2244         return 0;
2245 }
2246
2247 static struct bnxt_filter_info*
2248 bnxt_match_ntuple_filter(struct bnxt *bp,
2249                          struct bnxt_filter_info *bfilter,
2250                          struct bnxt_vnic_info **mvnic)
2251 {
2252         struct bnxt_filter_info *mfilter = NULL;
2253         int i;
2254
2255         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2256                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2257                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2258                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2259                             bfilter->src_ipaddr_mask[0] ==
2260                             mfilter->src_ipaddr_mask[0] &&
2261                             bfilter->src_port == mfilter->src_port &&
2262                             bfilter->src_port_mask == mfilter->src_port_mask &&
2263                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2264                             bfilter->dst_ipaddr_mask[0] ==
2265                             mfilter->dst_ipaddr_mask[0] &&
2266                             bfilter->dst_port == mfilter->dst_port &&
2267                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2268                             bfilter->flags == mfilter->flags &&
2269                             bfilter->enables == mfilter->enables) {
2270                                 if (mvnic)
2271                                         *mvnic = vnic;
2272                                 return mfilter;
2273                         }
2274                 }
2275         }
2276         return NULL;
2277 }
2278
2279 static int
2280 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2281                        struct rte_eth_ntuple_filter *nfilter,
2282                        enum rte_filter_op filter_op)
2283 {
2284         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2285         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2286         int ret;
2287
2288         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2289                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2290                 return -EINVAL;
2291         }
2292
2293         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2294                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2295                 return -EINVAL;
2296         }
2297
2298         bfilter = bnxt_get_unused_filter(bp);
2299         if (bfilter == NULL) {
2300                 PMD_DRV_LOG(ERR,
2301                         "Not enough resources for a new filter.\n");
2302                 return -ENOMEM;
2303         }
2304         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2305         if (ret < 0)
2306                 goto free_filter;
2307
2308         vnic = &bp->vnic_info[nfilter->queue];
2309         vnic0 = &bp->vnic_info[0];
2310         filter1 = STAILQ_FIRST(&vnic0->filter);
2311         if (filter1 == NULL) {
2312                 ret = -1;
2313                 goto free_filter;
2314         }
2315
2316         bfilter->dst_id = vnic->fw_vnic_id;
2317         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2318         bfilter->enables |=
2319                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2320         bfilter->ethertype = 0x800;
2321         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2322
2323         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2324
2325         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2326             bfilter->dst_id == mfilter->dst_id) {
2327                 PMD_DRV_LOG(ERR, "filter exists.\n");
2328                 ret = -EEXIST;
2329                 goto free_filter;
2330         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2331                    bfilter->dst_id != mfilter->dst_id) {
2332                 mfilter->dst_id = vnic->fw_vnic_id;
2333                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2334                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2335                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2336                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2337                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2338                 goto free_filter;
2339         }
2340         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2341                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2342                 ret = -ENOENT;
2343                 goto free_filter;
2344         }
2345
2346         if (filter_op == RTE_ETH_FILTER_ADD) {
2347                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2348                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2349                 if (ret)
2350                         goto free_filter;
2351                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2352         } else {
2353                 if (mfilter == NULL) {
2354                         /* This should not happen. But for Coverity! */
2355                         ret = -ENOENT;
2356                         goto free_filter;
2357                 }
2358                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2359
2360                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2361                 bnxt_free_filter(bp, mfilter);
2362                 mfilter->fw_l2_filter_id = -1;
2363                 bnxt_free_filter(bp, bfilter);
2364                 bfilter->fw_l2_filter_id = -1;
2365         }
2366
2367         return 0;
2368 free_filter:
2369         bfilter->fw_l2_filter_id = -1;
2370         bnxt_free_filter(bp, bfilter);
2371         return ret;
2372 }
2373
2374 static int
2375 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2376                         enum rte_filter_op filter_op,
2377                         void *arg)
2378 {
2379         struct bnxt *bp = dev->data->dev_private;
2380         int ret;
2381
2382         if (filter_op == RTE_ETH_FILTER_NOP)
2383                 return 0;
2384
2385         if (arg == NULL) {
2386                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2387                             filter_op);
2388                 return -EINVAL;
2389         }
2390
2391         switch (filter_op) {
2392         case RTE_ETH_FILTER_ADD:
2393                 ret = bnxt_cfg_ntuple_filter(bp,
2394                         (struct rte_eth_ntuple_filter *)arg,
2395                         filter_op);
2396                 break;
2397         case RTE_ETH_FILTER_DELETE:
2398                 ret = bnxt_cfg_ntuple_filter(bp,
2399                         (struct rte_eth_ntuple_filter *)arg,
2400                         filter_op);
2401                 break;
2402         default:
2403                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2404                 ret = -EINVAL;
2405                 break;
2406         }
2407         return ret;
2408 }
2409
2410 static int
2411 bnxt_parse_fdir_filter(struct bnxt *bp,
2412                        struct rte_eth_fdir_filter *fdir,
2413                        struct bnxt_filter_info *filter)
2414 {
2415         enum rte_fdir_mode fdir_mode =
2416                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2417         struct bnxt_vnic_info *vnic0, *vnic;
2418         struct bnxt_filter_info *filter1;
2419         uint32_t en = 0;
2420         int i;
2421
2422         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2423                 return -EINVAL;
2424
2425         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2426         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2427
2428         switch (fdir->input.flow_type) {
2429         case RTE_ETH_FLOW_IPV4:
2430         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2431                 /* FALLTHROUGH */
2432                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2433                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2434                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2435                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2436                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2437                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2438                 filter->ip_addr_type =
2439                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2440                 filter->src_ipaddr_mask[0] = 0xffffffff;
2441                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2442                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2443                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2444                 filter->ethertype = 0x800;
2445                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2446                 break;
2447         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2448                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2449                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2450                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2451                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2452                 filter->dst_port_mask = 0xffff;
2453                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2454                 filter->src_port_mask = 0xffff;
2455                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2456                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2457                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2458                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2459                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2460                 filter->ip_protocol = 6;
2461                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2462                 filter->ip_addr_type =
2463                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2464                 filter->src_ipaddr_mask[0] = 0xffffffff;
2465                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2466                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2467                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2468                 filter->ethertype = 0x800;
2469                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2470                 break;
2471         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2472                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2473                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2474                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2475                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2476                 filter->dst_port_mask = 0xffff;
2477                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2478                 filter->src_port_mask = 0xffff;
2479                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2480                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2481                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2482                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2483                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2484                 filter->ip_protocol = 17;
2485                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2486                 filter->ip_addr_type =
2487                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2488                 filter->src_ipaddr_mask[0] = 0xffffffff;
2489                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2490                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2491                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2492                 filter->ethertype = 0x800;
2493                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2494                 break;
2495         case RTE_ETH_FLOW_IPV6:
2496         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2497                 /* FALLTHROUGH */
2498                 filter->ip_addr_type =
2499                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2500                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2501                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2502                 rte_memcpy(filter->src_ipaddr,
2503                            fdir->input.flow.ipv6_flow.src_ip, 16);
2504                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2505                 rte_memcpy(filter->dst_ipaddr,
2506                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2507                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2508                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2509                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2510                 memset(filter->src_ipaddr_mask, 0xff, 16);
2511                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2512                 filter->ethertype = 0x86dd;
2513                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2514                 break;
2515         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2516                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2517                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2518                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2519                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2520                 filter->dst_port_mask = 0xffff;
2521                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2522                 filter->src_port_mask = 0xffff;
2523                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2524                 filter->ip_addr_type =
2525                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2526                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2527                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2528                 rte_memcpy(filter->src_ipaddr,
2529                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2530                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2531                 rte_memcpy(filter->dst_ipaddr,
2532                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2533                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2534                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2535                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2536                 memset(filter->src_ipaddr_mask, 0xff, 16);
2537                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2538                 filter->ethertype = 0x86dd;
2539                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2540                 break;
2541         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2542                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2543                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2544                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2545                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2546                 filter->dst_port_mask = 0xffff;
2547                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2548                 filter->src_port_mask = 0xffff;
2549                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2550                 filter->ip_addr_type =
2551                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2552                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2553                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2554                 rte_memcpy(filter->src_ipaddr,
2555                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2556                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2557                 rte_memcpy(filter->dst_ipaddr,
2558                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2559                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2560                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2561                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2562                 memset(filter->src_ipaddr_mask, 0xff, 16);
2563                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2564                 filter->ethertype = 0x86dd;
2565                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2566                 break;
2567         case RTE_ETH_FLOW_L2_PAYLOAD:
2568                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2569                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2570                 break;
2571         case RTE_ETH_FLOW_VXLAN:
2572                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2573                         return -EINVAL;
2574                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2575                 filter->tunnel_type =
2576                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2577                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2578                 break;
2579         case RTE_ETH_FLOW_NVGRE:
2580                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2581                         return -EINVAL;
2582                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2583                 filter->tunnel_type =
2584                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2585                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2586                 break;
2587         case RTE_ETH_FLOW_UNKNOWN:
2588         case RTE_ETH_FLOW_RAW:
2589         case RTE_ETH_FLOW_FRAG_IPV4:
2590         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2591         case RTE_ETH_FLOW_FRAG_IPV6:
2592         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2593         case RTE_ETH_FLOW_IPV6_EX:
2594         case RTE_ETH_FLOW_IPV6_TCP_EX:
2595         case RTE_ETH_FLOW_IPV6_UDP_EX:
2596         case RTE_ETH_FLOW_GENEVE:
2597                 /* FALLTHROUGH */
2598         default:
2599                 return -EINVAL;
2600         }
2601
2602         vnic0 = &bp->vnic_info[0];
2603         vnic = &bp->vnic_info[fdir->action.rx_queue];
2604         if (vnic == NULL) {
2605                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2606                 return -EINVAL;
2607         }
2608
2609
2610         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2611                 rte_memcpy(filter->dst_macaddr,
2612                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2613                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2614         }
2615
2616         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2617                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2618                 filter1 = STAILQ_FIRST(&vnic0->filter);
2619                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2620         } else {
2621                 filter->dst_id = vnic->fw_vnic_id;
2622                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2623                         if (filter->dst_macaddr[i] == 0x00)
2624                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2625                         else
2626                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2627         }
2628
2629         if (filter1 == NULL)
2630                 return -EINVAL;
2631
2632         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2633         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2634
2635         filter->enables = en;
2636
2637         return 0;
2638 }
2639
2640 static struct bnxt_filter_info *
2641 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2642                 struct bnxt_vnic_info **mvnic)
2643 {
2644         struct bnxt_filter_info *mf = NULL;
2645         int i;
2646
2647         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2648                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2649
2650                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2651                         if (mf->filter_type == nf->filter_type &&
2652                             mf->flags == nf->flags &&
2653                             mf->src_port == nf->src_port &&
2654                             mf->src_port_mask == nf->src_port_mask &&
2655                             mf->dst_port == nf->dst_port &&
2656                             mf->dst_port_mask == nf->dst_port_mask &&
2657                             mf->ip_protocol == nf->ip_protocol &&
2658                             mf->ip_addr_type == nf->ip_addr_type &&
2659                             mf->ethertype == nf->ethertype &&
2660                             mf->vni == nf->vni &&
2661                             mf->tunnel_type == nf->tunnel_type &&
2662                             mf->l2_ovlan == nf->l2_ovlan &&
2663                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2664                             mf->l2_ivlan == nf->l2_ivlan &&
2665                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2666                             !memcmp(mf->l2_addr, nf->l2_addr,
2667                                     RTE_ETHER_ADDR_LEN) &&
2668                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2669                                     RTE_ETHER_ADDR_LEN) &&
2670                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2671                                     RTE_ETHER_ADDR_LEN) &&
2672                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2673                                     RTE_ETHER_ADDR_LEN) &&
2674                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2675                                     sizeof(nf->src_ipaddr)) &&
2676                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2677                                     sizeof(nf->src_ipaddr_mask)) &&
2678                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2679                                     sizeof(nf->dst_ipaddr)) &&
2680                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2681                                     sizeof(nf->dst_ipaddr_mask))) {
2682                                 if (mvnic)
2683                                         *mvnic = vnic;
2684                                 return mf;
2685                         }
2686                 }
2687         }
2688         return NULL;
2689 }
2690
2691 static int
2692 bnxt_fdir_filter(struct rte_eth_dev *dev,
2693                  enum rte_filter_op filter_op,
2694                  void *arg)
2695 {
2696         struct bnxt *bp = dev->data->dev_private;
2697         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2698         struct bnxt_filter_info *filter, *match;
2699         struct bnxt_vnic_info *vnic, *mvnic;
2700         int ret = 0, i;
2701
2702         if (filter_op == RTE_ETH_FILTER_NOP)
2703                 return 0;
2704
2705         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2706                 return -EINVAL;
2707
2708         switch (filter_op) {
2709         case RTE_ETH_FILTER_ADD:
2710         case RTE_ETH_FILTER_DELETE:
2711                 /* FALLTHROUGH */
2712                 filter = bnxt_get_unused_filter(bp);
2713                 if (filter == NULL) {
2714                         PMD_DRV_LOG(ERR,
2715                                 "Not enough resources for a new flow.\n");
2716                         return -ENOMEM;
2717                 }
2718
2719                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2720                 if (ret != 0)
2721                         goto free_filter;
2722                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2723
2724                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2725                         vnic = &bp->vnic_info[0];
2726                 else
2727                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2728
2729                 match = bnxt_match_fdir(bp, filter, &mvnic);
2730                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2731                         if (match->dst_id == vnic->fw_vnic_id) {
2732                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2733                                 ret = -EEXIST;
2734                                 goto free_filter;
2735                         } else {
2736                                 match->dst_id = vnic->fw_vnic_id;
2737                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2738                                                                   match->dst_id,
2739                                                                   match);
2740                                 STAILQ_REMOVE(&mvnic->filter, match,
2741                                               bnxt_filter_info, next);
2742                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2743                                 PMD_DRV_LOG(ERR,
2744                                         "Filter with matching pattern exist\n");
2745                                 PMD_DRV_LOG(ERR,
2746                                         "Updated it to new destination q\n");
2747                                 goto free_filter;
2748                         }
2749                 }
2750                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2751                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2752                         ret = -ENOENT;
2753                         goto free_filter;
2754                 }
2755
2756                 if (filter_op == RTE_ETH_FILTER_ADD) {
2757                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2758                                                           filter->dst_id,
2759                                                           filter);
2760                         if (ret)
2761                                 goto free_filter;
2762                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2763                 } else {
2764                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2765                         STAILQ_REMOVE(&vnic->filter, match,
2766                                       bnxt_filter_info, next);
2767                         bnxt_free_filter(bp, match);
2768                         filter->fw_l2_filter_id = -1;
2769                         bnxt_free_filter(bp, filter);
2770                 }
2771                 break;
2772         case RTE_ETH_FILTER_FLUSH:
2773                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2774                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2775
2776                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2777                                 if (filter->filter_type ==
2778                                     HWRM_CFA_NTUPLE_FILTER) {
2779                                         ret =
2780                                         bnxt_hwrm_clear_ntuple_filter(bp,
2781                                                                       filter);
2782                                         STAILQ_REMOVE(&vnic->filter, filter,
2783                                                       bnxt_filter_info, next);
2784                                 }
2785                         }
2786                 }
2787                 return ret;
2788         case RTE_ETH_FILTER_UPDATE:
2789         case RTE_ETH_FILTER_STATS:
2790         case RTE_ETH_FILTER_INFO:
2791                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2792                 break;
2793         default:
2794                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2795                 ret = -EINVAL;
2796                 break;
2797         }
2798         return ret;
2799
2800 free_filter:
2801         filter->fw_l2_filter_id = -1;
2802         bnxt_free_filter(bp, filter);
2803         return ret;
2804 }
2805
2806 static int
2807 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2808                     enum rte_filter_type filter_type,
2809                     enum rte_filter_op filter_op, void *arg)
2810 {
2811         int ret = 0;
2812
2813         switch (filter_type) {
2814         case RTE_ETH_FILTER_TUNNEL:
2815                 PMD_DRV_LOG(ERR,
2816                         "filter type: %d: To be implemented\n", filter_type);
2817                 break;
2818         case RTE_ETH_FILTER_FDIR:
2819                 ret = bnxt_fdir_filter(dev, filter_op, arg);
2820                 break;
2821         case RTE_ETH_FILTER_NTUPLE:
2822                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2823                 break;
2824         case RTE_ETH_FILTER_ETHERTYPE:
2825                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2826                 break;
2827         case RTE_ETH_FILTER_GENERIC:
2828                 if (filter_op != RTE_ETH_FILTER_GET)
2829                         return -EINVAL;
2830                 *(const void **)arg = &bnxt_flow_ops;
2831                 break;
2832         default:
2833                 PMD_DRV_LOG(ERR,
2834                         "Filter type (%d) not supported", filter_type);
2835                 ret = -EINVAL;
2836                 break;
2837         }
2838         return ret;
2839 }
2840
2841 static const uint32_t *
2842 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2843 {
2844         static const uint32_t ptypes[] = {
2845                 RTE_PTYPE_L2_ETHER_VLAN,
2846                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2847                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2848                 RTE_PTYPE_L4_ICMP,
2849                 RTE_PTYPE_L4_TCP,
2850                 RTE_PTYPE_L4_UDP,
2851                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2852                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2853                 RTE_PTYPE_INNER_L4_ICMP,
2854                 RTE_PTYPE_INNER_L4_TCP,
2855                 RTE_PTYPE_INNER_L4_UDP,
2856                 RTE_PTYPE_UNKNOWN
2857         };
2858
2859         if (!dev->rx_pkt_burst)
2860                 return NULL;
2861
2862         return ptypes;
2863 }
2864
2865 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2866                          int reg_win)
2867 {
2868         uint32_t reg_base = *reg_arr & 0xfffff000;
2869         uint32_t win_off;
2870         int i;
2871
2872         for (i = 0; i < count; i++) {
2873                 if ((reg_arr[i] & 0xfffff000) != reg_base)
2874                         return -ERANGE;
2875         }
2876         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2877         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
2878         return 0;
2879 }
2880
2881 static int bnxt_map_ptp_regs(struct bnxt *bp)
2882 {
2883         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2884         uint32_t *reg_arr;
2885         int rc, i;
2886
2887         reg_arr = ptp->rx_regs;
2888         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2889         if (rc)
2890                 return rc;
2891
2892         reg_arr = ptp->tx_regs;
2893         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2894         if (rc)
2895                 return rc;
2896
2897         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2898                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2899
2900         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2901                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2902
2903         return 0;
2904 }
2905
2906 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2907 {
2908         rte_write32(0, (uint8_t *)bp->bar0 +
2909                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
2910         rte_write32(0, (uint8_t *)bp->bar0 +
2911                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
2912 }
2913
2914 static uint64_t bnxt_cc_read(struct bnxt *bp)
2915 {
2916         uint64_t ns;
2917
2918         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2919                               BNXT_GRCPF_REG_SYNC_TIME));
2920         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2921                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2922         return ns;
2923 }
2924
2925 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2926 {
2927         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2928         uint32_t fifo;
2929
2930         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2931                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2932         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2933                 return -EAGAIN;
2934
2935         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2936                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2937         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2938                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2939         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2940                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2941
2942         return 0;
2943 }
2944
2945 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2946 {
2947         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2948         struct bnxt_pf_info *pf = &bp->pf;
2949         uint16_t port_id;
2950         uint32_t fifo;
2951
2952         if (!ptp)
2953                 return -ENODEV;
2954
2955         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2956                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2957         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2958                 return -EAGAIN;
2959
2960         port_id = pf->port_id;
2961         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2962                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
2963
2964         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2965                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2966         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2967 /*              bnxt_clr_rx_ts(bp);       TBD  */
2968                 return -EBUSY;
2969         }
2970
2971         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2972                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2973         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2974                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2975
2976         return 0;
2977 }
2978
2979 static int
2980 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2981 {
2982         uint64_t ns;
2983         struct bnxt *bp = dev->data->dev_private;
2984         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2985
2986         if (!ptp)
2987                 return 0;
2988
2989         ns = rte_timespec_to_ns(ts);
2990         /* Set the timecounters to a new value. */
2991         ptp->tc.nsec = ns;
2992
2993         return 0;
2994 }
2995
2996 static int
2997 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2998 {
2999         uint64_t ns, systime_cycles;
3000         struct bnxt *bp = dev->data->dev_private;
3001         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3002
3003         if (!ptp)
3004                 return 0;
3005
3006         systime_cycles = bnxt_cc_read(bp);
3007         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3008         *ts = rte_ns_to_timespec(ns);
3009
3010         return 0;
3011 }
3012 static int
3013 bnxt_timesync_enable(struct rte_eth_dev *dev)
3014 {
3015         struct bnxt *bp = dev->data->dev_private;
3016         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3017         uint32_t shift = 0;
3018
3019         if (!ptp)
3020                 return 0;
3021
3022         ptp->rx_filter = 1;
3023         ptp->tx_tstamp_en = 1;
3024         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3025
3026         if (!bnxt_hwrm_ptp_cfg(bp))
3027                 bnxt_map_ptp_regs(bp);
3028
3029         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3030         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3031         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3032
3033         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3034         ptp->tc.cc_shift = shift;
3035         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3036
3037         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3038         ptp->rx_tstamp_tc.cc_shift = shift;
3039         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3040
3041         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3042         ptp->tx_tstamp_tc.cc_shift = shift;
3043         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3044
3045         return 0;
3046 }
3047
3048 static int
3049 bnxt_timesync_disable(struct rte_eth_dev *dev)
3050 {
3051         struct bnxt *bp = dev->data->dev_private;
3052         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3053
3054         if (!ptp)
3055                 return 0;
3056
3057         ptp->rx_filter = 0;
3058         ptp->tx_tstamp_en = 0;
3059         ptp->rxctl = 0;
3060
3061         bnxt_hwrm_ptp_cfg(bp);
3062
3063         bnxt_unmap_ptp_regs(bp);
3064
3065         return 0;
3066 }
3067
3068 static int
3069 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3070                                  struct timespec *timestamp,
3071                                  uint32_t flags __rte_unused)
3072 {
3073         struct bnxt *bp = dev->data->dev_private;
3074         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3075         uint64_t rx_tstamp_cycles = 0;
3076         uint64_t ns;
3077
3078         if (!ptp)
3079                 return 0;
3080
3081         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3082         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3083         *timestamp = rte_ns_to_timespec(ns);
3084         return  0;
3085 }
3086
3087 static int
3088 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3089                                  struct timespec *timestamp)
3090 {
3091         struct bnxt *bp = dev->data->dev_private;
3092         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3093         uint64_t tx_tstamp_cycles = 0;
3094         uint64_t ns;
3095
3096         if (!ptp)
3097                 return 0;
3098
3099         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3100         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3101         *timestamp = rte_ns_to_timespec(ns);
3102
3103         return 0;
3104 }
3105
3106 static int
3107 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3108 {
3109         struct bnxt *bp = dev->data->dev_private;
3110         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3111
3112         if (!ptp)
3113                 return 0;
3114
3115         ptp->tc.nsec += delta;
3116
3117         return 0;
3118 }
3119
3120 static int
3121 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3122 {
3123         struct bnxt *bp = dev->data->dev_private;
3124         int rc;
3125         uint32_t dir_entries;
3126         uint32_t entry_length;
3127
3128         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3129                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3130                 bp->pdev->addr.devid, bp->pdev->addr.function);
3131
3132         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3133         if (rc != 0)
3134                 return rc;
3135
3136         return dir_entries * entry_length;
3137 }
3138
3139 static int
3140 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3141                 struct rte_dev_eeprom_info *in_eeprom)
3142 {
3143         struct bnxt *bp = dev->data->dev_private;
3144         uint32_t index;
3145         uint32_t offset;
3146
3147         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3148                 "len = %d\n", bp->pdev->addr.domain,
3149                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3150                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3151
3152         if (in_eeprom->offset == 0) /* special offset value to get directory */
3153                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3154                                                 in_eeprom->data);
3155
3156         index = in_eeprom->offset >> 24;
3157         offset = in_eeprom->offset & 0xffffff;
3158
3159         if (index != 0)
3160                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3161                                            in_eeprom->length, in_eeprom->data);
3162
3163         return 0;
3164 }
3165
3166 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3167 {
3168         switch (dir_type) {
3169         case BNX_DIR_TYPE_CHIMP_PATCH:
3170         case BNX_DIR_TYPE_BOOTCODE:
3171         case BNX_DIR_TYPE_BOOTCODE_2:
3172         case BNX_DIR_TYPE_APE_FW:
3173         case BNX_DIR_TYPE_APE_PATCH:
3174         case BNX_DIR_TYPE_KONG_FW:
3175         case BNX_DIR_TYPE_KONG_PATCH:
3176         case BNX_DIR_TYPE_BONO_FW:
3177         case BNX_DIR_TYPE_BONO_PATCH:
3178                 /* FALLTHROUGH */
3179                 return true;
3180         }
3181
3182         return false;
3183 }
3184
3185 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3186 {
3187         switch (dir_type) {
3188         case BNX_DIR_TYPE_AVS:
3189         case BNX_DIR_TYPE_EXP_ROM_MBA:
3190         case BNX_DIR_TYPE_PCIE:
3191         case BNX_DIR_TYPE_TSCF_UCODE:
3192         case BNX_DIR_TYPE_EXT_PHY:
3193         case BNX_DIR_TYPE_CCM:
3194         case BNX_DIR_TYPE_ISCSI_BOOT:
3195         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3196         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3197                 /* FALLTHROUGH */
3198                 return true;
3199         }
3200
3201         return false;
3202 }
3203
3204 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3205 {
3206         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3207                 bnxt_dir_type_is_other_exec_format(dir_type);
3208 }
3209
3210 static int
3211 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3212                 struct rte_dev_eeprom_info *in_eeprom)
3213 {
3214         struct bnxt *bp = dev->data->dev_private;
3215         uint8_t index, dir_op;
3216         uint16_t type, ext, ordinal, attr;
3217
3218         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3219                 "len = %d\n", bp->pdev->addr.domain,
3220                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3221                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3222
3223         if (!BNXT_PF(bp)) {
3224                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3225                 return -EINVAL;
3226         }
3227
3228         type = in_eeprom->magic >> 16;
3229
3230         if (type == 0xffff) { /* special value for directory operations */
3231                 index = in_eeprom->magic & 0xff;
3232                 dir_op = in_eeprom->magic >> 8;
3233                 if (index == 0)
3234                         return -EINVAL;
3235                 switch (dir_op) {
3236                 case 0x0e: /* erase */
3237                         if (in_eeprom->offset != ~in_eeprom->magic)
3238                                 return -EINVAL;
3239                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3240                 default:
3241                         return -EINVAL;
3242                 }
3243         }
3244
3245         /* Create or re-write an NVM item: */
3246         if (bnxt_dir_type_is_executable(type) == true)
3247                 return -EOPNOTSUPP;
3248         ext = in_eeprom->magic & 0xffff;
3249         ordinal = in_eeprom->offset >> 16;
3250         attr = in_eeprom->offset & 0xffff;
3251
3252         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3253                                      in_eeprom->data, in_eeprom->length);
3254         return 0;
3255 }
3256
3257 /*
3258  * Initialization
3259  */
3260
3261 static const struct eth_dev_ops bnxt_dev_ops = {
3262         .dev_infos_get = bnxt_dev_info_get_op,
3263         .dev_close = bnxt_dev_close_op,
3264         .dev_configure = bnxt_dev_configure_op,
3265         .dev_start = bnxt_dev_start_op,
3266         .dev_stop = bnxt_dev_stop_op,
3267         .dev_set_link_up = bnxt_dev_set_link_up_op,
3268         .dev_set_link_down = bnxt_dev_set_link_down_op,
3269         .stats_get = bnxt_stats_get_op,
3270         .stats_reset = bnxt_stats_reset_op,
3271         .rx_queue_setup = bnxt_rx_queue_setup_op,
3272         .rx_queue_release = bnxt_rx_queue_release_op,
3273         .tx_queue_setup = bnxt_tx_queue_setup_op,
3274         .tx_queue_release = bnxt_tx_queue_release_op,
3275         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3276         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3277         .reta_update = bnxt_reta_update_op,
3278         .reta_query = bnxt_reta_query_op,
3279         .rss_hash_update = bnxt_rss_hash_update_op,
3280         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3281         .link_update = bnxt_link_update_op,
3282         .promiscuous_enable = bnxt_promiscuous_enable_op,
3283         .promiscuous_disable = bnxt_promiscuous_disable_op,
3284         .allmulticast_enable = bnxt_allmulticast_enable_op,
3285         .allmulticast_disable = bnxt_allmulticast_disable_op,
3286         .mac_addr_add = bnxt_mac_addr_add_op,
3287         .mac_addr_remove = bnxt_mac_addr_remove_op,
3288         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3289         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3290         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3291         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3292         .vlan_filter_set = bnxt_vlan_filter_set_op,
3293         .vlan_offload_set = bnxt_vlan_offload_set_op,
3294         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3295         .mtu_set = bnxt_mtu_set_op,
3296         .mac_addr_set = bnxt_set_default_mac_addr_op,
3297         .xstats_get = bnxt_dev_xstats_get_op,
3298         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3299         .xstats_reset = bnxt_dev_xstats_reset_op,
3300         .fw_version_get = bnxt_fw_version_get,
3301         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3302         .rxq_info_get = bnxt_rxq_info_get_op,
3303         .txq_info_get = bnxt_txq_info_get_op,
3304         .dev_led_on = bnxt_dev_led_on_op,
3305         .dev_led_off = bnxt_dev_led_off_op,
3306         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3307         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3308         .rx_queue_count = bnxt_rx_queue_count_op,
3309         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3310         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3311         .rx_queue_start = bnxt_rx_queue_start,
3312         .rx_queue_stop = bnxt_rx_queue_stop,
3313         .tx_queue_start = bnxt_tx_queue_start,
3314         .tx_queue_stop = bnxt_tx_queue_stop,
3315         .filter_ctrl = bnxt_filter_ctrl_op,
3316         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3317         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3318         .get_eeprom           = bnxt_get_eeprom_op,
3319         .set_eeprom           = bnxt_set_eeprom_op,
3320         .timesync_enable      = bnxt_timesync_enable,
3321         .timesync_disable     = bnxt_timesync_disable,
3322         .timesync_read_time   = bnxt_timesync_read_time,
3323         .timesync_write_time   = bnxt_timesync_write_time,
3324         .timesync_adjust_time = bnxt_timesync_adjust_time,
3325         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3326         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3327 };
3328
3329 static bool bnxt_vf_pciid(uint16_t id)
3330 {
3331         if (id == BROADCOM_DEV_ID_57304_VF ||
3332             id == BROADCOM_DEV_ID_57406_VF ||
3333             id == BROADCOM_DEV_ID_5731X_VF ||
3334             id == BROADCOM_DEV_ID_5741X_VF ||
3335             id == BROADCOM_DEV_ID_57414_VF ||
3336             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3337             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3338             id == BROADCOM_DEV_ID_58802_VF ||
3339             id == BROADCOM_DEV_ID_57500_VF)
3340                 return true;
3341         return false;
3342 }
3343
3344 bool bnxt_stratus_device(struct bnxt *bp)
3345 {
3346         uint16_t id = bp->pdev->id.device_id;
3347
3348         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3349             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3350             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3351                 return true;
3352         return false;
3353 }
3354
3355 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3356 {
3357         struct bnxt *bp = eth_dev->data->dev_private;
3358         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3359         int rc;
3360
3361         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3362         if (!pci_dev->mem_resource[0].addr) {
3363                 PMD_DRV_LOG(ERR,
3364                         "Cannot find PCI device base address, aborting\n");
3365                 rc = -ENODEV;
3366                 goto init_err_disable;
3367         }
3368
3369         bp->eth_dev = eth_dev;
3370         bp->pdev = pci_dev;
3371
3372         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3373         if (!bp->bar0) {
3374                 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3375                 rc = -ENOMEM;
3376                 goto init_err_release;
3377         }
3378
3379         if (!pci_dev->mem_resource[2].addr) {
3380                 PMD_DRV_LOG(ERR,
3381                             "Cannot find PCI device BAR 2 address, aborting\n");
3382                 rc = -ENODEV;
3383                 goto init_err_release;
3384         } else {
3385                 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3386         }
3387
3388         return 0;
3389
3390 init_err_release:
3391         if (bp->bar0)
3392                 bp->bar0 = NULL;
3393         if (bp->doorbell_base)
3394                 bp->doorbell_base = NULL;
3395
3396 init_err_disable:
3397
3398         return rc;
3399 }
3400
3401 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3402                                   struct bnxt_ctx_pg_info *ctx_pg,
3403                                   uint32_t mem_size,
3404                                   const char *suffix,
3405                                   uint16_t idx)
3406 {
3407         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3408         const struct rte_memzone *mz = NULL;
3409         char mz_name[RTE_MEMZONE_NAMESIZE];
3410         rte_iova_t mz_phys_addr;
3411         uint64_t valid_bits = 0;
3412         uint32_t sz;
3413         int i;
3414
3415         if (!mem_size)
3416                 return 0;
3417
3418         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3419                          BNXT_PAGE_SIZE;
3420         rmem->page_size = BNXT_PAGE_SIZE;
3421         rmem->pg_arr = ctx_pg->ctx_pg_arr;
3422         rmem->dma_arr = ctx_pg->ctx_dma_arr;
3423         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3424
3425         valid_bits = PTU_PTE_VALID;
3426
3427         if (rmem->nr_pages > 1) {
3428                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_pg_tbl%s_%x",
3429                          suffix, idx);
3430                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3431                 mz = rte_memzone_lookup(mz_name);
3432                 if (!mz) {
3433                         mz = rte_memzone_reserve_aligned(mz_name,
3434                                                 rmem->nr_pages * 8,
3435                                                 SOCKET_ID_ANY,
3436                                                 RTE_MEMZONE_2MB |
3437                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
3438                                                 RTE_MEMZONE_IOVA_CONTIG,
3439                                                 BNXT_PAGE_SIZE);
3440                         if (mz == NULL)
3441                                 return -ENOMEM;
3442                 }
3443
3444                 memset(mz->addr, 0, mz->len);
3445                 mz_phys_addr = mz->iova;
3446                 if ((unsigned long)mz->addr == mz_phys_addr) {
3447                         PMD_DRV_LOG(WARNING,
3448                                 "Memzone physical address same as virtual.\n");
3449                         PMD_DRV_LOG(WARNING,
3450                                     "Using rte_mem_virt2iova()\n");
3451                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3452                         if (mz_phys_addr == 0) {
3453                                 PMD_DRV_LOG(ERR,
3454                                         "unable to map addr to phys memory\n");
3455                                 return -ENOMEM;
3456                         }
3457                 }
3458                 rte_mem_lock_page(((char *)mz->addr));
3459
3460                 rmem->pg_tbl = mz->addr;
3461                 rmem->pg_tbl_map = mz_phys_addr;
3462                 rmem->pg_tbl_mz = mz;
3463         }
3464
3465         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x", suffix, idx);
3466         mz = rte_memzone_lookup(mz_name);
3467         if (!mz) {
3468                 mz = rte_memzone_reserve_aligned(mz_name,
3469                                                  mem_size,
3470                                                  SOCKET_ID_ANY,
3471                                                  RTE_MEMZONE_1GB |
3472                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
3473                                                  RTE_MEMZONE_IOVA_CONTIG,
3474                                                  BNXT_PAGE_SIZE);
3475                 if (mz == NULL)
3476                         return -ENOMEM;
3477         }
3478
3479         memset(mz->addr, 0, mz->len);
3480         mz_phys_addr = mz->iova;
3481         if ((unsigned long)mz->addr == mz_phys_addr) {
3482                 PMD_DRV_LOG(WARNING,
3483                             "Memzone physical address same as virtual.\n");
3484                 PMD_DRV_LOG(WARNING,
3485                             "Using rte_mem_virt2iova()\n");
3486                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
3487                         rte_mem_lock_page(((char *)mz->addr) + sz);
3488                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3489                 if (mz_phys_addr == RTE_BAD_IOVA) {
3490                         PMD_DRV_LOG(ERR,
3491                                     "unable to map addr to phys memory\n");
3492                         return -ENOMEM;
3493                 }
3494         }
3495
3496         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
3497                 rte_mem_lock_page(((char *)mz->addr) + sz);
3498                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
3499                 rmem->dma_arr[i] = mz_phys_addr + sz;
3500
3501                 if (rmem->nr_pages > 1) {
3502                         if (i == rmem->nr_pages - 2 &&
3503                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3504                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
3505                         else if (i == rmem->nr_pages - 1 &&
3506                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3507                                 valid_bits |= PTU_PTE_LAST;
3508
3509                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
3510                                                            valid_bits);
3511                 }
3512         }
3513
3514         rmem->mz = mz;
3515         if (rmem->vmem_size)
3516                 rmem->vmem = (void **)mz->addr;
3517         rmem->dma_arr[0] = mz_phys_addr;
3518         return 0;
3519 }
3520
3521 static void bnxt_free_ctx_mem(struct bnxt *bp)
3522 {
3523         int i;
3524
3525         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
3526                 return;
3527
3528         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
3529         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
3530         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
3531         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
3532         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
3533         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
3534         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
3535         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
3536         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
3537         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
3538         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
3539
3540         for (i = 0; i < BNXT_MAX_Q; i++) {
3541                 if (bp->ctx->tqm_mem[i])
3542                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
3543         }
3544
3545         rte_free(bp->ctx);
3546         bp->ctx = NULL;
3547 }
3548
3549 #define roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
3550
3551 #define min_t(type, x, y) ({                    \
3552         type __min1 = (x);                      \
3553         type __min2 = (y);                      \
3554         __min1 < __min2 ? __min1 : __min2; })
3555
3556 #define max_t(type, x, y) ({                    \
3557         type __max1 = (x);                      \
3558         type __max2 = (y);                      \
3559         __max1 > __max2 ? __max1 : __max2; })
3560
3561 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
3562
3563 int bnxt_alloc_ctx_mem(struct bnxt *bp)
3564 {
3565         struct bnxt_ctx_pg_info *ctx_pg;
3566         struct bnxt_ctx_mem_info *ctx;
3567         uint32_t mem_size, ena, entries;
3568         int i, rc;
3569
3570         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
3571         if (rc) {
3572                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
3573                 return rc;
3574         }
3575         ctx = bp->ctx;
3576         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
3577                 return 0;
3578
3579         ctx_pg = &ctx->qp_mem;
3580         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
3581         mem_size = ctx->qp_entry_size * ctx_pg->entries;
3582         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
3583         if (rc)
3584                 return rc;
3585
3586         ctx_pg = &ctx->srq_mem;
3587         ctx_pg->entries = ctx->srq_max_l2_entries;
3588         mem_size = ctx->srq_entry_size * ctx_pg->entries;
3589         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
3590         if (rc)
3591                 return rc;
3592
3593         ctx_pg = &ctx->cq_mem;
3594         ctx_pg->entries = ctx->cq_max_l2_entries;
3595         mem_size = ctx->cq_entry_size * ctx_pg->entries;
3596         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
3597         if (rc)
3598                 return rc;
3599
3600         ctx_pg = &ctx->vnic_mem;
3601         ctx_pg->entries = ctx->vnic_max_vnic_entries +
3602                 ctx->vnic_max_ring_table_entries;
3603         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
3604         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
3605         if (rc)
3606                 return rc;
3607
3608         ctx_pg = &ctx->stat_mem;
3609         ctx_pg->entries = ctx->stat_max_entries;
3610         mem_size = ctx->stat_entry_size * ctx_pg->entries;
3611         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
3612         if (rc)
3613                 return rc;
3614
3615         entries = ctx->qp_max_l2_entries;
3616         entries = roundup(entries, ctx->tqm_entries_multiple);
3617         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
3618                           ctx->tqm_max_entries_per_ring);
3619         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
3620                 ctx_pg = ctx->tqm_mem[i];
3621                 /* use min tqm entries for now. */
3622                 ctx_pg->entries = entries;
3623                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
3624                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
3625                 if (rc)
3626                         return rc;
3627                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
3628         }
3629
3630         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
3631         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
3632         if (rc)
3633                 PMD_DRV_LOG(ERR,
3634                             "Failed to configure context mem: rc = %d\n", rc);
3635         else
3636                 ctx->flags |= BNXT_CTX_FLAG_INITED;
3637
3638         return 0;
3639 }
3640
3641 #define ALLOW_FUNC(x)   \
3642         { \
3643                 typeof(x) arg = (x); \
3644                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3645                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3646         }
3647 static int
3648 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3649 {
3650         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3651         char mz_name[RTE_MEMZONE_NAMESIZE];
3652         const struct rte_memzone *mz = NULL;
3653         static int version_printed;
3654         uint32_t total_alloc_len;
3655         rte_iova_t mz_phys_addr;
3656         struct bnxt *bp;
3657         int rc;
3658
3659         if (version_printed++ == 0)
3660                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3661
3662         rte_eth_copy_pci_info(eth_dev, pci_dev);
3663
3664         bp = eth_dev->data->dev_private;
3665
3666         bp->dev_stopped = 1;
3667
3668         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3669                 goto skip_init;
3670
3671         if (bnxt_vf_pciid(pci_dev->id.device_id))
3672                 bp->flags |= BNXT_FLAG_VF;
3673
3674         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
3675             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
3676             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
3677             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF)
3678                 bp->flags |= BNXT_FLAG_THOR_CHIP;
3679
3680         rc = bnxt_init_board(eth_dev);
3681         if (rc) {
3682                 PMD_DRV_LOG(ERR,
3683                         "Board initialization failed rc: %x\n", rc);
3684                 goto error;
3685         }
3686 skip_init:
3687         eth_dev->dev_ops = &bnxt_dev_ops;
3688         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3689         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3690         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3691                 return 0;
3692
3693         if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3694                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3695                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3696                          pci_dev->addr.bus, pci_dev->addr.devid,
3697                          pci_dev->addr.function, "rx_port_stats");
3698                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3699                 mz = rte_memzone_lookup(mz_name);
3700                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3701                                         sizeof(struct rx_port_stats) +
3702                                         sizeof(struct rx_port_stats_ext) +
3703                                         512);
3704                 if (!mz) {
3705                         mz = rte_memzone_reserve(mz_name, total_alloc_len,
3706                                         SOCKET_ID_ANY,
3707                                         RTE_MEMZONE_2MB |
3708                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3709                                         RTE_MEMZONE_IOVA_CONTIG);
3710                         if (mz == NULL)
3711                                 return -ENOMEM;
3712                 }
3713                 memset(mz->addr, 0, mz->len);
3714                 mz_phys_addr = mz->iova;
3715                 if ((unsigned long)mz->addr == mz_phys_addr) {
3716                         PMD_DRV_LOG(INFO,
3717                                 "Memzone physical address same as virtual using rte_mem_virt2iova()\n");
3718                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3719                         if (mz_phys_addr == 0) {
3720                                 PMD_DRV_LOG(ERR,
3721                                 "unable to map address to physical memory\n");
3722                                 return -ENOMEM;
3723                         }
3724                 }
3725
3726                 bp->rx_mem_zone = (const void *)mz;
3727                 bp->hw_rx_port_stats = mz->addr;
3728                 bp->hw_rx_port_stats_map = mz_phys_addr;
3729
3730                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3731                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3732                          pci_dev->addr.bus, pci_dev->addr.devid,
3733                          pci_dev->addr.function, "tx_port_stats");
3734                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3735                 mz = rte_memzone_lookup(mz_name);
3736                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3737                                         sizeof(struct tx_port_stats) +
3738                                         sizeof(struct tx_port_stats_ext) +
3739                                         512);
3740                 if (!mz) {
3741                         mz = rte_memzone_reserve(mz_name,
3742                                         total_alloc_len,
3743                                         SOCKET_ID_ANY,
3744                                         RTE_MEMZONE_2MB |
3745                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3746                                         RTE_MEMZONE_IOVA_CONTIG);
3747                         if (mz == NULL)
3748                                 return -ENOMEM;
3749                 }
3750                 memset(mz->addr, 0, mz->len);
3751                 mz_phys_addr = mz->iova;
3752                 if ((unsigned long)mz->addr == mz_phys_addr) {
3753                         PMD_DRV_LOG(WARNING,
3754                                 "Memzone physical address same as virtual.\n");
3755                         PMD_DRV_LOG(WARNING,
3756                                 "Using rte_mem_virt2iova()\n");
3757                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3758                         if (mz_phys_addr == 0) {
3759                                 PMD_DRV_LOG(ERR,
3760                                 "unable to map address to physical memory\n");
3761                                 return -ENOMEM;
3762                         }
3763                 }
3764
3765                 bp->tx_mem_zone = (const void *)mz;
3766                 bp->hw_tx_port_stats = mz->addr;
3767                 bp->hw_tx_port_stats_map = mz_phys_addr;
3768
3769                 bp->flags |= BNXT_FLAG_PORT_STATS;
3770
3771                 /* Display extended statistics if FW supports it */
3772                 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3773                     bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0)
3774                         goto skip_ext_stats;
3775
3776                 bp->hw_rx_port_stats_ext = (void *)
3777                         (bp->hw_rx_port_stats + sizeof(struct rx_port_stats));
3778                 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3779                         sizeof(struct rx_port_stats);
3780                 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3781
3782
3783                 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2) {
3784                         bp->hw_tx_port_stats_ext = (void *)
3785                         (bp->hw_tx_port_stats + sizeof(struct tx_port_stats));
3786                         bp->hw_tx_port_stats_ext_map =
3787                                 bp->hw_tx_port_stats_map +
3788                                 sizeof(struct tx_port_stats);
3789                         bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3790                 }
3791         }
3792
3793 skip_ext_stats:
3794         rc = bnxt_alloc_hwrm_resources(bp);
3795         if (rc) {
3796                 PMD_DRV_LOG(ERR,
3797                         "hwrm resource allocation failure rc: %x\n", rc);
3798                 goto error_free;
3799         }
3800         rc = bnxt_hwrm_ver_get(bp);
3801         if (rc)
3802                 goto error_free;
3803
3804         rc = bnxt_hwrm_func_reset(bp);
3805         if (rc) {
3806                 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3807                 rc = -EIO;
3808                 goto error_free;
3809         }
3810
3811         rc = bnxt_hwrm_queue_qportcfg(bp);
3812         if (rc) {
3813                 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3814                 goto error_free;
3815         }
3816         /* Get the MAX capabilities for this function */
3817         rc = bnxt_hwrm_func_qcaps(bp);
3818         if (rc) {
3819                 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3820                 goto error_free;
3821         }
3822         if (bp->max_tx_rings == 0) {
3823                 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3824                 rc = -EBUSY;
3825                 goto error_free;
3826         }
3827         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3828                                         RTE_ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3829         if (eth_dev->data->mac_addrs == NULL) {
3830                 PMD_DRV_LOG(ERR,
3831                         "Failed to alloc %u bytes needed to store MAC addr tbl",
3832                         RTE_ETHER_ADDR_LEN * bp->max_l2_ctx);
3833                 rc = -ENOMEM;
3834                 goto error_free;
3835         }
3836
3837         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
3838                 PMD_DRV_LOG(ERR,
3839                             "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3840                             bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3841                             bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3842                             bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3843                 rc = -EINVAL;
3844                 goto error_free;
3845         }
3846         /* Copy the permanent MAC from the qcap response address now. */
3847         memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3848         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
3849
3850         /* THOR does not support ring groups.
3851          * But we will use the array to save RSS context IDs.
3852          */
3853         if (BNXT_CHIP_THOR(bp)) {
3854                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
3855         } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3856                 /* 1 ring is for default completion ring */
3857                 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3858                 rc = -ENOSPC;
3859                 goto error_free;
3860         }
3861
3862         bp->grp_info = rte_zmalloc("bnxt_grp_info",
3863                                 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3864         if (!bp->grp_info) {
3865                 PMD_DRV_LOG(ERR,
3866                         "Failed to alloc %zu bytes to store group info table\n",
3867                         sizeof(*bp->grp_info) * bp->max_ring_grps);
3868                 rc = -ENOMEM;
3869                 goto error_free;
3870         }
3871
3872         /* Forward all requests if firmware is new enough */
3873         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3874             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3875             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3876                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3877         } else {
3878                 PMD_DRV_LOG(WARNING,
3879                         "Firmware too old for VF mailbox functionality\n");
3880                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3881         }
3882
3883         /*
3884          * The following are used for driver cleanup.  If we disallow these,
3885          * VF drivers can't clean up cleanly.
3886          */
3887         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3888         ALLOW_FUNC(HWRM_VNIC_FREE);
3889         ALLOW_FUNC(HWRM_RING_FREE);
3890         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3891         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3892         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3893         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3894         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3895         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3896         rc = bnxt_hwrm_func_driver_register(bp);
3897         if (rc) {
3898                 PMD_DRV_LOG(ERR,
3899                         "Failed to register driver");
3900                 rc = -EBUSY;
3901                 goto error_free;
3902         }
3903
3904         PMD_DRV_LOG(INFO,
3905                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3906                 pci_dev->mem_resource[0].phys_addr,
3907                 pci_dev->mem_resource[0].addr);
3908
3909         rc = bnxt_hwrm_func_qcfg(bp);
3910         if (rc) {
3911                 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3912                 goto error_free;
3913         }
3914
3915         if (BNXT_PF(bp)) {
3916                 //if (bp->pf.active_vfs) {
3917                         // TODO: Deallocate VF resources?
3918                 //}
3919                 if (bp->pdev->max_vfs) {
3920                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3921                         if (rc) {
3922                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3923                                 goto error_free;
3924                         }
3925                 } else {
3926                         rc = bnxt_hwrm_allocate_pf_only(bp);
3927                         if (rc) {
3928                                 PMD_DRV_LOG(ERR,
3929                                         "Failed to allocate PF resources\n");
3930                                 goto error_free;
3931                         }
3932                 }
3933         }
3934
3935         bnxt_hwrm_port_led_qcaps(bp);
3936
3937         rc = bnxt_setup_int(bp);
3938         if (rc)
3939                 goto error_free;
3940
3941         rc = bnxt_alloc_mem(bp);
3942         if (rc)
3943                 goto error_free_int;
3944
3945         rc = bnxt_request_int(bp);
3946         if (rc)
3947                 goto error_free_int;
3948
3949         bnxt_enable_int(bp);
3950         bnxt_init_nic(bp);
3951
3952         return 0;
3953
3954 error_free_int:
3955         bnxt_disable_int(bp);
3956         bnxt_hwrm_func_buf_unrgtr(bp);
3957         bnxt_free_int(bp);
3958         bnxt_free_mem(bp);
3959 error_free:
3960         bnxt_dev_uninit(eth_dev);
3961 error:
3962         return rc;
3963 }
3964
3965 static int
3966 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3967 {
3968         struct bnxt *bp = eth_dev->data->dev_private;
3969         int rc;
3970
3971         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3972                 return -EPERM;
3973
3974         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
3975         bnxt_disable_int(bp);
3976         bnxt_free_int(bp);
3977         bnxt_free_mem(bp);
3978         if (bp->grp_info != NULL) {
3979                 rte_free(bp->grp_info);
3980                 bp->grp_info = NULL;
3981         }
3982         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3983         bnxt_free_hwrm_resources(bp);
3984
3985         if (bp->tx_mem_zone) {
3986                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3987                 bp->tx_mem_zone = NULL;
3988         }
3989
3990         if (bp->rx_mem_zone) {
3991                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3992                 bp->rx_mem_zone = NULL;
3993         }
3994
3995         if (bp->dev_stopped == 0)
3996                 bnxt_dev_close_op(eth_dev);
3997         if (bp->pf.vf_info)
3998                 rte_free(bp->pf.vf_info);
3999         bnxt_free_ctx_mem(bp);
4000         eth_dev->dev_ops = NULL;
4001         eth_dev->rx_pkt_burst = NULL;
4002         eth_dev->tx_pkt_burst = NULL;
4003
4004         return rc;
4005 }
4006
4007 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4008         struct rte_pci_device *pci_dev)
4009 {
4010         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4011                 bnxt_dev_init);
4012 }
4013
4014 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4015 {
4016         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4017                 return rte_eth_dev_pci_generic_remove(pci_dev,
4018                                 bnxt_dev_uninit);
4019         else
4020                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4021 }
4022
4023 static struct rte_pci_driver bnxt_rte_pmd = {
4024         .id_table = bnxt_pci_id_map,
4025         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
4026                 RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_IOVA_AS_VA,
4027         .probe = bnxt_pci_probe,
4028         .remove = bnxt_pci_remove,
4029 };
4030
4031 static bool
4032 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4033 {
4034         if (strcmp(dev->device->driver->name, drv->driver.name))
4035                 return false;
4036
4037         return true;
4038 }
4039
4040 bool is_bnxt_supported(struct rte_eth_dev *dev)
4041 {
4042         return is_device_supported(dev, &bnxt_rte_pmd);
4043 }
4044
4045 RTE_INIT(bnxt_init_log)
4046 {
4047         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4048         if (bnxt_logtype_driver >= 0)
4049                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4050 }
4051
4052 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4053 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4054 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");