drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 /*
  37  * The set of PCI devices this driver supports
  38  */
  39 static const struct rte_pci_id bnxt_pci_id_map[] = {
  40         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  41                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  93         { .vendor_id = 0, /* sentinel */ },
  94 };
  95
  96 #define BNXT_ETH_RSS_SUPPORT (  \
  97         ETH_RSS_IPV4 |          \
  98         ETH_RSS_NONFRAG_IPV4_TCP |      \
  99         ETH_RSS_NONFRAG_IPV4_UDP |      \
 100         ETH_RSS_IPV6 |          \
 101         ETH_RSS_NONFRAG_IPV6_TCP |      \
 102         ETH_RSS_NONFRAG_IPV6_UDP)
 103
 104 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 105                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 106                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 108                                      DEV_TX_OFFLOAD_TCP_TSO | \
 109                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 110                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 114                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 115                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 116
 117 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 118                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 119                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 120                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 122                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 123                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 124                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 125                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 126                                      DEV_RX_OFFLOAD_TCP_LRO | \
 127                                      DEV_RX_OFFLOAD_SCATTER | \
 128                                      DEV_RX_OFFLOAD_RSS_HASH)
 129
 130 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
 131 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 132 static const char *const bnxt_dev_args[] = {
 133         BNXT_DEVARG_TRUFLOW,
 134         BNXT_DEVARG_FLOW_XSTAT,
 135         NULL
 136 };
 137
 138 /*
 139  * truflow == false to disable the feature
 140  * truflow == true to enable the feature
 141  */
 142 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 143
 144 /*
 145  * flow_xstat == false to disable the feature
 146  * flow_xstat == true to enable the feature
 147  */
 148 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 149
 150 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 151 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 152 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 153 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 154 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 155 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 156 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 157 static void bnxt_dev_recover(void *arg);
 158 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 159
 160 int is_bnxt_in_error(struct bnxt *bp)
 161 {
 162         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 163                 return -EIO;
 164         if (bp->flags & BNXT_FLAG_FW_RESET)
 165                 return -EBUSY;
 166
 167         return 0;
 168 }
 169
 170 /***********************/
 171
 172 /*
 173  * High level utility functions
 174  */
 175
 176 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 177 {
 178         if (!BNXT_CHIP_THOR(bp))
 179                 return 1;
 180
 181         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 182                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 183                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 184 }
 185
 186 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 187 {
 188         if (!BNXT_CHIP_THOR(bp))
 189                 return HW_HASH_INDEX_SIZE;
 190
 191         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 192 }
 193
 194 static void bnxt_free_leds_info(struct bnxt *bp)
 195 {
 196         rte_free(bp->leds);
 197         bp->leds = NULL;
 198 }
 199
 200 static void bnxt_free_cos_queues(struct bnxt *bp)
 201 {
 202         rte_free(bp->rx_cos_queue);
 203         rte_free(bp->tx_cos_queue);
 204 }
 205
 206 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 207 {
 208         bnxt_free_filter_mem(bp);
 209         bnxt_free_vnic_attributes(bp);
 210         bnxt_free_vnic_mem(bp);
 211
 212         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 213          * If the number of rings change across fw update,
 214          * we don't have much choice except to warn the user.
 215          */
 216         if (!reconfig) {
 217                 bnxt_free_stats(bp);
 218                 bnxt_free_tx_rings(bp);
 219                 bnxt_free_rx_rings(bp);
 220         }
 221         bnxt_free_async_cp_ring(bp);
 222         bnxt_free_rxtx_nq_ring(bp);
 223
 224         rte_free(bp->grp_info);
 225         bp->grp_info = NULL;
 226 }
 227
 228 static int bnxt_alloc_leds_info(struct bnxt *bp)
 229 {
 230         bp->leds = rte_zmalloc("bnxt_leds",
 231                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 232                                0);
 233         if (bp->leds == NULL)
 234                 return -ENOMEM;
 235
 236         return 0;
 237 }
 238
 239 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 240 {
 241         bp->rx_cos_queue =
 242                 rte_zmalloc("bnxt_rx_cosq",
 243                             BNXT_COS_QUEUE_COUNT *
 244                             sizeof(struct bnxt_cos_queue_info),
 245                             0);
 246         if (bp->rx_cos_queue == NULL)
 247                 return -ENOMEM;
 248
 249         bp->tx_cos_queue =
 250                 rte_zmalloc("bnxt_tx_cosq",
 251                             BNXT_COS_QUEUE_COUNT *
 252                             sizeof(struct bnxt_cos_queue_info),
 253                             0);
 254         if (bp->tx_cos_queue == NULL)
 255                 return -ENOMEM;
 256
 257         return 0;
 258 }
 259
 260 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 261 {
 262         int rc;
 263
 264         rc = bnxt_alloc_ring_grps(bp);
 265         if (rc)
 266                 goto alloc_mem_err;
 267
 268         rc = bnxt_alloc_async_ring_struct(bp);
 269         if (rc)
 270                 goto alloc_mem_err;
 271
 272         rc = bnxt_alloc_vnic_mem(bp);
 273         if (rc)
 274                 goto alloc_mem_err;
 275
 276         rc = bnxt_alloc_vnic_attributes(bp);
 277         if (rc)
 278                 goto alloc_mem_err;
 279
 280         rc = bnxt_alloc_filter_mem(bp);
 281         if (rc)
 282                 goto alloc_mem_err;
 283
 284         rc = bnxt_alloc_async_cp_ring(bp);
 285         if (rc)
 286                 goto alloc_mem_err;
 287
 288         rc = bnxt_alloc_rxtx_nq_ring(bp);
 289         if (rc)
 290                 goto alloc_mem_err;
 291
 292         return 0;
 293
 294 alloc_mem_err:
 295         bnxt_free_mem(bp, reconfig);
 296         return rc;
 297 }
 298
 299 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 300 {
 301         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 302         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 303         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 304         struct bnxt_rx_queue *rxq;
 305         unsigned int j;
 306         int rc;
 307
 308         rc = bnxt_vnic_grp_alloc(bp, vnic);
 309         if (rc)
 310                 goto err_out;
 311
 312         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 313                     vnic_id, vnic, vnic->fw_grp_ids);
 314
 315         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 316         if (rc)
 317                 goto err_out;
 318
 319         /* Alloc RSS context only if RSS mode is enabled */
 320         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 321                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 322
 323                 rc = 0;
 324                 for (j = 0; j < nr_ctxs; j++) {
 325                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 326                         if (rc)
 327                                 break;
 328                 }
 329                 if (rc) {
 330                         PMD_DRV_LOG(ERR,
 331                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 332                                     vnic_id, j, rc);
 333                         goto err_out;
 334                 }
 335                 vnic->num_lb_ctxts = nr_ctxs;
 336         }
 337
 338         /*
 339          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 340          * setting is not available at this time, it will not be
 341          * configured correctly in the CFA.
 342          */
 343         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 344                 vnic->vlan_strip = true;
 345         else
 346                 vnic->vlan_strip = false;
 347
 348         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 349         if (rc)
 350                 goto err_out;
 351
 352         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 353         if (rc)
 354                 goto err_out;
 355
 356         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 357                 rxq = bp->eth_dev->data->rx_queues[j];
 358
 359                 PMD_DRV_LOG(DEBUG,
 360                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 361                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 362
 363                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 364                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 365                 else
 366                         vnic->rx_queue_cnt++;
 367         }
 368
 369         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 370
 371         rc = bnxt_vnic_rss_configure(bp, vnic);
 372         if (rc)
 373                 goto err_out;
 374
 375         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 376
 377         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 378                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 379         else
 380                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 381
 382         return 0;
 383 err_out:
 384         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 385                     vnic_id, rc);
 386         return rc;
 387 }
 388
 389 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 390 {
 391         int rc = 0;
 392
 393         rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_in_tbl.dma,
 394                                 &bp->rx_fc_in_tbl.ctx_id);
 395         if (rc)
 396                 return rc;
 397
 398         PMD_DRV_LOG(DEBUG,
 399                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 400                     " rx_fc_in_tbl.ctx_id = %d\n",
 401                     bp->rx_fc_in_tbl.va,
 402                     (void *)((uintptr_t)bp->rx_fc_in_tbl.dma),
 403                     bp->rx_fc_in_tbl.ctx_id);
 404
 405         rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_out_tbl.dma,
 406                                 &bp->rx_fc_out_tbl.ctx_id);
 407         if (rc)
 408                 return rc;
 409
 410         PMD_DRV_LOG(DEBUG,
 411                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 412                     " rx_fc_out_tbl.ctx_id = %d\n",
 413                     bp->rx_fc_out_tbl.va,
 414                     (void *)((uintptr_t)bp->rx_fc_out_tbl.dma),
 415                     bp->rx_fc_out_tbl.ctx_id);
 416
 417         rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_in_tbl.dma,
 418                                 &bp->tx_fc_in_tbl.ctx_id);
 419         if (rc)
 420                 return rc;
 421
 422         PMD_DRV_LOG(DEBUG,
 423                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 424                     " tx_fc_in_tbl.ctx_id = %d\n",
 425                     bp->tx_fc_in_tbl.va,
 426                     (void *)((uintptr_t)bp->tx_fc_in_tbl.dma),
 427                     bp->tx_fc_in_tbl.ctx_id);
 428
 429         rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_out_tbl.dma,
 430                                 &bp->tx_fc_out_tbl.ctx_id);
 431         if (rc)
 432                 return rc;
 433
 434         PMD_DRV_LOG(DEBUG,
 435                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 436                     " tx_fc_out_tbl.ctx_id = %d\n",
 437                     bp->tx_fc_out_tbl.va,
 438                     (void *)((uintptr_t)bp->tx_fc_out_tbl.dma),
 439                     bp->tx_fc_out_tbl.ctx_id);
 440
 441         memset(bp->rx_fc_out_tbl.va, 0, bp->rx_fc_out_tbl.size);
 442         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 443                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 444                                        bp->rx_fc_out_tbl.ctx_id,
 445                                        bp->max_fc,
 446                                        true);
 447         if (rc)
 448                 return rc;
 449
 450         memset(bp->tx_fc_out_tbl.va, 0, bp->tx_fc_out_tbl.size);
 451         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 452                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 453                                        bp->tx_fc_out_tbl.ctx_id,
 454                                        bp->max_fc,
 455                                        true);
 456
 457         return rc;
 458 }
 459
 460 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 461                                   struct bnxt_ctx_mem_buf_info *ctx)
 462 {
 463         if (!ctx)
 464                 return -EINVAL;
 465
 466         ctx->va = rte_zmalloc(type, size, 0);
 467         if (ctx->va == NULL)
 468                 return -ENOMEM;
 469         rte_mem_lock_page(ctx->va);
 470         ctx->size = size;
 471         ctx->dma = rte_mem_virt2iova(ctx->va);
 472         if (ctx->dma == RTE_BAD_IOVA)
 473                 return -ENOMEM;
 474
 475         return 0;
 476 }
 477
 478 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 479 {
 480         struct rte_pci_device *pdev = bp->pdev;
 481         char type[RTE_MEMZONE_NAMESIZE];
 482         uint16_t max_fc;
 483         int rc = 0;
 484
 485         max_fc = bp->max_fc;
 486
 487         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 488                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 489         /* 4 bytes for each counter-id */
 490         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->rx_fc_in_tbl);
 491         if (rc)
 492                 return rc;
 493
 494         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 495                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 496         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 497         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->rx_fc_out_tbl);
 498         if (rc)
 499                 return rc;
 500
 501         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 502                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 503         /* 4 bytes for each counter-id */
 504         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->tx_fc_in_tbl);
 505         if (rc)
 506                 return rc;
 507
 508         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 509                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 510         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 511         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->tx_fc_out_tbl);
 512         if (rc)
 513                 return rc;
 514
 515         rc = bnxt_register_fc_ctx_mem(bp);
 516
 517         return rc;
 518 }
 519
 520 static int bnxt_init_ctx_mem(struct bnxt *bp)
 521 {
 522         int rc = 0;
 523
 524         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 525             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
 526                 return 0;
 527
 528         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->max_fc);
 529         if (rc)
 530                 return rc;
 531
 532         rc = bnxt_init_fc_ctx_mem(bp);
 533
 534         return rc;
 535 }
 536
 537 static int bnxt_init_chip(struct bnxt *bp)
 538 {
 539         struct rte_eth_link new;
 540         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 541         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 542         uint32_t intr_vector = 0;
 543         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 544         uint32_t vec = BNXT_MISC_VEC_ID;
 545         unsigned int i, j;
 546         int rc;
 547
 548         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 549                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 550                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 551                 bp->flags |= BNXT_FLAG_JUMBO;
 552         } else {
 553                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 554                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 555                 bp->flags &= ~BNXT_FLAG_JUMBO;
 556         }
 557
 558         /* THOR does not support ring groups.
 559          * But we will use the array to save RSS context IDs.
 560          */
 561         if (BNXT_CHIP_THOR(bp))
 562                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 563
 564         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 565         if (rc) {
 566                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 567                 goto err_out;
 568         }
 569
 570         rc = bnxt_alloc_hwrm_rings(bp);
 571         if (rc) {
 572                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 573                 goto err_out;
 574         }
 575
 576         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 577         if (rc) {
 578                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 579                 goto err_out;
 580         }
 581
 582         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 583                 goto skip_cosq_cfg;
 584
 585         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 586                 if (bp->rx_cos_queue[i].id != 0xff) {
 587                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 588
 589                         if (!vnic) {
 590                                 PMD_DRV_LOG(ERR,
 591                                             "Num pools more than FW profile\n");
 592                                 rc = -EINVAL;
 593                                 goto err_out;
 594                         }
 595                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 596                         bp->rx_cosq_cnt++;
 597                 }
 598         }
 599
 600 skip_cosq_cfg:
 601         rc = bnxt_mq_rx_configure(bp);
 602         if (rc) {
 603                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 604                 goto err_out;
 605         }
 606
 607         /* VNIC configuration */
 608         for (i = 0; i < bp->nr_vnics; i++) {
 609                 rc = bnxt_setup_one_vnic(bp, i);
 610                 if (rc)
 611                         goto err_out;
 612         }
 613
 614         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 615         if (rc) {
 616                 PMD_DRV_LOG(ERR,
 617                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 618                 goto err_out;
 619         }
 620
 621         /* check and configure queue intr-vector mapping */
 622         if ((rte_intr_cap_multiple(intr_handle) ||
 623              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 624             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 625                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 626                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 627                 if (intr_vector > bp->rx_cp_nr_rings) {
 628                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 629                                         bp->rx_cp_nr_rings);
 630                         return -ENOTSUP;
 631                 }
 632                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 633                 if (rc)
 634                         return rc;
 635         }
 636
 637         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 638                 intr_handle->intr_vec =
 639                         rte_zmalloc("intr_vec",
 640                                     bp->eth_dev->data->nb_rx_queues *
 641                                     sizeof(int), 0);
 642                 if (intr_handle->intr_vec == NULL) {
 643                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 644                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 645                         rc = -ENOMEM;
 646                         goto err_disable;
 647                 }
 648                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 649                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 650                          intr_handle->intr_vec, intr_handle->nb_efd,
 651                         intr_handle->max_intr);
 652                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 653                      queue_id++) {
 654                         intr_handle->intr_vec[queue_id] =
 655                                                         vec + BNXT_RX_VEC_START;
 656                         if (vec < base + intr_handle->nb_efd - 1)
 657                                 vec++;
 658                 }
 659         }
 660
 661         /* enable uio/vfio intr/eventfd mapping */
 662         rc = rte_intr_enable(intr_handle);
 663 #ifndef RTE_EXEC_ENV_FREEBSD
 664         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 665         if (rc)
 666                 goto err_free;
 667 #endif
 668
 669         rc = bnxt_get_hwrm_link_config(bp, &new);
 670         if (rc) {
 671                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 672                 goto err_free;
 673         }
 674
 675         if (!bp->link_info.link_up) {
 676                 rc = bnxt_set_hwrm_link_config(bp, true);
 677                 if (rc) {
 678                         PMD_DRV_LOG(ERR,
 679                                 "HWRM link config failure rc: %x\n", rc);
 680                         goto err_free;
 681                 }
 682         }
 683         bnxt_print_link_info(bp->eth_dev);
 684
 685         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 686         if (!bp->mark_table)
 687                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 688
 689         return 0;
 690
 691 err_free:
 692         rte_free(intr_handle->intr_vec);
 693 err_disable:
 694         rte_intr_efd_disable(intr_handle);
 695 err_out:
 696         /* Some of the error status returned by FW may not be from errno.h */
 697         if (rc > 0)
 698                 rc = -EIO;
 699
 700         return rc;
 701 }
 702
 703 static int bnxt_shutdown_nic(struct bnxt *bp)
 704 {
 705         bnxt_free_all_hwrm_resources(bp);
 706         bnxt_free_all_filters(bp);
 707         bnxt_free_all_vnics(bp);
 708         return 0;
 709 }
 710
 711 /*
 712  * Device configuration and status function
 713  */
 714
 715 static uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 716 {
 717         uint32_t link_speed = bp->link_info.support_speeds;
 718         uint32_t speed_capa = 0;
 719
 720         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 721                 speed_capa |= ETH_LINK_SPEED_100M;
 722         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 723                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 724         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 725                 speed_capa |= ETH_LINK_SPEED_1G;
 726         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 727                 speed_capa |= ETH_LINK_SPEED_2_5G;
 728         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 729                 speed_capa |= ETH_LINK_SPEED_10G;
 730         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 731                 speed_capa |= ETH_LINK_SPEED_20G;
 732         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 733                 speed_capa |= ETH_LINK_SPEED_25G;
 734         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 735                 speed_capa |= ETH_LINK_SPEED_40G;
 736         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 737                 speed_capa |= ETH_LINK_SPEED_50G;
 738         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 739                 speed_capa |= ETH_LINK_SPEED_100G;
 740         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
 741                 speed_capa |= ETH_LINK_SPEED_200G;
 742
 743         if (bp->link_info.auto_mode == HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 744                 speed_capa |= ETH_LINK_SPEED_FIXED;
 745         else
 746                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 747
 748         return speed_capa;
 749 }
 750
 751 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 752                                 struct rte_eth_dev_info *dev_info)
 753 {
 754         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 755         struct bnxt *bp = eth_dev->data->dev_private;
 756         uint16_t max_vnics, i, j, vpool, vrxq;
 757         unsigned int max_rx_rings;
 758         int rc;
 759
 760         rc = is_bnxt_in_error(bp);
 761         if (rc)
 762                 return rc;
 763
 764         /* MAC Specifics */
 765         dev_info->max_mac_addrs = bp->max_l2_ctx;
 766         dev_info->max_hash_mac_addrs = 0;
 767
 768         /* PF/VF specifics */
 769         if (BNXT_PF(bp))
 770                 dev_info->max_vfs = pdev->max_vfs;
 771
 772         max_rx_rings = BNXT_MAX_RINGS(bp);
 773         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 774         dev_info->max_rx_queues = max_rx_rings;
 775         dev_info->max_tx_queues = max_rx_rings;
 776         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 777         dev_info->hash_key_size = 40;
 778         max_vnics = bp->max_vnics;
 779
 780         /* MTU specifics */
 781         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 782         dev_info->max_mtu = BNXT_MAX_MTU;
 783
 784         /* Fast path specifics */
 785         dev_info->min_rx_bufsize = 1;
 786         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 787
 788         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 789         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 790                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 791         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 792         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 793
 794         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 795
 796         /* *INDENT-OFF* */
 797         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 798                 .rx_thresh = {
 799                         .pthresh = 8,
 800                         .hthresh = 8,
 801                         .wthresh = 0,
 802                 },
 803                 .rx_free_thresh = 32,
 804                 /* If no descriptors available, pkts are dropped by default */
 805                 .rx_drop_en = 1,
 806         };
 807
 808         dev_info->default_txconf = (struct rte_eth_txconf) {
 809                 .tx_thresh = {
 810                         .pthresh = 32,
 811                         .hthresh = 0,
 812                         .wthresh = 0,
 813                 },
 814                 .tx_free_thresh = 32,
 815                 .tx_rs_thresh = 32,
 816         };
 817         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 818
 819         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 820         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 821         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 822         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 823         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 824
 825         /* *INDENT-ON* */
 826
 827         /*
 828          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 829          *       need further investigation.
 830          */
 831
 832         /* VMDq resources */
 833         vpool = 64; /* ETH_64_POOLS */
 834         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 835         for (i = 0; i < 4; vpool >>= 1, i++) {
 836                 if (max_vnics > vpool) {
 837                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 838                                 if (dev_info->max_rx_queues > vrxq) {
 839                                         if (vpool > vrxq)
 840                                                 vpool = vrxq;
 841                                         goto found;
 842                                 }
 843                         }
 844                         /* Not enough resources to support VMDq */
 845                         break;
 846                 }
 847         }
 848         /* Not enough resources to support VMDq */
 849         vpool = 0;
 850         vrxq = 0;
 851 found:
 852         dev_info->max_vmdq_pools = vpool;
 853         dev_info->vmdq_queue_num = vrxq;
 854
 855         dev_info->vmdq_pool_base = 0;
 856         dev_info->vmdq_queue_base = 0;
 857
 858         return 0;
 859 }
 860
 861 /* Configure the device based on the configuration provided */
 862 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 863 {
 864         struct bnxt *bp = eth_dev->data->dev_private;
 865         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 866         int rc;
 867
 868         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 869         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 870         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 871         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 872
 873         rc = is_bnxt_in_error(bp);
 874         if (rc)
 875                 return rc;
 876
 877         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 878                 rc = bnxt_hwrm_check_vf_rings(bp);
 879                 if (rc) {
 880                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 881                         return -ENOSPC;
 882                 }
 883
 884                 /* If a resource has already been allocated - in this case
 885                  * it is the async completion ring, free it. Reallocate it after
 886                  * resource reservation. This will ensure the resource counts
 887                  * are calculated correctly.
 888                  */
 889
 890                 pthread_mutex_lock(&bp->def_cp_lock);
 891
 892                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 893                         bnxt_disable_int(bp);
 894                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 895                 }
 896
 897                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 898                 if (rc) {
 899                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 900                         pthread_mutex_unlock(&bp->def_cp_lock);
 901                         return -ENOSPC;
 902                 }
 903
 904                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 905                         rc = bnxt_alloc_async_cp_ring(bp);
 906                         if (rc) {
 907                                 pthread_mutex_unlock(&bp->def_cp_lock);
 908                                 return rc;
 909                         }
 910                         bnxt_enable_int(bp);
 911                 }
 912
 913                 pthread_mutex_unlock(&bp->def_cp_lock);
 914         } else {
 915                 /* legacy driver needs to get updated values */
 916                 rc = bnxt_hwrm_func_qcaps(bp);
 917                 if (rc) {
 918                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 919                         return rc;
 920                 }
 921         }
 922
 923         /* Inherit new configurations */
 924         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 925             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 926             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 927                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 928             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 929             bp->max_stat_ctx)
 930                 goto resource_error;
 931
 932         if (BNXT_HAS_RING_GRPS(bp) &&
 933             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 934                 goto resource_error;
 935
 936         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 937             bp->max_vnics < eth_dev->data->nb_rx_queues)
 938                 goto resource_error;
 939
 940         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 941         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 942
 943         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 944                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 945         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
 946
 947         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 948                 eth_dev->data->mtu =
 949                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 950                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 951                         BNXT_NUM_VLANS;
 952                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 953         }
 954         return 0;
 955
 956 resource_error:
 957         PMD_DRV_LOG(ERR,
 958                     "Insufficient resources to support requested config\n");
 959         PMD_DRV_LOG(ERR,
 960                     "Num Queues Requested: Tx %d, Rx %d\n",
 961                     eth_dev->data->nb_tx_queues,
 962                     eth_dev->data->nb_rx_queues);
 963         PMD_DRV_LOG(ERR,
 964                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 965                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 966                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 967         return -ENOSPC;
 968 }
 969
 970 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 971 {
 972         struct rte_eth_link *link = &eth_dev->data->dev_link;
 973
 974         if (link->link_status)
 975                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 976                         eth_dev->data->port_id,
 977                         (uint32_t)link->link_speed,
 978                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 979                         ("full-duplex") : ("half-duplex\n"));
 980         else
 981                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 982                         eth_dev->data->port_id);
 983 }
 984
 985 /*
 986  * Determine whether the current configuration requires support for scattered
 987  * receive; return 1 if scattered receive is required and 0 if not.
 988  */
 989 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 990 {
 991         uint16_t buf_size;
 992         int i;
 993
 994         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 995                 return 1;
 996
 997         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 998                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 999
1000                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1001                                       RTE_PKTMBUF_HEADROOM);
1002                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1003                         return 1;
1004         }
1005         return 0;
1006 }
1007
1008 static eth_rx_burst_t
1009 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1010 {
1011         struct bnxt *bp = eth_dev->data->dev_private;
1012
1013 #ifdef RTE_ARCH_X86
1014 #ifndef RTE_LIBRTE_IEEE1588
1015         /*
1016          * Vector mode receive can be enabled only if scatter rx is not
1017          * in use and rx offloads are limited to VLAN stripping and
1018          * CRC stripping.
1019          */
1020         if (!eth_dev->data->scattered_rx &&
1021             !(eth_dev->data->dev_conf.rxmode.offloads &
1022               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1023                 DEV_RX_OFFLOAD_KEEP_CRC |
1024                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1025                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1026                 DEV_RX_OFFLOAD_UDP_CKSUM |
1027                 DEV_RX_OFFLOAD_TCP_CKSUM |
1028                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1029                 DEV_RX_OFFLOAD_RSS_HASH |
1030                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1031             !bp->truflow) {
1032                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1033                             eth_dev->data->port_id);
1034                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1035                 return bnxt_recv_pkts_vec;
1036         }
1037         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1038                     eth_dev->data->port_id);
1039         PMD_DRV_LOG(INFO,
1040                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1041                     eth_dev->data->port_id,
1042                     eth_dev->data->scattered_rx,
1043                     eth_dev->data->dev_conf.rxmode.offloads);
1044 #endif
1045 #endif
1046         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1047         return bnxt_recv_pkts;
1048 }
1049
1050 static eth_tx_burst_t
1051 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1052 {
1053 #ifdef RTE_ARCH_X86
1054 #ifndef RTE_LIBRTE_IEEE1588
1055         /*
1056          * Vector mode transmit can be enabled only if not using scatter rx
1057          * or tx offloads.
1058          */
1059         if (!eth_dev->data->scattered_rx &&
1060             !eth_dev->data->dev_conf.txmode.offloads) {
1061                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1062                             eth_dev->data->port_id);
1063                 return bnxt_xmit_pkts_vec;
1064         }
1065         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1066                     eth_dev->data->port_id);
1067         PMD_DRV_LOG(INFO,
1068                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1069                     eth_dev->data->port_id,
1070                     eth_dev->data->scattered_rx,
1071                     eth_dev->data->dev_conf.txmode.offloads);
1072 #endif
1073 #endif
1074         return bnxt_xmit_pkts;
1075 }
1076
1077 static int bnxt_handle_if_change_status(struct bnxt *bp)
1078 {
1079         int rc;
1080
1081         /* Since fw has undergone a reset and lost all contexts,
1082          * set fatal flag to not issue hwrm during cleanup
1083          */
1084         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1085         bnxt_uninit_resources(bp, true);
1086
1087         /* clear fatal flag so that re-init happens */
1088         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1089         rc = bnxt_init_resources(bp, true);
1090
1091         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1092
1093         return rc;
1094 }
1095
1096 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1097 {
1098         struct bnxt *bp = eth_dev->data->dev_private;
1099         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1100         int vlan_mask = 0;
1101         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1102
1103         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1104                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1105                 return -EINVAL;
1106         }
1107
1108         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1109                 PMD_DRV_LOG(ERR,
1110                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1111                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1112         }
1113
1114         do {
1115                 rc = bnxt_hwrm_if_change(bp, true);
1116                 if (rc == 0 || rc != -EAGAIN)
1117                         break;
1118
1119                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1120         } while (retry_cnt--);
1121
1122         if (rc)
1123                 return rc;
1124
1125         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1126                 rc = bnxt_handle_if_change_status(bp);
1127                 if (rc)
1128                         return rc;
1129         }
1130
1131         bnxt_enable_int(bp);
1132
1133         rc = bnxt_init_chip(bp);
1134         if (rc)
1135                 goto error;
1136
1137         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1138         eth_dev->data->dev_started = 1;
1139
1140         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1141
1142         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1143                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1144         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1145                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1146         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1147         if (rc)
1148                 goto error;
1149
1150         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1151         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1152
1153         pthread_mutex_lock(&bp->def_cp_lock);
1154         bnxt_schedule_fw_health_check(bp);
1155         pthread_mutex_unlock(&bp->def_cp_lock);
1156
1157         if (bp->truflow)
1158                 bnxt_ulp_init(bp);
1159
1160         return 0;
1161
1162 error:
1163         bnxt_shutdown_nic(bp);
1164         bnxt_free_tx_mbufs(bp);
1165         bnxt_free_rx_mbufs(bp);
1166         bnxt_hwrm_if_change(bp, false);
1167         eth_dev->data->dev_started = 0;
1168         return rc;
1169 }
1170
1171 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1172 {
1173         struct bnxt *bp = eth_dev->data->dev_private;
1174         int rc = 0;
1175
1176         if (!bp->link_info.link_up)
1177                 rc = bnxt_set_hwrm_link_config(bp, true);
1178         if (!rc)
1179                 eth_dev->data->dev_link.link_status = 1;
1180
1181         bnxt_print_link_info(eth_dev);
1182         return rc;
1183 }
1184
1185 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1186 {
1187         struct bnxt *bp = eth_dev->data->dev_private;
1188
1189         eth_dev->data->dev_link.link_status = 0;
1190         bnxt_set_hwrm_link_config(bp, false);
1191         bp->link_info.link_up = 0;
1192
1193         return 0;
1194 }
1195
1196 /* Unload the driver, release resources */
1197 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1198 {
1199         struct bnxt *bp = eth_dev->data->dev_private;
1200         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1201         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1202
1203         if (bp->truflow)
1204                 bnxt_ulp_deinit(bp);
1205
1206         eth_dev->data->dev_started = 0;
1207         /* Prevent crashes when queues are still in use */
1208         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1209         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1210
1211         bnxt_disable_int(bp);
1212
1213         /* disable uio/vfio intr/eventfd mapping */
1214         rte_intr_disable(intr_handle);
1215
1216         bnxt_cancel_fw_health_check(bp);
1217
1218         bnxt_dev_set_link_down_op(eth_dev);
1219
1220         /* Wait for link to be reset and the async notification to process.
1221          * During reset recovery, there is no need to wait and
1222          * VF/NPAR functions do not have privilege to change PHY config.
1223          */
1224         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1225                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1226
1227         /* Clean queue intr-vector mapping */
1228         rte_intr_efd_disable(intr_handle);
1229         if (intr_handle->intr_vec != NULL) {
1230                 rte_free(intr_handle->intr_vec);
1231                 intr_handle->intr_vec = NULL;
1232         }
1233
1234         bnxt_hwrm_port_clr_stats(bp);
1235         bnxt_free_tx_mbufs(bp);
1236         bnxt_free_rx_mbufs(bp);
1237         /* Process any remaining notifications in default completion queue */
1238         bnxt_int_handler(eth_dev);
1239         bnxt_shutdown_nic(bp);
1240         bnxt_hwrm_if_change(bp, false);
1241
1242         rte_free(bp->mark_table);
1243         bp->mark_table = NULL;
1244
1245         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1246         bp->rx_cosq_cnt = 0;
1247 }
1248
1249 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1250 {
1251         struct bnxt *bp = eth_dev->data->dev_private;
1252
1253         /* cancel the recovery handler before remove dev */
1254         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1255         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1256         bnxt_cancel_fc_thread(bp);
1257
1258         if (eth_dev->data->dev_started)
1259                 bnxt_dev_stop_op(eth_dev);
1260
1261         bnxt_uninit_resources(bp, false);
1262
1263         bnxt_free_leds_info(bp);
1264         bnxt_free_cos_queues(bp);
1265
1266         eth_dev->dev_ops = NULL;
1267         eth_dev->rx_pkt_burst = NULL;
1268         eth_dev->tx_pkt_burst = NULL;
1269
1270         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1271         bp->tx_mem_zone = NULL;
1272         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1273         bp->rx_mem_zone = NULL;
1274
1275         rte_free(bp->pf.vf_info);
1276         bp->pf.vf_info = NULL;
1277
1278         rte_free(bp->grp_info);
1279         bp->grp_info = NULL;
1280 }
1281
1282 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1283                                     uint32_t index)
1284 {
1285         struct bnxt *bp = eth_dev->data->dev_private;
1286         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1287         struct bnxt_vnic_info *vnic;
1288         struct bnxt_filter_info *filter, *temp_filter;
1289         uint32_t i;
1290
1291         if (is_bnxt_in_error(bp))
1292                 return;
1293
1294         /*
1295          * Loop through all VNICs from the specified filter flow pools to
1296          * remove the corresponding MAC addr filter
1297          */
1298         for (i = 0; i < bp->nr_vnics; i++) {
1299                 if (!(pool_mask & (1ULL << i)))
1300                         continue;
1301
1302                 vnic = &bp->vnic_info[i];
1303                 filter = STAILQ_FIRST(&vnic->filter);
1304                 while (filter) {
1305                         temp_filter = STAILQ_NEXT(filter, next);
1306                         if (filter->mac_index == index) {
1307                                 STAILQ_REMOVE(&vnic->filter, filter,
1308                                                 bnxt_filter_info, next);
1309                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1310                                 bnxt_free_filter(bp, filter);
1311                         }
1312                         filter = temp_filter;
1313                 }
1314         }
1315 }
1316
1317 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1318                                struct rte_ether_addr *mac_addr, uint32_t index,
1319                                uint32_t pool)
1320 {
1321         struct bnxt_filter_info *filter;
1322         int rc = 0;
1323
1324         /* Attach requested MAC address to the new l2_filter */
1325         STAILQ_FOREACH(filter, &vnic->filter, next) {
1326                 if (filter->mac_index == index) {
1327                         PMD_DRV_LOG(DEBUG,
1328                                     "MAC addr already existed for pool %d\n",
1329                                     pool);
1330                         return 0;
1331                 }
1332         }
1333
1334         filter = bnxt_alloc_filter(bp);
1335         if (!filter) {
1336                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1337                 return -ENODEV;
1338         }
1339
1340         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1341          * if the MAC that's been programmed now is a different one, then,
1342          * copy that addr to filter->l2_addr
1343          */
1344         if (mac_addr)
1345                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1346         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1347
1348         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1349         if (!rc) {
1350                 filter->mac_index = index;
1351                 if (filter->mac_index == 0)
1352                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1353                 else
1354                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1355         } else {
1356                 bnxt_free_filter(bp, filter);
1357         }
1358
1359         return rc;
1360 }
1361
1362 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1363                                 struct rte_ether_addr *mac_addr,
1364                                 uint32_t index, uint32_t pool)
1365 {
1366         struct bnxt *bp = eth_dev->data->dev_private;
1367         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1368         int rc = 0;
1369
1370         rc = is_bnxt_in_error(bp);
1371         if (rc)
1372                 return rc;
1373
1374         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1375                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1376                 return -ENOTSUP;
1377         }
1378
1379         if (!vnic) {
1380                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1381                 return -EINVAL;
1382         }
1383
1384         /* Filter settings will get applied when port is started */
1385         if (!eth_dev->data->dev_started)
1386                 return 0;
1387
1388         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1389
1390         return rc;
1391 }
1392
1393 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1394                      bool exp_link_status)
1395 {
1396         int rc = 0;
1397         struct bnxt *bp = eth_dev->data->dev_private;
1398         struct rte_eth_link new;
1399         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1400                   BNXT_LINK_DOWN_WAIT_CNT;
1401
1402         rc = is_bnxt_in_error(bp);
1403         if (rc)
1404                 return rc;
1405
1406         memset(&new, 0, sizeof(new));
1407         do {
1408                 /* Retrieve link info from hardware */
1409                 rc = bnxt_get_hwrm_link_config(bp, &new);
1410                 if (rc) {
1411                         new.link_speed = ETH_LINK_SPEED_100M;
1412                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1413                         PMD_DRV_LOG(ERR,
1414                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1415                         goto out;
1416                 }
1417
1418                 if (!wait_to_complete || new.link_status == exp_link_status)
1419                         break;
1420
1421                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1422         } while (cnt--);
1423
1424 out:
1425         /* Timed out or success */
1426         if (new.link_status != eth_dev->data->dev_link.link_status ||
1427         new.link_speed != eth_dev->data->dev_link.link_speed) {
1428                 rte_eth_linkstatus_set(eth_dev, &new);
1429
1430                 _rte_eth_dev_callback_process(eth_dev,
1431                                               RTE_ETH_EVENT_INTR_LSC,
1432                                               NULL);
1433
1434                 bnxt_print_link_info(eth_dev);
1435         }
1436
1437         return rc;
1438 }
1439
1440 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1441                                int wait_to_complete)
1442 {
1443         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1444 }
1445
1446 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1447 {
1448         struct bnxt *bp = eth_dev->data->dev_private;
1449         struct bnxt_vnic_info *vnic;
1450         uint32_t old_flags;
1451         int rc;
1452
1453         rc = is_bnxt_in_error(bp);
1454         if (rc)
1455                 return rc;
1456
1457         /* Filter settings will get applied when port is started */
1458         if (!eth_dev->data->dev_started)
1459                 return 0;
1460
1461         if (bp->vnic_info == NULL)
1462                 return 0;
1463
1464         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1465
1466         old_flags = vnic->flags;
1467         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1468         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1469         if (rc != 0)
1470                 vnic->flags = old_flags;
1471
1472         return rc;
1473 }
1474
1475 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1476 {
1477         struct bnxt *bp = eth_dev->data->dev_private;
1478         struct bnxt_vnic_info *vnic;
1479         uint32_t old_flags;
1480         int rc;
1481
1482         rc = is_bnxt_in_error(bp);
1483         if (rc)
1484                 return rc;
1485
1486         /* Filter settings will get applied when port is started */
1487         if (!eth_dev->data->dev_started)
1488                 return 0;
1489
1490         if (bp->vnic_info == NULL)
1491                 return 0;
1492
1493         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1494
1495         old_flags = vnic->flags;
1496         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1497         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1498         if (rc != 0)
1499                 vnic->flags = old_flags;
1500
1501         return rc;
1502 }
1503
1504 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1505 {
1506         struct bnxt *bp = eth_dev->data->dev_private;
1507         struct bnxt_vnic_info *vnic;
1508         uint32_t old_flags;
1509         int rc;
1510
1511         rc = is_bnxt_in_error(bp);
1512         if (rc)
1513                 return rc;
1514
1515         /* Filter settings will get applied when port is started */
1516         if (!eth_dev->data->dev_started)
1517                 return 0;
1518
1519         if (bp->vnic_info == NULL)
1520                 return 0;
1521
1522         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1523
1524         old_flags = vnic->flags;
1525         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1526         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1527         if (rc != 0)
1528                 vnic->flags = old_flags;
1529
1530         return rc;
1531 }
1532
1533 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1534 {
1535         struct bnxt *bp = eth_dev->data->dev_private;
1536         struct bnxt_vnic_info *vnic;
1537         uint32_t old_flags;
1538         int rc;
1539
1540         rc = is_bnxt_in_error(bp);
1541         if (rc)
1542                 return rc;
1543
1544         /* Filter settings will get applied when port is started */
1545         if (!eth_dev->data->dev_started)
1546                 return 0;
1547
1548         if (bp->vnic_info == NULL)
1549                 return 0;
1550
1551         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1552
1553         old_flags = vnic->flags;
1554         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1555         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1556         if (rc != 0)
1557                 vnic->flags = old_flags;
1558
1559         return rc;
1560 }
1561
1562 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1563 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1564 {
1565         if (qid >= bp->rx_nr_rings)
1566                 return NULL;
1567
1568         return bp->eth_dev->data->rx_queues[qid];
1569 }
1570
1571 /* Return rxq corresponding to a given rss table ring/group ID. */
1572 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1573 {
1574         struct bnxt_rx_queue *rxq;
1575         unsigned int i;
1576
1577         if (!BNXT_HAS_RING_GRPS(bp)) {
1578                 for (i = 0; i < bp->rx_nr_rings; i++) {
1579                         rxq = bp->eth_dev->data->rx_queues[i];
1580                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1581                                 return rxq->index;
1582                 }
1583         } else {
1584                 for (i = 0; i < bp->rx_nr_rings; i++) {
1585                         if (bp->grp_info[i].fw_grp_id == fwr)
1586                                 return i;
1587                 }
1588         }
1589
1590         return INVALID_HW_RING_ID;
1591 }
1592
1593 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1594                             struct rte_eth_rss_reta_entry64 *reta_conf,
1595                             uint16_t reta_size)
1596 {
1597         struct bnxt *bp = eth_dev->data->dev_private;
1598         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1599         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1600         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1601         uint16_t idx, sft;
1602         int i, rc;
1603
1604         rc = is_bnxt_in_error(bp);
1605         if (rc)
1606                 return rc;
1607
1608         if (!vnic->rss_table)
1609                 return -EINVAL;
1610
1611         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1612                 return -EINVAL;
1613
1614         if (reta_size != tbl_size) {
1615                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1616                         "(%d) must equal the size supported by the hardware "
1617                         "(%d)\n", reta_size, tbl_size);
1618                 return -EINVAL;
1619         }
1620
1621         for (i = 0; i < reta_size; i++) {
1622                 struct bnxt_rx_queue *rxq;
1623
1624                 idx = i / RTE_RETA_GROUP_SIZE;
1625                 sft = i % RTE_RETA_GROUP_SIZE;
1626
1627                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1628                         continue;
1629
1630                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1631                 if (!rxq) {
1632                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1633                         return -EINVAL;
1634                 }
1635
1636                 if (BNXT_CHIP_THOR(bp)) {
1637                         vnic->rss_table[i * 2] =
1638                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1639                         vnic->rss_table[i * 2 + 1] =
1640                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1641                 } else {
1642                         vnic->rss_table[i] =
1643                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1644                 }
1645         }
1646
1647         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1648         return 0;
1649 }
1650
1651 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1652                               struct rte_eth_rss_reta_entry64 *reta_conf,
1653                               uint16_t reta_size)
1654 {
1655         struct bnxt *bp = eth_dev->data->dev_private;
1656         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1657         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1658         uint16_t idx, sft, i;
1659         int rc;
1660
1661         rc = is_bnxt_in_error(bp);
1662         if (rc)
1663                 return rc;
1664
1665         /* Retrieve from the default VNIC */
1666         if (!vnic)
1667                 return -EINVAL;
1668         if (!vnic->rss_table)
1669                 return -EINVAL;
1670
1671         if (reta_size != tbl_size) {
1672                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1673                         "(%d) must equal the size supported by the hardware "
1674                         "(%d)\n", reta_size, tbl_size);
1675                 return -EINVAL;
1676         }
1677
1678         for (idx = 0, i = 0; i < reta_size; i++) {
1679                 idx = i / RTE_RETA_GROUP_SIZE;
1680                 sft = i % RTE_RETA_GROUP_SIZE;
1681
1682                 if (reta_conf[idx].mask & (1ULL << sft)) {
1683                         uint16_t qid;
1684
1685                         if (BNXT_CHIP_THOR(bp))
1686                                 qid = bnxt_rss_to_qid(bp,
1687                                                       vnic->rss_table[i * 2]);
1688                         else
1689                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1690
1691                         if (qid == INVALID_HW_RING_ID) {
1692                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1693                                 return -EINVAL;
1694                         }
1695                         reta_conf[idx].reta[sft] = qid;
1696                 }
1697         }
1698
1699         return 0;
1700 }
1701
1702 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1703                                    struct rte_eth_rss_conf *rss_conf)
1704 {
1705         struct bnxt *bp = eth_dev->data->dev_private;
1706         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1707         struct bnxt_vnic_info *vnic;
1708         int rc;
1709
1710         rc = is_bnxt_in_error(bp);
1711         if (rc)
1712                 return rc;
1713
1714         /*
1715          * If RSS enablement were different than dev_configure,
1716          * then return -EINVAL
1717          */
1718         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1719                 if (!rss_conf->rss_hf)
1720                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1721         } else {
1722                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1723                         return -EINVAL;
1724         }
1725
1726         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1727         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1728
1729         /* Update the default RSS VNIC(s) */
1730         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1731         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1732
1733         /*
1734          * If hashkey is not specified, use the previously configured
1735          * hashkey
1736          */
1737         if (!rss_conf->rss_key)
1738                 goto rss_config;
1739
1740         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1741                 PMD_DRV_LOG(ERR,
1742                             "Invalid hashkey length, should be 16 bytes\n");
1743                 return -EINVAL;
1744         }
1745         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1746
1747 rss_config:
1748         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1749         return 0;
1750 }
1751
1752 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1753                                      struct rte_eth_rss_conf *rss_conf)
1754 {
1755         struct bnxt *bp = eth_dev->data->dev_private;
1756         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1757         int len, rc;
1758         uint32_t hash_types;
1759
1760         rc = is_bnxt_in_error(bp);
1761         if (rc)
1762                 return rc;
1763
1764         /* RSS configuration is the same for all VNICs */
1765         if (vnic && vnic->rss_hash_key) {
1766                 if (rss_conf->rss_key) {
1767                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1768                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1769                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1770                 }
1771
1772                 hash_types = vnic->hash_type;
1773                 rss_conf->rss_hf = 0;
1774                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1775                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1776                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1777                 }
1778                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1779                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1780                         hash_types &=
1781                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1782                 }
1783                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1784                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1785                         hash_types &=
1786                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1787                 }
1788                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1789                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1790                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1791                 }
1792                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1793                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1794                         hash_types &=
1795                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1796                 }
1797                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1798                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1799                         hash_types &=
1800                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1801                 }
1802                 if (hash_types) {
1803                         PMD_DRV_LOG(ERR,
1804                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1805                                 vnic->hash_type);
1806                         return -ENOTSUP;
1807                 }
1808         } else {
1809                 rss_conf->rss_hf = 0;
1810         }
1811         return 0;
1812 }
1813
1814 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1815                                struct rte_eth_fc_conf *fc_conf)
1816 {
1817         struct bnxt *bp = dev->data->dev_private;
1818         struct rte_eth_link link_info;
1819         int rc;
1820
1821         rc = is_bnxt_in_error(bp);
1822         if (rc)
1823                 return rc;
1824
1825         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1826         if (rc)
1827                 return rc;
1828
1829         memset(fc_conf, 0, sizeof(*fc_conf));
1830         if (bp->link_info.auto_pause)
1831                 fc_conf->autoneg = 1;
1832         switch (bp->link_info.pause) {
1833         case 0:
1834                 fc_conf->mode = RTE_FC_NONE;
1835                 break;
1836         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1837                 fc_conf->mode = RTE_FC_TX_PAUSE;
1838                 break;
1839         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1840                 fc_conf->mode = RTE_FC_RX_PAUSE;
1841                 break;
1842         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1843                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1844                 fc_conf->mode = RTE_FC_FULL;
1845                 break;
1846         }
1847         return 0;
1848 }
1849
1850 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1851                                struct rte_eth_fc_conf *fc_conf)
1852 {
1853         struct bnxt *bp = dev->data->dev_private;
1854         int rc;
1855
1856         rc = is_bnxt_in_error(bp);
1857         if (rc)
1858                 return rc;
1859
1860         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1861                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1862                 return -ENOTSUP;
1863         }
1864
1865         switch (fc_conf->mode) {
1866         case RTE_FC_NONE:
1867                 bp->link_info.auto_pause = 0;
1868                 bp->link_info.force_pause = 0;
1869                 break;
1870         case RTE_FC_RX_PAUSE:
1871                 if (fc_conf->autoneg) {
1872                         bp->link_info.auto_pause =
1873                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1874                         bp->link_info.force_pause = 0;
1875                 } else {
1876                         bp->link_info.auto_pause = 0;
1877                         bp->link_info.force_pause =
1878                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1879                 }
1880                 break;
1881         case RTE_FC_TX_PAUSE:
1882                 if (fc_conf->autoneg) {
1883                         bp->link_info.auto_pause =
1884                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1885                         bp->link_info.force_pause = 0;
1886                 } else {
1887                         bp->link_info.auto_pause = 0;
1888                         bp->link_info.force_pause =
1889                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1890                 }
1891                 break;
1892         case RTE_FC_FULL:
1893                 if (fc_conf->autoneg) {
1894                         bp->link_info.auto_pause =
1895                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1896                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1897                         bp->link_info.force_pause = 0;
1898                 } else {
1899                         bp->link_info.auto_pause = 0;
1900                         bp->link_info.force_pause =
1901                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1902                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1903                 }
1904                 break;
1905         }
1906         return bnxt_set_hwrm_link_config(bp, true);
1907 }
1908
1909 /* Add UDP tunneling port */
1910 static int
1911 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1912                          struct rte_eth_udp_tunnel *udp_tunnel)
1913 {
1914         struct bnxt *bp = eth_dev->data->dev_private;
1915         uint16_t tunnel_type = 0;
1916         int rc = 0;
1917
1918         rc = is_bnxt_in_error(bp);
1919         if (rc)
1920                 return rc;
1921
1922         switch (udp_tunnel->prot_type) {
1923         case RTE_TUNNEL_TYPE_VXLAN:
1924                 if (bp->vxlan_port_cnt) {
1925                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1926                                 udp_tunnel->udp_port);
1927                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1928                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1929                                 return -ENOSPC;
1930                         }
1931                         bp->vxlan_port_cnt++;
1932                         return 0;
1933                 }
1934                 tunnel_type =
1935                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1936                 bp->vxlan_port_cnt++;
1937                 break;
1938         case RTE_TUNNEL_TYPE_GENEVE:
1939                 if (bp->geneve_port_cnt) {
1940                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1941                                 udp_tunnel->udp_port);
1942                         if (bp->geneve_port != udp_tunnel->udp_port) {
1943                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1944                                 return -ENOSPC;
1945                         }
1946                         bp->geneve_port_cnt++;
1947                         return 0;
1948                 }
1949                 tunnel_type =
1950                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1951                 bp->geneve_port_cnt++;
1952                 break;
1953         default:
1954                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1955                 return -ENOTSUP;
1956         }
1957         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1958                                              tunnel_type);
1959         return rc;
1960 }
1961
1962 static int
1963 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1964                          struct rte_eth_udp_tunnel *udp_tunnel)
1965 {
1966         struct bnxt *bp = eth_dev->data->dev_private;
1967         uint16_t tunnel_type = 0;
1968         uint16_t port = 0;
1969         int rc = 0;
1970
1971         rc = is_bnxt_in_error(bp);
1972         if (rc)
1973                 return rc;
1974
1975         switch (udp_tunnel->prot_type) {
1976         case RTE_TUNNEL_TYPE_VXLAN:
1977                 if (!bp->vxlan_port_cnt) {
1978                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1979                         return -EINVAL;
1980                 }
1981                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1982                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1983                                 udp_tunnel->udp_port, bp->vxlan_port);
1984                         return -EINVAL;
1985                 }
1986                 if (--bp->vxlan_port_cnt)
1987                         return 0;
1988
1989                 tunnel_type =
1990                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1991                 port = bp->vxlan_fw_dst_port_id;
1992                 break;
1993         case RTE_TUNNEL_TYPE_GENEVE:
1994                 if (!bp->geneve_port_cnt) {
1995                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1996                         return -EINVAL;
1997                 }
1998                 if (bp->geneve_port != udp_tunnel->udp_port) {
1999                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2000                                 udp_tunnel->udp_port, bp->geneve_port);
2001                         return -EINVAL;
2002                 }
2003                 if (--bp->geneve_port_cnt)
2004                         return 0;
2005
2006                 tunnel_type =
2007                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2008                 port = bp->geneve_fw_dst_port_id;
2009                 break;
2010         default:
2011                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2012                 return -ENOTSUP;
2013         }
2014
2015         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2016         if (!rc) {
2017                 if (tunnel_type ==
2018                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2019                         bp->vxlan_port = 0;
2020                 if (tunnel_type ==
2021                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2022                         bp->geneve_port = 0;
2023         }
2024         return rc;
2025 }
2026
2027 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2028 {
2029         struct bnxt_filter_info *filter;
2030         struct bnxt_vnic_info *vnic;
2031         int rc = 0;
2032         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2033
2034         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2035         filter = STAILQ_FIRST(&vnic->filter);
2036         while (filter) {
2037                 /* Search for this matching MAC+VLAN filter */
2038                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2039                         /* Delete the filter */
2040                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2041                         if (rc)
2042                                 return rc;
2043                         STAILQ_REMOVE(&vnic->filter, filter,
2044                                       bnxt_filter_info, next);
2045                         bnxt_free_filter(bp, filter);
2046                         PMD_DRV_LOG(INFO,
2047                                     "Deleted vlan filter for %d\n",
2048                                     vlan_id);
2049                         return 0;
2050                 }
2051                 filter = STAILQ_NEXT(filter, next);
2052         }
2053         return -ENOENT;
2054 }
2055
2056 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2057 {
2058         struct bnxt_filter_info *filter;
2059         struct bnxt_vnic_info *vnic;
2060         int rc = 0;
2061         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2062                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2063         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2064
2065         /* Implementation notes on the use of VNIC in this command:
2066          *
2067          * By default, these filters belong to default vnic for the function.
2068          * Once these filters are set up, only destination VNIC can be modified.
2069          * If the destination VNIC is not specified in this command,
2070          * then the HWRM shall only create an l2 context id.
2071          */
2072
2073         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2074         filter = STAILQ_FIRST(&vnic->filter);
2075         /* Check if the VLAN has already been added */
2076         while (filter) {
2077                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2078                         return -EEXIST;
2079
2080                 filter = STAILQ_NEXT(filter, next);
2081         }
2082
2083         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2084          * command to create MAC+VLAN filter with the right flags, enables set.
2085          */
2086         filter = bnxt_alloc_filter(bp);
2087         if (!filter) {
2088                 PMD_DRV_LOG(ERR,
2089                             "MAC/VLAN filter alloc failed\n");
2090                 return -ENOMEM;
2091         }
2092         /* MAC + VLAN ID filter */
2093         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2094          * untagged packets are received
2095          *
2096          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2097          * packets and only the programmed vlan's packets are received
2098          */
2099         filter->l2_ivlan = vlan_id;
2100         filter->l2_ivlan_mask = 0x0FFF;
2101         filter->enables |= en;
2102         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2103
2104         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2105         if (rc) {
2106                 /* Free the newly allocated filter as we were
2107                  * not able to create the filter in hardware.
2108                  */
2109                 bnxt_free_filter(bp, filter);
2110                 return rc;
2111         }
2112
2113         filter->mac_index = 0;
2114         /* Add this new filter to the list */
2115         if (vlan_id == 0)
2116                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2117         else
2118                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2119
2120         PMD_DRV_LOG(INFO,
2121                     "Added Vlan filter for %d\n", vlan_id);
2122         return rc;
2123 }
2124
2125 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2126                 uint16_t vlan_id, int on)
2127 {
2128         struct bnxt *bp = eth_dev->data->dev_private;
2129         int rc;
2130
2131         rc = is_bnxt_in_error(bp);
2132         if (rc)
2133                 return rc;
2134
2135         if (!eth_dev->data->dev_started) {
2136                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2137                 return -EINVAL;
2138         }
2139
2140         /* These operations apply to ALL existing MAC/VLAN filters */
2141         if (on)
2142                 return bnxt_add_vlan_filter(bp, vlan_id);
2143         else
2144                 return bnxt_del_vlan_filter(bp, vlan_id);
2145 }
2146
2147 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2148                                     struct bnxt_vnic_info *vnic)
2149 {
2150         struct bnxt_filter_info *filter;
2151         int rc;
2152
2153         filter = STAILQ_FIRST(&vnic->filter);
2154         while (filter) {
2155                 if (filter->mac_index == 0 &&
2156                     !memcmp(filter->l2_addr, bp->mac_addr,
2157                             RTE_ETHER_ADDR_LEN)) {
2158                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2159                         if (!rc) {
2160                                 STAILQ_REMOVE(&vnic->filter, filter,
2161                                               bnxt_filter_info, next);
2162                                 bnxt_free_filter(bp, filter);
2163                         }
2164                         return rc;
2165                 }
2166                 filter = STAILQ_NEXT(filter, next);
2167         }
2168         return 0;
2169 }
2170
2171 static int
2172 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2173 {
2174         struct bnxt_vnic_info *vnic;
2175         unsigned int i;
2176         int rc;
2177
2178         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2179         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2180                 /* Remove any VLAN filters programmed */
2181                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2182                         bnxt_del_vlan_filter(bp, i);
2183
2184                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2185                 if (rc)
2186                         return rc;
2187         } else {
2188                 /* Default filter will allow packets that match the
2189                  * dest mac. So, it has to be deleted, otherwise, we
2190                  * will endup receiving vlan packets for which the
2191                  * filter is not programmed, when hw-vlan-filter
2192                  * configuration is ON
2193                  */
2194                 bnxt_del_dflt_mac_filter(bp, vnic);
2195                 /* This filter will allow only untagged packets */
2196                 bnxt_add_vlan_filter(bp, 0);
2197         }
2198         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2199                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2200
2201         return 0;
2202 }
2203
2204 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2205 {
2206         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2207         unsigned int i;
2208         int rc;
2209
2210         /* Destroy vnic filters and vnic */
2211         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2212             DEV_RX_OFFLOAD_VLAN_FILTER) {
2213                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2214                         bnxt_del_vlan_filter(bp, i);
2215         }
2216         bnxt_del_dflt_mac_filter(bp, vnic);
2217
2218         rc = bnxt_hwrm_vnic_free(bp, vnic);
2219         if (rc)
2220                 return rc;
2221
2222         rte_free(vnic->fw_grp_ids);
2223         vnic->fw_grp_ids = NULL;
2224
2225         vnic->rx_queue_cnt = 0;
2226
2227         return 0;
2228 }
2229
2230 static int
2231 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2232 {
2233         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2234         int rc;
2235
2236         /* Destroy, recreate and reconfigure the default vnic */
2237         rc = bnxt_free_one_vnic(bp, 0);
2238         if (rc)
2239                 return rc;
2240
2241         /* default vnic 0 */
2242         rc = bnxt_setup_one_vnic(bp, 0);
2243         if (rc)
2244                 return rc;
2245
2246         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2247             DEV_RX_OFFLOAD_VLAN_FILTER) {
2248                 rc = bnxt_add_vlan_filter(bp, 0);
2249                 if (rc)
2250                         return rc;
2251                 rc = bnxt_restore_vlan_filters(bp);
2252                 if (rc)
2253                         return rc;
2254         } else {
2255                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2256                 if (rc)
2257                         return rc;
2258         }
2259
2260         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2261         if (rc)
2262                 return rc;
2263
2264         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2265                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2266
2267         return rc;
2268 }
2269
2270 static int
2271 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2272 {
2273         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2274         struct bnxt *bp = dev->data->dev_private;
2275         int rc;
2276
2277         rc = is_bnxt_in_error(bp);
2278         if (rc)
2279                 return rc;
2280
2281         /* Filter settings will get applied when port is started */
2282         if (!dev->data->dev_started)
2283                 return 0;
2284
2285         if (mask & ETH_VLAN_FILTER_MASK) {
2286                 /* Enable or disable VLAN filtering */
2287                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2288                 if (rc)
2289                         return rc;
2290         }
2291
2292         if (mask & ETH_VLAN_STRIP_MASK) {
2293                 /* Enable or disable VLAN stripping */
2294                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2295                 if (rc)
2296                         return rc;
2297         }
2298
2299         if (mask & ETH_VLAN_EXTEND_MASK) {
2300                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2301                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2302                 else
2303                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2304         }
2305
2306         return 0;
2307 }
2308
2309 static int
2310 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2311                       uint16_t tpid)
2312 {
2313         struct bnxt *bp = dev->data->dev_private;
2314         int qinq = dev->data->dev_conf.rxmode.offloads &
2315                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2316
2317         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2318             vlan_type != ETH_VLAN_TYPE_OUTER) {
2319                 PMD_DRV_LOG(ERR,
2320                             "Unsupported vlan type.");
2321                 return -EINVAL;
2322         }
2323         if (!qinq) {
2324                 PMD_DRV_LOG(ERR,
2325                             "QinQ not enabled. Needs to be ON as we can "
2326                             "accelerate only outer vlan\n");
2327                 return -EINVAL;
2328         }
2329
2330         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2331                 switch (tpid) {
2332                 case RTE_ETHER_TYPE_QINQ:
2333                         bp->outer_tpid_bd =
2334                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2335                                 break;
2336                 case RTE_ETHER_TYPE_VLAN:
2337                         bp->outer_tpid_bd =
2338                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2339                                 break;
2340                 case 0x9100:
2341                         bp->outer_tpid_bd =
2342                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2343                                 break;
2344                 case 0x9200:
2345                         bp->outer_tpid_bd =
2346                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2347                                 break;
2348                 case 0x9300:
2349                         bp->outer_tpid_bd =
2350                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2351                                 break;
2352                 default:
2353                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2354                         return -EINVAL;
2355                 }
2356                 bp->outer_tpid_bd |= tpid;
2357                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2358         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2359                 PMD_DRV_LOG(ERR,
2360                             "Can accelerate only outer vlan in QinQ\n");
2361                 return -EINVAL;
2362         }
2363
2364         return 0;
2365 }
2366
2367 static int
2368 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2369                              struct rte_ether_addr *addr)
2370 {
2371         struct bnxt *bp = dev->data->dev_private;
2372         /* Default Filter is tied to VNIC 0 */
2373         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2374         int rc;
2375
2376         rc = is_bnxt_in_error(bp);
2377         if (rc)
2378                 return rc;
2379
2380         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2381                 return -EPERM;
2382
2383         if (rte_is_zero_ether_addr(addr))
2384                 return -EINVAL;
2385
2386         /* Filter settings will get applied when port is started */
2387         if (!dev->data->dev_started)
2388                 return 0;
2389
2390         /* Check if the requested MAC is already added */
2391         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2392                 return 0;
2393
2394         /* Destroy filter and re-create it */
2395         bnxt_del_dflt_mac_filter(bp, vnic);
2396
2397         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2398         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2399                 /* This filter will allow only untagged packets */
2400                 rc = bnxt_add_vlan_filter(bp, 0);
2401         } else {
2402                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2403         }
2404
2405         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2406         return rc;
2407 }
2408
2409 static int
2410 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2411                           struct rte_ether_addr *mc_addr_set,
2412                           uint32_t nb_mc_addr)
2413 {
2414         struct bnxt *bp = eth_dev->data->dev_private;
2415         char *mc_addr_list = (char *)mc_addr_set;
2416         struct bnxt_vnic_info *vnic;
2417         uint32_t off = 0, i = 0;
2418         int rc;
2419
2420         rc = is_bnxt_in_error(bp);
2421         if (rc)
2422                 return rc;
2423
2424         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2425
2426         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2427                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2428                 goto allmulti;
2429         }
2430
2431         /* TODO Check for Duplicate mcast addresses */
2432         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2433         for (i = 0; i < nb_mc_addr; i++) {
2434                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2435                         RTE_ETHER_ADDR_LEN);
2436                 off += RTE_ETHER_ADDR_LEN;
2437         }
2438
2439         vnic->mc_addr_cnt = i;
2440         if (vnic->mc_addr_cnt)
2441                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2442         else
2443                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2444
2445 allmulti:
2446         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2447 }
2448
2449 static int
2450 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2451 {
2452         struct bnxt *bp = dev->data->dev_private;
2453         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2454         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2455         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2456         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2457         int ret;
2458
2459         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2460                         fw_major, fw_minor, fw_updt, fw_rsvd);
2461
2462         ret += 1; /* add the size of '\0' */
2463         if (fw_size < (uint32_t)ret)
2464                 return ret;
2465         else
2466                 return 0;
2467 }
2468
2469 static void
2470 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2471         struct rte_eth_rxq_info *qinfo)
2472 {
2473         struct bnxt *bp = dev->data->dev_private;
2474         struct bnxt_rx_queue *rxq;
2475
2476         if (is_bnxt_in_error(bp))
2477                 return;
2478
2479         rxq = dev->data->rx_queues[queue_id];
2480
2481         qinfo->mp = rxq->mb_pool;
2482         qinfo->scattered_rx = dev->data->scattered_rx;
2483         qinfo->nb_desc = rxq->nb_rx_desc;
2484
2485         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2486         qinfo->conf.rx_drop_en = 0;
2487         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2488 }
2489
2490 static void
2491 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2492         struct rte_eth_txq_info *qinfo)
2493 {
2494         struct bnxt *bp = dev->data->dev_private;
2495         struct bnxt_tx_queue *txq;
2496
2497         if (is_bnxt_in_error(bp))
2498                 return;
2499
2500         txq = dev->data->tx_queues[queue_id];
2501
2502         qinfo->nb_desc = txq->nb_tx_desc;
2503
2504         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2505         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2506         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2507
2508         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2509         qinfo->conf.tx_rs_thresh = 0;
2510         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2511 }
2512
2513 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2514 {
2515         struct bnxt *bp = eth_dev->data->dev_private;
2516         uint32_t new_pkt_size;
2517         uint32_t rc = 0;
2518         uint32_t i;
2519
2520         rc = is_bnxt_in_error(bp);
2521         if (rc)
2522                 return rc;
2523
2524         /* Exit if receive queues are not configured yet */
2525         if (!eth_dev->data->nb_rx_queues)
2526                 return rc;
2527
2528         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2529                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2530
2531 #ifdef RTE_ARCH_X86
2532         /*
2533          * If vector-mode tx/rx is active, disallow any MTU change that would
2534          * require scattered receive support.
2535          */
2536         if (eth_dev->data->dev_started &&
2537             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2538              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2539             (new_pkt_size >
2540              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2541                 PMD_DRV_LOG(ERR,
2542                             "MTU change would require scattered rx support. ");
2543                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2544                 return -EINVAL;
2545         }
2546 #endif
2547
2548         if (new_mtu > RTE_ETHER_MTU) {
2549                 bp->flags |= BNXT_FLAG_JUMBO;
2550                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2551                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2552         } else {
2553                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2554                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2555                 bp->flags &= ~BNXT_FLAG_JUMBO;
2556         }
2557
2558         /* Is there a change in mtu setting? */
2559         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2560                 return rc;
2561
2562         for (i = 0; i < bp->nr_vnics; i++) {
2563                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2564                 uint16_t size = 0;
2565
2566                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2567                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2568                 if (rc)
2569                         break;
2570
2571                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2572                 size -= RTE_PKTMBUF_HEADROOM;
2573
2574                 if (size < new_mtu) {
2575                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2576                         if (rc)
2577                                 return rc;
2578                 }
2579         }
2580
2581         if (!rc)
2582                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2583
2584         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2585
2586         return rc;
2587 }
2588
2589 static int
2590 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2591 {
2592         struct bnxt *bp = dev->data->dev_private;
2593         uint16_t vlan = bp->vlan;
2594         int rc;
2595
2596         rc = is_bnxt_in_error(bp);
2597         if (rc)
2598                 return rc;
2599
2600         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2601                 PMD_DRV_LOG(ERR,
2602                         "PVID cannot be modified for this function\n");
2603                 return -ENOTSUP;
2604         }
2605         bp->vlan = on ? pvid : 0;
2606
2607         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2608         if (rc)
2609                 bp->vlan = vlan;
2610         return rc;
2611 }
2612
2613 static int
2614 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2615 {
2616         struct bnxt *bp = dev->data->dev_private;
2617         int rc;
2618
2619         rc = is_bnxt_in_error(bp);
2620         if (rc)
2621                 return rc;
2622
2623         return bnxt_hwrm_port_led_cfg(bp, true);
2624 }
2625
2626 static int
2627 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2628 {
2629         struct bnxt *bp = dev->data->dev_private;
2630         int rc;
2631
2632         rc = is_bnxt_in_error(bp);
2633         if (rc)
2634                 return rc;
2635
2636         return bnxt_hwrm_port_led_cfg(bp, false);
2637 }
2638
2639 static uint32_t
2640 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2641 {
2642         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2643         uint32_t desc = 0, raw_cons = 0, cons;
2644         struct bnxt_cp_ring_info *cpr;
2645         struct bnxt_rx_queue *rxq;
2646         struct rx_pkt_cmpl *rxcmp;
2647         int rc;
2648
2649         rc = is_bnxt_in_error(bp);
2650         if (rc)
2651                 return rc;
2652
2653         rxq = dev->data->rx_queues[rx_queue_id];
2654         cpr = rxq->cp_ring;
2655         raw_cons = cpr->cp_raw_cons;
2656
2657         while (1) {
2658                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2659                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2660                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2661
2662                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2663                         break;
2664                 } else {
2665                         raw_cons++;
2666                         desc++;
2667                 }
2668         }
2669
2670         return desc;
2671 }
2672
2673 static int
2674 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2675 {
2676         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2677         struct bnxt_rx_ring_info *rxr;
2678         struct bnxt_cp_ring_info *cpr;
2679         struct bnxt_sw_rx_bd *rx_buf;
2680         struct rx_pkt_cmpl *rxcmp;
2681         uint32_t cons, cp_cons;
2682         int rc;
2683
2684         if (!rxq)
2685                 return -EINVAL;
2686
2687         rc = is_bnxt_in_error(rxq->bp);
2688         if (rc)
2689                 return rc;
2690
2691         cpr = rxq->cp_ring;
2692         rxr = rxq->rx_ring;
2693
2694         if (offset >= rxq->nb_rx_desc)
2695                 return -EINVAL;
2696
2697         cons = RING_CMP(cpr->cp_ring_struct, offset);
2698         cp_cons = cpr->cp_raw_cons;
2699         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2700
2701         if (cons > cp_cons) {
2702                 if (CMPL_VALID(rxcmp, cpr->valid))
2703                         return RTE_ETH_RX_DESC_DONE;
2704         } else {
2705                 if (CMPL_VALID(rxcmp, !cpr->valid))
2706                         return RTE_ETH_RX_DESC_DONE;
2707         }
2708         rx_buf = &rxr->rx_buf_ring[cons];
2709         if (rx_buf->mbuf == NULL)
2710                 return RTE_ETH_RX_DESC_UNAVAIL;
2711
2712
2713         return RTE_ETH_RX_DESC_AVAIL;
2714 }
2715
2716 static int
2717 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2718 {
2719         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2720         struct bnxt_tx_ring_info *txr;
2721         struct bnxt_cp_ring_info *cpr;
2722         struct bnxt_sw_tx_bd *tx_buf;
2723         struct tx_pkt_cmpl *txcmp;
2724         uint32_t cons, cp_cons;
2725         int rc;
2726
2727         if (!txq)
2728                 return -EINVAL;
2729
2730         rc = is_bnxt_in_error(txq->bp);
2731         if (rc)
2732                 return rc;
2733
2734         cpr = txq->cp_ring;
2735         txr = txq->tx_ring;
2736
2737         if (offset >= txq->nb_tx_desc)
2738                 return -EINVAL;
2739
2740         cons = RING_CMP(cpr->cp_ring_struct, offset);
2741         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2742         cp_cons = cpr->cp_raw_cons;
2743
2744         if (cons > cp_cons) {
2745                 if (CMPL_VALID(txcmp, cpr->valid))
2746                         return RTE_ETH_TX_DESC_UNAVAIL;
2747         } else {
2748                 if (CMPL_VALID(txcmp, !cpr->valid))
2749                         return RTE_ETH_TX_DESC_UNAVAIL;
2750         }
2751         tx_buf = &txr->tx_buf_ring[cons];
2752         if (tx_buf->mbuf == NULL)
2753                 return RTE_ETH_TX_DESC_DONE;
2754
2755         return RTE_ETH_TX_DESC_FULL;
2756 }
2757
2758 static struct bnxt_filter_info *
2759 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2760                                 struct rte_eth_ethertype_filter *efilter,
2761                                 struct bnxt_vnic_info *vnic0,
2762                                 struct bnxt_vnic_info *vnic,
2763                                 int *ret)
2764 {
2765         struct bnxt_filter_info *mfilter = NULL;
2766         int match = 0;
2767         *ret = 0;
2768
2769         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2770                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2771                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2772                         " ethertype filter.", efilter->ether_type);
2773                 *ret = -EINVAL;
2774                 goto exit;
2775         }
2776         if (efilter->queue >= bp->rx_nr_rings) {
2777                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2778                 *ret = -EINVAL;
2779                 goto exit;
2780         }
2781
2782         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2783         vnic = &bp->vnic_info[efilter->queue];
2784         if (vnic == NULL) {
2785                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2786                 *ret = -EINVAL;
2787                 goto exit;
2788         }
2789
2790         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2791                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2792                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2793                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2794                              mfilter->flags ==
2795                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2796                              mfilter->ethertype == efilter->ether_type)) {
2797                                 match = 1;
2798                                 break;
2799                         }
2800                 }
2801         } else {
2802                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2803                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2804                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2805                              mfilter->ethertype == efilter->ether_type &&
2806                              mfilter->flags ==
2807                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2808                                 match = 1;
2809                                 break;
2810                         }
2811         }
2812
2813         if (match)
2814                 *ret = -EEXIST;
2815
2816 exit:
2817         return mfilter;
2818 }
2819
2820 static int
2821 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2822                         enum rte_filter_op filter_op,
2823                         void *arg)
2824 {
2825         struct bnxt *bp = dev->data->dev_private;
2826         struct rte_eth_ethertype_filter *efilter =
2827                         (struct rte_eth_ethertype_filter *)arg;
2828         struct bnxt_filter_info *bfilter, *filter1;
2829         struct bnxt_vnic_info *vnic, *vnic0;
2830         int ret;
2831
2832         if (filter_op == RTE_ETH_FILTER_NOP)
2833                 return 0;
2834
2835         if (arg == NULL) {
2836                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2837                             filter_op);
2838                 return -EINVAL;
2839         }
2840
2841         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2842         vnic = &bp->vnic_info[efilter->queue];
2843
2844         switch (filter_op) {
2845         case RTE_ETH_FILTER_ADD:
2846                 bnxt_match_and_validate_ether_filter(bp, efilter,
2847                                                         vnic0, vnic, &ret);
2848                 if (ret < 0)
2849                         return ret;
2850
2851                 bfilter = bnxt_get_unused_filter(bp);
2852                 if (bfilter == NULL) {
2853                         PMD_DRV_LOG(ERR,
2854                                 "Not enough resources for a new filter.\n");
2855                         return -ENOMEM;
2856                 }
2857                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2858                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2859                        RTE_ETHER_ADDR_LEN);
2860                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2861                        RTE_ETHER_ADDR_LEN);
2862                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2863                 bfilter->ethertype = efilter->ether_type;
2864                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2865
2866                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2867                 if (filter1 == NULL) {
2868                         ret = -EINVAL;
2869                         goto cleanup;
2870                 }
2871                 bfilter->enables |=
2872                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2873                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2874
2875                 bfilter->dst_id = vnic->fw_vnic_id;
2876
2877                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2878                         bfilter->flags =
2879                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2880                 }
2881
2882                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2883                 if (ret)
2884                         goto cleanup;
2885                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2886                 break;
2887         case RTE_ETH_FILTER_DELETE:
2888                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2889                                                         vnic0, vnic, &ret);
2890                 if (ret == -EEXIST) {
2891                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2892
2893                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2894                                       next);
2895                         bnxt_free_filter(bp, filter1);
2896                 } else if (ret == 0) {
2897                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2898                 }
2899                 break;
2900         default:
2901                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2902                 ret = -EINVAL;
2903                 goto error;
2904         }
2905         return ret;
2906 cleanup:
2907         bnxt_free_filter(bp, bfilter);
2908 error:
2909         return ret;
2910 }
2911
2912 static inline int
2913 parse_ntuple_filter(struct bnxt *bp,
2914                     struct rte_eth_ntuple_filter *nfilter,
2915                     struct bnxt_filter_info *bfilter)
2916 {
2917         uint32_t en = 0;
2918
2919         if (nfilter->queue >= bp->rx_nr_rings) {
2920                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2921                 return -EINVAL;
2922         }
2923
2924         switch (nfilter->dst_port_mask) {
2925         case UINT16_MAX:
2926                 bfilter->dst_port_mask = -1;
2927                 bfilter->dst_port = nfilter->dst_port;
2928                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2929                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2930                 break;
2931         default:
2932                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2933                 return -EINVAL;
2934         }
2935
2936         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2937         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2938
2939         switch (nfilter->proto_mask) {
2940         case UINT8_MAX:
2941                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2942                         bfilter->ip_protocol = 17;
2943                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2944                         bfilter->ip_protocol = 6;
2945                 else
2946                         return -EINVAL;
2947                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2948                 break;
2949         default:
2950                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2951                 return -EINVAL;
2952         }
2953
2954         switch (nfilter->dst_ip_mask) {
2955         case UINT32_MAX:
2956                 bfilter->dst_ipaddr_mask[0] = -1;
2957                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2958                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2959                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2960                 break;
2961         default:
2962                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2963                 return -EINVAL;
2964         }
2965
2966         switch (nfilter->src_ip_mask) {
2967         case UINT32_MAX:
2968                 bfilter->src_ipaddr_mask[0] = -1;
2969                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2970                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2971                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2972                 break;
2973         default:
2974                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2975                 return -EINVAL;
2976         }
2977
2978         switch (nfilter->src_port_mask) {
2979         case UINT16_MAX:
2980                 bfilter->src_port_mask = -1;
2981                 bfilter->src_port = nfilter->src_port;
2982                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2983                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2984                 break;
2985         default:
2986                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2987                 return -EINVAL;
2988         }
2989
2990         bfilter->enables = en;
2991         return 0;
2992 }
2993
2994 static struct bnxt_filter_info*
2995 bnxt_match_ntuple_filter(struct bnxt *bp,
2996                          struct bnxt_filter_info *bfilter,
2997                          struct bnxt_vnic_info **mvnic)
2998 {
2999         struct bnxt_filter_info *mfilter = NULL;
3000         int i;
3001
3002         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3003                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3004                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3005                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3006                             bfilter->src_ipaddr_mask[0] ==
3007                             mfilter->src_ipaddr_mask[0] &&
3008                             bfilter->src_port == mfilter->src_port &&
3009                             bfilter->src_port_mask == mfilter->src_port_mask &&
3010                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3011                             bfilter->dst_ipaddr_mask[0] ==
3012                             mfilter->dst_ipaddr_mask[0] &&
3013                             bfilter->dst_port == mfilter->dst_port &&
3014                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3015                             bfilter->flags == mfilter->flags &&
3016                             bfilter->enables == mfilter->enables) {
3017                                 if (mvnic)
3018                                         *mvnic = vnic;
3019                                 return mfilter;
3020                         }
3021                 }
3022         }
3023         return NULL;
3024 }
3025
3026 static int
3027 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3028                        struct rte_eth_ntuple_filter *nfilter,
3029                        enum rte_filter_op filter_op)
3030 {
3031         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3032         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3033         int ret;
3034
3035         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3036                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3037                 return -EINVAL;
3038         }
3039
3040         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3041                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3042                 return -EINVAL;
3043         }
3044
3045         bfilter = bnxt_get_unused_filter(bp);
3046         if (bfilter == NULL) {
3047                 PMD_DRV_LOG(ERR,
3048                         "Not enough resources for a new filter.\n");
3049                 return -ENOMEM;
3050         }
3051         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3052         if (ret < 0)
3053                 goto free_filter;
3054
3055         vnic = &bp->vnic_info[nfilter->queue];
3056         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3057         filter1 = STAILQ_FIRST(&vnic0->filter);
3058         if (filter1 == NULL) {
3059                 ret = -EINVAL;
3060                 goto free_filter;
3061         }
3062
3063         bfilter->dst_id = vnic->fw_vnic_id;
3064         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3065         bfilter->enables |=
3066                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3067         bfilter->ethertype = 0x800;
3068         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3069
3070         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3071
3072         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3073             bfilter->dst_id == mfilter->dst_id) {
3074                 PMD_DRV_LOG(ERR, "filter exists.\n");
3075                 ret = -EEXIST;
3076                 goto free_filter;
3077         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3078                    bfilter->dst_id != mfilter->dst_id) {
3079                 mfilter->dst_id = vnic->fw_vnic_id;
3080                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3081                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3082                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3083                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3084                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3085                 goto free_filter;
3086         }
3087         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3088                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3089                 ret = -ENOENT;
3090                 goto free_filter;
3091         }
3092
3093         if (filter_op == RTE_ETH_FILTER_ADD) {
3094                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3095                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3096                 if (ret)
3097                         goto free_filter;
3098                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3099         } else {
3100                 if (mfilter == NULL) {
3101                         /* This should not happen. But for Coverity! */
3102                         ret = -ENOENT;
3103                         goto free_filter;
3104                 }
3105                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3106
3107                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3108                 bnxt_free_filter(bp, mfilter);
3109                 bnxt_free_filter(bp, bfilter);
3110         }
3111
3112         return 0;
3113 free_filter:
3114         bnxt_free_filter(bp, bfilter);
3115         return ret;
3116 }
3117
3118 static int
3119 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3120                         enum rte_filter_op filter_op,
3121                         void *arg)
3122 {
3123         struct bnxt *bp = dev->data->dev_private;
3124         int ret;
3125
3126         if (filter_op == RTE_ETH_FILTER_NOP)
3127                 return 0;
3128
3129         if (arg == NULL) {
3130                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3131                             filter_op);
3132                 return -EINVAL;
3133         }
3134
3135         switch (filter_op) {
3136         case RTE_ETH_FILTER_ADD:
3137                 ret = bnxt_cfg_ntuple_filter(bp,
3138                         (struct rte_eth_ntuple_filter *)arg,
3139                         filter_op);
3140                 break;
3141         case RTE_ETH_FILTER_DELETE:
3142                 ret = bnxt_cfg_ntuple_filter(bp,
3143                         (struct rte_eth_ntuple_filter *)arg,
3144                         filter_op);
3145                 break;
3146         default:
3147                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3148                 ret = -EINVAL;
3149                 break;
3150         }
3151         return ret;
3152 }
3153
3154 static int
3155 bnxt_parse_fdir_filter(struct bnxt *bp,
3156                        struct rte_eth_fdir_filter *fdir,
3157                        struct bnxt_filter_info *filter)
3158 {
3159         enum rte_fdir_mode fdir_mode =
3160                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3161         struct bnxt_vnic_info *vnic0, *vnic;
3162         struct bnxt_filter_info *filter1;
3163         uint32_t en = 0;
3164         int i;
3165
3166         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3167                 return -EINVAL;
3168
3169         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3170         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3171
3172         switch (fdir->input.flow_type) {
3173         case RTE_ETH_FLOW_IPV4:
3174         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3175                 /* FALLTHROUGH */
3176                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3177                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3178                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3179                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3180                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3181                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3182                 filter->ip_addr_type =
3183                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3184                 filter->src_ipaddr_mask[0] = 0xffffffff;
3185                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3186                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3187                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3188                 filter->ethertype = 0x800;
3189                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3190                 break;
3191         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3192                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3193                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3194                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3195                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3196                 filter->dst_port_mask = 0xffff;
3197                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3198                 filter->src_port_mask = 0xffff;
3199                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3200                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3201                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3202                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3203                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3204                 filter->ip_protocol = 6;
3205                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3206                 filter->ip_addr_type =
3207                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3208                 filter->src_ipaddr_mask[0] = 0xffffffff;
3209                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3210                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3211                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3212                 filter->ethertype = 0x800;
3213                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3214                 break;
3215         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3216                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3217                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3218                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3219                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3220                 filter->dst_port_mask = 0xffff;
3221                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3222                 filter->src_port_mask = 0xffff;
3223                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3224                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3225                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3226                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3227                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3228                 filter->ip_protocol = 17;
3229                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3230                 filter->ip_addr_type =
3231                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3232                 filter->src_ipaddr_mask[0] = 0xffffffff;
3233                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3234                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3235                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3236                 filter->ethertype = 0x800;
3237                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3238                 break;
3239         case RTE_ETH_FLOW_IPV6:
3240         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3241                 /* FALLTHROUGH */
3242                 filter->ip_addr_type =
3243                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3244                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3245                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3246                 rte_memcpy(filter->src_ipaddr,
3247                            fdir->input.flow.ipv6_flow.src_ip, 16);
3248                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3249                 rte_memcpy(filter->dst_ipaddr,
3250                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3251                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3252                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3253                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3254                 memset(filter->src_ipaddr_mask, 0xff, 16);
3255                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3256                 filter->ethertype = 0x86dd;
3257                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3258                 break;
3259         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3260                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3261                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3262                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3263                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3264                 filter->dst_port_mask = 0xffff;
3265                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3266                 filter->src_port_mask = 0xffff;
3267                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3268                 filter->ip_addr_type =
3269                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3270                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3271                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3272                 rte_memcpy(filter->src_ipaddr,
3273                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3274                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3275                 rte_memcpy(filter->dst_ipaddr,
3276                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3277                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3278                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3279                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3280                 memset(filter->src_ipaddr_mask, 0xff, 16);
3281                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3282                 filter->ethertype = 0x86dd;
3283                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3284                 break;
3285         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3286                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3287                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3288                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3289                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3290                 filter->dst_port_mask = 0xffff;
3291                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3292                 filter->src_port_mask = 0xffff;
3293                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3294                 filter->ip_addr_type =
3295                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3296                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3297                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3298                 rte_memcpy(filter->src_ipaddr,
3299                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3300                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3301                 rte_memcpy(filter->dst_ipaddr,
3302                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3303                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3304                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3305                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3306                 memset(filter->src_ipaddr_mask, 0xff, 16);
3307                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3308                 filter->ethertype = 0x86dd;
3309                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3310                 break;
3311         case RTE_ETH_FLOW_L2_PAYLOAD:
3312                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3313                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3314                 break;
3315         case RTE_ETH_FLOW_VXLAN:
3316                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3317                         return -EINVAL;
3318                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3319                 filter->tunnel_type =
3320                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3321                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3322                 break;
3323         case RTE_ETH_FLOW_NVGRE:
3324                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3325                         return -EINVAL;
3326                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3327                 filter->tunnel_type =
3328                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3329                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3330                 break;
3331         case RTE_ETH_FLOW_UNKNOWN:
3332         case RTE_ETH_FLOW_RAW:
3333         case RTE_ETH_FLOW_FRAG_IPV4:
3334         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3335         case RTE_ETH_FLOW_FRAG_IPV6:
3336         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3337         case RTE_ETH_FLOW_IPV6_EX:
3338         case RTE_ETH_FLOW_IPV6_TCP_EX:
3339         case RTE_ETH_FLOW_IPV6_UDP_EX:
3340         case RTE_ETH_FLOW_GENEVE:
3341                 /* FALLTHROUGH */
3342         default:
3343                 return -EINVAL;
3344         }
3345
3346         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3347         vnic = &bp->vnic_info[fdir->action.rx_queue];
3348         if (vnic == NULL) {
3349                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3350                 return -EINVAL;
3351         }
3352
3353         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3354                 rte_memcpy(filter->dst_macaddr,
3355                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3356                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3357         }
3358
3359         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3360                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3361                 filter1 = STAILQ_FIRST(&vnic0->filter);
3362                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3363         } else {
3364                 filter->dst_id = vnic->fw_vnic_id;
3365                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3366                         if (filter->dst_macaddr[i] == 0x00)
3367                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3368                         else
3369                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3370         }
3371
3372         if (filter1 == NULL)
3373                 return -EINVAL;
3374
3375         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3376         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3377
3378         filter->enables = en;
3379
3380         return 0;
3381 }
3382
3383 static struct bnxt_filter_info *
3384 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3385                 struct bnxt_vnic_info **mvnic)
3386 {
3387         struct bnxt_filter_info *mf = NULL;
3388         int i;
3389
3390         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3391                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3392
3393                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3394                         if (mf->filter_type == nf->filter_type &&
3395                             mf->flags == nf->flags &&
3396                             mf->src_port == nf->src_port &&
3397                             mf->src_port_mask == nf->src_port_mask &&
3398                             mf->dst_port == nf->dst_port &&
3399                             mf->dst_port_mask == nf->dst_port_mask &&
3400                             mf->ip_protocol == nf->ip_protocol &&
3401                             mf->ip_addr_type == nf->ip_addr_type &&
3402                             mf->ethertype == nf->ethertype &&
3403                             mf->vni == nf->vni &&
3404                             mf->tunnel_type == nf->tunnel_type &&
3405                             mf->l2_ovlan == nf->l2_ovlan &&
3406                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3407                             mf->l2_ivlan == nf->l2_ivlan &&
3408                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3409                             !memcmp(mf->l2_addr, nf->l2_addr,
3410                                     RTE_ETHER_ADDR_LEN) &&
3411                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3412                                     RTE_ETHER_ADDR_LEN) &&
3413                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3414                                     RTE_ETHER_ADDR_LEN) &&
3415                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3416                                     RTE_ETHER_ADDR_LEN) &&
3417                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3418                                     sizeof(nf->src_ipaddr)) &&
3419                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3420                                     sizeof(nf->src_ipaddr_mask)) &&
3421                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3422                                     sizeof(nf->dst_ipaddr)) &&
3423                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3424                                     sizeof(nf->dst_ipaddr_mask))) {
3425                                 if (mvnic)
3426                                         *mvnic = vnic;
3427                                 return mf;
3428                         }
3429                 }
3430         }
3431         return NULL;
3432 }
3433
3434 static int
3435 bnxt_fdir_filter(struct rte_eth_dev *dev,
3436                  enum rte_filter_op filter_op,
3437                  void *arg)
3438 {
3439         struct bnxt *bp = dev->data->dev_private;
3440         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3441         struct bnxt_filter_info *filter, *match;
3442         struct bnxt_vnic_info *vnic, *mvnic;
3443         int ret = 0, i;
3444
3445         if (filter_op == RTE_ETH_FILTER_NOP)
3446                 return 0;
3447
3448         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3449                 return -EINVAL;
3450
3451         switch (filter_op) {
3452         case RTE_ETH_FILTER_ADD:
3453         case RTE_ETH_FILTER_DELETE:
3454                 /* FALLTHROUGH */
3455                 filter = bnxt_get_unused_filter(bp);
3456                 if (filter == NULL) {
3457                         PMD_DRV_LOG(ERR,
3458                                 "Not enough resources for a new flow.\n");
3459                         return -ENOMEM;
3460                 }
3461
3462                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3463                 if (ret != 0)
3464                         goto free_filter;
3465                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3466
3467                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3468                         vnic = &bp->vnic_info[0];
3469                 else
3470                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3471
3472                 match = bnxt_match_fdir(bp, filter, &mvnic);
3473                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3474                         if (match->dst_id == vnic->fw_vnic_id) {
3475                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3476                                 ret = -EEXIST;
3477                                 goto free_filter;
3478                         } else {
3479                                 match->dst_id = vnic->fw_vnic_id;
3480                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3481                                                                   match->dst_id,
3482                                                                   match);
3483                                 STAILQ_REMOVE(&mvnic->filter, match,
3484                                               bnxt_filter_info, next);
3485                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3486                                 PMD_DRV_LOG(ERR,
3487                                         "Filter with matching pattern exist\n");
3488                                 PMD_DRV_LOG(ERR,
3489                                         "Updated it to new destination q\n");
3490                                 goto free_filter;
3491                         }
3492                 }
3493                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3494                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3495                         ret = -ENOENT;
3496                         goto free_filter;
3497                 }
3498
3499                 if (filter_op == RTE_ETH_FILTER_ADD) {
3500                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3501                                                           filter->dst_id,
3502                                                           filter);
3503                         if (ret)
3504                                 goto free_filter;
3505                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3506                 } else {
3507                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3508                         STAILQ_REMOVE(&vnic->filter, match,
3509                                       bnxt_filter_info, next);
3510                         bnxt_free_filter(bp, match);
3511                         bnxt_free_filter(bp, filter);
3512                 }
3513                 break;
3514         case RTE_ETH_FILTER_FLUSH:
3515                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3516                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3517
3518                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3519                                 if (filter->filter_type ==
3520                                     HWRM_CFA_NTUPLE_FILTER) {
3521                                         ret =
3522                                         bnxt_hwrm_clear_ntuple_filter(bp,
3523                                                                       filter);
3524                                         STAILQ_REMOVE(&vnic->filter, filter,
3525                                                       bnxt_filter_info, next);
3526                                 }
3527                         }
3528                 }
3529                 return ret;
3530         case RTE_ETH_FILTER_UPDATE:
3531         case RTE_ETH_FILTER_STATS:
3532         case RTE_ETH_FILTER_INFO:
3533                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3534                 break;
3535         default:
3536                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3537                 ret = -EINVAL;
3538                 break;
3539         }
3540         return ret;
3541
3542 free_filter:
3543         bnxt_free_filter(bp, filter);
3544         return ret;
3545 }
3546
3547 static int
3548 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3549                     enum rte_filter_type filter_type,
3550                     enum rte_filter_op filter_op, void *arg)
3551 {
3552         struct bnxt *bp = dev->data->dev_private;
3553         int ret = 0;
3554
3555         ret = is_bnxt_in_error(dev->data->dev_private);
3556         if (ret)
3557                 return ret;
3558
3559         switch (filter_type) {
3560         case RTE_ETH_FILTER_TUNNEL:
3561                 PMD_DRV_LOG(ERR,
3562                         "filter type: %d: To be implemented\n", filter_type);
3563                 break;
3564         case RTE_ETH_FILTER_FDIR:
3565                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3566                 break;
3567         case RTE_ETH_FILTER_NTUPLE:
3568                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3569                 break;
3570         case RTE_ETH_FILTER_ETHERTYPE:
3571                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3572                 break;
3573         case RTE_ETH_FILTER_GENERIC:
3574                 if (filter_op != RTE_ETH_FILTER_GET)
3575                         return -EINVAL;
3576                 if (bp->truflow)
3577                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3578                 else
3579                         *(const void **)arg = &bnxt_flow_ops;
3580                 break;
3581         default:
3582                 PMD_DRV_LOG(ERR,
3583                         "Filter type (%d) not supported", filter_type);
3584                 ret = -EINVAL;
3585                 break;
3586         }
3587         return ret;
3588 }
3589
3590 static const uint32_t *
3591 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3592 {
3593         static const uint32_t ptypes[] = {
3594                 RTE_PTYPE_L2_ETHER_VLAN,
3595                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3596                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3597                 RTE_PTYPE_L4_ICMP,
3598                 RTE_PTYPE_L4_TCP,
3599                 RTE_PTYPE_L4_UDP,
3600                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3601                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3602                 RTE_PTYPE_INNER_L4_ICMP,
3603                 RTE_PTYPE_INNER_L4_TCP,
3604                 RTE_PTYPE_INNER_L4_UDP,
3605                 RTE_PTYPE_UNKNOWN
3606         };
3607
3608         if (!dev->rx_pkt_burst)
3609                 return NULL;
3610
3611         return ptypes;
3612 }
3613
3614 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3615                          int reg_win)
3616 {
3617         uint32_t reg_base = *reg_arr & 0xfffff000;
3618         uint32_t win_off;
3619         int i;
3620
3621         for (i = 0; i < count; i++) {
3622                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3623                         return -ERANGE;
3624         }
3625         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3626         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3627         return 0;
3628 }
3629
3630 static int bnxt_map_ptp_regs(struct bnxt *bp)
3631 {
3632         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3633         uint32_t *reg_arr;
3634         int rc, i;
3635
3636         reg_arr = ptp->rx_regs;
3637         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3638         if (rc)
3639                 return rc;
3640
3641         reg_arr = ptp->tx_regs;
3642         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3643         if (rc)
3644                 return rc;
3645
3646         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3647                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3648
3649         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3650                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3651
3652         return 0;
3653 }
3654
3655 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3656 {
3657         rte_write32(0, (uint8_t *)bp->bar0 +
3658                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3659         rte_write32(0, (uint8_t *)bp->bar0 +
3660                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3661 }
3662
3663 static uint64_t bnxt_cc_read(struct bnxt *bp)
3664 {
3665         uint64_t ns;
3666
3667         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3668                               BNXT_GRCPF_REG_SYNC_TIME));
3669         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3670                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3671         return ns;
3672 }
3673
3674 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3675 {
3676         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3677         uint32_t fifo;
3678
3679         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3680                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3681         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3682                 return -EAGAIN;
3683
3684         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3685                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3686         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3687                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3688         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3689                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3690
3691         return 0;
3692 }
3693
3694 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3695 {
3696         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3697         struct bnxt_pf_info *pf = &bp->pf;
3698         uint16_t port_id;
3699         uint32_t fifo;
3700
3701         if (!ptp)
3702                 return -ENODEV;
3703
3704         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3705                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3706         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3707                 return -EAGAIN;
3708
3709         port_id = pf->port_id;
3710         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3711                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3712
3713         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3714                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3715         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3716 /*              bnxt_clr_rx_ts(bp);       TBD  */
3717                 return -EBUSY;
3718         }
3719
3720         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3721                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3722         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3723                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3724
3725         return 0;
3726 }
3727
3728 static int
3729 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3730 {
3731         uint64_t ns;
3732         struct bnxt *bp = dev->data->dev_private;
3733         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3734
3735         if (!ptp)
3736                 return 0;
3737
3738         ns = rte_timespec_to_ns(ts);
3739         /* Set the timecounters to a new value. */
3740         ptp->tc.nsec = ns;
3741
3742         return 0;
3743 }
3744
3745 static int
3746 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3747 {
3748         struct bnxt *bp = dev->data->dev_private;
3749         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3750         uint64_t ns, systime_cycles = 0;
3751         int rc = 0;
3752
3753         if (!ptp)
3754                 return 0;
3755
3756         if (BNXT_CHIP_THOR(bp))
3757                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3758                                              &systime_cycles);
3759         else
3760                 systime_cycles = bnxt_cc_read(bp);
3761
3762         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3763         *ts = rte_ns_to_timespec(ns);
3764
3765         return rc;
3766 }
3767 static int
3768 bnxt_timesync_enable(struct rte_eth_dev *dev)
3769 {
3770         struct bnxt *bp = dev->data->dev_private;
3771         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3772         uint32_t shift = 0;
3773         int rc;
3774
3775         if (!ptp)
3776                 return 0;
3777
3778         ptp->rx_filter = 1;
3779         ptp->tx_tstamp_en = 1;
3780         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3781
3782         rc = bnxt_hwrm_ptp_cfg(bp);
3783         if (rc)
3784                 return rc;
3785
3786         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3787         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3788         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3789
3790         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3791         ptp->tc.cc_shift = shift;
3792         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3793
3794         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3795         ptp->rx_tstamp_tc.cc_shift = shift;
3796         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3797
3798         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3799         ptp->tx_tstamp_tc.cc_shift = shift;
3800         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3801
3802         if (!BNXT_CHIP_THOR(bp))
3803                 bnxt_map_ptp_regs(bp);
3804
3805         return 0;
3806 }
3807
3808 static int
3809 bnxt_timesync_disable(struct rte_eth_dev *dev)
3810 {
3811         struct bnxt *bp = dev->data->dev_private;
3812         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3813
3814         if (!ptp)
3815                 return 0;
3816
3817         ptp->rx_filter = 0;
3818         ptp->tx_tstamp_en = 0;
3819         ptp->rxctl = 0;
3820
3821         bnxt_hwrm_ptp_cfg(bp);
3822
3823         if (!BNXT_CHIP_THOR(bp))
3824                 bnxt_unmap_ptp_regs(bp);
3825
3826         return 0;
3827 }
3828
3829 static int
3830 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3831                                  struct timespec *timestamp,
3832                                  uint32_t flags __rte_unused)
3833 {
3834         struct bnxt *bp = dev->data->dev_private;
3835         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3836         uint64_t rx_tstamp_cycles = 0;
3837         uint64_t ns;
3838
3839         if (!ptp)
3840                 return 0;
3841
3842         if (BNXT_CHIP_THOR(bp))
3843                 rx_tstamp_cycles = ptp->rx_timestamp;
3844         else
3845                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3846
3847         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3848         *timestamp = rte_ns_to_timespec(ns);
3849         return  0;
3850 }
3851
3852 static int
3853 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3854                                  struct timespec *timestamp)
3855 {
3856         struct bnxt *bp = dev->data->dev_private;
3857         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3858         uint64_t tx_tstamp_cycles = 0;
3859         uint64_t ns;
3860         int rc = 0;
3861
3862         if (!ptp)
3863                 return 0;
3864
3865         if (BNXT_CHIP_THOR(bp))
3866                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3867                                              &tx_tstamp_cycles);
3868         else
3869                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3870
3871         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3872         *timestamp = rte_ns_to_timespec(ns);
3873
3874         return rc;
3875 }
3876
3877 static int
3878 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3879 {
3880         struct bnxt *bp = dev->data->dev_private;
3881         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3882
3883         if (!ptp)
3884                 return 0;
3885
3886         ptp->tc.nsec += delta;
3887
3888         return 0;
3889 }
3890
3891 static int
3892 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3893 {
3894         struct bnxt *bp = dev->data->dev_private;
3895         int rc;
3896         uint32_t dir_entries;
3897         uint32_t entry_length;
3898
3899         rc = is_bnxt_in_error(bp);
3900         if (rc)
3901                 return rc;
3902
3903         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3904                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3905                     bp->pdev->addr.devid, bp->pdev->addr.function);
3906
3907         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3908         if (rc != 0)
3909                 return rc;
3910
3911         return dir_entries * entry_length;
3912 }
3913
3914 static int
3915 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3916                 struct rte_dev_eeprom_info *in_eeprom)
3917 {
3918         struct bnxt *bp = dev->data->dev_private;
3919         uint32_t index;
3920         uint32_t offset;
3921         int rc;
3922
3923         rc = is_bnxt_in_error(bp);
3924         if (rc)
3925                 return rc;
3926
3927         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3928                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3929                     bp->pdev->addr.devid, bp->pdev->addr.function,
3930                     in_eeprom->offset, in_eeprom->length);
3931
3932         if (in_eeprom->offset == 0) /* special offset value to get directory */
3933                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3934                                                 in_eeprom->data);
3935
3936         index = in_eeprom->offset >> 24;
3937         offset = in_eeprom->offset & 0xffffff;
3938
3939         if (index != 0)
3940                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3941                                            in_eeprom->length, in_eeprom->data);
3942
3943         return 0;
3944 }
3945
3946 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3947 {
3948         switch (dir_type) {
3949         case BNX_DIR_TYPE_CHIMP_PATCH:
3950         case BNX_DIR_TYPE_BOOTCODE:
3951         case BNX_DIR_TYPE_BOOTCODE_2:
3952         case BNX_DIR_TYPE_APE_FW:
3953         case BNX_DIR_TYPE_APE_PATCH:
3954         case BNX_DIR_TYPE_KONG_FW:
3955         case BNX_DIR_TYPE_KONG_PATCH:
3956         case BNX_DIR_TYPE_BONO_FW:
3957         case BNX_DIR_TYPE_BONO_PATCH:
3958                 /* FALLTHROUGH */
3959                 return true;
3960         }
3961
3962         return false;
3963 }
3964
3965 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3966 {
3967         switch (dir_type) {
3968         case BNX_DIR_TYPE_AVS:
3969         case BNX_DIR_TYPE_EXP_ROM_MBA:
3970         case BNX_DIR_TYPE_PCIE:
3971         case BNX_DIR_TYPE_TSCF_UCODE:
3972         case BNX_DIR_TYPE_EXT_PHY:
3973         case BNX_DIR_TYPE_CCM:
3974         case BNX_DIR_TYPE_ISCSI_BOOT:
3975         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3976         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3977                 /* FALLTHROUGH */
3978                 return true;
3979         }
3980
3981         return false;
3982 }
3983
3984 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3985 {
3986         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3987                 bnxt_dir_type_is_other_exec_format(dir_type);
3988 }
3989
3990 static int
3991 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3992                 struct rte_dev_eeprom_info *in_eeprom)
3993 {
3994         struct bnxt *bp = dev->data->dev_private;
3995         uint8_t index, dir_op;
3996         uint16_t type, ext, ordinal, attr;
3997         int rc;
3998
3999         rc = is_bnxt_in_error(bp);
4000         if (rc)
4001                 return rc;
4002
4003         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4004                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4005                     bp->pdev->addr.devid, bp->pdev->addr.function,
4006                     in_eeprom->offset, in_eeprom->length);
4007
4008         if (!BNXT_PF(bp)) {
4009                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4010                 return -EINVAL;
4011         }
4012
4013         type = in_eeprom->magic >> 16;
4014
4015         if (type == 0xffff) { /* special value for directory operations */
4016                 index = in_eeprom->magic & 0xff;
4017                 dir_op = in_eeprom->magic >> 8;
4018                 if (index == 0)
4019                         return -EINVAL;
4020                 switch (dir_op) {
4021                 case 0x0e: /* erase */
4022                         if (in_eeprom->offset != ~in_eeprom->magic)
4023                                 return -EINVAL;
4024                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4025                 default:
4026                         return -EINVAL;
4027                 }
4028         }
4029
4030         /* Create or re-write an NVM item: */
4031         if (bnxt_dir_type_is_executable(type) == true)
4032                 return -EOPNOTSUPP;
4033         ext = in_eeprom->magic & 0xffff;
4034         ordinal = in_eeprom->offset >> 16;
4035         attr = in_eeprom->offset & 0xffff;
4036
4037         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4038                                      in_eeprom->data, in_eeprom->length);
4039 }
4040
4041 /*
4042  * Initialization
4043  */
4044
4045 static const struct eth_dev_ops bnxt_dev_ops = {
4046         .dev_infos_get = bnxt_dev_info_get_op,
4047         .dev_close = bnxt_dev_close_op,
4048         .dev_configure = bnxt_dev_configure_op,
4049         .dev_start = bnxt_dev_start_op,
4050         .dev_stop = bnxt_dev_stop_op,
4051         .dev_set_link_up = bnxt_dev_set_link_up_op,
4052         .dev_set_link_down = bnxt_dev_set_link_down_op,
4053         .stats_get = bnxt_stats_get_op,
4054         .stats_reset = bnxt_stats_reset_op,
4055         .rx_queue_setup = bnxt_rx_queue_setup_op,
4056         .rx_queue_release = bnxt_rx_queue_release_op,
4057         .tx_queue_setup = bnxt_tx_queue_setup_op,
4058         .tx_queue_release = bnxt_tx_queue_release_op,
4059         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4060         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4061         .reta_update = bnxt_reta_update_op,
4062         .reta_query = bnxt_reta_query_op,
4063         .rss_hash_update = bnxt_rss_hash_update_op,
4064         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4065         .link_update = bnxt_link_update_op,
4066         .promiscuous_enable = bnxt_promiscuous_enable_op,
4067         .promiscuous_disable = bnxt_promiscuous_disable_op,
4068         .allmulticast_enable = bnxt_allmulticast_enable_op,
4069         .allmulticast_disable = bnxt_allmulticast_disable_op,
4070         .mac_addr_add = bnxt_mac_addr_add_op,
4071         .mac_addr_remove = bnxt_mac_addr_remove_op,
4072         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4073         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4074         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4075         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4076         .vlan_filter_set = bnxt_vlan_filter_set_op,
4077         .vlan_offload_set = bnxt_vlan_offload_set_op,
4078         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4079         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4080         .mtu_set = bnxt_mtu_set_op,
4081         .mac_addr_set = bnxt_set_default_mac_addr_op,
4082         .xstats_get = bnxt_dev_xstats_get_op,
4083         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4084         .xstats_reset = bnxt_dev_xstats_reset_op,
4085         .fw_version_get = bnxt_fw_version_get,
4086         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4087         .rxq_info_get = bnxt_rxq_info_get_op,
4088         .txq_info_get = bnxt_txq_info_get_op,
4089         .dev_led_on = bnxt_dev_led_on_op,
4090         .dev_led_off = bnxt_dev_led_off_op,
4091         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4092         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4093         .rx_queue_count = bnxt_rx_queue_count_op,
4094         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4095         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4096         .rx_queue_start = bnxt_rx_queue_start,
4097         .rx_queue_stop = bnxt_rx_queue_stop,
4098         .tx_queue_start = bnxt_tx_queue_start,
4099         .tx_queue_stop = bnxt_tx_queue_stop,
4100         .filter_ctrl = bnxt_filter_ctrl_op,
4101         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4102         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4103         .get_eeprom           = bnxt_get_eeprom_op,
4104         .set_eeprom           = bnxt_set_eeprom_op,
4105         .timesync_enable      = bnxt_timesync_enable,
4106         .timesync_disable     = bnxt_timesync_disable,
4107         .timesync_read_time   = bnxt_timesync_read_time,
4108         .timesync_write_time   = bnxt_timesync_write_time,
4109         .timesync_adjust_time = bnxt_timesync_adjust_time,
4110         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4111         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4112 };
4113
4114 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4115 {
4116         uint32_t offset;
4117
4118         /* Only pre-map the reset GRC registers using window 3 */
4119         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4120                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4121
4122         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4123
4124         return offset;
4125 }
4126
4127 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4128 {
4129         struct bnxt_error_recovery_info *info = bp->recovery_info;
4130         uint32_t reg_base = 0xffffffff;
4131         int i;
4132
4133         /* Only pre-map the monitoring GRC registers using window 2 */
4134         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4135                 uint32_t reg = info->status_regs[i];
4136
4137                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4138                         continue;
4139
4140                 if (reg_base == 0xffffffff)
4141                         reg_base = reg & 0xfffff000;
4142                 if ((reg & 0xfffff000) != reg_base)
4143                         return -ERANGE;
4144
4145                 /* Use mask 0xffc as the Lower 2 bits indicates
4146                  * address space location
4147                  */
4148                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4149                                                 (reg & 0xffc);
4150         }
4151
4152         if (reg_base == 0xffffffff)
4153                 return 0;
4154
4155         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4156                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4157
4158         return 0;
4159 }
4160
4161 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4162 {
4163         struct bnxt_error_recovery_info *info = bp->recovery_info;
4164         uint32_t delay = info->delay_after_reset[index];
4165         uint32_t val = info->reset_reg_val[index];
4166         uint32_t reg = info->reset_reg[index];
4167         uint32_t type, offset;
4168
4169         type = BNXT_FW_STATUS_REG_TYPE(reg);
4170         offset = BNXT_FW_STATUS_REG_OFF(reg);
4171
4172         switch (type) {
4173         case BNXT_FW_STATUS_REG_TYPE_CFG:
4174                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4175                 break;
4176         case BNXT_FW_STATUS_REG_TYPE_GRC:
4177                 offset = bnxt_map_reset_regs(bp, offset);
4178                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4179                 break;
4180         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4181                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4182                 break;
4183         }
4184         /* wait on a specific interval of time until core reset is complete */
4185         if (delay)
4186                 rte_delay_ms(delay);
4187 }
4188
4189 static void bnxt_dev_cleanup(struct bnxt *bp)
4190 {
4191         bnxt_set_hwrm_link_config(bp, false);
4192         bp->link_info.link_up = 0;
4193         if (bp->eth_dev->data->dev_started)
4194                 bnxt_dev_stop_op(bp->eth_dev);
4195
4196         bnxt_uninit_resources(bp, true);
4197 }
4198
4199 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4200 {
4201         struct rte_eth_dev *dev = bp->eth_dev;
4202         struct rte_vlan_filter_conf *vfc;
4203         int vidx, vbit, rc;
4204         uint16_t vlan_id;
4205
4206         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4207                 vfc = &dev->data->vlan_filter_conf;
4208                 vidx = vlan_id / 64;
4209                 vbit = vlan_id % 64;
4210
4211                 /* Each bit corresponds to a VLAN id */
4212                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4213                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4214                         if (rc)
4215                                 return rc;
4216                 }
4217         }
4218
4219         return 0;
4220 }
4221
4222 static int bnxt_restore_mac_filters(struct bnxt *bp)
4223 {
4224         struct rte_eth_dev *dev = bp->eth_dev;
4225         struct rte_eth_dev_info dev_info;
4226         struct rte_ether_addr *addr;
4227         uint64_t pool_mask;
4228         uint32_t pool = 0;
4229         uint16_t i;
4230         int rc;
4231
4232         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4233                 return 0;
4234
4235         rc = bnxt_dev_info_get_op(dev, &dev_info);
4236         if (rc)
4237                 return rc;
4238
4239         /* replay MAC address configuration */
4240         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4241                 addr = &dev->data->mac_addrs[i];
4242
4243                 /* skip zero address */
4244                 if (rte_is_zero_ether_addr(addr))
4245                         continue;
4246
4247                 pool = 0;
4248                 pool_mask = dev->data->mac_pool_sel[i];
4249
4250                 do {
4251                         if (pool_mask & 1ULL) {
4252                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4253                                 if (rc)
4254                                         return rc;
4255                         }
4256                         pool_mask >>= 1;
4257                         pool++;
4258                 } while (pool_mask);
4259         }
4260
4261         return 0;
4262 }
4263
4264 static int bnxt_restore_filters(struct bnxt *bp)
4265 {
4266         struct rte_eth_dev *dev = bp->eth_dev;
4267         int ret = 0;
4268
4269         if (dev->data->all_multicast) {
4270                 ret = bnxt_allmulticast_enable_op(dev);
4271                 if (ret)
4272                         return ret;
4273         }
4274         if (dev->data->promiscuous) {
4275                 ret = bnxt_promiscuous_enable_op(dev);
4276                 if (ret)
4277                         return ret;
4278         }
4279
4280         ret = bnxt_restore_mac_filters(bp);
4281         if (ret)
4282                 return ret;
4283
4284         ret = bnxt_restore_vlan_filters(bp);
4285         /* TODO restore other filters as well */
4286         return ret;
4287 }
4288
4289 static void bnxt_dev_recover(void *arg)
4290 {
4291         struct bnxt *bp = arg;
4292         int timeout = bp->fw_reset_max_msecs;
4293         int rc = 0;
4294
4295         /* Clear Error flag so that device re-init should happen */
4296         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4297
4298         do {
4299                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4300                 if (rc == 0)
4301                         break;
4302                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4303                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4304         } while (rc && timeout);
4305
4306         if (rc) {
4307                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4308                 goto err;
4309         }
4310
4311         rc = bnxt_init_resources(bp, true);
4312         if (rc) {
4313                 PMD_DRV_LOG(ERR,
4314                             "Failed to initialize resources after reset\n");
4315                 goto err;
4316         }
4317         /* clear reset flag as the device is initialized now */
4318         bp->flags &= ~BNXT_FLAG_FW_RESET;
4319
4320         rc = bnxt_dev_start_op(bp->eth_dev);
4321         if (rc) {
4322                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4323                 goto err_start;
4324         }
4325
4326         rc = bnxt_restore_filters(bp);
4327         if (rc)
4328                 goto err_start;
4329
4330         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4331         return;
4332 err_start:
4333         bnxt_dev_stop_op(bp->eth_dev);
4334 err:
4335         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4336         bnxt_uninit_resources(bp, false);
4337         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4338 }
4339
4340 void bnxt_dev_reset_and_resume(void *arg)
4341 {
4342         struct bnxt *bp = arg;
4343         int rc;
4344
4345         bnxt_dev_cleanup(bp);
4346
4347         bnxt_wait_for_device_shutdown(bp);
4348
4349         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4350                                bnxt_dev_recover, (void *)bp);
4351         if (rc)
4352                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4353 }
4354
4355 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4356 {
4357         struct bnxt_error_recovery_info *info = bp->recovery_info;
4358         uint32_t reg = info->status_regs[index];
4359         uint32_t type, offset, val = 0;
4360
4361         type = BNXT_FW_STATUS_REG_TYPE(reg);
4362         offset = BNXT_FW_STATUS_REG_OFF(reg);
4363
4364         switch (type) {
4365         case BNXT_FW_STATUS_REG_TYPE_CFG:
4366                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4367                 break;
4368         case BNXT_FW_STATUS_REG_TYPE_GRC:
4369                 offset = info->mapped_status_regs[index];
4370                 /* FALLTHROUGH */
4371         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4372                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4373                                        offset));
4374                 break;
4375         }
4376
4377         return val;
4378 }
4379
4380 static int bnxt_fw_reset_all(struct bnxt *bp)
4381 {
4382         struct bnxt_error_recovery_info *info = bp->recovery_info;
4383         uint32_t i;
4384         int rc = 0;
4385
4386         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4387                 /* Reset through master function driver */
4388                 for (i = 0; i < info->reg_array_cnt; i++)
4389                         bnxt_write_fw_reset_reg(bp, i);
4390                 /* Wait for time specified by FW after triggering reset */
4391                 rte_delay_ms(info->master_func_wait_period_after_reset);
4392         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4393                 /* Reset with the help of Kong processor */
4394                 rc = bnxt_hwrm_fw_reset(bp);
4395                 if (rc)
4396                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4397         }
4398
4399         return rc;
4400 }
4401
4402 static void bnxt_fw_reset_cb(void *arg)
4403 {
4404         struct bnxt *bp = arg;
4405         struct bnxt_error_recovery_info *info = bp->recovery_info;
4406         int rc = 0;
4407
4408         /* Only Master function can do FW reset */
4409         if (bnxt_is_master_func(bp) &&
4410             bnxt_is_recovery_enabled(bp)) {
4411                 rc = bnxt_fw_reset_all(bp);
4412                 if (rc) {
4413                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4414                         return;
4415                 }
4416         }
4417
4418         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4419          * EXCEPTION_FATAL_ASYNC event to all the functions
4420          * (including MASTER FUNC). After receiving this Async, all the active
4421          * drivers should treat this case as FW initiated recovery
4422          */
4423         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4424                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4425                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4426
4427                 /* To recover from error */
4428                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4429                                   (void *)bp);
4430         }
4431 }
4432
4433 /* Driver should poll FW heartbeat, reset_counter with the frequency
4434  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4435  * When the driver detects heartbeat stop or change in reset_counter,
4436  * it has to trigger a reset to recover from the error condition.
4437  * A “master PF” is the function who will have the privilege to
4438  * initiate the chimp reset. The master PF will be elected by the
4439  * firmware and will be notified through async message.
4440  */
4441 static void bnxt_check_fw_health(void *arg)
4442 {
4443         struct bnxt *bp = arg;
4444         struct bnxt_error_recovery_info *info = bp->recovery_info;
4445         uint32_t val = 0, wait_msec;
4446
4447         if (!info || !bnxt_is_recovery_enabled(bp) ||
4448             is_bnxt_in_error(bp))
4449                 return;
4450
4451         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4452         if (val == info->last_heart_beat)
4453                 goto reset;
4454
4455         info->last_heart_beat = val;
4456
4457         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4458         if (val != info->last_reset_counter)
4459                 goto reset;
4460
4461         info->last_reset_counter = val;
4462
4463         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4464                           bnxt_check_fw_health, (void *)bp);
4465
4466         return;
4467 reset:
4468         /* Stop DMA to/from device */
4469         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4470         bp->flags |= BNXT_FLAG_FW_RESET;
4471
4472         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4473
4474         if (bnxt_is_master_func(bp))
4475                 wait_msec = info->master_func_wait_period;
4476         else
4477                 wait_msec = info->normal_func_wait_period;
4478
4479         rte_eal_alarm_set(US_PER_MS * wait_msec,
4480                           bnxt_fw_reset_cb, (void *)bp);
4481 }
4482
4483 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4484 {
4485         uint32_t polling_freq;
4486
4487         if (!bnxt_is_recovery_enabled(bp))
4488                 return;
4489
4490         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4491                 return;
4492
4493         polling_freq = bp->recovery_info->driver_polling_freq;
4494
4495         rte_eal_alarm_set(US_PER_MS * polling_freq,
4496                           bnxt_check_fw_health, (void *)bp);
4497         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4498 }
4499
4500 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4501 {
4502         if (!bnxt_is_recovery_enabled(bp))
4503                 return;
4504
4505         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4506         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4507 }
4508
4509 static bool bnxt_vf_pciid(uint16_t device_id)
4510 {
4511         switch (device_id) {
4512         case BROADCOM_DEV_ID_57304_VF:
4513         case BROADCOM_DEV_ID_57406_VF:
4514         case BROADCOM_DEV_ID_5731X_VF:
4515         case BROADCOM_DEV_ID_5741X_VF:
4516         case BROADCOM_DEV_ID_57414_VF:
4517         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4518         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4519         case BROADCOM_DEV_ID_58802_VF:
4520         case BROADCOM_DEV_ID_57500_VF1:
4521         case BROADCOM_DEV_ID_57500_VF2:
4522                 /* FALLTHROUGH */
4523                 return true;
4524         default:
4525                 return false;
4526         }
4527 }
4528
4529 static bool bnxt_thor_device(uint16_t device_id)
4530 {
4531         switch (device_id) {
4532         case BROADCOM_DEV_ID_57508:
4533         case BROADCOM_DEV_ID_57504:
4534         case BROADCOM_DEV_ID_57502:
4535         case BROADCOM_DEV_ID_57508_MF1:
4536         case BROADCOM_DEV_ID_57504_MF1:
4537         case BROADCOM_DEV_ID_57502_MF1:
4538         case BROADCOM_DEV_ID_57508_MF2:
4539         case BROADCOM_DEV_ID_57504_MF2:
4540         case BROADCOM_DEV_ID_57502_MF2:
4541         case BROADCOM_DEV_ID_57500_VF1:
4542         case BROADCOM_DEV_ID_57500_VF2:
4543                 /* FALLTHROUGH */
4544                 return true;
4545         default:
4546                 return false;
4547         }
4548 }
4549
4550 bool bnxt_stratus_device(struct bnxt *bp)
4551 {
4552         uint16_t device_id = bp->pdev->id.device_id;
4553
4554         switch (device_id) {
4555         case BROADCOM_DEV_ID_STRATUS_NIC:
4556         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4557         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4558                 /* FALLTHROUGH */
4559                 return true;
4560         default:
4561                 return false;
4562         }
4563 }
4564
4565 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4566 {
4567         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4568         struct bnxt *bp = eth_dev->data->dev_private;
4569
4570         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4571         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4572         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4573         if (!bp->bar0 || !bp->doorbell_base) {
4574                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4575                 return -ENODEV;
4576         }
4577
4578         bp->eth_dev = eth_dev;
4579         bp->pdev = pci_dev;
4580
4581         return 0;
4582 }
4583
4584 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4585                                   struct bnxt_ctx_pg_info *ctx_pg,
4586                                   uint32_t mem_size,
4587                                   const char *suffix,
4588                                   uint16_t idx)
4589 {
4590         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4591         const struct rte_memzone *mz = NULL;
4592         char mz_name[RTE_MEMZONE_NAMESIZE];
4593         rte_iova_t mz_phys_addr;
4594         uint64_t valid_bits = 0;
4595         uint32_t sz;
4596         int i;
4597
4598         if (!mem_size)
4599                 return 0;
4600
4601         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4602                          BNXT_PAGE_SIZE;
4603         rmem->page_size = BNXT_PAGE_SIZE;
4604         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4605         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4606         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4607
4608         valid_bits = PTU_PTE_VALID;
4609
4610         if (rmem->nr_pages > 1) {
4611                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4612                          "bnxt_ctx_pg_tbl%s_%x_%d",
4613                          suffix, idx, bp->eth_dev->data->port_id);
4614                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4615                 mz = rte_memzone_lookup(mz_name);
4616                 if (!mz) {
4617                         mz = rte_memzone_reserve_aligned(mz_name,
4618                                                 rmem->nr_pages * 8,
4619                                                 SOCKET_ID_ANY,
4620                                                 RTE_MEMZONE_2MB |
4621                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4622                                                 RTE_MEMZONE_IOVA_CONTIG,
4623                                                 BNXT_PAGE_SIZE);
4624                         if (mz == NULL)
4625                                 return -ENOMEM;
4626                 }
4627
4628                 memset(mz->addr, 0, mz->len);
4629                 mz_phys_addr = mz->iova;
4630
4631                 rmem->pg_tbl = mz->addr;
4632                 rmem->pg_tbl_map = mz_phys_addr;
4633                 rmem->pg_tbl_mz = mz;
4634         }
4635
4636         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4637                  suffix, idx, bp->eth_dev->data->port_id);
4638         mz = rte_memzone_lookup(mz_name);
4639         if (!mz) {
4640                 mz = rte_memzone_reserve_aligned(mz_name,
4641                                                  mem_size,
4642                                                  SOCKET_ID_ANY,
4643                                                  RTE_MEMZONE_1GB |
4644                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4645                                                  RTE_MEMZONE_IOVA_CONTIG,
4646                                                  BNXT_PAGE_SIZE);
4647                 if (mz == NULL)
4648                         return -ENOMEM;
4649         }
4650
4651         memset(mz->addr, 0, mz->len);
4652         mz_phys_addr = mz->iova;
4653
4654         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4655                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4656                 rmem->dma_arr[i] = mz_phys_addr + sz;
4657
4658                 if (rmem->nr_pages > 1) {
4659                         if (i == rmem->nr_pages - 2 &&
4660                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4661                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4662                         else if (i == rmem->nr_pages - 1 &&
4663                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4664                                 valid_bits |= PTU_PTE_LAST;
4665
4666                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4667                                                            valid_bits);
4668                 }
4669         }
4670
4671         rmem->mz = mz;
4672         if (rmem->vmem_size)
4673                 rmem->vmem = (void **)mz->addr;
4674         rmem->dma_arr[0] = mz_phys_addr;
4675         return 0;
4676 }
4677
4678 static void bnxt_free_ctx_mem(struct bnxt *bp)
4679 {
4680         int i;
4681
4682         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4683                 return;
4684
4685         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4686         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4687         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4688         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4689         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4690         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4691         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4692         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4693         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4694         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4695         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4696
4697         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4698                 if (bp->ctx->tqm_mem[i])
4699                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4700         }
4701
4702         rte_free(bp->ctx);
4703         bp->ctx = NULL;
4704 }
4705
4706 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4707
4708 #define min_t(type, x, y) ({                    \
4709         type __min1 = (x);                      \
4710         type __min2 = (y);                      \
4711         __min1 < __min2 ? __min1 : __min2; })
4712
4713 #define max_t(type, x, y) ({                    \
4714         type __max1 = (x);                      \
4715         type __max2 = (y);                      \
4716         __max1 > __max2 ? __max1 : __max2; })
4717
4718 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4719
4720 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4721 {
4722         struct bnxt_ctx_pg_info *ctx_pg;
4723         struct bnxt_ctx_mem_info *ctx;
4724         uint32_t mem_size, ena, entries;
4725         uint32_t entries_sp, min;
4726         int i, rc;
4727
4728         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4729         if (rc) {
4730                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4731                 return rc;
4732         }
4733         ctx = bp->ctx;
4734         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4735                 return 0;
4736
4737         ctx_pg = &ctx->qp_mem;
4738         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4739         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4740         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4741         if (rc)
4742                 return rc;
4743
4744         ctx_pg = &ctx->srq_mem;
4745         ctx_pg->entries = ctx->srq_max_l2_entries;
4746         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4747         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4748         if (rc)
4749                 return rc;
4750
4751         ctx_pg = &ctx->cq_mem;
4752         ctx_pg->entries = ctx->cq_max_l2_entries;
4753         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4754         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4755         if (rc)
4756                 return rc;
4757
4758         ctx_pg = &ctx->vnic_mem;
4759         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4760                 ctx->vnic_max_ring_table_entries;
4761         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4762         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4763         if (rc)
4764                 return rc;
4765
4766         ctx_pg = &ctx->stat_mem;
4767         ctx_pg->entries = ctx->stat_max_entries;
4768         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4769         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4770         if (rc)
4771                 return rc;
4772
4773         min = ctx->tqm_min_entries_per_ring;
4774
4775         entries_sp = ctx->qp_max_l2_entries +
4776                      ctx->vnic_max_vnic_entries +
4777                      2 * ctx->qp_min_qp1_entries + min;
4778         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4779
4780         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4781         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4782         entries = clamp_t(uint32_t, entries, min,
4783                           ctx->tqm_max_entries_per_ring);
4784         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4785                 ctx_pg = ctx->tqm_mem[i];
4786                 ctx_pg->entries = i ? entries : entries_sp;
4787                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4788                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4789                 if (rc)
4790                         return rc;
4791                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4792         }
4793
4794         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4795         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4796         if (rc)
4797                 PMD_DRV_LOG(ERR,
4798                             "Failed to configure context mem: rc = %d\n", rc);
4799         else
4800                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4801
4802         return rc;
4803 }
4804
4805 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4806 {
4807         struct rte_pci_device *pci_dev = bp->pdev;
4808         char mz_name[RTE_MEMZONE_NAMESIZE];
4809         const struct rte_memzone *mz = NULL;
4810         uint32_t total_alloc_len;
4811         rte_iova_t mz_phys_addr;
4812
4813         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4814                 return 0;
4815
4816         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4817                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4818                  pci_dev->addr.bus, pci_dev->addr.devid,
4819                  pci_dev->addr.function, "rx_port_stats");
4820         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4821         mz = rte_memzone_lookup(mz_name);
4822         total_alloc_len =
4823                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4824                                        sizeof(struct rx_port_stats_ext) + 512);
4825         if (!mz) {
4826                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4827                                          SOCKET_ID_ANY,
4828                                          RTE_MEMZONE_2MB |
4829                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4830                                          RTE_MEMZONE_IOVA_CONTIG);
4831                 if (mz == NULL)
4832                         return -ENOMEM;
4833         }
4834         memset(mz->addr, 0, mz->len);
4835         mz_phys_addr = mz->iova;
4836
4837         bp->rx_mem_zone = (const void *)mz;
4838         bp->hw_rx_port_stats = mz->addr;
4839         bp->hw_rx_port_stats_map = mz_phys_addr;
4840
4841         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4842                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4843                  pci_dev->addr.bus, pci_dev->addr.devid,
4844                  pci_dev->addr.function, "tx_port_stats");
4845         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4846         mz = rte_memzone_lookup(mz_name);
4847         total_alloc_len =
4848                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4849                                        sizeof(struct tx_port_stats_ext) + 512);
4850         if (!mz) {
4851                 mz = rte_memzone_reserve(mz_name,
4852                                          total_alloc_len,
4853                                          SOCKET_ID_ANY,
4854                                          RTE_MEMZONE_2MB |
4855                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4856                                          RTE_MEMZONE_IOVA_CONTIG);
4857                 if (mz == NULL)
4858                         return -ENOMEM;
4859         }
4860         memset(mz->addr, 0, mz->len);
4861         mz_phys_addr = mz->iova;
4862
4863         bp->tx_mem_zone = (const void *)mz;
4864         bp->hw_tx_port_stats = mz->addr;
4865         bp->hw_tx_port_stats_map = mz_phys_addr;
4866         bp->flags |= BNXT_FLAG_PORT_STATS;
4867
4868         /* Display extended statistics if FW supports it */
4869         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4870             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4871             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4872                 return 0;
4873
4874         bp->hw_rx_port_stats_ext = (void *)
4875                 ((uint8_t *)bp->hw_rx_port_stats +
4876                  sizeof(struct rx_port_stats));
4877         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4878                 sizeof(struct rx_port_stats);
4879         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4880
4881         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4882             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4883                 bp->hw_tx_port_stats_ext = (void *)
4884                         ((uint8_t *)bp->hw_tx_port_stats +
4885                          sizeof(struct tx_port_stats));
4886                 bp->hw_tx_port_stats_ext_map =
4887                         bp->hw_tx_port_stats_map +
4888                         sizeof(struct tx_port_stats);
4889                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4890         }
4891
4892         return 0;
4893 }
4894
4895 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4896 {
4897         struct bnxt *bp = eth_dev->data->dev_private;
4898         int rc = 0;
4899
4900         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4901                                                RTE_ETHER_ADDR_LEN *
4902                                                bp->max_l2_ctx,
4903                                                0);
4904         if (eth_dev->data->mac_addrs == NULL) {
4905                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4906                 return -ENOMEM;
4907         }
4908
4909         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4910                 if (BNXT_PF(bp))
4911                         return -EINVAL;
4912
4913                 /* Generate a random MAC address, if none was assigned by PF */
4914                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4915                 bnxt_eth_hw_addr_random(bp->mac_addr);
4916                 PMD_DRV_LOG(INFO,
4917                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4918                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4919                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4920
4921                 rc = bnxt_hwrm_set_mac(bp);
4922                 if (!rc)
4923                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4924                                RTE_ETHER_ADDR_LEN);
4925                 return rc;
4926         }
4927
4928         /* Copy the permanent MAC from the FUNC_QCAPS response */
4929         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4930         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4931
4932         return rc;
4933 }
4934
4935 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4936 {
4937         int rc = 0;
4938
4939         /* MAC is already configured in FW */
4940         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4941                 return 0;
4942
4943         /* Restore the old MAC configured */
4944         rc = bnxt_hwrm_set_mac(bp);
4945         if (rc)
4946                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4947
4948         return rc;
4949 }
4950
4951 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4952 {
4953         if (!BNXT_PF(bp))
4954                 return;
4955
4956 #define ALLOW_FUNC(x)   \
4957         { \
4958                 uint32_t arg = (x); \
4959                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4960                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4961         }
4962
4963         /* Forward all requests if firmware is new enough */
4964         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4965              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4966             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4967                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4968         } else {
4969                 PMD_DRV_LOG(WARNING,
4970                             "Firmware too old for VF mailbox functionality\n");
4971                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4972         }
4973
4974         /*
4975          * The following are used for driver cleanup. If we disallow these,
4976          * VF drivers can't clean up cleanly.
4977          */
4978         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4979         ALLOW_FUNC(HWRM_VNIC_FREE);
4980         ALLOW_FUNC(HWRM_RING_FREE);
4981         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4982         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4983         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4984         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4985         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4986         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4987 }
4988
4989 uint16_t
4990 bnxt_get_svif(uint16_t port_id, bool func_svif)
4991 {
4992         struct rte_eth_dev *eth_dev;
4993         struct bnxt *bp;
4994
4995         eth_dev = &rte_eth_devices[port_id];
4996         bp = eth_dev->data->dev_private;
4997
4998         return func_svif ? bp->func_svif : bp->port_svif;
4999 }
5000
5001 uint16_t
5002 bnxt_get_vnic_id(uint16_t port)
5003 {
5004         struct rte_eth_dev *eth_dev;
5005         struct bnxt_vnic_info *vnic;
5006         struct bnxt *bp;
5007
5008         eth_dev = &rte_eth_devices[port];
5009         bp = eth_dev->data->dev_private;
5010
5011         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5012
5013         return vnic->fw_vnic_id;
5014 }
5015
5016 uint16_t
5017 bnxt_get_fw_func_id(uint16_t port)
5018 {
5019         struct rte_eth_dev *eth_dev;
5020         struct bnxt *bp;
5021
5022         eth_dev = &rte_eth_devices[port];
5023         bp = eth_dev->data->dev_private;
5024
5025         return bp->fw_fid;
5026 }
5027
5028 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5029 {
5030         struct bnxt_error_recovery_info *info = bp->recovery_info;
5031
5032         if (info) {
5033                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5034                         memset(info, 0, sizeof(*info));
5035                 return;
5036         }
5037
5038         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5039                 return;
5040
5041         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5042                            sizeof(*info), 0);
5043         if (!info)
5044                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5045
5046         bp->recovery_info = info;
5047 }
5048
5049 static void bnxt_check_fw_status(struct bnxt *bp)
5050 {
5051         uint32_t fw_status;
5052
5053         if (!(bp->recovery_info &&
5054               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5055                 return;
5056
5057         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5058         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5059                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5060                             fw_status);
5061 }
5062
5063 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5064 {
5065         struct bnxt_error_recovery_info *info = bp->recovery_info;
5066         uint32_t status_loc;
5067         uint32_t sig_ver;
5068
5069         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5070                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5071         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5072                                    BNXT_GRCP_WINDOW_2_BASE +
5073                                    offsetof(struct hcomm_status,
5074                                             sig_ver)));
5075         /* If the signature is absent, then FW does not support this feature */
5076         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5077             HCOMM_STATUS_SIGNATURE_VAL)
5078                 return 0;
5079
5080         if (!info) {
5081                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5082                                    sizeof(*info), 0);
5083                 if (!info)
5084                         return -ENOMEM;
5085                 bp->recovery_info = info;
5086         } else {
5087                 memset(info, 0, sizeof(*info));
5088         }
5089
5090         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5091                                       BNXT_GRCP_WINDOW_2_BASE +
5092                                       offsetof(struct hcomm_status,
5093                                                fw_status_loc)));
5094
5095         /* Only pre-map the FW health status GRC register */
5096         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5097                 return 0;
5098
5099         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5100         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5101                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5102
5103         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5104                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5105
5106         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5107
5108         return 0;
5109 }
5110
5111 static int bnxt_init_fw(struct bnxt *bp)
5112 {
5113         uint16_t mtu;
5114         int rc = 0;
5115
5116         bp->fw_cap = 0;
5117
5118         rc = bnxt_map_hcomm_fw_status_reg(bp);
5119         if (rc)
5120                 return rc;
5121
5122         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5123         if (rc) {
5124                 bnxt_check_fw_status(bp);
5125                 return rc;
5126         }
5127
5128         rc = bnxt_hwrm_func_reset(bp);
5129         if (rc)
5130                 return -EIO;
5131
5132         rc = bnxt_hwrm_vnic_qcaps(bp);
5133         if (rc)
5134                 return rc;
5135
5136         rc = bnxt_hwrm_queue_qportcfg(bp);
5137         if (rc)
5138                 return rc;
5139
5140         /* Get the MAX capabilities for this function.
5141          * This function also allocates context memory for TQM rings and
5142          * informs the firmware about this allocated backing store memory.
5143          */
5144         rc = bnxt_hwrm_func_qcaps(bp);
5145         if (rc)
5146                 return rc;
5147
5148         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5149         if (rc)
5150                 return rc;
5151
5152         bnxt_hwrm_port_mac_qcfg(bp);
5153
5154         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5155         if (rc)
5156                 return rc;
5157
5158         bnxt_alloc_error_recovery_info(bp);
5159         /* Get the adapter error recovery support info */
5160         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5161         if (rc)
5162                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5163
5164         bnxt_hwrm_port_led_qcaps(bp);
5165
5166         return 0;
5167 }
5168
5169 static int
5170 bnxt_init_locks(struct bnxt *bp)
5171 {
5172         int err;
5173
5174         err = pthread_mutex_init(&bp->flow_lock, NULL);
5175         if (err) {
5176                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5177                 return err;
5178         }
5179
5180         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5181         if (err)
5182                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5183         return err;
5184 }
5185
5186 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5187 {
5188         int rc;
5189
5190         rc = bnxt_init_fw(bp);
5191         if (rc)
5192                 return rc;
5193
5194         if (!reconfig_dev) {
5195                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5196                 if (rc)
5197                         return rc;
5198         } else {
5199                 rc = bnxt_restore_dflt_mac(bp);
5200                 if (rc)
5201                         return rc;
5202         }
5203
5204         bnxt_config_vf_req_fwd(bp);
5205
5206         rc = bnxt_hwrm_func_driver_register(bp);
5207         if (rc) {
5208                 PMD_DRV_LOG(ERR, "Failed to register driver");
5209                 return -EBUSY;
5210         }
5211
5212         if (BNXT_PF(bp)) {
5213                 if (bp->pdev->max_vfs) {
5214                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5215                         if (rc) {
5216                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5217                                 return rc;
5218                         }
5219                 } else {
5220                         rc = bnxt_hwrm_allocate_pf_only(bp);
5221                         if (rc) {
5222                                 PMD_DRV_LOG(ERR,
5223                                             "Failed to allocate PF resources");
5224                                 return rc;
5225                         }
5226                 }
5227         }
5228
5229         rc = bnxt_alloc_mem(bp, reconfig_dev);
5230         if (rc)
5231                 return rc;
5232
5233         rc = bnxt_setup_int(bp);
5234         if (rc)
5235                 return rc;
5236
5237         rc = bnxt_request_int(bp);
5238         if (rc)
5239                 return rc;
5240
5241         rc = bnxt_init_ctx_mem(bp);
5242         if (rc) {
5243                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5244                 return rc;
5245         }
5246
5247         rc = bnxt_init_locks(bp);
5248         if (rc)
5249                 return rc;
5250
5251         return 0;
5252 }
5253
5254 static int
5255 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5256                           const char *value, void *opaque_arg)
5257 {
5258         struct bnxt *bp = opaque_arg;
5259         unsigned long truflow;
5260         char *end = NULL;
5261
5262         if (!value || !opaque_arg) {
5263                 PMD_DRV_LOG(ERR,
5264                             "Invalid parameter passed to truflow devargs.\n");
5265                 return -EINVAL;
5266         }
5267
5268         truflow = strtoul(value, &end, 10);
5269         if (end == NULL || *end != '\0' ||
5270             (truflow == ULONG_MAX && errno == ERANGE)) {
5271                 PMD_DRV_LOG(ERR,
5272                             "Invalid parameter passed to truflow devargs.\n");
5273                 return -EINVAL;
5274         }
5275
5276         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5277                 PMD_DRV_LOG(ERR,
5278                             "Invalid value passed to truflow devargs.\n");
5279                 return -EINVAL;
5280         }
5281
5282         bp->truflow = truflow;
5283         if (bp->truflow)
5284                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5285
5286         return 0;
5287 }
5288
5289 static int
5290 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5291                              const char *value, void *opaque_arg)
5292 {
5293         struct bnxt *bp = opaque_arg;
5294         unsigned long flow_xstat;
5295         char *end = NULL;
5296
5297         if (!value || !opaque_arg) {
5298                 PMD_DRV_LOG(ERR,
5299                             "Invalid parameter passed to flow_xstat devarg.\n");
5300                 return -EINVAL;
5301         }
5302
5303         flow_xstat = strtoul(value, &end, 10);
5304         if (end == NULL || *end != '\0' ||
5305             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5306                 PMD_DRV_LOG(ERR,
5307                             "Invalid parameter passed to flow_xstat devarg.\n");
5308                 return -EINVAL;
5309         }
5310
5311         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5312                 PMD_DRV_LOG(ERR,
5313                             "Invalid value passed to flow_xstat devarg.\n");
5314                 return -EINVAL;
5315         }
5316
5317         bp->flow_xstat = flow_xstat;
5318         if (bp->flow_xstat)
5319                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5320
5321         return 0;
5322 }
5323
5324 static void
5325 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5326 {
5327         struct rte_kvargs *kvlist;
5328
5329         if (devargs == NULL)
5330                 return;
5331
5332         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5333         if (kvlist == NULL)
5334                 return;
5335
5336         /*
5337          * Handler for "truflow" devarg.
5338          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1”
5339          */
5340         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5341                            bnxt_parse_devarg_truflow, bp);
5342
5343         /*
5344          * Handler for "flow_xstat" devarg.
5345          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1”
5346          */
5347         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5348                            bnxt_parse_devarg_flow_xstat, bp);
5349
5350         rte_kvargs_free(kvlist);
5351 }
5352
5353 static int
5354 bnxt_dev_init(struct rte_eth_dev *eth_dev)
5355 {
5356         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5357         static int version_printed;
5358         struct bnxt *bp;
5359         int rc;
5360
5361         if (version_printed++ == 0)
5362                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5363
5364         eth_dev->dev_ops = &bnxt_dev_ops;
5365         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5366         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5367
5368         /*
5369          * For secondary processes, we don't initialise any further
5370          * as primary has already done this work.
5371          */
5372         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5373                 return 0;
5374
5375         rte_eth_copy_pci_info(eth_dev, pci_dev);
5376
5377         bp = eth_dev->data->dev_private;
5378
5379         /* Parse dev arguments passed on when starting the DPDK application. */
5380         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5381
5382         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5383
5384         if (bnxt_vf_pciid(pci_dev->id.device_id))
5385                 bp->flags |= BNXT_FLAG_VF;
5386
5387         if (bnxt_thor_device(pci_dev->id.device_id))
5388                 bp->flags |= BNXT_FLAG_THOR_CHIP;
5389
5390         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5391             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5392             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5393             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5394                 bp->flags |= BNXT_FLAG_STINGRAY;
5395
5396         rc = bnxt_init_board(eth_dev);
5397         if (rc) {
5398                 PMD_DRV_LOG(ERR,
5399                             "Failed to initialize board rc: %x\n", rc);
5400                 return rc;
5401         }
5402
5403         rc = bnxt_alloc_hwrm_resources(bp);
5404         if (rc) {
5405                 PMD_DRV_LOG(ERR,
5406                             "Failed to allocate hwrm resource rc: %x\n", rc);
5407                 goto error_free;
5408         }
5409         rc = bnxt_alloc_leds_info(bp);
5410         if (rc)
5411                 goto error_free;
5412
5413         rc = bnxt_alloc_cos_queues(bp);
5414         if (rc)
5415                 goto error_free;
5416
5417         rc = bnxt_init_resources(bp, false);
5418         if (rc)
5419                 goto error_free;
5420
5421         rc = bnxt_alloc_stats_mem(bp);
5422         if (rc)
5423                 goto error_free;
5424
5425         /* Pass the information to the rte_eth_dev_close() that it should also
5426          * release the private port resources.
5427          */
5428         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5429
5430         PMD_DRV_LOG(INFO,
5431                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5432                     pci_dev->mem_resource[0].phys_addr,
5433                     pci_dev->mem_resource[0].addr);
5434
5435         return 0;
5436
5437 error_free:
5438         bnxt_dev_uninit(eth_dev);
5439         return rc;
5440 }
5441
5442
5443 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5444 {
5445         if (!ctx)
5446                 return;
5447
5448         if (ctx->va)
5449                 rte_free(ctx->va);
5450
5451         ctx->va = NULL;
5452         ctx->dma = RTE_BAD_IOVA;
5453         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5454 }
5455
5456 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5457 {
5458         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5459                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5460                                   bp->rx_fc_out_tbl.ctx_id,
5461                                   bp->max_fc,
5462                                   false);
5463
5464         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5465                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5466                                   bp->tx_fc_out_tbl.ctx_id,
5467                                   bp->max_fc,
5468                                   false);
5469
5470         if (bp->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5471                 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_in_tbl.ctx_id);
5472         bp->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5473
5474         if (bp->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5475                 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_out_tbl.ctx_id);
5476         bp->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5477
5478         if (bp->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5479                 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_in_tbl.ctx_id);
5480         bp->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5481
5482         if (bp->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5483                 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_out_tbl.ctx_id);
5484         bp->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5485 }
5486
5487 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5488 {
5489         bnxt_unregister_fc_ctx_mem(bp);
5490
5491         bnxt_free_ctx_mem_buf(&bp->rx_fc_in_tbl);
5492         bnxt_free_ctx_mem_buf(&bp->rx_fc_out_tbl);
5493         bnxt_free_ctx_mem_buf(&bp->tx_fc_in_tbl);
5494         bnxt_free_ctx_mem_buf(&bp->tx_fc_out_tbl);
5495 }
5496
5497 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5498 {
5499         bnxt_uninit_fc_ctx_mem(bp);
5500 }
5501
5502 static void
5503 bnxt_free_error_recovery_info(struct bnxt *bp)
5504 {
5505         rte_free(bp->recovery_info);
5506         bp->recovery_info = NULL;
5507         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5508 }
5509
5510 static void
5511 bnxt_uninit_locks(struct bnxt *bp)
5512 {
5513         pthread_mutex_destroy(&bp->flow_lock);
5514         pthread_mutex_destroy(&bp->def_cp_lock);
5515 }
5516
5517 static int
5518 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5519 {
5520         int rc;
5521
5522         bnxt_free_int(bp);
5523         bnxt_free_mem(bp, reconfig_dev);
5524         bnxt_hwrm_func_buf_unrgtr(bp);
5525         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5526         bp->flags &= ~BNXT_FLAG_REGISTERED;
5527         bnxt_free_ctx_mem(bp);
5528         if (!reconfig_dev) {
5529                 bnxt_free_hwrm_resources(bp);
5530                 bnxt_free_error_recovery_info(bp);
5531         }
5532
5533         bnxt_uninit_ctx_mem(bp);
5534
5535         bnxt_uninit_locks(bp);
5536         rte_free(bp->ptp_cfg);
5537         bp->ptp_cfg = NULL;
5538         return rc;
5539 }
5540
5541 static int
5542 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5543 {
5544         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5545                 return -EPERM;
5546
5547         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5548
5549         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5550                 bnxt_dev_close_op(eth_dev);
5551
5552         return 0;
5553 }
5554
5555 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5556         struct rte_pci_device *pci_dev)
5557 {
5558         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
5559                 bnxt_dev_init);
5560 }
5561
5562 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5563 {
5564         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
5565                 return rte_eth_dev_pci_generic_remove(pci_dev,
5566                                 bnxt_dev_uninit);
5567         else
5568                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5569 }
5570
5571 static struct rte_pci_driver bnxt_rte_pmd = {
5572         .id_table = bnxt_pci_id_map,
5573         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5574         .probe = bnxt_pci_probe,
5575         .remove = bnxt_pci_remove,
5576 };
5577
5578 static bool
5579 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5580 {
5581         if (strcmp(dev->device->driver->name, drv->driver.name))
5582                 return false;
5583
5584         return true;
5585 }
5586
5587 bool is_bnxt_supported(struct rte_eth_dev *dev)
5588 {
5589         return is_device_supported(dev, &bnxt_rte_pmd);
5590 }
5591
5592 RTE_INIT(bnxt_init_log)
5593 {
5594         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
5595         if (bnxt_logtype_driver >= 0)
5596                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
5597 }
5598
5599 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5600 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5601 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");