drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29
  30 #define DRV_MODULE_NAME         "bnxt"
  31 static const char bnxt_version[] =
  32         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  33 int bnxt_logtype_driver;
  34
  35 /*
  36  * The set of PCI devices this driver supports
  37  */
  38 static const struct rte_pci_id bnxt_pci_id_map[] = {
  39         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  40                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  41         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  42                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  43         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  92         { .vendor_id = 0, /* sentinel */ },
  93 };
  94
  95 #define BNXT_ETH_RSS_SUPPORT (  \
  96         ETH_RSS_IPV4 |          \
  97         ETH_RSS_NONFRAG_IPV4_TCP |      \
  98         ETH_RSS_NONFRAG_IPV4_UDP |      \
  99         ETH_RSS_IPV6 |          \
 100         ETH_RSS_NONFRAG_IPV6_TCP |      \
 101         ETH_RSS_NONFRAG_IPV6_UDP)
 102
 103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 104                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 105                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 106                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_TCP_TSO | \
 108                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 109                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 110                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 114                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 115
 116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 117                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 118                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 119                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 120                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 122                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 123                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 124                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 125                                      DEV_RX_OFFLOAD_TCP_LRO | \
 126                                      DEV_RX_OFFLOAD_SCATTER | \
 127                                      DEV_RX_OFFLOAD_RSS_HASH)
 128
 129 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 130 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 131 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 132 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 133 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 134 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 135 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 136
 137 int is_bnxt_in_error(struct bnxt *bp)
 138 {
 139         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 140                 return -EIO;
 141         if (bp->flags & BNXT_FLAG_FW_RESET)
 142                 return -EBUSY;
 143
 144         return 0;
 145 }
 146
 147 /***********************/
 148
 149 /*
 150  * High level utility functions
 151  */
 152
 153 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 154 {
 155         if (!BNXT_CHIP_THOR(bp))
 156                 return 1;
 157
 158         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 159                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 160                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 161 }
 162
 163 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 164 {
 165         if (!BNXT_CHIP_THOR(bp))
 166                 return HW_HASH_INDEX_SIZE;
 167
 168         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 169 }
 170
 171 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 172 {
 173         bnxt_free_filter_mem(bp);
 174         bnxt_free_vnic_attributes(bp);
 175         bnxt_free_vnic_mem(bp);
 176
 177         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 178          * If the number of rings change across fw update,
 179          * we don't have much choice except to warn the user.
 180          */
 181         if (!reconfig) {
 182                 bnxt_free_stats(bp);
 183                 bnxt_free_tx_rings(bp);
 184                 bnxt_free_rx_rings(bp);
 185         }
 186         bnxt_free_async_cp_ring(bp);
 187         bnxt_free_rxtx_nq_ring(bp);
 188
 189         rte_free(bp->grp_info);
 190         bp->grp_info = NULL;
 191 }
 192
 193 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 194 {
 195         int rc;
 196
 197         rc = bnxt_alloc_ring_grps(bp);
 198         if (rc)
 199                 goto alloc_mem_err;
 200
 201         rc = bnxt_alloc_async_ring_struct(bp);
 202         if (rc)
 203                 goto alloc_mem_err;
 204
 205         rc = bnxt_alloc_vnic_mem(bp);
 206         if (rc)
 207                 goto alloc_mem_err;
 208
 209         rc = bnxt_alloc_vnic_attributes(bp);
 210         if (rc)
 211                 goto alloc_mem_err;
 212
 213         rc = bnxt_alloc_filter_mem(bp);
 214         if (rc)
 215                 goto alloc_mem_err;
 216
 217         rc = bnxt_alloc_async_cp_ring(bp);
 218         if (rc)
 219                 goto alloc_mem_err;
 220
 221         rc = bnxt_alloc_rxtx_nq_ring(bp);
 222         if (rc)
 223                 goto alloc_mem_err;
 224
 225         return 0;
 226
 227 alloc_mem_err:
 228         bnxt_free_mem(bp, reconfig);
 229         return rc;
 230 }
 231
 232 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 233 {
 234         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 235         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 236         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 237         struct bnxt_rx_queue *rxq;
 238         unsigned int j;
 239         int rc;
 240
 241         rc = bnxt_vnic_grp_alloc(bp, vnic);
 242         if (rc)
 243                 goto err_out;
 244
 245         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 246                     vnic_id, vnic, vnic->fw_grp_ids);
 247
 248         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 249         if (rc)
 250                 goto err_out;
 251
 252         /* Alloc RSS context only if RSS mode is enabled */
 253         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 254                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 255
 256                 rc = 0;
 257                 for (j = 0; j < nr_ctxs; j++) {
 258                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 259                         if (rc)
 260                                 break;
 261                 }
 262                 if (rc) {
 263                         PMD_DRV_LOG(ERR,
 264                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 265                                     vnic_id, j, rc);
 266                         goto err_out;
 267                 }
 268                 vnic->num_lb_ctxts = nr_ctxs;
 269         }
 270
 271         /*
 272          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 273          * setting is not available at this time, it will not be
 274          * configured correctly in the CFA.
 275          */
 276         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 277                 vnic->vlan_strip = true;
 278         else
 279                 vnic->vlan_strip = false;
 280
 281         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 282         if (rc)
 283                 goto err_out;
 284
 285         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 286         if (rc)
 287                 goto err_out;
 288
 289         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 290                 rxq = bp->eth_dev->data->rx_queues[j];
 291
 292                 PMD_DRV_LOG(DEBUG,
 293                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 294                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 295
 296                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 297                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 298                 else
 299                         vnic->rx_queue_cnt++;
 300         }
 301
 302         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 303
 304         rc = bnxt_vnic_rss_configure(bp, vnic);
 305         if (rc)
 306                 goto err_out;
 307
 308         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 309
 310         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 311                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 312         else
 313                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 314
 315         return 0;
 316 err_out:
 317         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 318                     vnic_id, rc);
 319         return rc;
 320 }
 321
 322 static int bnxt_init_chip(struct bnxt *bp)
 323 {
 324         struct rte_eth_link new;
 325         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 326         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 327         uint32_t intr_vector = 0;
 328         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 329         uint32_t vec = BNXT_MISC_VEC_ID;
 330         unsigned int i, j;
 331         int rc;
 332
 333         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 334                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 335                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 336                 bp->flags |= BNXT_FLAG_JUMBO;
 337         } else {
 338                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 339                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 340                 bp->flags &= ~BNXT_FLAG_JUMBO;
 341         }
 342
 343         /* THOR does not support ring groups.
 344          * But we will use the array to save RSS context IDs.
 345          */
 346         if (BNXT_CHIP_THOR(bp))
 347                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 348
 349         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 350         if (rc) {
 351                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 352                 goto err_out;
 353         }
 354
 355         rc = bnxt_alloc_hwrm_rings(bp);
 356         if (rc) {
 357                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 358                 goto err_out;
 359         }
 360
 361         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 362         if (rc) {
 363                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 364                 goto err_out;
 365         }
 366
 367         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 368                 goto skip_cosq_cfg;
 369
 370         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 371                 if (bp->rx_cos_queue[i].id != 0xff) {
 372                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 373
 374                         if (!vnic) {
 375                                 PMD_DRV_LOG(ERR,
 376                                             "Num pools more than FW profile\n");
 377                                 rc = -EINVAL;
 378                                 goto err_out;
 379                         }
 380                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 381                         bp->rx_cosq_cnt++;
 382                 }
 383         }
 384
 385 skip_cosq_cfg:
 386         rc = bnxt_mq_rx_configure(bp);
 387         if (rc) {
 388                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 389                 goto err_out;
 390         }
 391
 392         /* VNIC configuration */
 393         for (i = 0; i < bp->nr_vnics; i++) {
 394                 rc = bnxt_setup_one_vnic(bp, i);
 395                 if (rc)
 396                         goto err_out;
 397         }
 398
 399         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 400         if (rc) {
 401                 PMD_DRV_LOG(ERR,
 402                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 403                 goto err_out;
 404         }
 405
 406         /* check and configure queue intr-vector mapping */
 407         if ((rte_intr_cap_multiple(intr_handle) ||
 408              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 409             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 410                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 411                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 412                 if (intr_vector > bp->rx_cp_nr_rings) {
 413                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 414                                         bp->rx_cp_nr_rings);
 415                         return -ENOTSUP;
 416                 }
 417                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 418                 if (rc)
 419                         return rc;
 420         }
 421
 422         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 423                 intr_handle->intr_vec =
 424                         rte_zmalloc("intr_vec",
 425                                     bp->eth_dev->data->nb_rx_queues *
 426                                     sizeof(int), 0);
 427                 if (intr_handle->intr_vec == NULL) {
 428                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 429                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 430                         rc = -ENOMEM;
 431                         goto err_disable;
 432                 }
 433                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 434                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 435                          intr_handle->intr_vec, intr_handle->nb_efd,
 436                         intr_handle->max_intr);
 437                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 438                      queue_id++) {
 439                         intr_handle->intr_vec[queue_id] =
 440                                                         vec + BNXT_RX_VEC_START;
 441                         if (vec < base + intr_handle->nb_efd - 1)
 442                                 vec++;
 443                 }
 444         }
 445
 446         /* enable uio/vfio intr/eventfd mapping */
 447         rc = rte_intr_enable(intr_handle);
 448 #ifndef RTE_EXEC_ENV_FREEBSD
 449         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 450         if (rc)
 451                 goto err_free;
 452 #endif
 453
 454         rc = bnxt_get_hwrm_link_config(bp, &new);
 455         if (rc) {
 456                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 457                 goto err_free;
 458         }
 459
 460         if (!bp->link_info.link_up) {
 461                 rc = bnxt_set_hwrm_link_config(bp, true);
 462                 if (rc) {
 463                         PMD_DRV_LOG(ERR,
 464                                 "HWRM link config failure rc: %x\n", rc);
 465                         goto err_free;
 466                 }
 467         }
 468         bnxt_print_link_info(bp->eth_dev);
 469
 470         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 471         if (!bp->mark_table)
 472                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 473
 474         return 0;
 475
 476 err_free:
 477         rte_free(intr_handle->intr_vec);
 478 err_disable:
 479         rte_intr_efd_disable(intr_handle);
 480 err_out:
 481         /* Some of the error status returned by FW may not be from errno.h */
 482         if (rc > 0)
 483                 rc = -EIO;
 484
 485         return rc;
 486 }
 487
 488 static int bnxt_shutdown_nic(struct bnxt *bp)
 489 {
 490         bnxt_free_all_hwrm_resources(bp);
 491         bnxt_free_all_filters(bp);
 492         bnxt_free_all_vnics(bp);
 493         return 0;
 494 }
 495
 496 /*
 497  * Device configuration and status function
 498  */
 499
 500 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 501                                 struct rte_eth_dev_info *dev_info)
 502 {
 503         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 504         struct bnxt *bp = eth_dev->data->dev_private;
 505         uint16_t max_vnics, i, j, vpool, vrxq;
 506         unsigned int max_rx_rings;
 507         int rc;
 508
 509         rc = is_bnxt_in_error(bp);
 510         if (rc)
 511                 return rc;
 512
 513         /* MAC Specifics */
 514         dev_info->max_mac_addrs = bp->max_l2_ctx;
 515         dev_info->max_hash_mac_addrs = 0;
 516
 517         /* PF/VF specifics */
 518         if (BNXT_PF(bp))
 519                 dev_info->max_vfs = pdev->max_vfs;
 520
 521         max_rx_rings = BNXT_MAX_RINGS(bp);
 522         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 523         dev_info->max_rx_queues = max_rx_rings;
 524         dev_info->max_tx_queues = max_rx_rings;
 525         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 526         dev_info->hash_key_size = 40;
 527         max_vnics = bp->max_vnics;
 528
 529         /* MTU specifics */
 530         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 531         dev_info->max_mtu = BNXT_MAX_MTU;
 532
 533         /* Fast path specifics */
 534         dev_info->min_rx_bufsize = 1;
 535         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 536
 537         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 538         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 539                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 540         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 541         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 542
 543         /* *INDENT-OFF* */
 544         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 545                 .rx_thresh = {
 546                         .pthresh = 8,
 547                         .hthresh = 8,
 548                         .wthresh = 0,
 549                 },
 550                 .rx_free_thresh = 32,
 551                 /* If no descriptors available, pkts are dropped by default */
 552                 .rx_drop_en = 1,
 553         };
 554
 555         dev_info->default_txconf = (struct rte_eth_txconf) {
 556                 .tx_thresh = {
 557                         .pthresh = 32,
 558                         .hthresh = 0,
 559                         .wthresh = 0,
 560                 },
 561                 .tx_free_thresh = 32,
 562                 .tx_rs_thresh = 32,
 563         };
 564         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 565
 566         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 567         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 568         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 569         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 570         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 571
 572         /* *INDENT-ON* */
 573
 574         /*
 575          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 576          *       need further investigation.
 577          */
 578
 579         /* VMDq resources */
 580         vpool = 64; /* ETH_64_POOLS */
 581         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 582         for (i = 0; i < 4; vpool >>= 1, i++) {
 583                 if (max_vnics > vpool) {
 584                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 585                                 if (dev_info->max_rx_queues > vrxq) {
 586                                         if (vpool > vrxq)
 587                                                 vpool = vrxq;
 588                                         goto found;
 589                                 }
 590                         }
 591                         /* Not enough resources to support VMDq */
 592                         break;
 593                 }
 594         }
 595         /* Not enough resources to support VMDq */
 596         vpool = 0;
 597         vrxq = 0;
 598 found:
 599         dev_info->max_vmdq_pools = vpool;
 600         dev_info->vmdq_queue_num = vrxq;
 601
 602         dev_info->vmdq_pool_base = 0;
 603         dev_info->vmdq_queue_base = 0;
 604
 605         return 0;
 606 }
 607
 608 /* Configure the device based on the configuration provided */
 609 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 610 {
 611         struct bnxt *bp = eth_dev->data->dev_private;
 612         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 613         int rc;
 614
 615         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 616         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 617         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 618         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 619
 620         rc = is_bnxt_in_error(bp);
 621         if (rc)
 622                 return rc;
 623
 624         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 625                 rc = bnxt_hwrm_check_vf_rings(bp);
 626                 if (rc) {
 627                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 628                         return -ENOSPC;
 629                 }
 630
 631                 /* If a resource has already been allocated - in this case
 632                  * it is the async completion ring, free it. Reallocate it after
 633                  * resource reservation. This will ensure the resource counts
 634                  * are calculated correctly.
 635                  */
 636
 637                 pthread_mutex_lock(&bp->def_cp_lock);
 638
 639                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 640                         bnxt_disable_int(bp);
 641                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 642                 }
 643
 644                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 645                 if (rc) {
 646                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 647                         pthread_mutex_unlock(&bp->def_cp_lock);
 648                         return -ENOSPC;
 649                 }
 650
 651                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 652                         rc = bnxt_alloc_async_cp_ring(bp);
 653                         if (rc) {
 654                                 pthread_mutex_unlock(&bp->def_cp_lock);
 655                                 return rc;
 656                         }
 657                         bnxt_enable_int(bp);
 658                 }
 659
 660                 pthread_mutex_unlock(&bp->def_cp_lock);
 661         } else {
 662                 /* legacy driver needs to get updated values */
 663                 rc = bnxt_hwrm_func_qcaps(bp);
 664                 if (rc) {
 665                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 666                         return rc;
 667                 }
 668         }
 669
 670         /* Inherit new configurations */
 671         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 672             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 673             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 674                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 675             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 676             bp->max_stat_ctx)
 677                 goto resource_error;
 678
 679         if (BNXT_HAS_RING_GRPS(bp) &&
 680             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 681                 goto resource_error;
 682
 683         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 684             bp->max_vnics < eth_dev->data->nb_rx_queues)
 685                 goto resource_error;
 686
 687         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 688         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 689
 690         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 691                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 692         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
 693
 694         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 695                 eth_dev->data->mtu =
 696                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 697                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 698                         BNXT_NUM_VLANS;
 699                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 700         }
 701         return 0;
 702
 703 resource_error:
 704         PMD_DRV_LOG(ERR,
 705                     "Insufficient resources to support requested config\n");
 706         PMD_DRV_LOG(ERR,
 707                     "Num Queues Requested: Tx %d, Rx %d\n",
 708                     eth_dev->data->nb_tx_queues,
 709                     eth_dev->data->nb_rx_queues);
 710         PMD_DRV_LOG(ERR,
 711                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 712                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 713                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 714         return -ENOSPC;
 715 }
 716
 717 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 718 {
 719         struct rte_eth_link *link = &eth_dev->data->dev_link;
 720
 721         if (link->link_status)
 722                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 723                         eth_dev->data->port_id,
 724                         (uint32_t)link->link_speed,
 725                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 726                         ("full-duplex") : ("half-duplex\n"));
 727         else
 728                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 729                         eth_dev->data->port_id);
 730 }
 731
 732 /*
 733  * Determine whether the current configuration requires support for scattered
 734  * receive; return 1 if scattered receive is required and 0 if not.
 735  */
 736 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 737 {
 738         uint16_t buf_size;
 739         int i;
 740
 741         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 742                 return 1;
 743
 744         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 745                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 746
 747                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 748                                       RTE_PKTMBUF_HEADROOM);
 749                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 750                         return 1;
 751         }
 752         return 0;
 753 }
 754
 755 static eth_rx_burst_t
 756 bnxt_receive_function(struct rte_eth_dev *eth_dev)
 757 {
 758         struct bnxt *bp = eth_dev->data->dev_private;
 759
 760 #ifdef RTE_ARCH_X86
 761 #ifndef RTE_LIBRTE_IEEE1588
 762         /*
 763          * Vector mode receive can be enabled only if scatter rx is not
 764          * in use and rx offloads are limited to VLAN stripping and
 765          * CRC stripping.
 766          */
 767         if (!eth_dev->data->scattered_rx &&
 768             !(eth_dev->data->dev_conf.rxmode.offloads &
 769               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 770                 DEV_RX_OFFLOAD_KEEP_CRC |
 771                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 772                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 773                 DEV_RX_OFFLOAD_UDP_CKSUM |
 774                 DEV_RX_OFFLOAD_TCP_CKSUM |
 775                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 776                 DEV_RX_OFFLOAD_RSS_HASH |
 777                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 778                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 779                             eth_dev->data->port_id);
 780                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
 781                 return bnxt_recv_pkts_vec;
 782         }
 783         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 784                     eth_dev->data->port_id);
 785         PMD_DRV_LOG(INFO,
 786                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 787                     eth_dev->data->port_id,
 788                     eth_dev->data->scattered_rx,
 789                     eth_dev->data->dev_conf.rxmode.offloads);
 790 #endif
 791 #endif
 792         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
 793         return bnxt_recv_pkts;
 794 }
 795
 796 static eth_tx_burst_t
 797 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 798 {
 799 #ifdef RTE_ARCH_X86
 800 #ifndef RTE_LIBRTE_IEEE1588
 801         /*
 802          * Vector mode transmit can be enabled only if not using scatter rx
 803          * or tx offloads.
 804          */
 805         if (!eth_dev->data->scattered_rx &&
 806             !eth_dev->data->dev_conf.txmode.offloads) {
 807                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 808                             eth_dev->data->port_id);
 809                 return bnxt_xmit_pkts_vec;
 810         }
 811         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 812                     eth_dev->data->port_id);
 813         PMD_DRV_LOG(INFO,
 814                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 815                     eth_dev->data->port_id,
 816                     eth_dev->data->scattered_rx,
 817                     eth_dev->data->dev_conf.txmode.offloads);
 818 #endif
 819 #endif
 820         return bnxt_xmit_pkts;
 821 }
 822
 823 static int bnxt_handle_if_change_status(struct bnxt *bp)
 824 {
 825         int rc;
 826
 827         /* Since fw has undergone a reset and lost all contexts,
 828          * set fatal flag to not issue hwrm during cleanup
 829          */
 830         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 831         bnxt_uninit_resources(bp, true);
 832
 833         /* clear fatal flag so that re-init happens */
 834         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 835         rc = bnxt_init_resources(bp, true);
 836
 837         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 838
 839         return rc;
 840 }
 841
 842 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 843 {
 844         struct bnxt *bp = eth_dev->data->dev_private;
 845         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 846         int vlan_mask = 0;
 847         int rc;
 848
 849         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
 850                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
 851                 return -EINVAL;
 852         }
 853
 854         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 855                 PMD_DRV_LOG(ERR,
 856                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 857                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 858         }
 859
 860         rc = bnxt_hwrm_if_change(bp, 1);
 861         if (!rc) {
 862                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 863                         rc = bnxt_handle_if_change_status(bp);
 864                         if (rc)
 865                                 return rc;
 866                 }
 867         }
 868         bnxt_enable_int(bp);
 869
 870         rc = bnxt_init_chip(bp);
 871         if (rc)
 872                 goto error;
 873
 874         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 875
 876         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
 877         bp->dev_stopped = 0;
 878
 879         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 880                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 881         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 882                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 883         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 884         if (rc)
 885                 goto error;
 886
 887         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 888         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 889
 890         bp->flags |= BNXT_FLAG_INIT_DONE;
 891         eth_dev->data->dev_started = 1;
 892         pthread_mutex_lock(&bp->def_cp_lock);
 893         bnxt_schedule_fw_health_check(bp);
 894         pthread_mutex_unlock(&bp->def_cp_lock);
 895         return 0;
 896
 897 error:
 898         bnxt_hwrm_if_change(bp, 0);
 899         bnxt_shutdown_nic(bp);
 900         bnxt_free_tx_mbufs(bp);
 901         bnxt_free_rx_mbufs(bp);
 902         bp->dev_stopped = 1;
 903         return rc;
 904 }
 905
 906 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 907 {
 908         struct bnxt *bp = eth_dev->data->dev_private;
 909         int rc = 0;
 910
 911         if (!bp->link_info.link_up)
 912                 rc = bnxt_set_hwrm_link_config(bp, true);
 913         if (!rc)
 914                 eth_dev->data->dev_link.link_status = 1;
 915
 916         bnxt_print_link_info(eth_dev);
 917         return rc;
 918 }
 919
 920 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 921 {
 922         struct bnxt *bp = eth_dev->data->dev_private;
 923
 924         eth_dev->data->dev_link.link_status = 0;
 925         bnxt_set_hwrm_link_config(bp, false);
 926         bp->link_info.link_up = 0;
 927
 928         return 0;
 929 }
 930
 931 /* Unload the driver, release resources */
 932 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 933 {
 934         struct bnxt *bp = eth_dev->data->dev_private;
 935         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 936         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 937
 938         eth_dev->data->dev_started = 0;
 939         /* Prevent crashes when queues are still in use */
 940         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 941         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 942
 943         bnxt_disable_int(bp);
 944
 945         /* disable uio/vfio intr/eventfd mapping */
 946         rte_intr_disable(intr_handle);
 947
 948         bnxt_cancel_fw_health_check(bp);
 949
 950         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 951         if (bp->eth_dev->data->dev_started) {
 952                 /* TBD: STOP HW queues DMA */
 953                 eth_dev->data->dev_link.link_status = 0;
 954         }
 955         bnxt_dev_set_link_down_op(eth_dev);
 956
 957         /* Wait for link to be reset and the async notification to process.
 958          * During reset recovery, there is no need to wait
 959          */
 960         if (!is_bnxt_in_error(bp))
 961                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
 962
 963         /* Clean queue intr-vector mapping */
 964         rte_intr_efd_disable(intr_handle);
 965         if (intr_handle->intr_vec != NULL) {
 966                 rte_free(intr_handle->intr_vec);
 967                 intr_handle->intr_vec = NULL;
 968         }
 969
 970         bnxt_hwrm_port_clr_stats(bp);
 971         bnxt_free_tx_mbufs(bp);
 972         bnxt_free_rx_mbufs(bp);
 973         /* Process any remaining notifications in default completion queue */
 974         bnxt_int_handler(eth_dev);
 975         bnxt_shutdown_nic(bp);
 976         bnxt_hwrm_if_change(bp, 0);
 977
 978         rte_free(bp->mark_table);
 979         bp->mark_table = NULL;
 980
 981         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
 982         bp->dev_stopped = 1;
 983         bp->rx_cosq_cnt = 0;
 984 }
 985
 986 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 987 {
 988         struct bnxt *bp = eth_dev->data->dev_private;
 989
 990         if (bp->dev_stopped == 0)
 991                 bnxt_dev_stop_op(eth_dev);
 992
 993         bnxt_uninit_resources(bp, false);
 994
 995         eth_dev->dev_ops = NULL;
 996         eth_dev->rx_pkt_burst = NULL;
 997         eth_dev->tx_pkt_burst = NULL;
 998
 999         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1000         bp->tx_mem_zone = NULL;
1001         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1002         bp->rx_mem_zone = NULL;
1003
1004         rte_free(bp->pf.vf_info);
1005         bp->pf.vf_info = NULL;
1006
1007         rte_free(bp->grp_info);
1008         bp->grp_info = NULL;
1009 }
1010
1011 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1012                                     uint32_t index)
1013 {
1014         struct bnxt *bp = eth_dev->data->dev_private;
1015         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1016         struct bnxt_vnic_info *vnic;
1017         struct bnxt_filter_info *filter, *temp_filter;
1018         uint32_t i;
1019
1020         if (is_bnxt_in_error(bp))
1021                 return;
1022
1023         /*
1024          * Loop through all VNICs from the specified filter flow pools to
1025          * remove the corresponding MAC addr filter
1026          */
1027         for (i = 0; i < bp->nr_vnics; i++) {
1028                 if (!(pool_mask & (1ULL << i)))
1029                         continue;
1030
1031                 vnic = &bp->vnic_info[i];
1032                 filter = STAILQ_FIRST(&vnic->filter);
1033                 while (filter) {
1034                         temp_filter = STAILQ_NEXT(filter, next);
1035                         if (filter->mac_index == index) {
1036                                 STAILQ_REMOVE(&vnic->filter, filter,
1037                                                 bnxt_filter_info, next);
1038                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1039                                 bnxt_free_filter(bp, filter);
1040                         }
1041                         filter = temp_filter;
1042                 }
1043         }
1044 }
1045
1046 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1047                                struct rte_ether_addr *mac_addr, uint32_t index,
1048                                uint32_t pool)
1049 {
1050         struct bnxt_filter_info *filter;
1051         int rc = 0;
1052
1053         /* Attach requested MAC address to the new l2_filter */
1054         STAILQ_FOREACH(filter, &vnic->filter, next) {
1055                 if (filter->mac_index == index) {
1056                         PMD_DRV_LOG(DEBUG,
1057                                     "MAC addr already existed for pool %d\n",
1058                                     pool);
1059                         return 0;
1060                 }
1061         }
1062
1063         filter = bnxt_alloc_filter(bp);
1064         if (!filter) {
1065                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1066                 return -ENODEV;
1067         }
1068
1069         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1070          * if the MAC that's been programmed now is a different one, then,
1071          * copy that addr to filter->l2_addr
1072          */
1073         if (mac_addr)
1074                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1075         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1076
1077         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1078         if (!rc) {
1079                 filter->mac_index = index;
1080                 if (filter->mac_index == 0)
1081                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1082                 else
1083                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1084         } else {
1085                 bnxt_free_filter(bp, filter);
1086         }
1087
1088         return rc;
1089 }
1090
1091 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1092                                 struct rte_ether_addr *mac_addr,
1093                                 uint32_t index, uint32_t pool)
1094 {
1095         struct bnxt *bp = eth_dev->data->dev_private;
1096         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1097         int rc = 0;
1098
1099         rc = is_bnxt_in_error(bp);
1100         if (rc)
1101                 return rc;
1102
1103         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1104                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1105                 return -ENOTSUP;
1106         }
1107
1108         if (!vnic) {
1109                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1110                 return -EINVAL;
1111         }
1112
1113         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1114
1115         return rc;
1116 }
1117
1118 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1119                      bool exp_link_status)
1120 {
1121         int rc = 0;
1122         struct bnxt *bp = eth_dev->data->dev_private;
1123         struct rte_eth_link new;
1124         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1125                   BNXT_LINK_DOWN_WAIT_CNT;
1126
1127         rc = is_bnxt_in_error(bp);
1128         if (rc)
1129                 return rc;
1130
1131         memset(&new, 0, sizeof(new));
1132         do {
1133                 /* Retrieve link info from hardware */
1134                 rc = bnxt_get_hwrm_link_config(bp, &new);
1135                 if (rc) {
1136                         new.link_speed = ETH_LINK_SPEED_100M;
1137                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1138                         PMD_DRV_LOG(ERR,
1139                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1140                         goto out;
1141                 }
1142
1143                 if (!wait_to_complete || new.link_status == exp_link_status)
1144                         break;
1145
1146                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1147         } while (cnt--);
1148
1149 out:
1150         /* Timed out or success */
1151         if (new.link_status != eth_dev->data->dev_link.link_status ||
1152         new.link_speed != eth_dev->data->dev_link.link_speed) {
1153                 rte_eth_linkstatus_set(eth_dev, &new);
1154
1155                 _rte_eth_dev_callback_process(eth_dev,
1156                                               RTE_ETH_EVENT_INTR_LSC,
1157                                               NULL);
1158
1159                 bnxt_print_link_info(eth_dev);
1160         }
1161
1162         return rc;
1163 }
1164
1165 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1166                                int wait_to_complete)
1167 {
1168         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1169 }
1170
1171 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1172 {
1173         struct bnxt *bp = eth_dev->data->dev_private;
1174         struct bnxt_vnic_info *vnic;
1175         uint32_t old_flags;
1176         int rc;
1177
1178         rc = is_bnxt_in_error(bp);
1179         if (rc)
1180                 return rc;
1181
1182         /* Filter settings will get applied when port is started */
1183         if (bp->dev_stopped == 1)
1184                 return 0;
1185
1186         if (bp->vnic_info == NULL)
1187                 return 0;
1188
1189         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1190
1191         old_flags = vnic->flags;
1192         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1193         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1194         if (rc != 0)
1195                 vnic->flags = old_flags;
1196
1197         return rc;
1198 }
1199
1200 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1201 {
1202         struct bnxt *bp = eth_dev->data->dev_private;
1203         struct bnxt_vnic_info *vnic;
1204         uint32_t old_flags;
1205         int rc;
1206
1207         rc = is_bnxt_in_error(bp);
1208         if (rc)
1209                 return rc;
1210
1211         /* Filter settings will get applied when port is started */
1212         if (bp->dev_stopped == 1)
1213                 return 0;
1214
1215         if (bp->vnic_info == NULL)
1216                 return 0;
1217
1218         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1219
1220         old_flags = vnic->flags;
1221         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1222         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1223         if (rc != 0)
1224                 vnic->flags = old_flags;
1225
1226         return rc;
1227 }
1228
1229 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1230 {
1231         struct bnxt *bp = eth_dev->data->dev_private;
1232         struct bnxt_vnic_info *vnic;
1233         uint32_t old_flags;
1234         int rc;
1235
1236         rc = is_bnxt_in_error(bp);
1237         if (rc)
1238                 return rc;
1239
1240         /* Filter settings will get applied when port is started */
1241         if (bp->dev_stopped == 1)
1242                 return 0;
1243
1244         if (bp->vnic_info == NULL)
1245                 return 0;
1246
1247         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1248
1249         old_flags = vnic->flags;
1250         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1251         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1252         if (rc != 0)
1253                 vnic->flags = old_flags;
1254
1255         return rc;
1256 }
1257
1258 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1259 {
1260         struct bnxt *bp = eth_dev->data->dev_private;
1261         struct bnxt_vnic_info *vnic;
1262         uint32_t old_flags;
1263         int rc;
1264
1265         rc = is_bnxt_in_error(bp);
1266         if (rc)
1267                 return rc;
1268
1269         /* Filter settings will get applied when port is started */
1270         if (bp->dev_stopped == 1)
1271                 return 0;
1272
1273         if (bp->vnic_info == NULL)
1274                 return 0;
1275
1276         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1277
1278         old_flags = vnic->flags;
1279         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1280         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1281         if (rc != 0)
1282                 vnic->flags = old_flags;
1283
1284         return rc;
1285 }
1286
1287 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1288 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1289 {
1290         if (qid >= bp->rx_nr_rings)
1291                 return NULL;
1292
1293         return bp->eth_dev->data->rx_queues[qid];
1294 }
1295
1296 /* Return rxq corresponding to a given rss table ring/group ID. */
1297 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1298 {
1299         struct bnxt_rx_queue *rxq;
1300         unsigned int i;
1301
1302         if (!BNXT_HAS_RING_GRPS(bp)) {
1303                 for (i = 0; i < bp->rx_nr_rings; i++) {
1304                         rxq = bp->eth_dev->data->rx_queues[i];
1305                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1306                                 return rxq->index;
1307                 }
1308         } else {
1309                 for (i = 0; i < bp->rx_nr_rings; i++) {
1310                         if (bp->grp_info[i].fw_grp_id == fwr)
1311                                 return i;
1312                 }
1313         }
1314
1315         return INVALID_HW_RING_ID;
1316 }
1317
1318 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1319                             struct rte_eth_rss_reta_entry64 *reta_conf,
1320                             uint16_t reta_size)
1321 {
1322         struct bnxt *bp = eth_dev->data->dev_private;
1323         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1324         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1325         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1326         uint16_t idx, sft;
1327         int i, rc;
1328
1329         rc = is_bnxt_in_error(bp);
1330         if (rc)
1331                 return rc;
1332
1333         if (!vnic->rss_table)
1334                 return -EINVAL;
1335
1336         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1337                 return -EINVAL;
1338
1339         if (reta_size != tbl_size) {
1340                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1341                         "(%d) must equal the size supported by the hardware "
1342                         "(%d)\n", reta_size, tbl_size);
1343                 return -EINVAL;
1344         }
1345
1346         for (i = 0; i < reta_size; i++) {
1347                 struct bnxt_rx_queue *rxq;
1348
1349                 idx = i / RTE_RETA_GROUP_SIZE;
1350                 sft = i % RTE_RETA_GROUP_SIZE;
1351
1352                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1353                         continue;
1354
1355                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1356                 if (!rxq) {
1357                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1358                         return -EINVAL;
1359                 }
1360
1361                 if (BNXT_CHIP_THOR(bp)) {
1362                         vnic->rss_table[i * 2] =
1363                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1364                         vnic->rss_table[i * 2 + 1] =
1365                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1366                 } else {
1367                         vnic->rss_table[i] =
1368                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1369                 }
1370         }
1371
1372         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1373         return 0;
1374 }
1375
1376 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1377                               struct rte_eth_rss_reta_entry64 *reta_conf,
1378                               uint16_t reta_size)
1379 {
1380         struct bnxt *bp = eth_dev->data->dev_private;
1381         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1382         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1383         uint16_t idx, sft, i;
1384         int rc;
1385
1386         rc = is_bnxt_in_error(bp);
1387         if (rc)
1388                 return rc;
1389
1390         /* Retrieve from the default VNIC */
1391         if (!vnic)
1392                 return -EINVAL;
1393         if (!vnic->rss_table)
1394                 return -EINVAL;
1395
1396         if (reta_size != tbl_size) {
1397                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1398                         "(%d) must equal the size supported by the hardware "
1399                         "(%d)\n", reta_size, tbl_size);
1400                 return -EINVAL;
1401         }
1402
1403         for (idx = 0, i = 0; i < reta_size; i++) {
1404                 idx = i / RTE_RETA_GROUP_SIZE;
1405                 sft = i % RTE_RETA_GROUP_SIZE;
1406
1407                 if (reta_conf[idx].mask & (1ULL << sft)) {
1408                         uint16_t qid;
1409
1410                         if (BNXT_CHIP_THOR(bp))
1411                                 qid = bnxt_rss_to_qid(bp,
1412                                                       vnic->rss_table[i * 2]);
1413                         else
1414                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1415
1416                         if (qid == INVALID_HW_RING_ID) {
1417                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1418                                 return -EINVAL;
1419                         }
1420                         reta_conf[idx].reta[sft] = qid;
1421                 }
1422         }
1423
1424         return 0;
1425 }
1426
1427 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1428                                    struct rte_eth_rss_conf *rss_conf)
1429 {
1430         struct bnxt *bp = eth_dev->data->dev_private;
1431         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1432         struct bnxt_vnic_info *vnic;
1433         int rc;
1434
1435         rc = is_bnxt_in_error(bp);
1436         if (rc)
1437                 return rc;
1438
1439         /*
1440          * If RSS enablement were different than dev_configure,
1441          * then return -EINVAL
1442          */
1443         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1444                 if (!rss_conf->rss_hf)
1445                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1446         } else {
1447                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1448                         return -EINVAL;
1449         }
1450
1451         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1452         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1453
1454         /* Update the default RSS VNIC(s) */
1455         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1456         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1457
1458         /*
1459          * If hashkey is not specified, use the previously configured
1460          * hashkey
1461          */
1462         if (!rss_conf->rss_key)
1463                 goto rss_config;
1464
1465         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1466                 PMD_DRV_LOG(ERR,
1467                             "Invalid hashkey length, should be 16 bytes\n");
1468                 return -EINVAL;
1469         }
1470         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1471
1472 rss_config:
1473         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1474         return 0;
1475 }
1476
1477 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1478                                      struct rte_eth_rss_conf *rss_conf)
1479 {
1480         struct bnxt *bp = eth_dev->data->dev_private;
1481         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1482         int len, rc;
1483         uint32_t hash_types;
1484
1485         rc = is_bnxt_in_error(bp);
1486         if (rc)
1487                 return rc;
1488
1489         /* RSS configuration is the same for all VNICs */
1490         if (vnic && vnic->rss_hash_key) {
1491                 if (rss_conf->rss_key) {
1492                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1493                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1494                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1495                 }
1496
1497                 hash_types = vnic->hash_type;
1498                 rss_conf->rss_hf = 0;
1499                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1500                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1501                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1502                 }
1503                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1504                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1505                         hash_types &=
1506                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1507                 }
1508                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1509                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1510                         hash_types &=
1511                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1512                 }
1513                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1514                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1515                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1516                 }
1517                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1518                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1519                         hash_types &=
1520                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1521                 }
1522                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1523                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1524                         hash_types &=
1525                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1526                 }
1527                 if (hash_types) {
1528                         PMD_DRV_LOG(ERR,
1529                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1530                                 vnic->hash_type);
1531                         return -ENOTSUP;
1532                 }
1533         } else {
1534                 rss_conf->rss_hf = 0;
1535         }
1536         return 0;
1537 }
1538
1539 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1540                                struct rte_eth_fc_conf *fc_conf)
1541 {
1542         struct bnxt *bp = dev->data->dev_private;
1543         struct rte_eth_link link_info;
1544         int rc;
1545
1546         rc = is_bnxt_in_error(bp);
1547         if (rc)
1548                 return rc;
1549
1550         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1551         if (rc)
1552                 return rc;
1553
1554         memset(fc_conf, 0, sizeof(*fc_conf));
1555         if (bp->link_info.auto_pause)
1556                 fc_conf->autoneg = 1;
1557         switch (bp->link_info.pause) {
1558         case 0:
1559                 fc_conf->mode = RTE_FC_NONE;
1560                 break;
1561         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1562                 fc_conf->mode = RTE_FC_TX_PAUSE;
1563                 break;
1564         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1565                 fc_conf->mode = RTE_FC_RX_PAUSE;
1566                 break;
1567         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1568                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1569                 fc_conf->mode = RTE_FC_FULL;
1570                 break;
1571         }
1572         return 0;
1573 }
1574
1575 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1576                                struct rte_eth_fc_conf *fc_conf)
1577 {
1578         struct bnxt *bp = dev->data->dev_private;
1579         int rc;
1580
1581         rc = is_bnxt_in_error(bp);
1582         if (rc)
1583                 return rc;
1584
1585         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1586                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1587                 return -ENOTSUP;
1588         }
1589
1590         switch (fc_conf->mode) {
1591         case RTE_FC_NONE:
1592                 bp->link_info.auto_pause = 0;
1593                 bp->link_info.force_pause = 0;
1594                 break;
1595         case RTE_FC_RX_PAUSE:
1596                 if (fc_conf->autoneg) {
1597                         bp->link_info.auto_pause =
1598                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1599                         bp->link_info.force_pause = 0;
1600                 } else {
1601                         bp->link_info.auto_pause = 0;
1602                         bp->link_info.force_pause =
1603                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1604                 }
1605                 break;
1606         case RTE_FC_TX_PAUSE:
1607                 if (fc_conf->autoneg) {
1608                         bp->link_info.auto_pause =
1609                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1610                         bp->link_info.force_pause = 0;
1611                 } else {
1612                         bp->link_info.auto_pause = 0;
1613                         bp->link_info.force_pause =
1614                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1615                 }
1616                 break;
1617         case RTE_FC_FULL:
1618                 if (fc_conf->autoneg) {
1619                         bp->link_info.auto_pause =
1620                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1621                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1622                         bp->link_info.force_pause = 0;
1623                 } else {
1624                         bp->link_info.auto_pause = 0;
1625                         bp->link_info.force_pause =
1626                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1627                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1628                 }
1629                 break;
1630         }
1631         return bnxt_set_hwrm_link_config(bp, true);
1632 }
1633
1634 /* Add UDP tunneling port */
1635 static int
1636 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1637                          struct rte_eth_udp_tunnel *udp_tunnel)
1638 {
1639         struct bnxt *bp = eth_dev->data->dev_private;
1640         uint16_t tunnel_type = 0;
1641         int rc = 0;
1642
1643         rc = is_bnxt_in_error(bp);
1644         if (rc)
1645                 return rc;
1646
1647         switch (udp_tunnel->prot_type) {
1648         case RTE_TUNNEL_TYPE_VXLAN:
1649                 if (bp->vxlan_port_cnt) {
1650                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1651                                 udp_tunnel->udp_port);
1652                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1653                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1654                                 return -ENOSPC;
1655                         }
1656                         bp->vxlan_port_cnt++;
1657                         return 0;
1658                 }
1659                 tunnel_type =
1660                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1661                 bp->vxlan_port_cnt++;
1662                 break;
1663         case RTE_TUNNEL_TYPE_GENEVE:
1664                 if (bp->geneve_port_cnt) {
1665                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1666                                 udp_tunnel->udp_port);
1667                         if (bp->geneve_port != udp_tunnel->udp_port) {
1668                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1669                                 return -ENOSPC;
1670                         }
1671                         bp->geneve_port_cnt++;
1672                         return 0;
1673                 }
1674                 tunnel_type =
1675                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1676                 bp->geneve_port_cnt++;
1677                 break;
1678         default:
1679                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1680                 return -ENOTSUP;
1681         }
1682         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1683                                              tunnel_type);
1684         return rc;
1685 }
1686
1687 static int
1688 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1689                          struct rte_eth_udp_tunnel *udp_tunnel)
1690 {
1691         struct bnxt *bp = eth_dev->data->dev_private;
1692         uint16_t tunnel_type = 0;
1693         uint16_t port = 0;
1694         int rc = 0;
1695
1696         rc = is_bnxt_in_error(bp);
1697         if (rc)
1698                 return rc;
1699
1700         switch (udp_tunnel->prot_type) {
1701         case RTE_TUNNEL_TYPE_VXLAN:
1702                 if (!bp->vxlan_port_cnt) {
1703                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1704                         return -EINVAL;
1705                 }
1706                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1707                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1708                                 udp_tunnel->udp_port, bp->vxlan_port);
1709                         return -EINVAL;
1710                 }
1711                 if (--bp->vxlan_port_cnt)
1712                         return 0;
1713
1714                 tunnel_type =
1715                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1716                 port = bp->vxlan_fw_dst_port_id;
1717                 break;
1718         case RTE_TUNNEL_TYPE_GENEVE:
1719                 if (!bp->geneve_port_cnt) {
1720                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1721                         return -EINVAL;
1722                 }
1723                 if (bp->geneve_port != udp_tunnel->udp_port) {
1724                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1725                                 udp_tunnel->udp_port, bp->geneve_port);
1726                         return -EINVAL;
1727                 }
1728                 if (--bp->geneve_port_cnt)
1729                         return 0;
1730
1731                 tunnel_type =
1732                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1733                 port = bp->geneve_fw_dst_port_id;
1734                 break;
1735         default:
1736                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1737                 return -ENOTSUP;
1738         }
1739
1740         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1741         if (!rc) {
1742                 if (tunnel_type ==
1743                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1744                         bp->vxlan_port = 0;
1745                 if (tunnel_type ==
1746                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1747                         bp->geneve_port = 0;
1748         }
1749         return rc;
1750 }
1751
1752 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1753 {
1754         struct bnxt_filter_info *filter;
1755         struct bnxt_vnic_info *vnic;
1756         int rc = 0;
1757         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1758
1759         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1760         filter = STAILQ_FIRST(&vnic->filter);
1761         while (filter) {
1762                 /* Search for this matching MAC+VLAN filter */
1763                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1764                         /* Delete the filter */
1765                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1766                         if (rc)
1767                                 return rc;
1768                         STAILQ_REMOVE(&vnic->filter, filter,
1769                                       bnxt_filter_info, next);
1770                         bnxt_free_filter(bp, filter);
1771                         PMD_DRV_LOG(INFO,
1772                                     "Deleted vlan filter for %d\n",
1773                                     vlan_id);
1774                         return 0;
1775                 }
1776                 filter = STAILQ_NEXT(filter, next);
1777         }
1778         return -ENOENT;
1779 }
1780
1781 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1782 {
1783         struct bnxt_filter_info *filter;
1784         struct bnxt_vnic_info *vnic;
1785         int rc = 0;
1786         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1787                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1788         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1789
1790         /* Implementation notes on the use of VNIC in this command:
1791          *
1792          * By default, these filters belong to default vnic for the function.
1793          * Once these filters are set up, only destination VNIC can be modified.
1794          * If the destination VNIC is not specified in this command,
1795          * then the HWRM shall only create an l2 context id.
1796          */
1797
1798         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1799         filter = STAILQ_FIRST(&vnic->filter);
1800         /* Check if the VLAN has already been added */
1801         while (filter) {
1802                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1803                         return -EEXIST;
1804
1805                 filter = STAILQ_NEXT(filter, next);
1806         }
1807
1808         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1809          * command to create MAC+VLAN filter with the right flags, enables set.
1810          */
1811         filter = bnxt_alloc_filter(bp);
1812         if (!filter) {
1813                 PMD_DRV_LOG(ERR,
1814                             "MAC/VLAN filter alloc failed\n");
1815                 return -ENOMEM;
1816         }
1817         /* MAC + VLAN ID filter */
1818         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1819          * untagged packets are received
1820          *
1821          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1822          * packets and only the programmed vlan's packets are received
1823          */
1824         filter->l2_ivlan = vlan_id;
1825         filter->l2_ivlan_mask = 0x0FFF;
1826         filter->enables |= en;
1827         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1828
1829         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1830         if (rc) {
1831                 /* Free the newly allocated filter as we were
1832                  * not able to create the filter in hardware.
1833                  */
1834                 bnxt_free_filter(bp, filter);
1835                 return rc;
1836         }
1837
1838         filter->mac_index = 0;
1839         /* Add this new filter to the list */
1840         if (vlan_id == 0)
1841                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1842         else
1843                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1844
1845         PMD_DRV_LOG(INFO,
1846                     "Added Vlan filter for %d\n", vlan_id);
1847         return rc;
1848 }
1849
1850 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1851                 uint16_t vlan_id, int on)
1852 {
1853         struct bnxt *bp = eth_dev->data->dev_private;
1854         int rc;
1855
1856         rc = is_bnxt_in_error(bp);
1857         if (rc)
1858                 return rc;
1859
1860         /* These operations apply to ALL existing MAC/VLAN filters */
1861         if (on)
1862                 return bnxt_add_vlan_filter(bp, vlan_id);
1863         else
1864                 return bnxt_del_vlan_filter(bp, vlan_id);
1865 }
1866
1867 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1868                                     struct bnxt_vnic_info *vnic)
1869 {
1870         struct bnxt_filter_info *filter;
1871         int rc;
1872
1873         filter = STAILQ_FIRST(&vnic->filter);
1874         while (filter) {
1875                 if (filter->mac_index == 0 &&
1876                     !memcmp(filter->l2_addr, bp->mac_addr,
1877                             RTE_ETHER_ADDR_LEN)) {
1878                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1879                         if (!rc) {
1880                                 STAILQ_REMOVE(&vnic->filter, filter,
1881                                               bnxt_filter_info, next);
1882                                 bnxt_free_filter(bp, filter);
1883                         }
1884                         return rc;
1885                 }
1886                 filter = STAILQ_NEXT(filter, next);
1887         }
1888         return 0;
1889 }
1890
1891 static int
1892 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
1893 {
1894         struct bnxt_vnic_info *vnic;
1895         unsigned int i;
1896         int rc;
1897
1898         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1899         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1900                 /* Remove any VLAN filters programmed */
1901                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1902                         bnxt_del_vlan_filter(bp, i);
1903
1904                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1905                 if (rc)
1906                         return rc;
1907         } else {
1908                 /* Default filter will allow packets that match the
1909                  * dest mac. So, it has to be deleted, otherwise, we
1910                  * will endup receiving vlan packets for which the
1911                  * filter is not programmed, when hw-vlan-filter
1912                  * configuration is ON
1913                  */
1914                 bnxt_del_dflt_mac_filter(bp, vnic);
1915                 /* This filter will allow only untagged packets */
1916                 bnxt_add_vlan_filter(bp, 0);
1917         }
1918         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1919                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1920
1921         return 0;
1922 }
1923
1924 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
1925 {
1926         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
1927         unsigned int i;
1928         int rc;
1929
1930         /* Destroy vnic filters and vnic */
1931         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1932             DEV_RX_OFFLOAD_VLAN_FILTER) {
1933                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1934                         bnxt_del_vlan_filter(bp, i);
1935         }
1936         bnxt_del_dflt_mac_filter(bp, vnic);
1937
1938         rc = bnxt_hwrm_vnic_free(bp, vnic);
1939         if (rc)
1940                 return rc;
1941
1942         rte_free(vnic->fw_grp_ids);
1943         vnic->fw_grp_ids = NULL;
1944
1945         return 0;
1946 }
1947
1948 static int
1949 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
1950 {
1951         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1952         int rc;
1953
1954         /* Destroy, recreate and reconfigure the default vnic */
1955         rc = bnxt_free_one_vnic(bp, 0);
1956         if (rc)
1957                 return rc;
1958
1959         /* default vnic 0 */
1960         rc = bnxt_setup_one_vnic(bp, 0);
1961         if (rc)
1962                 return rc;
1963
1964         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1965             DEV_RX_OFFLOAD_VLAN_FILTER) {
1966                 rc = bnxt_add_vlan_filter(bp, 0);
1967                 bnxt_restore_vlan_filters(bp);
1968         } else {
1969                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1970         }
1971
1972         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1973         if (rc)
1974                 return rc;
1975
1976         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1977                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1978
1979         return rc;
1980 }
1981
1982 static int
1983 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1984 {
1985         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1986         struct bnxt *bp = dev->data->dev_private;
1987         int rc;
1988
1989         rc = is_bnxt_in_error(bp);
1990         if (rc)
1991                 return rc;
1992
1993         /* Filter settings will get applied when port is started */
1994         if (bp->dev_stopped == 1)
1995                 return 0;
1996
1997         if (mask & ETH_VLAN_FILTER_MASK) {
1998                 /* Enable or disable VLAN filtering */
1999                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2000                 if (rc)
2001                         return rc;
2002         }
2003
2004         if (mask & ETH_VLAN_STRIP_MASK) {
2005                 /* Enable or disable VLAN stripping */
2006                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2007                 if (rc)
2008                         return rc;
2009         }
2010
2011         if (mask & ETH_VLAN_EXTEND_MASK) {
2012                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2013                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2014                 else
2015                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2016         }
2017
2018         return 0;
2019 }
2020
2021 static int
2022 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2023                       uint16_t tpid)
2024 {
2025         struct bnxt *bp = dev->data->dev_private;
2026         int qinq = dev->data->dev_conf.rxmode.offloads &
2027                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2028
2029         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2030             vlan_type != ETH_VLAN_TYPE_OUTER) {
2031                 PMD_DRV_LOG(ERR,
2032                             "Unsupported vlan type.");
2033                 return -EINVAL;
2034         }
2035         if (!qinq) {
2036                 PMD_DRV_LOG(ERR,
2037                             "QinQ not enabled. Needs to be ON as we can "
2038                             "accelerate only outer vlan\n");
2039                 return -EINVAL;
2040         }
2041
2042         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2043                 switch (tpid) {
2044                 case RTE_ETHER_TYPE_QINQ:
2045                         bp->outer_tpid_bd =
2046                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2047                                 break;
2048                 case RTE_ETHER_TYPE_VLAN:
2049                         bp->outer_tpid_bd =
2050                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2051                                 break;
2052                 case 0x9100:
2053                         bp->outer_tpid_bd =
2054                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2055                                 break;
2056                 case 0x9200:
2057                         bp->outer_tpid_bd =
2058                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2059                                 break;
2060                 case 0x9300:
2061                         bp->outer_tpid_bd =
2062                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2063                                 break;
2064                 default:
2065                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2066                         return -EINVAL;
2067                 }
2068                 bp->outer_tpid_bd |= tpid;
2069                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2070         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2071                 PMD_DRV_LOG(ERR,
2072                             "Can accelerate only outer vlan in QinQ\n");
2073                 return -EINVAL;
2074         }
2075
2076         return 0;
2077 }
2078
2079 static int
2080 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2081                              struct rte_ether_addr *addr)
2082 {
2083         struct bnxt *bp = dev->data->dev_private;
2084         /* Default Filter is tied to VNIC 0 */
2085         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2086         int rc;
2087
2088         rc = is_bnxt_in_error(bp);
2089         if (rc)
2090                 return rc;
2091
2092         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2093                 return -EPERM;
2094
2095         if (rte_is_zero_ether_addr(addr))
2096                 return -EINVAL;
2097
2098         /* Check if the requested MAC is already added */
2099         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2100                 return 0;
2101
2102         /* Destroy filter and re-create it */
2103         bnxt_del_dflt_mac_filter(bp, vnic);
2104
2105         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2106         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2107                 /* This filter will allow only untagged packets */
2108                 rc = bnxt_add_vlan_filter(bp, 0);
2109         } else {
2110                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2111         }
2112
2113         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2114         return rc;
2115 }
2116
2117 static int
2118 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2119                           struct rte_ether_addr *mc_addr_set,
2120                           uint32_t nb_mc_addr)
2121 {
2122         struct bnxt *bp = eth_dev->data->dev_private;
2123         char *mc_addr_list = (char *)mc_addr_set;
2124         struct bnxt_vnic_info *vnic;
2125         uint32_t off = 0, i = 0;
2126         int rc;
2127
2128         rc = is_bnxt_in_error(bp);
2129         if (rc)
2130                 return rc;
2131
2132         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2133
2134         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2135                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2136                 goto allmulti;
2137         }
2138
2139         /* TODO Check for Duplicate mcast addresses */
2140         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2141         for (i = 0; i < nb_mc_addr; i++) {
2142                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2143                         RTE_ETHER_ADDR_LEN);
2144                 off += RTE_ETHER_ADDR_LEN;
2145         }
2146
2147         vnic->mc_addr_cnt = i;
2148         if (vnic->mc_addr_cnt)
2149                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2150         else
2151                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2152
2153 allmulti:
2154         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2155 }
2156
2157 static int
2158 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2159 {
2160         struct bnxt *bp = dev->data->dev_private;
2161         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2162         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2163         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2164         int ret;
2165
2166         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2167                         fw_major, fw_minor, fw_updt);
2168
2169         ret += 1; /* add the size of '\0' */
2170         if (fw_size < (uint32_t)ret)
2171                 return ret;
2172         else
2173                 return 0;
2174 }
2175
2176 static void
2177 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2178         struct rte_eth_rxq_info *qinfo)
2179 {
2180         struct bnxt *bp = dev->data->dev_private;
2181         struct bnxt_rx_queue *rxq;
2182
2183         if (is_bnxt_in_error(bp))
2184                 return;
2185
2186         rxq = dev->data->rx_queues[queue_id];
2187
2188         qinfo->mp = rxq->mb_pool;
2189         qinfo->scattered_rx = dev->data->scattered_rx;
2190         qinfo->nb_desc = rxq->nb_rx_desc;
2191
2192         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2193         qinfo->conf.rx_drop_en = 0;
2194         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2195 }
2196
2197 static void
2198 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2199         struct rte_eth_txq_info *qinfo)
2200 {
2201         struct bnxt *bp = dev->data->dev_private;
2202         struct bnxt_tx_queue *txq;
2203
2204         if (is_bnxt_in_error(bp))
2205                 return;
2206
2207         txq = dev->data->tx_queues[queue_id];
2208
2209         qinfo->nb_desc = txq->nb_tx_desc;
2210
2211         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2212         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2213         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2214
2215         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2216         qinfo->conf.tx_rs_thresh = 0;
2217         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2218 }
2219
2220 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2221 {
2222         struct bnxt *bp = eth_dev->data->dev_private;
2223         uint32_t new_pkt_size;
2224         uint32_t rc = 0;
2225         uint32_t i;
2226
2227         rc = is_bnxt_in_error(bp);
2228         if (rc)
2229                 return rc;
2230
2231         /* Exit if receive queues are not configured yet */
2232         if (!eth_dev->data->nb_rx_queues)
2233                 return rc;
2234
2235         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2236                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2237
2238 #ifdef RTE_ARCH_X86
2239         /*
2240          * If vector-mode tx/rx is active, disallow any MTU change that would
2241          * require scattered receive support.
2242          */
2243         if (eth_dev->data->dev_started &&
2244             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2245              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2246             (new_pkt_size >
2247              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2248                 PMD_DRV_LOG(ERR,
2249                             "MTU change would require scattered rx support. ");
2250                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2251                 return -EINVAL;
2252         }
2253 #endif
2254
2255         if (new_mtu > RTE_ETHER_MTU) {
2256                 bp->flags |= BNXT_FLAG_JUMBO;
2257                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2258                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2259         } else {
2260                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2261                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2262                 bp->flags &= ~BNXT_FLAG_JUMBO;
2263         }
2264
2265         /* Is there a change in mtu setting? */
2266         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2267                 return rc;
2268
2269         for (i = 0; i < bp->nr_vnics; i++) {
2270                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2271                 uint16_t size = 0;
2272
2273                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2274                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2275                 if (rc)
2276                         break;
2277
2278                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2279                 size -= RTE_PKTMBUF_HEADROOM;
2280
2281                 if (size < new_mtu) {
2282                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2283                         if (rc)
2284                                 return rc;
2285                 }
2286         }
2287
2288         if (!rc)
2289                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2290
2291         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2292
2293         return rc;
2294 }
2295
2296 static int
2297 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2298 {
2299         struct bnxt *bp = dev->data->dev_private;
2300         uint16_t vlan = bp->vlan;
2301         int rc;
2302
2303         rc = is_bnxt_in_error(bp);
2304         if (rc)
2305                 return rc;
2306
2307         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2308                 PMD_DRV_LOG(ERR,
2309                         "PVID cannot be modified for this function\n");
2310                 return -ENOTSUP;
2311         }
2312         bp->vlan = on ? pvid : 0;
2313
2314         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2315         if (rc)
2316                 bp->vlan = vlan;
2317         return rc;
2318 }
2319
2320 static int
2321 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2322 {
2323         struct bnxt *bp = dev->data->dev_private;
2324         int rc;
2325
2326         rc = is_bnxt_in_error(bp);
2327         if (rc)
2328                 return rc;
2329
2330         return bnxt_hwrm_port_led_cfg(bp, true);
2331 }
2332
2333 static int
2334 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2335 {
2336         struct bnxt *bp = dev->data->dev_private;
2337         int rc;
2338
2339         rc = is_bnxt_in_error(bp);
2340         if (rc)
2341                 return rc;
2342
2343         return bnxt_hwrm_port_led_cfg(bp, false);
2344 }
2345
2346 static uint32_t
2347 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2348 {
2349         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2350         uint32_t desc = 0, raw_cons = 0, cons;
2351         struct bnxt_cp_ring_info *cpr;
2352         struct bnxt_rx_queue *rxq;
2353         struct rx_pkt_cmpl *rxcmp;
2354         int rc;
2355
2356         rc = is_bnxt_in_error(bp);
2357         if (rc)
2358                 return rc;
2359
2360         rxq = dev->data->rx_queues[rx_queue_id];
2361         cpr = rxq->cp_ring;
2362         raw_cons = cpr->cp_raw_cons;
2363
2364         while (1) {
2365                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2366                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2367                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2368
2369                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2370                         break;
2371                 } else {
2372                         raw_cons++;
2373                         desc++;
2374                 }
2375         }
2376
2377         return desc;
2378 }
2379
2380 static int
2381 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2382 {
2383         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2384         struct bnxt_rx_ring_info *rxr;
2385         struct bnxt_cp_ring_info *cpr;
2386         struct bnxt_sw_rx_bd *rx_buf;
2387         struct rx_pkt_cmpl *rxcmp;
2388         uint32_t cons, cp_cons;
2389         int rc;
2390
2391         if (!rxq)
2392                 return -EINVAL;
2393
2394         rc = is_bnxt_in_error(rxq->bp);
2395         if (rc)
2396                 return rc;
2397
2398         cpr = rxq->cp_ring;
2399         rxr = rxq->rx_ring;
2400
2401         if (offset >= rxq->nb_rx_desc)
2402                 return -EINVAL;
2403
2404         cons = RING_CMP(cpr->cp_ring_struct, offset);
2405         cp_cons = cpr->cp_raw_cons;
2406         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2407
2408         if (cons > cp_cons) {
2409                 if (CMPL_VALID(rxcmp, cpr->valid))
2410                         return RTE_ETH_RX_DESC_DONE;
2411         } else {
2412                 if (CMPL_VALID(rxcmp, !cpr->valid))
2413                         return RTE_ETH_RX_DESC_DONE;
2414         }
2415         rx_buf = &rxr->rx_buf_ring[cons];
2416         if (rx_buf->mbuf == NULL)
2417                 return RTE_ETH_RX_DESC_UNAVAIL;
2418
2419
2420         return RTE_ETH_RX_DESC_AVAIL;
2421 }
2422
2423 static int
2424 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2425 {
2426         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2427         struct bnxt_tx_ring_info *txr;
2428         struct bnxt_cp_ring_info *cpr;
2429         struct bnxt_sw_tx_bd *tx_buf;
2430         struct tx_pkt_cmpl *txcmp;
2431         uint32_t cons, cp_cons;
2432         int rc;
2433
2434         if (!txq)
2435                 return -EINVAL;
2436
2437         rc = is_bnxt_in_error(txq->bp);
2438         if (rc)
2439                 return rc;
2440
2441         cpr = txq->cp_ring;
2442         txr = txq->tx_ring;
2443
2444         if (offset >= txq->nb_tx_desc)
2445                 return -EINVAL;
2446
2447         cons = RING_CMP(cpr->cp_ring_struct, offset);
2448         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2449         cp_cons = cpr->cp_raw_cons;
2450
2451         if (cons > cp_cons) {
2452                 if (CMPL_VALID(txcmp, cpr->valid))
2453                         return RTE_ETH_TX_DESC_UNAVAIL;
2454         } else {
2455                 if (CMPL_VALID(txcmp, !cpr->valid))
2456                         return RTE_ETH_TX_DESC_UNAVAIL;
2457         }
2458         tx_buf = &txr->tx_buf_ring[cons];
2459         if (tx_buf->mbuf == NULL)
2460                 return RTE_ETH_TX_DESC_DONE;
2461
2462         return RTE_ETH_TX_DESC_FULL;
2463 }
2464
2465 static struct bnxt_filter_info *
2466 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2467                                 struct rte_eth_ethertype_filter *efilter,
2468                                 struct bnxt_vnic_info *vnic0,
2469                                 struct bnxt_vnic_info *vnic,
2470                                 int *ret)
2471 {
2472         struct bnxt_filter_info *mfilter = NULL;
2473         int match = 0;
2474         *ret = 0;
2475
2476         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2477                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2478                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2479                         " ethertype filter.", efilter->ether_type);
2480                 *ret = -EINVAL;
2481                 goto exit;
2482         }
2483         if (efilter->queue >= bp->rx_nr_rings) {
2484                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2485                 *ret = -EINVAL;
2486                 goto exit;
2487         }
2488
2489         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2490         vnic = &bp->vnic_info[efilter->queue];
2491         if (vnic == NULL) {
2492                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2493                 *ret = -EINVAL;
2494                 goto exit;
2495         }
2496
2497         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2498                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2499                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2500                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2501                              mfilter->flags ==
2502                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2503                              mfilter->ethertype == efilter->ether_type)) {
2504                                 match = 1;
2505                                 break;
2506                         }
2507                 }
2508         } else {
2509                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2510                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2511                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2512                              mfilter->ethertype == efilter->ether_type &&
2513                              mfilter->flags ==
2514                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2515                                 match = 1;
2516                                 break;
2517                         }
2518         }
2519
2520         if (match)
2521                 *ret = -EEXIST;
2522
2523 exit:
2524         return mfilter;
2525 }
2526
2527 static int
2528 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2529                         enum rte_filter_op filter_op,
2530                         void *arg)
2531 {
2532         struct bnxt *bp = dev->data->dev_private;
2533         struct rte_eth_ethertype_filter *efilter =
2534                         (struct rte_eth_ethertype_filter *)arg;
2535         struct bnxt_filter_info *bfilter, *filter1;
2536         struct bnxt_vnic_info *vnic, *vnic0;
2537         int ret;
2538
2539         if (filter_op == RTE_ETH_FILTER_NOP)
2540                 return 0;
2541
2542         if (arg == NULL) {
2543                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2544                             filter_op);
2545                 return -EINVAL;
2546         }
2547
2548         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2549         vnic = &bp->vnic_info[efilter->queue];
2550
2551         switch (filter_op) {
2552         case RTE_ETH_FILTER_ADD:
2553                 bnxt_match_and_validate_ether_filter(bp, efilter,
2554                                                         vnic0, vnic, &ret);
2555                 if (ret < 0)
2556                         return ret;
2557
2558                 bfilter = bnxt_get_unused_filter(bp);
2559                 if (bfilter == NULL) {
2560                         PMD_DRV_LOG(ERR,
2561                                 "Not enough resources for a new filter.\n");
2562                         return -ENOMEM;
2563                 }
2564                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2565                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2566                        RTE_ETHER_ADDR_LEN);
2567                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2568                        RTE_ETHER_ADDR_LEN);
2569                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2570                 bfilter->ethertype = efilter->ether_type;
2571                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2572
2573                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2574                 if (filter1 == NULL) {
2575                         ret = -EINVAL;
2576                         goto cleanup;
2577                 }
2578                 bfilter->enables |=
2579                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2580                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2581
2582                 bfilter->dst_id = vnic->fw_vnic_id;
2583
2584                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2585                         bfilter->flags =
2586                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2587                 }
2588
2589                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2590                 if (ret)
2591                         goto cleanup;
2592                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2593                 break;
2594         case RTE_ETH_FILTER_DELETE:
2595                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2596                                                         vnic0, vnic, &ret);
2597                 if (ret == -EEXIST) {
2598                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2599
2600                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2601                                       next);
2602                         bnxt_free_filter(bp, filter1);
2603                 } else if (ret == 0) {
2604                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2605                 }
2606                 break;
2607         default:
2608                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2609                 ret = -EINVAL;
2610                 goto error;
2611         }
2612         return ret;
2613 cleanup:
2614         bnxt_free_filter(bp, bfilter);
2615 error:
2616         return ret;
2617 }
2618
2619 static inline int
2620 parse_ntuple_filter(struct bnxt *bp,
2621                     struct rte_eth_ntuple_filter *nfilter,
2622                     struct bnxt_filter_info *bfilter)
2623 {
2624         uint32_t en = 0;
2625
2626         if (nfilter->queue >= bp->rx_nr_rings) {
2627                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2628                 return -EINVAL;
2629         }
2630
2631         switch (nfilter->dst_port_mask) {
2632         case UINT16_MAX:
2633                 bfilter->dst_port_mask = -1;
2634                 bfilter->dst_port = nfilter->dst_port;
2635                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2636                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2637                 break;
2638         default:
2639                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2640                 return -EINVAL;
2641         }
2642
2643         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2644         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2645
2646         switch (nfilter->proto_mask) {
2647         case UINT8_MAX:
2648                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2649                         bfilter->ip_protocol = 17;
2650                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2651                         bfilter->ip_protocol = 6;
2652                 else
2653                         return -EINVAL;
2654                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2655                 break;
2656         default:
2657                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2658                 return -EINVAL;
2659         }
2660
2661         switch (nfilter->dst_ip_mask) {
2662         case UINT32_MAX:
2663                 bfilter->dst_ipaddr_mask[0] = -1;
2664                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2665                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2666                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2667                 break;
2668         default:
2669                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2670                 return -EINVAL;
2671         }
2672
2673         switch (nfilter->src_ip_mask) {
2674         case UINT32_MAX:
2675                 bfilter->src_ipaddr_mask[0] = -1;
2676                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2677                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2678                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2679                 break;
2680         default:
2681                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2682                 return -EINVAL;
2683         }
2684
2685         switch (nfilter->src_port_mask) {
2686         case UINT16_MAX:
2687                 bfilter->src_port_mask = -1;
2688                 bfilter->src_port = nfilter->src_port;
2689                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2690                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2691                 break;
2692         default:
2693                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2694                 return -EINVAL;
2695         }
2696
2697         bfilter->enables = en;
2698         return 0;
2699 }
2700
2701 static struct bnxt_filter_info*
2702 bnxt_match_ntuple_filter(struct bnxt *bp,
2703                          struct bnxt_filter_info *bfilter,
2704                          struct bnxt_vnic_info **mvnic)
2705 {
2706         struct bnxt_filter_info *mfilter = NULL;
2707         int i;
2708
2709         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2710                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2711                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2712                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2713                             bfilter->src_ipaddr_mask[0] ==
2714                             mfilter->src_ipaddr_mask[0] &&
2715                             bfilter->src_port == mfilter->src_port &&
2716                             bfilter->src_port_mask == mfilter->src_port_mask &&
2717                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2718                             bfilter->dst_ipaddr_mask[0] ==
2719                             mfilter->dst_ipaddr_mask[0] &&
2720                             bfilter->dst_port == mfilter->dst_port &&
2721                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2722                             bfilter->flags == mfilter->flags &&
2723                             bfilter->enables == mfilter->enables) {
2724                                 if (mvnic)
2725                                         *mvnic = vnic;
2726                                 return mfilter;
2727                         }
2728                 }
2729         }
2730         return NULL;
2731 }
2732
2733 static int
2734 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2735                        struct rte_eth_ntuple_filter *nfilter,
2736                        enum rte_filter_op filter_op)
2737 {
2738         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2739         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2740         int ret;
2741
2742         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2743                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2744                 return -EINVAL;
2745         }
2746
2747         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2748                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2749                 return -EINVAL;
2750         }
2751
2752         bfilter = bnxt_get_unused_filter(bp);
2753         if (bfilter == NULL) {
2754                 PMD_DRV_LOG(ERR,
2755                         "Not enough resources for a new filter.\n");
2756                 return -ENOMEM;
2757         }
2758         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2759         if (ret < 0)
2760                 goto free_filter;
2761
2762         vnic = &bp->vnic_info[nfilter->queue];
2763         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2764         filter1 = STAILQ_FIRST(&vnic0->filter);
2765         if (filter1 == NULL) {
2766                 ret = -EINVAL;
2767                 goto free_filter;
2768         }
2769
2770         bfilter->dst_id = vnic->fw_vnic_id;
2771         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2772         bfilter->enables |=
2773                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2774         bfilter->ethertype = 0x800;
2775         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2776
2777         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2778
2779         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2780             bfilter->dst_id == mfilter->dst_id) {
2781                 PMD_DRV_LOG(ERR, "filter exists.\n");
2782                 ret = -EEXIST;
2783                 goto free_filter;
2784         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2785                    bfilter->dst_id != mfilter->dst_id) {
2786                 mfilter->dst_id = vnic->fw_vnic_id;
2787                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2788                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2789                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2790                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2791                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2792                 goto free_filter;
2793         }
2794         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2795                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2796                 ret = -ENOENT;
2797                 goto free_filter;
2798         }
2799
2800         if (filter_op == RTE_ETH_FILTER_ADD) {
2801                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2802                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2803                 if (ret)
2804                         goto free_filter;
2805                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2806         } else {
2807                 if (mfilter == NULL) {
2808                         /* This should not happen. But for Coverity! */
2809                         ret = -ENOENT;
2810                         goto free_filter;
2811                 }
2812                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2813
2814                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2815                 bnxt_free_filter(bp, mfilter);
2816                 bnxt_free_filter(bp, bfilter);
2817         }
2818
2819         return 0;
2820 free_filter:
2821         bnxt_free_filter(bp, bfilter);
2822         return ret;
2823 }
2824
2825 static int
2826 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2827                         enum rte_filter_op filter_op,
2828                         void *arg)
2829 {
2830         struct bnxt *bp = dev->data->dev_private;
2831         int ret;
2832
2833         if (filter_op == RTE_ETH_FILTER_NOP)
2834                 return 0;
2835
2836         if (arg == NULL) {
2837                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2838                             filter_op);
2839                 return -EINVAL;
2840         }
2841
2842         switch (filter_op) {
2843         case RTE_ETH_FILTER_ADD:
2844                 ret = bnxt_cfg_ntuple_filter(bp,
2845                         (struct rte_eth_ntuple_filter *)arg,
2846                         filter_op);
2847                 break;
2848         case RTE_ETH_FILTER_DELETE:
2849                 ret = bnxt_cfg_ntuple_filter(bp,
2850                         (struct rte_eth_ntuple_filter *)arg,
2851                         filter_op);
2852                 break;
2853         default:
2854                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2855                 ret = -EINVAL;
2856                 break;
2857         }
2858         return ret;
2859 }
2860
2861 static int
2862 bnxt_parse_fdir_filter(struct bnxt *bp,
2863                        struct rte_eth_fdir_filter *fdir,
2864                        struct bnxt_filter_info *filter)
2865 {
2866         enum rte_fdir_mode fdir_mode =
2867                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2868         struct bnxt_vnic_info *vnic0, *vnic;
2869         struct bnxt_filter_info *filter1;
2870         uint32_t en = 0;
2871         int i;
2872
2873         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2874                 return -EINVAL;
2875
2876         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2877         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2878
2879         switch (fdir->input.flow_type) {
2880         case RTE_ETH_FLOW_IPV4:
2881         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2882                 /* FALLTHROUGH */
2883                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2884                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2885                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2886                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2887                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2888                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2889                 filter->ip_addr_type =
2890                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2891                 filter->src_ipaddr_mask[0] = 0xffffffff;
2892                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2893                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2894                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2895                 filter->ethertype = 0x800;
2896                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2897                 break;
2898         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2899                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2900                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2901                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2902                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2903                 filter->dst_port_mask = 0xffff;
2904                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2905                 filter->src_port_mask = 0xffff;
2906                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2907                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2908                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2909                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2910                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2911                 filter->ip_protocol = 6;
2912                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2913                 filter->ip_addr_type =
2914                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2915                 filter->src_ipaddr_mask[0] = 0xffffffff;
2916                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2917                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2918                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2919                 filter->ethertype = 0x800;
2920                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2921                 break;
2922         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2923                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2924                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2925                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2926                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2927                 filter->dst_port_mask = 0xffff;
2928                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2929                 filter->src_port_mask = 0xffff;
2930                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2931                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2932                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2933                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2934                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2935                 filter->ip_protocol = 17;
2936                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2937                 filter->ip_addr_type =
2938                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2939                 filter->src_ipaddr_mask[0] = 0xffffffff;
2940                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2941                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2942                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2943                 filter->ethertype = 0x800;
2944                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2945                 break;
2946         case RTE_ETH_FLOW_IPV6:
2947         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2948                 /* FALLTHROUGH */
2949                 filter->ip_addr_type =
2950                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2951                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2952                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2953                 rte_memcpy(filter->src_ipaddr,
2954                            fdir->input.flow.ipv6_flow.src_ip, 16);
2955                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2956                 rte_memcpy(filter->dst_ipaddr,
2957                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2958                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2959                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2960                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2961                 memset(filter->src_ipaddr_mask, 0xff, 16);
2962                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2963                 filter->ethertype = 0x86dd;
2964                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2965                 break;
2966         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2967                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2968                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2969                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2970                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2971                 filter->dst_port_mask = 0xffff;
2972                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2973                 filter->src_port_mask = 0xffff;
2974                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2975                 filter->ip_addr_type =
2976                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2977                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2978                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2979                 rte_memcpy(filter->src_ipaddr,
2980                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2981                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2982                 rte_memcpy(filter->dst_ipaddr,
2983                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2984                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2985                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2986                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2987                 memset(filter->src_ipaddr_mask, 0xff, 16);
2988                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2989                 filter->ethertype = 0x86dd;
2990                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2991                 break;
2992         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2993                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2994                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2995                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2996                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2997                 filter->dst_port_mask = 0xffff;
2998                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2999                 filter->src_port_mask = 0xffff;
3000                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3001                 filter->ip_addr_type =
3002                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3003                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3004                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3005                 rte_memcpy(filter->src_ipaddr,
3006                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3007                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3008                 rte_memcpy(filter->dst_ipaddr,
3009                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3010                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3011                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3012                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3013                 memset(filter->src_ipaddr_mask, 0xff, 16);
3014                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3015                 filter->ethertype = 0x86dd;
3016                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3017                 break;
3018         case RTE_ETH_FLOW_L2_PAYLOAD:
3019                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3020                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3021                 break;
3022         case RTE_ETH_FLOW_VXLAN:
3023                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3024                         return -EINVAL;
3025                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3026                 filter->tunnel_type =
3027                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3028                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3029                 break;
3030         case RTE_ETH_FLOW_NVGRE:
3031                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3032                         return -EINVAL;
3033                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3034                 filter->tunnel_type =
3035                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3036                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3037                 break;
3038         case RTE_ETH_FLOW_UNKNOWN:
3039         case RTE_ETH_FLOW_RAW:
3040         case RTE_ETH_FLOW_FRAG_IPV4:
3041         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3042         case RTE_ETH_FLOW_FRAG_IPV6:
3043         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3044         case RTE_ETH_FLOW_IPV6_EX:
3045         case RTE_ETH_FLOW_IPV6_TCP_EX:
3046         case RTE_ETH_FLOW_IPV6_UDP_EX:
3047         case RTE_ETH_FLOW_GENEVE:
3048                 /* FALLTHROUGH */
3049         default:
3050                 return -EINVAL;
3051         }
3052
3053         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3054         vnic = &bp->vnic_info[fdir->action.rx_queue];
3055         if (vnic == NULL) {
3056                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3057                 return -EINVAL;
3058         }
3059
3060         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3061                 rte_memcpy(filter->dst_macaddr,
3062                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3063                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3064         }
3065
3066         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3067                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3068                 filter1 = STAILQ_FIRST(&vnic0->filter);
3069                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3070         } else {
3071                 filter->dst_id = vnic->fw_vnic_id;
3072                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3073                         if (filter->dst_macaddr[i] == 0x00)
3074                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3075                         else
3076                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3077         }
3078
3079         if (filter1 == NULL)
3080                 return -EINVAL;
3081
3082         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3083         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3084
3085         filter->enables = en;
3086
3087         return 0;
3088 }
3089
3090 static struct bnxt_filter_info *
3091 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3092                 struct bnxt_vnic_info **mvnic)
3093 {
3094         struct bnxt_filter_info *mf = NULL;
3095         int i;
3096
3097         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3098                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3099
3100                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3101                         if (mf->filter_type == nf->filter_type &&
3102                             mf->flags == nf->flags &&
3103                             mf->src_port == nf->src_port &&
3104                             mf->src_port_mask == nf->src_port_mask &&
3105                             mf->dst_port == nf->dst_port &&
3106                             mf->dst_port_mask == nf->dst_port_mask &&
3107                             mf->ip_protocol == nf->ip_protocol &&
3108                             mf->ip_addr_type == nf->ip_addr_type &&
3109                             mf->ethertype == nf->ethertype &&
3110                             mf->vni == nf->vni &&
3111                             mf->tunnel_type == nf->tunnel_type &&
3112                             mf->l2_ovlan == nf->l2_ovlan &&
3113                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3114                             mf->l2_ivlan == nf->l2_ivlan &&
3115                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3116                             !memcmp(mf->l2_addr, nf->l2_addr,
3117                                     RTE_ETHER_ADDR_LEN) &&
3118                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3119                                     RTE_ETHER_ADDR_LEN) &&
3120                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3121                                     RTE_ETHER_ADDR_LEN) &&
3122                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3123                                     RTE_ETHER_ADDR_LEN) &&
3124                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3125                                     sizeof(nf->src_ipaddr)) &&
3126                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3127                                     sizeof(nf->src_ipaddr_mask)) &&
3128                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3129                                     sizeof(nf->dst_ipaddr)) &&
3130                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3131                                     sizeof(nf->dst_ipaddr_mask))) {
3132                                 if (mvnic)
3133                                         *mvnic = vnic;
3134                                 return mf;
3135                         }
3136                 }
3137         }
3138         return NULL;
3139 }
3140
3141 static int
3142 bnxt_fdir_filter(struct rte_eth_dev *dev,
3143                  enum rte_filter_op filter_op,
3144                  void *arg)
3145 {
3146         struct bnxt *bp = dev->data->dev_private;
3147         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3148         struct bnxt_filter_info *filter, *match;
3149         struct bnxt_vnic_info *vnic, *mvnic;
3150         int ret = 0, i;
3151
3152         if (filter_op == RTE_ETH_FILTER_NOP)
3153                 return 0;
3154
3155         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3156                 return -EINVAL;
3157
3158         switch (filter_op) {
3159         case RTE_ETH_FILTER_ADD:
3160         case RTE_ETH_FILTER_DELETE:
3161                 /* FALLTHROUGH */
3162                 filter = bnxt_get_unused_filter(bp);
3163                 if (filter == NULL) {
3164                         PMD_DRV_LOG(ERR,
3165                                 "Not enough resources for a new flow.\n");
3166                         return -ENOMEM;
3167                 }
3168
3169                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3170                 if (ret != 0)
3171                         goto free_filter;
3172                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3173
3174                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3175                         vnic = &bp->vnic_info[0];
3176                 else
3177                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3178
3179                 match = bnxt_match_fdir(bp, filter, &mvnic);
3180                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3181                         if (match->dst_id == vnic->fw_vnic_id) {
3182                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3183                                 ret = -EEXIST;
3184                                 goto free_filter;
3185                         } else {
3186                                 match->dst_id = vnic->fw_vnic_id;
3187                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3188                                                                   match->dst_id,
3189                                                                   match);
3190                                 STAILQ_REMOVE(&mvnic->filter, match,
3191                                               bnxt_filter_info, next);
3192                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3193                                 PMD_DRV_LOG(ERR,
3194                                         "Filter with matching pattern exist\n");
3195                                 PMD_DRV_LOG(ERR,
3196                                         "Updated it to new destination q\n");
3197                                 goto free_filter;
3198                         }
3199                 }
3200                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3201                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3202                         ret = -ENOENT;
3203                         goto free_filter;
3204                 }
3205
3206                 if (filter_op == RTE_ETH_FILTER_ADD) {
3207                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3208                                                           filter->dst_id,
3209                                                           filter);
3210                         if (ret)
3211                                 goto free_filter;
3212                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3213                 } else {
3214                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3215                         STAILQ_REMOVE(&vnic->filter, match,
3216                                       bnxt_filter_info, next);
3217                         bnxt_free_filter(bp, match);
3218                         bnxt_free_filter(bp, filter);
3219                 }
3220                 break;
3221         case RTE_ETH_FILTER_FLUSH:
3222                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3223                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3224
3225                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3226                                 if (filter->filter_type ==
3227                                     HWRM_CFA_NTUPLE_FILTER) {
3228                                         ret =
3229                                         bnxt_hwrm_clear_ntuple_filter(bp,
3230                                                                       filter);
3231                                         STAILQ_REMOVE(&vnic->filter, filter,
3232                                                       bnxt_filter_info, next);
3233                                 }
3234                         }
3235                 }
3236                 return ret;
3237         case RTE_ETH_FILTER_UPDATE:
3238         case RTE_ETH_FILTER_STATS:
3239         case RTE_ETH_FILTER_INFO:
3240                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3241                 break;
3242         default:
3243                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3244                 ret = -EINVAL;
3245                 break;
3246         }
3247         return ret;
3248
3249 free_filter:
3250         bnxt_free_filter(bp, filter);
3251         return ret;
3252 }
3253
3254 static int
3255 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3256                     enum rte_filter_type filter_type,
3257                     enum rte_filter_op filter_op, void *arg)
3258 {
3259         int ret = 0;
3260
3261         ret = is_bnxt_in_error(dev->data->dev_private);
3262         if (ret)
3263                 return ret;
3264
3265         switch (filter_type) {
3266         case RTE_ETH_FILTER_TUNNEL:
3267                 PMD_DRV_LOG(ERR,
3268                         "filter type: %d: To be implemented\n", filter_type);
3269                 break;
3270         case RTE_ETH_FILTER_FDIR:
3271                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3272                 break;
3273         case RTE_ETH_FILTER_NTUPLE:
3274                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3275                 break;
3276         case RTE_ETH_FILTER_ETHERTYPE:
3277                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3278                 break;
3279         case RTE_ETH_FILTER_GENERIC:
3280                 if (filter_op != RTE_ETH_FILTER_GET)
3281                         return -EINVAL;
3282                 *(const void **)arg = &bnxt_flow_ops;
3283                 break;
3284         default:
3285                 PMD_DRV_LOG(ERR,
3286                         "Filter type (%d) not supported", filter_type);
3287                 ret = -EINVAL;
3288                 break;
3289         }
3290         return ret;
3291 }
3292
3293 static const uint32_t *
3294 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3295 {
3296         static const uint32_t ptypes[] = {
3297                 RTE_PTYPE_L2_ETHER_VLAN,
3298                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3299                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3300                 RTE_PTYPE_L4_ICMP,
3301                 RTE_PTYPE_L4_TCP,
3302                 RTE_PTYPE_L4_UDP,
3303                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3304                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3305                 RTE_PTYPE_INNER_L4_ICMP,
3306                 RTE_PTYPE_INNER_L4_TCP,
3307                 RTE_PTYPE_INNER_L4_UDP,
3308                 RTE_PTYPE_UNKNOWN
3309         };
3310
3311         if (!dev->rx_pkt_burst)
3312                 return NULL;
3313
3314         return ptypes;
3315 }
3316
3317 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3318                          int reg_win)
3319 {
3320         uint32_t reg_base = *reg_arr & 0xfffff000;
3321         uint32_t win_off;
3322         int i;
3323
3324         for (i = 0; i < count; i++) {
3325                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3326                         return -ERANGE;
3327         }
3328         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3329         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3330         return 0;
3331 }
3332
3333 static int bnxt_map_ptp_regs(struct bnxt *bp)
3334 {
3335         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3336         uint32_t *reg_arr;
3337         int rc, i;
3338
3339         reg_arr = ptp->rx_regs;
3340         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3341         if (rc)
3342                 return rc;
3343
3344         reg_arr = ptp->tx_regs;
3345         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3346         if (rc)
3347                 return rc;
3348
3349         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3350                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3351
3352         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3353                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3354
3355         return 0;
3356 }
3357
3358 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3359 {
3360         rte_write32(0, (uint8_t *)bp->bar0 +
3361                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3362         rte_write32(0, (uint8_t *)bp->bar0 +
3363                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3364 }
3365
3366 static uint64_t bnxt_cc_read(struct bnxt *bp)
3367 {
3368         uint64_t ns;
3369
3370         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3371                               BNXT_GRCPF_REG_SYNC_TIME));
3372         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3373                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3374         return ns;
3375 }
3376
3377 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3378 {
3379         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3380         uint32_t fifo;
3381
3382         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3383                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3384         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3385                 return -EAGAIN;
3386
3387         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3388                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3389         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3390                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3391         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3392                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3393
3394         return 0;
3395 }
3396
3397 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3398 {
3399         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3400         struct bnxt_pf_info *pf = &bp->pf;
3401         uint16_t port_id;
3402         uint32_t fifo;
3403
3404         if (!ptp)
3405                 return -ENODEV;
3406
3407         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3408                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3409         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3410                 return -EAGAIN;
3411
3412         port_id = pf->port_id;
3413         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3414                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3415
3416         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3417                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3418         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3419 /*              bnxt_clr_rx_ts(bp);       TBD  */
3420                 return -EBUSY;
3421         }
3422
3423         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3424                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3425         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3426                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3427
3428         return 0;
3429 }
3430
3431 static int
3432 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3433 {
3434         uint64_t ns;
3435         struct bnxt *bp = dev->data->dev_private;
3436         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3437
3438         if (!ptp)
3439                 return 0;
3440
3441         ns = rte_timespec_to_ns(ts);
3442         /* Set the timecounters to a new value. */
3443         ptp->tc.nsec = ns;
3444
3445         return 0;
3446 }
3447
3448 static int
3449 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3450 {
3451         struct bnxt *bp = dev->data->dev_private;
3452         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3453         uint64_t ns, systime_cycles = 0;
3454         int rc = 0;
3455
3456         if (!ptp)
3457                 return 0;
3458
3459         if (BNXT_CHIP_THOR(bp))
3460                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3461                                              &systime_cycles);
3462         else
3463                 systime_cycles = bnxt_cc_read(bp);
3464
3465         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3466         *ts = rte_ns_to_timespec(ns);
3467
3468         return rc;
3469 }
3470 static int
3471 bnxt_timesync_enable(struct rte_eth_dev *dev)
3472 {
3473         struct bnxt *bp = dev->data->dev_private;
3474         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3475         uint32_t shift = 0;
3476         int rc;
3477
3478         if (!ptp)
3479                 return 0;
3480
3481         ptp->rx_filter = 1;
3482         ptp->tx_tstamp_en = 1;
3483         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3484
3485         rc = bnxt_hwrm_ptp_cfg(bp);
3486         if (rc)
3487                 return rc;
3488
3489         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3490         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3491         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3492
3493         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3494         ptp->tc.cc_shift = shift;
3495         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3496
3497         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3498         ptp->rx_tstamp_tc.cc_shift = shift;
3499         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3500
3501         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3502         ptp->tx_tstamp_tc.cc_shift = shift;
3503         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3504
3505         if (!BNXT_CHIP_THOR(bp))
3506                 bnxt_map_ptp_regs(bp);
3507
3508         return 0;
3509 }
3510
3511 static int
3512 bnxt_timesync_disable(struct rte_eth_dev *dev)
3513 {
3514         struct bnxt *bp = dev->data->dev_private;
3515         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3516
3517         if (!ptp)
3518                 return 0;
3519
3520         ptp->rx_filter = 0;
3521         ptp->tx_tstamp_en = 0;
3522         ptp->rxctl = 0;
3523
3524         bnxt_hwrm_ptp_cfg(bp);
3525
3526         if (!BNXT_CHIP_THOR(bp))
3527                 bnxt_unmap_ptp_regs(bp);
3528
3529         return 0;
3530 }
3531
3532 static int
3533 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3534                                  struct timespec *timestamp,
3535                                  uint32_t flags __rte_unused)
3536 {
3537         struct bnxt *bp = dev->data->dev_private;
3538         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3539         uint64_t rx_tstamp_cycles = 0;
3540         uint64_t ns;
3541
3542         if (!ptp)
3543                 return 0;
3544
3545         if (BNXT_CHIP_THOR(bp))
3546                 rx_tstamp_cycles = ptp->rx_timestamp;
3547         else
3548                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3549
3550         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3551         *timestamp = rte_ns_to_timespec(ns);
3552         return  0;
3553 }
3554
3555 static int
3556 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3557                                  struct timespec *timestamp)
3558 {
3559         struct bnxt *bp = dev->data->dev_private;
3560         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3561         uint64_t tx_tstamp_cycles = 0;
3562         uint64_t ns;
3563         int rc = 0;
3564
3565         if (!ptp)
3566                 return 0;
3567
3568         if (BNXT_CHIP_THOR(bp))
3569                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3570                                              &tx_tstamp_cycles);
3571         else
3572                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3573
3574         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3575         *timestamp = rte_ns_to_timespec(ns);
3576
3577         return rc;
3578 }
3579
3580 static int
3581 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3582 {
3583         struct bnxt *bp = dev->data->dev_private;
3584         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3585
3586         if (!ptp)
3587                 return 0;
3588
3589         ptp->tc.nsec += delta;
3590
3591         return 0;
3592 }
3593
3594 static int
3595 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3596 {
3597         struct bnxt *bp = dev->data->dev_private;
3598         int rc;
3599         uint32_t dir_entries;
3600         uint32_t entry_length;
3601
3602         rc = is_bnxt_in_error(bp);
3603         if (rc)
3604                 return rc;
3605
3606         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3607                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3608                     bp->pdev->addr.devid, bp->pdev->addr.function);
3609
3610         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3611         if (rc != 0)
3612                 return rc;
3613
3614         return dir_entries * entry_length;
3615 }
3616
3617 static int
3618 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3619                 struct rte_dev_eeprom_info *in_eeprom)
3620 {
3621         struct bnxt *bp = dev->data->dev_private;
3622         uint32_t index;
3623         uint32_t offset;
3624         int rc;
3625
3626         rc = is_bnxt_in_error(bp);
3627         if (rc)
3628                 return rc;
3629
3630         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3631                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3632                     bp->pdev->addr.devid, bp->pdev->addr.function,
3633                     in_eeprom->offset, in_eeprom->length);
3634
3635         if (in_eeprom->offset == 0) /* special offset value to get directory */
3636                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3637                                                 in_eeprom->data);
3638
3639         index = in_eeprom->offset >> 24;
3640         offset = in_eeprom->offset & 0xffffff;
3641
3642         if (index != 0)
3643                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3644                                            in_eeprom->length, in_eeprom->data);
3645
3646         return 0;
3647 }
3648
3649 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3650 {
3651         switch (dir_type) {
3652         case BNX_DIR_TYPE_CHIMP_PATCH:
3653         case BNX_DIR_TYPE_BOOTCODE:
3654         case BNX_DIR_TYPE_BOOTCODE_2:
3655         case BNX_DIR_TYPE_APE_FW:
3656         case BNX_DIR_TYPE_APE_PATCH:
3657         case BNX_DIR_TYPE_KONG_FW:
3658         case BNX_DIR_TYPE_KONG_PATCH:
3659         case BNX_DIR_TYPE_BONO_FW:
3660         case BNX_DIR_TYPE_BONO_PATCH:
3661                 /* FALLTHROUGH */
3662                 return true;
3663         }
3664
3665         return false;
3666 }
3667
3668 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3669 {
3670         switch (dir_type) {
3671         case BNX_DIR_TYPE_AVS:
3672         case BNX_DIR_TYPE_EXP_ROM_MBA:
3673         case BNX_DIR_TYPE_PCIE:
3674         case BNX_DIR_TYPE_TSCF_UCODE:
3675         case BNX_DIR_TYPE_EXT_PHY:
3676         case BNX_DIR_TYPE_CCM:
3677         case BNX_DIR_TYPE_ISCSI_BOOT:
3678         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3679         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3680                 /* FALLTHROUGH */
3681                 return true;
3682         }
3683
3684         return false;
3685 }
3686
3687 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3688 {
3689         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3690                 bnxt_dir_type_is_other_exec_format(dir_type);
3691 }
3692
3693 static int
3694 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3695                 struct rte_dev_eeprom_info *in_eeprom)
3696 {
3697         struct bnxt *bp = dev->data->dev_private;
3698         uint8_t index, dir_op;
3699         uint16_t type, ext, ordinal, attr;
3700         int rc;
3701
3702         rc = is_bnxt_in_error(bp);
3703         if (rc)
3704                 return rc;
3705
3706         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3707                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3708                     bp->pdev->addr.devid, bp->pdev->addr.function,
3709                     in_eeprom->offset, in_eeprom->length);
3710
3711         if (!BNXT_PF(bp)) {
3712                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3713                 return -EINVAL;
3714         }
3715
3716         type = in_eeprom->magic >> 16;
3717
3718         if (type == 0xffff) { /* special value for directory operations */
3719                 index = in_eeprom->magic & 0xff;
3720                 dir_op = in_eeprom->magic >> 8;
3721                 if (index == 0)
3722                         return -EINVAL;
3723                 switch (dir_op) {
3724                 case 0x0e: /* erase */
3725                         if (in_eeprom->offset != ~in_eeprom->magic)
3726                                 return -EINVAL;
3727                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3728                 default:
3729                         return -EINVAL;
3730                 }
3731         }
3732
3733         /* Create or re-write an NVM item: */
3734         if (bnxt_dir_type_is_executable(type) == true)
3735                 return -EOPNOTSUPP;
3736         ext = in_eeprom->magic & 0xffff;
3737         ordinal = in_eeprom->offset >> 16;
3738         attr = in_eeprom->offset & 0xffff;
3739
3740         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3741                                      in_eeprom->data, in_eeprom->length);
3742 }
3743
3744 /*
3745  * Initialization
3746  */
3747
3748 static const struct eth_dev_ops bnxt_dev_ops = {
3749         .dev_infos_get = bnxt_dev_info_get_op,
3750         .dev_close = bnxt_dev_close_op,
3751         .dev_configure = bnxt_dev_configure_op,
3752         .dev_start = bnxt_dev_start_op,
3753         .dev_stop = bnxt_dev_stop_op,
3754         .dev_set_link_up = bnxt_dev_set_link_up_op,
3755         .dev_set_link_down = bnxt_dev_set_link_down_op,
3756         .stats_get = bnxt_stats_get_op,
3757         .stats_reset = bnxt_stats_reset_op,
3758         .rx_queue_setup = bnxt_rx_queue_setup_op,
3759         .rx_queue_release = bnxt_rx_queue_release_op,
3760         .tx_queue_setup = bnxt_tx_queue_setup_op,
3761         .tx_queue_release = bnxt_tx_queue_release_op,
3762         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3763         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3764         .reta_update = bnxt_reta_update_op,
3765         .reta_query = bnxt_reta_query_op,
3766         .rss_hash_update = bnxt_rss_hash_update_op,
3767         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3768         .link_update = bnxt_link_update_op,
3769         .promiscuous_enable = bnxt_promiscuous_enable_op,
3770         .promiscuous_disable = bnxt_promiscuous_disable_op,
3771         .allmulticast_enable = bnxt_allmulticast_enable_op,
3772         .allmulticast_disable = bnxt_allmulticast_disable_op,
3773         .mac_addr_add = bnxt_mac_addr_add_op,
3774         .mac_addr_remove = bnxt_mac_addr_remove_op,
3775         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3776         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3777         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3778         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3779         .vlan_filter_set = bnxt_vlan_filter_set_op,
3780         .vlan_offload_set = bnxt_vlan_offload_set_op,
3781         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3782         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3783         .mtu_set = bnxt_mtu_set_op,
3784         .mac_addr_set = bnxt_set_default_mac_addr_op,
3785         .xstats_get = bnxt_dev_xstats_get_op,
3786         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3787         .xstats_reset = bnxt_dev_xstats_reset_op,
3788         .fw_version_get = bnxt_fw_version_get,
3789         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3790         .rxq_info_get = bnxt_rxq_info_get_op,
3791         .txq_info_get = bnxt_txq_info_get_op,
3792         .dev_led_on = bnxt_dev_led_on_op,
3793         .dev_led_off = bnxt_dev_led_off_op,
3794         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3795         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3796         .rx_queue_count = bnxt_rx_queue_count_op,
3797         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3798         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3799         .rx_queue_start = bnxt_rx_queue_start,
3800         .rx_queue_stop = bnxt_rx_queue_stop,
3801         .tx_queue_start = bnxt_tx_queue_start,
3802         .tx_queue_stop = bnxt_tx_queue_stop,
3803         .filter_ctrl = bnxt_filter_ctrl_op,
3804         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3805         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3806         .get_eeprom           = bnxt_get_eeprom_op,
3807         .set_eeprom           = bnxt_set_eeprom_op,
3808         .timesync_enable      = bnxt_timesync_enable,
3809         .timesync_disable     = bnxt_timesync_disable,
3810         .timesync_read_time   = bnxt_timesync_read_time,
3811         .timesync_write_time   = bnxt_timesync_write_time,
3812         .timesync_adjust_time = bnxt_timesync_adjust_time,
3813         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3814         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3815 };
3816
3817 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3818 {
3819         uint32_t offset;
3820
3821         /* Only pre-map the reset GRC registers using window 3 */
3822         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3823                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3824
3825         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3826
3827         return offset;
3828 }
3829
3830 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3831 {
3832         struct bnxt_error_recovery_info *info = bp->recovery_info;
3833         uint32_t reg_base = 0xffffffff;
3834         int i;
3835
3836         /* Only pre-map the monitoring GRC registers using window 2 */
3837         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3838                 uint32_t reg = info->status_regs[i];
3839
3840                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3841                         continue;
3842
3843                 if (reg_base == 0xffffffff)
3844                         reg_base = reg & 0xfffff000;
3845                 if ((reg & 0xfffff000) != reg_base)
3846                         return -ERANGE;
3847
3848                 /* Use mask 0xffc as the Lower 2 bits indicates
3849                  * address space location
3850                  */
3851                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3852                                                 (reg & 0xffc);
3853         }
3854
3855         if (reg_base == 0xffffffff)
3856                 return 0;
3857
3858         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3859                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3860
3861         return 0;
3862 }
3863
3864 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3865 {
3866         struct bnxt_error_recovery_info *info = bp->recovery_info;
3867         uint32_t delay = info->delay_after_reset[index];
3868         uint32_t val = info->reset_reg_val[index];
3869         uint32_t reg = info->reset_reg[index];
3870         uint32_t type, offset;
3871
3872         type = BNXT_FW_STATUS_REG_TYPE(reg);
3873         offset = BNXT_FW_STATUS_REG_OFF(reg);
3874
3875         switch (type) {
3876         case BNXT_FW_STATUS_REG_TYPE_CFG:
3877                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3878                 break;
3879         case BNXT_FW_STATUS_REG_TYPE_GRC:
3880                 offset = bnxt_map_reset_regs(bp, offset);
3881                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3882                 break;
3883         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3884                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3885                 break;
3886         }
3887         /* wait on a specific interval of time until core reset is complete */
3888         if (delay)
3889                 rte_delay_ms(delay);
3890 }
3891
3892 static void bnxt_dev_cleanup(struct bnxt *bp)
3893 {
3894         bnxt_set_hwrm_link_config(bp, false);
3895         bp->link_info.link_up = 0;
3896         if (bp->dev_stopped == 0)
3897                 bnxt_dev_stop_op(bp->eth_dev);
3898
3899         bnxt_uninit_resources(bp, true);
3900 }
3901
3902 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3903 {
3904         struct rte_eth_dev *dev = bp->eth_dev;
3905         struct rte_vlan_filter_conf *vfc;
3906         int vidx, vbit, rc;
3907         uint16_t vlan_id;
3908
3909         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3910                 vfc = &dev->data->vlan_filter_conf;
3911                 vidx = vlan_id / 64;
3912                 vbit = vlan_id % 64;
3913
3914                 /* Each bit corresponds to a VLAN id */
3915                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3916                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3917                         if (rc)
3918                                 return rc;
3919                 }
3920         }
3921
3922         return 0;
3923 }
3924
3925 static int bnxt_restore_mac_filters(struct bnxt *bp)
3926 {
3927         struct rte_eth_dev *dev = bp->eth_dev;
3928         struct rte_eth_dev_info dev_info;
3929         struct rte_ether_addr *addr;
3930         uint64_t pool_mask;
3931         uint32_t pool = 0;
3932         uint16_t i;
3933         int rc;
3934
3935         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
3936                 return 0;
3937
3938         rc = bnxt_dev_info_get_op(dev, &dev_info);
3939         if (rc)
3940                 return rc;
3941
3942         /* replay MAC address configuration */
3943         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3944                 addr = &dev->data->mac_addrs[i];
3945
3946                 /* skip zero address */
3947                 if (rte_is_zero_ether_addr(addr))
3948                         continue;
3949
3950                 pool = 0;
3951                 pool_mask = dev->data->mac_pool_sel[i];
3952
3953                 do {
3954                         if (pool_mask & 1ULL) {
3955                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3956                                 if (rc)
3957                                         return rc;
3958                         }
3959                         pool_mask >>= 1;
3960                         pool++;
3961                 } while (pool_mask);
3962         }
3963
3964         return 0;
3965 }
3966
3967 static int bnxt_restore_filters(struct bnxt *bp)
3968 {
3969         struct rte_eth_dev *dev = bp->eth_dev;
3970         int ret = 0;
3971
3972         if (dev->data->all_multicast)
3973                 ret = bnxt_allmulticast_enable_op(dev);
3974         if (dev->data->promiscuous)
3975                 ret = bnxt_promiscuous_enable_op(dev);
3976
3977         ret = bnxt_restore_mac_filters(bp);
3978         if (ret)
3979                 return ret;
3980
3981         ret = bnxt_restore_vlan_filters(bp);
3982         /* TODO restore other filters as well */
3983         return ret;
3984 }
3985
3986 static void bnxt_dev_recover(void *arg)
3987 {
3988         struct bnxt *bp = arg;
3989         int timeout = bp->fw_reset_max_msecs;
3990         int rc = 0;
3991
3992         /* Clear Error flag so that device re-init should happen */
3993         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3994
3995         do {
3996                 rc = bnxt_hwrm_ver_get(bp);
3997                 if (rc == 0)
3998                         break;
3999                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4000                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4001         } while (rc && timeout);
4002
4003         if (rc) {
4004                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4005                 goto err;
4006         }
4007
4008         rc = bnxt_init_resources(bp, true);
4009         if (rc) {
4010                 PMD_DRV_LOG(ERR,
4011                             "Failed to initialize resources after reset\n");
4012                 goto err;
4013         }
4014         /* clear reset flag as the device is initialized now */
4015         bp->flags &= ~BNXT_FLAG_FW_RESET;
4016
4017         rc = bnxt_dev_start_op(bp->eth_dev);
4018         if (rc) {
4019                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4020                 goto err;
4021         }
4022
4023         rc = bnxt_restore_filters(bp);
4024         if (rc)
4025                 goto err;
4026
4027         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4028         return;
4029 err:
4030         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4031         bnxt_uninit_resources(bp, false);
4032         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4033 }
4034
4035 void bnxt_dev_reset_and_resume(void *arg)
4036 {
4037         struct bnxt *bp = arg;
4038         int rc;
4039
4040         bnxt_dev_cleanup(bp);
4041
4042         bnxt_wait_for_device_shutdown(bp);
4043
4044         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4045                                bnxt_dev_recover, (void *)bp);
4046         if (rc)
4047                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4048 }
4049
4050 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4051 {
4052         struct bnxt_error_recovery_info *info = bp->recovery_info;
4053         uint32_t reg = info->status_regs[index];
4054         uint32_t type, offset, val = 0;
4055
4056         type = BNXT_FW_STATUS_REG_TYPE(reg);
4057         offset = BNXT_FW_STATUS_REG_OFF(reg);
4058
4059         switch (type) {
4060         case BNXT_FW_STATUS_REG_TYPE_CFG:
4061                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4062                 break;
4063         case BNXT_FW_STATUS_REG_TYPE_GRC:
4064                 offset = info->mapped_status_regs[index];
4065                 /* FALLTHROUGH */
4066         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4067                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4068                                        offset));
4069                 break;
4070         }
4071
4072         return val;
4073 }
4074
4075 static int bnxt_fw_reset_all(struct bnxt *bp)
4076 {
4077         struct bnxt_error_recovery_info *info = bp->recovery_info;
4078         uint32_t i;
4079         int rc = 0;
4080
4081         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4082                 /* Reset through master function driver */
4083                 for (i = 0; i < info->reg_array_cnt; i++)
4084                         bnxt_write_fw_reset_reg(bp, i);
4085                 /* Wait for time specified by FW after triggering reset */
4086                 rte_delay_ms(info->master_func_wait_period_after_reset);
4087         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4088                 /* Reset with the help of Kong processor */
4089                 rc = bnxt_hwrm_fw_reset(bp);
4090                 if (rc)
4091                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4092         }
4093
4094         return rc;
4095 }
4096
4097 static void bnxt_fw_reset_cb(void *arg)
4098 {
4099         struct bnxt *bp = arg;
4100         struct bnxt_error_recovery_info *info = bp->recovery_info;
4101         int rc = 0;
4102
4103         /* Only Master function can do FW reset */
4104         if (bnxt_is_master_func(bp) &&
4105             bnxt_is_recovery_enabled(bp)) {
4106                 rc = bnxt_fw_reset_all(bp);
4107                 if (rc) {
4108                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4109                         return;
4110                 }
4111         }
4112
4113         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4114          * EXCEPTION_FATAL_ASYNC event to all the functions
4115          * (including MASTER FUNC). After receiving this Async, all the active
4116          * drivers should treat this case as FW initiated recovery
4117          */
4118         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4119                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4120                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4121
4122                 /* To recover from error */
4123                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4124                                   (void *)bp);
4125         }
4126 }
4127
4128 /* Driver should poll FW heartbeat, reset_counter with the frequency
4129  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4130  * When the driver detects heartbeat stop or change in reset_counter,
4131  * it has to trigger a reset to recover from the error condition.
4132  * A “master PF” is the function who will have the privilege to
4133  * initiate the chimp reset. The master PF will be elected by the
4134  * firmware and will be notified through async message.
4135  */
4136 static void bnxt_check_fw_health(void *arg)
4137 {
4138         struct bnxt *bp = arg;
4139         struct bnxt_error_recovery_info *info = bp->recovery_info;
4140         uint32_t val = 0, wait_msec;
4141
4142         if (!info || !bnxt_is_recovery_enabled(bp) ||
4143             is_bnxt_in_error(bp))
4144                 return;
4145
4146         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4147         if (val == info->last_heart_beat)
4148                 goto reset;
4149
4150         info->last_heart_beat = val;
4151
4152         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4153         if (val != info->last_reset_counter)
4154                 goto reset;
4155
4156         info->last_reset_counter = val;
4157
4158         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4159                           bnxt_check_fw_health, (void *)bp);
4160
4161         return;
4162 reset:
4163         /* Stop DMA to/from device */
4164         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4165         bp->flags |= BNXT_FLAG_FW_RESET;
4166
4167         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4168
4169         if (bnxt_is_master_func(bp))
4170                 wait_msec = info->master_func_wait_period;
4171         else
4172                 wait_msec = info->normal_func_wait_period;
4173
4174         rte_eal_alarm_set(US_PER_MS * wait_msec,
4175                           bnxt_fw_reset_cb, (void *)bp);
4176 }
4177
4178 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4179 {
4180         uint32_t polling_freq;
4181
4182         if (!bnxt_is_recovery_enabled(bp))
4183                 return;
4184
4185         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4186                 return;
4187
4188         polling_freq = bp->recovery_info->driver_polling_freq;
4189
4190         rte_eal_alarm_set(US_PER_MS * polling_freq,
4191                           bnxt_check_fw_health, (void *)bp);
4192         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4193 }
4194
4195 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4196 {
4197         if (!bnxt_is_recovery_enabled(bp))
4198                 return;
4199
4200         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4201         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4202 }
4203
4204 static bool bnxt_vf_pciid(uint16_t device_id)
4205 {
4206         switch (device_id) {
4207         case BROADCOM_DEV_ID_57304_VF:
4208         case BROADCOM_DEV_ID_57406_VF:
4209         case BROADCOM_DEV_ID_5731X_VF:
4210         case BROADCOM_DEV_ID_5741X_VF:
4211         case BROADCOM_DEV_ID_57414_VF:
4212         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4213         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4214         case BROADCOM_DEV_ID_58802_VF:
4215         case BROADCOM_DEV_ID_57500_VF1:
4216         case BROADCOM_DEV_ID_57500_VF2:
4217                 /* FALLTHROUGH */
4218                 return true;
4219         default:
4220                 return false;
4221         }
4222 }
4223
4224 static bool bnxt_thor_device(uint16_t device_id)
4225 {
4226         switch (device_id) {
4227         case BROADCOM_DEV_ID_57508:
4228         case BROADCOM_DEV_ID_57504:
4229         case BROADCOM_DEV_ID_57502:
4230         case BROADCOM_DEV_ID_57508_MF1:
4231         case BROADCOM_DEV_ID_57504_MF1:
4232         case BROADCOM_DEV_ID_57502_MF1:
4233         case BROADCOM_DEV_ID_57508_MF2:
4234         case BROADCOM_DEV_ID_57504_MF2:
4235         case BROADCOM_DEV_ID_57502_MF2:
4236         case BROADCOM_DEV_ID_57500_VF1:
4237         case BROADCOM_DEV_ID_57500_VF2:
4238                 /* FALLTHROUGH */
4239                 return true;
4240         default:
4241                 return false;
4242         }
4243 }
4244
4245 bool bnxt_stratus_device(struct bnxt *bp)
4246 {
4247         uint16_t device_id = bp->pdev->id.device_id;
4248
4249         switch (device_id) {
4250         case BROADCOM_DEV_ID_STRATUS_NIC:
4251         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4252         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4253                 /* FALLTHROUGH */
4254                 return true;
4255         default:
4256                 return false;
4257         }
4258 }
4259
4260 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4261 {
4262         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4263         struct bnxt *bp = eth_dev->data->dev_private;
4264
4265         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4266         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4267         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4268         if (!bp->bar0 || !bp->doorbell_base) {
4269                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4270                 return -ENODEV;
4271         }
4272
4273         bp->eth_dev = eth_dev;
4274         bp->pdev = pci_dev;
4275
4276         return 0;
4277 }
4278
4279 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4280                                   struct bnxt_ctx_pg_info *ctx_pg,
4281                                   uint32_t mem_size,
4282                                   const char *suffix,
4283                                   uint16_t idx)
4284 {
4285         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4286         const struct rte_memzone *mz = NULL;
4287         char mz_name[RTE_MEMZONE_NAMESIZE];
4288         rte_iova_t mz_phys_addr;
4289         uint64_t valid_bits = 0;
4290         uint32_t sz;
4291         int i;
4292
4293         if (!mem_size)
4294                 return 0;
4295
4296         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4297                          BNXT_PAGE_SIZE;
4298         rmem->page_size = BNXT_PAGE_SIZE;
4299         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4300         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4301         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4302
4303         valid_bits = PTU_PTE_VALID;
4304
4305         if (rmem->nr_pages > 1) {
4306                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4307                          "bnxt_ctx_pg_tbl%s_%x_%d",
4308                          suffix, idx, bp->eth_dev->data->port_id);
4309                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4310                 mz = rte_memzone_lookup(mz_name);
4311                 if (!mz) {
4312                         mz = rte_memzone_reserve_aligned(mz_name,
4313                                                 rmem->nr_pages * 8,
4314                                                 SOCKET_ID_ANY,
4315                                                 RTE_MEMZONE_2MB |
4316                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4317                                                 RTE_MEMZONE_IOVA_CONTIG,
4318                                                 BNXT_PAGE_SIZE);
4319                         if (mz == NULL)
4320                                 return -ENOMEM;
4321                 }
4322
4323                 memset(mz->addr, 0, mz->len);
4324                 mz_phys_addr = mz->iova;
4325
4326                 rmem->pg_tbl = mz->addr;
4327                 rmem->pg_tbl_map = mz_phys_addr;
4328                 rmem->pg_tbl_mz = mz;
4329         }
4330
4331         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4332                  suffix, idx, bp->eth_dev->data->port_id);
4333         mz = rte_memzone_lookup(mz_name);
4334         if (!mz) {
4335                 mz = rte_memzone_reserve_aligned(mz_name,
4336                                                  mem_size,
4337                                                  SOCKET_ID_ANY,
4338                                                  RTE_MEMZONE_1GB |
4339                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4340                                                  RTE_MEMZONE_IOVA_CONTIG,
4341                                                  BNXT_PAGE_SIZE);
4342                 if (mz == NULL)
4343                         return -ENOMEM;
4344         }
4345
4346         memset(mz->addr, 0, mz->len);
4347         mz_phys_addr = mz->iova;
4348
4349         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4350                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4351                 rmem->dma_arr[i] = mz_phys_addr + sz;
4352
4353                 if (rmem->nr_pages > 1) {
4354                         if (i == rmem->nr_pages - 2 &&
4355                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4356                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4357                         else if (i == rmem->nr_pages - 1 &&
4358                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4359                                 valid_bits |= PTU_PTE_LAST;
4360
4361                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4362                                                            valid_bits);
4363                 }
4364         }
4365
4366         rmem->mz = mz;
4367         if (rmem->vmem_size)
4368                 rmem->vmem = (void **)mz->addr;
4369         rmem->dma_arr[0] = mz_phys_addr;
4370         return 0;
4371 }
4372
4373 static void bnxt_free_ctx_mem(struct bnxt *bp)
4374 {
4375         int i;
4376
4377         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4378                 return;
4379
4380         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4381         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4382         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4383         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4384         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4385         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4386         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4387         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4388         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4389         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4390         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4391
4392         for (i = 0; i < BNXT_MAX_Q; i++) {
4393                 if (bp->ctx->tqm_mem[i])
4394                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4395         }
4396
4397         rte_free(bp->ctx);
4398         bp->ctx = NULL;
4399 }
4400
4401 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4402
4403 #define min_t(type, x, y) ({                    \
4404         type __min1 = (x);                      \
4405         type __min2 = (y);                      \
4406         __min1 < __min2 ? __min1 : __min2; })
4407
4408 #define max_t(type, x, y) ({                    \
4409         type __max1 = (x);                      \
4410         type __max2 = (y);                      \
4411         __max1 > __max2 ? __max1 : __max2; })
4412
4413 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4414
4415 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4416 {
4417         struct bnxt_ctx_pg_info *ctx_pg;
4418         struct bnxt_ctx_mem_info *ctx;
4419         uint32_t mem_size, ena, entries;
4420         int i, rc;
4421
4422         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4423         if (rc) {
4424                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4425                 return rc;
4426         }
4427         ctx = bp->ctx;
4428         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4429                 return 0;
4430
4431         ctx_pg = &ctx->qp_mem;
4432         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4433         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4434         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4435         if (rc)
4436                 return rc;
4437
4438         ctx_pg = &ctx->srq_mem;
4439         ctx_pg->entries = ctx->srq_max_l2_entries;
4440         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4441         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4442         if (rc)
4443                 return rc;
4444
4445         ctx_pg = &ctx->cq_mem;
4446         ctx_pg->entries = ctx->cq_max_l2_entries;
4447         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4448         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4449         if (rc)
4450                 return rc;
4451
4452         ctx_pg = &ctx->vnic_mem;
4453         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4454                 ctx->vnic_max_ring_table_entries;
4455         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4456         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4457         if (rc)
4458                 return rc;
4459
4460         ctx_pg = &ctx->stat_mem;
4461         ctx_pg->entries = ctx->stat_max_entries;
4462         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4463         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4464         if (rc)
4465                 return rc;
4466
4467         entries = ctx->qp_max_l2_entries +
4468                   ctx->vnic_max_vnic_entries +
4469                   ctx->tqm_min_entries_per_ring;
4470         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4471         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4472                           ctx->tqm_max_entries_per_ring);
4473         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4474                 ctx_pg = ctx->tqm_mem[i];
4475                 /* use min tqm entries for now. */
4476                 ctx_pg->entries = entries;
4477                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4478                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4479                 if (rc)
4480                         return rc;
4481                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4482         }
4483
4484         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4485         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4486         if (rc)
4487                 PMD_DRV_LOG(ERR,
4488                             "Failed to configure context mem: rc = %d\n", rc);
4489         else
4490                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4491
4492         return rc;
4493 }
4494
4495 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4496 {
4497         struct rte_pci_device *pci_dev = bp->pdev;
4498         char mz_name[RTE_MEMZONE_NAMESIZE];
4499         const struct rte_memzone *mz = NULL;
4500         uint32_t total_alloc_len;
4501         rte_iova_t mz_phys_addr;
4502
4503         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4504                 return 0;
4505
4506         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4507                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4508                  pci_dev->addr.bus, pci_dev->addr.devid,
4509                  pci_dev->addr.function, "rx_port_stats");
4510         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4511         mz = rte_memzone_lookup(mz_name);
4512         total_alloc_len =
4513                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4514                                        sizeof(struct rx_port_stats_ext) + 512);
4515         if (!mz) {
4516                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4517                                          SOCKET_ID_ANY,
4518                                          RTE_MEMZONE_2MB |
4519                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4520                                          RTE_MEMZONE_IOVA_CONTIG);
4521                 if (mz == NULL)
4522                         return -ENOMEM;
4523         }
4524         memset(mz->addr, 0, mz->len);
4525         mz_phys_addr = mz->iova;
4526
4527         bp->rx_mem_zone = (const void *)mz;
4528         bp->hw_rx_port_stats = mz->addr;
4529         bp->hw_rx_port_stats_map = mz_phys_addr;
4530
4531         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4532                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4533                  pci_dev->addr.bus, pci_dev->addr.devid,
4534                  pci_dev->addr.function, "tx_port_stats");
4535         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4536         mz = rte_memzone_lookup(mz_name);
4537         total_alloc_len =
4538                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4539                                        sizeof(struct tx_port_stats_ext) + 512);
4540         if (!mz) {
4541                 mz = rte_memzone_reserve(mz_name,
4542                                          total_alloc_len,
4543                                          SOCKET_ID_ANY,
4544                                          RTE_MEMZONE_2MB |
4545                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4546                                          RTE_MEMZONE_IOVA_CONTIG);
4547                 if (mz == NULL)
4548                         return -ENOMEM;
4549         }
4550         memset(mz->addr, 0, mz->len);
4551         mz_phys_addr = mz->iova;
4552
4553         bp->tx_mem_zone = (const void *)mz;
4554         bp->hw_tx_port_stats = mz->addr;
4555         bp->hw_tx_port_stats_map = mz_phys_addr;
4556         bp->flags |= BNXT_FLAG_PORT_STATS;
4557
4558         /* Display extended statistics if FW supports it */
4559         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4560             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4561             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4562                 return 0;
4563
4564         bp->hw_rx_port_stats_ext = (void *)
4565                 ((uint8_t *)bp->hw_rx_port_stats +
4566                  sizeof(struct rx_port_stats));
4567         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4568                 sizeof(struct rx_port_stats);
4569         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4570
4571         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4572             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4573                 bp->hw_tx_port_stats_ext = (void *)
4574                         ((uint8_t *)bp->hw_tx_port_stats +
4575                          sizeof(struct tx_port_stats));
4576                 bp->hw_tx_port_stats_ext_map =
4577                         bp->hw_tx_port_stats_map +
4578                         sizeof(struct tx_port_stats);
4579                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4580         }
4581
4582         return 0;
4583 }
4584
4585 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4586 {
4587         struct bnxt *bp = eth_dev->data->dev_private;
4588         int rc = 0;
4589
4590         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4591                                                RTE_ETHER_ADDR_LEN *
4592                                                bp->max_l2_ctx,
4593                                                0);
4594         if (eth_dev->data->mac_addrs == NULL) {
4595                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4596                 return -ENOMEM;
4597         }
4598
4599         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4600                 if (BNXT_PF(bp))
4601                         return -EINVAL;
4602
4603                 /* Generate a random MAC address, if none was assigned by PF */
4604                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4605                 bnxt_eth_hw_addr_random(bp->mac_addr);
4606                 PMD_DRV_LOG(INFO,
4607                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4608                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4609                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4610
4611                 rc = bnxt_hwrm_set_mac(bp);
4612                 if (!rc)
4613                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4614                                RTE_ETHER_ADDR_LEN);
4615                 return rc;
4616         }
4617
4618         /* Copy the permanent MAC from the FUNC_QCAPS response */
4619         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4620         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4621
4622         return rc;
4623 }
4624
4625 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4626 {
4627         int rc = 0;
4628
4629         /* MAC is already configured in FW */
4630         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4631                 return 0;
4632
4633         /* Restore the old MAC configured */
4634         rc = bnxt_hwrm_set_mac(bp);
4635         if (rc)
4636                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4637
4638         return rc;
4639 }
4640
4641 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4642 {
4643         if (!BNXT_PF(bp))
4644                 return;
4645
4646 #define ALLOW_FUNC(x)   \
4647         { \
4648                 uint32_t arg = (x); \
4649                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4650                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4651         }
4652
4653         /* Forward all requests if firmware is new enough */
4654         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4655              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4656             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4657                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4658         } else {
4659                 PMD_DRV_LOG(WARNING,
4660                             "Firmware too old for VF mailbox functionality\n");
4661                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4662         }
4663
4664         /*
4665          * The following are used for driver cleanup. If we disallow these,
4666          * VF drivers can't clean up cleanly.
4667          */
4668         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4669         ALLOW_FUNC(HWRM_VNIC_FREE);
4670         ALLOW_FUNC(HWRM_RING_FREE);
4671         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4672         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4673         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4674         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4675         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4676         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4677 }
4678
4679 static int bnxt_init_fw(struct bnxt *bp)
4680 {
4681         uint16_t mtu;
4682         int rc = 0;
4683
4684         bp->fw_cap = 0;
4685
4686         rc = bnxt_hwrm_ver_get(bp);
4687         if (rc)
4688                 return rc;
4689
4690         rc = bnxt_hwrm_func_reset(bp);
4691         if (rc)
4692                 return -EIO;
4693
4694         rc = bnxt_hwrm_vnic_qcaps(bp);
4695         if (rc)
4696                 return rc;
4697
4698         rc = bnxt_hwrm_queue_qportcfg(bp);
4699         if (rc)
4700                 return rc;
4701
4702         /* Get the MAX capabilities for this function.
4703          * This function also allocates context memory for TQM rings and
4704          * informs the firmware about this allocated backing store memory.
4705          */
4706         rc = bnxt_hwrm_func_qcaps(bp);
4707         if (rc)
4708                 return rc;
4709
4710         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4711         if (rc)
4712                 return rc;
4713
4714         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4715         if (rc)
4716                 return rc;
4717
4718         /* Get the adapter error recovery support info */
4719         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4720         if (rc)
4721                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4722
4723         bnxt_hwrm_port_led_qcaps(bp);
4724
4725         return 0;
4726 }
4727
4728 static int
4729 bnxt_init_locks(struct bnxt *bp)
4730 {
4731         int err;
4732
4733         err = pthread_mutex_init(&bp->flow_lock, NULL);
4734         if (err) {
4735                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4736                 return err;
4737         }
4738
4739         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4740         if (err)
4741                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4742         return err;
4743 }
4744
4745 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4746 {
4747         int rc;
4748
4749         rc = bnxt_init_fw(bp);
4750         if (rc)
4751                 return rc;
4752
4753         if (!reconfig_dev) {
4754                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4755                 if (rc)
4756                         return rc;
4757         } else {
4758                 rc = bnxt_restore_dflt_mac(bp);
4759                 if (rc)
4760                         return rc;
4761         }
4762
4763         bnxt_config_vf_req_fwd(bp);
4764
4765         rc = bnxt_hwrm_func_driver_register(bp);
4766         if (rc) {
4767                 PMD_DRV_LOG(ERR, "Failed to register driver");
4768                 return -EBUSY;
4769         }
4770
4771         if (BNXT_PF(bp)) {
4772                 if (bp->pdev->max_vfs) {
4773                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4774                         if (rc) {
4775                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4776                                 return rc;
4777                         }
4778                 } else {
4779                         rc = bnxt_hwrm_allocate_pf_only(bp);
4780                         if (rc) {
4781                                 PMD_DRV_LOG(ERR,
4782                                             "Failed to allocate PF resources");
4783                                 return rc;
4784                         }
4785                 }
4786         }
4787
4788         rc = bnxt_alloc_mem(bp, reconfig_dev);
4789         if (rc)
4790                 return rc;
4791
4792         rc = bnxt_setup_int(bp);
4793         if (rc)
4794                 return rc;
4795
4796         rc = bnxt_request_int(bp);
4797         if (rc)
4798                 return rc;
4799
4800         rc = bnxt_init_locks(bp);
4801         if (rc)
4802                 return rc;
4803
4804         return 0;
4805 }
4806
4807 static int
4808 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4809 {
4810         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4811         static int version_printed;
4812         struct bnxt *bp;
4813         int rc;
4814
4815         if (version_printed++ == 0)
4816                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4817
4818         eth_dev->dev_ops = &bnxt_dev_ops;
4819         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4820         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4821
4822         /*
4823          * For secondary processes, we don't initialise any further
4824          * as primary has already done this work.
4825          */
4826         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4827                 return 0;
4828
4829         rte_eth_copy_pci_info(eth_dev, pci_dev);
4830
4831         bp = eth_dev->data->dev_private;
4832
4833         bp->dev_stopped = 1;
4834         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
4835
4836         if (bnxt_vf_pciid(pci_dev->id.device_id))
4837                 bp->flags |= BNXT_FLAG_VF;
4838
4839         if (bnxt_thor_device(pci_dev->id.device_id))
4840                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4841
4842         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4843             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4844             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4845             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4846                 bp->flags |= BNXT_FLAG_STINGRAY;
4847
4848         rc = bnxt_init_board(eth_dev);
4849         if (rc) {
4850                 PMD_DRV_LOG(ERR,
4851                             "Failed to initialize board rc: %x\n", rc);
4852                 return rc;
4853         }
4854
4855         rc = bnxt_alloc_hwrm_resources(bp);
4856         if (rc) {
4857                 PMD_DRV_LOG(ERR,
4858                             "Failed to allocate hwrm resource rc: %x\n", rc);
4859                 goto error_free;
4860         }
4861         rc = bnxt_init_resources(bp, false);
4862         if (rc)
4863                 goto error_free;
4864
4865         rc = bnxt_alloc_stats_mem(bp);
4866         if (rc)
4867                 goto error_free;
4868
4869         /* Pass the information to the rte_eth_dev_close() that it should also
4870          * release the private port resources.
4871          */
4872         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
4873
4874         PMD_DRV_LOG(INFO,
4875                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4876                     pci_dev->mem_resource[0].phys_addr,
4877                     pci_dev->mem_resource[0].addr);
4878
4879         return 0;
4880
4881 error_free:
4882         bnxt_dev_uninit(eth_dev);
4883         return rc;
4884 }
4885
4886 static void
4887 bnxt_uninit_locks(struct bnxt *bp)
4888 {
4889         pthread_mutex_destroy(&bp->flow_lock);
4890         pthread_mutex_destroy(&bp->def_cp_lock);
4891 }
4892
4893 static int
4894 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4895 {
4896         int rc;
4897
4898         bnxt_free_int(bp);
4899         bnxt_free_mem(bp, reconfig_dev);
4900         bnxt_hwrm_func_buf_unrgtr(bp);
4901         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4902         bp->flags &= ~BNXT_FLAG_REGISTERED;
4903         bnxt_free_ctx_mem(bp);
4904         if (!reconfig_dev) {
4905                 bnxt_free_hwrm_resources(bp);
4906
4907                 if (bp->recovery_info != NULL) {
4908                         rte_free(bp->recovery_info);
4909                         bp->recovery_info = NULL;
4910                 }
4911         }
4912
4913         bnxt_uninit_locks(bp);
4914         rte_free(bp->ptp_cfg);
4915         bp->ptp_cfg = NULL;
4916         return rc;
4917 }
4918
4919 static int
4920 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4921 {
4922         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4923                 return -EPERM;
4924
4925         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4926
4927         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
4928                 bnxt_dev_close_op(eth_dev);
4929
4930         return 0;
4931 }
4932
4933 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4934         struct rte_pci_device *pci_dev)
4935 {
4936         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4937                 bnxt_dev_init);
4938 }
4939
4940 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4941 {
4942         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4943                 return rte_eth_dev_pci_generic_remove(pci_dev,
4944                                 bnxt_dev_uninit);
4945         else
4946                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4947 }
4948
4949 static struct rte_pci_driver bnxt_rte_pmd = {
4950         .id_table = bnxt_pci_id_map,
4951         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4952         .probe = bnxt_pci_probe,
4953         .remove = bnxt_pci_remove,
4954 };
4955
4956 static bool
4957 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4958 {
4959         if (strcmp(dev->device->driver->name, drv->driver.name))
4960                 return false;
4961
4962         return true;
4963 }
4964
4965 bool is_bnxt_supported(struct rte_eth_dev *dev)
4966 {
4967         return is_device_supported(dev, &bnxt_rte_pmd);
4968 }
4969
4970 RTE_INIT(bnxt_init_log)
4971 {
4972         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4973         if (bnxt_logtype_driver >= 0)
4974                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4975 }
4976
4977 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4978 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4979 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");