drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_cpr.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30 #include "bnxt_util.h"
  31
  32 #define DRV_MODULE_NAME         "bnxt"
  33 static const char bnxt_version[] =
  34         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  35 int bnxt_logtype_driver;
  36
  37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  38
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  43 #define BROADCOM_DEV_ID_57301 0x16c8
  44 #define BROADCOM_DEV_ID_57302 0x16c9
  45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  48 #define BROADCOM_DEV_ID_NS2 0x16cd
  49 #define BROADCOM_DEV_ID_57311 0x16ce
  50 #define BROADCOM_DEV_ID_57312 0x16cf
  51 #define BROADCOM_DEV_ID_57402 0x16d0
  52 #define BROADCOM_DEV_ID_57404 0x16d1
  53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  57 #define BROADCOM_DEV_ID_57412 0x16d6
  58 #define BROADCOM_DEV_ID_57414 0x16d7
  59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  62 #define BROADCOM_DEV_ID_57412_MF 0x16de
  63 #define BROADCOM_DEV_ID_57314 0x16df
  64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  75 #define BROADCOM_DEV_ID_57508 0x1750
  76 #define BROADCOM_DEV_ID_57504 0x1751
  77 #define BROADCOM_DEV_ID_57502 0x1752
  78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
  79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
  80 #define BROADCOM_DEV_ID_58802 0xd802
  81 #define BROADCOM_DEV_ID_58804 0xd804
  82 #define BROADCOM_DEV_ID_58808 0x16f0
  83 #define BROADCOM_DEV_ID_58802_VF 0xd800
  84
  85 static const struct rte_pci_id bnxt_pci_id_map[] = {
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  87                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  89                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 130         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 131         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
 132         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
 133         { .vendor_id = 0, /* sentinel */ },
 134 };
 135
 136 #define BNXT_ETH_RSS_SUPPORT (  \
 137         ETH_RSS_IPV4 |          \
 138         ETH_RSS_NONFRAG_IPV4_TCP |      \
 139         ETH_RSS_NONFRAG_IPV4_UDP |      \
 140         ETH_RSS_IPV6 |          \
 141         ETH_RSS_NONFRAG_IPV6_TCP |      \
 142         ETH_RSS_NONFRAG_IPV6_UDP)
 143
 144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 145                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 146                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 147                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 148                                      DEV_TX_OFFLOAD_TCP_TSO | \
 149                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 150                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 152                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 153                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 154                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 155
 156 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 157                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 158                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 159                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 160                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 161                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 162                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 163                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 164                                      DEV_RX_OFFLOAD_TCP_LRO)
 165
 166 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 167 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 168 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 169 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 170 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 171 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 172 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 173
 174 int is_bnxt_in_error(struct bnxt *bp)
 175 {
 176         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 177                 return -EIO;
 178         if (bp->flags & BNXT_FLAG_FW_RESET)
 179                 return -EBUSY;
 180
 181         return 0;
 182 }
 183
 184 /***********************/
 185
 186 /*
 187  * High level utility functions
 188  */
 189
 190 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 191 {
 192         if (!BNXT_CHIP_THOR(bp))
 193                 return 1;
 194
 195         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 196                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 197                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 198 }
 199
 200 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 201 {
 202         if (!BNXT_CHIP_THOR(bp))
 203                 return HW_HASH_INDEX_SIZE;
 204
 205         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 206 }
 207
 208 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 209 {
 210         bnxt_free_filter_mem(bp);
 211         bnxt_free_vnic_attributes(bp);
 212         bnxt_free_vnic_mem(bp);
 213
 214         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 215          * If the number of rings change across fw update,
 216          * we don't have much choice except to warn the user.
 217          */
 218         if (!reconfig) {
 219                 bnxt_free_stats(bp);
 220                 bnxt_free_tx_rings(bp);
 221                 bnxt_free_rx_rings(bp);
 222         }
 223         bnxt_free_async_cp_ring(bp);
 224 }
 225
 226 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 227 {
 228         int rc;
 229
 230         rc = bnxt_alloc_ring_grps(bp);
 231         if (rc)
 232                 goto alloc_mem_err;
 233
 234         rc = bnxt_alloc_async_ring_struct(bp);
 235         if (rc)
 236                 goto alloc_mem_err;
 237
 238         rc = bnxt_alloc_vnic_mem(bp);
 239         if (rc)
 240                 goto alloc_mem_err;
 241
 242         rc = bnxt_alloc_vnic_attributes(bp);
 243         if (rc)
 244                 goto alloc_mem_err;
 245
 246         rc = bnxt_alloc_filter_mem(bp);
 247         if (rc)
 248                 goto alloc_mem_err;
 249
 250         rc = bnxt_alloc_async_cp_ring(bp);
 251         if (rc)
 252                 goto alloc_mem_err;
 253
 254         return 0;
 255
 256 alloc_mem_err:
 257         bnxt_free_mem(bp, reconfig);
 258         return rc;
 259 }
 260
 261 static int bnxt_init_chip(struct bnxt *bp)
 262 {
 263         struct bnxt_rx_queue *rxq;
 264         struct rte_eth_link new;
 265         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 266         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 267         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 268         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 269         uint32_t intr_vector = 0;
 270         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 271         uint32_t vec = BNXT_MISC_VEC_ID;
 272         unsigned int i, j;
 273         int rc;
 274
 275         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 276                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 277                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 278                 bp->flags |= BNXT_FLAG_JUMBO;
 279         } else {
 280                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 281                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 282                 bp->flags &= ~BNXT_FLAG_JUMBO;
 283         }
 284
 285         /* THOR does not support ring groups.
 286          * But we will use the array to save RSS context IDs.
 287          */
 288         if (BNXT_CHIP_THOR(bp))
 289                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 290
 291         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 292         if (rc) {
 293                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 294                 goto err_out;
 295         }
 296
 297         rc = bnxt_alloc_hwrm_rings(bp);
 298         if (rc) {
 299                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 300                 goto err_out;
 301         }
 302
 303         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 304         if (rc) {
 305                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 306                 goto err_out;
 307         }
 308
 309         rc = bnxt_mq_rx_configure(bp);
 310         if (rc) {
 311                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 312                 goto err_out;
 313         }
 314
 315         /* VNIC configuration */
 316         for (i = 0; i < bp->nr_vnics; i++) {
 317                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 318                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 319                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 320
 321                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 322                 if (!vnic->fw_grp_ids) {
 323                         PMD_DRV_LOG(ERR,
 324                                     "Failed to alloc %d bytes for group ids\n",
 325                                     size);
 326                         rc = -ENOMEM;
 327                         goto err_out;
 328                 }
 329                 memset(vnic->fw_grp_ids, -1, size);
 330
 331                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 332                             i, vnic, vnic->fw_grp_ids);
 333
 334                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 335                 if (rc) {
 336                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 337                                 i, rc);
 338                         goto err_out;
 339                 }
 340
 341                 /* Alloc RSS context only if RSS mode is enabled */
 342                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 343                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 344
 345                         rc = 0;
 346                         for (j = 0; j < nr_ctxs; j++) {
 347                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 348                                 if (rc)
 349                                         break;
 350                         }
 351                         if (rc) {
 352                                 PMD_DRV_LOG(ERR,
 353                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 354                                   i, j, rc);
 355                                 goto err_out;
 356                         }
 357                         vnic->num_lb_ctxts = nr_ctxs;
 358                 }
 359
 360                 /*
 361                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 362                  * setting is not available at this time, it will not be
 363                  * configured correctly in the CFA.
 364                  */
 365                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 366                         vnic->vlan_strip = true;
 367                 else
 368                         vnic->vlan_strip = false;
 369
 370                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 371                 if (rc) {
 372                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 373                                 i, rc);
 374                         goto err_out;
 375                 }
 376
 377                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 378                 if (rc) {
 379                         PMD_DRV_LOG(ERR,
 380                                 "HWRM vnic %d filter failure rc: %x\n",
 381                                 i, rc);
 382                         goto err_out;
 383                 }
 384
 385                 for (j = 0; j < bp->rx_nr_rings; j++) {
 386                         rxq = bp->eth_dev->data->rx_queues[j];
 387
 388                         PMD_DRV_LOG(DEBUG,
 389                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 390                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 391
 392                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 393                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 394                 }
 395
 396                 rc = bnxt_vnic_rss_configure(bp, vnic);
 397                 if (rc) {
 398                         PMD_DRV_LOG(ERR,
 399                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 400                         goto err_out;
 401                 }
 402
 403                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 404
 405                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 406                     DEV_RX_OFFLOAD_TCP_LRO)
 407                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 408                 else
 409                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 410         }
 411         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 412         if (rc) {
 413                 PMD_DRV_LOG(ERR,
 414                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 415                 goto err_out;
 416         }
 417
 418         /* check and configure queue intr-vector mapping */
 419         if ((rte_intr_cap_multiple(intr_handle) ||
 420              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 421             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 422                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 423                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 424                 if (intr_vector > bp->rx_cp_nr_rings) {
 425                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 426                                         bp->rx_cp_nr_rings);
 427                         return -ENOTSUP;
 428                 }
 429                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 430                 if (rc)
 431                         return rc;
 432         }
 433
 434         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 435                 intr_handle->intr_vec =
 436                         rte_zmalloc("intr_vec",
 437                                     bp->eth_dev->data->nb_rx_queues *
 438                                     sizeof(int), 0);
 439                 if (intr_handle->intr_vec == NULL) {
 440                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 441                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 442                         rc = -ENOMEM;
 443                         goto err_disable;
 444                 }
 445                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 446                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 447                          intr_handle->intr_vec, intr_handle->nb_efd,
 448                         intr_handle->max_intr);
 449                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 450                      queue_id++) {
 451                         intr_handle->intr_vec[queue_id] =
 452                                                         vec + BNXT_RX_VEC_START;
 453                         if (vec < base + intr_handle->nb_efd - 1)
 454                                 vec++;
 455                 }
 456         }
 457
 458         /* enable uio/vfio intr/eventfd mapping */
 459         rc = rte_intr_enable(intr_handle);
 460         if (rc)
 461                 goto err_free;
 462
 463         rc = bnxt_get_hwrm_link_config(bp, &new);
 464         if (rc) {
 465                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 466                 goto err_free;
 467         }
 468
 469         if (!bp->link_info.link_up) {
 470                 rc = bnxt_set_hwrm_link_config(bp, true);
 471                 if (rc) {
 472                         PMD_DRV_LOG(ERR,
 473                                 "HWRM link config failure rc: %x\n", rc);
 474                         goto err_free;
 475                 }
 476         }
 477         bnxt_print_link_info(bp->eth_dev);
 478
 479         return 0;
 480
 481 err_free:
 482         rte_free(intr_handle->intr_vec);
 483 err_disable:
 484         rte_intr_efd_disable(intr_handle);
 485 err_out:
 486         /* Some of the error status returned by FW may not be from errno.h */
 487         if (rc > 0)
 488                 rc = -EIO;
 489
 490         return rc;
 491 }
 492
 493 static int bnxt_shutdown_nic(struct bnxt *bp)
 494 {
 495         bnxt_free_all_hwrm_resources(bp);
 496         bnxt_free_all_filters(bp);
 497         bnxt_free_all_vnics(bp);
 498         return 0;
 499 }
 500
 501 static int bnxt_init_nic(struct bnxt *bp)
 502 {
 503         int rc;
 504
 505         if (BNXT_HAS_RING_GRPS(bp)) {
 506                 rc = bnxt_init_ring_grps(bp);
 507                 if (rc)
 508                         return rc;
 509         }
 510
 511         bnxt_init_vnics(bp);
 512         bnxt_init_filters(bp);
 513
 514         return 0;
 515 }
 516
 517 /*
 518  * Device configuration and status function
 519  */
 520
 521 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 522                                 struct rte_eth_dev_info *dev_info)
 523 {
 524         struct bnxt *bp = eth_dev->data->dev_private;
 525         uint16_t max_vnics, i, j, vpool, vrxq;
 526         unsigned int max_rx_rings;
 527         int rc;
 528
 529         rc = is_bnxt_in_error(bp);
 530         if (rc)
 531                 return rc;
 532
 533         /* MAC Specifics */
 534         dev_info->max_mac_addrs = bp->max_l2_ctx;
 535         dev_info->max_hash_mac_addrs = 0;
 536
 537         /* PF/VF specifics */
 538         if (BNXT_PF(bp))
 539                 dev_info->max_vfs = bp->pdev->max_vfs;
 540         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 541         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 542         dev_info->max_rx_queues = max_rx_rings;
 543         dev_info->max_tx_queues = max_rx_rings;
 544         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 545         dev_info->hash_key_size = 40;
 546         max_vnics = bp->max_vnics;
 547
 548         /* MTU specifics */
 549         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 550         dev_info->max_mtu = BNXT_MAX_MTU;
 551
 552         /* Fast path specifics */
 553         dev_info->min_rx_bufsize = 1;
 554         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 555
 556         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 557         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 558                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 559         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 560         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 561
 562         /* *INDENT-OFF* */
 563         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 564                 .rx_thresh = {
 565                         .pthresh = 8,
 566                         .hthresh = 8,
 567                         .wthresh = 0,
 568                 },
 569                 .rx_free_thresh = 32,
 570                 /* If no descriptors available, pkts are dropped by default */
 571                 .rx_drop_en = 1,
 572         };
 573
 574         dev_info->default_txconf = (struct rte_eth_txconf) {
 575                 .tx_thresh = {
 576                         .pthresh = 32,
 577                         .hthresh = 0,
 578                         .wthresh = 0,
 579                 },
 580                 .tx_free_thresh = 32,
 581                 .tx_rs_thresh = 32,
 582         };
 583         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 584
 585         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 586         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 587         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 588         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 589         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 590
 591         /* *INDENT-ON* */
 592
 593         /*
 594          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 595          *       need further investigation.
 596          */
 597
 598         /* VMDq resources */
 599         vpool = 64; /* ETH_64_POOLS */
 600         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 601         for (i = 0; i < 4; vpool >>= 1, i++) {
 602                 if (max_vnics > vpool) {
 603                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 604                                 if (dev_info->max_rx_queues > vrxq) {
 605                                         if (vpool > vrxq)
 606                                                 vpool = vrxq;
 607                                         goto found;
 608                                 }
 609                         }
 610                         /* Not enough resources to support VMDq */
 611                         break;
 612                 }
 613         }
 614         /* Not enough resources to support VMDq */
 615         vpool = 0;
 616         vrxq = 0;
 617 found:
 618         dev_info->max_vmdq_pools = vpool;
 619         dev_info->vmdq_queue_num = vrxq;
 620
 621         dev_info->vmdq_pool_base = 0;
 622         dev_info->vmdq_queue_base = 0;
 623
 624         return 0;
 625 }
 626
 627 /* Configure the device based on the configuration provided */
 628 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 629 {
 630         struct bnxt *bp = eth_dev->data->dev_private;
 631         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 632         int rc;
 633
 634         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 635         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 636         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 637         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 638
 639         rc = is_bnxt_in_error(bp);
 640         if (rc)
 641                 return rc;
 642
 643         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 644                 rc = bnxt_hwrm_check_vf_rings(bp);
 645                 if (rc) {
 646                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 647                         return -ENOSPC;
 648                 }
 649
 650                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 651                 if (rc) {
 652                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 653                         return -ENOSPC;
 654                 }
 655         } else {
 656                 /* legacy driver needs to get updated values */
 657                 rc = bnxt_hwrm_func_qcaps(bp);
 658                 if (rc) {
 659                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 660                         return rc;
 661                 }
 662         }
 663
 664         /* Inherit new configurations */
 665         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 666             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 667             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 668                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 669             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 670             bp->max_stat_ctx)
 671                 goto resource_error;
 672
 673         if (BNXT_HAS_RING_GRPS(bp) &&
 674             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 675                 goto resource_error;
 676
 677         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 678             bp->max_vnics < eth_dev->data->nb_rx_queues)
 679                 goto resource_error;
 680
 681         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 682         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 683
 684         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 685                 eth_dev->data->mtu =
 686                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 687                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 688                         BNXT_NUM_VLANS;
 689                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 690         }
 691         return 0;
 692
 693 resource_error:
 694         PMD_DRV_LOG(ERR,
 695                     "Insufficient resources to support requested config\n");
 696         PMD_DRV_LOG(ERR,
 697                     "Num Queues Requested: Tx %d, Rx %d\n",
 698                     eth_dev->data->nb_tx_queues,
 699                     eth_dev->data->nb_rx_queues);
 700         PMD_DRV_LOG(ERR,
 701                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 702                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 703                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 704         return -ENOSPC;
 705 }
 706
 707 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 708 {
 709         struct rte_eth_link *link = &eth_dev->data->dev_link;
 710
 711         if (link->link_status)
 712                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 713                         eth_dev->data->port_id,
 714                         (uint32_t)link->link_speed,
 715                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 716                         ("full-duplex") : ("half-duplex\n"));
 717         else
 718                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 719                         eth_dev->data->port_id);
 720 }
 721
 722 /*
 723  * Determine whether the current configuration requires support for scattered
 724  * receive; return 1 if scattered receive is required and 0 if not.
 725  */
 726 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 727 {
 728         uint16_t buf_size;
 729         int i;
 730
 731         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 732                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 733
 734                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 735                                       RTE_PKTMBUF_HEADROOM);
 736                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 737                         return 1;
 738         }
 739         return 0;
 740 }
 741
 742 static eth_rx_burst_t
 743 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 744 {
 745 #ifdef RTE_ARCH_X86
 746 #ifndef RTE_LIBRTE_IEEE1588
 747         /*
 748          * Vector mode receive can be enabled only if scatter rx is not
 749          * in use and rx offloads are limited to VLAN stripping and
 750          * CRC stripping.
 751          */
 752         if (!eth_dev->data->scattered_rx &&
 753             !(eth_dev->data->dev_conf.rxmode.offloads &
 754               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 755                 DEV_RX_OFFLOAD_KEEP_CRC |
 756                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 757                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 758                 DEV_RX_OFFLOAD_UDP_CKSUM |
 759                 DEV_RX_OFFLOAD_TCP_CKSUM |
 760                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 761                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 762                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 763                             eth_dev->data->port_id);
 764                 return bnxt_recv_pkts_vec;
 765         }
 766         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 767                     eth_dev->data->port_id);
 768         PMD_DRV_LOG(INFO,
 769                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 770                     eth_dev->data->port_id,
 771                     eth_dev->data->scattered_rx,
 772                     eth_dev->data->dev_conf.rxmode.offloads);
 773 #endif
 774 #endif
 775         return bnxt_recv_pkts;
 776 }
 777
 778 static eth_tx_burst_t
 779 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 780 {
 781 #ifdef RTE_ARCH_X86
 782 #ifndef RTE_LIBRTE_IEEE1588
 783         /*
 784          * Vector mode transmit can be enabled only if not using scatter rx
 785          * or tx offloads.
 786          */
 787         if (!eth_dev->data->scattered_rx &&
 788             !eth_dev->data->dev_conf.txmode.offloads) {
 789                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 790                             eth_dev->data->port_id);
 791                 return bnxt_xmit_pkts_vec;
 792         }
 793         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 794                     eth_dev->data->port_id);
 795         PMD_DRV_LOG(INFO,
 796                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 797                     eth_dev->data->port_id,
 798                     eth_dev->data->scattered_rx,
 799                     eth_dev->data->dev_conf.txmode.offloads);
 800 #endif
 801 #endif
 802         return bnxt_xmit_pkts;
 803 }
 804
 805 static int bnxt_handle_if_change_status(struct bnxt *bp)
 806 {
 807         int rc;
 808
 809         /* Since fw has undergone a reset and lost all contexts,
 810          * set fatal flag to not issue hwrm during cleanup
 811          */
 812         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 813         bnxt_uninit_resources(bp, true);
 814
 815         /* clear fatal flag so that re-init happens */
 816         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 817         rc = bnxt_init_resources(bp, true);
 818
 819         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 820
 821         return rc;
 822 }
 823
 824 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 825 {
 826         struct bnxt *bp = eth_dev->data->dev_private;
 827         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 828         int vlan_mask = 0;
 829         int rc;
 830
 831         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 832                 PMD_DRV_LOG(ERR,
 833                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 834                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 835         }
 836
 837         rc = bnxt_hwrm_if_change(bp, 1);
 838         if (!rc) {
 839                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 840                         rc = bnxt_handle_if_change_status(bp);
 841                         if (rc)
 842                                 return rc;
 843                 }
 844         }
 845
 846         rc = bnxt_init_chip(bp);
 847         if (rc)
 848                 goto error;
 849
 850         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 851
 852         bnxt_link_update_op(eth_dev, 1);
 853
 854         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 855                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 856         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 857                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 858         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 859         if (rc)
 860                 goto error;
 861
 862         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 863         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 864
 865         bnxt_enable_int(bp);
 866         bp->flags |= BNXT_FLAG_INIT_DONE;
 867         eth_dev->data->dev_started = 1;
 868         bp->dev_stopped = 0;
 869         bnxt_schedule_fw_health_check(bp);
 870         return 0;
 871
 872 error:
 873         bnxt_hwrm_if_change(bp, 0);
 874         bnxt_shutdown_nic(bp);
 875         bnxt_free_tx_mbufs(bp);
 876         bnxt_free_rx_mbufs(bp);
 877         return rc;
 878 }
 879
 880 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 881 {
 882         struct bnxt *bp = eth_dev->data->dev_private;
 883         int rc = 0;
 884
 885         if (!bp->link_info.link_up)
 886                 rc = bnxt_set_hwrm_link_config(bp, true);
 887         if (!rc)
 888                 eth_dev->data->dev_link.link_status = 1;
 889
 890         bnxt_print_link_info(eth_dev);
 891         return 0;
 892 }
 893
 894 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 895 {
 896         struct bnxt *bp = eth_dev->data->dev_private;
 897
 898         eth_dev->data->dev_link.link_status = 0;
 899         bnxt_set_hwrm_link_config(bp, false);
 900         bp->link_info.link_up = 0;
 901
 902         return 0;
 903 }
 904
 905 /* Unload the driver, release resources */
 906 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 907 {
 908         struct bnxt *bp = eth_dev->data->dev_private;
 909         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 910         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 911
 912         eth_dev->data->dev_started = 0;
 913         /* Prevent crashes when queues are still in use */
 914         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 915         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 916
 917         bnxt_disable_int(bp);
 918
 919         /* disable uio/vfio intr/eventfd mapping */
 920         rte_intr_disable(intr_handle);
 921
 922         bnxt_cancel_fw_health_check(bp);
 923
 924         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 925         if (bp->eth_dev->data->dev_started) {
 926                 /* TBD: STOP HW queues DMA */
 927                 eth_dev->data->dev_link.link_status = 0;
 928         }
 929         bnxt_set_hwrm_link_config(bp, false);
 930
 931         /* Clean queue intr-vector mapping */
 932         rte_intr_efd_disable(intr_handle);
 933         if (intr_handle->intr_vec != NULL) {
 934                 rte_free(intr_handle->intr_vec);
 935                 intr_handle->intr_vec = NULL;
 936         }
 937
 938         bnxt_hwrm_port_clr_stats(bp);
 939         bnxt_free_tx_mbufs(bp);
 940         bnxt_free_rx_mbufs(bp);
 941         bnxt_shutdown_nic(bp);
 942         bnxt_hwrm_if_change(bp, 0);
 943         bp->dev_stopped = 1;
 944 }
 945
 946 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 947 {
 948         struct bnxt *bp = eth_dev->data->dev_private;
 949
 950         if (bp->dev_stopped == 0)
 951                 bnxt_dev_stop_op(eth_dev);
 952
 953         if (eth_dev->data->mac_addrs != NULL) {
 954                 rte_free(eth_dev->data->mac_addrs);
 955                 eth_dev->data->mac_addrs = NULL;
 956         }
 957         if (bp->grp_info != NULL) {
 958                 rte_free(bp->grp_info);
 959                 bp->grp_info = NULL;
 960         }
 961
 962         bnxt_dev_uninit(eth_dev);
 963 }
 964
 965 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 966                                     uint32_t index)
 967 {
 968         struct bnxt *bp = eth_dev->data->dev_private;
 969         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 970         struct bnxt_vnic_info *vnic;
 971         struct bnxt_filter_info *filter, *temp_filter;
 972         uint32_t i;
 973
 974         if (is_bnxt_in_error(bp))
 975                 return;
 976
 977         /*
 978          * Loop through all VNICs from the specified filter flow pools to
 979          * remove the corresponding MAC addr filter
 980          */
 981         for (i = 0; i < bp->nr_vnics; i++) {
 982                 if (!(pool_mask & (1ULL << i)))
 983                         continue;
 984
 985                 vnic = &bp->vnic_info[i];
 986                 filter = STAILQ_FIRST(&vnic->filter);
 987                 while (filter) {
 988                         temp_filter = STAILQ_NEXT(filter, next);
 989                         if (filter->mac_index == index) {
 990                                 STAILQ_REMOVE(&vnic->filter, filter,
 991                                                 bnxt_filter_info, next);
 992                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 993                                 filter->mac_index = INVALID_MAC_INDEX;
 994                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 995                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 996                                                    filter, next);
 997                         }
 998                         filter = temp_filter;
 999                 }
1000         }
1001 }
1002
1003 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1004                                 struct rte_ether_addr *mac_addr,
1005                                 uint32_t index, uint32_t pool)
1006 {
1007         struct bnxt *bp = eth_dev->data->dev_private;
1008         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1009         struct bnxt_filter_info *filter;
1010         int rc = 0;
1011
1012         rc = is_bnxt_in_error(bp);
1013         if (rc)
1014                 return rc;
1015
1016         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1017                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1018                 return -ENOTSUP;
1019         }
1020
1021         if (!vnic) {
1022                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1023                 return -EINVAL;
1024         }
1025         /* Attach requested MAC address to the new l2_filter */
1026         STAILQ_FOREACH(filter, &vnic->filter, next) {
1027                 if (filter->mac_index == index) {
1028                         PMD_DRV_LOG(ERR,
1029                                 "MAC addr already existed for pool %d\n", pool);
1030                         return 0;
1031                 }
1032         }
1033         filter = bnxt_alloc_filter(bp);
1034         if (!filter) {
1035                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1036                 return -ENODEV;
1037         }
1038
1039         filter->mac_index = index;
1040         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1041
1042         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1043         if (!rc) {
1044                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1045         } else {
1046                 filter->mac_index = INVALID_MAC_INDEX;
1047                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1048                 bnxt_free_filter(bp, filter);
1049         }
1050
1051         return rc;
1052 }
1053
1054 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1055 {
1056         int rc = 0;
1057         struct bnxt *bp = eth_dev->data->dev_private;
1058         struct rte_eth_link new;
1059         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1060
1061         rc = is_bnxt_in_error(bp);
1062         if (rc)
1063                 return rc;
1064
1065         memset(&new, 0, sizeof(new));
1066         do {
1067                 /* Retrieve link info from hardware */
1068                 rc = bnxt_get_hwrm_link_config(bp, &new);
1069                 if (rc) {
1070                         new.link_speed = ETH_LINK_SPEED_100M;
1071                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1072                         PMD_DRV_LOG(ERR,
1073                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1074                         goto out;
1075                 }
1076
1077                 if (!wait_to_complete || new.link_status)
1078                         break;
1079
1080                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1081         } while (cnt--);
1082
1083 out:
1084         /* Timed out or success */
1085         if (new.link_status != eth_dev->data->dev_link.link_status ||
1086         new.link_speed != eth_dev->data->dev_link.link_speed) {
1087                 memcpy(&eth_dev->data->dev_link, &new,
1088                         sizeof(struct rte_eth_link));
1089
1090                 _rte_eth_dev_callback_process(eth_dev,
1091                                               RTE_ETH_EVENT_INTR_LSC,
1092                                               NULL);
1093
1094                 bnxt_print_link_info(eth_dev);
1095         }
1096
1097         return rc;
1098 }
1099
1100 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1101 {
1102         struct bnxt *bp = eth_dev->data->dev_private;
1103         struct bnxt_vnic_info *vnic;
1104         uint32_t old_flags;
1105         int rc;
1106
1107         rc = is_bnxt_in_error(bp);
1108         if (rc)
1109                 return rc;
1110
1111         if (bp->vnic_info == NULL)
1112                 return 0;
1113
1114         vnic = &bp->vnic_info[0];
1115
1116         old_flags = vnic->flags;
1117         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1118         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1119         if (rc != 0)
1120                 vnic->flags = old_flags;
1121
1122         return rc;
1123 }
1124
1125 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1126 {
1127         struct bnxt *bp = eth_dev->data->dev_private;
1128         struct bnxt_vnic_info *vnic;
1129         uint32_t old_flags;
1130         int rc;
1131
1132         rc = is_bnxt_in_error(bp);
1133         if (rc)
1134                 return rc;
1135
1136         if (bp->vnic_info == NULL)
1137                 return 0;
1138
1139         vnic = &bp->vnic_info[0];
1140
1141         old_flags = vnic->flags;
1142         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1143         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1144         if (rc != 0)
1145                 vnic->flags = old_flags;
1146
1147         return rc;
1148 }
1149
1150 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1151 {
1152         struct bnxt *bp = eth_dev->data->dev_private;
1153         struct bnxt_vnic_info *vnic;
1154         uint32_t old_flags;
1155         int rc;
1156
1157         rc = is_bnxt_in_error(bp);
1158         if (rc)
1159                 return rc;
1160
1161         if (bp->vnic_info == NULL)
1162                 return 0;
1163
1164         vnic = &bp->vnic_info[0];
1165
1166         old_flags = vnic->flags;
1167         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1168         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1169         if (rc != 0)
1170                 vnic->flags = old_flags;
1171
1172         return rc;
1173 }
1174
1175 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1176 {
1177         struct bnxt *bp = eth_dev->data->dev_private;
1178         struct bnxt_vnic_info *vnic;
1179         uint32_t old_flags;
1180         int rc;
1181
1182         rc = is_bnxt_in_error(bp);
1183         if (rc)
1184                 return rc;
1185
1186         if (bp->vnic_info == NULL)
1187                 return 0;
1188
1189         vnic = &bp->vnic_info[0];
1190
1191         old_flags = vnic->flags;
1192         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1193         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1194         if (rc != 0)
1195                 vnic->flags = old_flags;
1196
1197         return rc;
1198 }
1199
1200 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1201 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1202 {
1203         if (qid >= bp->rx_nr_rings)
1204                 return NULL;
1205
1206         return bp->eth_dev->data->rx_queues[qid];
1207 }
1208
1209 /* Return rxq corresponding to a given rss table ring/group ID. */
1210 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1211 {
1212         struct bnxt_rx_queue *rxq;
1213         unsigned int i;
1214
1215         if (!BNXT_HAS_RING_GRPS(bp)) {
1216                 for (i = 0; i < bp->rx_nr_rings; i++) {
1217                         rxq = bp->eth_dev->data->rx_queues[i];
1218                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1219                                 return rxq->index;
1220                 }
1221         } else {
1222                 for (i = 0; i < bp->rx_nr_rings; i++) {
1223                         if (bp->grp_info[i].fw_grp_id == fwr)
1224                                 return i;
1225                 }
1226         }
1227
1228         return INVALID_HW_RING_ID;
1229 }
1230
1231 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1232                             struct rte_eth_rss_reta_entry64 *reta_conf,
1233                             uint16_t reta_size)
1234 {
1235         struct bnxt *bp = eth_dev->data->dev_private;
1236         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1237         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1238         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1239         uint16_t idx, sft;
1240         int i, rc;
1241
1242         rc = is_bnxt_in_error(bp);
1243         if (rc)
1244                 return rc;
1245
1246         if (!vnic->rss_table)
1247                 return -EINVAL;
1248
1249         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1250                 return -EINVAL;
1251
1252         if (reta_size != tbl_size) {
1253                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1254                         "(%d) must equal the size supported by the hardware "
1255                         "(%d)\n", reta_size, tbl_size);
1256                 return -EINVAL;
1257         }
1258
1259         for (i = 0; i < reta_size; i++) {
1260                 struct bnxt_rx_queue *rxq;
1261
1262                 idx = i / RTE_RETA_GROUP_SIZE;
1263                 sft = i % RTE_RETA_GROUP_SIZE;
1264
1265                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1266                         continue;
1267
1268                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1269                 if (!rxq) {
1270                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1271                         return -EINVAL;
1272                 }
1273
1274                 if (BNXT_CHIP_THOR(bp)) {
1275                         vnic->rss_table[i * 2] =
1276                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1277                         vnic->rss_table[i * 2 + 1] =
1278                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1279                 } else {
1280                         vnic->rss_table[i] =
1281                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1282                 }
1283
1284                 vnic->rss_table[i] =
1285                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1286         }
1287
1288         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1289         return 0;
1290 }
1291
1292 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1293                               struct rte_eth_rss_reta_entry64 *reta_conf,
1294                               uint16_t reta_size)
1295 {
1296         struct bnxt *bp = eth_dev->data->dev_private;
1297         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1298         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1299         uint16_t idx, sft, i;
1300         int rc;
1301
1302         rc = is_bnxt_in_error(bp);
1303         if (rc)
1304                 return rc;
1305
1306         /* Retrieve from the default VNIC */
1307         if (!vnic)
1308                 return -EINVAL;
1309         if (!vnic->rss_table)
1310                 return -EINVAL;
1311
1312         if (reta_size != tbl_size) {
1313                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1314                         "(%d) must equal the size supported by the hardware "
1315                         "(%d)\n", reta_size, tbl_size);
1316                 return -EINVAL;
1317         }
1318
1319         for (idx = 0, i = 0; i < reta_size; i++) {
1320                 idx = i / RTE_RETA_GROUP_SIZE;
1321                 sft = i % RTE_RETA_GROUP_SIZE;
1322
1323                 if (reta_conf[idx].mask & (1ULL << sft)) {
1324                         uint16_t qid;
1325
1326                         if (BNXT_CHIP_THOR(bp))
1327                                 qid = bnxt_rss_to_qid(bp,
1328                                                       vnic->rss_table[i * 2]);
1329                         else
1330                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1331
1332                         if (qid == INVALID_HW_RING_ID) {
1333                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1334                                 return -EINVAL;
1335                         }
1336                         reta_conf[idx].reta[sft] = qid;
1337                 }
1338         }
1339
1340         return 0;
1341 }
1342
1343 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1344                                    struct rte_eth_rss_conf *rss_conf)
1345 {
1346         struct bnxt *bp = eth_dev->data->dev_private;
1347         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1348         struct bnxt_vnic_info *vnic;
1349         uint16_t hash_type = 0;
1350         unsigned int i;
1351         int rc;
1352
1353         rc = is_bnxt_in_error(bp);
1354         if (rc)
1355                 return rc;
1356
1357         /*
1358          * If RSS enablement were different than dev_configure,
1359          * then return -EINVAL
1360          */
1361         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1362                 if (!rss_conf->rss_hf)
1363                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1364         } else {
1365                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1366                         return -EINVAL;
1367         }
1368
1369         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1370         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1371
1372         if (rss_conf->rss_hf & ETH_RSS_IPV4)
1373                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1374         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1375                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1376         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1377                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1378         if (rss_conf->rss_hf & ETH_RSS_IPV6)
1379                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1380         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1381                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1382         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1383                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1384
1385         /* Update the RSS VNIC(s) */
1386         for (i = 0; i < bp->nr_vnics; i++) {
1387                 vnic = &bp->vnic_info[i];
1388                 vnic->hash_type = hash_type;
1389
1390                 /*
1391                  * Use the supplied key if the key length is
1392                  * acceptable and the rss_key is not NULL
1393                  */
1394                 if (rss_conf->rss_key &&
1395                     rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1396                         memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1397                                rss_conf->rss_key_len);
1398
1399                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1400         }
1401         return 0;
1402 }
1403
1404 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1405                                      struct rte_eth_rss_conf *rss_conf)
1406 {
1407         struct bnxt *bp = eth_dev->data->dev_private;
1408         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1409         int len, rc;
1410         uint32_t hash_types;
1411
1412         rc = is_bnxt_in_error(bp);
1413         if (rc)
1414                 return rc;
1415
1416         /* RSS configuration is the same for all VNICs */
1417         if (vnic && vnic->rss_hash_key) {
1418                 if (rss_conf->rss_key) {
1419                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1420                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1421                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1422                 }
1423
1424                 hash_types = vnic->hash_type;
1425                 rss_conf->rss_hf = 0;
1426                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1427                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1428                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1429                 }
1430                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1431                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1432                         hash_types &=
1433                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1434                 }
1435                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1436                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1437                         hash_types &=
1438                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1439                 }
1440                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1441                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1442                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1443                 }
1444                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1445                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1446                         hash_types &=
1447                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1448                 }
1449                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1450                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1451                         hash_types &=
1452                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1453                 }
1454                 if (hash_types) {
1455                         PMD_DRV_LOG(ERR,
1456                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1457                                 vnic->hash_type);
1458                         return -ENOTSUP;
1459                 }
1460         } else {
1461                 rss_conf->rss_hf = 0;
1462         }
1463         return 0;
1464 }
1465
1466 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1467                                struct rte_eth_fc_conf *fc_conf)
1468 {
1469         struct bnxt *bp = dev->data->dev_private;
1470         struct rte_eth_link link_info;
1471         int rc;
1472
1473         rc = is_bnxt_in_error(bp);
1474         if (rc)
1475                 return rc;
1476
1477         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1478         if (rc)
1479                 return rc;
1480
1481         memset(fc_conf, 0, sizeof(*fc_conf));
1482         if (bp->link_info.auto_pause)
1483                 fc_conf->autoneg = 1;
1484         switch (bp->link_info.pause) {
1485         case 0:
1486                 fc_conf->mode = RTE_FC_NONE;
1487                 break;
1488         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1489                 fc_conf->mode = RTE_FC_TX_PAUSE;
1490                 break;
1491         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1492                 fc_conf->mode = RTE_FC_RX_PAUSE;
1493                 break;
1494         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1495                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1496                 fc_conf->mode = RTE_FC_FULL;
1497                 break;
1498         }
1499         return 0;
1500 }
1501
1502 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1503                                struct rte_eth_fc_conf *fc_conf)
1504 {
1505         struct bnxt *bp = dev->data->dev_private;
1506         int rc;
1507
1508         rc = is_bnxt_in_error(bp);
1509         if (rc)
1510                 return rc;
1511
1512         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1513                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1514                 return -ENOTSUP;
1515         }
1516
1517         switch (fc_conf->mode) {
1518         case RTE_FC_NONE:
1519                 bp->link_info.auto_pause = 0;
1520                 bp->link_info.force_pause = 0;
1521                 break;
1522         case RTE_FC_RX_PAUSE:
1523                 if (fc_conf->autoneg) {
1524                         bp->link_info.auto_pause =
1525                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1526                         bp->link_info.force_pause = 0;
1527                 } else {
1528                         bp->link_info.auto_pause = 0;
1529                         bp->link_info.force_pause =
1530                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1531                 }
1532                 break;
1533         case RTE_FC_TX_PAUSE:
1534                 if (fc_conf->autoneg) {
1535                         bp->link_info.auto_pause =
1536                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1537                         bp->link_info.force_pause = 0;
1538                 } else {
1539                         bp->link_info.auto_pause = 0;
1540                         bp->link_info.force_pause =
1541                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1542                 }
1543                 break;
1544         case RTE_FC_FULL:
1545                 if (fc_conf->autoneg) {
1546                         bp->link_info.auto_pause =
1547                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1548                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1549                         bp->link_info.force_pause = 0;
1550                 } else {
1551                         bp->link_info.auto_pause = 0;
1552                         bp->link_info.force_pause =
1553                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1554                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1555                 }
1556                 break;
1557         }
1558         return bnxt_set_hwrm_link_config(bp, true);
1559 }
1560
1561 /* Add UDP tunneling port */
1562 static int
1563 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1564                          struct rte_eth_udp_tunnel *udp_tunnel)
1565 {
1566         struct bnxt *bp = eth_dev->data->dev_private;
1567         uint16_t tunnel_type = 0;
1568         int rc = 0;
1569
1570         rc = is_bnxt_in_error(bp);
1571         if (rc)
1572                 return rc;
1573
1574         switch (udp_tunnel->prot_type) {
1575         case RTE_TUNNEL_TYPE_VXLAN:
1576                 if (bp->vxlan_port_cnt) {
1577                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1578                                 udp_tunnel->udp_port);
1579                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1580                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1581                                 return -ENOSPC;
1582                         }
1583                         bp->vxlan_port_cnt++;
1584                         return 0;
1585                 }
1586                 tunnel_type =
1587                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1588                 bp->vxlan_port_cnt++;
1589                 break;
1590         case RTE_TUNNEL_TYPE_GENEVE:
1591                 if (bp->geneve_port_cnt) {
1592                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1593                                 udp_tunnel->udp_port);
1594                         if (bp->geneve_port != udp_tunnel->udp_port) {
1595                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1596                                 return -ENOSPC;
1597                         }
1598                         bp->geneve_port_cnt++;
1599                         return 0;
1600                 }
1601                 tunnel_type =
1602                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1603                 bp->geneve_port_cnt++;
1604                 break;
1605         default:
1606                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1607                 return -ENOTSUP;
1608         }
1609         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1610                                              tunnel_type);
1611         return rc;
1612 }
1613
1614 static int
1615 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1616                          struct rte_eth_udp_tunnel *udp_tunnel)
1617 {
1618         struct bnxt *bp = eth_dev->data->dev_private;
1619         uint16_t tunnel_type = 0;
1620         uint16_t port = 0;
1621         int rc = 0;
1622
1623         rc = is_bnxt_in_error(bp);
1624         if (rc)
1625                 return rc;
1626
1627         switch (udp_tunnel->prot_type) {
1628         case RTE_TUNNEL_TYPE_VXLAN:
1629                 if (!bp->vxlan_port_cnt) {
1630                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1631                         return -EINVAL;
1632                 }
1633                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1634                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1635                                 udp_tunnel->udp_port, bp->vxlan_port);
1636                         return -EINVAL;
1637                 }
1638                 if (--bp->vxlan_port_cnt)
1639                         return 0;
1640
1641                 tunnel_type =
1642                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1643                 port = bp->vxlan_fw_dst_port_id;
1644                 break;
1645         case RTE_TUNNEL_TYPE_GENEVE:
1646                 if (!bp->geneve_port_cnt) {
1647                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1648                         return -EINVAL;
1649                 }
1650                 if (bp->geneve_port != udp_tunnel->udp_port) {
1651                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1652                                 udp_tunnel->udp_port, bp->geneve_port);
1653                         return -EINVAL;
1654                 }
1655                 if (--bp->geneve_port_cnt)
1656                         return 0;
1657
1658                 tunnel_type =
1659                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1660                 port = bp->geneve_fw_dst_port_id;
1661                 break;
1662         default:
1663                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1664                 return -ENOTSUP;
1665         }
1666
1667         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1668         if (!rc) {
1669                 if (tunnel_type ==
1670                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1671                         bp->vxlan_port = 0;
1672                 if (tunnel_type ==
1673                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1674                         bp->geneve_port = 0;
1675         }
1676         return rc;
1677 }
1678
1679 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1680 {
1681         struct bnxt_filter_info *filter;
1682         struct bnxt_vnic_info *vnic;
1683         int rc = 0;
1684         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1685
1686         /* if VLAN exists && VLAN matches vlan_id
1687          *      remove the MAC+VLAN filter
1688          *      add a new MAC only filter
1689          * else
1690          *      VLAN filter doesn't exist, just skip and continue
1691          */
1692         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1693         filter = STAILQ_FIRST(&vnic->filter);
1694         while (filter) {
1695                 /* Search for this matching MAC+VLAN filter */
1696                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1697                     !memcmp(filter->l2_addr,
1698                             bp->mac_addr,
1699                             RTE_ETHER_ADDR_LEN)) {
1700                         /* Delete the filter */
1701                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1702                         if (rc)
1703                                 return rc;
1704                         STAILQ_REMOVE(&vnic->filter, filter,
1705                                       bnxt_filter_info, next);
1706                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1707
1708                         PMD_DRV_LOG(INFO,
1709                                     "Del Vlan filter for %d\n",
1710                                     vlan_id);
1711                         return rc;
1712                 }
1713                 filter = STAILQ_NEXT(filter, next);
1714         }
1715         return -ENOENT;
1716 }
1717
1718 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1719 {
1720         struct bnxt_filter_info *filter;
1721         struct bnxt_vnic_info *vnic;
1722         int rc = 0;
1723         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1724                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1725         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1726
1727         /* Implementation notes on the use of VNIC in this command:
1728          *
1729          * By default, these filters belong to default vnic for the function.
1730          * Once these filters are set up, only destination VNIC can be modified.
1731          * If the destination VNIC is not specified in this command,
1732          * then the HWRM shall only create an l2 context id.
1733          */
1734
1735         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1736         filter = STAILQ_FIRST(&vnic->filter);
1737         /* Check if the VLAN has already been added */
1738         while (filter) {
1739                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1740                     !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1741                         return -EEXIST;
1742
1743                 filter = STAILQ_NEXT(filter, next);
1744         }
1745
1746         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1747          * command to create MAC+VLAN filter with the right flags, enables set.
1748          */
1749         filter = bnxt_alloc_filter(bp);
1750         if (!filter) {
1751                 PMD_DRV_LOG(ERR,
1752                             "MAC/VLAN filter alloc failed\n");
1753                 return -ENOMEM;
1754         }
1755         /* MAC + VLAN ID filter */
1756         filter->l2_ivlan = vlan_id;
1757         filter->l2_ivlan_mask = 0x0FFF;
1758         filter->enables |= en;
1759         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1760         if (rc) {
1761                 /* Free the newly allocated filter as we were
1762                  * not able to create the filter in hardware.
1763                  */
1764                 filter->fw_l2_filter_id = UINT64_MAX;
1765                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1766                 return rc;
1767         }
1768
1769         /* Add this new filter to the list */
1770         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1771         PMD_DRV_LOG(INFO,
1772                     "Added Vlan filter for %d\n", vlan_id);
1773         return rc;
1774 }
1775
1776 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1777                 uint16_t vlan_id, int on)
1778 {
1779         struct bnxt *bp = eth_dev->data->dev_private;
1780         int rc;
1781
1782         rc = is_bnxt_in_error(bp);
1783         if (rc)
1784                 return rc;
1785
1786         /* These operations apply to ALL existing MAC/VLAN filters */
1787         if (on)
1788                 return bnxt_add_vlan_filter(bp, vlan_id);
1789         else
1790                 return bnxt_del_vlan_filter(bp, vlan_id);
1791 }
1792
1793 static int
1794 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1795 {
1796         struct bnxt *bp = dev->data->dev_private;
1797         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1798         unsigned int i;
1799         int rc;
1800
1801         rc = is_bnxt_in_error(bp);
1802         if (rc)
1803                 return rc;
1804
1805         if (mask & ETH_VLAN_FILTER_MASK) {
1806                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1807                         /* Remove any VLAN filters programmed */
1808                         for (i = 0; i < 4095; i++)
1809                                 bnxt_del_vlan_filter(bp, i);
1810                 }
1811                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1812                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1813         }
1814
1815         if (mask & ETH_VLAN_STRIP_MASK) {
1816                 /* Enable or disable VLAN stripping */
1817                 for (i = 0; i < bp->nr_vnics; i++) {
1818                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1819                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1820                                 vnic->vlan_strip = true;
1821                         else
1822                                 vnic->vlan_strip = false;
1823                         bnxt_hwrm_vnic_cfg(bp, vnic);
1824                 }
1825                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1826                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1827         }
1828
1829         if (mask & ETH_VLAN_EXTEND_MASK)
1830                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1831
1832         return 0;
1833 }
1834
1835 static int
1836 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1837                         struct rte_ether_addr *addr)
1838 {
1839         struct bnxt *bp = dev->data->dev_private;
1840         /* Default Filter is tied to VNIC 0 */
1841         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1842         struct bnxt_filter_info *filter;
1843         int rc;
1844
1845         rc = is_bnxt_in_error(bp);
1846         if (rc)
1847                 return rc;
1848
1849         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1850                 return -EPERM;
1851
1852         if (rte_is_zero_ether_addr(addr))
1853                 return -EINVAL;
1854
1855         STAILQ_FOREACH(filter, &vnic->filter, next) {
1856                 /* Default Filter is at Index 0 */
1857                 if (filter->mac_index != 0)
1858                         continue;
1859
1860                 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1861                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1862                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1863                 filter->enables |=
1864                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1865                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1866
1867                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1868                 if (rc)
1869                         return rc;
1870
1871                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1872                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1873                 return 0;
1874         }
1875
1876         return 0;
1877 }
1878
1879 static int
1880 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1881                           struct rte_ether_addr *mc_addr_set,
1882                           uint32_t nb_mc_addr)
1883 {
1884         struct bnxt *bp = eth_dev->data->dev_private;
1885         char *mc_addr_list = (char *)mc_addr_set;
1886         struct bnxt_vnic_info *vnic;
1887         uint32_t off = 0, i = 0;
1888         int rc;
1889
1890         rc = is_bnxt_in_error(bp);
1891         if (rc)
1892                 return rc;
1893
1894         vnic = &bp->vnic_info[0];
1895
1896         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1897                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1898                 goto allmulti;
1899         }
1900
1901         /* TODO Check for Duplicate mcast addresses */
1902         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1903         for (i = 0; i < nb_mc_addr; i++) {
1904                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1905                         RTE_ETHER_ADDR_LEN);
1906                 off += RTE_ETHER_ADDR_LEN;
1907         }
1908
1909         vnic->mc_addr_cnt = i;
1910
1911 allmulti:
1912         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1913 }
1914
1915 static int
1916 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1917 {
1918         struct bnxt *bp = dev->data->dev_private;
1919         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1920         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1921         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1922         int ret;
1923
1924         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1925                         fw_major, fw_minor, fw_updt);
1926
1927         ret += 1; /* add the size of '\0' */
1928         if (fw_size < (uint32_t)ret)
1929                 return ret;
1930         else
1931                 return 0;
1932 }
1933
1934 static void
1935 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1936         struct rte_eth_rxq_info *qinfo)
1937 {
1938         struct bnxt_rx_queue *rxq;
1939
1940         rxq = dev->data->rx_queues[queue_id];
1941
1942         qinfo->mp = rxq->mb_pool;
1943         qinfo->scattered_rx = dev->data->scattered_rx;
1944         qinfo->nb_desc = rxq->nb_rx_desc;
1945
1946         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1947         qinfo->conf.rx_drop_en = 0;
1948         qinfo->conf.rx_deferred_start = 0;
1949 }
1950
1951 static void
1952 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1953         struct rte_eth_txq_info *qinfo)
1954 {
1955         struct bnxt_tx_queue *txq;
1956
1957         txq = dev->data->tx_queues[queue_id];
1958
1959         qinfo->nb_desc = txq->nb_tx_desc;
1960
1961         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1962         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1963         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1964
1965         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1966         qinfo->conf.tx_rs_thresh = 0;
1967         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1968 }
1969
1970 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1971 {
1972         struct bnxt *bp = eth_dev->data->dev_private;
1973         uint32_t new_pkt_size;
1974         uint32_t rc = 0;
1975         uint32_t i;
1976
1977         rc = is_bnxt_in_error(bp);
1978         if (rc)
1979                 return rc;
1980
1981         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1982                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1983
1984 #ifdef RTE_ARCH_X86
1985         /*
1986          * If vector-mode tx/rx is active, disallow any MTU change that would
1987          * require scattered receive support.
1988          */
1989         if (eth_dev->data->dev_started &&
1990             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1991              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1992             (new_pkt_size >
1993              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1994                 PMD_DRV_LOG(ERR,
1995                             "MTU change would require scattered rx support. ");
1996                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1997                 return -EINVAL;
1998         }
1999 #endif
2000
2001         if (new_mtu > RTE_ETHER_MTU) {
2002                 bp->flags |= BNXT_FLAG_JUMBO;
2003                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2004                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2005         } else {
2006                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2007                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2008                 bp->flags &= ~BNXT_FLAG_JUMBO;
2009         }
2010
2011         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2012
2013         for (i = 0; i < bp->nr_vnics; i++) {
2014                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2015                 uint16_t size = 0;
2016
2017                 vnic->mru = new_mtu + RTE_ETHER_HDR_LEN +
2018                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2019                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2020                 if (rc)
2021                         break;
2022
2023                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2024                 size -= RTE_PKTMBUF_HEADROOM;
2025
2026                 if (size < new_mtu) {
2027                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2028                         if (rc)
2029                                 return rc;
2030                 }
2031         }
2032
2033         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2034
2035         return rc;
2036 }
2037
2038 static int
2039 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2040 {
2041         struct bnxt *bp = dev->data->dev_private;
2042         uint16_t vlan = bp->vlan;
2043         int rc;
2044
2045         rc = is_bnxt_in_error(bp);
2046         if (rc)
2047                 return rc;
2048
2049         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2050                 PMD_DRV_LOG(ERR,
2051                         "PVID cannot be modified for this function\n");
2052                 return -ENOTSUP;
2053         }
2054         bp->vlan = on ? pvid : 0;
2055
2056         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2057         if (rc)
2058                 bp->vlan = vlan;
2059         return rc;
2060 }
2061
2062 static int
2063 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2064 {
2065         struct bnxt *bp = dev->data->dev_private;
2066         int rc;
2067
2068         rc = is_bnxt_in_error(bp);
2069         if (rc)
2070                 return rc;
2071
2072         return bnxt_hwrm_port_led_cfg(bp, true);
2073 }
2074
2075 static int
2076 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2077 {
2078         struct bnxt *bp = dev->data->dev_private;
2079         int rc;
2080
2081         rc = is_bnxt_in_error(bp);
2082         if (rc)
2083                 return rc;
2084
2085         return bnxt_hwrm_port_led_cfg(bp, false);
2086 }
2087
2088 static uint32_t
2089 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2090 {
2091         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2092         uint32_t desc = 0, raw_cons = 0, cons;
2093         struct bnxt_cp_ring_info *cpr;
2094         struct bnxt_rx_queue *rxq;
2095         struct rx_pkt_cmpl *rxcmp;
2096         uint16_t cmp_type;
2097         uint8_t cmp = 1;
2098         bool valid;
2099         int rc;
2100
2101         rc = is_bnxt_in_error(bp);
2102         if (rc)
2103                 return rc;
2104
2105         rxq = dev->data->rx_queues[rx_queue_id];
2106         cpr = rxq->cp_ring;
2107         valid = cpr->valid;
2108
2109         while (raw_cons < rxq->nb_rx_desc) {
2110                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2111                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2112
2113                 if (!CMPL_VALID(rxcmp, valid))
2114                         goto nothing_to_do;
2115                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
2116                 cmp_type = CMP_TYPE(rxcmp);
2117                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
2118                         cmp = (rte_le_to_cpu_32(
2119                                         ((struct rx_tpa_end_cmpl *)
2120                                          (rxcmp))->agg_bufs_v1) &
2121                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
2122                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
2123                         desc++;
2124                 } else if (cmp_type == 0x11) {
2125                         desc++;
2126                         cmp = (rxcmp->agg_bufs_v1 &
2127                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
2128                                 RX_PKT_CMPL_AGG_BUFS_SFT;
2129                 } else {
2130                         cmp = 1;
2131                 }
2132 nothing_to_do:
2133                 raw_cons += cmp ? cmp : 2;
2134         }
2135
2136         return desc;
2137 }
2138
2139 static int
2140 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2141 {
2142         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2143         struct bnxt_rx_ring_info *rxr;
2144         struct bnxt_cp_ring_info *cpr;
2145         struct bnxt_sw_rx_bd *rx_buf;
2146         struct rx_pkt_cmpl *rxcmp;
2147         uint32_t cons, cp_cons;
2148         int rc;
2149
2150         if (!rxq)
2151                 return -EINVAL;
2152
2153         rc = is_bnxt_in_error(rxq->bp);
2154         if (rc)
2155                 return rc;
2156
2157         cpr = rxq->cp_ring;
2158         rxr = rxq->rx_ring;
2159
2160         if (offset >= rxq->nb_rx_desc)
2161                 return -EINVAL;
2162
2163         cons = RING_CMP(cpr->cp_ring_struct, offset);
2164         cp_cons = cpr->cp_raw_cons;
2165         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2166
2167         if (cons > cp_cons) {
2168                 if (CMPL_VALID(rxcmp, cpr->valid))
2169                         return RTE_ETH_RX_DESC_DONE;
2170         } else {
2171                 if (CMPL_VALID(rxcmp, !cpr->valid))
2172                         return RTE_ETH_RX_DESC_DONE;
2173         }
2174         rx_buf = &rxr->rx_buf_ring[cons];
2175         if (rx_buf->mbuf == NULL)
2176                 return RTE_ETH_RX_DESC_UNAVAIL;
2177
2178
2179         return RTE_ETH_RX_DESC_AVAIL;
2180 }
2181
2182 static int
2183 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2184 {
2185         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2186         struct bnxt_tx_ring_info *txr;
2187         struct bnxt_cp_ring_info *cpr;
2188         struct bnxt_sw_tx_bd *tx_buf;
2189         struct tx_pkt_cmpl *txcmp;
2190         uint32_t cons, cp_cons;
2191         int rc;
2192
2193         if (!txq)
2194                 return -EINVAL;
2195
2196         rc = is_bnxt_in_error(txq->bp);
2197         if (rc)
2198                 return rc;
2199
2200         cpr = txq->cp_ring;
2201         txr = txq->tx_ring;
2202
2203         if (offset >= txq->nb_tx_desc)
2204                 return -EINVAL;
2205
2206         cons = RING_CMP(cpr->cp_ring_struct, offset);
2207         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2208         cp_cons = cpr->cp_raw_cons;
2209
2210         if (cons > cp_cons) {
2211                 if (CMPL_VALID(txcmp, cpr->valid))
2212                         return RTE_ETH_TX_DESC_UNAVAIL;
2213         } else {
2214                 if (CMPL_VALID(txcmp, !cpr->valid))
2215                         return RTE_ETH_TX_DESC_UNAVAIL;
2216         }
2217         tx_buf = &txr->tx_buf_ring[cons];
2218         if (tx_buf->mbuf == NULL)
2219                 return RTE_ETH_TX_DESC_DONE;
2220
2221         return RTE_ETH_TX_DESC_FULL;
2222 }
2223
2224 static struct bnxt_filter_info *
2225 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2226                                 struct rte_eth_ethertype_filter *efilter,
2227                                 struct bnxt_vnic_info *vnic0,
2228                                 struct bnxt_vnic_info *vnic,
2229                                 int *ret)
2230 {
2231         struct bnxt_filter_info *mfilter = NULL;
2232         int match = 0;
2233         *ret = 0;
2234
2235         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2236                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2237                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2238                         " ethertype filter.", efilter->ether_type);
2239                 *ret = -EINVAL;
2240                 goto exit;
2241         }
2242         if (efilter->queue >= bp->rx_nr_rings) {
2243                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2244                 *ret = -EINVAL;
2245                 goto exit;
2246         }
2247
2248         vnic0 = &bp->vnic_info[0];
2249         vnic = &bp->vnic_info[efilter->queue];
2250         if (vnic == NULL) {
2251                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2252                 *ret = -EINVAL;
2253                 goto exit;
2254         }
2255
2256         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2257                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2258                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2259                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2260                              mfilter->flags ==
2261                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2262                              mfilter->ethertype == efilter->ether_type)) {
2263                                 match = 1;
2264                                 break;
2265                         }
2266                 }
2267         } else {
2268                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2269                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2270                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2271                              mfilter->ethertype == efilter->ether_type &&
2272                              mfilter->flags ==
2273                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2274                                 match = 1;
2275                                 break;
2276                         }
2277         }
2278
2279         if (match)
2280                 *ret = -EEXIST;
2281
2282 exit:
2283         return mfilter;
2284 }
2285
2286 static int
2287 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2288                         enum rte_filter_op filter_op,
2289                         void *arg)
2290 {
2291         struct bnxt *bp = dev->data->dev_private;
2292         struct rte_eth_ethertype_filter *efilter =
2293                         (struct rte_eth_ethertype_filter *)arg;
2294         struct bnxt_filter_info *bfilter, *filter1;
2295         struct bnxt_vnic_info *vnic, *vnic0;
2296         int ret;
2297
2298         if (filter_op == RTE_ETH_FILTER_NOP)
2299                 return 0;
2300
2301         if (arg == NULL) {
2302                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2303                             filter_op);
2304                 return -EINVAL;
2305         }
2306
2307         vnic0 = &bp->vnic_info[0];
2308         vnic = &bp->vnic_info[efilter->queue];
2309
2310         switch (filter_op) {
2311         case RTE_ETH_FILTER_ADD:
2312                 bnxt_match_and_validate_ether_filter(bp, efilter,
2313                                                         vnic0, vnic, &ret);
2314                 if (ret < 0)
2315                         return ret;
2316
2317                 bfilter = bnxt_get_unused_filter(bp);
2318                 if (bfilter == NULL) {
2319                         PMD_DRV_LOG(ERR,
2320                                 "Not enough resources for a new filter.\n");
2321                         return -ENOMEM;
2322                 }
2323                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2324                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2325                        RTE_ETHER_ADDR_LEN);
2326                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2327                        RTE_ETHER_ADDR_LEN);
2328                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2329                 bfilter->ethertype = efilter->ether_type;
2330                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2331
2332                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2333                 if (filter1 == NULL) {
2334                         ret = -EINVAL;
2335                         goto cleanup;
2336                 }
2337                 bfilter->enables |=
2338                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2339                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2340
2341                 bfilter->dst_id = vnic->fw_vnic_id;
2342
2343                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2344                         bfilter->flags =
2345                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2346                 }
2347
2348                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2349                 if (ret)
2350                         goto cleanup;
2351                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2352                 break;
2353         case RTE_ETH_FILTER_DELETE:
2354                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2355                                                         vnic0, vnic, &ret);
2356                 if (ret == -EEXIST) {
2357                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2358
2359                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2360                                       next);
2361                         bnxt_free_filter(bp, filter1);
2362                 } else if (ret == 0) {
2363                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2364                 }
2365                 break;
2366         default:
2367                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2368                 ret = -EINVAL;
2369                 goto error;
2370         }
2371         return ret;
2372 cleanup:
2373         bnxt_free_filter(bp, bfilter);
2374 error:
2375         return ret;
2376 }
2377
2378 static inline int
2379 parse_ntuple_filter(struct bnxt *bp,
2380                     struct rte_eth_ntuple_filter *nfilter,
2381                     struct bnxt_filter_info *bfilter)
2382 {
2383         uint32_t en = 0;
2384
2385         if (nfilter->queue >= bp->rx_nr_rings) {
2386                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2387                 return -EINVAL;
2388         }
2389
2390         switch (nfilter->dst_port_mask) {
2391         case UINT16_MAX:
2392                 bfilter->dst_port_mask = -1;
2393                 bfilter->dst_port = nfilter->dst_port;
2394                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2395                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2396                 break;
2397         default:
2398                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2399                 return -EINVAL;
2400         }
2401
2402         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2403         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2404
2405         switch (nfilter->proto_mask) {
2406         case UINT8_MAX:
2407                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2408                         bfilter->ip_protocol = 17;
2409                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2410                         bfilter->ip_protocol = 6;
2411                 else
2412                         return -EINVAL;
2413                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2414                 break;
2415         default:
2416                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2417                 return -EINVAL;
2418         }
2419
2420         switch (nfilter->dst_ip_mask) {
2421         case UINT32_MAX:
2422                 bfilter->dst_ipaddr_mask[0] = -1;
2423                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2424                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2425                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2426                 break;
2427         default:
2428                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2429                 return -EINVAL;
2430         }
2431
2432         switch (nfilter->src_ip_mask) {
2433         case UINT32_MAX:
2434                 bfilter->src_ipaddr_mask[0] = -1;
2435                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2436                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2437                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2438                 break;
2439         default:
2440                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2441                 return -EINVAL;
2442         }
2443
2444         switch (nfilter->src_port_mask) {
2445         case UINT16_MAX:
2446                 bfilter->src_port_mask = -1;
2447                 bfilter->src_port = nfilter->src_port;
2448                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2449                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2450                 break;
2451         default:
2452                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2453                 return -EINVAL;
2454         }
2455
2456         //TODO Priority
2457         //nfilter->priority = (uint8_t)filter->priority;
2458
2459         bfilter->enables = en;
2460         return 0;
2461 }
2462
2463 static struct bnxt_filter_info*
2464 bnxt_match_ntuple_filter(struct bnxt *bp,
2465                          struct bnxt_filter_info *bfilter,
2466                          struct bnxt_vnic_info **mvnic)
2467 {
2468         struct bnxt_filter_info *mfilter = NULL;
2469         int i;
2470
2471         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2472                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2473                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2474                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2475                             bfilter->src_ipaddr_mask[0] ==
2476                             mfilter->src_ipaddr_mask[0] &&
2477                             bfilter->src_port == mfilter->src_port &&
2478                             bfilter->src_port_mask == mfilter->src_port_mask &&
2479                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2480                             bfilter->dst_ipaddr_mask[0] ==
2481                             mfilter->dst_ipaddr_mask[0] &&
2482                             bfilter->dst_port == mfilter->dst_port &&
2483                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2484                             bfilter->flags == mfilter->flags &&
2485                             bfilter->enables == mfilter->enables) {
2486                                 if (mvnic)
2487                                         *mvnic = vnic;
2488                                 return mfilter;
2489                         }
2490                 }
2491         }
2492         return NULL;
2493 }
2494
2495 static int
2496 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2497                        struct rte_eth_ntuple_filter *nfilter,
2498                        enum rte_filter_op filter_op)
2499 {
2500         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2501         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2502         int ret;
2503
2504         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2505                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2506                 return -EINVAL;
2507         }
2508
2509         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2510                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2511                 return -EINVAL;
2512         }
2513
2514         bfilter = bnxt_get_unused_filter(bp);
2515         if (bfilter == NULL) {
2516                 PMD_DRV_LOG(ERR,
2517                         "Not enough resources for a new filter.\n");
2518                 return -ENOMEM;
2519         }
2520         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2521         if (ret < 0)
2522                 goto free_filter;
2523
2524         vnic = &bp->vnic_info[nfilter->queue];
2525         vnic0 = &bp->vnic_info[0];
2526         filter1 = STAILQ_FIRST(&vnic0->filter);
2527         if (filter1 == NULL) {
2528                 ret = -EINVAL;
2529                 goto free_filter;
2530         }
2531
2532         bfilter->dst_id = vnic->fw_vnic_id;
2533         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2534         bfilter->enables |=
2535                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2536         bfilter->ethertype = 0x800;
2537         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2538
2539         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2540
2541         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2542             bfilter->dst_id == mfilter->dst_id) {
2543                 PMD_DRV_LOG(ERR, "filter exists.\n");
2544                 ret = -EEXIST;
2545                 goto free_filter;
2546         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2547                    bfilter->dst_id != mfilter->dst_id) {
2548                 mfilter->dst_id = vnic->fw_vnic_id;
2549                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2550                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2551                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2552                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2553                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2554                 goto free_filter;
2555         }
2556         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2557                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2558                 ret = -ENOENT;
2559                 goto free_filter;
2560         }
2561
2562         if (filter_op == RTE_ETH_FILTER_ADD) {
2563                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2564                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2565                 if (ret)
2566                         goto free_filter;
2567                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2568         } else {
2569                 if (mfilter == NULL) {
2570                         /* This should not happen. But for Coverity! */
2571                         ret = -ENOENT;
2572                         goto free_filter;
2573                 }
2574                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2575
2576                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2577                 bnxt_free_filter(bp, mfilter);
2578                 mfilter->fw_l2_filter_id = -1;
2579                 bnxt_free_filter(bp, bfilter);
2580                 bfilter->fw_l2_filter_id = -1;
2581         }
2582
2583         return 0;
2584 free_filter:
2585         bfilter->fw_l2_filter_id = -1;
2586         bnxt_free_filter(bp, bfilter);
2587         return ret;
2588 }
2589
2590 static int
2591 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2592                         enum rte_filter_op filter_op,
2593                         void *arg)
2594 {
2595         struct bnxt *bp = dev->data->dev_private;
2596         int ret;
2597
2598         if (filter_op == RTE_ETH_FILTER_NOP)
2599                 return 0;
2600
2601         if (arg == NULL) {
2602                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2603                             filter_op);
2604                 return -EINVAL;
2605         }
2606
2607         switch (filter_op) {
2608         case RTE_ETH_FILTER_ADD:
2609                 ret = bnxt_cfg_ntuple_filter(bp,
2610                         (struct rte_eth_ntuple_filter *)arg,
2611                         filter_op);
2612                 break;
2613         case RTE_ETH_FILTER_DELETE:
2614                 ret = bnxt_cfg_ntuple_filter(bp,
2615                         (struct rte_eth_ntuple_filter *)arg,
2616                         filter_op);
2617                 break;
2618         default:
2619                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2620                 ret = -EINVAL;
2621                 break;
2622         }
2623         return ret;
2624 }
2625
2626 static int
2627 bnxt_parse_fdir_filter(struct bnxt *bp,
2628                        struct rte_eth_fdir_filter *fdir,
2629                        struct bnxt_filter_info *filter)
2630 {
2631         enum rte_fdir_mode fdir_mode =
2632                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2633         struct bnxt_vnic_info *vnic0, *vnic;
2634         struct bnxt_filter_info *filter1;
2635         uint32_t en = 0;
2636         int i;
2637
2638         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2639                 return -EINVAL;
2640
2641         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2642         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2643
2644         switch (fdir->input.flow_type) {
2645         case RTE_ETH_FLOW_IPV4:
2646         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2647                 /* FALLTHROUGH */
2648                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2649                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2650                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2651                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2652                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2653                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2654                 filter->ip_addr_type =
2655                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2656                 filter->src_ipaddr_mask[0] = 0xffffffff;
2657                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2658                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2659                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2660                 filter->ethertype = 0x800;
2661                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2662                 break;
2663         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2664                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2665                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2666                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2667                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2668                 filter->dst_port_mask = 0xffff;
2669                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2670                 filter->src_port_mask = 0xffff;
2671                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2672                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2673                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2674                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2675                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2676                 filter->ip_protocol = 6;
2677                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2678                 filter->ip_addr_type =
2679                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2680                 filter->src_ipaddr_mask[0] = 0xffffffff;
2681                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2682                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2683                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2684                 filter->ethertype = 0x800;
2685                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2686                 break;
2687         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2688                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2689                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2690                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2691                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2692                 filter->dst_port_mask = 0xffff;
2693                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2694                 filter->src_port_mask = 0xffff;
2695                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2696                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2697                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2698                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2699                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2700                 filter->ip_protocol = 17;
2701                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2702                 filter->ip_addr_type =
2703                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2704                 filter->src_ipaddr_mask[0] = 0xffffffff;
2705                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2706                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2707                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2708                 filter->ethertype = 0x800;
2709                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2710                 break;
2711         case RTE_ETH_FLOW_IPV6:
2712         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2713                 /* FALLTHROUGH */
2714                 filter->ip_addr_type =
2715                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2716                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2717                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2718                 rte_memcpy(filter->src_ipaddr,
2719                            fdir->input.flow.ipv6_flow.src_ip, 16);
2720                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2721                 rte_memcpy(filter->dst_ipaddr,
2722                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2723                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2724                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2725                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2726                 memset(filter->src_ipaddr_mask, 0xff, 16);
2727                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2728                 filter->ethertype = 0x86dd;
2729                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2730                 break;
2731         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2732                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2733                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2734                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2735                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2736                 filter->dst_port_mask = 0xffff;
2737                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2738                 filter->src_port_mask = 0xffff;
2739                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2740                 filter->ip_addr_type =
2741                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2742                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2743                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2744                 rte_memcpy(filter->src_ipaddr,
2745                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2746                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2747                 rte_memcpy(filter->dst_ipaddr,
2748                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2749                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2750                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2751                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2752                 memset(filter->src_ipaddr_mask, 0xff, 16);
2753                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2754                 filter->ethertype = 0x86dd;
2755                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2756                 break;
2757         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2758                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2759                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2760                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2761                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2762                 filter->dst_port_mask = 0xffff;
2763                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2764                 filter->src_port_mask = 0xffff;
2765                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2766                 filter->ip_addr_type =
2767                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2768                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2769                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2770                 rte_memcpy(filter->src_ipaddr,
2771                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2772                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2773                 rte_memcpy(filter->dst_ipaddr,
2774                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2775                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2776                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2777                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2778                 memset(filter->src_ipaddr_mask, 0xff, 16);
2779                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2780                 filter->ethertype = 0x86dd;
2781                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2782                 break;
2783         case RTE_ETH_FLOW_L2_PAYLOAD:
2784                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2785                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2786                 break;
2787         case RTE_ETH_FLOW_VXLAN:
2788                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2789                         return -EINVAL;
2790                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2791                 filter->tunnel_type =
2792                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2793                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2794                 break;
2795         case RTE_ETH_FLOW_NVGRE:
2796                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2797                         return -EINVAL;
2798                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2799                 filter->tunnel_type =
2800                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2801                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2802                 break;
2803         case RTE_ETH_FLOW_UNKNOWN:
2804         case RTE_ETH_FLOW_RAW:
2805         case RTE_ETH_FLOW_FRAG_IPV4:
2806         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2807         case RTE_ETH_FLOW_FRAG_IPV6:
2808         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2809         case RTE_ETH_FLOW_IPV6_EX:
2810         case RTE_ETH_FLOW_IPV6_TCP_EX:
2811         case RTE_ETH_FLOW_IPV6_UDP_EX:
2812         case RTE_ETH_FLOW_GENEVE:
2813                 /* FALLTHROUGH */
2814         default:
2815                 return -EINVAL;
2816         }
2817
2818         vnic0 = &bp->vnic_info[0];
2819         vnic = &bp->vnic_info[fdir->action.rx_queue];
2820         if (vnic == NULL) {
2821                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2822                 return -EINVAL;
2823         }
2824
2825
2826         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2827                 rte_memcpy(filter->dst_macaddr,
2828                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2829                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2830         }
2831
2832         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2833                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2834                 filter1 = STAILQ_FIRST(&vnic0->filter);
2835                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2836         } else {
2837                 filter->dst_id = vnic->fw_vnic_id;
2838                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2839                         if (filter->dst_macaddr[i] == 0x00)
2840                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2841                         else
2842                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2843         }
2844
2845         if (filter1 == NULL)
2846                 return -EINVAL;
2847
2848         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2849         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2850
2851         filter->enables = en;
2852
2853         return 0;
2854 }
2855
2856 static struct bnxt_filter_info *
2857 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2858                 struct bnxt_vnic_info **mvnic)
2859 {
2860         struct bnxt_filter_info *mf = NULL;
2861         int i;
2862
2863         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2864                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2865
2866                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2867                         if (mf->filter_type == nf->filter_type &&
2868                             mf->flags == nf->flags &&
2869                             mf->src_port == nf->src_port &&
2870                             mf->src_port_mask == nf->src_port_mask &&
2871                             mf->dst_port == nf->dst_port &&
2872                             mf->dst_port_mask == nf->dst_port_mask &&
2873                             mf->ip_protocol == nf->ip_protocol &&
2874                             mf->ip_addr_type == nf->ip_addr_type &&
2875                             mf->ethertype == nf->ethertype &&
2876                             mf->vni == nf->vni &&
2877                             mf->tunnel_type == nf->tunnel_type &&
2878                             mf->l2_ovlan == nf->l2_ovlan &&
2879                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2880                             mf->l2_ivlan == nf->l2_ivlan &&
2881                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2882                             !memcmp(mf->l2_addr, nf->l2_addr,
2883                                     RTE_ETHER_ADDR_LEN) &&
2884                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2885                                     RTE_ETHER_ADDR_LEN) &&
2886                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2887                                     RTE_ETHER_ADDR_LEN) &&
2888                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2889                                     RTE_ETHER_ADDR_LEN) &&
2890                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2891                                     sizeof(nf->src_ipaddr)) &&
2892                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2893                                     sizeof(nf->src_ipaddr_mask)) &&
2894                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2895                                     sizeof(nf->dst_ipaddr)) &&
2896                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2897                                     sizeof(nf->dst_ipaddr_mask))) {
2898                                 if (mvnic)
2899                                         *mvnic = vnic;
2900                                 return mf;
2901                         }
2902                 }
2903         }
2904         return NULL;
2905 }
2906
2907 static int
2908 bnxt_fdir_filter(struct rte_eth_dev *dev,
2909                  enum rte_filter_op filter_op,
2910                  void *arg)
2911 {
2912         struct bnxt *bp = dev->data->dev_private;
2913         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2914         struct bnxt_filter_info *filter, *match;
2915         struct bnxt_vnic_info *vnic, *mvnic;
2916         int ret = 0, i;
2917
2918         if (filter_op == RTE_ETH_FILTER_NOP)
2919                 return 0;
2920
2921         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2922                 return -EINVAL;
2923
2924         switch (filter_op) {
2925         case RTE_ETH_FILTER_ADD:
2926         case RTE_ETH_FILTER_DELETE:
2927                 /* FALLTHROUGH */
2928                 filter = bnxt_get_unused_filter(bp);
2929                 if (filter == NULL) {
2930                         PMD_DRV_LOG(ERR,
2931                                 "Not enough resources for a new flow.\n");
2932                         return -ENOMEM;
2933                 }
2934
2935                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2936                 if (ret != 0)
2937                         goto free_filter;
2938                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2939
2940                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2941                         vnic = &bp->vnic_info[0];
2942                 else
2943                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2944
2945                 match = bnxt_match_fdir(bp, filter, &mvnic);
2946                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2947                         if (match->dst_id == vnic->fw_vnic_id) {
2948                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2949                                 ret = -EEXIST;
2950                                 goto free_filter;
2951                         } else {
2952                                 match->dst_id = vnic->fw_vnic_id;
2953                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2954                                                                   match->dst_id,
2955                                                                   match);
2956                                 STAILQ_REMOVE(&mvnic->filter, match,
2957                                               bnxt_filter_info, next);
2958                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2959                                 PMD_DRV_LOG(ERR,
2960                                         "Filter with matching pattern exist\n");
2961                                 PMD_DRV_LOG(ERR,
2962                                         "Updated it to new destination q\n");
2963                                 goto free_filter;
2964                         }
2965                 }
2966                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2967                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2968                         ret = -ENOENT;
2969                         goto free_filter;
2970                 }
2971
2972                 if (filter_op == RTE_ETH_FILTER_ADD) {
2973                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2974                                                           filter->dst_id,
2975                                                           filter);
2976                         if (ret)
2977                                 goto free_filter;
2978                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2979                 } else {
2980                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2981                         STAILQ_REMOVE(&vnic->filter, match,
2982                                       bnxt_filter_info, next);
2983                         bnxt_free_filter(bp, match);
2984                         filter->fw_l2_filter_id = -1;
2985                         bnxt_free_filter(bp, filter);
2986                 }
2987                 break;
2988         case RTE_ETH_FILTER_FLUSH:
2989                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2990                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2991
2992                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2993                                 if (filter->filter_type ==
2994                                     HWRM_CFA_NTUPLE_FILTER) {
2995                                         ret =
2996                                         bnxt_hwrm_clear_ntuple_filter(bp,
2997                                                                       filter);
2998                                         STAILQ_REMOVE(&vnic->filter, filter,
2999                                                       bnxt_filter_info, next);
3000                                 }
3001                         }
3002                 }
3003                 return ret;
3004         case RTE_ETH_FILTER_UPDATE:
3005         case RTE_ETH_FILTER_STATS:
3006         case RTE_ETH_FILTER_INFO:
3007                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3008                 break;
3009         default:
3010                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3011                 ret = -EINVAL;
3012                 break;
3013         }
3014         return ret;
3015
3016 free_filter:
3017         filter->fw_l2_filter_id = -1;
3018         bnxt_free_filter(bp, filter);
3019         return ret;
3020 }
3021
3022 static int
3023 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3024                     enum rte_filter_type filter_type,
3025                     enum rte_filter_op filter_op, void *arg)
3026 {
3027         int ret = 0;
3028
3029         ret = is_bnxt_in_error(dev->data->dev_private);
3030         if (ret)
3031                 return ret;
3032
3033         switch (filter_type) {
3034         case RTE_ETH_FILTER_TUNNEL:
3035                 PMD_DRV_LOG(ERR,
3036                         "filter type: %d: To be implemented\n", filter_type);
3037                 break;
3038         case RTE_ETH_FILTER_FDIR:
3039                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3040                 break;
3041         case RTE_ETH_FILTER_NTUPLE:
3042                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3043                 break;
3044         case RTE_ETH_FILTER_ETHERTYPE:
3045                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3046                 break;
3047         case RTE_ETH_FILTER_GENERIC:
3048                 if (filter_op != RTE_ETH_FILTER_GET)
3049                         return -EINVAL;
3050                 *(const void **)arg = &bnxt_flow_ops;
3051                 break;
3052         default:
3053                 PMD_DRV_LOG(ERR,
3054                         "Filter type (%d) not supported", filter_type);
3055                 ret = -EINVAL;
3056                 break;
3057         }
3058         return ret;
3059 }
3060
3061 static const uint32_t *
3062 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3063 {
3064         static const uint32_t ptypes[] = {
3065                 RTE_PTYPE_L2_ETHER_VLAN,
3066                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3067                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3068                 RTE_PTYPE_L4_ICMP,
3069                 RTE_PTYPE_L4_TCP,
3070                 RTE_PTYPE_L4_UDP,
3071                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3072                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3073                 RTE_PTYPE_INNER_L4_ICMP,
3074                 RTE_PTYPE_INNER_L4_TCP,
3075                 RTE_PTYPE_INNER_L4_UDP,
3076                 RTE_PTYPE_UNKNOWN
3077         };
3078
3079         if (!dev->rx_pkt_burst)
3080                 return NULL;
3081
3082         return ptypes;
3083 }
3084
3085 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3086                          int reg_win)
3087 {
3088         uint32_t reg_base = *reg_arr & 0xfffff000;
3089         uint32_t win_off;
3090         int i;
3091
3092         for (i = 0; i < count; i++) {
3093                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3094                         return -ERANGE;
3095         }
3096         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3097         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3098         return 0;
3099 }
3100
3101 static int bnxt_map_ptp_regs(struct bnxt *bp)
3102 {
3103         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3104         uint32_t *reg_arr;
3105         int rc, i;
3106
3107         reg_arr = ptp->rx_regs;
3108         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3109         if (rc)
3110                 return rc;
3111
3112         reg_arr = ptp->tx_regs;
3113         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3114         if (rc)
3115                 return rc;
3116
3117         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3118                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3119
3120         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3121                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3122
3123         return 0;
3124 }
3125
3126 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3127 {
3128         rte_write32(0, (uint8_t *)bp->bar0 +
3129                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3130         rte_write32(0, (uint8_t *)bp->bar0 +
3131                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3132 }
3133
3134 static uint64_t bnxt_cc_read(struct bnxt *bp)
3135 {
3136         uint64_t ns;
3137
3138         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3139                               BNXT_GRCPF_REG_SYNC_TIME));
3140         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3141                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3142         return ns;
3143 }
3144
3145 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3146 {
3147         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3148         uint32_t fifo;
3149
3150         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3151                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3152         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3153                 return -EAGAIN;
3154
3155         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3156                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3157         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3158                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3159         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3160                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3161
3162         return 0;
3163 }
3164
3165 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3166 {
3167         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3168         struct bnxt_pf_info *pf = &bp->pf;
3169         uint16_t port_id;
3170         uint32_t fifo;
3171
3172         if (!ptp)
3173                 return -ENODEV;
3174
3175         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3176                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3177         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3178                 return -EAGAIN;
3179
3180         port_id = pf->port_id;
3181         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3182                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3183
3184         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3185                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3186         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3187 /*              bnxt_clr_rx_ts(bp);       TBD  */
3188                 return -EBUSY;
3189         }
3190
3191         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3192                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3193         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3194                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3195
3196         return 0;
3197 }
3198
3199 static int
3200 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3201 {
3202         uint64_t ns;
3203         struct bnxt *bp = dev->data->dev_private;
3204         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3205
3206         if (!ptp)
3207                 return 0;
3208
3209         ns = rte_timespec_to_ns(ts);
3210         /* Set the timecounters to a new value. */
3211         ptp->tc.nsec = ns;
3212
3213         return 0;
3214 }
3215
3216 static int
3217 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3218 {
3219         struct bnxt *bp = dev->data->dev_private;
3220         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3221         uint64_t ns, systime_cycles = 0;
3222         int rc = 0;
3223
3224         if (!ptp)
3225                 return 0;
3226
3227         if (BNXT_CHIP_THOR(bp))
3228                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3229                                              &systime_cycles);
3230         else
3231                 systime_cycles = bnxt_cc_read(bp);
3232
3233         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3234         *ts = rte_ns_to_timespec(ns);
3235
3236         return rc;
3237 }
3238 static int
3239 bnxt_timesync_enable(struct rte_eth_dev *dev)
3240 {
3241         struct bnxt *bp = dev->data->dev_private;
3242         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3243         uint32_t shift = 0;
3244         int rc;
3245
3246         if (!ptp)
3247                 return 0;
3248
3249         ptp->rx_filter = 1;
3250         ptp->tx_tstamp_en = 1;
3251         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3252
3253         rc = bnxt_hwrm_ptp_cfg(bp);
3254         if (rc)
3255                 return rc;
3256
3257         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3258         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3259         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3260
3261         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3262         ptp->tc.cc_shift = shift;
3263         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3264
3265         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3266         ptp->rx_tstamp_tc.cc_shift = shift;
3267         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3268
3269         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3270         ptp->tx_tstamp_tc.cc_shift = shift;
3271         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3272
3273         if (!BNXT_CHIP_THOR(bp))
3274                 bnxt_map_ptp_regs(bp);
3275
3276         return 0;
3277 }
3278
3279 static int
3280 bnxt_timesync_disable(struct rte_eth_dev *dev)
3281 {
3282         struct bnxt *bp = dev->data->dev_private;
3283         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3284
3285         if (!ptp)
3286                 return 0;
3287
3288         ptp->rx_filter = 0;
3289         ptp->tx_tstamp_en = 0;
3290         ptp->rxctl = 0;
3291
3292         bnxt_hwrm_ptp_cfg(bp);
3293
3294         if (!BNXT_CHIP_THOR(bp))
3295                 bnxt_unmap_ptp_regs(bp);
3296
3297         return 0;
3298 }
3299
3300 static int
3301 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3302                                  struct timespec *timestamp,
3303                                  uint32_t flags __rte_unused)
3304 {
3305         struct bnxt *bp = dev->data->dev_private;
3306         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3307         uint64_t rx_tstamp_cycles = 0;
3308         uint64_t ns;
3309
3310         if (!ptp)
3311                 return 0;
3312
3313         if (BNXT_CHIP_THOR(bp))
3314                 rx_tstamp_cycles = ptp->rx_timestamp;
3315         else
3316                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3317
3318         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3319         *timestamp = rte_ns_to_timespec(ns);
3320         return  0;
3321 }
3322
3323 static int
3324 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3325                                  struct timespec *timestamp)
3326 {
3327         struct bnxt *bp = dev->data->dev_private;
3328         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3329         uint64_t tx_tstamp_cycles = 0;
3330         uint64_t ns;
3331         int rc = 0;
3332
3333         if (!ptp)
3334                 return 0;
3335
3336         if (BNXT_CHIP_THOR(bp))
3337                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3338                                              &tx_tstamp_cycles);
3339         else
3340                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3341
3342         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3343         *timestamp = rte_ns_to_timespec(ns);
3344
3345         return rc;
3346 }
3347
3348 static int
3349 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3350 {
3351         struct bnxt *bp = dev->data->dev_private;
3352         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3353
3354         if (!ptp)
3355                 return 0;
3356
3357         ptp->tc.nsec += delta;
3358
3359         return 0;
3360 }
3361
3362 static int
3363 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3364 {
3365         struct bnxt *bp = dev->data->dev_private;
3366         int rc;
3367         uint32_t dir_entries;
3368         uint32_t entry_length;
3369
3370         rc = is_bnxt_in_error(bp);
3371         if (rc)
3372                 return rc;
3373
3374         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3375                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3376                 bp->pdev->addr.devid, bp->pdev->addr.function);
3377
3378         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3379         if (rc != 0)
3380                 return rc;
3381
3382         return dir_entries * entry_length;
3383 }
3384
3385 static int
3386 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3387                 struct rte_dev_eeprom_info *in_eeprom)
3388 {
3389         struct bnxt *bp = dev->data->dev_private;
3390         uint32_t index;
3391         uint32_t offset;
3392         int rc;
3393
3394         rc = is_bnxt_in_error(bp);
3395         if (rc)
3396                 return rc;
3397
3398         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3399                 "len = %d\n", bp->pdev->addr.domain,
3400                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3401                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3402
3403         if (in_eeprom->offset == 0) /* special offset value to get directory */
3404                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3405                                                 in_eeprom->data);
3406
3407         index = in_eeprom->offset >> 24;
3408         offset = in_eeprom->offset & 0xffffff;
3409
3410         if (index != 0)
3411                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3412                                            in_eeprom->length, in_eeprom->data);
3413
3414         return 0;
3415 }
3416
3417 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3418 {
3419         switch (dir_type) {
3420         case BNX_DIR_TYPE_CHIMP_PATCH:
3421         case BNX_DIR_TYPE_BOOTCODE:
3422         case BNX_DIR_TYPE_BOOTCODE_2:
3423         case BNX_DIR_TYPE_APE_FW:
3424         case BNX_DIR_TYPE_APE_PATCH:
3425         case BNX_DIR_TYPE_KONG_FW:
3426         case BNX_DIR_TYPE_KONG_PATCH:
3427         case BNX_DIR_TYPE_BONO_FW:
3428         case BNX_DIR_TYPE_BONO_PATCH:
3429                 /* FALLTHROUGH */
3430                 return true;
3431         }
3432
3433         return false;
3434 }
3435
3436 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3437 {
3438         switch (dir_type) {
3439         case BNX_DIR_TYPE_AVS:
3440         case BNX_DIR_TYPE_EXP_ROM_MBA:
3441         case BNX_DIR_TYPE_PCIE:
3442         case BNX_DIR_TYPE_TSCF_UCODE:
3443         case BNX_DIR_TYPE_EXT_PHY:
3444         case BNX_DIR_TYPE_CCM:
3445         case BNX_DIR_TYPE_ISCSI_BOOT:
3446         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3447         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3448                 /* FALLTHROUGH */
3449                 return true;
3450         }
3451
3452         return false;
3453 }
3454
3455 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3456 {
3457         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3458                 bnxt_dir_type_is_other_exec_format(dir_type);
3459 }
3460
3461 static int
3462 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3463                 struct rte_dev_eeprom_info *in_eeprom)
3464 {
3465         struct bnxt *bp = dev->data->dev_private;
3466         uint8_t index, dir_op;
3467         uint16_t type, ext, ordinal, attr;
3468         int rc;
3469
3470         rc = is_bnxt_in_error(bp);
3471         if (rc)
3472                 return rc;
3473
3474         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3475                 "len = %d\n", bp->pdev->addr.domain,
3476                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3477                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3478
3479         if (!BNXT_PF(bp)) {
3480                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3481                 return -EINVAL;
3482         }
3483
3484         type = in_eeprom->magic >> 16;
3485
3486         if (type == 0xffff) { /* special value for directory operations */
3487                 index = in_eeprom->magic & 0xff;
3488                 dir_op = in_eeprom->magic >> 8;
3489                 if (index == 0)
3490                         return -EINVAL;
3491                 switch (dir_op) {
3492                 case 0x0e: /* erase */
3493                         if (in_eeprom->offset != ~in_eeprom->magic)
3494                                 return -EINVAL;
3495                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3496                 default:
3497                         return -EINVAL;
3498                 }
3499         }
3500
3501         /* Create or re-write an NVM item: */
3502         if (bnxt_dir_type_is_executable(type) == true)
3503                 return -EOPNOTSUPP;
3504         ext = in_eeprom->magic & 0xffff;
3505         ordinal = in_eeprom->offset >> 16;
3506         attr = in_eeprom->offset & 0xffff;
3507
3508         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3509                                      in_eeprom->data, in_eeprom->length);
3510 }
3511
3512 /*
3513  * Initialization
3514  */
3515
3516 static const struct eth_dev_ops bnxt_dev_ops = {
3517         .dev_infos_get = bnxt_dev_info_get_op,
3518         .dev_close = bnxt_dev_close_op,
3519         .dev_configure = bnxt_dev_configure_op,
3520         .dev_start = bnxt_dev_start_op,
3521         .dev_stop = bnxt_dev_stop_op,
3522         .dev_set_link_up = bnxt_dev_set_link_up_op,
3523         .dev_set_link_down = bnxt_dev_set_link_down_op,
3524         .stats_get = bnxt_stats_get_op,
3525         .stats_reset = bnxt_stats_reset_op,
3526         .rx_queue_setup = bnxt_rx_queue_setup_op,
3527         .rx_queue_release = bnxt_rx_queue_release_op,
3528         .tx_queue_setup = bnxt_tx_queue_setup_op,
3529         .tx_queue_release = bnxt_tx_queue_release_op,
3530         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3531         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3532         .reta_update = bnxt_reta_update_op,
3533         .reta_query = bnxt_reta_query_op,
3534         .rss_hash_update = bnxt_rss_hash_update_op,
3535         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3536         .link_update = bnxt_link_update_op,
3537         .promiscuous_enable = bnxt_promiscuous_enable_op,
3538         .promiscuous_disable = bnxt_promiscuous_disable_op,
3539         .allmulticast_enable = bnxt_allmulticast_enable_op,
3540         .allmulticast_disable = bnxt_allmulticast_disable_op,
3541         .mac_addr_add = bnxt_mac_addr_add_op,
3542         .mac_addr_remove = bnxt_mac_addr_remove_op,
3543         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3544         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3545         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3546         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3547         .vlan_filter_set = bnxt_vlan_filter_set_op,
3548         .vlan_offload_set = bnxt_vlan_offload_set_op,
3549         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3550         .mtu_set = bnxt_mtu_set_op,
3551         .mac_addr_set = bnxt_set_default_mac_addr_op,
3552         .xstats_get = bnxt_dev_xstats_get_op,
3553         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3554         .xstats_reset = bnxt_dev_xstats_reset_op,
3555         .fw_version_get = bnxt_fw_version_get,
3556         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3557         .rxq_info_get = bnxt_rxq_info_get_op,
3558         .txq_info_get = bnxt_txq_info_get_op,
3559         .dev_led_on = bnxt_dev_led_on_op,
3560         .dev_led_off = bnxt_dev_led_off_op,
3561         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3562         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3563         .rx_queue_count = bnxt_rx_queue_count_op,
3564         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3565         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3566         .rx_queue_start = bnxt_rx_queue_start,
3567         .rx_queue_stop = bnxt_rx_queue_stop,
3568         .tx_queue_start = bnxt_tx_queue_start,
3569         .tx_queue_stop = bnxt_tx_queue_stop,
3570         .filter_ctrl = bnxt_filter_ctrl_op,
3571         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3572         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3573         .get_eeprom           = bnxt_get_eeprom_op,
3574         .set_eeprom           = bnxt_set_eeprom_op,
3575         .timesync_enable      = bnxt_timesync_enable,
3576         .timesync_disable     = bnxt_timesync_disable,
3577         .timesync_read_time   = bnxt_timesync_read_time,
3578         .timesync_write_time   = bnxt_timesync_write_time,
3579         .timesync_adjust_time = bnxt_timesync_adjust_time,
3580         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3581         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3582 };
3583
3584 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3585 {
3586         uint32_t offset;
3587
3588         /* Only pre-map the reset GRC registers using window 3 */
3589         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3590                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3591
3592         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3593
3594         return offset;
3595 }
3596
3597 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3598 {
3599         struct bnxt_error_recovery_info *info = bp->recovery_info;
3600         uint32_t reg_base = 0xffffffff;
3601         int i;
3602
3603         /* Only pre-map the monitoring GRC registers using window 2 */
3604         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3605                 uint32_t reg = info->status_regs[i];
3606
3607                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3608                         continue;
3609
3610                 if (reg_base == 0xffffffff)
3611                         reg_base = reg & 0xfffff000;
3612                 if ((reg & 0xfffff000) != reg_base)
3613                         return -ERANGE;
3614
3615                 /* Use mask 0xffc as the Lower 2 bits indicates
3616                  * address space location
3617                  */
3618                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3619                                                 (reg & 0xffc);
3620         }
3621
3622         if (reg_base == 0xffffffff)
3623                 return 0;
3624
3625         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3626                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3627
3628         return 0;
3629 }
3630
3631 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3632 {
3633         struct bnxt_error_recovery_info *info = bp->recovery_info;
3634         uint32_t delay = info->delay_after_reset[index];
3635         uint32_t val = info->reset_reg_val[index];
3636         uint32_t reg = info->reset_reg[index];
3637         uint32_t type, offset;
3638
3639         type = BNXT_FW_STATUS_REG_TYPE(reg);
3640         offset = BNXT_FW_STATUS_REG_OFF(reg);
3641
3642         switch (type) {
3643         case BNXT_FW_STATUS_REG_TYPE_CFG:
3644                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3645                 break;
3646         case BNXT_FW_STATUS_REG_TYPE_GRC:
3647                 offset = bnxt_map_reset_regs(bp, offset);
3648                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3649                 break;
3650         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3651                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3652                 break;
3653         }
3654         /* wait on a specific interval of time until core reset is complete */
3655         if (delay)
3656                 rte_delay_ms(delay);
3657 }
3658
3659 static void bnxt_dev_cleanup(struct bnxt *bp)
3660 {
3661         bnxt_set_hwrm_link_config(bp, false);
3662         bp->link_info.link_up = 0;
3663         if (bp->dev_stopped == 0)
3664                 bnxt_dev_stop_op(bp->eth_dev);
3665
3666         bnxt_uninit_resources(bp, true);
3667 }
3668
3669 static int bnxt_restore_filters(struct bnxt *bp)
3670 {
3671         struct rte_eth_dev *dev = bp->eth_dev;
3672         int ret = 0;
3673
3674         if (dev->data->all_multicast)
3675                 ret = bnxt_allmulticast_enable_op(dev);
3676         if (dev->data->promiscuous)
3677                 ret = bnxt_promiscuous_enable_op(dev);
3678
3679         /* TODO restore other filters as well */
3680         return ret;
3681 }
3682
3683 static void bnxt_dev_recover(void *arg)
3684 {
3685         struct bnxt *bp = arg;
3686         int timeout = bp->fw_reset_max_msecs;
3687         int rc = 0;
3688
3689         /* Clear Error flag so that device re-init should happen */
3690         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3691
3692         do {
3693                 rc = bnxt_hwrm_ver_get(bp);
3694                 if (rc == 0)
3695                         break;
3696                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3697                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3698         } while (rc && timeout);
3699
3700         if (rc) {
3701                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3702                 goto err;
3703         }
3704
3705         rc = bnxt_init_resources(bp, true);
3706         if (rc) {
3707                 PMD_DRV_LOG(ERR,
3708                             "Failed to initialize resources after reset\n");
3709                 goto err;
3710         }
3711         /* clear reset flag as the device is initialized now */
3712         bp->flags &= ~BNXT_FLAG_FW_RESET;
3713
3714         rc = bnxt_dev_start_op(bp->eth_dev);
3715         if (rc) {
3716                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3717                 goto err;
3718         }
3719
3720         rc = bnxt_restore_filters(bp);
3721         if (rc)
3722                 goto err;
3723
3724         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3725         return;
3726 err:
3727         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3728         bnxt_uninit_resources(bp, false);
3729         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3730 }
3731
3732 void bnxt_dev_reset_and_resume(void *arg)
3733 {
3734         struct bnxt *bp = arg;
3735         int rc;
3736
3737         bnxt_dev_cleanup(bp);
3738
3739         bnxt_wait_for_device_shutdown(bp);
3740
3741         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3742                                bnxt_dev_recover, (void *)bp);
3743         if (rc)
3744                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3745 }
3746
3747 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3748 {
3749         struct bnxt_error_recovery_info *info = bp->recovery_info;
3750         uint32_t reg = info->status_regs[index];
3751         uint32_t type, offset, val = 0;
3752
3753         type = BNXT_FW_STATUS_REG_TYPE(reg);
3754         offset = BNXT_FW_STATUS_REG_OFF(reg);
3755
3756         switch (type) {
3757         case BNXT_FW_STATUS_REG_TYPE_CFG:
3758                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3759                 break;
3760         case BNXT_FW_STATUS_REG_TYPE_GRC:
3761                 offset = info->mapped_status_regs[index];
3762                 /* FALLTHROUGH */
3763         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3764                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3765                                        offset));
3766                 break;
3767         }
3768
3769         return val;
3770 }
3771
3772 static int bnxt_fw_reset_all(struct bnxt *bp)
3773 {
3774         struct bnxt_error_recovery_info *info = bp->recovery_info;
3775         uint32_t i;
3776         int rc = 0;
3777
3778         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3779                 /* Reset through master function driver */
3780                 for (i = 0; i < info->reg_array_cnt; i++)
3781                         bnxt_write_fw_reset_reg(bp, i);
3782                 /* Wait for time specified by FW after triggering reset */
3783                 rte_delay_ms(info->master_func_wait_period_after_reset);
3784         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3785                 /* Reset with the help of Kong processor */
3786                 rc = bnxt_hwrm_fw_reset(bp);
3787                 if (rc)
3788                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3789         }
3790
3791         return rc;
3792 }
3793
3794 static void bnxt_fw_reset_cb(void *arg)
3795 {
3796         struct bnxt *bp = arg;
3797         struct bnxt_error_recovery_info *info = bp->recovery_info;
3798         int rc = 0;
3799
3800         /* Only Master function can do FW reset */
3801         if (bnxt_is_master_func(bp) &&
3802             bnxt_is_recovery_enabled(bp)) {
3803                 rc = bnxt_fw_reset_all(bp);
3804                 if (rc) {
3805                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3806                         return;
3807                 }
3808         }
3809
3810         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3811          * EXCEPTION_FATAL_ASYNC event to all the functions
3812          * (including MASTER FUNC). After receiving this Async, all the active
3813          * drivers should treat this case as FW initiated recovery
3814          */
3815         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3816                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3817                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3818
3819                 /* To recover from error */
3820                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3821                                   (void *)bp);
3822         }
3823 }
3824
3825 /* Driver should poll FW heartbeat, reset_counter with the frequency
3826  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3827  * When the driver detects heartbeat stop or change in reset_counter,
3828  * it has to trigger a reset to recover from the error condition.
3829  * A “master PF” is the function who will have the privilege to
3830  * initiate the chimp reset. The master PF will be elected by the
3831  * firmware and will be notified through async message.
3832  */
3833 static void bnxt_check_fw_health(void *arg)
3834 {
3835         struct bnxt *bp = arg;
3836         struct bnxt_error_recovery_info *info = bp->recovery_info;
3837         uint32_t val = 0, wait_msec;
3838
3839         if (!info || !bnxt_is_recovery_enabled(bp) ||
3840             is_bnxt_in_error(bp))
3841                 return;
3842
3843         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3844         if (val == info->last_heart_beat)
3845                 goto reset;
3846
3847         info->last_heart_beat = val;
3848
3849         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3850         if (val != info->last_reset_counter)
3851                 goto reset;
3852
3853         info->last_reset_counter = val;
3854
3855         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3856                           bnxt_check_fw_health, (void *)bp);
3857
3858         return;
3859 reset:
3860         /* Stop DMA to/from device */
3861         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3862         bp->flags |= BNXT_FLAG_FW_RESET;
3863
3864         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3865
3866         if (bnxt_is_master_func(bp))
3867                 wait_msec = info->master_func_wait_period;
3868         else
3869                 wait_msec = info->normal_func_wait_period;
3870
3871         rte_eal_alarm_set(US_PER_MS * wait_msec,
3872                           bnxt_fw_reset_cb, (void *)bp);
3873 }
3874
3875 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3876 {
3877         uint32_t polling_freq;
3878
3879         if (!bnxt_is_recovery_enabled(bp))
3880                 return;
3881
3882         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3883                 return;
3884
3885         polling_freq = bp->recovery_info->driver_polling_freq;
3886
3887         rte_eal_alarm_set(US_PER_MS * polling_freq,
3888                           bnxt_check_fw_health, (void *)bp);
3889         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3890 }
3891
3892 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3893 {
3894         if (!bnxt_is_recovery_enabled(bp))
3895                 return;
3896
3897         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3898         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3899 }
3900
3901 static bool bnxt_vf_pciid(uint16_t id)
3902 {
3903         if (id == BROADCOM_DEV_ID_57304_VF ||
3904             id == BROADCOM_DEV_ID_57406_VF ||
3905             id == BROADCOM_DEV_ID_5731X_VF ||
3906             id == BROADCOM_DEV_ID_5741X_VF ||
3907             id == BROADCOM_DEV_ID_57414_VF ||
3908             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3909             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3910             id == BROADCOM_DEV_ID_58802_VF ||
3911             id == BROADCOM_DEV_ID_57500_VF1 ||
3912             id == BROADCOM_DEV_ID_57500_VF2)
3913                 return true;
3914         return false;
3915 }
3916
3917 bool bnxt_stratus_device(struct bnxt *bp)
3918 {
3919         uint16_t id = bp->pdev->id.device_id;
3920
3921         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3922             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3923             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3924                 return true;
3925         return false;
3926 }
3927
3928 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3929 {
3930         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3931         struct bnxt *bp = eth_dev->data->dev_private;
3932
3933         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3934         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3935         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3936         if (!bp->bar0 || !bp->doorbell_base) {
3937                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3938                 return -ENODEV;
3939         }
3940
3941         bp->eth_dev = eth_dev;
3942         bp->pdev = pci_dev;
3943
3944         return 0;
3945 }
3946
3947 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3948                                   struct bnxt_ctx_pg_info *ctx_pg,
3949                                   uint32_t mem_size,
3950                                   const char *suffix,
3951                                   uint16_t idx)
3952 {
3953         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3954         const struct rte_memzone *mz = NULL;
3955         char mz_name[RTE_MEMZONE_NAMESIZE];
3956         rte_iova_t mz_phys_addr;
3957         uint64_t valid_bits = 0;
3958         uint32_t sz;
3959         int i;
3960
3961         if (!mem_size)
3962                 return 0;
3963
3964         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3965                          BNXT_PAGE_SIZE;
3966         rmem->page_size = BNXT_PAGE_SIZE;
3967         rmem->pg_arr = ctx_pg->ctx_pg_arr;
3968         rmem->dma_arr = ctx_pg->ctx_dma_arr;
3969         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3970
3971         valid_bits = PTU_PTE_VALID;
3972
3973         if (rmem->nr_pages > 1) {
3974                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3975                          "bnxt_ctx_pg_tbl%s_%x_%d",
3976                          suffix, idx, bp->eth_dev->data->port_id);
3977                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3978                 mz = rte_memzone_lookup(mz_name);
3979                 if (!mz) {
3980                         mz = rte_memzone_reserve_aligned(mz_name,
3981                                                 rmem->nr_pages * 8,
3982                                                 SOCKET_ID_ANY,
3983                                                 RTE_MEMZONE_2MB |
3984                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
3985                                                 RTE_MEMZONE_IOVA_CONTIG,
3986                                                 BNXT_PAGE_SIZE);
3987                         if (mz == NULL)
3988                                 return -ENOMEM;
3989                 }
3990
3991                 memset(mz->addr, 0, mz->len);
3992                 mz_phys_addr = mz->iova;
3993                 if ((unsigned long)mz->addr == mz_phys_addr) {
3994                         PMD_DRV_LOG(DEBUG,
3995                                     "physical address same as virtual\n");
3996                         PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
3997                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3998                         if (mz_phys_addr == RTE_BAD_IOVA) {
3999                                 PMD_DRV_LOG(ERR,
4000                                         "unable to map addr to phys memory\n");
4001                                 return -ENOMEM;
4002                         }
4003                 }
4004                 rte_mem_lock_page(((char *)mz->addr));
4005
4006                 rmem->pg_tbl = mz->addr;
4007                 rmem->pg_tbl_map = mz_phys_addr;
4008                 rmem->pg_tbl_mz = mz;
4009         }
4010
4011         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4012                  suffix, idx, bp->eth_dev->data->port_id);
4013         mz = rte_memzone_lookup(mz_name);
4014         if (!mz) {
4015                 mz = rte_memzone_reserve_aligned(mz_name,
4016                                                  mem_size,
4017                                                  SOCKET_ID_ANY,
4018                                                  RTE_MEMZONE_1GB |
4019                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4020                                                  RTE_MEMZONE_IOVA_CONTIG,
4021                                                  BNXT_PAGE_SIZE);
4022                 if (mz == NULL)
4023                         return -ENOMEM;
4024         }
4025
4026         memset(mz->addr, 0, mz->len);
4027         mz_phys_addr = mz->iova;
4028         if ((unsigned long)mz->addr == mz_phys_addr) {
4029                 PMD_DRV_LOG(DEBUG,
4030                             "Memzone physical address same as virtual.\n");
4031                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4032                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4033                         rte_mem_lock_page(((char *)mz->addr) + sz);
4034                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4035                 if (mz_phys_addr == RTE_BAD_IOVA) {
4036                         PMD_DRV_LOG(ERR,
4037                                     "unable to map addr to phys memory\n");
4038                         return -ENOMEM;
4039                 }
4040         }
4041
4042         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4043                 rte_mem_lock_page(((char *)mz->addr) + sz);
4044                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4045                 rmem->dma_arr[i] = mz_phys_addr + sz;
4046
4047                 if (rmem->nr_pages > 1) {
4048                         if (i == rmem->nr_pages - 2 &&
4049                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4050                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4051                         else if (i == rmem->nr_pages - 1 &&
4052                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4053                                 valid_bits |= PTU_PTE_LAST;
4054
4055                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4056                                                            valid_bits);
4057                 }
4058         }
4059
4060         rmem->mz = mz;
4061         if (rmem->vmem_size)
4062                 rmem->vmem = (void **)mz->addr;
4063         rmem->dma_arr[0] = mz_phys_addr;
4064         return 0;
4065 }
4066
4067 static void bnxt_free_ctx_mem(struct bnxt *bp)
4068 {
4069         int i;
4070
4071         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4072                 return;
4073
4074         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4075         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4076         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4077         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4078         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4079         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4080         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4081         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4082         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4083         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4084         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4085
4086         for (i = 0; i < BNXT_MAX_Q; i++) {
4087                 if (bp->ctx->tqm_mem[i])
4088                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4089         }
4090
4091         rte_free(bp->ctx);
4092         bp->ctx = NULL;
4093 }
4094
4095 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4096
4097 #define min_t(type, x, y) ({                    \
4098         type __min1 = (x);                      \
4099         type __min2 = (y);                      \
4100         __min1 < __min2 ? __min1 : __min2; })
4101
4102 #define max_t(type, x, y) ({                    \
4103         type __max1 = (x);                      \
4104         type __max2 = (y);                      \
4105         __max1 > __max2 ? __max1 : __max2; })
4106
4107 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4108
4109 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4110 {
4111         struct bnxt_ctx_pg_info *ctx_pg;
4112         struct bnxt_ctx_mem_info *ctx;
4113         uint32_t mem_size, ena, entries;
4114         int i, rc;
4115
4116         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4117         if (rc) {
4118                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4119                 return rc;
4120         }
4121         ctx = bp->ctx;
4122         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4123                 return 0;
4124
4125         ctx_pg = &ctx->qp_mem;
4126         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4127         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4128         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4129         if (rc)
4130                 return rc;
4131
4132         ctx_pg = &ctx->srq_mem;
4133         ctx_pg->entries = ctx->srq_max_l2_entries;
4134         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4135         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4136         if (rc)
4137                 return rc;
4138
4139         ctx_pg = &ctx->cq_mem;
4140         ctx_pg->entries = ctx->cq_max_l2_entries;
4141         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4142         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4143         if (rc)
4144                 return rc;
4145
4146         ctx_pg = &ctx->vnic_mem;
4147         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4148                 ctx->vnic_max_ring_table_entries;
4149         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4150         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4151         if (rc)
4152                 return rc;
4153
4154         ctx_pg = &ctx->stat_mem;
4155         ctx_pg->entries = ctx->stat_max_entries;
4156         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4157         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4158         if (rc)
4159                 return rc;
4160
4161         entries = ctx->qp_max_l2_entries;
4162         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4163         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4164                           ctx->tqm_max_entries_per_ring);
4165         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4166                 ctx_pg = ctx->tqm_mem[i];
4167                 /* use min tqm entries for now. */
4168                 ctx_pg->entries = entries;
4169                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4170                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4171                 if (rc)
4172                         return rc;
4173                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4174         }
4175
4176         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4177         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4178         if (rc)
4179                 PMD_DRV_LOG(ERR,
4180                             "Failed to configure context mem: rc = %d\n", rc);
4181         else
4182                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4183
4184         return rc;
4185 }
4186
4187 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4188 {
4189         struct rte_pci_device *pci_dev = bp->pdev;
4190         char mz_name[RTE_MEMZONE_NAMESIZE];
4191         const struct rte_memzone *mz = NULL;
4192         uint32_t total_alloc_len;
4193         rte_iova_t mz_phys_addr;
4194
4195         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4196                 return 0;
4197
4198         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4199                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4200                  pci_dev->addr.bus, pci_dev->addr.devid,
4201                  pci_dev->addr.function, "rx_port_stats");
4202         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4203         mz = rte_memzone_lookup(mz_name);
4204         total_alloc_len =
4205                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4206                                        sizeof(struct rx_port_stats_ext) + 512);
4207         if (!mz) {
4208                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4209                                          SOCKET_ID_ANY,
4210                                          RTE_MEMZONE_2MB |
4211                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4212                                          RTE_MEMZONE_IOVA_CONTIG);
4213                 if (mz == NULL)
4214                         return -ENOMEM;
4215         }
4216         memset(mz->addr, 0, mz->len);
4217         mz_phys_addr = mz->iova;
4218         if ((unsigned long)mz->addr == mz_phys_addr) {
4219                 PMD_DRV_LOG(DEBUG,
4220                             "Memzone physical address same as virtual.\n");
4221                 PMD_DRV_LOG(DEBUG,
4222                             "Using rte_mem_virt2iova()\n");
4223                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4224                 if (mz_phys_addr == RTE_BAD_IOVA) {
4225                         PMD_DRV_LOG(ERR,
4226                                     "Can't map address to physical memory\n");
4227                         return -ENOMEM;
4228                 }
4229         }
4230
4231         bp->rx_mem_zone = (const void *)mz;
4232         bp->hw_rx_port_stats = mz->addr;
4233         bp->hw_rx_port_stats_map = mz_phys_addr;
4234
4235         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4236                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4237                  pci_dev->addr.bus, pci_dev->addr.devid,
4238                  pci_dev->addr.function, "tx_port_stats");
4239         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4240         mz = rte_memzone_lookup(mz_name);
4241         total_alloc_len =
4242                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4243                                        sizeof(struct tx_port_stats_ext) + 512);
4244         if (!mz) {
4245                 mz = rte_memzone_reserve(mz_name,
4246                                          total_alloc_len,
4247                                          SOCKET_ID_ANY,
4248                                          RTE_MEMZONE_2MB |
4249                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4250                                          RTE_MEMZONE_IOVA_CONTIG);
4251                 if (mz == NULL)
4252                         return -ENOMEM;
4253         }
4254         memset(mz->addr, 0, mz->len);
4255         mz_phys_addr = mz->iova;
4256         if ((unsigned long)mz->addr == mz_phys_addr) {
4257                 PMD_DRV_LOG(DEBUG,
4258                             "Memzone physical address same as virtual\n");
4259                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4260                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4261                 if (mz_phys_addr == RTE_BAD_IOVA) {
4262                         PMD_DRV_LOG(ERR,
4263                                     "Can't map address to physical memory\n");
4264                         return -ENOMEM;
4265                 }
4266         }
4267
4268         bp->tx_mem_zone = (const void *)mz;
4269         bp->hw_tx_port_stats = mz->addr;
4270         bp->hw_tx_port_stats_map = mz_phys_addr;
4271         bp->flags |= BNXT_FLAG_PORT_STATS;
4272
4273         /* Display extended statistics if FW supports it */
4274         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4275             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4276             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4277                 return 0;
4278
4279         bp->hw_rx_port_stats_ext = (void *)
4280                 ((uint8_t *)bp->hw_rx_port_stats +
4281                  sizeof(struct rx_port_stats));
4282         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4283                 sizeof(struct rx_port_stats);
4284         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4285
4286         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4287             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4288                 bp->hw_tx_port_stats_ext = (void *)
4289                         ((uint8_t *)bp->hw_tx_port_stats +
4290                          sizeof(struct tx_port_stats));
4291                 bp->hw_tx_port_stats_ext_map =
4292                         bp->hw_tx_port_stats_map +
4293                         sizeof(struct tx_port_stats);
4294                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4295         }
4296
4297         return 0;
4298 }
4299
4300 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4301 {
4302         struct bnxt *bp = eth_dev->data->dev_private;
4303         int rc = 0;
4304
4305         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4306                                                RTE_ETHER_ADDR_LEN *
4307                                                bp->max_l2_ctx,
4308                                                0);
4309         if (eth_dev->data->mac_addrs == NULL) {
4310                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4311                 return -ENOMEM;
4312         }
4313
4314         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4315                 if (BNXT_PF(bp))
4316                         return -EINVAL;
4317
4318                 /* Generate a random MAC address, if none was assigned by PF */
4319                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4320                 bnxt_eth_hw_addr_random(bp->mac_addr);
4321                 PMD_DRV_LOG(INFO,
4322                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4323                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4324                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4325
4326                 rc = bnxt_hwrm_set_mac(bp);
4327                 if (!rc)
4328                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4329                                RTE_ETHER_ADDR_LEN);
4330                 return rc;
4331         }
4332
4333         /* Copy the permanent MAC from the FUNC_QCAPS response */
4334         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4335         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4336
4337         return rc;
4338 }
4339
4340 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4341 {
4342         int rc = 0;
4343
4344         /* MAC is already configured in FW */
4345         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4346                 return 0;
4347
4348         /* Restore the old MAC configured */
4349         rc = bnxt_hwrm_set_mac(bp);
4350         if (rc)
4351                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4352
4353         return rc;
4354 }
4355
4356 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4357 {
4358         if (!BNXT_PF(bp))
4359                 return;
4360
4361 #define ALLOW_FUNC(x)   \
4362         { \
4363                 uint32_t arg = (x); \
4364                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4365                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4366         }
4367
4368         /* Forward all requests if firmware is new enough */
4369         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4370              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4371             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4372                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4373         } else {
4374                 PMD_DRV_LOG(WARNING,
4375                             "Firmware too old for VF mailbox functionality\n");
4376                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4377         }
4378
4379         /*
4380          * The following are used for driver cleanup. If we disallow these,
4381          * VF drivers can't clean up cleanly.
4382          */
4383         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4384         ALLOW_FUNC(HWRM_VNIC_FREE);
4385         ALLOW_FUNC(HWRM_RING_FREE);
4386         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4387         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4388         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4389         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4390         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4391         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4392 }
4393
4394 static int bnxt_init_fw(struct bnxt *bp)
4395 {
4396         uint16_t mtu;
4397         int rc = 0;
4398
4399         rc = bnxt_hwrm_ver_get(bp);
4400         if (rc)
4401                 return rc;
4402
4403         rc = bnxt_hwrm_func_reset(bp);
4404         if (rc)
4405                 return -EIO;
4406
4407         rc = bnxt_hwrm_queue_qportcfg(bp);
4408         if (rc)
4409                 return rc;
4410
4411         /* Get the MAX capabilities for this function */
4412         rc = bnxt_hwrm_func_qcaps(bp);
4413         if (rc)
4414                 return rc;
4415
4416         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4417         if (rc)
4418                 return rc;
4419
4420         /* Get the adapter error recovery support info */
4421         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4422         if (rc)
4423                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4424
4425         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4426             mtu != bp->eth_dev->data->mtu)
4427                 bp->eth_dev->data->mtu = mtu;
4428
4429         bnxt_hwrm_port_led_qcaps(bp);
4430
4431         return 0;
4432 }
4433
4434 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4435 {
4436         int rc;
4437
4438         rc = bnxt_init_fw(bp);
4439         if (rc)
4440                 return rc;
4441
4442         if (!reconfig_dev) {
4443                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4444                 if (rc)
4445                         return rc;
4446         } else {
4447                 rc = bnxt_restore_dflt_mac(bp);
4448                 if (rc)
4449                         return rc;
4450         }
4451
4452         bnxt_config_vf_req_fwd(bp);
4453
4454         rc = bnxt_hwrm_func_driver_register(bp);
4455         if (rc) {
4456                 PMD_DRV_LOG(ERR, "Failed to register driver");
4457                 return -EBUSY;
4458         }
4459
4460         if (BNXT_PF(bp)) {
4461                 if (bp->pdev->max_vfs) {
4462                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4463                         if (rc) {
4464                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4465                                 return rc;
4466                         }
4467                 } else {
4468                         rc = bnxt_hwrm_allocate_pf_only(bp);
4469                         if (rc) {
4470                                 PMD_DRV_LOG(ERR,
4471                                             "Failed to allocate PF resources");
4472                                 return rc;
4473                         }
4474                 }
4475         }
4476
4477         rc = bnxt_alloc_mem(bp, reconfig_dev);
4478         if (rc)
4479                 return rc;
4480
4481         rc = bnxt_setup_int(bp);
4482         if (rc)
4483                 return rc;
4484
4485         bnxt_init_nic(bp);
4486
4487         rc = bnxt_request_int(bp);
4488         if (rc)
4489                 return rc;
4490
4491         return 0;
4492 }
4493
4494 static int
4495 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4496 {
4497         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4498         static int version_printed;
4499         struct bnxt *bp;
4500         int rc;
4501
4502         if (version_printed++ == 0)
4503                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4504
4505         rte_eth_copy_pci_info(eth_dev, pci_dev);
4506
4507         bp = eth_dev->data->dev_private;
4508
4509         bp->dev_stopped = 1;
4510
4511         eth_dev->dev_ops = &bnxt_dev_ops;
4512         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4513         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4514
4515         /*
4516          * For secondary processes, we don't initialise any further
4517          * as primary has already done this work.
4518          */
4519         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4520                 return 0;
4521
4522         if (bnxt_vf_pciid(pci_dev->id.device_id))
4523                 bp->flags |= BNXT_FLAG_VF;
4524
4525         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4526             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4527             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4528             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4529             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4530                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4531
4532         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4533             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4534             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4535             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4536                 bp->flags |= BNXT_FLAG_STINGRAY;
4537
4538         rc = bnxt_init_board(eth_dev);
4539         if (rc) {
4540                 PMD_DRV_LOG(ERR,
4541                             "Failed to initialize board rc: %x\n", rc);
4542                 return rc;
4543         }
4544
4545         rc = bnxt_alloc_hwrm_resources(bp);
4546         if (rc) {
4547                 PMD_DRV_LOG(ERR,
4548                             "Failed to allocate hwrm resource rc: %x\n", rc);
4549                 goto error_free;
4550         }
4551         rc = bnxt_init_resources(bp, false);
4552         if (rc)
4553                 goto error_free;
4554
4555         rc = bnxt_alloc_stats_mem(bp);
4556         if (rc)
4557                 goto error_free;
4558
4559         PMD_DRV_LOG(INFO,
4560                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4561                     pci_dev->mem_resource[0].phys_addr,
4562                     pci_dev->mem_resource[0].addr);
4563
4564         return 0;
4565
4566 error_free:
4567         bnxt_dev_uninit(eth_dev);
4568         return rc;
4569 }
4570
4571 static int
4572 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4573 {
4574         int rc;
4575
4576         bnxt_disable_int(bp);
4577         bnxt_free_int(bp);
4578         bnxt_free_mem(bp, reconfig_dev);
4579         bnxt_hwrm_func_buf_unrgtr(bp);
4580         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4581         bp->flags &= ~BNXT_FLAG_REGISTERED;
4582         bnxt_free_ctx_mem(bp);
4583         if (!reconfig_dev) {
4584                 bnxt_free_hwrm_resources(bp);
4585
4586                 if (bp->recovery_info != NULL) {
4587                         rte_free(bp->recovery_info);
4588                         bp->recovery_info = NULL;
4589                 }
4590         }
4591
4592         rte_free(bp->ptp_cfg);
4593         bp->ptp_cfg = NULL;
4594         return rc;
4595 }
4596
4597 static int
4598 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4599 {
4600         struct bnxt *bp = eth_dev->data->dev_private;
4601         int rc;
4602
4603         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4604                 return -EPERM;
4605
4606         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4607
4608         rc = bnxt_uninit_resources(bp, false);
4609
4610         if (bp->grp_info != NULL) {
4611                 rte_free(bp->grp_info);
4612                 bp->grp_info = NULL;
4613         }
4614
4615         if (bp->tx_mem_zone) {
4616                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4617                 bp->tx_mem_zone = NULL;
4618         }
4619
4620         if (bp->rx_mem_zone) {
4621                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4622                 bp->rx_mem_zone = NULL;
4623         }
4624
4625         if (bp->dev_stopped == 0)
4626                 bnxt_dev_close_op(eth_dev);
4627         if (bp->pf.vf_info)
4628                 rte_free(bp->pf.vf_info);
4629         eth_dev->dev_ops = NULL;
4630         eth_dev->rx_pkt_burst = NULL;
4631         eth_dev->tx_pkt_burst = NULL;
4632
4633         return rc;
4634 }
4635
4636 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4637         struct rte_pci_device *pci_dev)
4638 {
4639         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4640                 bnxt_dev_init);
4641 }
4642
4643 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4644 {
4645         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4646                 return rte_eth_dev_pci_generic_remove(pci_dev,
4647                                 bnxt_dev_uninit);
4648         else
4649                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4650 }
4651
4652 static struct rte_pci_driver bnxt_rte_pmd = {
4653         .id_table = bnxt_pci_id_map,
4654         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4655         .probe = bnxt_pci_probe,
4656         .remove = bnxt_pci_remove,
4657 };
4658
4659 static bool
4660 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4661 {
4662         if (strcmp(dev->device->driver->name, drv->driver.name))
4663                 return false;
4664
4665         return true;
4666 }
4667
4668 bool is_bnxt_supported(struct rte_eth_dev *dev)
4669 {
4670         return is_device_supported(dev, &bnxt_rte_pmd);
4671 }
4672
4673 RTE_INIT(bnxt_init_log)
4674 {
4675         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4676         if (bnxt_logtype_driver >= 0)
4677                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4678 }
4679
4680 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4681 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4682 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");