drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29
  30 #define DRV_MODULE_NAME         "bnxt"
  31 static const char bnxt_version[] =
  32         "Broadcom NetXtreme driver " DRV_MODULE_NAME "\n";
  33 int bnxt_logtype_driver;
  34
  35 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  36
  37 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  39 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  40 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  41 #define BROADCOM_DEV_ID_57301 0x16c8
  42 #define BROADCOM_DEV_ID_57302 0x16c9
  43 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  44 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  45 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  46 #define BROADCOM_DEV_ID_NS2 0x16cd
  47 #define BROADCOM_DEV_ID_57311 0x16ce
  48 #define BROADCOM_DEV_ID_57312 0x16cf
  49 #define BROADCOM_DEV_ID_57402 0x16d0
  50 #define BROADCOM_DEV_ID_57404 0x16d1
  51 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  52 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  53 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  54 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  55 #define BROADCOM_DEV_ID_57412 0x16d6
  56 #define BROADCOM_DEV_ID_57414 0x16d7
  57 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  58 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  59 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  60 #define BROADCOM_DEV_ID_57412_MF 0x16de
  61 #define BROADCOM_DEV_ID_57314 0x16df
  62 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  63 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  64 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  65 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  66 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  67 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  68 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  69 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  70 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  71 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  72 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  73 #define BROADCOM_DEV_ID_58802 0xd802
  74 #define BROADCOM_DEV_ID_58804 0xd804
  75 #define BROADCOM_DEV_ID_58808 0x16f0
  76 #define BROADCOM_DEV_ID_58802_VF 0xd800
  77
  78 static const struct rte_pci_id bnxt_pci_id_map[] = {
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  80                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  82                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 121         { .vendor_id = 0, /* sentinel */ },
 122 };
 123
 124 #define BNXT_ETH_RSS_SUPPORT (  \
 125         ETH_RSS_IPV4 |          \
 126         ETH_RSS_NONFRAG_IPV4_TCP |      \
 127         ETH_RSS_NONFRAG_IPV4_UDP |      \
 128         ETH_RSS_IPV6 |          \
 129         ETH_RSS_NONFRAG_IPV6_TCP |      \
 130         ETH_RSS_NONFRAG_IPV6_UDP)
 131
 132 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 133                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 134                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 135                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 136                                      DEV_TX_OFFLOAD_TCP_TSO | \
 137                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 138                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 139                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 140                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 141                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 142                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 143
 144 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 145                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 146                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 147                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 148                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 149                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 150                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 151                                      DEV_RX_OFFLOAD_CRC_STRIP | \
 152                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 153                                      DEV_RX_OFFLOAD_TCP_LRO)
 154
 155 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 156 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 157 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 158 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 159
 160 /***********************/
 161
 162 /*
 163  * High level utility functions
 164  */
 165
 166 static void bnxt_free_mem(struct bnxt *bp)
 167 {
 168         bnxt_free_filter_mem(bp);
 169         bnxt_free_vnic_attributes(bp);
 170         bnxt_free_vnic_mem(bp);
 171
 172         bnxt_free_stats(bp);
 173         bnxt_free_tx_rings(bp);
 174         bnxt_free_rx_rings(bp);
 175 }
 176
 177 static int bnxt_alloc_mem(struct bnxt *bp)
 178 {
 179         int rc;
 180
 181         rc = bnxt_alloc_vnic_mem(bp);
 182         if (rc)
 183                 goto alloc_mem_err;
 184
 185         rc = bnxt_alloc_vnic_attributes(bp);
 186         if (rc)
 187                 goto alloc_mem_err;
 188
 189         rc = bnxt_alloc_filter_mem(bp);
 190         if (rc)
 191                 goto alloc_mem_err;
 192
 193         return 0;
 194
 195 alloc_mem_err:
 196         bnxt_free_mem(bp);
 197         return rc;
 198 }
 199
 200 static int bnxt_init_chip(struct bnxt *bp)
 201 {
 202         unsigned int i;
 203         struct rte_eth_link new;
 204         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 205         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 206         uint32_t intr_vector = 0;
 207         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 208         uint32_t vec = BNXT_MISC_VEC_ID;
 209         int rc;
 210
 211         /* disable uio/vfio intr/eventfd mapping */
 212         rte_intr_disable(intr_handle);
 213
 214         if (bp->eth_dev->data->mtu > ETHER_MTU) {
 215                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 216                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 217                 bp->flags |= BNXT_FLAG_JUMBO;
 218         } else {
 219                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 220                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 221                 bp->flags &= ~BNXT_FLAG_JUMBO;
 222         }
 223
 224         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 225         if (rc) {
 226                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 227                 goto err_out;
 228         }
 229
 230         rc = bnxt_alloc_hwrm_rings(bp);
 231         if (rc) {
 232                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 233                 goto err_out;
 234         }
 235
 236         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 237         if (rc) {
 238                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 239                 goto err_out;
 240         }
 241
 242         rc = bnxt_mq_rx_configure(bp);
 243         if (rc) {
 244                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 245                 goto err_out;
 246         }
 247
 248         /* VNIC configuration */
 249         for (i = 0; i < bp->nr_vnics; i++) {
 250                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 251
 252                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 253                 if (rc) {
 254                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 255                                 i, rc);
 256                         goto err_out;
 257                 }
 258
 259                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
 260                 if (rc) {
 261                         PMD_DRV_LOG(ERR,
 262                                 "HWRM vnic %d ctx alloc failure rc: %x\n",
 263                                 i, rc);
 264                         goto err_out;
 265                 }
 266
 267                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 268                 if (rc) {
 269                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 270                                 i, rc);
 271                         goto err_out;
 272                 }
 273
 274                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 275                 if (rc) {
 276                         PMD_DRV_LOG(ERR,
 277                                 "HWRM vnic %d filter failure rc: %x\n",
 278                                 i, rc);
 279                         goto err_out;
 280                 }
 281
 282                 rc = bnxt_vnic_rss_configure(bp, vnic);
 283                 if (rc) {
 284                         PMD_DRV_LOG(ERR,
 285                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 286                         goto err_out;
 287                 }
 288
 289                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 290
 291                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 292                     DEV_RX_OFFLOAD_TCP_LRO)
 293                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 294                 else
 295                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 296         }
 297         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 298         if (rc) {
 299                 PMD_DRV_LOG(ERR,
 300                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 301                 goto err_out;
 302         }
 303
 304         /* check and configure queue intr-vector mapping */
 305         if ((rte_intr_cap_multiple(intr_handle) ||
 306              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 307             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 308                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 309                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 310                 if (intr_vector > bp->rx_cp_nr_rings) {
 311                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 312                                         bp->rx_cp_nr_rings);
 313                         return -ENOTSUP;
 314                 }
 315                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 316                         return -1;
 317         }
 318
 319         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 320                 intr_handle->intr_vec =
 321                         rte_zmalloc("intr_vec",
 322                                     bp->eth_dev->data->nb_rx_queues *
 323                                     sizeof(int), 0);
 324                 if (intr_handle->intr_vec == NULL) {
 325                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 326                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 327                         return -ENOMEM;
 328                 }
 329                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 330                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 331                          intr_handle->intr_vec, intr_handle->nb_efd,
 332                         intr_handle->max_intr);
 333         }
 334
 335         for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 336              queue_id++) {
 337                 intr_handle->intr_vec[queue_id] = vec;
 338                 if (vec < base + intr_handle->nb_efd - 1)
 339                         vec++;
 340         }
 341
 342         /* enable uio/vfio intr/eventfd mapping */
 343         rte_intr_enable(intr_handle);
 344
 345         rc = bnxt_get_hwrm_link_config(bp, &new);
 346         if (rc) {
 347                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 348                 goto err_out;
 349         }
 350
 351         if (!bp->link_info.link_up) {
 352                 rc = bnxt_set_hwrm_link_config(bp, true);
 353                 if (rc) {
 354                         PMD_DRV_LOG(ERR,
 355                                 "HWRM link config failure rc: %x\n", rc);
 356                         goto err_out;
 357                 }
 358         }
 359         bnxt_print_link_info(bp->eth_dev);
 360
 361         return 0;
 362
 363 err_out:
 364         bnxt_free_all_hwrm_resources(bp);
 365
 366         /* Some of the error status returned by FW may not be from errno.h */
 367         if (rc > 0)
 368                 rc = -EIO;
 369
 370         return rc;
 371 }
 372
 373 static int bnxt_shutdown_nic(struct bnxt *bp)
 374 {
 375         bnxt_free_all_hwrm_resources(bp);
 376         bnxt_free_all_filters(bp);
 377         bnxt_free_all_vnics(bp);
 378         return 0;
 379 }
 380
 381 static int bnxt_init_nic(struct bnxt *bp)
 382 {
 383         int rc;
 384
 385         rc = bnxt_init_ring_grps(bp);
 386         if (rc)
 387                 return rc;
 388
 389         bnxt_init_vnics(bp);
 390         bnxt_init_filters(bp);
 391
 392         return 0;
 393 }
 394
 395 /*
 396  * Device configuration and status function
 397  */
 398
 399 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 400                                   struct rte_eth_dev_info *dev_info)
 401 {
 402         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 403         uint16_t max_vnics, i, j, vpool, vrxq;
 404         unsigned int max_rx_rings;
 405
 406         /* MAC Specifics */
 407         dev_info->max_mac_addrs = bp->max_l2_ctx;
 408         dev_info->max_hash_mac_addrs = 0;
 409
 410         /* PF/VF specifics */
 411         if (BNXT_PF(bp))
 412                 dev_info->max_vfs = bp->pdev->max_vfs;
 413         max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx);
 414         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 415         dev_info->max_rx_queues = max_rx_rings;
 416         dev_info->max_tx_queues = max_rx_rings;
 417         dev_info->reta_size = bp->max_rsscos_ctx;
 418         dev_info->hash_key_size = 40;
 419         max_vnics = bp->max_vnics;
 420
 421         /* Fast path specifics */
 422         dev_info->min_rx_bufsize = 1;
 423         dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
 424                                   + VLAN_TAG_SIZE;
 425
 426         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 427         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 428                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 429         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 430         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 431
 432         /* *INDENT-OFF* */
 433         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 434                 .rx_thresh = {
 435                         .pthresh = 8,
 436                         .hthresh = 8,
 437                         .wthresh = 0,
 438                 },
 439                 .rx_free_thresh = 32,
 440                 /* If no descriptors available, pkts are dropped by default */
 441                 .rx_drop_en = 1,
 442         };
 443
 444         dev_info->default_txconf = (struct rte_eth_txconf) {
 445                 .tx_thresh = {
 446                         .pthresh = 32,
 447                         .hthresh = 0,
 448                         .wthresh = 0,
 449                 },
 450                 .tx_free_thresh = 32,
 451                 .tx_rs_thresh = 32,
 452         };
 453         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 454
 455         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 456         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 457         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 458         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 459         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 460
 461         /* *INDENT-ON* */
 462
 463         /*
 464          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 465          *       need further investigation.
 466          */
 467
 468         /* VMDq resources */
 469         vpool = 64; /* ETH_64_POOLS */
 470         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 471         for (i = 0; i < 4; vpool >>= 1, i++) {
 472                 if (max_vnics > vpool) {
 473                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 474                                 if (dev_info->max_rx_queues > vrxq) {
 475                                         if (vpool > vrxq)
 476                                                 vpool = vrxq;
 477                                         goto found;
 478                                 }
 479                         }
 480                         /* Not enough resources to support VMDq */
 481                         break;
 482                 }
 483         }
 484         /* Not enough resources to support VMDq */
 485         vpool = 0;
 486         vrxq = 0;
 487 found:
 488         dev_info->max_vmdq_pools = vpool;
 489         dev_info->vmdq_queue_num = vrxq;
 490
 491         dev_info->vmdq_pool_base = 0;
 492         dev_info->vmdq_queue_base = 0;
 493 }
 494
 495 /* Configure the device based on the configuration provided */
 496 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 497 {
 498         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 499         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 500
 501         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 502         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 503         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 504         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 505
 506         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 507                 int rc;
 508
 509                 rc = bnxt_hwrm_func_reserve_vf_resc(bp);
 510                 if (rc) {
 511                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 512                         return -ENOSPC;
 513                 }
 514
 515                 /* legacy driver needs to get updated values */
 516                 rc = bnxt_hwrm_func_qcaps(bp);
 517                 if (rc) {
 518                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 519                         return -ENOSPC;
 520                 }
 521         }
 522
 523         /* Inherit new configurations */
 524         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 525             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 526             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 527             bp->max_cp_rings ||
 528             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 529             bp->max_stat_ctx ||
 530             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) {
 531                 PMD_DRV_LOG(ERR,
 532                         "Insufficient resources to support requested config\n");
 533                 PMD_DRV_LOG(ERR,
 534                         "Num Queues Requested: Tx %d, Rx %d\n",
 535                         eth_dev->data->nb_tx_queues,
 536                         eth_dev->data->nb_rx_queues);
 537                 PMD_DRV_LOG(ERR,
 538                         "Res available: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d\n",
 539                         bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 540                         bp->max_stat_ctx, bp->max_ring_grps);
 541                 return -ENOSPC;
 542         }
 543
 544         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 545         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 546
 547         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 548                 eth_dev->data->mtu =
 549                                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 550                                 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE *
 551                                 BNXT_NUM_VLANS;
 552                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 553         }
 554         return 0;
 555 }
 556
 557 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 558 {
 559         struct rte_eth_link *link = &eth_dev->data->dev_link;
 560
 561         if (link->link_status)
 562                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 563                         eth_dev->data->port_id,
 564                         (uint32_t)link->link_speed,
 565                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 566                         ("full-duplex") : ("half-duplex\n"));
 567         else
 568                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 569                         eth_dev->data->port_id);
 570 }
 571
 572 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
 573 {
 574         bnxt_print_link_info(eth_dev);
 575         return 0;
 576 }
 577
 578 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 579 {
 580         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 581         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 582         int vlan_mask = 0;
 583         int rc;
 584
 585         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 586                 PMD_DRV_LOG(ERR,
 587                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 588                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 589         }
 590         bp->dev_stopped = 0;
 591
 592         rc = bnxt_init_chip(bp);
 593         if (rc)
 594                 goto error;
 595
 596         bnxt_link_update_op(eth_dev, 1);
 597
 598         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 599                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 600         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 601                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 602         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 603         if (rc)
 604                 goto error;
 605
 606         bp->flags |= BNXT_FLAG_INIT_DONE;
 607         return 0;
 608
 609 error:
 610         bnxt_shutdown_nic(bp);
 611         bnxt_free_tx_mbufs(bp);
 612         bnxt_free_rx_mbufs(bp);
 613         return rc;
 614 }
 615
 616 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 617 {
 618         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 619         int rc = 0;
 620
 621         if (!bp->link_info.link_up)
 622                 rc = bnxt_set_hwrm_link_config(bp, true);
 623         if (!rc)
 624                 eth_dev->data->dev_link.link_status = 1;
 625
 626         bnxt_print_link_info(eth_dev);
 627         return 0;
 628 }
 629
 630 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 631 {
 632         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 633
 634         eth_dev->data->dev_link.link_status = 0;
 635         bnxt_set_hwrm_link_config(bp, false);
 636         bp->link_info.link_up = 0;
 637
 638         return 0;
 639 }
 640
 641 /* Unload the driver, release resources */
 642 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 643 {
 644         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 645
 646         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 647         if (bp->eth_dev->data->dev_started) {
 648                 /* TBD: STOP HW queues DMA */
 649                 eth_dev->data->dev_link.link_status = 0;
 650         }
 651         bnxt_set_hwrm_link_config(bp, false);
 652         bnxt_hwrm_port_clr_stats(bp);
 653         bnxt_free_tx_mbufs(bp);
 654         bnxt_free_rx_mbufs(bp);
 655         bnxt_shutdown_nic(bp);
 656         bp->dev_stopped = 1;
 657 }
 658
 659 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 660 {
 661         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 662
 663         if (bp->dev_stopped == 0)
 664                 bnxt_dev_stop_op(eth_dev);
 665
 666         bnxt_free_mem(bp);
 667         if (eth_dev->data->mac_addrs != NULL) {
 668                 rte_free(eth_dev->data->mac_addrs);
 669                 eth_dev->data->mac_addrs = NULL;
 670         }
 671         if (bp->grp_info != NULL) {
 672                 rte_free(bp->grp_info);
 673                 bp->grp_info = NULL;
 674         }
 675
 676         bnxt_dev_uninit(eth_dev);
 677 }
 678
 679 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 680                                     uint32_t index)
 681 {
 682         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 683         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 684         struct bnxt_vnic_info *vnic;
 685         struct bnxt_filter_info *filter, *temp_filter;
 686         uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS);
 687         uint32_t i;
 688
 689         /*
 690          * Loop through all VNICs from the specified filter flow pools to
 691          * remove the corresponding MAC addr filter
 692          */
 693         for (i = 0; i < pool; i++) {
 694                 if (!(pool_mask & (1ULL << i)))
 695                         continue;
 696
 697                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 698                         filter = STAILQ_FIRST(&vnic->filter);
 699                         while (filter) {
 700                                 temp_filter = STAILQ_NEXT(filter, next);
 701                                 if (filter->mac_index == index) {
 702                                         STAILQ_REMOVE(&vnic->filter, filter,
 703                                                       bnxt_filter_info, next);
 704                                         bnxt_hwrm_clear_l2_filter(bp, filter);
 705                                         filter->mac_index = INVALID_MAC_INDEX;
 706                                         memset(&filter->l2_addr, 0,
 707                                                ETHER_ADDR_LEN);
 708                                         STAILQ_INSERT_TAIL(
 709                                                         &bp->free_filter_list,
 710                                                         filter, next);
 711                                 }
 712                                 filter = temp_filter;
 713                         }
 714                 }
 715         }
 716 }
 717
 718 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 719                                 struct ether_addr *mac_addr,
 720                                 uint32_t index, uint32_t pool)
 721 {
 722         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 723         struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
 724         struct bnxt_filter_info *filter;
 725
 726         if (BNXT_VF(bp)) {
 727                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
 728                 return -ENOTSUP;
 729         }
 730
 731         if (!vnic) {
 732                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
 733                 return -EINVAL;
 734         }
 735         /* Attach requested MAC address to the new l2_filter */
 736         STAILQ_FOREACH(filter, &vnic->filter, next) {
 737                 if (filter->mac_index == index) {
 738                         PMD_DRV_LOG(ERR,
 739                                 "MAC addr already existed for pool %d\n", pool);
 740                         return 0;
 741                 }
 742         }
 743         filter = bnxt_alloc_filter(bp);
 744         if (!filter) {
 745                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
 746                 return -ENODEV;
 747         }
 748         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 749         filter->mac_index = index;
 750         memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
 751         return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 752 }
 753
 754 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 755 {
 756         int rc = 0;
 757         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 758         struct rte_eth_link new;
 759         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 760
 761         memset(&new, 0, sizeof(new));
 762         do {
 763                 /* Retrieve link info from hardware */
 764                 rc = bnxt_get_hwrm_link_config(bp, &new);
 765                 if (rc) {
 766                         new.link_speed = ETH_LINK_SPEED_100M;
 767                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 768                         PMD_DRV_LOG(ERR,
 769                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 770                         goto out;
 771                 }
 772                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 773
 774                 if (!wait_to_complete)
 775                         break;
 776         } while (!new.link_status && cnt--);
 777
 778 out:
 779         /* Timed out or success */
 780         if (new.link_status != eth_dev->data->dev_link.link_status ||
 781         new.link_speed != eth_dev->data->dev_link.link_speed) {
 782                 memcpy(&eth_dev->data->dev_link, &new,
 783                         sizeof(struct rte_eth_link));
 784
 785                 _rte_eth_dev_callback_process(eth_dev,
 786                                               RTE_ETH_EVENT_INTR_LSC,
 787                                               NULL);
 788
 789                 bnxt_print_link_info(eth_dev);
 790         }
 791
 792         return rc;
 793 }
 794
 795 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
 796 {
 797         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 798         struct bnxt_vnic_info *vnic;
 799
 800         if (bp->vnic_info == NULL)
 801                 return;
 802
 803         vnic = &bp->vnic_info[0];
 804
 805         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
 806         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 807 }
 808
 809 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
 810 {
 811         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 812         struct bnxt_vnic_info *vnic;
 813
 814         if (bp->vnic_info == NULL)
 815                 return;
 816
 817         vnic = &bp->vnic_info[0];
 818
 819         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
 820         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 821 }
 822
 823 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
 824 {
 825         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 826         struct bnxt_vnic_info *vnic;
 827
 828         if (bp->vnic_info == NULL)
 829                 return;
 830
 831         vnic = &bp->vnic_info[0];
 832
 833         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
 834         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 835 }
 836
 837 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
 838 {
 839         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 840         struct bnxt_vnic_info *vnic;
 841
 842         if (bp->vnic_info == NULL)
 843                 return;
 844
 845         vnic = &bp->vnic_info[0];
 846
 847         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
 848         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 849 }
 850
 851 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
 852                             struct rte_eth_rss_reta_entry64 *reta_conf,
 853                             uint16_t reta_size)
 854 {
 855         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 856         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 857         struct bnxt_vnic_info *vnic;
 858         int i;
 859
 860         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
 861                 return -EINVAL;
 862
 863         if (reta_size != HW_HASH_INDEX_SIZE) {
 864                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
 865                         "(%d) must equal the size supported by the hardware "
 866                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 867                 return -EINVAL;
 868         }
 869         /* Update the RSS VNIC(s) */
 870         for (i = 0; i < MAX_FF_POOLS; i++) {
 871                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 872                         memcpy(vnic->rss_table, reta_conf, reta_size);
 873
 874                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 875                 }
 876         }
 877         return 0;
 878 }
 879
 880 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
 881                               struct rte_eth_rss_reta_entry64 *reta_conf,
 882                               uint16_t reta_size)
 883 {
 884         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 885         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 886         struct rte_intr_handle *intr_handle
 887                 = &bp->pdev->intr_handle;
 888
 889         /* Retrieve from the default VNIC */
 890         if (!vnic)
 891                 return -EINVAL;
 892         if (!vnic->rss_table)
 893                 return -EINVAL;
 894
 895         if (reta_size != HW_HASH_INDEX_SIZE) {
 896                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
 897                         "(%d) must equal the size supported by the hardware "
 898                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 899                 return -EINVAL;
 900         }
 901         /* EW - need to revisit here copying from uint64_t to uint16_t */
 902         memcpy(reta_conf, vnic->rss_table, reta_size);
 903
 904         if (rte_intr_allow_others(intr_handle)) {
 905                 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
 906                         bnxt_dev_lsc_intr_setup(eth_dev);
 907         }
 908
 909         return 0;
 910 }
 911
 912 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
 913                                    struct rte_eth_rss_conf *rss_conf)
 914 {
 915         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 916         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 917         struct bnxt_vnic_info *vnic;
 918         uint16_t hash_type = 0;
 919         int i;
 920
 921         /*
 922          * If RSS enablement were different than dev_configure,
 923          * then return -EINVAL
 924          */
 925         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
 926                 if (!rss_conf->rss_hf)
 927                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
 928         } else {
 929                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
 930                         return -EINVAL;
 931         }
 932
 933         bp->flags |= BNXT_FLAG_UPDATE_HASH;
 934         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
 935
 936         if (rss_conf->rss_hf & ETH_RSS_IPV4)
 937                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 938         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
 939                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 940         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
 941                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
 942         if (rss_conf->rss_hf & ETH_RSS_IPV6)
 943                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
 944         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
 945                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
 946         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
 947                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
 948
 949         /* Update the RSS VNIC(s) */
 950         for (i = 0; i < MAX_FF_POOLS; i++) {
 951                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 952                         vnic->hash_type = hash_type;
 953
 954                         /*
 955                          * Use the supplied key if the key length is
 956                          * acceptable and the rss_key is not NULL
 957                          */
 958                         if (rss_conf->rss_key &&
 959                             rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
 960                                 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
 961                                        rss_conf->rss_key_len);
 962
 963                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 964                 }
 965         }
 966         return 0;
 967 }
 968
 969 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
 970                                      struct rte_eth_rss_conf *rss_conf)
 971 {
 972         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 973         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 974         int len;
 975         uint32_t hash_types;
 976
 977         /* RSS configuration is the same for all VNICs */
 978         if (vnic && vnic->rss_hash_key) {
 979                 if (rss_conf->rss_key) {
 980                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
 981                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
 982                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
 983                 }
 984
 985                 hash_types = vnic->hash_type;
 986                 rss_conf->rss_hf = 0;
 987                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
 988                         rss_conf->rss_hf |= ETH_RSS_IPV4;
 989                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 990                 }
 991                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
 992                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
 993                         hash_types &=
 994                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 995                 }
 996                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
 997                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
 998                         hash_types &=
 999                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1000                 }
1001                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1002                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1003                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1004                 }
1005                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1006                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1007                         hash_types &=
1008                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1009                 }
1010                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1011                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1012                         hash_types &=
1013                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1014                 }
1015                 if (hash_types) {
1016                         PMD_DRV_LOG(ERR,
1017                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1018                                 vnic->hash_type);
1019                         return -ENOTSUP;
1020                 }
1021         } else {
1022                 rss_conf->rss_hf = 0;
1023         }
1024         return 0;
1025 }
1026
1027 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1028                                struct rte_eth_fc_conf *fc_conf)
1029 {
1030         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1031         struct rte_eth_link link_info;
1032         int rc;
1033
1034         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1035         if (rc)
1036                 return rc;
1037
1038         memset(fc_conf, 0, sizeof(*fc_conf));
1039         if (bp->link_info.auto_pause)
1040                 fc_conf->autoneg = 1;
1041         switch (bp->link_info.pause) {
1042         case 0:
1043                 fc_conf->mode = RTE_FC_NONE;
1044                 break;
1045         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1046                 fc_conf->mode = RTE_FC_TX_PAUSE;
1047                 break;
1048         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1049                 fc_conf->mode = RTE_FC_RX_PAUSE;
1050                 break;
1051         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1052                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1053                 fc_conf->mode = RTE_FC_FULL;
1054                 break;
1055         }
1056         return 0;
1057 }
1058
1059 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1060                                struct rte_eth_fc_conf *fc_conf)
1061 {
1062         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1063
1064         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1065                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1066                 return -ENOTSUP;
1067         }
1068
1069         switch (fc_conf->mode) {
1070         case RTE_FC_NONE:
1071                 bp->link_info.auto_pause = 0;
1072                 bp->link_info.force_pause = 0;
1073                 break;
1074         case RTE_FC_RX_PAUSE:
1075                 if (fc_conf->autoneg) {
1076                         bp->link_info.auto_pause =
1077                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1078                         bp->link_info.force_pause = 0;
1079                 } else {
1080                         bp->link_info.auto_pause = 0;
1081                         bp->link_info.force_pause =
1082                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1083                 }
1084                 break;
1085         case RTE_FC_TX_PAUSE:
1086                 if (fc_conf->autoneg) {
1087                         bp->link_info.auto_pause =
1088                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1089                         bp->link_info.force_pause = 0;
1090                 } else {
1091                         bp->link_info.auto_pause = 0;
1092                         bp->link_info.force_pause =
1093                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1094                 }
1095                 break;
1096         case RTE_FC_FULL:
1097                 if (fc_conf->autoneg) {
1098                         bp->link_info.auto_pause =
1099                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1100                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1101                         bp->link_info.force_pause = 0;
1102                 } else {
1103                         bp->link_info.auto_pause = 0;
1104                         bp->link_info.force_pause =
1105                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1106                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1107                 }
1108                 break;
1109         }
1110         return bnxt_set_hwrm_link_config(bp, true);
1111 }
1112
1113 /* Add UDP tunneling port */
1114 static int
1115 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1116                          struct rte_eth_udp_tunnel *udp_tunnel)
1117 {
1118         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1119         uint16_t tunnel_type = 0;
1120         int rc = 0;
1121
1122         switch (udp_tunnel->prot_type) {
1123         case RTE_TUNNEL_TYPE_VXLAN:
1124                 if (bp->vxlan_port_cnt) {
1125                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1126                                 udp_tunnel->udp_port);
1127                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1128                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1129                                 return -ENOSPC;
1130                         }
1131                         bp->vxlan_port_cnt++;
1132                         return 0;
1133                 }
1134                 tunnel_type =
1135                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1136                 bp->vxlan_port_cnt++;
1137                 break;
1138         case RTE_TUNNEL_TYPE_GENEVE:
1139                 if (bp->geneve_port_cnt) {
1140                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1141                                 udp_tunnel->udp_port);
1142                         if (bp->geneve_port != udp_tunnel->udp_port) {
1143                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1144                                 return -ENOSPC;
1145                         }
1146                         bp->geneve_port_cnt++;
1147                         return 0;
1148                 }
1149                 tunnel_type =
1150                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1151                 bp->geneve_port_cnt++;
1152                 break;
1153         default:
1154                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1155                 return -ENOTSUP;
1156         }
1157         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1158                                              tunnel_type);
1159         return rc;
1160 }
1161
1162 static int
1163 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1164                          struct rte_eth_udp_tunnel *udp_tunnel)
1165 {
1166         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1167         uint16_t tunnel_type = 0;
1168         uint16_t port = 0;
1169         int rc = 0;
1170
1171         switch (udp_tunnel->prot_type) {
1172         case RTE_TUNNEL_TYPE_VXLAN:
1173                 if (!bp->vxlan_port_cnt) {
1174                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1175                         return -EINVAL;
1176                 }
1177                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1178                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1179                                 udp_tunnel->udp_port, bp->vxlan_port);
1180                         return -EINVAL;
1181                 }
1182                 if (--bp->vxlan_port_cnt)
1183                         return 0;
1184
1185                 tunnel_type =
1186                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1187                 port = bp->vxlan_fw_dst_port_id;
1188                 break;
1189         case RTE_TUNNEL_TYPE_GENEVE:
1190                 if (!bp->geneve_port_cnt) {
1191                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1192                         return -EINVAL;
1193                 }
1194                 if (bp->geneve_port != udp_tunnel->udp_port) {
1195                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1196                                 udp_tunnel->udp_port, bp->geneve_port);
1197                         return -EINVAL;
1198                 }
1199                 if (--bp->geneve_port_cnt)
1200                         return 0;
1201
1202                 tunnel_type =
1203                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1204                 port = bp->geneve_fw_dst_port_id;
1205                 break;
1206         default:
1207                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1208                 return -ENOTSUP;
1209         }
1210
1211         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1212         if (!rc) {
1213                 if (tunnel_type ==
1214                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1215                         bp->vxlan_port = 0;
1216                 if (tunnel_type ==
1217                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1218                         bp->geneve_port = 0;
1219         }
1220         return rc;
1221 }
1222
1223 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1224 {
1225         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1226         struct bnxt_vnic_info *vnic;
1227         unsigned int i;
1228         int rc = 0;
1229         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1230
1231         /* Cycle through all VNICs */
1232         for (i = 0; i < bp->nr_vnics; i++) {
1233                 /*
1234                  * For each VNIC and each associated filter(s)
1235                  * if VLAN exists && VLAN matches vlan_id
1236                  *      remove the MAC+VLAN filter
1237                  *      add a new MAC only filter
1238                  * else
1239                  *      VLAN filter doesn't exist, just skip and continue
1240                  */
1241                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1242                         filter = STAILQ_FIRST(&vnic->filter);
1243                         while (filter) {
1244                                 temp_filter = STAILQ_NEXT(filter, next);
1245
1246                                 if (filter->enables & chk &&
1247                                     filter->l2_ovlan == vlan_id) {
1248                                         /* Must delete the filter */
1249                                         STAILQ_REMOVE(&vnic->filter, filter,
1250                                                       bnxt_filter_info, next);
1251                                         bnxt_hwrm_clear_l2_filter(bp, filter);
1252                                         STAILQ_INSERT_TAIL(
1253                                                         &bp->free_filter_list,
1254                                                         filter, next);
1255
1256                                         /*
1257                                          * Need to examine to see if the MAC
1258                                          * filter already existed or not before
1259                                          * allocating a new one
1260                                          */
1261
1262                                         new_filter = bnxt_alloc_filter(bp);
1263                                         if (!new_filter) {
1264                                                 PMD_DRV_LOG(ERR,
1265                                                         "MAC/VLAN filter alloc failed\n");
1266                                                 rc = -ENOMEM;
1267                                                 goto exit;
1268                                         }
1269                                         STAILQ_INSERT_TAIL(&vnic->filter,
1270                                                            new_filter, next);
1271                                         /* Inherit MAC from previous filter */
1272                                         new_filter->mac_index =
1273                                                         filter->mac_index;
1274                                         memcpy(new_filter->l2_addr,
1275                                                filter->l2_addr, ETHER_ADDR_LEN);
1276                                         /* MAC only filter */
1277                                         rc = bnxt_hwrm_set_l2_filter(bp,
1278                                                         vnic->fw_vnic_id,
1279                                                         new_filter);
1280                                         if (rc)
1281                                                 goto exit;
1282                                         PMD_DRV_LOG(INFO,
1283                                                 "Del Vlan filter for %d\n",
1284                                                 vlan_id);
1285                                 }
1286                                 filter = temp_filter;
1287                         }
1288                 }
1289         }
1290 exit:
1291         return rc;
1292 }
1293
1294 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1295 {
1296         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1297         struct bnxt_vnic_info *vnic;
1298         unsigned int i;
1299         int rc = 0;
1300         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1301                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1302         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1303
1304         /* Cycle through all VNICs */
1305         for (i = 0; i < bp->nr_vnics; i++) {
1306                 /*
1307                  * For each VNIC and each associated filter(s)
1308                  * if VLAN exists:
1309                  *   if VLAN matches vlan_id
1310                  *      VLAN filter already exists, just skip and continue
1311                  *   else
1312                  *      add a new MAC+VLAN filter
1313                  * else
1314                  *   Remove the old MAC only filter
1315                  *    Add a new MAC+VLAN filter
1316                  */
1317                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1318                         filter = STAILQ_FIRST(&vnic->filter);
1319                         while (filter) {
1320                                 temp_filter = STAILQ_NEXT(filter, next);
1321
1322                                 if (filter->enables & chk) {
1323                                         if (filter->l2_ovlan == vlan_id)
1324                                                 goto cont;
1325                                 } else {
1326                                         /* Must delete the MAC filter */
1327                                         STAILQ_REMOVE(&vnic->filter, filter,
1328                                                       bnxt_filter_info, next);
1329                                         bnxt_hwrm_clear_l2_filter(bp, filter);
1330                                         filter->l2_ovlan = 0;
1331                                         STAILQ_INSERT_TAIL(
1332                                                         &bp->free_filter_list,
1333                                                         filter, next);
1334                                 }
1335                                 new_filter = bnxt_alloc_filter(bp);
1336                                 if (!new_filter) {
1337                                         PMD_DRV_LOG(ERR,
1338                                                 "MAC/VLAN filter alloc failed\n");
1339                                         rc = -ENOMEM;
1340                                         goto exit;
1341                                 }
1342                                 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1343                                                    next);
1344                                 /* Inherit MAC from the previous filter */
1345                                 new_filter->mac_index = filter->mac_index;
1346                                 memcpy(new_filter->l2_addr, filter->l2_addr,
1347                                        ETHER_ADDR_LEN);
1348                                 /* MAC + VLAN ID filter */
1349                                 new_filter->l2_ovlan = vlan_id;
1350                                 new_filter->l2_ovlan_mask = 0xF000;
1351                                 new_filter->enables |= en;
1352                                 rc = bnxt_hwrm_set_l2_filter(bp,
1353                                                              vnic->fw_vnic_id,
1354                                                              new_filter);
1355                                 if (rc)
1356                                         goto exit;
1357                                 PMD_DRV_LOG(INFO,
1358                                         "Added Vlan filter for %d\n", vlan_id);
1359 cont:
1360                                 filter = temp_filter;
1361                         }
1362                 }
1363         }
1364 exit:
1365         return rc;
1366 }
1367
1368 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1369                                    uint16_t vlan_id, int on)
1370 {
1371         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1372
1373         /* These operations apply to ALL existing MAC/VLAN filters */
1374         if (on)
1375                 return bnxt_add_vlan_filter(bp, vlan_id);
1376         else
1377                 return bnxt_del_vlan_filter(bp, vlan_id);
1378 }
1379
1380 static int
1381 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1382 {
1383         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1384         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1385         unsigned int i;
1386
1387         if (mask & ETH_VLAN_FILTER_MASK) {
1388                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1389                         /* Remove any VLAN filters programmed */
1390                         for (i = 0; i < 4095; i++)
1391                                 bnxt_del_vlan_filter(bp, i);
1392                 }
1393                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1394                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1395         }
1396
1397         if (mask & ETH_VLAN_STRIP_MASK) {
1398                 /* Enable or disable VLAN stripping */
1399                 for (i = 0; i < bp->nr_vnics; i++) {
1400                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1401                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1402                                 vnic->vlan_strip = true;
1403                         else
1404                                 vnic->vlan_strip = false;
1405                         bnxt_hwrm_vnic_cfg(bp, vnic);
1406                 }
1407                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1408                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1409         }
1410
1411         if (mask & ETH_VLAN_EXTEND_MASK)
1412                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1413
1414         return 0;
1415 }
1416
1417 static int
1418 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1419 {
1420         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1421         /* Default Filter is tied to VNIC 0 */
1422         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1423         struct bnxt_filter_info *filter;
1424         int rc;
1425
1426         if (BNXT_VF(bp))
1427                 return -EPERM;
1428
1429         memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1430
1431         STAILQ_FOREACH(filter, &vnic->filter, next) {
1432                 /* Default Filter is at Index 0 */
1433                 if (filter->mac_index != 0)
1434                         continue;
1435                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1436                 if (rc)
1437                         return rc;
1438                 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1439                 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1440                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1441                 filter->enables |=
1442                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1443                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1444                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1445                 if (rc)
1446                         return rc;
1447                 filter->mac_index = 0;
1448                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1449         }
1450
1451         return 0;
1452 }
1453
1454 static int
1455 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1456                           struct ether_addr *mc_addr_set,
1457                           uint32_t nb_mc_addr)
1458 {
1459         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1460         char *mc_addr_list = (char *)mc_addr_set;
1461         struct bnxt_vnic_info *vnic;
1462         uint32_t off = 0, i = 0;
1463
1464         vnic = &bp->vnic_info[0];
1465
1466         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1467                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1468                 goto allmulti;
1469         }
1470
1471         /* TODO Check for Duplicate mcast addresses */
1472         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1473         for (i = 0; i < nb_mc_addr; i++) {
1474                 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1475                 off += ETHER_ADDR_LEN;
1476         }
1477
1478         vnic->mc_addr_cnt = i;
1479
1480 allmulti:
1481         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1482 }
1483
1484 static int
1485 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1486 {
1487         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1488         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1489         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1490         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1491         int ret;
1492
1493         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1494                         fw_major, fw_minor, fw_updt);
1495
1496         ret += 1; /* add the size of '\0' */
1497         if (fw_size < (uint32_t)ret)
1498                 return ret;
1499         else
1500                 return 0;
1501 }
1502
1503 static void
1504 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1505         struct rte_eth_rxq_info *qinfo)
1506 {
1507         struct bnxt_rx_queue *rxq;
1508
1509         rxq = dev->data->rx_queues[queue_id];
1510
1511         qinfo->mp = rxq->mb_pool;
1512         qinfo->scattered_rx = dev->data->scattered_rx;
1513         qinfo->nb_desc = rxq->nb_rx_desc;
1514
1515         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1516         qinfo->conf.rx_drop_en = 0;
1517         qinfo->conf.rx_deferred_start = 0;
1518 }
1519
1520 static void
1521 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1522         struct rte_eth_txq_info *qinfo)
1523 {
1524         struct bnxt_tx_queue *txq;
1525
1526         txq = dev->data->tx_queues[queue_id];
1527
1528         qinfo->nb_desc = txq->nb_tx_desc;
1529
1530         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1531         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1532         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1533
1534         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1535         qinfo->conf.tx_rs_thresh = 0;
1536         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1537 }
1538
1539 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1540 {
1541         struct bnxt *bp = eth_dev->data->dev_private;
1542         struct rte_eth_dev_info dev_info;
1543         uint32_t max_dev_mtu;
1544         uint32_t rc = 0;
1545         uint32_t i;
1546
1547         bnxt_dev_info_get_op(eth_dev, &dev_info);
1548         max_dev_mtu = dev_info.max_rx_pktlen -
1549                       ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1550
1551         if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1552                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1553                         ETHER_MIN_MTU, max_dev_mtu);
1554                 return -EINVAL;
1555         }
1556
1557
1558         if (new_mtu > ETHER_MTU) {
1559                 bp->flags |= BNXT_FLAG_JUMBO;
1560                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1561                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1562         } else {
1563                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1564                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1565                 bp->flags &= ~BNXT_FLAG_JUMBO;
1566         }
1567
1568         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1569                 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1570
1571         eth_dev->data->mtu = new_mtu;
1572         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1573
1574         for (i = 0; i < bp->nr_vnics; i++) {
1575                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1576
1577                 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1578                                         ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1579                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1580                 if (rc)
1581                         break;
1582
1583                 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1584                 if (rc)
1585                         return rc;
1586         }
1587
1588         return rc;
1589 }
1590
1591 static int
1592 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1593 {
1594         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1595         uint16_t vlan = bp->vlan;
1596         int rc;
1597
1598         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1599                 PMD_DRV_LOG(ERR,
1600                         "PVID cannot be modified for this function\n");
1601                 return -ENOTSUP;
1602         }
1603         bp->vlan = on ? pvid : 0;
1604
1605         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1606         if (rc)
1607                 bp->vlan = vlan;
1608         return rc;
1609 }
1610
1611 static int
1612 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1613 {
1614         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1615
1616         return bnxt_hwrm_port_led_cfg(bp, true);
1617 }
1618
1619 static int
1620 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1621 {
1622         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1623
1624         return bnxt_hwrm_port_led_cfg(bp, false);
1625 }
1626
1627 static uint32_t
1628 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1629 {
1630         uint32_t desc = 0, raw_cons = 0, cons;
1631         struct bnxt_cp_ring_info *cpr;
1632         struct bnxt_rx_queue *rxq;
1633         struct rx_pkt_cmpl *rxcmp;
1634         uint16_t cmp_type;
1635         uint8_t cmp = 1;
1636         bool valid;
1637
1638         rxq = dev->data->rx_queues[rx_queue_id];
1639         cpr = rxq->cp_ring;
1640         valid = cpr->valid;
1641
1642         while (raw_cons < rxq->nb_rx_desc) {
1643                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1644                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1645
1646                 if (!CMPL_VALID(rxcmp, valid))
1647                         goto nothing_to_do;
1648                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1649                 cmp_type = CMP_TYPE(rxcmp);
1650                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1651                         cmp = (rte_le_to_cpu_32(
1652                                         ((struct rx_tpa_end_cmpl *)
1653                                          (rxcmp))->agg_bufs_v1) &
1654                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1655                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1656                         desc++;
1657                 } else if (cmp_type == 0x11) {
1658                         desc++;
1659                         cmp = (rxcmp->agg_bufs_v1 &
1660                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1661                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1662                 } else {
1663                         cmp = 1;
1664                 }
1665 nothing_to_do:
1666                 raw_cons += cmp ? cmp : 2;
1667         }
1668
1669         return desc;
1670 }
1671
1672 static int
1673 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1674 {
1675         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1676         struct bnxt_rx_ring_info *rxr;
1677         struct bnxt_cp_ring_info *cpr;
1678         struct bnxt_sw_rx_bd *rx_buf;
1679         struct rx_pkt_cmpl *rxcmp;
1680         uint32_t cons, cp_cons;
1681
1682         if (!rxq)
1683                 return -EINVAL;
1684
1685         cpr = rxq->cp_ring;
1686         rxr = rxq->rx_ring;
1687
1688         if (offset >= rxq->nb_rx_desc)
1689                 return -EINVAL;
1690
1691         cons = RING_CMP(cpr->cp_ring_struct, offset);
1692         cp_cons = cpr->cp_raw_cons;
1693         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1694
1695         if (cons > cp_cons) {
1696                 if (CMPL_VALID(rxcmp, cpr->valid))
1697                         return RTE_ETH_RX_DESC_DONE;
1698         } else {
1699                 if (CMPL_VALID(rxcmp, !cpr->valid))
1700                         return RTE_ETH_RX_DESC_DONE;
1701         }
1702         rx_buf = &rxr->rx_buf_ring[cons];
1703         if (rx_buf->mbuf == NULL)
1704                 return RTE_ETH_RX_DESC_UNAVAIL;
1705
1706
1707         return RTE_ETH_RX_DESC_AVAIL;
1708 }
1709
1710 static int
1711 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1712 {
1713         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1714         struct bnxt_tx_ring_info *txr;
1715         struct bnxt_cp_ring_info *cpr;
1716         struct bnxt_sw_tx_bd *tx_buf;
1717         struct tx_pkt_cmpl *txcmp;
1718         uint32_t cons, cp_cons;
1719
1720         if (!txq)
1721                 return -EINVAL;
1722
1723         cpr = txq->cp_ring;
1724         txr = txq->tx_ring;
1725
1726         if (offset >= txq->nb_tx_desc)
1727                 return -EINVAL;
1728
1729         cons = RING_CMP(cpr->cp_ring_struct, offset);
1730         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1731         cp_cons = cpr->cp_raw_cons;
1732
1733         if (cons > cp_cons) {
1734                 if (CMPL_VALID(txcmp, cpr->valid))
1735                         return RTE_ETH_TX_DESC_UNAVAIL;
1736         } else {
1737                 if (CMPL_VALID(txcmp, !cpr->valid))
1738                         return RTE_ETH_TX_DESC_UNAVAIL;
1739         }
1740         tx_buf = &txr->tx_buf_ring[cons];
1741         if (tx_buf->mbuf == NULL)
1742                 return RTE_ETH_TX_DESC_DONE;
1743
1744         return RTE_ETH_TX_DESC_FULL;
1745 }
1746
1747 static struct bnxt_filter_info *
1748 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1749                                 struct rte_eth_ethertype_filter *efilter,
1750                                 struct bnxt_vnic_info *vnic0,
1751                                 struct bnxt_vnic_info *vnic,
1752                                 int *ret)
1753 {
1754         struct bnxt_filter_info *mfilter = NULL;
1755         int match = 0;
1756         *ret = 0;
1757
1758         if (efilter->ether_type == ETHER_TYPE_IPv4 ||
1759                 efilter->ether_type == ETHER_TYPE_IPv6) {
1760                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1761                         " ethertype filter.", efilter->ether_type);
1762                 *ret = -EINVAL;
1763                 goto exit;
1764         }
1765         if (efilter->queue >= bp->rx_nr_rings) {
1766                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1767                 *ret = -EINVAL;
1768                 goto exit;
1769         }
1770
1771         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1772         vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1773         if (vnic == NULL) {
1774                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1775                 *ret = -EINVAL;
1776                 goto exit;
1777         }
1778
1779         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1780                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1781                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1782                                      mfilter->l2_addr, ETHER_ADDR_LEN) &&
1783                              mfilter->flags ==
1784                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1785                              mfilter->ethertype == efilter->ether_type)) {
1786                                 match = 1;
1787                                 break;
1788                         }
1789                 }
1790         } else {
1791                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1792                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1793                                      mfilter->l2_addr, ETHER_ADDR_LEN) &&
1794                              mfilter->ethertype == efilter->ether_type &&
1795                              mfilter->flags ==
1796                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1797                                 match = 1;
1798                                 break;
1799                         }
1800         }
1801
1802         if (match)
1803                 *ret = -EEXIST;
1804
1805 exit:
1806         return mfilter;
1807 }
1808
1809 static int
1810 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1811                         enum rte_filter_op filter_op,
1812                         void *arg)
1813 {
1814         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1815         struct rte_eth_ethertype_filter *efilter =
1816                         (struct rte_eth_ethertype_filter *)arg;
1817         struct bnxt_filter_info *bfilter, *filter1;
1818         struct bnxt_vnic_info *vnic, *vnic0;
1819         int ret;
1820
1821         if (filter_op == RTE_ETH_FILTER_NOP)
1822                 return 0;
1823
1824         if (arg == NULL) {
1825                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
1826                             filter_op);
1827                 return -EINVAL;
1828         }
1829
1830         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1831         vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1832
1833         switch (filter_op) {
1834         case RTE_ETH_FILTER_ADD:
1835                 bnxt_match_and_validate_ether_filter(bp, efilter,
1836                                                         vnic0, vnic, &ret);
1837                 if (ret < 0)
1838                         return ret;
1839
1840                 bfilter = bnxt_get_unused_filter(bp);
1841                 if (bfilter == NULL) {
1842                         PMD_DRV_LOG(ERR,
1843                                 "Not enough resources for a new filter.\n");
1844                         return -ENOMEM;
1845                 }
1846                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1847                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1848                        ETHER_ADDR_LEN);
1849                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1850                        ETHER_ADDR_LEN);
1851                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1852                 bfilter->ethertype = efilter->ether_type;
1853                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1854
1855                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1856                 if (filter1 == NULL) {
1857                         ret = -1;
1858                         goto cleanup;
1859                 }
1860                 bfilter->enables |=
1861                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1862                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1863
1864                 bfilter->dst_id = vnic->fw_vnic_id;
1865
1866                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1867                         bfilter->flags =
1868                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1869                 }
1870
1871                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1872                 if (ret)
1873                         goto cleanup;
1874                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1875                 break;
1876         case RTE_ETH_FILTER_DELETE:
1877                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1878                                                         vnic0, vnic, &ret);
1879                 if (ret == -EEXIST) {
1880                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1881
1882                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1883                                       next);
1884                         bnxt_free_filter(bp, filter1);
1885                 } else if (ret == 0) {
1886                         PMD_DRV_LOG(ERR, "No matching filter found\n");
1887                 }
1888                 break;
1889         default:
1890                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
1891                 ret = -EINVAL;
1892                 goto error;
1893         }
1894         return ret;
1895 cleanup:
1896         bnxt_free_filter(bp, bfilter);
1897 error:
1898         return ret;
1899 }
1900
1901 static inline int
1902 parse_ntuple_filter(struct bnxt *bp,
1903                     struct rte_eth_ntuple_filter *nfilter,
1904                     struct bnxt_filter_info *bfilter)
1905 {
1906         uint32_t en = 0;
1907
1908         if (nfilter->queue >= bp->rx_nr_rings) {
1909                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
1910                 return -EINVAL;
1911         }
1912
1913         switch (nfilter->dst_port_mask) {
1914         case UINT16_MAX:
1915                 bfilter->dst_port_mask = -1;
1916                 bfilter->dst_port = nfilter->dst_port;
1917                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1918                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1919                 break;
1920         default:
1921                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
1922                 return -EINVAL;
1923         }
1924
1925         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1926         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1927
1928         switch (nfilter->proto_mask) {
1929         case UINT8_MAX:
1930                 if (nfilter->proto == 17) /* IPPROTO_UDP */
1931                         bfilter->ip_protocol = 17;
1932                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1933                         bfilter->ip_protocol = 6;
1934                 else
1935                         return -EINVAL;
1936                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1937                 break;
1938         default:
1939                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
1940                 return -EINVAL;
1941         }
1942
1943         switch (nfilter->dst_ip_mask) {
1944         case UINT32_MAX:
1945                 bfilter->dst_ipaddr_mask[0] = -1;
1946                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
1947                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
1948                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
1949                 break;
1950         default:
1951                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
1952                 return -EINVAL;
1953         }
1954
1955         switch (nfilter->src_ip_mask) {
1956         case UINT32_MAX:
1957                 bfilter->src_ipaddr_mask[0] = -1;
1958                 bfilter->src_ipaddr[0] = nfilter->src_ip;
1959                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
1960                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
1961                 break;
1962         default:
1963                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
1964                 return -EINVAL;
1965         }
1966
1967         switch (nfilter->src_port_mask) {
1968         case UINT16_MAX:
1969                 bfilter->src_port_mask = -1;
1970                 bfilter->src_port = nfilter->src_port;
1971                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
1972                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
1973                 break;
1974         default:
1975                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
1976                 return -EINVAL;
1977         }
1978
1979         //TODO Priority
1980         //nfilter->priority = (uint8_t)filter->priority;
1981
1982         bfilter->enables = en;
1983         return 0;
1984 }
1985
1986 static struct bnxt_filter_info*
1987 bnxt_match_ntuple_filter(struct bnxt *bp,
1988                          struct bnxt_filter_info *bfilter,
1989                          struct bnxt_vnic_info **mvnic)
1990 {
1991         struct bnxt_filter_info *mfilter = NULL;
1992         int i;
1993
1994         for (i = bp->nr_vnics - 1; i >= 0; i--) {
1995                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1996                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
1997                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
1998                             bfilter->src_ipaddr_mask[0] ==
1999                             mfilter->src_ipaddr_mask[0] &&
2000                             bfilter->src_port == mfilter->src_port &&
2001                             bfilter->src_port_mask == mfilter->src_port_mask &&
2002                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2003                             bfilter->dst_ipaddr_mask[0] ==
2004                             mfilter->dst_ipaddr_mask[0] &&
2005                             bfilter->dst_port == mfilter->dst_port &&
2006                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2007                             bfilter->flags == mfilter->flags &&
2008                             bfilter->enables == mfilter->enables) {
2009                                 if (mvnic)
2010                                         *mvnic = vnic;
2011                                 return mfilter;
2012                         }
2013                 }
2014         }
2015         return NULL;
2016 }
2017
2018 static int
2019 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2020                        struct rte_eth_ntuple_filter *nfilter,
2021                        enum rte_filter_op filter_op)
2022 {
2023         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2024         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2025         int ret;
2026
2027         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2028                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2029                 return -EINVAL;
2030         }
2031
2032         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2033                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2034                 return -EINVAL;
2035         }
2036
2037         bfilter = bnxt_get_unused_filter(bp);
2038         if (bfilter == NULL) {
2039                 PMD_DRV_LOG(ERR,
2040                         "Not enough resources for a new filter.\n");
2041                 return -ENOMEM;
2042         }
2043         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2044         if (ret < 0)
2045                 goto free_filter;
2046
2047         vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]);
2048         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2049         filter1 = STAILQ_FIRST(&vnic0->filter);
2050         if (filter1 == NULL) {
2051                 ret = -1;
2052                 goto free_filter;
2053         }
2054
2055         bfilter->dst_id = vnic->fw_vnic_id;
2056         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2057         bfilter->enables |=
2058                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2059         bfilter->ethertype = 0x800;
2060         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2061
2062         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2063
2064         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2065             bfilter->dst_id == mfilter->dst_id) {
2066                 PMD_DRV_LOG(ERR, "filter exists.\n");
2067                 ret = -EEXIST;
2068                 goto free_filter;
2069         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2070                    bfilter->dst_id != mfilter->dst_id) {
2071                 mfilter->dst_id = vnic->fw_vnic_id;
2072                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2073                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2074                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2075                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2076                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2077                 goto free_filter;
2078         }
2079         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2080                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2081                 ret = -ENOENT;
2082                 goto free_filter;
2083         }
2084
2085         if (filter_op == RTE_ETH_FILTER_ADD) {
2086                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2087                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2088                 if (ret)
2089                         goto free_filter;
2090                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2091         } else {
2092                 if (mfilter == NULL) {
2093                         /* This should not happen. But for Coverity! */
2094                         ret = -ENOENT;
2095                         goto free_filter;
2096                 }
2097                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2098
2099                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2100                 bnxt_free_filter(bp, mfilter);
2101                 mfilter->fw_l2_filter_id = -1;
2102                 bnxt_free_filter(bp, bfilter);
2103                 bfilter->fw_l2_filter_id = -1;
2104         }
2105
2106         return 0;
2107 free_filter:
2108         bfilter->fw_l2_filter_id = -1;
2109         bnxt_free_filter(bp, bfilter);
2110         return ret;
2111 }
2112
2113 static int
2114 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2115                         enum rte_filter_op filter_op,
2116                         void *arg)
2117 {
2118         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2119         int ret;
2120
2121         if (filter_op == RTE_ETH_FILTER_NOP)
2122                 return 0;
2123
2124         if (arg == NULL) {
2125                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2126                             filter_op);
2127                 return -EINVAL;
2128         }
2129
2130         switch (filter_op) {
2131         case RTE_ETH_FILTER_ADD:
2132                 ret = bnxt_cfg_ntuple_filter(bp,
2133                         (struct rte_eth_ntuple_filter *)arg,
2134                         filter_op);
2135                 break;
2136         case RTE_ETH_FILTER_DELETE:
2137                 ret = bnxt_cfg_ntuple_filter(bp,
2138                         (struct rte_eth_ntuple_filter *)arg,
2139                         filter_op);
2140                 break;
2141         default:
2142                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2143                 ret = -EINVAL;
2144                 break;
2145         }
2146         return ret;
2147 }
2148
2149 static int
2150 bnxt_parse_fdir_filter(struct bnxt *bp,
2151                        struct rte_eth_fdir_filter *fdir,
2152                        struct bnxt_filter_info *filter)
2153 {
2154         enum rte_fdir_mode fdir_mode =
2155                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2156         struct bnxt_vnic_info *vnic0, *vnic;
2157         struct bnxt_filter_info *filter1;
2158         uint32_t en = 0;
2159         int i;
2160
2161         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2162                 return -EINVAL;
2163
2164         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2165         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2166
2167         switch (fdir->input.flow_type) {
2168         case RTE_ETH_FLOW_IPV4:
2169         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2170                 /* FALLTHROUGH */
2171                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2172                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2173                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2174                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2175                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2176                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2177                 filter->ip_addr_type =
2178                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2179                 filter->src_ipaddr_mask[0] = 0xffffffff;
2180                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2181                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2182                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2183                 filter->ethertype = 0x800;
2184                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2185                 break;
2186         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2187                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2188                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2189                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2190                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2191                 filter->dst_port_mask = 0xffff;
2192                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2193                 filter->src_port_mask = 0xffff;
2194                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2195                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2196                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2197                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2198                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2199                 filter->ip_protocol = 6;
2200                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2201                 filter->ip_addr_type =
2202                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2203                 filter->src_ipaddr_mask[0] = 0xffffffff;
2204                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2205                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2206                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2207                 filter->ethertype = 0x800;
2208                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2209                 break;
2210         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2211                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2212                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2213                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2214                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2215                 filter->dst_port_mask = 0xffff;
2216                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2217                 filter->src_port_mask = 0xffff;
2218                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2219                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2220                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2221                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2222                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2223                 filter->ip_protocol = 17;
2224                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2225                 filter->ip_addr_type =
2226                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2227                 filter->src_ipaddr_mask[0] = 0xffffffff;
2228                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2229                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2230                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2231                 filter->ethertype = 0x800;
2232                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2233                 break;
2234         case RTE_ETH_FLOW_IPV6:
2235         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2236                 /* FALLTHROUGH */
2237                 filter->ip_addr_type =
2238                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2239                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2240                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2241                 rte_memcpy(filter->src_ipaddr,
2242                            fdir->input.flow.ipv6_flow.src_ip, 16);
2243                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2244                 rte_memcpy(filter->dst_ipaddr,
2245                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2246                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2247                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2248                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2249                 memset(filter->src_ipaddr_mask, 0xff, 16);
2250                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2251                 filter->ethertype = 0x86dd;
2252                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2253                 break;
2254         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2255                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2256                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2257                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2258                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2259                 filter->dst_port_mask = 0xffff;
2260                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2261                 filter->src_port_mask = 0xffff;
2262                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2263                 filter->ip_addr_type =
2264                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2265                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2266                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2267                 rte_memcpy(filter->src_ipaddr,
2268                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2269                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2270                 rte_memcpy(filter->dst_ipaddr,
2271                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2272                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2273                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2274                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2275                 memset(filter->src_ipaddr_mask, 0xff, 16);
2276                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2277                 filter->ethertype = 0x86dd;
2278                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2279                 break;
2280         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2281                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2282                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2283                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2284                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2285                 filter->dst_port_mask = 0xffff;
2286                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2287                 filter->src_port_mask = 0xffff;
2288                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2289                 filter->ip_addr_type =
2290                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2291                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2292                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2293                 rte_memcpy(filter->src_ipaddr,
2294                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2295                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2296                 rte_memcpy(filter->dst_ipaddr,
2297                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2298                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2299                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2300                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2301                 memset(filter->src_ipaddr_mask, 0xff, 16);
2302                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2303                 filter->ethertype = 0x86dd;
2304                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2305                 break;
2306         case RTE_ETH_FLOW_L2_PAYLOAD:
2307                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2308                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2309                 break;
2310         case RTE_ETH_FLOW_VXLAN:
2311                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2312                         return -EINVAL;
2313                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2314                 filter->tunnel_type =
2315                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2316                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2317                 break;
2318         case RTE_ETH_FLOW_NVGRE:
2319                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2320                         return -EINVAL;
2321                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2322                 filter->tunnel_type =
2323                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2324                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2325                 break;
2326         case RTE_ETH_FLOW_UNKNOWN:
2327         case RTE_ETH_FLOW_RAW:
2328         case RTE_ETH_FLOW_FRAG_IPV4:
2329         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2330         case RTE_ETH_FLOW_FRAG_IPV6:
2331         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2332         case RTE_ETH_FLOW_IPV6_EX:
2333         case RTE_ETH_FLOW_IPV6_TCP_EX:
2334         case RTE_ETH_FLOW_IPV6_UDP_EX:
2335         case RTE_ETH_FLOW_GENEVE:
2336                 /* FALLTHROUGH */
2337         default:
2338                 return -EINVAL;
2339         }
2340
2341         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2342         vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2343         if (vnic == NULL) {
2344                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2345                 return -EINVAL;
2346         }
2347
2348
2349         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2350                 rte_memcpy(filter->dst_macaddr,
2351                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2352                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2353         }
2354
2355         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2356                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2357                 filter1 = STAILQ_FIRST(&vnic0->filter);
2358                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2359         } else {
2360                 filter->dst_id = vnic->fw_vnic_id;
2361                 for (i = 0; i < ETHER_ADDR_LEN; i++)
2362                         if (filter->dst_macaddr[i] == 0x00)
2363                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2364                         else
2365                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2366         }
2367
2368         if (filter1 == NULL)
2369                 return -EINVAL;
2370
2371         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2372         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2373
2374         filter->enables = en;
2375
2376         return 0;
2377 }
2378
2379 static struct bnxt_filter_info *
2380 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2381                 struct bnxt_vnic_info **mvnic)
2382 {
2383         struct bnxt_filter_info *mf = NULL;
2384         int i;
2385
2386         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2387                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2388
2389                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2390                         if (mf->filter_type == nf->filter_type &&
2391                             mf->flags == nf->flags &&
2392                             mf->src_port == nf->src_port &&
2393                             mf->src_port_mask == nf->src_port_mask &&
2394                             mf->dst_port == nf->dst_port &&
2395                             mf->dst_port_mask == nf->dst_port_mask &&
2396                             mf->ip_protocol == nf->ip_protocol &&
2397                             mf->ip_addr_type == nf->ip_addr_type &&
2398                             mf->ethertype == nf->ethertype &&
2399                             mf->vni == nf->vni &&
2400                             mf->tunnel_type == nf->tunnel_type &&
2401                             mf->l2_ovlan == nf->l2_ovlan &&
2402                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2403                             mf->l2_ivlan == nf->l2_ivlan &&
2404                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2405                             !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) &&
2406                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2407                                     ETHER_ADDR_LEN) &&
2408                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2409                                     ETHER_ADDR_LEN) &&
2410                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2411                                     ETHER_ADDR_LEN) &&
2412                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2413                                     sizeof(nf->src_ipaddr)) &&
2414                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2415                                     sizeof(nf->src_ipaddr_mask)) &&
2416                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2417                                     sizeof(nf->dst_ipaddr)) &&
2418                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2419                                     sizeof(nf->dst_ipaddr_mask))) {
2420                                 if (mvnic)
2421                                         *mvnic = vnic;
2422                                 return mf;
2423                         }
2424                 }
2425         }
2426         return NULL;
2427 }
2428
2429 static int
2430 bnxt_fdir_filter(struct rte_eth_dev *dev,
2431                  enum rte_filter_op filter_op,
2432                  void *arg)
2433 {
2434         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2435         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2436         struct bnxt_filter_info *filter, *match;
2437         struct bnxt_vnic_info *vnic, *mvnic;
2438         int ret = 0, i;
2439
2440         if (filter_op == RTE_ETH_FILTER_NOP)
2441                 return 0;
2442
2443         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2444                 return -EINVAL;
2445
2446         switch (filter_op) {
2447         case RTE_ETH_FILTER_ADD:
2448         case RTE_ETH_FILTER_DELETE:
2449                 /* FALLTHROUGH */
2450                 filter = bnxt_get_unused_filter(bp);
2451                 if (filter == NULL) {
2452                         PMD_DRV_LOG(ERR,
2453                                 "Not enough resources for a new flow.\n");
2454                         return -ENOMEM;
2455                 }
2456
2457                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2458                 if (ret != 0)
2459                         goto free_filter;
2460                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2461
2462                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2463                         vnic = STAILQ_FIRST(&bp->ff_pool[0]);
2464                 else
2465                         vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2466
2467                 match = bnxt_match_fdir(bp, filter, &mvnic);
2468                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2469                         if (match->dst_id == vnic->fw_vnic_id) {
2470                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2471                                 ret = -EEXIST;
2472                                 goto free_filter;
2473                         } else {
2474                                 match->dst_id = vnic->fw_vnic_id;
2475                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2476                                                                   match->dst_id,
2477                                                                   match);
2478                                 STAILQ_REMOVE(&mvnic->filter, match,
2479                                               bnxt_filter_info, next);
2480                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2481                                 PMD_DRV_LOG(ERR,
2482                                         "Filter with matching pattern exist\n");
2483                                 PMD_DRV_LOG(ERR,
2484                                         "Updated it to new destination q\n");
2485                                 goto free_filter;
2486                         }
2487                 }
2488                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2489                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2490                         ret = -ENOENT;
2491                         goto free_filter;
2492                 }
2493
2494                 if (filter_op == RTE_ETH_FILTER_ADD) {
2495                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2496                                                           filter->dst_id,
2497                                                           filter);
2498                         if (ret)
2499                                 goto free_filter;
2500                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2501                 } else {
2502                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2503                         STAILQ_REMOVE(&vnic->filter, match,
2504                                       bnxt_filter_info, next);
2505                         bnxt_free_filter(bp, match);
2506                         filter->fw_l2_filter_id = -1;
2507                         bnxt_free_filter(bp, filter);
2508                 }
2509                 break;
2510         case RTE_ETH_FILTER_FLUSH:
2511                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2512                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2513
2514                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2515                                 if (filter->filter_type ==
2516                                     HWRM_CFA_NTUPLE_FILTER) {
2517                                         ret =
2518                                         bnxt_hwrm_clear_ntuple_filter(bp,
2519                                                                       filter);
2520                                         STAILQ_REMOVE(&vnic->filter, filter,
2521                                                       bnxt_filter_info, next);
2522                                 }
2523                         }
2524                 }
2525                 return ret;
2526         case RTE_ETH_FILTER_UPDATE:
2527         case RTE_ETH_FILTER_STATS:
2528         case RTE_ETH_FILTER_INFO:
2529                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2530                 break;
2531         default:
2532                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2533                 ret = -EINVAL;
2534                 break;
2535         }
2536         return ret;
2537
2538 free_filter:
2539         filter->fw_l2_filter_id = -1;
2540         bnxt_free_filter(bp, filter);
2541         return ret;
2542 }
2543
2544 static int
2545 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2546                     enum rte_filter_type filter_type,
2547                     enum rte_filter_op filter_op, void *arg)
2548 {
2549         int ret = 0;
2550
2551         switch (filter_type) {
2552         case RTE_ETH_FILTER_TUNNEL:
2553                 PMD_DRV_LOG(ERR,
2554                         "filter type: %d: To be implemented\n", filter_type);
2555                 break;
2556         case RTE_ETH_FILTER_FDIR:
2557                 ret = bnxt_fdir_filter(dev, filter_op, arg);
2558                 break;
2559         case RTE_ETH_FILTER_NTUPLE:
2560                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2561                 break;
2562         case RTE_ETH_FILTER_ETHERTYPE:
2563                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2564                 break;
2565         case RTE_ETH_FILTER_GENERIC:
2566                 if (filter_op != RTE_ETH_FILTER_GET)
2567                         return -EINVAL;
2568                 *(const void **)arg = &bnxt_flow_ops;
2569                 break;
2570         default:
2571                 PMD_DRV_LOG(ERR,
2572                         "Filter type (%d) not supported", filter_type);
2573                 ret = -EINVAL;
2574                 break;
2575         }
2576         return ret;
2577 }
2578
2579 static const uint32_t *
2580 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2581 {
2582         static const uint32_t ptypes[] = {
2583                 RTE_PTYPE_L2_ETHER_VLAN,
2584                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2585                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2586                 RTE_PTYPE_L4_ICMP,
2587                 RTE_PTYPE_L4_TCP,
2588                 RTE_PTYPE_L4_UDP,
2589                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2590                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2591                 RTE_PTYPE_INNER_L4_ICMP,
2592                 RTE_PTYPE_INNER_L4_TCP,
2593                 RTE_PTYPE_INNER_L4_UDP,
2594                 RTE_PTYPE_UNKNOWN
2595         };
2596
2597         if (dev->rx_pkt_burst == bnxt_recv_pkts)
2598                 return ptypes;
2599         return NULL;
2600 }
2601
2602 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2603                          int reg_win)
2604 {
2605         uint32_t reg_base = *reg_arr & 0xfffff000;
2606         uint32_t win_off;
2607         int i;
2608
2609         for (i = 0; i < count; i++) {
2610                 if ((reg_arr[i] & 0xfffff000) != reg_base)
2611                         return -ERANGE;
2612         }
2613         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2614         rte_cpu_to_le_32(rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off));
2615         return 0;
2616 }
2617
2618 static int bnxt_map_ptp_regs(struct bnxt *bp)
2619 {
2620         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2621         uint32_t *reg_arr;
2622         int rc, i;
2623
2624         reg_arr = ptp->rx_regs;
2625         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2626         if (rc)
2627                 return rc;
2628
2629         reg_arr = ptp->tx_regs;
2630         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2631         if (rc)
2632                 return rc;
2633
2634         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2635                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2636
2637         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2638                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2639
2640         return 0;
2641 }
2642
2643 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2644 {
2645         rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2646                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16));
2647         rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2648                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20));
2649 }
2650
2651 static uint64_t bnxt_cc_read(struct bnxt *bp)
2652 {
2653         uint64_t ns;
2654
2655         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2656                               BNXT_GRCPF_REG_SYNC_TIME));
2657         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2658                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2659         return ns;
2660 }
2661
2662 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2663 {
2664         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2665         uint32_t fifo;
2666
2667         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2668                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2669         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2670                 return -EAGAIN;
2671
2672         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2673                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2674         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2675                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2676         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2677                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2678
2679         return 0;
2680 }
2681
2682 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2683 {
2684         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2685         struct bnxt_pf_info *pf = &bp->pf;
2686         uint16_t port_id;
2687         uint32_t fifo;
2688
2689         if (!ptp)
2690                 return -ENODEV;
2691
2692         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2693                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2694         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2695                 return -EAGAIN;
2696
2697         port_id = pf->port_id;
2698         rte_cpu_to_le_32(rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2699                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]));
2700
2701         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2702                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2703         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2704 /*              bnxt_clr_rx_ts(bp);       TBD  */
2705                 return -EBUSY;
2706         }
2707
2708         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2709                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2710         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2711                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2712
2713         return 0;
2714 }
2715
2716 static int
2717 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2718 {
2719         uint64_t ns;
2720         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2721         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2722
2723         if (!ptp)
2724                 return 0;
2725
2726         ns = rte_timespec_to_ns(ts);
2727         /* Set the timecounters to a new value. */
2728         ptp->tc.nsec = ns;
2729
2730         return 0;
2731 }
2732
2733 static int
2734 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2735 {
2736         uint64_t ns, systime_cycles;
2737         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2738         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2739
2740         if (!ptp)
2741                 return 0;
2742
2743         systime_cycles = bnxt_cc_read(bp);
2744         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2745         *ts = rte_ns_to_timespec(ns);
2746
2747         return 0;
2748 }
2749 static int
2750 bnxt_timesync_enable(struct rte_eth_dev *dev)
2751 {
2752         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2753         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2754         uint32_t shift = 0;
2755
2756         if (!ptp)
2757                 return 0;
2758
2759         ptp->rx_filter = 1;
2760         ptp->tx_tstamp_en = 1;
2761         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2762
2763         if (!bnxt_hwrm_ptp_cfg(bp))
2764                 bnxt_map_ptp_regs(bp);
2765
2766         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2767         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2768         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2769
2770         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2771         ptp->tc.cc_shift = shift;
2772         ptp->tc.nsec_mask = (1ULL << shift) - 1;
2773
2774         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2775         ptp->rx_tstamp_tc.cc_shift = shift;
2776         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2777
2778         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2779         ptp->tx_tstamp_tc.cc_shift = shift;
2780         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2781
2782         return 0;
2783 }
2784
2785 static int
2786 bnxt_timesync_disable(struct rte_eth_dev *dev)
2787 {
2788         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2789         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2790
2791         if (!ptp)
2792                 return 0;
2793
2794         ptp->rx_filter = 0;
2795         ptp->tx_tstamp_en = 0;
2796         ptp->rxctl = 0;
2797
2798         bnxt_hwrm_ptp_cfg(bp);
2799
2800         bnxt_unmap_ptp_regs(bp);
2801
2802         return 0;
2803 }
2804
2805 static int
2806 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2807                                  struct timespec *timestamp,
2808                                  uint32_t flags __rte_unused)
2809 {
2810         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2811         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2812         uint64_t rx_tstamp_cycles = 0;
2813         uint64_t ns;
2814
2815         if (!ptp)
2816                 return 0;
2817
2818         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2819         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2820         *timestamp = rte_ns_to_timespec(ns);
2821         return  0;
2822 }
2823
2824 static int
2825 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2826                                  struct timespec *timestamp)
2827 {
2828         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2829         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2830         uint64_t tx_tstamp_cycles = 0;
2831         uint64_t ns;
2832
2833         if (!ptp)
2834                 return 0;
2835
2836         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2837         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2838         *timestamp = rte_ns_to_timespec(ns);
2839
2840         return 0;
2841 }
2842
2843 static int
2844 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2845 {
2846         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2847         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2848
2849         if (!ptp)
2850                 return 0;
2851
2852         ptp->tc.nsec += delta;
2853
2854         return 0;
2855 }
2856
2857 static int
2858 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2859 {
2860         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2861         int rc;
2862         uint32_t dir_entries;
2863         uint32_t entry_length;
2864
2865         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
2866                 bp->pdev->addr.domain, bp->pdev->addr.bus,
2867                 bp->pdev->addr.devid, bp->pdev->addr.function);
2868
2869         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2870         if (rc != 0)
2871                 return rc;
2872
2873         return dir_entries * entry_length;
2874 }
2875
2876 static int
2877 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2878                 struct rte_dev_eeprom_info *in_eeprom)
2879 {
2880         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2881         uint32_t index;
2882         uint32_t offset;
2883
2884         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2885                 "len = %d\n", bp->pdev->addr.domain,
2886                 bp->pdev->addr.bus, bp->pdev->addr.devid,
2887                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2888
2889         if (in_eeprom->offset == 0) /* special offset value to get directory */
2890                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2891                                                 in_eeprom->data);
2892
2893         index = in_eeprom->offset >> 24;
2894         offset = in_eeprom->offset & 0xffffff;
2895
2896         if (index != 0)
2897                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2898                                            in_eeprom->length, in_eeprom->data);
2899
2900         return 0;
2901 }
2902
2903 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2904 {
2905         switch (dir_type) {
2906         case BNX_DIR_TYPE_CHIMP_PATCH:
2907         case BNX_DIR_TYPE_BOOTCODE:
2908         case BNX_DIR_TYPE_BOOTCODE_2:
2909         case BNX_DIR_TYPE_APE_FW:
2910         case BNX_DIR_TYPE_APE_PATCH:
2911         case BNX_DIR_TYPE_KONG_FW:
2912         case BNX_DIR_TYPE_KONG_PATCH:
2913         case BNX_DIR_TYPE_BONO_FW:
2914         case BNX_DIR_TYPE_BONO_PATCH:
2915                 /* FALLTHROUGH */
2916                 return true;
2917         }
2918
2919         return false;
2920 }
2921
2922 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2923 {
2924         switch (dir_type) {
2925         case BNX_DIR_TYPE_AVS:
2926         case BNX_DIR_TYPE_EXP_ROM_MBA:
2927         case BNX_DIR_TYPE_PCIE:
2928         case BNX_DIR_TYPE_TSCF_UCODE:
2929         case BNX_DIR_TYPE_EXT_PHY:
2930         case BNX_DIR_TYPE_CCM:
2931         case BNX_DIR_TYPE_ISCSI_BOOT:
2932         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2933         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2934                 /* FALLTHROUGH */
2935                 return true;
2936         }
2937
2938         return false;
2939 }
2940
2941 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
2942 {
2943         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2944                 bnxt_dir_type_is_other_exec_format(dir_type);
2945 }
2946
2947 static int
2948 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2949                 struct rte_dev_eeprom_info *in_eeprom)
2950 {
2951         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2952         uint8_t index, dir_op;
2953         uint16_t type, ext, ordinal, attr;
2954
2955         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2956                 "len = %d\n", bp->pdev->addr.domain,
2957                 bp->pdev->addr.bus, bp->pdev->addr.devid,
2958                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2959
2960         if (!BNXT_PF(bp)) {
2961                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
2962                 return -EINVAL;
2963         }
2964
2965         type = in_eeprom->magic >> 16;
2966
2967         if (type == 0xffff) { /* special value for directory operations */
2968                 index = in_eeprom->magic & 0xff;
2969                 dir_op = in_eeprom->magic >> 8;
2970                 if (index == 0)
2971                         return -EINVAL;
2972                 switch (dir_op) {
2973                 case 0x0e: /* erase */
2974                         if (in_eeprom->offset != ~in_eeprom->magic)
2975                                 return -EINVAL;
2976                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
2977                 default:
2978                         return -EINVAL;
2979                 }
2980         }
2981
2982         /* Create or re-write an NVM item: */
2983         if (bnxt_dir_type_is_executable(type) == true)
2984                 return -EOPNOTSUPP;
2985         ext = in_eeprom->magic & 0xffff;
2986         ordinal = in_eeprom->offset >> 16;
2987         attr = in_eeprom->offset & 0xffff;
2988
2989         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
2990                                      in_eeprom->data, in_eeprom->length);
2991         return 0;
2992 }
2993
2994 /*
2995  * Initialization
2996  */
2997
2998 static const struct eth_dev_ops bnxt_dev_ops = {
2999         .dev_infos_get = bnxt_dev_info_get_op,
3000         .dev_close = bnxt_dev_close_op,
3001         .dev_configure = bnxt_dev_configure_op,
3002         .dev_start = bnxt_dev_start_op,
3003         .dev_stop = bnxt_dev_stop_op,
3004         .dev_set_link_up = bnxt_dev_set_link_up_op,
3005         .dev_set_link_down = bnxt_dev_set_link_down_op,
3006         .stats_get = bnxt_stats_get_op,
3007         .stats_reset = bnxt_stats_reset_op,
3008         .rx_queue_setup = bnxt_rx_queue_setup_op,
3009         .rx_queue_release = bnxt_rx_queue_release_op,
3010         .tx_queue_setup = bnxt_tx_queue_setup_op,
3011         .tx_queue_release = bnxt_tx_queue_release_op,
3012         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3013         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3014         .reta_update = bnxt_reta_update_op,
3015         .reta_query = bnxt_reta_query_op,
3016         .rss_hash_update = bnxt_rss_hash_update_op,
3017         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3018         .link_update = bnxt_link_update_op,
3019         .promiscuous_enable = bnxt_promiscuous_enable_op,
3020         .promiscuous_disable = bnxt_promiscuous_disable_op,
3021         .allmulticast_enable = bnxt_allmulticast_enable_op,
3022         .allmulticast_disable = bnxt_allmulticast_disable_op,
3023         .mac_addr_add = bnxt_mac_addr_add_op,
3024         .mac_addr_remove = bnxt_mac_addr_remove_op,
3025         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3026         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3027         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3028         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3029         .vlan_filter_set = bnxt_vlan_filter_set_op,
3030         .vlan_offload_set = bnxt_vlan_offload_set_op,
3031         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3032         .mtu_set = bnxt_mtu_set_op,
3033         .mac_addr_set = bnxt_set_default_mac_addr_op,
3034         .xstats_get = bnxt_dev_xstats_get_op,
3035         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3036         .xstats_reset = bnxt_dev_xstats_reset_op,
3037         .fw_version_get = bnxt_fw_version_get,
3038         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3039         .rxq_info_get = bnxt_rxq_info_get_op,
3040         .txq_info_get = bnxt_txq_info_get_op,
3041         .dev_led_on = bnxt_dev_led_on_op,
3042         .dev_led_off = bnxt_dev_led_off_op,
3043         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3044         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3045         .rx_queue_count = bnxt_rx_queue_count_op,
3046         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3047         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3048         .rx_queue_start = bnxt_rx_queue_start,
3049         .rx_queue_stop = bnxt_rx_queue_stop,
3050         .tx_queue_start = bnxt_tx_queue_start,
3051         .tx_queue_stop = bnxt_tx_queue_stop,
3052         .filter_ctrl = bnxt_filter_ctrl_op,
3053         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3054         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3055         .get_eeprom           = bnxt_get_eeprom_op,
3056         .set_eeprom           = bnxt_set_eeprom_op,
3057         .timesync_enable      = bnxt_timesync_enable,
3058         .timesync_disable     = bnxt_timesync_disable,
3059         .timesync_read_time   = bnxt_timesync_read_time,
3060         .timesync_write_time   = bnxt_timesync_write_time,
3061         .timesync_adjust_time = bnxt_timesync_adjust_time,
3062         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3063         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3064 };
3065
3066 static bool bnxt_vf_pciid(uint16_t id)
3067 {
3068         if (id == BROADCOM_DEV_ID_57304_VF ||
3069             id == BROADCOM_DEV_ID_57406_VF ||
3070             id == BROADCOM_DEV_ID_5731X_VF ||
3071             id == BROADCOM_DEV_ID_5741X_VF ||
3072             id == BROADCOM_DEV_ID_57414_VF ||
3073             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3074             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3075             id == BROADCOM_DEV_ID_58802_VF)
3076                 return true;
3077         return false;
3078 }
3079
3080 bool bnxt_stratus_device(struct bnxt *bp)
3081 {
3082         uint16_t id = bp->pdev->id.device_id;
3083
3084         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3085             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3086             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3087                 return true;
3088         return false;
3089 }
3090
3091 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3092 {
3093         struct bnxt *bp = eth_dev->data->dev_private;
3094         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3095         int rc;
3096
3097         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3098         if (!pci_dev->mem_resource[0].addr) {
3099                 PMD_DRV_LOG(ERR,
3100                         "Cannot find PCI device base address, aborting\n");
3101                 rc = -ENODEV;
3102                 goto init_err_disable;
3103         }
3104
3105         bp->eth_dev = eth_dev;
3106         bp->pdev = pci_dev;
3107
3108         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3109         if (!bp->bar0) {
3110                 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3111                 rc = -ENOMEM;
3112                 goto init_err_release;
3113         }
3114
3115         if (!pci_dev->mem_resource[2].addr) {
3116                 PMD_DRV_LOG(ERR,
3117                             "Cannot find PCI device BAR 2 address, aborting\n");
3118                 rc = -ENODEV;
3119                 goto init_err_release;
3120         } else {
3121                 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3122         }
3123
3124         return 0;
3125
3126 init_err_release:
3127         if (bp->bar0)
3128                 bp->bar0 = NULL;
3129         if (bp->doorbell_base)
3130                 bp->doorbell_base = NULL;
3131
3132 init_err_disable:
3133
3134         return rc;
3135 }
3136
3137
3138 #define ALLOW_FUNC(x)   \
3139         { \
3140                 typeof(x) arg = (x); \
3141                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3142                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3143         }
3144 static int
3145 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3146 {
3147         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3148         char mz_name[RTE_MEMZONE_NAMESIZE];
3149         const struct rte_memzone *mz = NULL;
3150         static int version_printed;
3151         uint32_t total_alloc_len;
3152         rte_iova_t mz_phys_addr;
3153         struct bnxt *bp;
3154         int rc;
3155
3156         if (version_printed++ == 0)
3157                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3158
3159         rte_eth_copy_pci_info(eth_dev, pci_dev);
3160
3161         bp = eth_dev->data->dev_private;
3162
3163         bp->dev_stopped = 1;
3164
3165         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3166                 goto skip_init;
3167
3168         if (bnxt_vf_pciid(pci_dev->id.device_id))
3169                 bp->flags |= BNXT_FLAG_VF;
3170
3171         rc = bnxt_init_board(eth_dev);
3172         if (rc) {
3173                 PMD_DRV_LOG(ERR,
3174                         "Board initialization failed rc: %x\n", rc);
3175                 goto error;
3176         }
3177 skip_init:
3178         eth_dev->dev_ops = &bnxt_dev_ops;
3179         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3180         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3181         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3182                 return 0;
3183
3184         if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3185                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3186                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3187                          pci_dev->addr.bus, pci_dev->addr.devid,
3188                          pci_dev->addr.function, "rx_port_stats");
3189                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3190                 mz = rte_memzone_lookup(mz_name);
3191                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3192                                 sizeof(struct rx_port_stats) + 512);
3193                 if (!mz) {
3194                         mz = rte_memzone_reserve(mz_name, total_alloc_len,
3195                                         SOCKET_ID_ANY,
3196                                         RTE_MEMZONE_2MB |
3197                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3198                                         RTE_MEMZONE_IOVA_CONTIG);
3199                         if (mz == NULL)
3200                                 return -ENOMEM;
3201                 }
3202                 memset(mz->addr, 0, mz->len);
3203                 mz_phys_addr = mz->iova;
3204                 if ((unsigned long)mz->addr == mz_phys_addr) {
3205                         PMD_DRV_LOG(WARNING,
3206                                 "Memzone physical address same as virtual.\n");
3207                         PMD_DRV_LOG(WARNING,
3208                                 "Using rte_mem_virt2iova()\n");
3209                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3210                         if (mz_phys_addr == 0) {
3211                                 PMD_DRV_LOG(ERR,
3212                                 "unable to map address to physical memory\n");
3213                                 return -ENOMEM;
3214                         }
3215                 }
3216
3217                 bp->rx_mem_zone = (const void *)mz;
3218                 bp->hw_rx_port_stats = mz->addr;
3219                 bp->hw_rx_port_stats_map = mz_phys_addr;
3220
3221                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3222                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3223                          pci_dev->addr.bus, pci_dev->addr.devid,
3224                          pci_dev->addr.function, "tx_port_stats");
3225                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3226                 mz = rte_memzone_lookup(mz_name);
3227                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3228                                 sizeof(struct tx_port_stats) + 512);
3229                 if (!mz) {
3230                         mz = rte_memzone_reserve(mz_name,
3231                                         total_alloc_len,
3232                                         SOCKET_ID_ANY,
3233                                         RTE_MEMZONE_2MB |
3234                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3235                                         RTE_MEMZONE_IOVA_CONTIG);
3236                         if (mz == NULL)
3237                                 return -ENOMEM;
3238                 }
3239                 memset(mz->addr, 0, mz->len);
3240                 mz_phys_addr = mz->iova;
3241                 if ((unsigned long)mz->addr == mz_phys_addr) {
3242                         PMD_DRV_LOG(WARNING,
3243                                 "Memzone physical address same as virtual.\n");
3244                         PMD_DRV_LOG(WARNING,
3245                                 "Using rte_mem_virt2iova()\n");
3246                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3247                         if (mz_phys_addr == 0) {
3248                                 PMD_DRV_LOG(ERR,
3249                                 "unable to map address to physical memory\n");
3250                                 return -ENOMEM;
3251                         }
3252                 }
3253
3254                 bp->tx_mem_zone = (const void *)mz;
3255                 bp->hw_tx_port_stats = mz->addr;
3256                 bp->hw_tx_port_stats_map = mz_phys_addr;
3257
3258                 bp->flags |= BNXT_FLAG_PORT_STATS;
3259         }
3260
3261         rc = bnxt_alloc_hwrm_resources(bp);
3262         if (rc) {
3263                 PMD_DRV_LOG(ERR,
3264                         "hwrm resource allocation failure rc: %x\n", rc);
3265                 goto error_free;
3266         }
3267         rc = bnxt_hwrm_ver_get(bp);
3268         if (rc)
3269                 goto error_free;
3270         rc = bnxt_hwrm_queue_qportcfg(bp);
3271         if (rc) {
3272                 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3273                 goto error_free;
3274         }
3275
3276         rc = bnxt_hwrm_func_qcfg(bp);
3277         if (rc) {
3278                 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3279                 goto error_free;
3280         }
3281
3282         /* Get the MAX capabilities for this function */
3283         rc = bnxt_hwrm_func_qcaps(bp);
3284         if (rc) {
3285                 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3286                 goto error_free;
3287         }
3288         if (bp->max_tx_rings == 0) {
3289                 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3290                 rc = -EBUSY;
3291                 goto error_free;
3292         }
3293         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3294                                         ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3295         if (eth_dev->data->mac_addrs == NULL) {
3296                 PMD_DRV_LOG(ERR,
3297                         "Failed to alloc %u bytes needed to store MAC addr tbl",
3298                         ETHER_ADDR_LEN * bp->max_l2_ctx);
3299                 rc = -ENOMEM;
3300                 goto error_free;
3301         }
3302
3303         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, ETHER_ADDR_LEN)) {
3304                 PMD_DRV_LOG(ERR,
3305                             "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3306                             bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3307                             bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3308                             bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3309                 rc = -EINVAL;
3310                 goto error_free;
3311         }
3312         /* Copy the permanent MAC from the qcap response address now. */
3313         memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3314         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
3315
3316         if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3317                 /* 1 ring is for default completion ring */
3318                 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3319                 rc = -ENOSPC;
3320                 goto error_free;
3321         }
3322
3323         bp->grp_info = rte_zmalloc("bnxt_grp_info",
3324                                 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3325         if (!bp->grp_info) {
3326                 PMD_DRV_LOG(ERR,
3327                         "Failed to alloc %zu bytes to store group info table\n",
3328                         sizeof(*bp->grp_info) * bp->max_ring_grps);
3329                 rc = -ENOMEM;
3330                 goto error_free;
3331         }
3332
3333         /* Forward all requests if firmware is new enough */
3334         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3335             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3336             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3337                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3338         } else {
3339                 PMD_DRV_LOG(WARNING,
3340                         "Firmware too old for VF mailbox functionality\n");
3341                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3342         }
3343
3344         /*
3345          * The following are used for driver cleanup.  If we disallow these,
3346          * VF drivers can't clean up cleanly.
3347          */
3348         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3349         ALLOW_FUNC(HWRM_VNIC_FREE);
3350         ALLOW_FUNC(HWRM_RING_FREE);
3351         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3352         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3353         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3354         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3355         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3356         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3357         rc = bnxt_hwrm_func_driver_register(bp);
3358         if (rc) {
3359                 PMD_DRV_LOG(ERR,
3360                         "Failed to register driver");
3361                 rc = -EBUSY;
3362                 goto error_free;
3363         }
3364
3365         PMD_DRV_LOG(INFO,
3366                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3367                 pci_dev->mem_resource[0].phys_addr,
3368                 pci_dev->mem_resource[0].addr);
3369
3370         rc = bnxt_hwrm_func_reset(bp);
3371         if (rc) {
3372                 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3373                 rc = -EIO;
3374                 goto error_free;
3375         }
3376
3377         if (BNXT_PF(bp)) {
3378                 //if (bp->pf.active_vfs) {
3379                         // TODO: Deallocate VF resources?
3380                 //}
3381                 if (bp->pdev->max_vfs) {
3382                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3383                         if (rc) {
3384                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3385                                 goto error_free;
3386                         }
3387                 } else {
3388                         rc = bnxt_hwrm_allocate_pf_only(bp);
3389                         if (rc) {
3390                                 PMD_DRV_LOG(ERR,
3391                                         "Failed to allocate PF resources\n");
3392                                 goto error_free;
3393                         }
3394                 }
3395         }
3396
3397         bnxt_hwrm_port_led_qcaps(bp);
3398
3399         rc = bnxt_setup_int(bp);
3400         if (rc)
3401                 goto error_free;
3402
3403         rc = bnxt_alloc_mem(bp);
3404         if (rc)
3405                 goto error_free_int;
3406
3407         rc = bnxt_request_int(bp);
3408         if (rc)
3409                 goto error_free_int;
3410
3411         bnxt_enable_int(bp);
3412         bnxt_init_nic(bp);
3413
3414         return 0;
3415
3416 error_free_int:
3417         bnxt_disable_int(bp);
3418         bnxt_hwrm_func_buf_unrgtr(bp);
3419         bnxt_free_int(bp);
3420         bnxt_free_mem(bp);
3421 error_free:
3422         bnxt_dev_uninit(eth_dev);
3423 error:
3424         return rc;
3425 }
3426
3427 static int
3428 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3429 {
3430         struct bnxt *bp = eth_dev->data->dev_private;
3431         int rc;
3432
3433         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3434                 return -EPERM;
3435
3436         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
3437         bnxt_disable_int(bp);
3438         bnxt_free_int(bp);
3439         bnxt_free_mem(bp);
3440         if (eth_dev->data->mac_addrs != NULL) {
3441                 rte_free(eth_dev->data->mac_addrs);
3442                 eth_dev->data->mac_addrs = NULL;
3443         }
3444         if (bp->grp_info != NULL) {
3445                 rte_free(bp->grp_info);
3446                 bp->grp_info = NULL;
3447         }
3448         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3449         bnxt_free_hwrm_resources(bp);
3450
3451         if (bp->tx_mem_zone) {
3452                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3453                 bp->tx_mem_zone = NULL;
3454         }
3455
3456         if (bp->rx_mem_zone) {
3457                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3458                 bp->rx_mem_zone = NULL;
3459         }
3460
3461         if (bp->dev_stopped == 0)
3462                 bnxt_dev_close_op(eth_dev);
3463         if (bp->pf.vf_info)
3464                 rte_free(bp->pf.vf_info);
3465         eth_dev->dev_ops = NULL;
3466         eth_dev->rx_pkt_burst = NULL;
3467         eth_dev->tx_pkt_burst = NULL;
3468
3469         return rc;
3470 }
3471
3472 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3473         struct rte_pci_device *pci_dev)
3474 {
3475         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3476                 bnxt_dev_init);
3477 }
3478
3479 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3480 {
3481         return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
3482 }
3483
3484 static struct rte_pci_driver bnxt_rte_pmd = {
3485         .id_table = bnxt_pci_id_map,
3486         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3487                 RTE_PCI_DRV_INTR_LSC,
3488         .probe = bnxt_pci_probe,
3489         .remove = bnxt_pci_remove,
3490 };
3491
3492 static bool
3493 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3494 {
3495         if (strcmp(dev->device->driver->name, drv->driver.name))
3496                 return false;
3497
3498         return true;
3499 }
3500
3501 bool is_bnxt_supported(struct rte_eth_dev *dev)
3502 {
3503         return is_device_supported(dev, &bnxt_rte_pmd);
3504 }
3505
3506 RTE_INIT(bnxt_init_log);
3507 static void
3508 bnxt_init_log(void)
3509 {
3510         bnxt_logtype_driver = rte_log_register("pmd.bnxt.driver");
3511         if (bnxt_logtype_driver >= 0)
3512                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_INFO);
3513 }
3514
3515 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3516 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3517 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");