drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_cpr.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30 #include "bnxt_util.h"
  31
  32 #define DRV_MODULE_NAME         "bnxt"
  33 static const char bnxt_version[] =
  34         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  35 int bnxt_logtype_driver;
  36
  37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  38
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  43 #define BROADCOM_DEV_ID_57301 0x16c8
  44 #define BROADCOM_DEV_ID_57302 0x16c9
  45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  48 #define BROADCOM_DEV_ID_NS2 0x16cd
  49 #define BROADCOM_DEV_ID_57311 0x16ce
  50 #define BROADCOM_DEV_ID_57312 0x16cf
  51 #define BROADCOM_DEV_ID_57402 0x16d0
  52 #define BROADCOM_DEV_ID_57404 0x16d1
  53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  57 #define BROADCOM_DEV_ID_57412 0x16d6
  58 #define BROADCOM_DEV_ID_57414 0x16d7
  59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  62 #define BROADCOM_DEV_ID_57412_MF 0x16de
  63 #define BROADCOM_DEV_ID_57314 0x16df
  64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  75 #define BROADCOM_DEV_ID_57508 0x1750
  76 #define BROADCOM_DEV_ID_57504 0x1751
  77 #define BROADCOM_DEV_ID_57502 0x1752
  78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
  79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
  80 #define BROADCOM_DEV_ID_58802 0xd802
  81 #define BROADCOM_DEV_ID_58804 0xd804
  82 #define BROADCOM_DEV_ID_58808 0x16f0
  83 #define BROADCOM_DEV_ID_58802_VF 0xd800
  84
  85 static const struct rte_pci_id bnxt_pci_id_map[] = {
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  87                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  89                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 130         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 131         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
 132         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
 133         { .vendor_id = 0, /* sentinel */ },
 134 };
 135
 136 #define BNXT_ETH_RSS_SUPPORT (  \
 137         ETH_RSS_IPV4 |          \
 138         ETH_RSS_NONFRAG_IPV4_TCP |      \
 139         ETH_RSS_NONFRAG_IPV4_UDP |      \
 140         ETH_RSS_IPV6 |          \
 141         ETH_RSS_NONFRAG_IPV6_TCP |      \
 142         ETH_RSS_NONFRAG_IPV6_UDP)
 143
 144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 145                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 146                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 147                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 148                                      DEV_TX_OFFLOAD_TCP_TSO | \
 149                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 150                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 152                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 153                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 154                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 155
 156 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 157                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 158                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 159                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 160                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 161                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 162                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 163                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 164                                      DEV_RX_OFFLOAD_TCP_LRO)
 165
 166 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 167 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 168 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 169 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 170 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 171 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 172
 173 int is_bnxt_in_error(struct bnxt *bp)
 174 {
 175         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 176                 return -EIO;
 177         if (bp->flags & BNXT_FLAG_FW_RESET)
 178                 return -EBUSY;
 179
 180         return 0;
 181 }
 182
 183 /***********************/
 184
 185 /*
 186  * High level utility functions
 187  */
 188
 189 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 190 {
 191         if (!BNXT_CHIP_THOR(bp))
 192                 return 1;
 193
 194         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 195                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 196                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 197 }
 198
 199 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 200 {
 201         if (!BNXT_CHIP_THOR(bp))
 202                 return HW_HASH_INDEX_SIZE;
 203
 204         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 205 }
 206
 207 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 208 {
 209         bnxt_free_filter_mem(bp);
 210         bnxt_free_vnic_attributes(bp);
 211         bnxt_free_vnic_mem(bp);
 212
 213         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 214          * If the number of rings change across fw update,
 215          * we don't have much choice except to warn the user.
 216          */
 217         if (!reconfig) {
 218                 bnxt_free_stats(bp);
 219                 bnxt_free_tx_rings(bp);
 220                 bnxt_free_rx_rings(bp);
 221         }
 222         bnxt_free_async_cp_ring(bp);
 223 }
 224
 225 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 226 {
 227         int rc;
 228
 229         rc = bnxt_alloc_ring_grps(bp);
 230         if (rc)
 231                 goto alloc_mem_err;
 232
 233         rc = bnxt_alloc_async_ring_struct(bp);
 234         if (rc)
 235                 goto alloc_mem_err;
 236
 237         rc = bnxt_alloc_vnic_mem(bp);
 238         if (rc)
 239                 goto alloc_mem_err;
 240
 241         rc = bnxt_alloc_vnic_attributes(bp);
 242         if (rc)
 243                 goto alloc_mem_err;
 244
 245         rc = bnxt_alloc_filter_mem(bp);
 246         if (rc)
 247                 goto alloc_mem_err;
 248
 249         rc = bnxt_alloc_async_cp_ring(bp);
 250         if (rc)
 251                 goto alloc_mem_err;
 252
 253         return 0;
 254
 255 alloc_mem_err:
 256         bnxt_free_mem(bp, reconfig);
 257         return rc;
 258 }
 259
 260 static int bnxt_init_chip(struct bnxt *bp)
 261 {
 262         struct bnxt_rx_queue *rxq;
 263         struct rte_eth_link new;
 264         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 265         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 266         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 267         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 268         uint32_t intr_vector = 0;
 269         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 270         uint32_t vec = BNXT_MISC_VEC_ID;
 271         unsigned int i, j;
 272         int rc;
 273
 274         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 275                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 276                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 277                 bp->flags |= BNXT_FLAG_JUMBO;
 278         } else {
 279                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 280                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 281                 bp->flags &= ~BNXT_FLAG_JUMBO;
 282         }
 283
 284         /* THOR does not support ring groups.
 285          * But we will use the array to save RSS context IDs.
 286          */
 287         if (BNXT_CHIP_THOR(bp))
 288                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 289
 290         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 291         if (rc) {
 292                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 293                 goto err_out;
 294         }
 295
 296         rc = bnxt_alloc_hwrm_rings(bp);
 297         if (rc) {
 298                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 299                 goto err_out;
 300         }
 301
 302         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 303         if (rc) {
 304                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 305                 goto err_out;
 306         }
 307
 308         rc = bnxt_mq_rx_configure(bp);
 309         if (rc) {
 310                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 311                 goto err_out;
 312         }
 313
 314         /* VNIC configuration */
 315         for (i = 0; i < bp->nr_vnics; i++) {
 316                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 317                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 318                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 319
 320                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 321                 if (!vnic->fw_grp_ids) {
 322                         PMD_DRV_LOG(ERR,
 323                                     "Failed to alloc %d bytes for group ids\n",
 324                                     size);
 325                         rc = -ENOMEM;
 326                         goto err_out;
 327                 }
 328                 memset(vnic->fw_grp_ids, -1, size);
 329
 330                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 331                             i, vnic, vnic->fw_grp_ids);
 332
 333                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 334                 if (rc) {
 335                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 336                                 i, rc);
 337                         goto err_out;
 338                 }
 339
 340                 /* Alloc RSS context only if RSS mode is enabled */
 341                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 342                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 343
 344                         rc = 0;
 345                         for (j = 0; j < nr_ctxs; j++) {
 346                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 347                                 if (rc)
 348                                         break;
 349                         }
 350                         if (rc) {
 351                                 PMD_DRV_LOG(ERR,
 352                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 353                                   i, j, rc);
 354                                 goto err_out;
 355                         }
 356                         vnic->num_lb_ctxts = nr_ctxs;
 357                 }
 358
 359                 /*
 360                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 361                  * setting is not available at this time, it will not be
 362                  * configured correctly in the CFA.
 363                  */
 364                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 365                         vnic->vlan_strip = true;
 366                 else
 367                         vnic->vlan_strip = false;
 368
 369                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 370                 if (rc) {
 371                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 372                                 i, rc);
 373                         goto err_out;
 374                 }
 375
 376                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 377                 if (rc) {
 378                         PMD_DRV_LOG(ERR,
 379                                 "HWRM vnic %d filter failure rc: %x\n",
 380                                 i, rc);
 381                         goto err_out;
 382                 }
 383
 384                 for (j = 0; j < bp->rx_nr_rings; j++) {
 385                         rxq = bp->eth_dev->data->rx_queues[j];
 386
 387                         PMD_DRV_LOG(DEBUG,
 388                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 389                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 390
 391                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 392                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 393                 }
 394
 395                 rc = bnxt_vnic_rss_configure(bp, vnic);
 396                 if (rc) {
 397                         PMD_DRV_LOG(ERR,
 398                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 399                         goto err_out;
 400                 }
 401
 402                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 403
 404                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 405                     DEV_RX_OFFLOAD_TCP_LRO)
 406                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 407                 else
 408                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 409         }
 410         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 411         if (rc) {
 412                 PMD_DRV_LOG(ERR,
 413                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 414                 goto err_out;
 415         }
 416
 417         /* check and configure queue intr-vector mapping */
 418         if ((rte_intr_cap_multiple(intr_handle) ||
 419              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 420             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 421                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 422                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 423                 if (intr_vector > bp->rx_cp_nr_rings) {
 424                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 425                                         bp->rx_cp_nr_rings);
 426                         return -ENOTSUP;
 427                 }
 428                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 429                 if (rc)
 430                         return rc;
 431         }
 432
 433         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 434                 intr_handle->intr_vec =
 435                         rte_zmalloc("intr_vec",
 436                                     bp->eth_dev->data->nb_rx_queues *
 437                                     sizeof(int), 0);
 438                 if (intr_handle->intr_vec == NULL) {
 439                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 440                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 441                         rc = -ENOMEM;
 442                         goto err_disable;
 443                 }
 444                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 445                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 446                          intr_handle->intr_vec, intr_handle->nb_efd,
 447                         intr_handle->max_intr);
 448                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 449                      queue_id++) {
 450                         intr_handle->intr_vec[queue_id] =
 451                                                         vec + BNXT_RX_VEC_START;
 452                         if (vec < base + intr_handle->nb_efd - 1)
 453                                 vec++;
 454                 }
 455         }
 456
 457         /* enable uio/vfio intr/eventfd mapping */
 458         rc = rte_intr_enable(intr_handle);
 459         if (rc)
 460                 goto err_free;
 461
 462         rc = bnxt_get_hwrm_link_config(bp, &new);
 463         if (rc) {
 464                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 465                 goto err_free;
 466         }
 467
 468         if (!bp->link_info.link_up) {
 469                 rc = bnxt_set_hwrm_link_config(bp, true);
 470                 if (rc) {
 471                         PMD_DRV_LOG(ERR,
 472                                 "HWRM link config failure rc: %x\n", rc);
 473                         goto err_free;
 474                 }
 475         }
 476         bnxt_print_link_info(bp->eth_dev);
 477
 478         return 0;
 479
 480 err_free:
 481         rte_free(intr_handle->intr_vec);
 482 err_disable:
 483         rte_intr_efd_disable(intr_handle);
 484 err_out:
 485         /* Some of the error status returned by FW may not be from errno.h */
 486         if (rc > 0)
 487                 rc = -EIO;
 488
 489         return rc;
 490 }
 491
 492 static int bnxt_shutdown_nic(struct bnxt *bp)
 493 {
 494         bnxt_free_all_hwrm_resources(bp);
 495         bnxt_free_all_filters(bp);
 496         bnxt_free_all_vnics(bp);
 497         return 0;
 498 }
 499
 500 static int bnxt_init_nic(struct bnxt *bp)
 501 {
 502         int rc;
 503
 504         if (BNXT_HAS_RING_GRPS(bp)) {
 505                 rc = bnxt_init_ring_grps(bp);
 506                 if (rc)
 507                         return rc;
 508         }
 509
 510         bnxt_init_vnics(bp);
 511         bnxt_init_filters(bp);
 512
 513         return 0;
 514 }
 515
 516 /*
 517  * Device configuration and status function
 518  */
 519
 520 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 521                                 struct rte_eth_dev_info *dev_info)
 522 {
 523         struct bnxt *bp = eth_dev->data->dev_private;
 524         uint16_t max_vnics, i, j, vpool, vrxq;
 525         unsigned int max_rx_rings;
 526         int rc;
 527
 528         rc = is_bnxt_in_error(bp);
 529         if (rc)
 530                 return rc;
 531
 532         /* MAC Specifics */
 533         dev_info->max_mac_addrs = bp->max_l2_ctx;
 534         dev_info->max_hash_mac_addrs = 0;
 535
 536         /* PF/VF specifics */
 537         if (BNXT_PF(bp))
 538                 dev_info->max_vfs = bp->pdev->max_vfs;
 539         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 540         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 541         dev_info->max_rx_queues = max_rx_rings;
 542         dev_info->max_tx_queues = max_rx_rings;
 543         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 544         dev_info->hash_key_size = 40;
 545         max_vnics = bp->max_vnics;
 546
 547         /* Fast path specifics */
 548         dev_info->min_rx_bufsize = 1;
 549         dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
 550                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
 551
 552         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 553         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 554                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 555         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 556         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 557
 558         /* *INDENT-OFF* */
 559         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 560                 .rx_thresh = {
 561                         .pthresh = 8,
 562                         .hthresh = 8,
 563                         .wthresh = 0,
 564                 },
 565                 .rx_free_thresh = 32,
 566                 /* If no descriptors available, pkts are dropped by default */
 567                 .rx_drop_en = 1,
 568         };
 569
 570         dev_info->default_txconf = (struct rte_eth_txconf) {
 571                 .tx_thresh = {
 572                         .pthresh = 32,
 573                         .hthresh = 0,
 574                         .wthresh = 0,
 575                 },
 576                 .tx_free_thresh = 32,
 577                 .tx_rs_thresh = 32,
 578         };
 579         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 580
 581         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 582         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 583         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 584         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 585         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 586
 587         /* *INDENT-ON* */
 588
 589         /*
 590          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 591          *       need further investigation.
 592          */
 593
 594         /* VMDq resources */
 595         vpool = 64; /* ETH_64_POOLS */
 596         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 597         for (i = 0; i < 4; vpool >>= 1, i++) {
 598                 if (max_vnics > vpool) {
 599                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 600                                 if (dev_info->max_rx_queues > vrxq) {
 601                                         if (vpool > vrxq)
 602                                                 vpool = vrxq;
 603                                         goto found;
 604                                 }
 605                         }
 606                         /* Not enough resources to support VMDq */
 607                         break;
 608                 }
 609         }
 610         /* Not enough resources to support VMDq */
 611         vpool = 0;
 612         vrxq = 0;
 613 found:
 614         dev_info->max_vmdq_pools = vpool;
 615         dev_info->vmdq_queue_num = vrxq;
 616
 617         dev_info->vmdq_pool_base = 0;
 618         dev_info->vmdq_queue_base = 0;
 619
 620         return 0;
 621 }
 622
 623 /* Configure the device based on the configuration provided */
 624 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 625 {
 626         struct bnxt *bp = eth_dev->data->dev_private;
 627         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 628         int rc;
 629
 630         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 631         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 632         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 633         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 634
 635         rc = is_bnxt_in_error(bp);
 636         if (rc)
 637                 return rc;
 638
 639         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 640                 rc = bnxt_hwrm_check_vf_rings(bp);
 641                 if (rc) {
 642                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 643                         return -ENOSPC;
 644                 }
 645
 646                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 647                 if (rc) {
 648                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 649                         return -ENOSPC;
 650                 }
 651         } else {
 652                 /* legacy driver needs to get updated values */
 653                 rc = bnxt_hwrm_func_qcaps(bp);
 654                 if (rc) {
 655                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 656                         return rc;
 657                 }
 658         }
 659
 660         /* Inherit new configurations */
 661         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 662             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 663             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 664                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 665             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 666             bp->max_stat_ctx)
 667                 goto resource_error;
 668
 669         if (BNXT_HAS_RING_GRPS(bp) &&
 670             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 671                 goto resource_error;
 672
 673         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 674             bp->max_vnics < eth_dev->data->nb_rx_queues)
 675                 goto resource_error;
 676
 677         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 678         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 679
 680         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 681                 eth_dev->data->mtu =
 682                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 683                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 684                         BNXT_NUM_VLANS;
 685                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 686         }
 687         return 0;
 688
 689 resource_error:
 690         PMD_DRV_LOG(ERR,
 691                     "Insufficient resources to support requested config\n");
 692         PMD_DRV_LOG(ERR,
 693                     "Num Queues Requested: Tx %d, Rx %d\n",
 694                     eth_dev->data->nb_tx_queues,
 695                     eth_dev->data->nb_rx_queues);
 696         PMD_DRV_LOG(ERR,
 697                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 698                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 699                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 700         return -ENOSPC;
 701 }
 702
 703 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 704 {
 705         struct rte_eth_link *link = &eth_dev->data->dev_link;
 706
 707         if (link->link_status)
 708                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 709                         eth_dev->data->port_id,
 710                         (uint32_t)link->link_speed,
 711                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 712                         ("full-duplex") : ("half-duplex\n"));
 713         else
 714                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 715                         eth_dev->data->port_id);
 716 }
 717
 718 /*
 719  * Determine whether the current configuration requires support for scattered
 720  * receive; return 1 if scattered receive is required and 0 if not.
 721  */
 722 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 723 {
 724         uint16_t buf_size;
 725         int i;
 726
 727         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 728                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 729
 730                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 731                                       RTE_PKTMBUF_HEADROOM);
 732                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 733                         return 1;
 734         }
 735         return 0;
 736 }
 737
 738 static eth_rx_burst_t
 739 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 740 {
 741 #ifdef RTE_ARCH_X86
 742         /*
 743          * Vector mode receive can be enabled only if scatter rx is not
 744          * in use and rx offloads are limited to VLAN stripping and
 745          * CRC stripping.
 746          */
 747         if (!eth_dev->data->scattered_rx &&
 748             !(eth_dev->data->dev_conf.rxmode.offloads &
 749               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 750                 DEV_RX_OFFLOAD_KEEP_CRC |
 751                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 752                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 753                 DEV_RX_OFFLOAD_UDP_CKSUM |
 754                 DEV_RX_OFFLOAD_TCP_CKSUM |
 755                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 756                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 757                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 758                             eth_dev->data->port_id);
 759                 return bnxt_recv_pkts_vec;
 760         }
 761         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 762                     eth_dev->data->port_id);
 763         PMD_DRV_LOG(INFO,
 764                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 765                     eth_dev->data->port_id,
 766                     eth_dev->data->scattered_rx,
 767                     eth_dev->data->dev_conf.rxmode.offloads);
 768 #endif
 769         return bnxt_recv_pkts;
 770 }
 771
 772 static eth_tx_burst_t
 773 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 774 {
 775 #ifdef RTE_ARCH_X86
 776         /*
 777          * Vector mode transmit can be enabled only if not using scatter rx
 778          * or tx offloads.
 779          */
 780         if (!eth_dev->data->scattered_rx &&
 781             !eth_dev->data->dev_conf.txmode.offloads) {
 782                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 783                             eth_dev->data->port_id);
 784                 return bnxt_xmit_pkts_vec;
 785         }
 786         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 787                     eth_dev->data->port_id);
 788         PMD_DRV_LOG(INFO,
 789                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 790                     eth_dev->data->port_id,
 791                     eth_dev->data->scattered_rx,
 792                     eth_dev->data->dev_conf.txmode.offloads);
 793 #endif
 794         return bnxt_xmit_pkts;
 795 }
 796
 797 static int bnxt_handle_if_change_status(struct bnxt *bp)
 798 {
 799         int rc;
 800
 801         /* Since fw has undergone a reset and lost all contexts,
 802          * set fatal flag to not issue hwrm during cleanup
 803          */
 804         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 805         bnxt_uninit_resources(bp, true);
 806
 807         /* clear fatal flag so that re-init happens */
 808         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 809         rc = bnxt_init_resources(bp, true);
 810
 811         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 812
 813         return rc;
 814 }
 815
 816 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 817 {
 818         struct bnxt *bp = eth_dev->data->dev_private;
 819         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 820         int vlan_mask = 0;
 821         int rc;
 822
 823         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 824                 PMD_DRV_LOG(ERR,
 825                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 826                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 827         }
 828
 829         rc = bnxt_hwrm_if_change(bp, 1);
 830         if (!rc) {
 831                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 832                         rc = bnxt_handle_if_change_status(bp);
 833                         if (rc)
 834                                 return rc;
 835                 }
 836         }
 837
 838         rc = bnxt_init_chip(bp);
 839         if (rc)
 840                 goto error;
 841
 842         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 843
 844         bnxt_link_update_op(eth_dev, 1);
 845
 846         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 847                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 848         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 849                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 850         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 851         if (rc)
 852                 goto error;
 853
 854         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 855         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 856
 857         bnxt_enable_int(bp);
 858         bp->flags |= BNXT_FLAG_INIT_DONE;
 859         eth_dev->data->dev_started = 1;
 860         bp->dev_stopped = 0;
 861         return 0;
 862
 863 error:
 864         bnxt_hwrm_if_change(bp, 0);
 865         bnxt_shutdown_nic(bp);
 866         bnxt_free_tx_mbufs(bp);
 867         bnxt_free_rx_mbufs(bp);
 868         return rc;
 869 }
 870
 871 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 872 {
 873         struct bnxt *bp = eth_dev->data->dev_private;
 874         int rc = 0;
 875
 876         if (!bp->link_info.link_up)
 877                 rc = bnxt_set_hwrm_link_config(bp, true);
 878         if (!rc)
 879                 eth_dev->data->dev_link.link_status = 1;
 880
 881         bnxt_print_link_info(eth_dev);
 882         return 0;
 883 }
 884
 885 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 886 {
 887         struct bnxt *bp = eth_dev->data->dev_private;
 888
 889         eth_dev->data->dev_link.link_status = 0;
 890         bnxt_set_hwrm_link_config(bp, false);
 891         bp->link_info.link_up = 0;
 892
 893         return 0;
 894 }
 895
 896 /* Unload the driver, release resources */
 897 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 898 {
 899         struct bnxt *bp = eth_dev->data->dev_private;
 900         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 901         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 902
 903         eth_dev->data->dev_started = 0;
 904         /* Prevent crashes when queues are still in use */
 905         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 906         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 907
 908         bnxt_disable_int(bp);
 909
 910         /* disable uio/vfio intr/eventfd mapping */
 911         rte_intr_disable(intr_handle);
 912
 913         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 914         if (bp->eth_dev->data->dev_started) {
 915                 /* TBD: STOP HW queues DMA */
 916                 eth_dev->data->dev_link.link_status = 0;
 917         }
 918         bnxt_set_hwrm_link_config(bp, false);
 919
 920         /* Clean queue intr-vector mapping */
 921         rte_intr_efd_disable(intr_handle);
 922         if (intr_handle->intr_vec != NULL) {
 923                 rte_free(intr_handle->intr_vec);
 924                 intr_handle->intr_vec = NULL;
 925         }
 926
 927         bnxt_hwrm_port_clr_stats(bp);
 928         bnxt_free_tx_mbufs(bp);
 929         bnxt_free_rx_mbufs(bp);
 930         bnxt_shutdown_nic(bp);
 931         bnxt_hwrm_if_change(bp, 0);
 932         bp->dev_stopped = 1;
 933 }
 934
 935 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 936 {
 937         struct bnxt *bp = eth_dev->data->dev_private;
 938
 939         if (bp->dev_stopped == 0)
 940                 bnxt_dev_stop_op(eth_dev);
 941
 942         if (eth_dev->data->mac_addrs != NULL) {
 943                 rte_free(eth_dev->data->mac_addrs);
 944                 eth_dev->data->mac_addrs = NULL;
 945         }
 946         if (bp->grp_info != NULL) {
 947                 rte_free(bp->grp_info);
 948                 bp->grp_info = NULL;
 949         }
 950
 951         bnxt_dev_uninit(eth_dev);
 952 }
 953
 954 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 955                                     uint32_t index)
 956 {
 957         struct bnxt *bp = eth_dev->data->dev_private;
 958         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 959         struct bnxt_vnic_info *vnic;
 960         struct bnxt_filter_info *filter, *temp_filter;
 961         uint32_t i;
 962
 963         if (is_bnxt_in_error(bp))
 964                 return;
 965
 966         /*
 967          * Loop through all VNICs from the specified filter flow pools to
 968          * remove the corresponding MAC addr filter
 969          */
 970         for (i = 0; i < bp->nr_vnics; i++) {
 971                 if (!(pool_mask & (1ULL << i)))
 972                         continue;
 973
 974                 vnic = &bp->vnic_info[i];
 975                 filter = STAILQ_FIRST(&vnic->filter);
 976                 while (filter) {
 977                         temp_filter = STAILQ_NEXT(filter, next);
 978                         if (filter->mac_index == index) {
 979                                 STAILQ_REMOVE(&vnic->filter, filter,
 980                                                 bnxt_filter_info, next);
 981                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 982                                 filter->mac_index = INVALID_MAC_INDEX;
 983                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 984                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 985                                                    filter, next);
 986                         }
 987                         filter = temp_filter;
 988                 }
 989         }
 990 }
 991
 992 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 993                                 struct rte_ether_addr *mac_addr,
 994                                 uint32_t index, uint32_t pool)
 995 {
 996         struct bnxt *bp = eth_dev->data->dev_private;
 997         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
 998         struct bnxt_filter_info *filter;
 999         int rc = 0;
1000
1001         rc = is_bnxt_in_error(bp);
1002         if (rc)
1003                 return rc;
1004
1005         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1006                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1007                 return -ENOTSUP;
1008         }
1009
1010         if (!vnic) {
1011                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1012                 return -EINVAL;
1013         }
1014         /* Attach requested MAC address to the new l2_filter */
1015         STAILQ_FOREACH(filter, &vnic->filter, next) {
1016                 if (filter->mac_index == index) {
1017                         PMD_DRV_LOG(ERR,
1018                                 "MAC addr already existed for pool %d\n", pool);
1019                         return 0;
1020                 }
1021         }
1022         filter = bnxt_alloc_filter(bp);
1023         if (!filter) {
1024                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1025                 return -ENODEV;
1026         }
1027
1028         filter->mac_index = index;
1029         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1030
1031         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1032         if (!rc) {
1033                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1034         } else {
1035                 filter->mac_index = INVALID_MAC_INDEX;
1036                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1037                 bnxt_free_filter(bp, filter);
1038         }
1039
1040         return rc;
1041 }
1042
1043 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1044 {
1045         int rc = 0;
1046         struct bnxt *bp = eth_dev->data->dev_private;
1047         struct rte_eth_link new;
1048         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1049
1050         rc = is_bnxt_in_error(bp);
1051         if (rc)
1052                 return rc;
1053
1054         memset(&new, 0, sizeof(new));
1055         do {
1056                 /* Retrieve link info from hardware */
1057                 rc = bnxt_get_hwrm_link_config(bp, &new);
1058                 if (rc) {
1059                         new.link_speed = ETH_LINK_SPEED_100M;
1060                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1061                         PMD_DRV_LOG(ERR,
1062                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1063                         goto out;
1064                 }
1065
1066                 if (!wait_to_complete || new.link_status)
1067                         break;
1068
1069                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1070         } while (cnt--);
1071
1072 out:
1073         /* Timed out or success */
1074         if (new.link_status != eth_dev->data->dev_link.link_status ||
1075         new.link_speed != eth_dev->data->dev_link.link_speed) {
1076                 memcpy(&eth_dev->data->dev_link, &new,
1077                         sizeof(struct rte_eth_link));
1078
1079                 _rte_eth_dev_callback_process(eth_dev,
1080                                               RTE_ETH_EVENT_INTR_LSC,
1081                                               NULL);
1082
1083                 bnxt_print_link_info(eth_dev);
1084         }
1085
1086         return rc;
1087 }
1088
1089 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1090 {
1091         struct bnxt *bp = eth_dev->data->dev_private;
1092         struct bnxt_vnic_info *vnic;
1093         uint32_t old_flags;
1094         int rc;
1095
1096         rc = is_bnxt_in_error(bp);
1097         if (rc)
1098                 return rc;
1099
1100         if (bp->vnic_info == NULL)
1101                 return 0;
1102
1103         vnic = &bp->vnic_info[0];
1104
1105         old_flags = vnic->flags;
1106         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1107         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1108         if (rc != 0)
1109                 vnic->flags = old_flags;
1110
1111         return rc;
1112 }
1113
1114 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1115 {
1116         struct bnxt *bp = eth_dev->data->dev_private;
1117         struct bnxt_vnic_info *vnic;
1118         uint32_t old_flags;
1119         int rc;
1120
1121         rc = is_bnxt_in_error(bp);
1122         if (rc)
1123                 return rc;
1124
1125         if (bp->vnic_info == NULL)
1126                 return 0;
1127
1128         vnic = &bp->vnic_info[0];
1129
1130         old_flags = vnic->flags;
1131         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1132         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1133         if (rc != 0)
1134                 vnic->flags = old_flags;
1135
1136         return rc;
1137 }
1138
1139 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1140 {
1141         struct bnxt *bp = eth_dev->data->dev_private;
1142         struct bnxt_vnic_info *vnic;
1143         uint32_t old_flags;
1144         int rc;
1145
1146         rc = is_bnxt_in_error(bp);
1147         if (rc)
1148                 return rc;
1149
1150         if (bp->vnic_info == NULL)
1151                 return 0;
1152
1153         vnic = &bp->vnic_info[0];
1154
1155         old_flags = vnic->flags;
1156         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1157         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1158         if (rc != 0)
1159                 vnic->flags = old_flags;
1160
1161         return rc;
1162 }
1163
1164 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1165 {
1166         struct bnxt *bp = eth_dev->data->dev_private;
1167         struct bnxt_vnic_info *vnic;
1168         uint32_t old_flags;
1169         int rc;
1170
1171         rc = is_bnxt_in_error(bp);
1172         if (rc)
1173                 return rc;
1174
1175         if (bp->vnic_info == NULL)
1176                 return 0;
1177
1178         vnic = &bp->vnic_info[0];
1179
1180         old_flags = vnic->flags;
1181         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1182         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1183         if (rc != 0)
1184                 vnic->flags = old_flags;
1185
1186         return rc;
1187 }
1188
1189 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1190 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1191 {
1192         if (qid >= bp->rx_nr_rings)
1193                 return NULL;
1194
1195         return bp->eth_dev->data->rx_queues[qid];
1196 }
1197
1198 /* Return rxq corresponding to a given rss table ring/group ID. */
1199 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1200 {
1201         struct bnxt_rx_queue *rxq;
1202         unsigned int i;
1203
1204         if (!BNXT_HAS_RING_GRPS(bp)) {
1205                 for (i = 0; i < bp->rx_nr_rings; i++) {
1206                         rxq = bp->eth_dev->data->rx_queues[i];
1207                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1208                                 return rxq->index;
1209                 }
1210         } else {
1211                 for (i = 0; i < bp->rx_nr_rings; i++) {
1212                         if (bp->grp_info[i].fw_grp_id == fwr)
1213                                 return i;
1214                 }
1215         }
1216
1217         return INVALID_HW_RING_ID;
1218 }
1219
1220 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1221                             struct rte_eth_rss_reta_entry64 *reta_conf,
1222                             uint16_t reta_size)
1223 {
1224         struct bnxt *bp = eth_dev->data->dev_private;
1225         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1226         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1227         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1228         uint16_t idx, sft;
1229         int i, rc;
1230
1231         rc = is_bnxt_in_error(bp);
1232         if (rc)
1233                 return rc;
1234
1235         if (!vnic->rss_table)
1236                 return -EINVAL;
1237
1238         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1239                 return -EINVAL;
1240
1241         if (reta_size != tbl_size) {
1242                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1243                         "(%d) must equal the size supported by the hardware "
1244                         "(%d)\n", reta_size, tbl_size);
1245                 return -EINVAL;
1246         }
1247
1248         for (i = 0; i < reta_size; i++) {
1249                 struct bnxt_rx_queue *rxq;
1250
1251                 idx = i / RTE_RETA_GROUP_SIZE;
1252                 sft = i % RTE_RETA_GROUP_SIZE;
1253
1254                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1255                         continue;
1256
1257                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1258                 if (!rxq) {
1259                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1260                         return -EINVAL;
1261                 }
1262
1263                 if (BNXT_CHIP_THOR(bp)) {
1264                         vnic->rss_table[i * 2] =
1265                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1266                         vnic->rss_table[i * 2 + 1] =
1267                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1268                 } else {
1269                         vnic->rss_table[i] =
1270                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1271                 }
1272
1273                 vnic->rss_table[i] =
1274                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1275         }
1276
1277         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1278         return 0;
1279 }
1280
1281 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1282                               struct rte_eth_rss_reta_entry64 *reta_conf,
1283                               uint16_t reta_size)
1284 {
1285         struct bnxt *bp = eth_dev->data->dev_private;
1286         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1287         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1288         uint16_t idx, sft, i;
1289         int rc;
1290
1291         rc = is_bnxt_in_error(bp);
1292         if (rc)
1293                 return rc;
1294
1295         /* Retrieve from the default VNIC */
1296         if (!vnic)
1297                 return -EINVAL;
1298         if (!vnic->rss_table)
1299                 return -EINVAL;
1300
1301         if (reta_size != tbl_size) {
1302                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1303                         "(%d) must equal the size supported by the hardware "
1304                         "(%d)\n", reta_size, tbl_size);
1305                 return -EINVAL;
1306         }
1307
1308         for (idx = 0, i = 0; i < reta_size; i++) {
1309                 idx = i / RTE_RETA_GROUP_SIZE;
1310                 sft = i % RTE_RETA_GROUP_SIZE;
1311
1312                 if (reta_conf[idx].mask & (1ULL << sft)) {
1313                         uint16_t qid;
1314
1315                         if (BNXT_CHIP_THOR(bp))
1316                                 qid = bnxt_rss_to_qid(bp,
1317                                                       vnic->rss_table[i * 2]);
1318                         else
1319                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1320
1321                         if (qid == INVALID_HW_RING_ID) {
1322                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1323                                 return -EINVAL;
1324                         }
1325                         reta_conf[idx].reta[sft] = qid;
1326                 }
1327         }
1328
1329         return 0;
1330 }
1331
1332 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1333                                    struct rte_eth_rss_conf *rss_conf)
1334 {
1335         struct bnxt *bp = eth_dev->data->dev_private;
1336         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1337         struct bnxt_vnic_info *vnic;
1338         uint16_t hash_type = 0;
1339         unsigned int i;
1340         int rc;
1341
1342         rc = is_bnxt_in_error(bp);
1343         if (rc)
1344                 return rc;
1345
1346         /*
1347          * If RSS enablement were different than dev_configure,
1348          * then return -EINVAL
1349          */
1350         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1351                 if (!rss_conf->rss_hf)
1352                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1353         } else {
1354                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1355                         return -EINVAL;
1356         }
1357
1358         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1359         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1360
1361         if (rss_conf->rss_hf & ETH_RSS_IPV4)
1362                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1363         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1364                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1365         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1366                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1367         if (rss_conf->rss_hf & ETH_RSS_IPV6)
1368                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1369         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1370                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1371         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1372                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1373
1374         /* Update the RSS VNIC(s) */
1375         for (i = 0; i < bp->nr_vnics; i++) {
1376                 vnic = &bp->vnic_info[i];
1377                 vnic->hash_type = hash_type;
1378
1379                 /*
1380                  * Use the supplied key if the key length is
1381                  * acceptable and the rss_key is not NULL
1382                  */
1383                 if (rss_conf->rss_key &&
1384                     rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1385                         memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1386                                rss_conf->rss_key_len);
1387
1388                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1389         }
1390         return 0;
1391 }
1392
1393 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1394                                      struct rte_eth_rss_conf *rss_conf)
1395 {
1396         struct bnxt *bp = eth_dev->data->dev_private;
1397         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1398         int len, rc;
1399         uint32_t hash_types;
1400
1401         rc = is_bnxt_in_error(bp);
1402         if (rc)
1403                 return rc;
1404
1405         /* RSS configuration is the same for all VNICs */
1406         if (vnic && vnic->rss_hash_key) {
1407                 if (rss_conf->rss_key) {
1408                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1409                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1410                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1411                 }
1412
1413                 hash_types = vnic->hash_type;
1414                 rss_conf->rss_hf = 0;
1415                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1416                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1417                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1418                 }
1419                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1420                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1421                         hash_types &=
1422                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1423                 }
1424                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1425                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1426                         hash_types &=
1427                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1428                 }
1429                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1430                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1431                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1432                 }
1433                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1434                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1435                         hash_types &=
1436                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1437                 }
1438                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1439                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1440                         hash_types &=
1441                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1442                 }
1443                 if (hash_types) {
1444                         PMD_DRV_LOG(ERR,
1445                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1446                                 vnic->hash_type);
1447                         return -ENOTSUP;
1448                 }
1449         } else {
1450                 rss_conf->rss_hf = 0;
1451         }
1452         return 0;
1453 }
1454
1455 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1456                                struct rte_eth_fc_conf *fc_conf)
1457 {
1458         struct bnxt *bp = dev->data->dev_private;
1459         struct rte_eth_link link_info;
1460         int rc;
1461
1462         rc = is_bnxt_in_error(bp);
1463         if (rc)
1464                 return rc;
1465
1466         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1467         if (rc)
1468                 return rc;
1469
1470         memset(fc_conf, 0, sizeof(*fc_conf));
1471         if (bp->link_info.auto_pause)
1472                 fc_conf->autoneg = 1;
1473         switch (bp->link_info.pause) {
1474         case 0:
1475                 fc_conf->mode = RTE_FC_NONE;
1476                 break;
1477         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1478                 fc_conf->mode = RTE_FC_TX_PAUSE;
1479                 break;
1480         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1481                 fc_conf->mode = RTE_FC_RX_PAUSE;
1482                 break;
1483         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1484                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1485                 fc_conf->mode = RTE_FC_FULL;
1486                 break;
1487         }
1488         return 0;
1489 }
1490
1491 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1492                                struct rte_eth_fc_conf *fc_conf)
1493 {
1494         struct bnxt *bp = dev->data->dev_private;
1495         int rc;
1496
1497         rc = is_bnxt_in_error(bp);
1498         if (rc)
1499                 return rc;
1500
1501         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1502                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1503                 return -ENOTSUP;
1504         }
1505
1506         switch (fc_conf->mode) {
1507         case RTE_FC_NONE:
1508                 bp->link_info.auto_pause = 0;
1509                 bp->link_info.force_pause = 0;
1510                 break;
1511         case RTE_FC_RX_PAUSE:
1512                 if (fc_conf->autoneg) {
1513                         bp->link_info.auto_pause =
1514                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1515                         bp->link_info.force_pause = 0;
1516                 } else {
1517                         bp->link_info.auto_pause = 0;
1518                         bp->link_info.force_pause =
1519                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1520                 }
1521                 break;
1522         case RTE_FC_TX_PAUSE:
1523                 if (fc_conf->autoneg) {
1524                         bp->link_info.auto_pause =
1525                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1526                         bp->link_info.force_pause = 0;
1527                 } else {
1528                         bp->link_info.auto_pause = 0;
1529                         bp->link_info.force_pause =
1530                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1531                 }
1532                 break;
1533         case RTE_FC_FULL:
1534                 if (fc_conf->autoneg) {
1535                         bp->link_info.auto_pause =
1536                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1537                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1538                         bp->link_info.force_pause = 0;
1539                 } else {
1540                         bp->link_info.auto_pause = 0;
1541                         bp->link_info.force_pause =
1542                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1543                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1544                 }
1545                 break;
1546         }
1547         return bnxt_set_hwrm_link_config(bp, true);
1548 }
1549
1550 /* Add UDP tunneling port */
1551 static int
1552 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1553                          struct rte_eth_udp_tunnel *udp_tunnel)
1554 {
1555         struct bnxt *bp = eth_dev->data->dev_private;
1556         uint16_t tunnel_type = 0;
1557         int rc = 0;
1558
1559         rc = is_bnxt_in_error(bp);
1560         if (rc)
1561                 return rc;
1562
1563         switch (udp_tunnel->prot_type) {
1564         case RTE_TUNNEL_TYPE_VXLAN:
1565                 if (bp->vxlan_port_cnt) {
1566                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1567                                 udp_tunnel->udp_port);
1568                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1569                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1570                                 return -ENOSPC;
1571                         }
1572                         bp->vxlan_port_cnt++;
1573                         return 0;
1574                 }
1575                 tunnel_type =
1576                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1577                 bp->vxlan_port_cnt++;
1578                 break;
1579         case RTE_TUNNEL_TYPE_GENEVE:
1580                 if (bp->geneve_port_cnt) {
1581                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1582                                 udp_tunnel->udp_port);
1583                         if (bp->geneve_port != udp_tunnel->udp_port) {
1584                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1585                                 return -ENOSPC;
1586                         }
1587                         bp->geneve_port_cnt++;
1588                         return 0;
1589                 }
1590                 tunnel_type =
1591                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1592                 bp->geneve_port_cnt++;
1593                 break;
1594         default:
1595                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1596                 return -ENOTSUP;
1597         }
1598         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1599                                              tunnel_type);
1600         return rc;
1601 }
1602
1603 static int
1604 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1605                          struct rte_eth_udp_tunnel *udp_tunnel)
1606 {
1607         struct bnxt *bp = eth_dev->data->dev_private;
1608         uint16_t tunnel_type = 0;
1609         uint16_t port = 0;
1610         int rc = 0;
1611
1612         rc = is_bnxt_in_error(bp);
1613         if (rc)
1614                 return rc;
1615
1616         switch (udp_tunnel->prot_type) {
1617         case RTE_TUNNEL_TYPE_VXLAN:
1618                 if (!bp->vxlan_port_cnt) {
1619                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1620                         return -EINVAL;
1621                 }
1622                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1623                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1624                                 udp_tunnel->udp_port, bp->vxlan_port);
1625                         return -EINVAL;
1626                 }
1627                 if (--bp->vxlan_port_cnt)
1628                         return 0;
1629
1630                 tunnel_type =
1631                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1632                 port = bp->vxlan_fw_dst_port_id;
1633                 break;
1634         case RTE_TUNNEL_TYPE_GENEVE:
1635                 if (!bp->geneve_port_cnt) {
1636                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1637                         return -EINVAL;
1638                 }
1639                 if (bp->geneve_port != udp_tunnel->udp_port) {
1640                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1641                                 udp_tunnel->udp_port, bp->geneve_port);
1642                         return -EINVAL;
1643                 }
1644                 if (--bp->geneve_port_cnt)
1645                         return 0;
1646
1647                 tunnel_type =
1648                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1649                 port = bp->geneve_fw_dst_port_id;
1650                 break;
1651         default:
1652                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1653                 return -ENOTSUP;
1654         }
1655
1656         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1657         if (!rc) {
1658                 if (tunnel_type ==
1659                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1660                         bp->vxlan_port = 0;
1661                 if (tunnel_type ==
1662                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1663                         bp->geneve_port = 0;
1664         }
1665         return rc;
1666 }
1667
1668 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1669 {
1670         struct bnxt_filter_info *filter;
1671         struct bnxt_vnic_info *vnic;
1672         int rc = 0;
1673         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1674
1675         /* if VLAN exists && VLAN matches vlan_id
1676          *      remove the MAC+VLAN filter
1677          *      add a new MAC only filter
1678          * else
1679          *      VLAN filter doesn't exist, just skip and continue
1680          */
1681         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1682         filter = STAILQ_FIRST(&vnic->filter);
1683         while (filter) {
1684                 /* Search for this matching MAC+VLAN filter */
1685                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1686                     !memcmp(filter->l2_addr,
1687                             bp->mac_addr,
1688                             RTE_ETHER_ADDR_LEN)) {
1689                         /* Delete the filter */
1690                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1691                         if (rc)
1692                                 return rc;
1693                         STAILQ_REMOVE(&vnic->filter, filter,
1694                                       bnxt_filter_info, next);
1695                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1696
1697                         PMD_DRV_LOG(INFO,
1698                                     "Del Vlan filter for %d\n",
1699                                     vlan_id);
1700                         return rc;
1701                 }
1702                 filter = STAILQ_NEXT(filter, next);
1703         }
1704         return -ENOENT;
1705 }
1706
1707 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1708 {
1709         struct bnxt_filter_info *filter;
1710         struct bnxt_vnic_info *vnic;
1711         int rc = 0;
1712         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1713                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1714         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1715
1716         /* Implementation notes on the use of VNIC in this command:
1717          *
1718          * By default, these filters belong to default vnic for the function.
1719          * Once these filters are set up, only destination VNIC can be modified.
1720          * If the destination VNIC is not specified in this command,
1721          * then the HWRM shall only create an l2 context id.
1722          */
1723
1724         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1725         filter = STAILQ_FIRST(&vnic->filter);
1726         /* Check if the VLAN has already been added */
1727         while (filter) {
1728                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1729                     !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1730                         return -EEXIST;
1731
1732                 filter = STAILQ_NEXT(filter, next);
1733         }
1734
1735         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1736          * command to create MAC+VLAN filter with the right flags, enables set.
1737          */
1738         filter = bnxt_alloc_filter(bp);
1739         if (!filter) {
1740                 PMD_DRV_LOG(ERR,
1741                             "MAC/VLAN filter alloc failed\n");
1742                 return -ENOMEM;
1743         }
1744         /* MAC + VLAN ID filter */
1745         filter->l2_ivlan = vlan_id;
1746         filter->l2_ivlan_mask = 0x0FFF;
1747         filter->enables |= en;
1748         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1749         if (rc) {
1750                 /* Free the newly allocated filter as we were
1751                  * not able to create the filter in hardware.
1752                  */
1753                 filter->fw_l2_filter_id = UINT64_MAX;
1754                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1755                 return rc;
1756         }
1757
1758         /* Add this new filter to the list */
1759         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1760         PMD_DRV_LOG(INFO,
1761                     "Added Vlan filter for %d\n", vlan_id);
1762         return rc;
1763 }
1764
1765 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1766                 uint16_t vlan_id, int on)
1767 {
1768         struct bnxt *bp = eth_dev->data->dev_private;
1769         int rc;
1770
1771         rc = is_bnxt_in_error(bp);
1772         if (rc)
1773                 return rc;
1774
1775         /* These operations apply to ALL existing MAC/VLAN filters */
1776         if (on)
1777                 return bnxt_add_vlan_filter(bp, vlan_id);
1778         else
1779                 return bnxt_del_vlan_filter(bp, vlan_id);
1780 }
1781
1782 static int
1783 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1784 {
1785         struct bnxt *bp = dev->data->dev_private;
1786         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1787         unsigned int i;
1788         int rc;
1789
1790         rc = is_bnxt_in_error(bp);
1791         if (rc)
1792                 return rc;
1793
1794         if (mask & ETH_VLAN_FILTER_MASK) {
1795                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1796                         /* Remove any VLAN filters programmed */
1797                         for (i = 0; i < 4095; i++)
1798                                 bnxt_del_vlan_filter(bp, i);
1799                 }
1800                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1801                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1802         }
1803
1804         if (mask & ETH_VLAN_STRIP_MASK) {
1805                 /* Enable or disable VLAN stripping */
1806                 for (i = 0; i < bp->nr_vnics; i++) {
1807                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1808                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1809                                 vnic->vlan_strip = true;
1810                         else
1811                                 vnic->vlan_strip = false;
1812                         bnxt_hwrm_vnic_cfg(bp, vnic);
1813                 }
1814                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1815                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1816         }
1817
1818         if (mask & ETH_VLAN_EXTEND_MASK)
1819                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1820
1821         return 0;
1822 }
1823
1824 static int
1825 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1826                         struct rte_ether_addr *addr)
1827 {
1828         struct bnxt *bp = dev->data->dev_private;
1829         /* Default Filter is tied to VNIC 0 */
1830         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1831         struct bnxt_filter_info *filter;
1832         int rc;
1833
1834         rc = is_bnxt_in_error(bp);
1835         if (rc)
1836                 return rc;
1837
1838         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1839                 return -EPERM;
1840
1841         if (rte_is_zero_ether_addr(addr))
1842                 return -EINVAL;
1843
1844         STAILQ_FOREACH(filter, &vnic->filter, next) {
1845                 /* Default Filter is at Index 0 */
1846                 if (filter->mac_index != 0)
1847                         continue;
1848
1849                 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1850                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1851                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1852                 filter->enables |=
1853                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1854                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1855
1856                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1857                 if (rc)
1858                         return rc;
1859
1860                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1861                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1862                 return 0;
1863         }
1864
1865         return 0;
1866 }
1867
1868 static int
1869 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1870                           struct rte_ether_addr *mc_addr_set,
1871                           uint32_t nb_mc_addr)
1872 {
1873         struct bnxt *bp = eth_dev->data->dev_private;
1874         char *mc_addr_list = (char *)mc_addr_set;
1875         struct bnxt_vnic_info *vnic;
1876         uint32_t off = 0, i = 0;
1877         int rc;
1878
1879         rc = is_bnxt_in_error(bp);
1880         if (rc)
1881                 return rc;
1882
1883         vnic = &bp->vnic_info[0];
1884
1885         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1886                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1887                 goto allmulti;
1888         }
1889
1890         /* TODO Check for Duplicate mcast addresses */
1891         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1892         for (i = 0; i < nb_mc_addr; i++) {
1893                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1894                         RTE_ETHER_ADDR_LEN);
1895                 off += RTE_ETHER_ADDR_LEN;
1896         }
1897
1898         vnic->mc_addr_cnt = i;
1899
1900 allmulti:
1901         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1902 }
1903
1904 static int
1905 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1906 {
1907         struct bnxt *bp = dev->data->dev_private;
1908         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1909         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1910         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1911         int ret;
1912
1913         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1914                         fw_major, fw_minor, fw_updt);
1915
1916         ret += 1; /* add the size of '\0' */
1917         if (fw_size < (uint32_t)ret)
1918                 return ret;
1919         else
1920                 return 0;
1921 }
1922
1923 static void
1924 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1925         struct rte_eth_rxq_info *qinfo)
1926 {
1927         struct bnxt_rx_queue *rxq;
1928
1929         rxq = dev->data->rx_queues[queue_id];
1930
1931         qinfo->mp = rxq->mb_pool;
1932         qinfo->scattered_rx = dev->data->scattered_rx;
1933         qinfo->nb_desc = rxq->nb_rx_desc;
1934
1935         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1936         qinfo->conf.rx_drop_en = 0;
1937         qinfo->conf.rx_deferred_start = 0;
1938 }
1939
1940 static void
1941 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1942         struct rte_eth_txq_info *qinfo)
1943 {
1944         struct bnxt_tx_queue *txq;
1945
1946         txq = dev->data->tx_queues[queue_id];
1947
1948         qinfo->nb_desc = txq->nb_tx_desc;
1949
1950         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1951         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1952         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1953
1954         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1955         qinfo->conf.tx_rs_thresh = 0;
1956         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1957 }
1958
1959 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1960 {
1961         struct bnxt *bp = eth_dev->data->dev_private;
1962         struct rte_eth_dev_info dev_info;
1963         uint32_t new_pkt_size;
1964         uint32_t rc = 0;
1965         uint32_t i;
1966
1967         rc = is_bnxt_in_error(bp);
1968         if (rc)
1969                 return rc;
1970
1971         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1972                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1973
1974         rc = bnxt_dev_info_get_op(eth_dev, &dev_info);
1975         if (rc != 0) {
1976                 PMD_DRV_LOG(ERR, "Error during getting ethernet device info\n");
1977                 return rc;
1978         }
1979
1980         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1981                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1982                         RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1983                 return -EINVAL;
1984         }
1985
1986 #ifdef RTE_ARCH_X86
1987         /*
1988          * If vector-mode tx/rx is active, disallow any MTU change that would
1989          * require scattered receive support.
1990          */
1991         if (eth_dev->data->dev_started &&
1992             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1993              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1994             (new_pkt_size >
1995              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1996                 PMD_DRV_LOG(ERR,
1997                             "MTU change would require scattered rx support. ");
1998                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1999                 return -EINVAL;
2000         }
2001 #endif
2002
2003         if (new_mtu > RTE_ETHER_MTU) {
2004                 bp->flags |= BNXT_FLAG_JUMBO;
2005                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2006                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2007         } else {
2008                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2009                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2010                 bp->flags &= ~BNXT_FLAG_JUMBO;
2011         }
2012
2013         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2014
2015         eth_dev->data->mtu = new_mtu;
2016         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
2017
2018         for (i = 0; i < bp->nr_vnics; i++) {
2019                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2020                 uint16_t size = 0;
2021
2022                 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2023                                         RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2024                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2025                 if (rc)
2026                         break;
2027
2028                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2029                 size -= RTE_PKTMBUF_HEADROOM;
2030
2031                 if (size < new_mtu) {
2032                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2033                         if (rc)
2034                                 return rc;
2035                 }
2036         }
2037
2038         return rc;
2039 }
2040
2041 static int
2042 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2043 {
2044         struct bnxt *bp = dev->data->dev_private;
2045         uint16_t vlan = bp->vlan;
2046         int rc;
2047
2048         rc = is_bnxt_in_error(bp);
2049         if (rc)
2050                 return rc;
2051
2052         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2053                 PMD_DRV_LOG(ERR,
2054                         "PVID cannot be modified for this function\n");
2055                 return -ENOTSUP;
2056         }
2057         bp->vlan = on ? pvid : 0;
2058
2059         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2060         if (rc)
2061                 bp->vlan = vlan;
2062         return rc;
2063 }
2064
2065 static int
2066 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2067 {
2068         struct bnxt *bp = dev->data->dev_private;
2069         int rc;
2070
2071         rc = is_bnxt_in_error(bp);
2072         if (rc)
2073                 return rc;
2074
2075         return bnxt_hwrm_port_led_cfg(bp, true);
2076 }
2077
2078 static int
2079 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2080 {
2081         struct bnxt *bp = dev->data->dev_private;
2082         int rc;
2083
2084         rc = is_bnxt_in_error(bp);
2085         if (rc)
2086                 return rc;
2087
2088         return bnxt_hwrm_port_led_cfg(bp, false);
2089 }
2090
2091 static uint32_t
2092 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2093 {
2094         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2095         uint32_t desc = 0, raw_cons = 0, cons;
2096         struct bnxt_cp_ring_info *cpr;
2097         struct bnxt_rx_queue *rxq;
2098         struct rx_pkt_cmpl *rxcmp;
2099         uint16_t cmp_type;
2100         uint8_t cmp = 1;
2101         bool valid;
2102         int rc;
2103
2104         rc = is_bnxt_in_error(bp);
2105         if (rc)
2106                 return rc;
2107
2108         rxq = dev->data->rx_queues[rx_queue_id];
2109         cpr = rxq->cp_ring;
2110         valid = cpr->valid;
2111
2112         while (raw_cons < rxq->nb_rx_desc) {
2113                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2114                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2115
2116                 if (!CMPL_VALID(rxcmp, valid))
2117                         goto nothing_to_do;
2118                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
2119                 cmp_type = CMP_TYPE(rxcmp);
2120                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
2121                         cmp = (rte_le_to_cpu_32(
2122                                         ((struct rx_tpa_end_cmpl *)
2123                                          (rxcmp))->agg_bufs_v1) &
2124                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
2125                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
2126                         desc++;
2127                 } else if (cmp_type == 0x11) {
2128                         desc++;
2129                         cmp = (rxcmp->agg_bufs_v1 &
2130                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
2131                                 RX_PKT_CMPL_AGG_BUFS_SFT;
2132                 } else {
2133                         cmp = 1;
2134                 }
2135 nothing_to_do:
2136                 raw_cons += cmp ? cmp : 2;
2137         }
2138
2139         return desc;
2140 }
2141
2142 static int
2143 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2144 {
2145         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2146         struct bnxt_rx_ring_info *rxr;
2147         struct bnxt_cp_ring_info *cpr;
2148         struct bnxt_sw_rx_bd *rx_buf;
2149         struct rx_pkt_cmpl *rxcmp;
2150         uint32_t cons, cp_cons;
2151         int rc;
2152
2153         if (!rxq)
2154                 return -EINVAL;
2155
2156         rc = is_bnxt_in_error(rxq->bp);
2157         if (rc)
2158                 return rc;
2159
2160         cpr = rxq->cp_ring;
2161         rxr = rxq->rx_ring;
2162
2163         if (offset >= rxq->nb_rx_desc)
2164                 return -EINVAL;
2165
2166         cons = RING_CMP(cpr->cp_ring_struct, offset);
2167         cp_cons = cpr->cp_raw_cons;
2168         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2169
2170         if (cons > cp_cons) {
2171                 if (CMPL_VALID(rxcmp, cpr->valid))
2172                         return RTE_ETH_RX_DESC_DONE;
2173         } else {
2174                 if (CMPL_VALID(rxcmp, !cpr->valid))
2175                         return RTE_ETH_RX_DESC_DONE;
2176         }
2177         rx_buf = &rxr->rx_buf_ring[cons];
2178         if (rx_buf->mbuf == NULL)
2179                 return RTE_ETH_RX_DESC_UNAVAIL;
2180
2181
2182         return RTE_ETH_RX_DESC_AVAIL;
2183 }
2184
2185 static int
2186 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2187 {
2188         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2189         struct bnxt_tx_ring_info *txr;
2190         struct bnxt_cp_ring_info *cpr;
2191         struct bnxt_sw_tx_bd *tx_buf;
2192         struct tx_pkt_cmpl *txcmp;
2193         uint32_t cons, cp_cons;
2194         int rc;
2195
2196         if (!txq)
2197                 return -EINVAL;
2198
2199         rc = is_bnxt_in_error(txq->bp);
2200         if (rc)
2201                 return rc;
2202
2203         cpr = txq->cp_ring;
2204         txr = txq->tx_ring;
2205
2206         if (offset >= txq->nb_tx_desc)
2207                 return -EINVAL;
2208
2209         cons = RING_CMP(cpr->cp_ring_struct, offset);
2210         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2211         cp_cons = cpr->cp_raw_cons;
2212
2213         if (cons > cp_cons) {
2214                 if (CMPL_VALID(txcmp, cpr->valid))
2215                         return RTE_ETH_TX_DESC_UNAVAIL;
2216         } else {
2217                 if (CMPL_VALID(txcmp, !cpr->valid))
2218                         return RTE_ETH_TX_DESC_UNAVAIL;
2219         }
2220         tx_buf = &txr->tx_buf_ring[cons];
2221         if (tx_buf->mbuf == NULL)
2222                 return RTE_ETH_TX_DESC_DONE;
2223
2224         return RTE_ETH_TX_DESC_FULL;
2225 }
2226
2227 static struct bnxt_filter_info *
2228 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2229                                 struct rte_eth_ethertype_filter *efilter,
2230                                 struct bnxt_vnic_info *vnic0,
2231                                 struct bnxt_vnic_info *vnic,
2232                                 int *ret)
2233 {
2234         struct bnxt_filter_info *mfilter = NULL;
2235         int match = 0;
2236         *ret = 0;
2237
2238         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2239                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2240                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2241                         " ethertype filter.", efilter->ether_type);
2242                 *ret = -EINVAL;
2243                 goto exit;
2244         }
2245         if (efilter->queue >= bp->rx_nr_rings) {
2246                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2247                 *ret = -EINVAL;
2248                 goto exit;
2249         }
2250
2251         vnic0 = &bp->vnic_info[0];
2252         vnic = &bp->vnic_info[efilter->queue];
2253         if (vnic == NULL) {
2254                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2255                 *ret = -EINVAL;
2256                 goto exit;
2257         }
2258
2259         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2260                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2261                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2262                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2263                              mfilter->flags ==
2264                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2265                              mfilter->ethertype == efilter->ether_type)) {
2266                                 match = 1;
2267                                 break;
2268                         }
2269                 }
2270         } else {
2271                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2272                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2273                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2274                              mfilter->ethertype == efilter->ether_type &&
2275                              mfilter->flags ==
2276                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2277                                 match = 1;
2278                                 break;
2279                         }
2280         }
2281
2282         if (match)
2283                 *ret = -EEXIST;
2284
2285 exit:
2286         return mfilter;
2287 }
2288
2289 static int
2290 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2291                         enum rte_filter_op filter_op,
2292                         void *arg)
2293 {
2294         struct bnxt *bp = dev->data->dev_private;
2295         struct rte_eth_ethertype_filter *efilter =
2296                         (struct rte_eth_ethertype_filter *)arg;
2297         struct bnxt_filter_info *bfilter, *filter1;
2298         struct bnxt_vnic_info *vnic, *vnic0;
2299         int ret;
2300
2301         if (filter_op == RTE_ETH_FILTER_NOP)
2302                 return 0;
2303
2304         if (arg == NULL) {
2305                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2306                             filter_op);
2307                 return -EINVAL;
2308         }
2309
2310         vnic0 = &bp->vnic_info[0];
2311         vnic = &bp->vnic_info[efilter->queue];
2312
2313         switch (filter_op) {
2314         case RTE_ETH_FILTER_ADD:
2315                 bnxt_match_and_validate_ether_filter(bp, efilter,
2316                                                         vnic0, vnic, &ret);
2317                 if (ret < 0)
2318                         return ret;
2319
2320                 bfilter = bnxt_get_unused_filter(bp);
2321                 if (bfilter == NULL) {
2322                         PMD_DRV_LOG(ERR,
2323                                 "Not enough resources for a new filter.\n");
2324                         return -ENOMEM;
2325                 }
2326                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2327                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2328                        RTE_ETHER_ADDR_LEN);
2329                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2330                        RTE_ETHER_ADDR_LEN);
2331                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2332                 bfilter->ethertype = efilter->ether_type;
2333                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2334
2335                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2336                 if (filter1 == NULL) {
2337                         ret = -EINVAL;
2338                         goto cleanup;
2339                 }
2340                 bfilter->enables |=
2341                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2342                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2343
2344                 bfilter->dst_id = vnic->fw_vnic_id;
2345
2346                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2347                         bfilter->flags =
2348                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2349                 }
2350
2351                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2352                 if (ret)
2353                         goto cleanup;
2354                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2355                 break;
2356         case RTE_ETH_FILTER_DELETE:
2357                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2358                                                         vnic0, vnic, &ret);
2359                 if (ret == -EEXIST) {
2360                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2361
2362                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2363                                       next);
2364                         bnxt_free_filter(bp, filter1);
2365                 } else if (ret == 0) {
2366                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2367                 }
2368                 break;
2369         default:
2370                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2371                 ret = -EINVAL;
2372                 goto error;
2373         }
2374         return ret;
2375 cleanup:
2376         bnxt_free_filter(bp, bfilter);
2377 error:
2378         return ret;
2379 }
2380
2381 static inline int
2382 parse_ntuple_filter(struct bnxt *bp,
2383                     struct rte_eth_ntuple_filter *nfilter,
2384                     struct bnxt_filter_info *bfilter)
2385 {
2386         uint32_t en = 0;
2387
2388         if (nfilter->queue >= bp->rx_nr_rings) {
2389                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2390                 return -EINVAL;
2391         }
2392
2393         switch (nfilter->dst_port_mask) {
2394         case UINT16_MAX:
2395                 bfilter->dst_port_mask = -1;
2396                 bfilter->dst_port = nfilter->dst_port;
2397                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2398                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2399                 break;
2400         default:
2401                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2402                 return -EINVAL;
2403         }
2404
2405         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2406         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2407
2408         switch (nfilter->proto_mask) {
2409         case UINT8_MAX:
2410                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2411                         bfilter->ip_protocol = 17;
2412                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2413                         bfilter->ip_protocol = 6;
2414                 else
2415                         return -EINVAL;
2416                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2417                 break;
2418         default:
2419                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2420                 return -EINVAL;
2421         }
2422
2423         switch (nfilter->dst_ip_mask) {
2424         case UINT32_MAX:
2425                 bfilter->dst_ipaddr_mask[0] = -1;
2426                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2427                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2428                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2429                 break;
2430         default:
2431                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2432                 return -EINVAL;
2433         }
2434
2435         switch (nfilter->src_ip_mask) {
2436         case UINT32_MAX:
2437                 bfilter->src_ipaddr_mask[0] = -1;
2438                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2439                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2440                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2441                 break;
2442         default:
2443                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2444                 return -EINVAL;
2445         }
2446
2447         switch (nfilter->src_port_mask) {
2448         case UINT16_MAX:
2449                 bfilter->src_port_mask = -1;
2450                 bfilter->src_port = nfilter->src_port;
2451                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2452                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2453                 break;
2454         default:
2455                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2456                 return -EINVAL;
2457         }
2458
2459         //TODO Priority
2460         //nfilter->priority = (uint8_t)filter->priority;
2461
2462         bfilter->enables = en;
2463         return 0;
2464 }
2465
2466 static struct bnxt_filter_info*
2467 bnxt_match_ntuple_filter(struct bnxt *bp,
2468                          struct bnxt_filter_info *bfilter,
2469                          struct bnxt_vnic_info **mvnic)
2470 {
2471         struct bnxt_filter_info *mfilter = NULL;
2472         int i;
2473
2474         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2475                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2476                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2477                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2478                             bfilter->src_ipaddr_mask[0] ==
2479                             mfilter->src_ipaddr_mask[0] &&
2480                             bfilter->src_port == mfilter->src_port &&
2481                             bfilter->src_port_mask == mfilter->src_port_mask &&
2482                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2483                             bfilter->dst_ipaddr_mask[0] ==
2484                             mfilter->dst_ipaddr_mask[0] &&
2485                             bfilter->dst_port == mfilter->dst_port &&
2486                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2487                             bfilter->flags == mfilter->flags &&
2488                             bfilter->enables == mfilter->enables) {
2489                                 if (mvnic)
2490                                         *mvnic = vnic;
2491                                 return mfilter;
2492                         }
2493                 }
2494         }
2495         return NULL;
2496 }
2497
2498 static int
2499 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2500                        struct rte_eth_ntuple_filter *nfilter,
2501                        enum rte_filter_op filter_op)
2502 {
2503         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2504         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2505         int ret;
2506
2507         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2508                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2509                 return -EINVAL;
2510         }
2511
2512         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2513                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2514                 return -EINVAL;
2515         }
2516
2517         bfilter = bnxt_get_unused_filter(bp);
2518         if (bfilter == NULL) {
2519                 PMD_DRV_LOG(ERR,
2520                         "Not enough resources for a new filter.\n");
2521                 return -ENOMEM;
2522         }
2523         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2524         if (ret < 0)
2525                 goto free_filter;
2526
2527         vnic = &bp->vnic_info[nfilter->queue];
2528         vnic0 = &bp->vnic_info[0];
2529         filter1 = STAILQ_FIRST(&vnic0->filter);
2530         if (filter1 == NULL) {
2531                 ret = -EINVAL;
2532                 goto free_filter;
2533         }
2534
2535         bfilter->dst_id = vnic->fw_vnic_id;
2536         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2537         bfilter->enables |=
2538                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2539         bfilter->ethertype = 0x800;
2540         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2541
2542         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2543
2544         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2545             bfilter->dst_id == mfilter->dst_id) {
2546                 PMD_DRV_LOG(ERR, "filter exists.\n");
2547                 ret = -EEXIST;
2548                 goto free_filter;
2549         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2550                    bfilter->dst_id != mfilter->dst_id) {
2551                 mfilter->dst_id = vnic->fw_vnic_id;
2552                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2553                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2554                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2555                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2556                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2557                 goto free_filter;
2558         }
2559         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2560                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2561                 ret = -ENOENT;
2562                 goto free_filter;
2563         }
2564
2565         if (filter_op == RTE_ETH_FILTER_ADD) {
2566                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2567                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2568                 if (ret)
2569                         goto free_filter;
2570                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2571         } else {
2572                 if (mfilter == NULL) {
2573                         /* This should not happen. But for Coverity! */
2574                         ret = -ENOENT;
2575                         goto free_filter;
2576                 }
2577                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2578
2579                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2580                 bnxt_free_filter(bp, mfilter);
2581                 mfilter->fw_l2_filter_id = -1;
2582                 bnxt_free_filter(bp, bfilter);
2583                 bfilter->fw_l2_filter_id = -1;
2584         }
2585
2586         return 0;
2587 free_filter:
2588         bfilter->fw_l2_filter_id = -1;
2589         bnxt_free_filter(bp, bfilter);
2590         return ret;
2591 }
2592
2593 static int
2594 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2595                         enum rte_filter_op filter_op,
2596                         void *arg)
2597 {
2598         struct bnxt *bp = dev->data->dev_private;
2599         int ret;
2600
2601         if (filter_op == RTE_ETH_FILTER_NOP)
2602                 return 0;
2603
2604         if (arg == NULL) {
2605                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2606                             filter_op);
2607                 return -EINVAL;
2608         }
2609
2610         switch (filter_op) {
2611         case RTE_ETH_FILTER_ADD:
2612                 ret = bnxt_cfg_ntuple_filter(bp,
2613                         (struct rte_eth_ntuple_filter *)arg,
2614                         filter_op);
2615                 break;
2616         case RTE_ETH_FILTER_DELETE:
2617                 ret = bnxt_cfg_ntuple_filter(bp,
2618                         (struct rte_eth_ntuple_filter *)arg,
2619                         filter_op);
2620                 break;
2621         default:
2622                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2623                 ret = -EINVAL;
2624                 break;
2625         }
2626         return ret;
2627 }
2628
2629 static int
2630 bnxt_parse_fdir_filter(struct bnxt *bp,
2631                        struct rte_eth_fdir_filter *fdir,
2632                        struct bnxt_filter_info *filter)
2633 {
2634         enum rte_fdir_mode fdir_mode =
2635                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2636         struct bnxt_vnic_info *vnic0, *vnic;
2637         struct bnxt_filter_info *filter1;
2638         uint32_t en = 0;
2639         int i;
2640
2641         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2642                 return -EINVAL;
2643
2644         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2645         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2646
2647         switch (fdir->input.flow_type) {
2648         case RTE_ETH_FLOW_IPV4:
2649         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2650                 /* FALLTHROUGH */
2651                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2652                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2653                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2654                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2655                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2656                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2657                 filter->ip_addr_type =
2658                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2659                 filter->src_ipaddr_mask[0] = 0xffffffff;
2660                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2661                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2662                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2663                 filter->ethertype = 0x800;
2664                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2665                 break;
2666         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2667                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2668                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2669                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2670                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2671                 filter->dst_port_mask = 0xffff;
2672                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2673                 filter->src_port_mask = 0xffff;
2674                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2675                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2676                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2677                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2678                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2679                 filter->ip_protocol = 6;
2680                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2681                 filter->ip_addr_type =
2682                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2683                 filter->src_ipaddr_mask[0] = 0xffffffff;
2684                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2685                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2686                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2687                 filter->ethertype = 0x800;
2688                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2689                 break;
2690         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2691                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2692                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2693                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2694                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2695                 filter->dst_port_mask = 0xffff;
2696                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2697                 filter->src_port_mask = 0xffff;
2698                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2699                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2700                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2701                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2702                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2703                 filter->ip_protocol = 17;
2704                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2705                 filter->ip_addr_type =
2706                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2707                 filter->src_ipaddr_mask[0] = 0xffffffff;
2708                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2709                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2710                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2711                 filter->ethertype = 0x800;
2712                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2713                 break;
2714         case RTE_ETH_FLOW_IPV6:
2715         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2716                 /* FALLTHROUGH */
2717                 filter->ip_addr_type =
2718                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2719                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2720                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2721                 rte_memcpy(filter->src_ipaddr,
2722                            fdir->input.flow.ipv6_flow.src_ip, 16);
2723                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2724                 rte_memcpy(filter->dst_ipaddr,
2725                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2726                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2727                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2728                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2729                 memset(filter->src_ipaddr_mask, 0xff, 16);
2730                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2731                 filter->ethertype = 0x86dd;
2732                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2733                 break;
2734         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2735                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2736                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2737                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2738                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2739                 filter->dst_port_mask = 0xffff;
2740                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2741                 filter->src_port_mask = 0xffff;
2742                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2743                 filter->ip_addr_type =
2744                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2745                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2746                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2747                 rte_memcpy(filter->src_ipaddr,
2748                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2749                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2750                 rte_memcpy(filter->dst_ipaddr,
2751                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2752                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2753                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2754                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2755                 memset(filter->src_ipaddr_mask, 0xff, 16);
2756                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2757                 filter->ethertype = 0x86dd;
2758                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2759                 break;
2760         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2761                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2762                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2763                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2764                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2765                 filter->dst_port_mask = 0xffff;
2766                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2767                 filter->src_port_mask = 0xffff;
2768                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2769                 filter->ip_addr_type =
2770                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2771                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2772                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2773                 rte_memcpy(filter->src_ipaddr,
2774                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2775                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2776                 rte_memcpy(filter->dst_ipaddr,
2777                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2778                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2779                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2780                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2781                 memset(filter->src_ipaddr_mask, 0xff, 16);
2782                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2783                 filter->ethertype = 0x86dd;
2784                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2785                 break;
2786         case RTE_ETH_FLOW_L2_PAYLOAD:
2787                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2788                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2789                 break;
2790         case RTE_ETH_FLOW_VXLAN:
2791                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2792                         return -EINVAL;
2793                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2794                 filter->tunnel_type =
2795                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2796                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2797                 break;
2798         case RTE_ETH_FLOW_NVGRE:
2799                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2800                         return -EINVAL;
2801                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2802                 filter->tunnel_type =
2803                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2804                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2805                 break;
2806         case RTE_ETH_FLOW_UNKNOWN:
2807         case RTE_ETH_FLOW_RAW:
2808         case RTE_ETH_FLOW_FRAG_IPV4:
2809         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2810         case RTE_ETH_FLOW_FRAG_IPV6:
2811         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2812         case RTE_ETH_FLOW_IPV6_EX:
2813         case RTE_ETH_FLOW_IPV6_TCP_EX:
2814         case RTE_ETH_FLOW_IPV6_UDP_EX:
2815         case RTE_ETH_FLOW_GENEVE:
2816                 /* FALLTHROUGH */
2817         default:
2818                 return -EINVAL;
2819         }
2820
2821         vnic0 = &bp->vnic_info[0];
2822         vnic = &bp->vnic_info[fdir->action.rx_queue];
2823         if (vnic == NULL) {
2824                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2825                 return -EINVAL;
2826         }
2827
2828
2829         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2830                 rte_memcpy(filter->dst_macaddr,
2831                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2832                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2833         }
2834
2835         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2836                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2837                 filter1 = STAILQ_FIRST(&vnic0->filter);
2838                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2839         } else {
2840                 filter->dst_id = vnic->fw_vnic_id;
2841                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2842                         if (filter->dst_macaddr[i] == 0x00)
2843                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2844                         else
2845                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2846         }
2847
2848         if (filter1 == NULL)
2849                 return -EINVAL;
2850
2851         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2852         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2853
2854         filter->enables = en;
2855
2856         return 0;
2857 }
2858
2859 static struct bnxt_filter_info *
2860 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2861                 struct bnxt_vnic_info **mvnic)
2862 {
2863         struct bnxt_filter_info *mf = NULL;
2864         int i;
2865
2866         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2867                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2868
2869                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2870                         if (mf->filter_type == nf->filter_type &&
2871                             mf->flags == nf->flags &&
2872                             mf->src_port == nf->src_port &&
2873                             mf->src_port_mask == nf->src_port_mask &&
2874                             mf->dst_port == nf->dst_port &&
2875                             mf->dst_port_mask == nf->dst_port_mask &&
2876                             mf->ip_protocol == nf->ip_protocol &&
2877                             mf->ip_addr_type == nf->ip_addr_type &&
2878                             mf->ethertype == nf->ethertype &&
2879                             mf->vni == nf->vni &&
2880                             mf->tunnel_type == nf->tunnel_type &&
2881                             mf->l2_ovlan == nf->l2_ovlan &&
2882                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2883                             mf->l2_ivlan == nf->l2_ivlan &&
2884                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2885                             !memcmp(mf->l2_addr, nf->l2_addr,
2886                                     RTE_ETHER_ADDR_LEN) &&
2887                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2888                                     RTE_ETHER_ADDR_LEN) &&
2889                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2890                                     RTE_ETHER_ADDR_LEN) &&
2891                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2892                                     RTE_ETHER_ADDR_LEN) &&
2893                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2894                                     sizeof(nf->src_ipaddr)) &&
2895                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2896                                     sizeof(nf->src_ipaddr_mask)) &&
2897                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2898                                     sizeof(nf->dst_ipaddr)) &&
2899                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2900                                     sizeof(nf->dst_ipaddr_mask))) {
2901                                 if (mvnic)
2902                                         *mvnic = vnic;
2903                                 return mf;
2904                         }
2905                 }
2906         }
2907         return NULL;
2908 }
2909
2910 static int
2911 bnxt_fdir_filter(struct rte_eth_dev *dev,
2912                  enum rte_filter_op filter_op,
2913                  void *arg)
2914 {
2915         struct bnxt *bp = dev->data->dev_private;
2916         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2917         struct bnxt_filter_info *filter, *match;
2918         struct bnxt_vnic_info *vnic, *mvnic;
2919         int ret = 0, i;
2920
2921         if (filter_op == RTE_ETH_FILTER_NOP)
2922                 return 0;
2923
2924         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2925                 return -EINVAL;
2926
2927         switch (filter_op) {
2928         case RTE_ETH_FILTER_ADD:
2929         case RTE_ETH_FILTER_DELETE:
2930                 /* FALLTHROUGH */
2931                 filter = bnxt_get_unused_filter(bp);
2932                 if (filter == NULL) {
2933                         PMD_DRV_LOG(ERR,
2934                                 "Not enough resources for a new flow.\n");
2935                         return -ENOMEM;
2936                 }
2937
2938                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2939                 if (ret != 0)
2940                         goto free_filter;
2941                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2942
2943                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2944                         vnic = &bp->vnic_info[0];
2945                 else
2946                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2947
2948                 match = bnxt_match_fdir(bp, filter, &mvnic);
2949                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2950                         if (match->dst_id == vnic->fw_vnic_id) {
2951                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2952                                 ret = -EEXIST;
2953                                 goto free_filter;
2954                         } else {
2955                                 match->dst_id = vnic->fw_vnic_id;
2956                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2957                                                                   match->dst_id,
2958                                                                   match);
2959                                 STAILQ_REMOVE(&mvnic->filter, match,
2960                                               bnxt_filter_info, next);
2961                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2962                                 PMD_DRV_LOG(ERR,
2963                                         "Filter with matching pattern exist\n");
2964                                 PMD_DRV_LOG(ERR,
2965                                         "Updated it to new destination q\n");
2966                                 goto free_filter;
2967                         }
2968                 }
2969                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2970                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2971                         ret = -ENOENT;
2972                         goto free_filter;
2973                 }
2974
2975                 if (filter_op == RTE_ETH_FILTER_ADD) {
2976                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2977                                                           filter->dst_id,
2978                                                           filter);
2979                         if (ret)
2980                                 goto free_filter;
2981                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2982                 } else {
2983                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2984                         STAILQ_REMOVE(&vnic->filter, match,
2985                                       bnxt_filter_info, next);
2986                         bnxt_free_filter(bp, match);
2987                         filter->fw_l2_filter_id = -1;
2988                         bnxt_free_filter(bp, filter);
2989                 }
2990                 break;
2991         case RTE_ETH_FILTER_FLUSH:
2992                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2993                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2994
2995                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2996                                 if (filter->filter_type ==
2997                                     HWRM_CFA_NTUPLE_FILTER) {
2998                                         ret =
2999                                         bnxt_hwrm_clear_ntuple_filter(bp,
3000                                                                       filter);
3001                                         STAILQ_REMOVE(&vnic->filter, filter,
3002                                                       bnxt_filter_info, next);
3003                                 }
3004                         }
3005                 }
3006                 return ret;
3007         case RTE_ETH_FILTER_UPDATE:
3008         case RTE_ETH_FILTER_STATS:
3009         case RTE_ETH_FILTER_INFO:
3010                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3011                 break;
3012         default:
3013                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3014                 ret = -EINVAL;
3015                 break;
3016         }
3017         return ret;
3018
3019 free_filter:
3020         filter->fw_l2_filter_id = -1;
3021         bnxt_free_filter(bp, filter);
3022         return ret;
3023 }
3024
3025 static int
3026 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3027                     enum rte_filter_type filter_type,
3028                     enum rte_filter_op filter_op, void *arg)
3029 {
3030         int ret = 0;
3031
3032         ret = is_bnxt_in_error(dev->data->dev_private);
3033         if (ret)
3034                 return ret;
3035
3036         switch (filter_type) {
3037         case RTE_ETH_FILTER_TUNNEL:
3038                 PMD_DRV_LOG(ERR,
3039                         "filter type: %d: To be implemented\n", filter_type);
3040                 break;
3041         case RTE_ETH_FILTER_FDIR:
3042                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3043                 break;
3044         case RTE_ETH_FILTER_NTUPLE:
3045                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3046                 break;
3047         case RTE_ETH_FILTER_ETHERTYPE:
3048                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3049                 break;
3050         case RTE_ETH_FILTER_GENERIC:
3051                 if (filter_op != RTE_ETH_FILTER_GET)
3052                         return -EINVAL;
3053                 *(const void **)arg = &bnxt_flow_ops;
3054                 break;
3055         default:
3056                 PMD_DRV_LOG(ERR,
3057                         "Filter type (%d) not supported", filter_type);
3058                 ret = -EINVAL;
3059                 break;
3060         }
3061         return ret;
3062 }
3063
3064 static const uint32_t *
3065 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3066 {
3067         static const uint32_t ptypes[] = {
3068                 RTE_PTYPE_L2_ETHER_VLAN,
3069                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3070                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3071                 RTE_PTYPE_L4_ICMP,
3072                 RTE_PTYPE_L4_TCP,
3073                 RTE_PTYPE_L4_UDP,
3074                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3075                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3076                 RTE_PTYPE_INNER_L4_ICMP,
3077                 RTE_PTYPE_INNER_L4_TCP,
3078                 RTE_PTYPE_INNER_L4_UDP,
3079                 RTE_PTYPE_UNKNOWN
3080         };
3081
3082         if (!dev->rx_pkt_burst)
3083                 return NULL;
3084
3085         return ptypes;
3086 }
3087
3088 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3089                          int reg_win)
3090 {
3091         uint32_t reg_base = *reg_arr & 0xfffff000;
3092         uint32_t win_off;
3093         int i;
3094
3095         for (i = 0; i < count; i++) {
3096                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3097                         return -ERANGE;
3098         }
3099         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3100         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3101         return 0;
3102 }
3103
3104 static int bnxt_map_ptp_regs(struct bnxt *bp)
3105 {
3106         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3107         uint32_t *reg_arr;
3108         int rc, i;
3109
3110         reg_arr = ptp->rx_regs;
3111         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3112         if (rc)
3113                 return rc;
3114
3115         reg_arr = ptp->tx_regs;
3116         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3117         if (rc)
3118                 return rc;
3119
3120         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3121                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3122
3123         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3124                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3125
3126         return 0;
3127 }
3128
3129 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3130 {
3131         rte_write32(0, (uint8_t *)bp->bar0 +
3132                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3133         rte_write32(0, (uint8_t *)bp->bar0 +
3134                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3135 }
3136
3137 static uint64_t bnxt_cc_read(struct bnxt *bp)
3138 {
3139         uint64_t ns;
3140
3141         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3142                               BNXT_GRCPF_REG_SYNC_TIME));
3143         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3144                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3145         return ns;
3146 }
3147
3148 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3149 {
3150         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3151         uint32_t fifo;
3152
3153         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3154                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3155         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3156                 return -EAGAIN;
3157
3158         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3159                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3160         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3161                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3162         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3163                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3164
3165         return 0;
3166 }
3167
3168 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3169 {
3170         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3171         struct bnxt_pf_info *pf = &bp->pf;
3172         uint16_t port_id;
3173         uint32_t fifo;
3174
3175         if (!ptp)
3176                 return -ENODEV;
3177
3178         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3179                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3180         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3181                 return -EAGAIN;
3182
3183         port_id = pf->port_id;
3184         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3185                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3186
3187         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3188                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3189         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3190 /*              bnxt_clr_rx_ts(bp);       TBD  */
3191                 return -EBUSY;
3192         }
3193
3194         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3195                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3196         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3197                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3198
3199         return 0;
3200 }
3201
3202 static int
3203 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3204 {
3205         uint64_t ns;
3206         struct bnxt *bp = dev->data->dev_private;
3207         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3208
3209         if (!ptp)
3210                 return 0;
3211
3212         ns = rte_timespec_to_ns(ts);
3213         /* Set the timecounters to a new value. */
3214         ptp->tc.nsec = ns;
3215
3216         return 0;
3217 }
3218
3219 static int
3220 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3221 {
3222         uint64_t ns, systime_cycles;
3223         struct bnxt *bp = dev->data->dev_private;
3224         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3225
3226         if (!ptp)
3227                 return 0;
3228
3229         systime_cycles = bnxt_cc_read(bp);
3230         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3231         *ts = rte_ns_to_timespec(ns);
3232
3233         return 0;
3234 }
3235 static int
3236 bnxt_timesync_enable(struct rte_eth_dev *dev)
3237 {
3238         struct bnxt *bp = dev->data->dev_private;
3239         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3240         uint32_t shift = 0;
3241
3242         if (!ptp)
3243                 return 0;
3244
3245         ptp->rx_filter = 1;
3246         ptp->tx_tstamp_en = 1;
3247         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3248
3249         if (!bnxt_hwrm_ptp_cfg(bp))
3250                 bnxt_map_ptp_regs(bp);
3251
3252         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3253         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3254         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3255
3256         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3257         ptp->tc.cc_shift = shift;
3258         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3259
3260         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3261         ptp->rx_tstamp_tc.cc_shift = shift;
3262         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3263
3264         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3265         ptp->tx_tstamp_tc.cc_shift = shift;
3266         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3267
3268         return 0;
3269 }
3270
3271 static int
3272 bnxt_timesync_disable(struct rte_eth_dev *dev)
3273 {
3274         struct bnxt *bp = dev->data->dev_private;
3275         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3276
3277         if (!ptp)
3278                 return 0;
3279
3280         ptp->rx_filter = 0;
3281         ptp->tx_tstamp_en = 0;
3282         ptp->rxctl = 0;
3283
3284         bnxt_hwrm_ptp_cfg(bp);
3285
3286         bnxt_unmap_ptp_regs(bp);
3287
3288         return 0;
3289 }
3290
3291 static int
3292 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3293                                  struct timespec *timestamp,
3294                                  uint32_t flags __rte_unused)
3295 {
3296         struct bnxt *bp = dev->data->dev_private;
3297         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3298         uint64_t rx_tstamp_cycles = 0;
3299         uint64_t ns;
3300
3301         if (!ptp)
3302                 return 0;
3303
3304         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3305         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3306         *timestamp = rte_ns_to_timespec(ns);
3307         return  0;
3308 }
3309
3310 static int
3311 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3312                                  struct timespec *timestamp)
3313 {
3314         struct bnxt *bp = dev->data->dev_private;
3315         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3316         uint64_t tx_tstamp_cycles = 0;
3317         uint64_t ns;
3318
3319         if (!ptp)
3320                 return 0;
3321
3322         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3323         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3324         *timestamp = rte_ns_to_timespec(ns);
3325
3326         return 0;
3327 }
3328
3329 static int
3330 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3331 {
3332         struct bnxt *bp = dev->data->dev_private;
3333         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3334
3335         if (!ptp)
3336                 return 0;
3337
3338         ptp->tc.nsec += delta;
3339
3340         return 0;
3341 }
3342
3343 static int
3344 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3345 {
3346         struct bnxt *bp = dev->data->dev_private;
3347         int rc;
3348         uint32_t dir_entries;
3349         uint32_t entry_length;
3350
3351         rc = is_bnxt_in_error(bp);
3352         if (rc)
3353                 return rc;
3354
3355         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3356                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3357                 bp->pdev->addr.devid, bp->pdev->addr.function);
3358
3359         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3360         if (rc != 0)
3361                 return rc;
3362
3363         return dir_entries * entry_length;
3364 }
3365
3366 static int
3367 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3368                 struct rte_dev_eeprom_info *in_eeprom)
3369 {
3370         struct bnxt *bp = dev->data->dev_private;
3371         uint32_t index;
3372         uint32_t offset;
3373         int rc;
3374
3375         rc = is_bnxt_in_error(bp);
3376         if (rc)
3377                 return rc;
3378
3379         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3380                 "len = %d\n", bp->pdev->addr.domain,
3381                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3382                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3383
3384         if (in_eeprom->offset == 0) /* special offset value to get directory */
3385                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3386                                                 in_eeprom->data);
3387
3388         index = in_eeprom->offset >> 24;
3389         offset = in_eeprom->offset & 0xffffff;
3390
3391         if (index != 0)
3392                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3393                                            in_eeprom->length, in_eeprom->data);
3394
3395         return 0;
3396 }
3397
3398 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3399 {
3400         switch (dir_type) {
3401         case BNX_DIR_TYPE_CHIMP_PATCH:
3402         case BNX_DIR_TYPE_BOOTCODE:
3403         case BNX_DIR_TYPE_BOOTCODE_2:
3404         case BNX_DIR_TYPE_APE_FW:
3405         case BNX_DIR_TYPE_APE_PATCH:
3406         case BNX_DIR_TYPE_KONG_FW:
3407         case BNX_DIR_TYPE_KONG_PATCH:
3408         case BNX_DIR_TYPE_BONO_FW:
3409         case BNX_DIR_TYPE_BONO_PATCH:
3410                 /* FALLTHROUGH */
3411                 return true;
3412         }
3413
3414         return false;
3415 }
3416
3417 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3418 {
3419         switch (dir_type) {
3420         case BNX_DIR_TYPE_AVS:
3421         case BNX_DIR_TYPE_EXP_ROM_MBA:
3422         case BNX_DIR_TYPE_PCIE:
3423         case BNX_DIR_TYPE_TSCF_UCODE:
3424         case BNX_DIR_TYPE_EXT_PHY:
3425         case BNX_DIR_TYPE_CCM:
3426         case BNX_DIR_TYPE_ISCSI_BOOT:
3427         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3428         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3429                 /* FALLTHROUGH */
3430                 return true;
3431         }
3432
3433         return false;
3434 }
3435
3436 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3437 {
3438         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3439                 bnxt_dir_type_is_other_exec_format(dir_type);
3440 }
3441
3442 static int
3443 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3444                 struct rte_dev_eeprom_info *in_eeprom)
3445 {
3446         struct bnxt *bp = dev->data->dev_private;
3447         uint8_t index, dir_op;
3448         uint16_t type, ext, ordinal, attr;
3449         int rc;
3450
3451         rc = is_bnxt_in_error(bp);
3452         if (rc)
3453                 return rc;
3454
3455         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3456                 "len = %d\n", bp->pdev->addr.domain,
3457                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3458                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3459
3460         if (!BNXT_PF(bp)) {
3461                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3462                 return -EINVAL;
3463         }
3464
3465         type = in_eeprom->magic >> 16;
3466
3467         if (type == 0xffff) { /* special value for directory operations */
3468                 index = in_eeprom->magic & 0xff;
3469                 dir_op = in_eeprom->magic >> 8;
3470                 if (index == 0)
3471                         return -EINVAL;
3472                 switch (dir_op) {
3473                 case 0x0e: /* erase */
3474                         if (in_eeprom->offset != ~in_eeprom->magic)
3475                                 return -EINVAL;
3476                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3477                 default:
3478                         return -EINVAL;
3479                 }
3480         }
3481
3482         /* Create or re-write an NVM item: */
3483         if (bnxt_dir_type_is_executable(type) == true)
3484                 return -EOPNOTSUPP;
3485         ext = in_eeprom->magic & 0xffff;
3486         ordinal = in_eeprom->offset >> 16;
3487         attr = in_eeprom->offset & 0xffff;
3488
3489         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3490                                      in_eeprom->data, in_eeprom->length);
3491 }
3492
3493 /*
3494  * Initialization
3495  */
3496
3497 static const struct eth_dev_ops bnxt_dev_ops = {
3498         .dev_infos_get = bnxt_dev_info_get_op,
3499         .dev_close = bnxt_dev_close_op,
3500         .dev_configure = bnxt_dev_configure_op,
3501         .dev_start = bnxt_dev_start_op,
3502         .dev_stop = bnxt_dev_stop_op,
3503         .dev_set_link_up = bnxt_dev_set_link_up_op,
3504         .dev_set_link_down = bnxt_dev_set_link_down_op,
3505         .stats_get = bnxt_stats_get_op,
3506         .stats_reset = bnxt_stats_reset_op,
3507         .rx_queue_setup = bnxt_rx_queue_setup_op,
3508         .rx_queue_release = bnxt_rx_queue_release_op,
3509         .tx_queue_setup = bnxt_tx_queue_setup_op,
3510         .tx_queue_release = bnxt_tx_queue_release_op,
3511         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3512         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3513         .reta_update = bnxt_reta_update_op,
3514         .reta_query = bnxt_reta_query_op,
3515         .rss_hash_update = bnxt_rss_hash_update_op,
3516         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3517         .link_update = bnxt_link_update_op,
3518         .promiscuous_enable = bnxt_promiscuous_enable_op,
3519         .promiscuous_disable = bnxt_promiscuous_disable_op,
3520         .allmulticast_enable = bnxt_allmulticast_enable_op,
3521         .allmulticast_disable = bnxt_allmulticast_disable_op,
3522         .mac_addr_add = bnxt_mac_addr_add_op,
3523         .mac_addr_remove = bnxt_mac_addr_remove_op,
3524         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3525         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3526         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3527         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3528         .vlan_filter_set = bnxt_vlan_filter_set_op,
3529         .vlan_offload_set = bnxt_vlan_offload_set_op,
3530         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3531         .mtu_set = bnxt_mtu_set_op,
3532         .mac_addr_set = bnxt_set_default_mac_addr_op,
3533         .xstats_get = bnxt_dev_xstats_get_op,
3534         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3535         .xstats_reset = bnxt_dev_xstats_reset_op,
3536         .fw_version_get = bnxt_fw_version_get,
3537         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3538         .rxq_info_get = bnxt_rxq_info_get_op,
3539         .txq_info_get = bnxt_txq_info_get_op,
3540         .dev_led_on = bnxt_dev_led_on_op,
3541         .dev_led_off = bnxt_dev_led_off_op,
3542         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3543         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3544         .rx_queue_count = bnxt_rx_queue_count_op,
3545         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3546         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3547         .rx_queue_start = bnxt_rx_queue_start,
3548         .rx_queue_stop = bnxt_rx_queue_stop,
3549         .tx_queue_start = bnxt_tx_queue_start,
3550         .tx_queue_stop = bnxt_tx_queue_stop,
3551         .filter_ctrl = bnxt_filter_ctrl_op,
3552         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3553         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3554         .get_eeprom           = bnxt_get_eeprom_op,
3555         .set_eeprom           = bnxt_set_eeprom_op,
3556         .timesync_enable      = bnxt_timesync_enable,
3557         .timesync_disable     = bnxt_timesync_disable,
3558         .timesync_read_time   = bnxt_timesync_read_time,
3559         .timesync_write_time   = bnxt_timesync_write_time,
3560         .timesync_adjust_time = bnxt_timesync_adjust_time,
3561         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3562         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3563 };
3564
3565 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3566 {
3567         struct bnxt_error_recovery_info *info = bp->recovery_info;
3568         uint32_t reg_base = 0xffffffff;
3569         int i;
3570
3571         /* Only pre-map the monitoring GRC registers using window 2 */
3572         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3573                 uint32_t reg = info->status_regs[i];
3574
3575                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3576                         continue;
3577
3578                 if (reg_base == 0xffffffff)
3579                         reg_base = reg & 0xfffff000;
3580                 if ((reg & 0xfffff000) != reg_base)
3581                         return -ERANGE;
3582
3583                 /* Use mask 0xffc as the Lower 2 bits indicates
3584                  * address space location
3585                  */
3586                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3587                                                 (reg & 0xffc);
3588         }
3589
3590         if (reg_base == 0xffffffff)
3591                 return 0;
3592
3593         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3594                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3595
3596         return 0;
3597 }
3598
3599 static void bnxt_dev_cleanup(struct bnxt *bp)
3600 {
3601         bnxt_set_hwrm_link_config(bp, false);
3602         bp->link_info.link_up = 0;
3603         if (bp->dev_stopped == 0)
3604                 bnxt_dev_stop_op(bp->eth_dev);
3605
3606         bnxt_uninit_resources(bp, true);
3607 }
3608
3609 static int bnxt_restore_filters(struct bnxt *bp)
3610 {
3611         struct rte_eth_dev *dev = bp->eth_dev;
3612         int ret = 0;
3613
3614         if (dev->data->all_multicast)
3615                 ret = bnxt_allmulticast_enable_op(dev);
3616         if (dev->data->promiscuous)
3617                 ret = bnxt_promiscuous_enable_op(dev);
3618
3619         /* TODO restore other filters as well */
3620         return ret;
3621 }
3622
3623 static void bnxt_dev_recover(void *arg)
3624 {
3625         struct bnxt *bp = arg;
3626         int timeout = bp->fw_reset_max_msecs;
3627         int rc = 0;
3628
3629         /* Clear Error flag so that device re-init should happen */
3630         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3631
3632         do {
3633                 rc = bnxt_hwrm_ver_get(bp);
3634                 if (rc == 0)
3635                         break;
3636                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3637                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3638         } while (rc && timeout);
3639
3640         if (rc) {
3641                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3642                 goto err;
3643         }
3644
3645         rc = bnxt_init_resources(bp, true);
3646         if (rc) {
3647                 PMD_DRV_LOG(ERR,
3648                             "Failed to initialize resources after reset\n");
3649                 goto err;
3650         }
3651         /* clear reset flag as the device is initialized now */
3652         bp->flags &= ~BNXT_FLAG_FW_RESET;
3653
3654         rc = bnxt_dev_start_op(bp->eth_dev);
3655         if (rc) {
3656                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3657                 goto err;
3658         }
3659
3660         rc = bnxt_restore_filters(bp);
3661         if (rc)
3662                 goto err;
3663
3664         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3665         return;
3666 err:
3667         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3668         bnxt_uninit_resources(bp, false);
3669         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3670 }
3671
3672 void bnxt_dev_reset_and_resume(void *arg)
3673 {
3674         struct bnxt *bp = arg;
3675         int rc;
3676
3677         bnxt_dev_cleanup(bp);
3678
3679         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3680                                bnxt_dev_recover, (void *)bp);
3681         if (rc)
3682                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3683 }
3684
3685 static bool bnxt_vf_pciid(uint16_t id)
3686 {
3687         if (id == BROADCOM_DEV_ID_57304_VF ||
3688             id == BROADCOM_DEV_ID_57406_VF ||
3689             id == BROADCOM_DEV_ID_5731X_VF ||
3690             id == BROADCOM_DEV_ID_5741X_VF ||
3691             id == BROADCOM_DEV_ID_57414_VF ||
3692             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3693             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3694             id == BROADCOM_DEV_ID_58802_VF ||
3695             id == BROADCOM_DEV_ID_57500_VF1 ||
3696             id == BROADCOM_DEV_ID_57500_VF2)
3697                 return true;
3698         return false;
3699 }
3700
3701 bool bnxt_stratus_device(struct bnxt *bp)
3702 {
3703         uint16_t id = bp->pdev->id.device_id;
3704
3705         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3706             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3707             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3708                 return true;
3709         return false;
3710 }
3711
3712 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3713 {
3714         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3715         struct bnxt *bp = eth_dev->data->dev_private;
3716
3717         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3718         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3719         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3720         if (!bp->bar0 || !bp->doorbell_base) {
3721                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3722                 return -ENODEV;
3723         }
3724
3725         bp->eth_dev = eth_dev;
3726         bp->pdev = pci_dev;
3727
3728         return 0;
3729 }
3730
3731 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3732                                   struct bnxt_ctx_pg_info *ctx_pg,
3733                                   uint32_t mem_size,
3734                                   const char *suffix,
3735                                   uint16_t idx)
3736 {
3737         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3738         const struct rte_memzone *mz = NULL;
3739         char mz_name[RTE_MEMZONE_NAMESIZE];
3740         rte_iova_t mz_phys_addr;
3741         uint64_t valid_bits = 0;
3742         uint32_t sz;
3743         int i;
3744
3745         if (!mem_size)
3746                 return 0;
3747
3748         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3749                          BNXT_PAGE_SIZE;
3750         rmem->page_size = BNXT_PAGE_SIZE;
3751         rmem->pg_arr = ctx_pg->ctx_pg_arr;
3752         rmem->dma_arr = ctx_pg->ctx_dma_arr;
3753         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3754
3755         valid_bits = PTU_PTE_VALID;
3756
3757         if (rmem->nr_pages > 1) {
3758                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3759                          "bnxt_ctx_pg_tbl%s_%x_%d",
3760                          suffix, idx, bp->eth_dev->data->port_id);
3761                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3762                 mz = rte_memzone_lookup(mz_name);
3763                 if (!mz) {
3764                         mz = rte_memzone_reserve_aligned(mz_name,
3765                                                 rmem->nr_pages * 8,
3766                                                 SOCKET_ID_ANY,
3767                                                 RTE_MEMZONE_2MB |
3768                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
3769                                                 RTE_MEMZONE_IOVA_CONTIG,
3770                                                 BNXT_PAGE_SIZE);
3771                         if (mz == NULL)
3772                                 return -ENOMEM;
3773                 }
3774
3775                 memset(mz->addr, 0, mz->len);
3776                 mz_phys_addr = mz->iova;
3777                 if ((unsigned long)mz->addr == mz_phys_addr) {
3778                         PMD_DRV_LOG(WARNING,
3779                                 "Memzone physical address same as virtual.\n");
3780                         PMD_DRV_LOG(WARNING,
3781                                     "Using rte_mem_virt2iova()\n");
3782                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3783                         if (mz_phys_addr == RTE_BAD_IOVA) {
3784                                 PMD_DRV_LOG(ERR,
3785                                         "unable to map addr to phys memory\n");
3786                                 return -ENOMEM;
3787                         }
3788                 }
3789                 rte_mem_lock_page(((char *)mz->addr));
3790
3791                 rmem->pg_tbl = mz->addr;
3792                 rmem->pg_tbl_map = mz_phys_addr;
3793                 rmem->pg_tbl_mz = mz;
3794         }
3795
3796         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
3797                  suffix, idx, bp->eth_dev->data->port_id);
3798         mz = rte_memzone_lookup(mz_name);
3799         if (!mz) {
3800                 mz = rte_memzone_reserve_aligned(mz_name,
3801                                                  mem_size,
3802                                                  SOCKET_ID_ANY,
3803                                                  RTE_MEMZONE_1GB |
3804                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
3805                                                  RTE_MEMZONE_IOVA_CONTIG,
3806                                                  BNXT_PAGE_SIZE);
3807                 if (mz == NULL)
3808                         return -ENOMEM;
3809         }
3810
3811         memset(mz->addr, 0, mz->len);
3812         mz_phys_addr = mz->iova;
3813         if ((unsigned long)mz->addr == mz_phys_addr) {
3814                 PMD_DRV_LOG(WARNING,
3815                             "Memzone physical address same as virtual.\n");
3816                 PMD_DRV_LOG(WARNING,
3817                             "Using rte_mem_virt2iova()\n");
3818                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
3819                         rte_mem_lock_page(((char *)mz->addr) + sz);
3820                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3821                 if (mz_phys_addr == RTE_BAD_IOVA) {
3822                         PMD_DRV_LOG(ERR,
3823                                     "unable to map addr to phys memory\n");
3824                         return -ENOMEM;
3825                 }
3826         }
3827
3828         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
3829                 rte_mem_lock_page(((char *)mz->addr) + sz);
3830                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
3831                 rmem->dma_arr[i] = mz_phys_addr + sz;
3832
3833                 if (rmem->nr_pages > 1) {
3834                         if (i == rmem->nr_pages - 2 &&
3835                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3836                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
3837                         else if (i == rmem->nr_pages - 1 &&
3838                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3839                                 valid_bits |= PTU_PTE_LAST;
3840
3841                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
3842                                                            valid_bits);
3843                 }
3844         }
3845
3846         rmem->mz = mz;
3847         if (rmem->vmem_size)
3848                 rmem->vmem = (void **)mz->addr;
3849         rmem->dma_arr[0] = mz_phys_addr;
3850         return 0;
3851 }
3852
3853 static void bnxt_free_ctx_mem(struct bnxt *bp)
3854 {
3855         int i;
3856
3857         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
3858                 return;
3859
3860         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
3861         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
3862         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
3863         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
3864         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
3865         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
3866         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
3867         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
3868         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
3869         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
3870         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
3871
3872         for (i = 0; i < BNXT_MAX_Q; i++) {
3873                 if (bp->ctx->tqm_mem[i])
3874                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
3875         }
3876
3877         rte_free(bp->ctx);
3878         bp->ctx = NULL;
3879 }
3880
3881 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
3882
3883 #define min_t(type, x, y) ({                    \
3884         type __min1 = (x);                      \
3885         type __min2 = (y);                      \
3886         __min1 < __min2 ? __min1 : __min2; })
3887
3888 #define max_t(type, x, y) ({                    \
3889         type __max1 = (x);                      \
3890         type __max2 = (y);                      \
3891         __max1 > __max2 ? __max1 : __max2; })
3892
3893 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
3894
3895 int bnxt_alloc_ctx_mem(struct bnxt *bp)
3896 {
3897         struct bnxt_ctx_pg_info *ctx_pg;
3898         struct bnxt_ctx_mem_info *ctx;
3899         uint32_t mem_size, ena, entries;
3900         int i, rc;
3901
3902         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
3903         if (rc) {
3904                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
3905                 return rc;
3906         }
3907         ctx = bp->ctx;
3908         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
3909                 return 0;
3910
3911         ctx_pg = &ctx->qp_mem;
3912         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
3913         mem_size = ctx->qp_entry_size * ctx_pg->entries;
3914         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
3915         if (rc)
3916                 return rc;
3917
3918         ctx_pg = &ctx->srq_mem;
3919         ctx_pg->entries = ctx->srq_max_l2_entries;
3920         mem_size = ctx->srq_entry_size * ctx_pg->entries;
3921         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
3922         if (rc)
3923                 return rc;
3924
3925         ctx_pg = &ctx->cq_mem;
3926         ctx_pg->entries = ctx->cq_max_l2_entries;
3927         mem_size = ctx->cq_entry_size * ctx_pg->entries;
3928         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
3929         if (rc)
3930                 return rc;
3931
3932         ctx_pg = &ctx->vnic_mem;
3933         ctx_pg->entries = ctx->vnic_max_vnic_entries +
3934                 ctx->vnic_max_ring_table_entries;
3935         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
3936         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
3937         if (rc)
3938                 return rc;
3939
3940         ctx_pg = &ctx->stat_mem;
3941         ctx_pg->entries = ctx->stat_max_entries;
3942         mem_size = ctx->stat_entry_size * ctx_pg->entries;
3943         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
3944         if (rc)
3945                 return rc;
3946
3947         entries = ctx->qp_max_l2_entries;
3948         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
3949         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
3950                           ctx->tqm_max_entries_per_ring);
3951         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
3952                 ctx_pg = ctx->tqm_mem[i];
3953                 /* use min tqm entries for now. */
3954                 ctx_pg->entries = entries;
3955                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
3956                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
3957                 if (rc)
3958                         return rc;
3959                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
3960         }
3961
3962         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
3963         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
3964         if (rc)
3965                 PMD_DRV_LOG(ERR,
3966                             "Failed to configure context mem: rc = %d\n", rc);
3967         else
3968                 ctx->flags |= BNXT_CTX_FLAG_INITED;
3969
3970         return rc;
3971 }
3972
3973 static int bnxt_alloc_stats_mem(struct bnxt *bp)
3974 {
3975         struct rte_pci_device *pci_dev = bp->pdev;
3976         char mz_name[RTE_MEMZONE_NAMESIZE];
3977         const struct rte_memzone *mz = NULL;
3978         uint32_t total_alloc_len;
3979         rte_iova_t mz_phys_addr;
3980
3981         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
3982                 return 0;
3983
3984         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3985                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3986                  pci_dev->addr.bus, pci_dev->addr.devid,
3987                  pci_dev->addr.function, "rx_port_stats");
3988         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3989         mz = rte_memzone_lookup(mz_name);
3990         total_alloc_len =
3991                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
3992                                        sizeof(struct rx_port_stats_ext) + 512);
3993         if (!mz) {
3994                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3995                                          SOCKET_ID_ANY,
3996                                          RTE_MEMZONE_2MB |
3997                                          RTE_MEMZONE_SIZE_HINT_ONLY |
3998                                          RTE_MEMZONE_IOVA_CONTIG);
3999                 if (mz == NULL)
4000                         return -ENOMEM;
4001         }
4002         memset(mz->addr, 0, mz->len);
4003         mz_phys_addr = mz->iova;
4004         if ((unsigned long)mz->addr == mz_phys_addr) {
4005                 PMD_DRV_LOG(WARNING,
4006                             "Memzone physical address same as virtual.\n");
4007                 PMD_DRV_LOG(WARNING,
4008                             "Using rte_mem_virt2iova()\n");
4009                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4010                 if (mz_phys_addr == RTE_BAD_IOVA) {
4011                         PMD_DRV_LOG(ERR,
4012                                     "Can't map address to physical memory\n");
4013                         return -ENOMEM;
4014                 }
4015         }
4016
4017         bp->rx_mem_zone = (const void *)mz;
4018         bp->hw_rx_port_stats = mz->addr;
4019         bp->hw_rx_port_stats_map = mz_phys_addr;
4020
4021         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4022                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4023                  pci_dev->addr.bus, pci_dev->addr.devid,
4024                  pci_dev->addr.function, "tx_port_stats");
4025         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4026         mz = rte_memzone_lookup(mz_name);
4027         total_alloc_len =
4028                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4029                                        sizeof(struct tx_port_stats_ext) + 512);
4030         if (!mz) {
4031                 mz = rte_memzone_reserve(mz_name,
4032                                          total_alloc_len,
4033                                          SOCKET_ID_ANY,
4034                                          RTE_MEMZONE_2MB |
4035                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4036                                          RTE_MEMZONE_IOVA_CONTIG);
4037                 if (mz == NULL)
4038                         return -ENOMEM;
4039         }
4040         memset(mz->addr, 0, mz->len);
4041         mz_phys_addr = mz->iova;
4042         if ((unsigned long)mz->addr == mz_phys_addr) {
4043                 PMD_DRV_LOG(WARNING,
4044                             "Memzone physical address same as virtual\n");
4045                 PMD_DRV_LOG(WARNING,
4046                             "Using rte_mem_virt2iova()\n");
4047                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4048                 if (mz_phys_addr == RTE_BAD_IOVA) {
4049                         PMD_DRV_LOG(ERR,
4050                                     "Can't map address to physical memory\n");
4051                         return -ENOMEM;
4052                 }
4053         }
4054
4055         bp->tx_mem_zone = (const void *)mz;
4056         bp->hw_tx_port_stats = mz->addr;
4057         bp->hw_tx_port_stats_map = mz_phys_addr;
4058         bp->flags |= BNXT_FLAG_PORT_STATS;
4059
4060         /* Display extended statistics if FW supports it */
4061         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4062             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4063             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4064                 return 0;
4065
4066         bp->hw_rx_port_stats_ext = (void *)
4067                 ((uint8_t *)bp->hw_rx_port_stats +
4068                  sizeof(struct rx_port_stats));
4069         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4070                 sizeof(struct rx_port_stats);
4071         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4072
4073         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4074             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4075                 bp->hw_tx_port_stats_ext = (void *)
4076                         ((uint8_t *)bp->hw_tx_port_stats +
4077                          sizeof(struct tx_port_stats));
4078                 bp->hw_tx_port_stats_ext_map =
4079                         bp->hw_tx_port_stats_map +
4080                         sizeof(struct tx_port_stats);
4081                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4082         }
4083
4084         return 0;
4085 }
4086
4087 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4088 {
4089         struct bnxt *bp = eth_dev->data->dev_private;
4090         int rc = 0;
4091
4092         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4093                                                RTE_ETHER_ADDR_LEN *
4094                                                bp->max_l2_ctx,
4095                                                0);
4096         if (eth_dev->data->mac_addrs == NULL) {
4097                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4098                 return -ENOMEM;
4099         }
4100
4101         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4102                 if (BNXT_PF(bp))
4103                         return -EINVAL;
4104
4105                 /* Generate a random MAC address, if none was assigned by PF */
4106                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4107                 bnxt_eth_hw_addr_random(bp->mac_addr);
4108                 PMD_DRV_LOG(INFO,
4109                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4110                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4111                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4112
4113                 rc = bnxt_hwrm_set_mac(bp);
4114                 if (!rc)
4115                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4116                                RTE_ETHER_ADDR_LEN);
4117                 return rc;
4118         }
4119
4120         /* Copy the permanent MAC from the FUNC_QCAPS response */
4121         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4122         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4123
4124         return rc;
4125 }
4126
4127 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4128 {
4129         int rc = 0;
4130
4131         /* MAC is already configured in FW */
4132         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4133                 return 0;
4134
4135         /* Restore the old MAC configured */
4136         rc = bnxt_hwrm_set_mac(bp);
4137         if (rc)
4138                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4139
4140         return rc;
4141 }
4142
4143 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4144 {
4145         if (!BNXT_PF(bp))
4146                 return;
4147
4148 #define ALLOW_FUNC(x)   \
4149         { \
4150                 uint32_t arg = (x); \
4151                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4152                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4153         }
4154
4155         /* Forward all requests if firmware is new enough */
4156         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4157              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4158             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4159                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4160         } else {
4161                 PMD_DRV_LOG(WARNING,
4162                             "Firmware too old for VF mailbox functionality\n");
4163                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4164         }
4165
4166         /*
4167          * The following are used for driver cleanup. If we disallow these,
4168          * VF drivers can't clean up cleanly.
4169          */
4170         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4171         ALLOW_FUNC(HWRM_VNIC_FREE);
4172         ALLOW_FUNC(HWRM_RING_FREE);
4173         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4174         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4175         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4176         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4177         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4178         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4179 }
4180
4181 static int bnxt_init_fw(struct bnxt *bp)
4182 {
4183         uint16_t mtu;
4184         int rc = 0;
4185
4186         rc = bnxt_hwrm_ver_get(bp);
4187         if (rc)
4188                 return rc;
4189
4190         rc = bnxt_hwrm_func_reset(bp);
4191         if (rc)
4192                 return -EIO;
4193
4194         rc = bnxt_hwrm_queue_qportcfg(bp);
4195         if (rc)
4196                 return rc;
4197
4198         /* Get the MAX capabilities for this function */
4199         rc = bnxt_hwrm_func_qcaps(bp);
4200         if (rc)
4201                 return rc;
4202
4203         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4204         if (rc)
4205                 return rc;
4206
4207         /* Get the adapter error recovery support info */
4208         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4209         if (rc)
4210                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4211
4212         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4213             mtu != bp->eth_dev->data->mtu)
4214                 bp->eth_dev->data->mtu = mtu;
4215
4216         bnxt_hwrm_port_led_qcaps(bp);
4217
4218         return 0;
4219 }
4220
4221 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4222 {
4223         int rc;
4224
4225         rc = bnxt_init_fw(bp);
4226         if (rc)
4227                 return rc;
4228
4229         if (!reconfig_dev) {
4230                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4231                 if (rc)
4232                         return rc;
4233         } else {
4234                 rc = bnxt_restore_dflt_mac(bp);
4235                 if (rc)
4236                         return rc;
4237         }
4238
4239         bnxt_config_vf_req_fwd(bp);
4240
4241         rc = bnxt_hwrm_func_driver_register(bp);
4242         if (rc) {
4243                 PMD_DRV_LOG(ERR, "Failed to register driver");
4244                 return -EBUSY;
4245         }
4246
4247         if (BNXT_PF(bp)) {
4248                 if (bp->pdev->max_vfs) {
4249                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4250                         if (rc) {
4251                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4252                                 return rc;
4253                         }
4254                 } else {
4255                         rc = bnxt_hwrm_allocate_pf_only(bp);
4256                         if (rc) {
4257                                 PMD_DRV_LOG(ERR,
4258                                             "Failed to allocate PF resources");
4259                                 return rc;
4260                         }
4261                 }
4262         }
4263
4264         rc = bnxt_alloc_mem(bp, reconfig_dev);
4265         if (rc)
4266                 return rc;
4267
4268         rc = bnxt_setup_int(bp);
4269         if (rc)
4270                 return rc;
4271
4272         bnxt_init_nic(bp);
4273
4274         rc = bnxt_request_int(bp);
4275         if (rc)
4276                 return rc;
4277
4278         return 0;
4279 }
4280
4281 static int
4282 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4283 {
4284         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4285         static int version_printed;
4286         struct bnxt *bp;
4287         int rc;
4288
4289         if (version_printed++ == 0)
4290                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4291
4292         rte_eth_copy_pci_info(eth_dev, pci_dev);
4293
4294         bp = eth_dev->data->dev_private;
4295
4296         bp->dev_stopped = 1;
4297
4298         eth_dev->dev_ops = &bnxt_dev_ops;
4299         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4300         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4301
4302         /*
4303          * For secondary processes, we don't initialise any further
4304          * as primary has already done this work.
4305          */
4306         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4307                 return 0;
4308
4309         if (bnxt_vf_pciid(pci_dev->id.device_id))
4310                 bp->flags |= BNXT_FLAG_VF;
4311
4312         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4313             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4314             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4315             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4316             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4317                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4318
4319         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4320             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4321             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4322             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4323                 bp->flags |= BNXT_FLAG_STINGRAY;
4324
4325         rc = bnxt_init_board(eth_dev);
4326         if (rc) {
4327                 PMD_DRV_LOG(ERR,
4328                             "Failed to initialize board rc: %x\n", rc);
4329                 return rc;
4330         }
4331
4332         rc = bnxt_alloc_hwrm_resources(bp);
4333         if (rc) {
4334                 PMD_DRV_LOG(ERR,
4335                             "Failed to allocate hwrm resource rc: %x\n", rc);
4336                 goto error_free;
4337         }
4338         rc = bnxt_init_resources(bp, false);
4339         if (rc)
4340                 goto error_free;
4341
4342         rc = bnxt_alloc_stats_mem(bp);
4343         if (rc)
4344                 goto error_free;
4345
4346         PMD_DRV_LOG(INFO,
4347                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4348                     pci_dev->mem_resource[0].phys_addr,
4349                     pci_dev->mem_resource[0].addr);
4350
4351         return 0;
4352
4353 error_free:
4354         bnxt_dev_uninit(eth_dev);
4355         return rc;
4356 }
4357
4358 static int
4359 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4360 {
4361         int rc;
4362
4363         bnxt_disable_int(bp);
4364         bnxt_free_int(bp);
4365         bnxt_free_mem(bp, reconfig_dev);
4366         bnxt_hwrm_func_buf_unrgtr(bp);
4367         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4368         bp->flags &= ~BNXT_FLAG_REGISTERED;
4369         bnxt_free_ctx_mem(bp);
4370         if (!reconfig_dev) {
4371                 bnxt_free_hwrm_resources(bp);
4372
4373                 if (bp->recovery_info != NULL) {
4374                         rte_free(bp->recovery_info);
4375                         bp->recovery_info = NULL;
4376                 }
4377         }
4378
4379         return rc;
4380 }
4381
4382 static int
4383 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4384 {
4385         struct bnxt *bp = eth_dev->data->dev_private;
4386         int rc;
4387
4388         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4389                 return -EPERM;
4390
4391         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4392
4393         rc = bnxt_uninit_resources(bp, false);
4394
4395         if (bp->grp_info != NULL) {
4396                 rte_free(bp->grp_info);
4397                 bp->grp_info = NULL;
4398         }
4399
4400         if (bp->tx_mem_zone) {
4401                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4402                 bp->tx_mem_zone = NULL;
4403         }
4404
4405         if (bp->rx_mem_zone) {
4406                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4407                 bp->rx_mem_zone = NULL;
4408         }
4409
4410         if (bp->dev_stopped == 0)
4411                 bnxt_dev_close_op(eth_dev);
4412         if (bp->pf.vf_info)
4413                 rte_free(bp->pf.vf_info);
4414         eth_dev->dev_ops = NULL;
4415         eth_dev->rx_pkt_burst = NULL;
4416         eth_dev->tx_pkt_burst = NULL;
4417
4418         return rc;
4419 }
4420
4421 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4422         struct rte_pci_device *pci_dev)
4423 {
4424         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4425                 bnxt_dev_init);
4426 }
4427
4428 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4429 {
4430         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4431                 return rte_eth_dev_pci_generic_remove(pci_dev,
4432                                 bnxt_dev_uninit);
4433         else
4434                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4435 }
4436
4437 static struct rte_pci_driver bnxt_rte_pmd = {
4438         .id_table = bnxt_pci_id_map,
4439         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4440         .probe = bnxt_pci_probe,
4441         .remove = bnxt_pci_remove,
4442 };
4443
4444 static bool
4445 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4446 {
4447         if (strcmp(dev->device->driver->name, drv->driver.name))
4448                 return false;
4449
4450         return true;
4451 }
4452
4453 bool is_bnxt_supported(struct rte_eth_dev *dev)
4454 {
4455         return is_device_supported(dev, &bnxt_rte_pmd);
4456 }
4457
4458 RTE_INIT(bnxt_init_log)
4459 {
4460         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4461         if (bnxt_logtype_driver >= 0)
4462                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4463 }
4464
4465 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4466 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4467 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");