drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 /*
  37  * The set of PCI devices this driver supports
  38  */
  39 static const struct rte_pci_id bnxt_pci_id_map[] = {
  40         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  41                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  93         { .vendor_id = 0, /* sentinel */ },
  94 };
  95
  96 #define BNXT_ETH_RSS_SUPPORT (  \
  97         ETH_RSS_IPV4 |          \
  98         ETH_RSS_NONFRAG_IPV4_TCP |      \
  99         ETH_RSS_NONFRAG_IPV4_UDP |      \
 100         ETH_RSS_IPV6 |          \
 101         ETH_RSS_NONFRAG_IPV6_TCP |      \
 102         ETH_RSS_NONFRAG_IPV6_UDP)
 103
 104 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 105                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 106                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 108                                      DEV_TX_OFFLOAD_TCP_TSO | \
 109                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 110                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 114                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 115                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 116
 117 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 118                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 119                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 120                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 122                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 123                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 124                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 125                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 126                                      DEV_RX_OFFLOAD_TCP_LRO | \
 127                                      DEV_RX_OFFLOAD_SCATTER | \
 128                                      DEV_RX_OFFLOAD_RSS_HASH)
 129
 130 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
 131 static const char *const bnxt_dev_args[] = {
 132         BNXT_DEVARG_TRUFLOW,
 133         NULL
 134 };
 135
 136 /*
 137  * truflow == false to disable the feature
 138  * truflow == true to enable the feature
 139  */
 140 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 141
 142 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 143 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 144 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 145 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 146 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 147 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 148 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 149 static void bnxt_dev_recover(void *arg);
 150
 151 int is_bnxt_in_error(struct bnxt *bp)
 152 {
 153         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 154                 return -EIO;
 155         if (bp->flags & BNXT_FLAG_FW_RESET)
 156                 return -EBUSY;
 157
 158         return 0;
 159 }
 160
 161 /***********************/
 162
 163 /*
 164  * High level utility functions
 165  */
 166
 167 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 168 {
 169         if (!BNXT_CHIP_THOR(bp))
 170                 return 1;
 171
 172         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 173                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 174                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 175 }
 176
 177 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 178 {
 179         if (!BNXT_CHIP_THOR(bp))
 180                 return HW_HASH_INDEX_SIZE;
 181
 182         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 183 }
 184
 185 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 186 {
 187         bnxt_free_filter_mem(bp);
 188         bnxt_free_vnic_attributes(bp);
 189         bnxt_free_vnic_mem(bp);
 190
 191         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 192          * If the number of rings change across fw update,
 193          * we don't have much choice except to warn the user.
 194          */
 195         if (!reconfig) {
 196                 bnxt_free_stats(bp);
 197                 bnxt_free_tx_rings(bp);
 198                 bnxt_free_rx_rings(bp);
 199         }
 200         bnxt_free_async_cp_ring(bp);
 201         bnxt_free_rxtx_nq_ring(bp);
 202
 203         rte_free(bp->grp_info);
 204         bp->grp_info = NULL;
 205 }
 206
 207 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 208 {
 209         int rc;
 210
 211         rc = bnxt_alloc_ring_grps(bp);
 212         if (rc)
 213                 goto alloc_mem_err;
 214
 215         rc = bnxt_alloc_async_ring_struct(bp);
 216         if (rc)
 217                 goto alloc_mem_err;
 218
 219         rc = bnxt_alloc_vnic_mem(bp);
 220         if (rc)
 221                 goto alloc_mem_err;
 222
 223         rc = bnxt_alloc_vnic_attributes(bp);
 224         if (rc)
 225                 goto alloc_mem_err;
 226
 227         rc = bnxt_alloc_filter_mem(bp);
 228         if (rc)
 229                 goto alloc_mem_err;
 230
 231         rc = bnxt_alloc_async_cp_ring(bp);
 232         if (rc)
 233                 goto alloc_mem_err;
 234
 235         rc = bnxt_alloc_rxtx_nq_ring(bp);
 236         if (rc)
 237                 goto alloc_mem_err;
 238
 239         return 0;
 240
 241 alloc_mem_err:
 242         bnxt_free_mem(bp, reconfig);
 243         return rc;
 244 }
 245
 246 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 247 {
 248         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 249         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 250         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 251         struct bnxt_rx_queue *rxq;
 252         unsigned int j;
 253         int rc;
 254
 255         rc = bnxt_vnic_grp_alloc(bp, vnic);
 256         if (rc)
 257                 goto err_out;
 258
 259         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 260                     vnic_id, vnic, vnic->fw_grp_ids);
 261
 262         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 263         if (rc)
 264                 goto err_out;
 265
 266         /* Alloc RSS context only if RSS mode is enabled */
 267         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 268                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 269
 270                 rc = 0;
 271                 for (j = 0; j < nr_ctxs; j++) {
 272                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 273                         if (rc)
 274                                 break;
 275                 }
 276                 if (rc) {
 277                         PMD_DRV_LOG(ERR,
 278                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 279                                     vnic_id, j, rc);
 280                         goto err_out;
 281                 }
 282                 vnic->num_lb_ctxts = nr_ctxs;
 283         }
 284
 285         /*
 286          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 287          * setting is not available at this time, it will not be
 288          * configured correctly in the CFA.
 289          */
 290         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 291                 vnic->vlan_strip = true;
 292         else
 293                 vnic->vlan_strip = false;
 294
 295         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 296         if (rc)
 297                 goto err_out;
 298
 299         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 300         if (rc)
 301                 goto err_out;
 302
 303         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 304                 rxq = bp->eth_dev->data->rx_queues[j];
 305
 306                 PMD_DRV_LOG(DEBUG,
 307                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 308                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 309
 310                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 311                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 312                 else
 313                         vnic->rx_queue_cnt++;
 314         }
 315
 316         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 317
 318         rc = bnxt_vnic_rss_configure(bp, vnic);
 319         if (rc)
 320                 goto err_out;
 321
 322         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 323
 324         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 325                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 326         else
 327                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 328
 329         return 0;
 330 err_out:
 331         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 332                     vnic_id, rc);
 333         return rc;
 334 }
 335
 336 static int bnxt_init_chip(struct bnxt *bp)
 337 {
 338         struct rte_eth_link new;
 339         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 340         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 341         uint32_t intr_vector = 0;
 342         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 343         uint32_t vec = BNXT_MISC_VEC_ID;
 344         unsigned int i, j;
 345         int rc;
 346
 347         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 348                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 349                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 350                 bp->flags |= BNXT_FLAG_JUMBO;
 351         } else {
 352                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 353                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 354                 bp->flags &= ~BNXT_FLAG_JUMBO;
 355         }
 356
 357         /* THOR does not support ring groups.
 358          * But we will use the array to save RSS context IDs.
 359          */
 360         if (BNXT_CHIP_THOR(bp))
 361                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 362
 363         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 364         if (rc) {
 365                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 366                 goto err_out;
 367         }
 368
 369         rc = bnxt_alloc_hwrm_rings(bp);
 370         if (rc) {
 371                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 372                 goto err_out;
 373         }
 374
 375         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 376         if (rc) {
 377                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 378                 goto err_out;
 379         }
 380
 381         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 382                 goto skip_cosq_cfg;
 383
 384         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 385                 if (bp->rx_cos_queue[i].id != 0xff) {
 386                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 387
 388                         if (!vnic) {
 389                                 PMD_DRV_LOG(ERR,
 390                                             "Num pools more than FW profile\n");
 391                                 rc = -EINVAL;
 392                                 goto err_out;
 393                         }
 394                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 395                         bp->rx_cosq_cnt++;
 396                 }
 397         }
 398
 399 skip_cosq_cfg:
 400         rc = bnxt_mq_rx_configure(bp);
 401         if (rc) {
 402                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 403                 goto err_out;
 404         }
 405
 406         /* VNIC configuration */
 407         for (i = 0; i < bp->nr_vnics; i++) {
 408                 rc = bnxt_setup_one_vnic(bp, i);
 409                 if (rc)
 410                         goto err_out;
 411         }
 412
 413         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 414         if (rc) {
 415                 PMD_DRV_LOG(ERR,
 416                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 417                 goto err_out;
 418         }
 419
 420         /* check and configure queue intr-vector mapping */
 421         if ((rte_intr_cap_multiple(intr_handle) ||
 422              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 423             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 424                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 425                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 426                 if (intr_vector > bp->rx_cp_nr_rings) {
 427                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 428                                         bp->rx_cp_nr_rings);
 429                         return -ENOTSUP;
 430                 }
 431                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 432                 if (rc)
 433                         return rc;
 434         }
 435
 436         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 437                 intr_handle->intr_vec =
 438                         rte_zmalloc("intr_vec",
 439                                     bp->eth_dev->data->nb_rx_queues *
 440                                     sizeof(int), 0);
 441                 if (intr_handle->intr_vec == NULL) {
 442                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 443                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 444                         rc = -ENOMEM;
 445                         goto err_disable;
 446                 }
 447                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 448                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 449                          intr_handle->intr_vec, intr_handle->nb_efd,
 450                         intr_handle->max_intr);
 451                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 452                      queue_id++) {
 453                         intr_handle->intr_vec[queue_id] =
 454                                                         vec + BNXT_RX_VEC_START;
 455                         if (vec < base + intr_handle->nb_efd - 1)
 456                                 vec++;
 457                 }
 458         }
 459
 460         /* enable uio/vfio intr/eventfd mapping */
 461         rc = rte_intr_enable(intr_handle);
 462 #ifndef RTE_EXEC_ENV_FREEBSD
 463         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 464         if (rc)
 465                 goto err_free;
 466 #endif
 467
 468         rc = bnxt_get_hwrm_link_config(bp, &new);
 469         if (rc) {
 470                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 471                 goto err_free;
 472         }
 473
 474         if (!bp->link_info.link_up) {
 475                 rc = bnxt_set_hwrm_link_config(bp, true);
 476                 if (rc) {
 477                         PMD_DRV_LOG(ERR,
 478                                 "HWRM link config failure rc: %x\n", rc);
 479                         goto err_free;
 480                 }
 481         }
 482         bnxt_print_link_info(bp->eth_dev);
 483
 484         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 485         if (!bp->mark_table)
 486                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 487
 488         return 0;
 489
 490 err_free:
 491         rte_free(intr_handle->intr_vec);
 492 err_disable:
 493         rte_intr_efd_disable(intr_handle);
 494 err_out:
 495         /* Some of the error status returned by FW may not be from errno.h */
 496         if (rc > 0)
 497                 rc = -EIO;
 498
 499         return rc;
 500 }
 501
 502 static int bnxt_shutdown_nic(struct bnxt *bp)
 503 {
 504         bnxt_free_all_hwrm_resources(bp);
 505         bnxt_free_all_filters(bp);
 506         bnxt_free_all_vnics(bp);
 507         return 0;
 508 }
 509
 510 /*
 511  * Device configuration and status function
 512  */
 513
 514 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 515                                 struct rte_eth_dev_info *dev_info)
 516 {
 517         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 518         struct bnxt *bp = eth_dev->data->dev_private;
 519         uint16_t max_vnics, i, j, vpool, vrxq;
 520         unsigned int max_rx_rings;
 521         int rc;
 522
 523         rc = is_bnxt_in_error(bp);
 524         if (rc)
 525                 return rc;
 526
 527         /* MAC Specifics */
 528         dev_info->max_mac_addrs = bp->max_l2_ctx;
 529         dev_info->max_hash_mac_addrs = 0;
 530
 531         /* PF/VF specifics */
 532         if (BNXT_PF(bp))
 533                 dev_info->max_vfs = pdev->max_vfs;
 534
 535         max_rx_rings = BNXT_MAX_RINGS(bp);
 536         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 537         dev_info->max_rx_queues = max_rx_rings;
 538         dev_info->max_tx_queues = max_rx_rings;
 539         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 540         dev_info->hash_key_size = 40;
 541         max_vnics = bp->max_vnics;
 542
 543         /* MTU specifics */
 544         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 545         dev_info->max_mtu = BNXT_MAX_MTU;
 546
 547         /* Fast path specifics */
 548         dev_info->min_rx_bufsize = 1;
 549         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 550
 551         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 552         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 553                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 554         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 555         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 556
 557         /* *INDENT-OFF* */
 558         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 559                 .rx_thresh = {
 560                         .pthresh = 8,
 561                         .hthresh = 8,
 562                         .wthresh = 0,
 563                 },
 564                 .rx_free_thresh = 32,
 565                 /* If no descriptors available, pkts are dropped by default */
 566                 .rx_drop_en = 1,
 567         };
 568
 569         dev_info->default_txconf = (struct rte_eth_txconf) {
 570                 .tx_thresh = {
 571                         .pthresh = 32,
 572                         .hthresh = 0,
 573                         .wthresh = 0,
 574                 },
 575                 .tx_free_thresh = 32,
 576                 .tx_rs_thresh = 32,
 577         };
 578         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 579
 580         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 581         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 582         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 583         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 584         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 585
 586         /* *INDENT-ON* */
 587
 588         /*
 589          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 590          *       need further investigation.
 591          */
 592
 593         /* VMDq resources */
 594         vpool = 64; /* ETH_64_POOLS */
 595         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 596         for (i = 0; i < 4; vpool >>= 1, i++) {
 597                 if (max_vnics > vpool) {
 598                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 599                                 if (dev_info->max_rx_queues > vrxq) {
 600                                         if (vpool > vrxq)
 601                                                 vpool = vrxq;
 602                                         goto found;
 603                                 }
 604                         }
 605                         /* Not enough resources to support VMDq */
 606                         break;
 607                 }
 608         }
 609         /* Not enough resources to support VMDq */
 610         vpool = 0;
 611         vrxq = 0;
 612 found:
 613         dev_info->max_vmdq_pools = vpool;
 614         dev_info->vmdq_queue_num = vrxq;
 615
 616         dev_info->vmdq_pool_base = 0;
 617         dev_info->vmdq_queue_base = 0;
 618
 619         return 0;
 620 }
 621
 622 /* Configure the device based on the configuration provided */
 623 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 624 {
 625         struct bnxt *bp = eth_dev->data->dev_private;
 626         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 627         int rc;
 628
 629         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 630         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 631         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 632         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 633
 634         rc = is_bnxt_in_error(bp);
 635         if (rc)
 636                 return rc;
 637
 638         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 639                 rc = bnxt_hwrm_check_vf_rings(bp);
 640                 if (rc) {
 641                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 642                         return -ENOSPC;
 643                 }
 644
 645                 /* If a resource has already been allocated - in this case
 646                  * it is the async completion ring, free it. Reallocate it after
 647                  * resource reservation. This will ensure the resource counts
 648                  * are calculated correctly.
 649                  */
 650
 651                 pthread_mutex_lock(&bp->def_cp_lock);
 652
 653                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 654                         bnxt_disable_int(bp);
 655                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 656                 }
 657
 658                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 659                 if (rc) {
 660                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 661                         pthread_mutex_unlock(&bp->def_cp_lock);
 662                         return -ENOSPC;
 663                 }
 664
 665                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 666                         rc = bnxt_alloc_async_cp_ring(bp);
 667                         if (rc) {
 668                                 pthread_mutex_unlock(&bp->def_cp_lock);
 669                                 return rc;
 670                         }
 671                         bnxt_enable_int(bp);
 672                 }
 673
 674                 pthread_mutex_unlock(&bp->def_cp_lock);
 675         } else {
 676                 /* legacy driver needs to get updated values */
 677                 rc = bnxt_hwrm_func_qcaps(bp);
 678                 if (rc) {
 679                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 680                         return rc;
 681                 }
 682         }
 683
 684         /* Inherit new configurations */
 685         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 686             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 687             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 688                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 689             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 690             bp->max_stat_ctx)
 691                 goto resource_error;
 692
 693         if (BNXT_HAS_RING_GRPS(bp) &&
 694             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 695                 goto resource_error;
 696
 697         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 698             bp->max_vnics < eth_dev->data->nb_rx_queues)
 699                 goto resource_error;
 700
 701         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 702         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 703
 704         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 705                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 706         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
 707
 708         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 709                 eth_dev->data->mtu =
 710                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 711                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 712                         BNXT_NUM_VLANS;
 713                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 714         }
 715         return 0;
 716
 717 resource_error:
 718         PMD_DRV_LOG(ERR,
 719                     "Insufficient resources to support requested config\n");
 720         PMD_DRV_LOG(ERR,
 721                     "Num Queues Requested: Tx %d, Rx %d\n",
 722                     eth_dev->data->nb_tx_queues,
 723                     eth_dev->data->nb_rx_queues);
 724         PMD_DRV_LOG(ERR,
 725                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 726                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 727                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 728         return -ENOSPC;
 729 }
 730
 731 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 732 {
 733         struct rte_eth_link *link = &eth_dev->data->dev_link;
 734
 735         if (link->link_status)
 736                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 737                         eth_dev->data->port_id,
 738                         (uint32_t)link->link_speed,
 739                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 740                         ("full-duplex") : ("half-duplex\n"));
 741         else
 742                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 743                         eth_dev->data->port_id);
 744 }
 745
 746 /*
 747  * Determine whether the current configuration requires support for scattered
 748  * receive; return 1 if scattered receive is required and 0 if not.
 749  */
 750 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 751 {
 752         uint16_t buf_size;
 753         int i;
 754
 755         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 756                 return 1;
 757
 758         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 759                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 760
 761                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 762                                       RTE_PKTMBUF_HEADROOM);
 763                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 764                         return 1;
 765         }
 766         return 0;
 767 }
 768
 769 static eth_rx_burst_t
 770 bnxt_receive_function(struct rte_eth_dev *eth_dev)
 771 {
 772         struct bnxt *bp = eth_dev->data->dev_private;
 773
 774 #ifdef RTE_ARCH_X86
 775 #ifndef RTE_LIBRTE_IEEE1588
 776         /*
 777          * Vector mode receive can be enabled only if scatter rx is not
 778          * in use and rx offloads are limited to VLAN stripping and
 779          * CRC stripping.
 780          */
 781         if (!eth_dev->data->scattered_rx &&
 782             !(eth_dev->data->dev_conf.rxmode.offloads &
 783               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 784                 DEV_RX_OFFLOAD_KEEP_CRC |
 785                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 786                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 787                 DEV_RX_OFFLOAD_UDP_CKSUM |
 788                 DEV_RX_OFFLOAD_TCP_CKSUM |
 789                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 790                 DEV_RX_OFFLOAD_RSS_HASH |
 791                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 792                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 793                             eth_dev->data->port_id);
 794                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
 795                 return bnxt_recv_pkts_vec;
 796         }
 797         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 798                     eth_dev->data->port_id);
 799         PMD_DRV_LOG(INFO,
 800                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 801                     eth_dev->data->port_id,
 802                     eth_dev->data->scattered_rx,
 803                     eth_dev->data->dev_conf.rxmode.offloads);
 804 #endif
 805 #endif
 806         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
 807         return bnxt_recv_pkts;
 808 }
 809
 810 static eth_tx_burst_t
 811 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 812 {
 813 #ifdef RTE_ARCH_X86
 814 #ifndef RTE_LIBRTE_IEEE1588
 815         /*
 816          * Vector mode transmit can be enabled only if not using scatter rx
 817          * or tx offloads.
 818          */
 819         if (!eth_dev->data->scattered_rx &&
 820             !eth_dev->data->dev_conf.txmode.offloads) {
 821                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 822                             eth_dev->data->port_id);
 823                 return bnxt_xmit_pkts_vec;
 824         }
 825         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 826                     eth_dev->data->port_id);
 827         PMD_DRV_LOG(INFO,
 828                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 829                     eth_dev->data->port_id,
 830                     eth_dev->data->scattered_rx,
 831                     eth_dev->data->dev_conf.txmode.offloads);
 832 #endif
 833 #endif
 834         return bnxt_xmit_pkts;
 835 }
 836
 837 static int bnxt_handle_if_change_status(struct bnxt *bp)
 838 {
 839         int rc;
 840
 841         /* Since fw has undergone a reset and lost all contexts,
 842          * set fatal flag to not issue hwrm during cleanup
 843          */
 844         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 845         bnxt_uninit_resources(bp, true);
 846
 847         /* clear fatal flag so that re-init happens */
 848         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 849         rc = bnxt_init_resources(bp, true);
 850
 851         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 852
 853         return rc;
 854 }
 855
 856 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 857 {
 858         struct bnxt *bp = eth_dev->data->dev_private;
 859         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 860         int vlan_mask = 0;
 861         int rc;
 862
 863         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
 864                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
 865                 return -EINVAL;
 866         }
 867
 868         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 869                 PMD_DRV_LOG(ERR,
 870                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 871                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 872         }
 873
 874         rc = bnxt_hwrm_if_change(bp, 1);
 875         if (!rc) {
 876                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 877                         rc = bnxt_handle_if_change_status(bp);
 878                         if (rc)
 879                                 return rc;
 880                 }
 881         }
 882         bnxt_enable_int(bp);
 883
 884         rc = bnxt_init_chip(bp);
 885         if (rc)
 886                 goto error;
 887
 888         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 889         eth_dev->data->dev_started = 1;
 890
 891         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
 892
 893         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 894                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 895         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 896                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 897         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 898         if (rc)
 899                 goto error;
 900
 901         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 902         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 903
 904         pthread_mutex_lock(&bp->def_cp_lock);
 905         bnxt_schedule_fw_health_check(bp);
 906         pthread_mutex_unlock(&bp->def_cp_lock);
 907
 908         if (bp->truflow)
 909                 bnxt_ulp_init(bp);
 910
 911         return 0;
 912
 913 error:
 914         bnxt_hwrm_if_change(bp, 0);
 915         bnxt_shutdown_nic(bp);
 916         bnxt_free_tx_mbufs(bp);
 917         bnxt_free_rx_mbufs(bp);
 918         eth_dev->data->dev_started = 0;
 919         return rc;
 920 }
 921
 922 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 923 {
 924         struct bnxt *bp = eth_dev->data->dev_private;
 925         int rc = 0;
 926
 927         if (!bp->link_info.link_up)
 928                 rc = bnxt_set_hwrm_link_config(bp, true);
 929         if (!rc)
 930                 eth_dev->data->dev_link.link_status = 1;
 931
 932         bnxt_print_link_info(eth_dev);
 933         return rc;
 934 }
 935
 936 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 937 {
 938         struct bnxt *bp = eth_dev->data->dev_private;
 939
 940         eth_dev->data->dev_link.link_status = 0;
 941         bnxt_set_hwrm_link_config(bp, false);
 942         bp->link_info.link_up = 0;
 943
 944         return 0;
 945 }
 946
 947 /* Unload the driver, release resources */
 948 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 949 {
 950         struct bnxt *bp = eth_dev->data->dev_private;
 951         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 952         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 953
 954         eth_dev->data->dev_started = 0;
 955         /* Prevent crashes when queues are still in use */
 956         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 957         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 958
 959         bnxt_disable_int(bp);
 960
 961         /* disable uio/vfio intr/eventfd mapping */
 962         rte_intr_disable(intr_handle);
 963
 964         bnxt_cancel_fw_health_check(bp);
 965
 966         bnxt_dev_set_link_down_op(eth_dev);
 967
 968         /* Wait for link to be reset and the async notification to process.
 969          * During reset recovery, there is no need to wait and
 970          * VF/NPAR functions do not have privilege to change PHY config.
 971          */
 972         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
 973                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
 974
 975         /* Clean queue intr-vector mapping */
 976         rte_intr_efd_disable(intr_handle);
 977         if (intr_handle->intr_vec != NULL) {
 978                 rte_free(intr_handle->intr_vec);
 979                 intr_handle->intr_vec = NULL;
 980         }
 981
 982         bnxt_hwrm_port_clr_stats(bp);
 983         bnxt_free_tx_mbufs(bp);
 984         bnxt_free_rx_mbufs(bp);
 985         /* Process any remaining notifications in default completion queue */
 986         bnxt_int_handler(eth_dev);
 987         bnxt_shutdown_nic(bp);
 988         bnxt_hwrm_if_change(bp, 0);
 989
 990         rte_free(bp->mark_table);
 991         bp->mark_table = NULL;
 992
 993         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
 994         bp->rx_cosq_cnt = 0;
 995 }
 996
 997 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 998 {
 999         struct bnxt *bp = eth_dev->data->dev_private;
1000
1001         /* cancel the recovery handler before remove dev */
1002         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1003         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1004
1005         if (eth_dev->data->dev_started)
1006                 bnxt_dev_stop_op(eth_dev);
1007
1008         bnxt_uninit_resources(bp, false);
1009
1010         eth_dev->dev_ops = NULL;
1011         eth_dev->rx_pkt_burst = NULL;
1012         eth_dev->tx_pkt_burst = NULL;
1013
1014         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1015         bp->tx_mem_zone = NULL;
1016         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1017         bp->rx_mem_zone = NULL;
1018
1019         rte_free(bp->pf.vf_info);
1020         bp->pf.vf_info = NULL;
1021
1022         rte_free(bp->grp_info);
1023         bp->grp_info = NULL;
1024 }
1025
1026 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1027                                     uint32_t index)
1028 {
1029         struct bnxt *bp = eth_dev->data->dev_private;
1030         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1031         struct bnxt_vnic_info *vnic;
1032         struct bnxt_filter_info *filter, *temp_filter;
1033         uint32_t i;
1034
1035         if (is_bnxt_in_error(bp))
1036                 return;
1037
1038         /*
1039          * Loop through all VNICs from the specified filter flow pools to
1040          * remove the corresponding MAC addr filter
1041          */
1042         for (i = 0; i < bp->nr_vnics; i++) {
1043                 if (!(pool_mask & (1ULL << i)))
1044                         continue;
1045
1046                 vnic = &bp->vnic_info[i];
1047                 filter = STAILQ_FIRST(&vnic->filter);
1048                 while (filter) {
1049                         temp_filter = STAILQ_NEXT(filter, next);
1050                         if (filter->mac_index == index) {
1051                                 STAILQ_REMOVE(&vnic->filter, filter,
1052                                                 bnxt_filter_info, next);
1053                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1054                                 bnxt_free_filter(bp, filter);
1055                         }
1056                         filter = temp_filter;
1057                 }
1058         }
1059 }
1060
1061 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1062                                struct rte_ether_addr *mac_addr, uint32_t index,
1063                                uint32_t pool)
1064 {
1065         struct bnxt_filter_info *filter;
1066         int rc = 0;
1067
1068         /* Attach requested MAC address to the new l2_filter */
1069         STAILQ_FOREACH(filter, &vnic->filter, next) {
1070                 if (filter->mac_index == index) {
1071                         PMD_DRV_LOG(DEBUG,
1072                                     "MAC addr already existed for pool %d\n",
1073                                     pool);
1074                         return 0;
1075                 }
1076         }
1077
1078         filter = bnxt_alloc_filter(bp);
1079         if (!filter) {
1080                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1081                 return -ENODEV;
1082         }
1083
1084         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1085          * if the MAC that's been programmed now is a different one, then,
1086          * copy that addr to filter->l2_addr
1087          */
1088         if (mac_addr)
1089                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1090         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1091
1092         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1093         if (!rc) {
1094                 filter->mac_index = index;
1095                 if (filter->mac_index == 0)
1096                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1097                 else
1098                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1099         } else {
1100                 bnxt_free_filter(bp, filter);
1101         }
1102
1103         return rc;
1104 }
1105
1106 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1107                                 struct rte_ether_addr *mac_addr,
1108                                 uint32_t index, uint32_t pool)
1109 {
1110         struct bnxt *bp = eth_dev->data->dev_private;
1111         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1112         int rc = 0;
1113
1114         rc = is_bnxt_in_error(bp);
1115         if (rc)
1116                 return rc;
1117
1118         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1119                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1120                 return -ENOTSUP;
1121         }
1122
1123         if (!vnic) {
1124                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1125                 return -EINVAL;
1126         }
1127
1128         /* Filter settings will get applied when port is started */
1129         if (!eth_dev->data->dev_started)
1130                 return 0;
1131
1132         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1133
1134         return rc;
1135 }
1136
1137 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1138                      bool exp_link_status)
1139 {
1140         int rc = 0;
1141         struct bnxt *bp = eth_dev->data->dev_private;
1142         struct rte_eth_link new;
1143         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1144                   BNXT_LINK_DOWN_WAIT_CNT;
1145
1146         rc = is_bnxt_in_error(bp);
1147         if (rc)
1148                 return rc;
1149
1150         memset(&new, 0, sizeof(new));
1151         do {
1152                 /* Retrieve link info from hardware */
1153                 rc = bnxt_get_hwrm_link_config(bp, &new);
1154                 if (rc) {
1155                         new.link_speed = ETH_LINK_SPEED_100M;
1156                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1157                         PMD_DRV_LOG(ERR,
1158                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1159                         goto out;
1160                 }
1161
1162                 if (!wait_to_complete || new.link_status == exp_link_status)
1163                         break;
1164
1165                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1166         } while (cnt--);
1167
1168 out:
1169         /* Timed out or success */
1170         if (new.link_status != eth_dev->data->dev_link.link_status ||
1171         new.link_speed != eth_dev->data->dev_link.link_speed) {
1172                 rte_eth_linkstatus_set(eth_dev, &new);
1173
1174                 _rte_eth_dev_callback_process(eth_dev,
1175                                               RTE_ETH_EVENT_INTR_LSC,
1176                                               NULL);
1177
1178                 bnxt_print_link_info(eth_dev);
1179         }
1180
1181         return rc;
1182 }
1183
1184 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1185                                int wait_to_complete)
1186 {
1187         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1188 }
1189
1190 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1191 {
1192         struct bnxt *bp = eth_dev->data->dev_private;
1193         struct bnxt_vnic_info *vnic;
1194         uint32_t old_flags;
1195         int rc;
1196
1197         rc = is_bnxt_in_error(bp);
1198         if (rc)
1199                 return rc;
1200
1201         /* Filter settings will get applied when port is started */
1202         if (!eth_dev->data->dev_started)
1203                 return 0;
1204
1205         if (bp->vnic_info == NULL)
1206                 return 0;
1207
1208         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1209
1210         old_flags = vnic->flags;
1211         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1212         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1213         if (rc != 0)
1214                 vnic->flags = old_flags;
1215
1216         return rc;
1217 }
1218
1219 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1220 {
1221         struct bnxt *bp = eth_dev->data->dev_private;
1222         struct bnxt_vnic_info *vnic;
1223         uint32_t old_flags;
1224         int rc;
1225
1226         rc = is_bnxt_in_error(bp);
1227         if (rc)
1228                 return rc;
1229
1230         /* Filter settings will get applied when port is started */
1231         if (!eth_dev->data->dev_started)
1232                 return 0;
1233
1234         if (bp->vnic_info == NULL)
1235                 return 0;
1236
1237         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1238
1239         old_flags = vnic->flags;
1240         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1241         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1242         if (rc != 0)
1243                 vnic->flags = old_flags;
1244
1245         return rc;
1246 }
1247
1248 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1249 {
1250         struct bnxt *bp = eth_dev->data->dev_private;
1251         struct bnxt_vnic_info *vnic;
1252         uint32_t old_flags;
1253         int rc;
1254
1255         rc = is_bnxt_in_error(bp);
1256         if (rc)
1257                 return rc;
1258
1259         /* Filter settings will get applied when port is started */
1260         if (!eth_dev->data->dev_started)
1261                 return 0;
1262
1263         if (bp->vnic_info == NULL)
1264                 return 0;
1265
1266         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1267
1268         old_flags = vnic->flags;
1269         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1270         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1271         if (rc != 0)
1272                 vnic->flags = old_flags;
1273
1274         return rc;
1275 }
1276
1277 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1278 {
1279         struct bnxt *bp = eth_dev->data->dev_private;
1280         struct bnxt_vnic_info *vnic;
1281         uint32_t old_flags;
1282         int rc;
1283
1284         rc = is_bnxt_in_error(bp);
1285         if (rc)
1286                 return rc;
1287
1288         /* Filter settings will get applied when port is started */
1289         if (!eth_dev->data->dev_started)
1290                 return 0;
1291
1292         if (bp->vnic_info == NULL)
1293                 return 0;
1294
1295         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1296
1297         old_flags = vnic->flags;
1298         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1299         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1300         if (rc != 0)
1301                 vnic->flags = old_flags;
1302
1303         return rc;
1304 }
1305
1306 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1307 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1308 {
1309         if (qid >= bp->rx_nr_rings)
1310                 return NULL;
1311
1312         return bp->eth_dev->data->rx_queues[qid];
1313 }
1314
1315 /* Return rxq corresponding to a given rss table ring/group ID. */
1316 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1317 {
1318         struct bnxt_rx_queue *rxq;
1319         unsigned int i;
1320
1321         if (!BNXT_HAS_RING_GRPS(bp)) {
1322                 for (i = 0; i < bp->rx_nr_rings; i++) {
1323                         rxq = bp->eth_dev->data->rx_queues[i];
1324                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1325                                 return rxq->index;
1326                 }
1327         } else {
1328                 for (i = 0; i < bp->rx_nr_rings; i++) {
1329                         if (bp->grp_info[i].fw_grp_id == fwr)
1330                                 return i;
1331                 }
1332         }
1333
1334         return INVALID_HW_RING_ID;
1335 }
1336
1337 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1338                             struct rte_eth_rss_reta_entry64 *reta_conf,
1339                             uint16_t reta_size)
1340 {
1341         struct bnxt *bp = eth_dev->data->dev_private;
1342         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1343         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1344         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1345         uint16_t idx, sft;
1346         int i, rc;
1347
1348         rc = is_bnxt_in_error(bp);
1349         if (rc)
1350                 return rc;
1351
1352         if (!vnic->rss_table)
1353                 return -EINVAL;
1354
1355         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1356                 return -EINVAL;
1357
1358         if (reta_size != tbl_size) {
1359                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1360                         "(%d) must equal the size supported by the hardware "
1361                         "(%d)\n", reta_size, tbl_size);
1362                 return -EINVAL;
1363         }
1364
1365         for (i = 0; i < reta_size; i++) {
1366                 struct bnxt_rx_queue *rxq;
1367
1368                 idx = i / RTE_RETA_GROUP_SIZE;
1369                 sft = i % RTE_RETA_GROUP_SIZE;
1370
1371                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1372                         continue;
1373
1374                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1375                 if (!rxq) {
1376                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1377                         return -EINVAL;
1378                 }
1379
1380                 if (BNXT_CHIP_THOR(bp)) {
1381                         vnic->rss_table[i * 2] =
1382                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1383                         vnic->rss_table[i * 2 + 1] =
1384                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1385                 } else {
1386                         vnic->rss_table[i] =
1387                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1388                 }
1389         }
1390
1391         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1392         return 0;
1393 }
1394
1395 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1396                               struct rte_eth_rss_reta_entry64 *reta_conf,
1397                               uint16_t reta_size)
1398 {
1399         struct bnxt *bp = eth_dev->data->dev_private;
1400         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1401         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1402         uint16_t idx, sft, i;
1403         int rc;
1404
1405         rc = is_bnxt_in_error(bp);
1406         if (rc)
1407                 return rc;
1408
1409         /* Retrieve from the default VNIC */
1410         if (!vnic)
1411                 return -EINVAL;
1412         if (!vnic->rss_table)
1413                 return -EINVAL;
1414
1415         if (reta_size != tbl_size) {
1416                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1417                         "(%d) must equal the size supported by the hardware "
1418                         "(%d)\n", reta_size, tbl_size);
1419                 return -EINVAL;
1420         }
1421
1422         for (idx = 0, i = 0; i < reta_size; i++) {
1423                 idx = i / RTE_RETA_GROUP_SIZE;
1424                 sft = i % RTE_RETA_GROUP_SIZE;
1425
1426                 if (reta_conf[idx].mask & (1ULL << sft)) {
1427                         uint16_t qid;
1428
1429                         if (BNXT_CHIP_THOR(bp))
1430                                 qid = bnxt_rss_to_qid(bp,
1431                                                       vnic->rss_table[i * 2]);
1432                         else
1433                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1434
1435                         if (qid == INVALID_HW_RING_ID) {
1436                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1437                                 return -EINVAL;
1438                         }
1439                         reta_conf[idx].reta[sft] = qid;
1440                 }
1441         }
1442
1443         return 0;
1444 }
1445
1446 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1447                                    struct rte_eth_rss_conf *rss_conf)
1448 {
1449         struct bnxt *bp = eth_dev->data->dev_private;
1450         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1451         struct bnxt_vnic_info *vnic;
1452         int rc;
1453
1454         rc = is_bnxt_in_error(bp);
1455         if (rc)
1456                 return rc;
1457
1458         /*
1459          * If RSS enablement were different than dev_configure,
1460          * then return -EINVAL
1461          */
1462         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1463                 if (!rss_conf->rss_hf)
1464                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1465         } else {
1466                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1467                         return -EINVAL;
1468         }
1469
1470         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1471         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1472
1473         /* Update the default RSS VNIC(s) */
1474         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1475         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1476
1477         /*
1478          * If hashkey is not specified, use the previously configured
1479          * hashkey
1480          */
1481         if (!rss_conf->rss_key)
1482                 goto rss_config;
1483
1484         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1485                 PMD_DRV_LOG(ERR,
1486                             "Invalid hashkey length, should be 16 bytes\n");
1487                 return -EINVAL;
1488         }
1489         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1490
1491 rss_config:
1492         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1493         return 0;
1494 }
1495
1496 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1497                                      struct rte_eth_rss_conf *rss_conf)
1498 {
1499         struct bnxt *bp = eth_dev->data->dev_private;
1500         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1501         int len, rc;
1502         uint32_t hash_types;
1503
1504         rc = is_bnxt_in_error(bp);
1505         if (rc)
1506                 return rc;
1507
1508         /* RSS configuration is the same for all VNICs */
1509         if (vnic && vnic->rss_hash_key) {
1510                 if (rss_conf->rss_key) {
1511                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1512                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1513                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1514                 }
1515
1516                 hash_types = vnic->hash_type;
1517                 rss_conf->rss_hf = 0;
1518                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1519                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1520                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1521                 }
1522                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1523                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1524                         hash_types &=
1525                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1526                 }
1527                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1528                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1529                         hash_types &=
1530                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1531                 }
1532                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1533                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1534                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1535                 }
1536                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1537                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1538                         hash_types &=
1539                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1540                 }
1541                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1542                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1543                         hash_types &=
1544                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1545                 }
1546                 if (hash_types) {
1547                         PMD_DRV_LOG(ERR,
1548                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1549                                 vnic->hash_type);
1550                         return -ENOTSUP;
1551                 }
1552         } else {
1553                 rss_conf->rss_hf = 0;
1554         }
1555         return 0;
1556 }
1557
1558 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1559                                struct rte_eth_fc_conf *fc_conf)
1560 {
1561         struct bnxt *bp = dev->data->dev_private;
1562         struct rte_eth_link link_info;
1563         int rc;
1564
1565         rc = is_bnxt_in_error(bp);
1566         if (rc)
1567                 return rc;
1568
1569         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1570         if (rc)
1571                 return rc;
1572
1573         memset(fc_conf, 0, sizeof(*fc_conf));
1574         if (bp->link_info.auto_pause)
1575                 fc_conf->autoneg = 1;
1576         switch (bp->link_info.pause) {
1577         case 0:
1578                 fc_conf->mode = RTE_FC_NONE;
1579                 break;
1580         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1581                 fc_conf->mode = RTE_FC_TX_PAUSE;
1582                 break;
1583         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1584                 fc_conf->mode = RTE_FC_RX_PAUSE;
1585                 break;
1586         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1587                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1588                 fc_conf->mode = RTE_FC_FULL;
1589                 break;
1590         }
1591         return 0;
1592 }
1593
1594 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1595                                struct rte_eth_fc_conf *fc_conf)
1596 {
1597         struct bnxt *bp = dev->data->dev_private;
1598         int rc;
1599
1600         rc = is_bnxt_in_error(bp);
1601         if (rc)
1602                 return rc;
1603
1604         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1605                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1606                 return -ENOTSUP;
1607         }
1608
1609         switch (fc_conf->mode) {
1610         case RTE_FC_NONE:
1611                 bp->link_info.auto_pause = 0;
1612                 bp->link_info.force_pause = 0;
1613                 break;
1614         case RTE_FC_RX_PAUSE:
1615                 if (fc_conf->autoneg) {
1616                         bp->link_info.auto_pause =
1617                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1618                         bp->link_info.force_pause = 0;
1619                 } else {
1620                         bp->link_info.auto_pause = 0;
1621                         bp->link_info.force_pause =
1622                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1623                 }
1624                 break;
1625         case RTE_FC_TX_PAUSE:
1626                 if (fc_conf->autoneg) {
1627                         bp->link_info.auto_pause =
1628                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1629                         bp->link_info.force_pause = 0;
1630                 } else {
1631                         bp->link_info.auto_pause = 0;
1632                         bp->link_info.force_pause =
1633                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1634                 }
1635                 break;
1636         case RTE_FC_FULL:
1637                 if (fc_conf->autoneg) {
1638                         bp->link_info.auto_pause =
1639                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1640                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1641                         bp->link_info.force_pause = 0;
1642                 } else {
1643                         bp->link_info.auto_pause = 0;
1644                         bp->link_info.force_pause =
1645                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1646                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1647                 }
1648                 break;
1649         }
1650         return bnxt_set_hwrm_link_config(bp, true);
1651 }
1652
1653 /* Add UDP tunneling port */
1654 static int
1655 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1656                          struct rte_eth_udp_tunnel *udp_tunnel)
1657 {
1658         struct bnxt *bp = eth_dev->data->dev_private;
1659         uint16_t tunnel_type = 0;
1660         int rc = 0;
1661
1662         rc = is_bnxt_in_error(bp);
1663         if (rc)
1664                 return rc;
1665
1666         switch (udp_tunnel->prot_type) {
1667         case RTE_TUNNEL_TYPE_VXLAN:
1668                 if (bp->vxlan_port_cnt) {
1669                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1670                                 udp_tunnel->udp_port);
1671                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1672                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1673                                 return -ENOSPC;
1674                         }
1675                         bp->vxlan_port_cnt++;
1676                         return 0;
1677                 }
1678                 tunnel_type =
1679                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1680                 bp->vxlan_port_cnt++;
1681                 break;
1682         case RTE_TUNNEL_TYPE_GENEVE:
1683                 if (bp->geneve_port_cnt) {
1684                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1685                                 udp_tunnel->udp_port);
1686                         if (bp->geneve_port != udp_tunnel->udp_port) {
1687                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1688                                 return -ENOSPC;
1689                         }
1690                         bp->geneve_port_cnt++;
1691                         return 0;
1692                 }
1693                 tunnel_type =
1694                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1695                 bp->geneve_port_cnt++;
1696                 break;
1697         default:
1698                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1699                 return -ENOTSUP;
1700         }
1701         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1702                                              tunnel_type);
1703         return rc;
1704 }
1705
1706 static int
1707 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1708                          struct rte_eth_udp_tunnel *udp_tunnel)
1709 {
1710         struct bnxt *bp = eth_dev->data->dev_private;
1711         uint16_t tunnel_type = 0;
1712         uint16_t port = 0;
1713         int rc = 0;
1714
1715         rc = is_bnxt_in_error(bp);
1716         if (rc)
1717                 return rc;
1718
1719         switch (udp_tunnel->prot_type) {
1720         case RTE_TUNNEL_TYPE_VXLAN:
1721                 if (!bp->vxlan_port_cnt) {
1722                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1723                         return -EINVAL;
1724                 }
1725                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1726                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1727                                 udp_tunnel->udp_port, bp->vxlan_port);
1728                         return -EINVAL;
1729                 }
1730                 if (--bp->vxlan_port_cnt)
1731                         return 0;
1732
1733                 tunnel_type =
1734                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1735                 port = bp->vxlan_fw_dst_port_id;
1736                 break;
1737         case RTE_TUNNEL_TYPE_GENEVE:
1738                 if (!bp->geneve_port_cnt) {
1739                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1740                         return -EINVAL;
1741                 }
1742                 if (bp->geneve_port != udp_tunnel->udp_port) {
1743                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1744                                 udp_tunnel->udp_port, bp->geneve_port);
1745                         return -EINVAL;
1746                 }
1747                 if (--bp->geneve_port_cnt)
1748                         return 0;
1749
1750                 tunnel_type =
1751                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1752                 port = bp->geneve_fw_dst_port_id;
1753                 break;
1754         default:
1755                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1756                 return -ENOTSUP;
1757         }
1758
1759         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1760         if (!rc) {
1761                 if (tunnel_type ==
1762                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1763                         bp->vxlan_port = 0;
1764                 if (tunnel_type ==
1765                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1766                         bp->geneve_port = 0;
1767         }
1768         return rc;
1769 }
1770
1771 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1772 {
1773         struct bnxt_filter_info *filter;
1774         struct bnxt_vnic_info *vnic;
1775         int rc = 0;
1776         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1777
1778         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1779         filter = STAILQ_FIRST(&vnic->filter);
1780         while (filter) {
1781                 /* Search for this matching MAC+VLAN filter */
1782                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1783                         /* Delete the filter */
1784                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1785                         if (rc)
1786                                 return rc;
1787                         STAILQ_REMOVE(&vnic->filter, filter,
1788                                       bnxt_filter_info, next);
1789                         bnxt_free_filter(bp, filter);
1790                         PMD_DRV_LOG(INFO,
1791                                     "Deleted vlan filter for %d\n",
1792                                     vlan_id);
1793                         return 0;
1794                 }
1795                 filter = STAILQ_NEXT(filter, next);
1796         }
1797         return -ENOENT;
1798 }
1799
1800 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1801 {
1802         struct bnxt_filter_info *filter;
1803         struct bnxt_vnic_info *vnic;
1804         int rc = 0;
1805         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1806                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1807         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1808
1809         /* Implementation notes on the use of VNIC in this command:
1810          *
1811          * By default, these filters belong to default vnic for the function.
1812          * Once these filters are set up, only destination VNIC can be modified.
1813          * If the destination VNIC is not specified in this command,
1814          * then the HWRM shall only create an l2 context id.
1815          */
1816
1817         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1818         filter = STAILQ_FIRST(&vnic->filter);
1819         /* Check if the VLAN has already been added */
1820         while (filter) {
1821                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1822                         return -EEXIST;
1823
1824                 filter = STAILQ_NEXT(filter, next);
1825         }
1826
1827         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1828          * command to create MAC+VLAN filter with the right flags, enables set.
1829          */
1830         filter = bnxt_alloc_filter(bp);
1831         if (!filter) {
1832                 PMD_DRV_LOG(ERR,
1833                             "MAC/VLAN filter alloc failed\n");
1834                 return -ENOMEM;
1835         }
1836         /* MAC + VLAN ID filter */
1837         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1838          * untagged packets are received
1839          *
1840          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1841          * packets and only the programmed vlan's packets are received
1842          */
1843         filter->l2_ivlan = vlan_id;
1844         filter->l2_ivlan_mask = 0x0FFF;
1845         filter->enables |= en;
1846         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1847
1848         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1849         if (rc) {
1850                 /* Free the newly allocated filter as we were
1851                  * not able to create the filter in hardware.
1852                  */
1853                 bnxt_free_filter(bp, filter);
1854                 return rc;
1855         }
1856
1857         filter->mac_index = 0;
1858         /* Add this new filter to the list */
1859         if (vlan_id == 0)
1860                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1861         else
1862                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1863
1864         PMD_DRV_LOG(INFO,
1865                     "Added Vlan filter for %d\n", vlan_id);
1866         return rc;
1867 }
1868
1869 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1870                 uint16_t vlan_id, int on)
1871 {
1872         struct bnxt *bp = eth_dev->data->dev_private;
1873         int rc;
1874
1875         rc = is_bnxt_in_error(bp);
1876         if (rc)
1877                 return rc;
1878
1879         /* These operations apply to ALL existing MAC/VLAN filters */
1880         if (on)
1881                 return bnxt_add_vlan_filter(bp, vlan_id);
1882         else
1883                 return bnxt_del_vlan_filter(bp, vlan_id);
1884 }
1885
1886 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1887                                     struct bnxt_vnic_info *vnic)
1888 {
1889         struct bnxt_filter_info *filter;
1890         int rc;
1891
1892         filter = STAILQ_FIRST(&vnic->filter);
1893         while (filter) {
1894                 if (filter->mac_index == 0 &&
1895                     !memcmp(filter->l2_addr, bp->mac_addr,
1896                             RTE_ETHER_ADDR_LEN)) {
1897                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1898                         if (!rc) {
1899                                 STAILQ_REMOVE(&vnic->filter, filter,
1900                                               bnxt_filter_info, next);
1901                                 bnxt_free_filter(bp, filter);
1902                         }
1903                         return rc;
1904                 }
1905                 filter = STAILQ_NEXT(filter, next);
1906         }
1907         return 0;
1908 }
1909
1910 static int
1911 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
1912 {
1913         struct bnxt_vnic_info *vnic;
1914         unsigned int i;
1915         int rc;
1916
1917         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1918         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1919                 /* Remove any VLAN filters programmed */
1920                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1921                         bnxt_del_vlan_filter(bp, i);
1922
1923                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1924                 if (rc)
1925                         return rc;
1926         } else {
1927                 /* Default filter will allow packets that match the
1928                  * dest mac. So, it has to be deleted, otherwise, we
1929                  * will endup receiving vlan packets for which the
1930                  * filter is not programmed, when hw-vlan-filter
1931                  * configuration is ON
1932                  */
1933                 bnxt_del_dflt_mac_filter(bp, vnic);
1934                 /* This filter will allow only untagged packets */
1935                 bnxt_add_vlan_filter(bp, 0);
1936         }
1937         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1938                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1939
1940         return 0;
1941 }
1942
1943 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
1944 {
1945         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
1946         unsigned int i;
1947         int rc;
1948
1949         /* Destroy vnic filters and vnic */
1950         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1951             DEV_RX_OFFLOAD_VLAN_FILTER) {
1952                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1953                         bnxt_del_vlan_filter(bp, i);
1954         }
1955         bnxt_del_dflt_mac_filter(bp, vnic);
1956
1957         rc = bnxt_hwrm_vnic_free(bp, vnic);
1958         if (rc)
1959                 return rc;
1960
1961         rte_free(vnic->fw_grp_ids);
1962         vnic->fw_grp_ids = NULL;
1963
1964         return 0;
1965 }
1966
1967 static int
1968 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
1969 {
1970         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1971         int rc;
1972
1973         /* Destroy, recreate and reconfigure the default vnic */
1974         rc = bnxt_free_one_vnic(bp, 0);
1975         if (rc)
1976                 return rc;
1977
1978         /* default vnic 0 */
1979         rc = bnxt_setup_one_vnic(bp, 0);
1980         if (rc)
1981                 return rc;
1982
1983         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1984             DEV_RX_OFFLOAD_VLAN_FILTER) {
1985                 rc = bnxt_add_vlan_filter(bp, 0);
1986                 if (rc)
1987                         return rc;
1988                 rc = bnxt_restore_vlan_filters(bp);
1989                 if (rc)
1990                         return rc;
1991         } else {
1992                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1993                 if (rc)
1994                         return rc;
1995         }
1996
1997         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1998         if (rc)
1999                 return rc;
2000
2001         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2002                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2003
2004         return rc;
2005 }
2006
2007 static int
2008 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2009 {
2010         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2011         struct bnxt *bp = dev->data->dev_private;
2012         int rc;
2013
2014         rc = is_bnxt_in_error(bp);
2015         if (rc)
2016                 return rc;
2017
2018         /* Filter settings will get applied when port is started */
2019         if (!dev->data->dev_started)
2020                 return 0;
2021
2022         if (mask & ETH_VLAN_FILTER_MASK) {
2023                 /* Enable or disable VLAN filtering */
2024                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2025                 if (rc)
2026                         return rc;
2027         }
2028
2029         if (mask & ETH_VLAN_STRIP_MASK) {
2030                 /* Enable or disable VLAN stripping */
2031                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2032                 if (rc)
2033                         return rc;
2034         }
2035
2036         if (mask & ETH_VLAN_EXTEND_MASK) {
2037                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2038                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2039                 else
2040                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2041         }
2042
2043         return 0;
2044 }
2045
2046 static int
2047 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2048                       uint16_t tpid)
2049 {
2050         struct bnxt *bp = dev->data->dev_private;
2051         int qinq = dev->data->dev_conf.rxmode.offloads &
2052                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2053
2054         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2055             vlan_type != ETH_VLAN_TYPE_OUTER) {
2056                 PMD_DRV_LOG(ERR,
2057                             "Unsupported vlan type.");
2058                 return -EINVAL;
2059         }
2060         if (!qinq) {
2061                 PMD_DRV_LOG(ERR,
2062                             "QinQ not enabled. Needs to be ON as we can "
2063                             "accelerate only outer vlan\n");
2064                 return -EINVAL;
2065         }
2066
2067         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2068                 switch (tpid) {
2069                 case RTE_ETHER_TYPE_QINQ:
2070                         bp->outer_tpid_bd =
2071                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2072                                 break;
2073                 case RTE_ETHER_TYPE_VLAN:
2074                         bp->outer_tpid_bd =
2075                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2076                                 break;
2077                 case 0x9100:
2078                         bp->outer_tpid_bd =
2079                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2080                                 break;
2081                 case 0x9200:
2082                         bp->outer_tpid_bd =
2083                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2084                                 break;
2085                 case 0x9300:
2086                         bp->outer_tpid_bd =
2087                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2088                                 break;
2089                 default:
2090                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2091                         return -EINVAL;
2092                 }
2093                 bp->outer_tpid_bd |= tpid;
2094                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2095         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2096                 PMD_DRV_LOG(ERR,
2097                             "Can accelerate only outer vlan in QinQ\n");
2098                 return -EINVAL;
2099         }
2100
2101         return 0;
2102 }
2103
2104 static int
2105 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2106                              struct rte_ether_addr *addr)
2107 {
2108         struct bnxt *bp = dev->data->dev_private;
2109         /* Default Filter is tied to VNIC 0 */
2110         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2111         int rc;
2112
2113         rc = is_bnxt_in_error(bp);
2114         if (rc)
2115                 return rc;
2116
2117         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2118                 return -EPERM;
2119
2120         if (rte_is_zero_ether_addr(addr))
2121                 return -EINVAL;
2122
2123         /* Filter settings will get applied when port is started */
2124         if (!dev->data->dev_started)
2125                 return 0;
2126
2127         /* Check if the requested MAC is already added */
2128         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2129                 return 0;
2130
2131         /* Destroy filter and re-create it */
2132         bnxt_del_dflt_mac_filter(bp, vnic);
2133
2134         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2135         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2136                 /* This filter will allow only untagged packets */
2137                 rc = bnxt_add_vlan_filter(bp, 0);
2138         } else {
2139                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2140         }
2141
2142         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2143         return rc;
2144 }
2145
2146 static int
2147 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2148                           struct rte_ether_addr *mc_addr_set,
2149                           uint32_t nb_mc_addr)
2150 {
2151         struct bnxt *bp = eth_dev->data->dev_private;
2152         char *mc_addr_list = (char *)mc_addr_set;
2153         struct bnxt_vnic_info *vnic;
2154         uint32_t off = 0, i = 0;
2155         int rc;
2156
2157         rc = is_bnxt_in_error(bp);
2158         if (rc)
2159                 return rc;
2160
2161         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2162
2163         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2164                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2165                 goto allmulti;
2166         }
2167
2168         /* TODO Check for Duplicate mcast addresses */
2169         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2170         for (i = 0; i < nb_mc_addr; i++) {
2171                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2172                         RTE_ETHER_ADDR_LEN);
2173                 off += RTE_ETHER_ADDR_LEN;
2174         }
2175
2176         vnic->mc_addr_cnt = i;
2177         if (vnic->mc_addr_cnt)
2178                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2179         else
2180                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2181
2182 allmulti:
2183         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2184 }
2185
2186 static int
2187 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2188 {
2189         struct bnxt *bp = dev->data->dev_private;
2190         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2191         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2192         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2193         int ret;
2194
2195         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2196                         fw_major, fw_minor, fw_updt);
2197
2198         ret += 1; /* add the size of '\0' */
2199         if (fw_size < (uint32_t)ret)
2200                 return ret;
2201         else
2202                 return 0;
2203 }
2204
2205 static void
2206 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2207         struct rte_eth_rxq_info *qinfo)
2208 {
2209         struct bnxt *bp = dev->data->dev_private;
2210         struct bnxt_rx_queue *rxq;
2211
2212         if (is_bnxt_in_error(bp))
2213                 return;
2214
2215         rxq = dev->data->rx_queues[queue_id];
2216
2217         qinfo->mp = rxq->mb_pool;
2218         qinfo->scattered_rx = dev->data->scattered_rx;
2219         qinfo->nb_desc = rxq->nb_rx_desc;
2220
2221         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2222         qinfo->conf.rx_drop_en = 0;
2223         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2224 }
2225
2226 static void
2227 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2228         struct rte_eth_txq_info *qinfo)
2229 {
2230         struct bnxt *bp = dev->data->dev_private;
2231         struct bnxt_tx_queue *txq;
2232
2233         if (is_bnxt_in_error(bp))
2234                 return;
2235
2236         txq = dev->data->tx_queues[queue_id];
2237
2238         qinfo->nb_desc = txq->nb_tx_desc;
2239
2240         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2241         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2242         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2243
2244         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2245         qinfo->conf.tx_rs_thresh = 0;
2246         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2247 }
2248
2249 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2250 {
2251         struct bnxt *bp = eth_dev->data->dev_private;
2252         uint32_t new_pkt_size;
2253         uint32_t rc = 0;
2254         uint32_t i;
2255
2256         rc = is_bnxt_in_error(bp);
2257         if (rc)
2258                 return rc;
2259
2260         /* Exit if receive queues are not configured yet */
2261         if (!eth_dev->data->nb_rx_queues)
2262                 return rc;
2263
2264         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2265                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2266
2267 #ifdef RTE_ARCH_X86
2268         /*
2269          * If vector-mode tx/rx is active, disallow any MTU change that would
2270          * require scattered receive support.
2271          */
2272         if (eth_dev->data->dev_started &&
2273             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2274              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2275             (new_pkt_size >
2276              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2277                 PMD_DRV_LOG(ERR,
2278                             "MTU change would require scattered rx support. ");
2279                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2280                 return -EINVAL;
2281         }
2282 #endif
2283
2284         if (new_mtu > RTE_ETHER_MTU) {
2285                 bp->flags |= BNXT_FLAG_JUMBO;
2286                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2287                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2288         } else {
2289                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2290                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2291                 bp->flags &= ~BNXT_FLAG_JUMBO;
2292         }
2293
2294         /* Is there a change in mtu setting? */
2295         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2296                 return rc;
2297
2298         for (i = 0; i < bp->nr_vnics; i++) {
2299                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2300                 uint16_t size = 0;
2301
2302                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2303                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2304                 if (rc)
2305                         break;
2306
2307                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2308                 size -= RTE_PKTMBUF_HEADROOM;
2309
2310                 if (size < new_mtu) {
2311                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2312                         if (rc)
2313                                 return rc;
2314                 }
2315         }
2316
2317         if (!rc)
2318                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2319
2320         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2321
2322         return rc;
2323 }
2324
2325 static int
2326 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2327 {
2328         struct bnxt *bp = dev->data->dev_private;
2329         uint16_t vlan = bp->vlan;
2330         int rc;
2331
2332         rc = is_bnxt_in_error(bp);
2333         if (rc)
2334                 return rc;
2335
2336         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2337                 PMD_DRV_LOG(ERR,
2338                         "PVID cannot be modified for this function\n");
2339                 return -ENOTSUP;
2340         }
2341         bp->vlan = on ? pvid : 0;
2342
2343         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2344         if (rc)
2345                 bp->vlan = vlan;
2346         return rc;
2347 }
2348
2349 static int
2350 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2351 {
2352         struct bnxt *bp = dev->data->dev_private;
2353         int rc;
2354
2355         rc = is_bnxt_in_error(bp);
2356         if (rc)
2357                 return rc;
2358
2359         return bnxt_hwrm_port_led_cfg(bp, true);
2360 }
2361
2362 static int
2363 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2364 {
2365         struct bnxt *bp = dev->data->dev_private;
2366         int rc;
2367
2368         rc = is_bnxt_in_error(bp);
2369         if (rc)
2370                 return rc;
2371
2372         return bnxt_hwrm_port_led_cfg(bp, false);
2373 }
2374
2375 static uint32_t
2376 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2377 {
2378         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2379         uint32_t desc = 0, raw_cons = 0, cons;
2380         struct bnxt_cp_ring_info *cpr;
2381         struct bnxt_rx_queue *rxq;
2382         struct rx_pkt_cmpl *rxcmp;
2383         int rc;
2384
2385         rc = is_bnxt_in_error(bp);
2386         if (rc)
2387                 return rc;
2388
2389         rxq = dev->data->rx_queues[rx_queue_id];
2390         cpr = rxq->cp_ring;
2391         raw_cons = cpr->cp_raw_cons;
2392
2393         while (1) {
2394                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2395                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2396                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2397
2398                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2399                         break;
2400                 } else {
2401                         raw_cons++;
2402                         desc++;
2403                 }
2404         }
2405
2406         return desc;
2407 }
2408
2409 static int
2410 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2411 {
2412         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2413         struct bnxt_rx_ring_info *rxr;
2414         struct bnxt_cp_ring_info *cpr;
2415         struct bnxt_sw_rx_bd *rx_buf;
2416         struct rx_pkt_cmpl *rxcmp;
2417         uint32_t cons, cp_cons;
2418         int rc;
2419
2420         if (!rxq)
2421                 return -EINVAL;
2422
2423         rc = is_bnxt_in_error(rxq->bp);
2424         if (rc)
2425                 return rc;
2426
2427         cpr = rxq->cp_ring;
2428         rxr = rxq->rx_ring;
2429
2430         if (offset >= rxq->nb_rx_desc)
2431                 return -EINVAL;
2432
2433         cons = RING_CMP(cpr->cp_ring_struct, offset);
2434         cp_cons = cpr->cp_raw_cons;
2435         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2436
2437         if (cons > cp_cons) {
2438                 if (CMPL_VALID(rxcmp, cpr->valid))
2439                         return RTE_ETH_RX_DESC_DONE;
2440         } else {
2441                 if (CMPL_VALID(rxcmp, !cpr->valid))
2442                         return RTE_ETH_RX_DESC_DONE;
2443         }
2444         rx_buf = &rxr->rx_buf_ring[cons];
2445         if (rx_buf->mbuf == NULL)
2446                 return RTE_ETH_RX_DESC_UNAVAIL;
2447
2448
2449         return RTE_ETH_RX_DESC_AVAIL;
2450 }
2451
2452 static int
2453 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2454 {
2455         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2456         struct bnxt_tx_ring_info *txr;
2457         struct bnxt_cp_ring_info *cpr;
2458         struct bnxt_sw_tx_bd *tx_buf;
2459         struct tx_pkt_cmpl *txcmp;
2460         uint32_t cons, cp_cons;
2461         int rc;
2462
2463         if (!txq)
2464                 return -EINVAL;
2465
2466         rc = is_bnxt_in_error(txq->bp);
2467         if (rc)
2468                 return rc;
2469
2470         cpr = txq->cp_ring;
2471         txr = txq->tx_ring;
2472
2473         if (offset >= txq->nb_tx_desc)
2474                 return -EINVAL;
2475
2476         cons = RING_CMP(cpr->cp_ring_struct, offset);
2477         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2478         cp_cons = cpr->cp_raw_cons;
2479
2480         if (cons > cp_cons) {
2481                 if (CMPL_VALID(txcmp, cpr->valid))
2482                         return RTE_ETH_TX_DESC_UNAVAIL;
2483         } else {
2484                 if (CMPL_VALID(txcmp, !cpr->valid))
2485                         return RTE_ETH_TX_DESC_UNAVAIL;
2486         }
2487         tx_buf = &txr->tx_buf_ring[cons];
2488         if (tx_buf->mbuf == NULL)
2489                 return RTE_ETH_TX_DESC_DONE;
2490
2491         return RTE_ETH_TX_DESC_FULL;
2492 }
2493
2494 static struct bnxt_filter_info *
2495 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2496                                 struct rte_eth_ethertype_filter *efilter,
2497                                 struct bnxt_vnic_info *vnic0,
2498                                 struct bnxt_vnic_info *vnic,
2499                                 int *ret)
2500 {
2501         struct bnxt_filter_info *mfilter = NULL;
2502         int match = 0;
2503         *ret = 0;
2504
2505         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2506                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2507                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2508                         " ethertype filter.", efilter->ether_type);
2509                 *ret = -EINVAL;
2510                 goto exit;
2511         }
2512         if (efilter->queue >= bp->rx_nr_rings) {
2513                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2514                 *ret = -EINVAL;
2515                 goto exit;
2516         }
2517
2518         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2519         vnic = &bp->vnic_info[efilter->queue];
2520         if (vnic == NULL) {
2521                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2522                 *ret = -EINVAL;
2523                 goto exit;
2524         }
2525
2526         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2527                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2528                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2529                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2530                              mfilter->flags ==
2531                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2532                              mfilter->ethertype == efilter->ether_type)) {
2533                                 match = 1;
2534                                 break;
2535                         }
2536                 }
2537         } else {
2538                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2539                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2540                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2541                              mfilter->ethertype == efilter->ether_type &&
2542                              mfilter->flags ==
2543                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2544                                 match = 1;
2545                                 break;
2546                         }
2547         }
2548
2549         if (match)
2550                 *ret = -EEXIST;
2551
2552 exit:
2553         return mfilter;
2554 }
2555
2556 static int
2557 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2558                         enum rte_filter_op filter_op,
2559                         void *arg)
2560 {
2561         struct bnxt *bp = dev->data->dev_private;
2562         struct rte_eth_ethertype_filter *efilter =
2563                         (struct rte_eth_ethertype_filter *)arg;
2564         struct bnxt_filter_info *bfilter, *filter1;
2565         struct bnxt_vnic_info *vnic, *vnic0;
2566         int ret;
2567
2568         if (filter_op == RTE_ETH_FILTER_NOP)
2569                 return 0;
2570
2571         if (arg == NULL) {
2572                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2573                             filter_op);
2574                 return -EINVAL;
2575         }
2576
2577         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2578         vnic = &bp->vnic_info[efilter->queue];
2579
2580         switch (filter_op) {
2581         case RTE_ETH_FILTER_ADD:
2582                 bnxt_match_and_validate_ether_filter(bp, efilter,
2583                                                         vnic0, vnic, &ret);
2584                 if (ret < 0)
2585                         return ret;
2586
2587                 bfilter = bnxt_get_unused_filter(bp);
2588                 if (bfilter == NULL) {
2589                         PMD_DRV_LOG(ERR,
2590                                 "Not enough resources for a new filter.\n");
2591                         return -ENOMEM;
2592                 }
2593                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2594                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2595                        RTE_ETHER_ADDR_LEN);
2596                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2597                        RTE_ETHER_ADDR_LEN);
2598                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2599                 bfilter->ethertype = efilter->ether_type;
2600                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2601
2602                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2603                 if (filter1 == NULL) {
2604                         ret = -EINVAL;
2605                         goto cleanup;
2606                 }
2607                 bfilter->enables |=
2608                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2609                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2610
2611                 bfilter->dst_id = vnic->fw_vnic_id;
2612
2613                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2614                         bfilter->flags =
2615                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2616                 }
2617
2618                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2619                 if (ret)
2620                         goto cleanup;
2621                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2622                 break;
2623         case RTE_ETH_FILTER_DELETE:
2624                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2625                                                         vnic0, vnic, &ret);
2626                 if (ret == -EEXIST) {
2627                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2628
2629                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2630                                       next);
2631                         bnxt_free_filter(bp, filter1);
2632                 } else if (ret == 0) {
2633                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2634                 }
2635                 break;
2636         default:
2637                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2638                 ret = -EINVAL;
2639                 goto error;
2640         }
2641         return ret;
2642 cleanup:
2643         bnxt_free_filter(bp, bfilter);
2644 error:
2645         return ret;
2646 }
2647
2648 static inline int
2649 parse_ntuple_filter(struct bnxt *bp,
2650                     struct rte_eth_ntuple_filter *nfilter,
2651                     struct bnxt_filter_info *bfilter)
2652 {
2653         uint32_t en = 0;
2654
2655         if (nfilter->queue >= bp->rx_nr_rings) {
2656                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2657                 return -EINVAL;
2658         }
2659
2660         switch (nfilter->dst_port_mask) {
2661         case UINT16_MAX:
2662                 bfilter->dst_port_mask = -1;
2663                 bfilter->dst_port = nfilter->dst_port;
2664                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2665                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2666                 break;
2667         default:
2668                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2669                 return -EINVAL;
2670         }
2671
2672         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2673         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2674
2675         switch (nfilter->proto_mask) {
2676         case UINT8_MAX:
2677                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2678                         bfilter->ip_protocol = 17;
2679                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2680                         bfilter->ip_protocol = 6;
2681                 else
2682                         return -EINVAL;
2683                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2684                 break;
2685         default:
2686                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2687                 return -EINVAL;
2688         }
2689
2690         switch (nfilter->dst_ip_mask) {
2691         case UINT32_MAX:
2692                 bfilter->dst_ipaddr_mask[0] = -1;
2693                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2694                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2695                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2696                 break;
2697         default:
2698                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2699                 return -EINVAL;
2700         }
2701
2702         switch (nfilter->src_ip_mask) {
2703         case UINT32_MAX:
2704                 bfilter->src_ipaddr_mask[0] = -1;
2705                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2706                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2707                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2708                 break;
2709         default:
2710                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2711                 return -EINVAL;
2712         }
2713
2714         switch (nfilter->src_port_mask) {
2715         case UINT16_MAX:
2716                 bfilter->src_port_mask = -1;
2717                 bfilter->src_port = nfilter->src_port;
2718                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2719                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2720                 break;
2721         default:
2722                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2723                 return -EINVAL;
2724         }
2725
2726         bfilter->enables = en;
2727         return 0;
2728 }
2729
2730 static struct bnxt_filter_info*
2731 bnxt_match_ntuple_filter(struct bnxt *bp,
2732                          struct bnxt_filter_info *bfilter,
2733                          struct bnxt_vnic_info **mvnic)
2734 {
2735         struct bnxt_filter_info *mfilter = NULL;
2736         int i;
2737
2738         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2739                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2740                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2741                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2742                             bfilter->src_ipaddr_mask[0] ==
2743                             mfilter->src_ipaddr_mask[0] &&
2744                             bfilter->src_port == mfilter->src_port &&
2745                             bfilter->src_port_mask == mfilter->src_port_mask &&
2746                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2747                             bfilter->dst_ipaddr_mask[0] ==
2748                             mfilter->dst_ipaddr_mask[0] &&
2749                             bfilter->dst_port == mfilter->dst_port &&
2750                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2751                             bfilter->flags == mfilter->flags &&
2752                             bfilter->enables == mfilter->enables) {
2753                                 if (mvnic)
2754                                         *mvnic = vnic;
2755                                 return mfilter;
2756                         }
2757                 }
2758         }
2759         return NULL;
2760 }
2761
2762 static int
2763 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2764                        struct rte_eth_ntuple_filter *nfilter,
2765                        enum rte_filter_op filter_op)
2766 {
2767         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2768         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2769         int ret;
2770
2771         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2772                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2773                 return -EINVAL;
2774         }
2775
2776         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2777                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2778                 return -EINVAL;
2779         }
2780
2781         bfilter = bnxt_get_unused_filter(bp);
2782         if (bfilter == NULL) {
2783                 PMD_DRV_LOG(ERR,
2784                         "Not enough resources for a new filter.\n");
2785                 return -ENOMEM;
2786         }
2787         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2788         if (ret < 0)
2789                 goto free_filter;
2790
2791         vnic = &bp->vnic_info[nfilter->queue];
2792         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2793         filter1 = STAILQ_FIRST(&vnic0->filter);
2794         if (filter1 == NULL) {
2795                 ret = -EINVAL;
2796                 goto free_filter;
2797         }
2798
2799         bfilter->dst_id = vnic->fw_vnic_id;
2800         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2801         bfilter->enables |=
2802                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2803         bfilter->ethertype = 0x800;
2804         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2805
2806         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2807
2808         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2809             bfilter->dst_id == mfilter->dst_id) {
2810                 PMD_DRV_LOG(ERR, "filter exists.\n");
2811                 ret = -EEXIST;
2812                 goto free_filter;
2813         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2814                    bfilter->dst_id != mfilter->dst_id) {
2815                 mfilter->dst_id = vnic->fw_vnic_id;
2816                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2817                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2818                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2819                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2820                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2821                 goto free_filter;
2822         }
2823         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2824                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2825                 ret = -ENOENT;
2826                 goto free_filter;
2827         }
2828
2829         if (filter_op == RTE_ETH_FILTER_ADD) {
2830                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2831                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2832                 if (ret)
2833                         goto free_filter;
2834                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2835         } else {
2836                 if (mfilter == NULL) {
2837                         /* This should not happen. But for Coverity! */
2838                         ret = -ENOENT;
2839                         goto free_filter;
2840                 }
2841                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2842
2843                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2844                 bnxt_free_filter(bp, mfilter);
2845                 bnxt_free_filter(bp, bfilter);
2846         }
2847
2848         return 0;
2849 free_filter:
2850         bnxt_free_filter(bp, bfilter);
2851         return ret;
2852 }
2853
2854 static int
2855 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2856                         enum rte_filter_op filter_op,
2857                         void *arg)
2858 {
2859         struct bnxt *bp = dev->data->dev_private;
2860         int ret;
2861
2862         if (filter_op == RTE_ETH_FILTER_NOP)
2863                 return 0;
2864
2865         if (arg == NULL) {
2866                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2867                             filter_op);
2868                 return -EINVAL;
2869         }
2870
2871         switch (filter_op) {
2872         case RTE_ETH_FILTER_ADD:
2873                 ret = bnxt_cfg_ntuple_filter(bp,
2874                         (struct rte_eth_ntuple_filter *)arg,
2875                         filter_op);
2876                 break;
2877         case RTE_ETH_FILTER_DELETE:
2878                 ret = bnxt_cfg_ntuple_filter(bp,
2879                         (struct rte_eth_ntuple_filter *)arg,
2880                         filter_op);
2881                 break;
2882         default:
2883                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2884                 ret = -EINVAL;
2885                 break;
2886         }
2887         return ret;
2888 }
2889
2890 static int
2891 bnxt_parse_fdir_filter(struct bnxt *bp,
2892                        struct rte_eth_fdir_filter *fdir,
2893                        struct bnxt_filter_info *filter)
2894 {
2895         enum rte_fdir_mode fdir_mode =
2896                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2897         struct bnxt_vnic_info *vnic0, *vnic;
2898         struct bnxt_filter_info *filter1;
2899         uint32_t en = 0;
2900         int i;
2901
2902         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2903                 return -EINVAL;
2904
2905         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2906         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2907
2908         switch (fdir->input.flow_type) {
2909         case RTE_ETH_FLOW_IPV4:
2910         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2911                 /* FALLTHROUGH */
2912                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2913                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2914                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2915                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2916                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2917                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2918                 filter->ip_addr_type =
2919                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2920                 filter->src_ipaddr_mask[0] = 0xffffffff;
2921                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2922                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2923                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2924                 filter->ethertype = 0x800;
2925                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2926                 break;
2927         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2928                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2929                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2930                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2931                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2932                 filter->dst_port_mask = 0xffff;
2933                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2934                 filter->src_port_mask = 0xffff;
2935                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2936                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2937                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2938                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2939                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2940                 filter->ip_protocol = 6;
2941                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2942                 filter->ip_addr_type =
2943                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2944                 filter->src_ipaddr_mask[0] = 0xffffffff;
2945                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2946                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2947                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2948                 filter->ethertype = 0x800;
2949                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2950                 break;
2951         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2952                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2953                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2954                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2955                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2956                 filter->dst_port_mask = 0xffff;
2957                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2958                 filter->src_port_mask = 0xffff;
2959                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2960                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2961                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2962                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2963                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2964                 filter->ip_protocol = 17;
2965                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2966                 filter->ip_addr_type =
2967                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2968                 filter->src_ipaddr_mask[0] = 0xffffffff;
2969                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2970                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2971                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2972                 filter->ethertype = 0x800;
2973                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2974                 break;
2975         case RTE_ETH_FLOW_IPV6:
2976         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2977                 /* FALLTHROUGH */
2978                 filter->ip_addr_type =
2979                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2980                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2981                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2982                 rte_memcpy(filter->src_ipaddr,
2983                            fdir->input.flow.ipv6_flow.src_ip, 16);
2984                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2985                 rte_memcpy(filter->dst_ipaddr,
2986                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2987                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2988                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2989                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2990                 memset(filter->src_ipaddr_mask, 0xff, 16);
2991                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2992                 filter->ethertype = 0x86dd;
2993                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2994                 break;
2995         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2996                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2997                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2998                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2999                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3000                 filter->dst_port_mask = 0xffff;
3001                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3002                 filter->src_port_mask = 0xffff;
3003                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3004                 filter->ip_addr_type =
3005                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3006                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3007                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3008                 rte_memcpy(filter->src_ipaddr,
3009                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3010                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3011                 rte_memcpy(filter->dst_ipaddr,
3012                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3013                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3014                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3015                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3016                 memset(filter->src_ipaddr_mask, 0xff, 16);
3017                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3018                 filter->ethertype = 0x86dd;
3019                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3020                 break;
3021         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3022                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3023                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3024                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3025                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3026                 filter->dst_port_mask = 0xffff;
3027                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3028                 filter->src_port_mask = 0xffff;
3029                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3030                 filter->ip_addr_type =
3031                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3032                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3033                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3034                 rte_memcpy(filter->src_ipaddr,
3035                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3036                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3037                 rte_memcpy(filter->dst_ipaddr,
3038                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3039                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3040                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3041                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3042                 memset(filter->src_ipaddr_mask, 0xff, 16);
3043                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3044                 filter->ethertype = 0x86dd;
3045                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3046                 break;
3047         case RTE_ETH_FLOW_L2_PAYLOAD:
3048                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3049                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3050                 break;
3051         case RTE_ETH_FLOW_VXLAN:
3052                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3053                         return -EINVAL;
3054                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3055                 filter->tunnel_type =
3056                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3057                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3058                 break;
3059         case RTE_ETH_FLOW_NVGRE:
3060                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3061                         return -EINVAL;
3062                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3063                 filter->tunnel_type =
3064                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3065                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3066                 break;
3067         case RTE_ETH_FLOW_UNKNOWN:
3068         case RTE_ETH_FLOW_RAW:
3069         case RTE_ETH_FLOW_FRAG_IPV4:
3070         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3071         case RTE_ETH_FLOW_FRAG_IPV6:
3072         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3073         case RTE_ETH_FLOW_IPV6_EX:
3074         case RTE_ETH_FLOW_IPV6_TCP_EX:
3075         case RTE_ETH_FLOW_IPV6_UDP_EX:
3076         case RTE_ETH_FLOW_GENEVE:
3077                 /* FALLTHROUGH */
3078         default:
3079                 return -EINVAL;
3080         }
3081
3082         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3083         vnic = &bp->vnic_info[fdir->action.rx_queue];
3084         if (vnic == NULL) {
3085                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3086                 return -EINVAL;
3087         }
3088
3089         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3090                 rte_memcpy(filter->dst_macaddr,
3091                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3092                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3093         }
3094
3095         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3096                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3097                 filter1 = STAILQ_FIRST(&vnic0->filter);
3098                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3099         } else {
3100                 filter->dst_id = vnic->fw_vnic_id;
3101                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3102                         if (filter->dst_macaddr[i] == 0x00)
3103                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3104                         else
3105                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3106         }
3107
3108         if (filter1 == NULL)
3109                 return -EINVAL;
3110
3111         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3112         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3113
3114         filter->enables = en;
3115
3116         return 0;
3117 }
3118
3119 static struct bnxt_filter_info *
3120 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3121                 struct bnxt_vnic_info **mvnic)
3122 {
3123         struct bnxt_filter_info *mf = NULL;
3124         int i;
3125
3126         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3127                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3128
3129                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3130                         if (mf->filter_type == nf->filter_type &&
3131                             mf->flags == nf->flags &&
3132                             mf->src_port == nf->src_port &&
3133                             mf->src_port_mask == nf->src_port_mask &&
3134                             mf->dst_port == nf->dst_port &&
3135                             mf->dst_port_mask == nf->dst_port_mask &&
3136                             mf->ip_protocol == nf->ip_protocol &&
3137                             mf->ip_addr_type == nf->ip_addr_type &&
3138                             mf->ethertype == nf->ethertype &&
3139                             mf->vni == nf->vni &&
3140                             mf->tunnel_type == nf->tunnel_type &&
3141                             mf->l2_ovlan == nf->l2_ovlan &&
3142                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3143                             mf->l2_ivlan == nf->l2_ivlan &&
3144                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3145                             !memcmp(mf->l2_addr, nf->l2_addr,
3146                                     RTE_ETHER_ADDR_LEN) &&
3147                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3148                                     RTE_ETHER_ADDR_LEN) &&
3149                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3150                                     RTE_ETHER_ADDR_LEN) &&
3151                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3152                                     RTE_ETHER_ADDR_LEN) &&
3153                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3154                                     sizeof(nf->src_ipaddr)) &&
3155                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3156                                     sizeof(nf->src_ipaddr_mask)) &&
3157                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3158                                     sizeof(nf->dst_ipaddr)) &&
3159                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3160                                     sizeof(nf->dst_ipaddr_mask))) {
3161                                 if (mvnic)
3162                                         *mvnic = vnic;
3163                                 return mf;
3164                         }
3165                 }
3166         }
3167         return NULL;
3168 }
3169
3170 static int
3171 bnxt_fdir_filter(struct rte_eth_dev *dev,
3172                  enum rte_filter_op filter_op,
3173                  void *arg)
3174 {
3175         struct bnxt *bp = dev->data->dev_private;
3176         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3177         struct bnxt_filter_info *filter, *match;
3178         struct bnxt_vnic_info *vnic, *mvnic;
3179         int ret = 0, i;
3180
3181         if (filter_op == RTE_ETH_FILTER_NOP)
3182                 return 0;
3183
3184         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3185                 return -EINVAL;
3186
3187         switch (filter_op) {
3188         case RTE_ETH_FILTER_ADD:
3189         case RTE_ETH_FILTER_DELETE:
3190                 /* FALLTHROUGH */
3191                 filter = bnxt_get_unused_filter(bp);
3192                 if (filter == NULL) {
3193                         PMD_DRV_LOG(ERR,
3194                                 "Not enough resources for a new flow.\n");
3195                         return -ENOMEM;
3196                 }
3197
3198                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3199                 if (ret != 0)
3200                         goto free_filter;
3201                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3202
3203                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3204                         vnic = &bp->vnic_info[0];
3205                 else
3206                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3207
3208                 match = bnxt_match_fdir(bp, filter, &mvnic);
3209                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3210                         if (match->dst_id == vnic->fw_vnic_id) {
3211                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3212                                 ret = -EEXIST;
3213                                 goto free_filter;
3214                         } else {
3215                                 match->dst_id = vnic->fw_vnic_id;
3216                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3217                                                                   match->dst_id,
3218                                                                   match);
3219                                 STAILQ_REMOVE(&mvnic->filter, match,
3220                                               bnxt_filter_info, next);
3221                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3222                                 PMD_DRV_LOG(ERR,
3223                                         "Filter with matching pattern exist\n");
3224                                 PMD_DRV_LOG(ERR,
3225                                         "Updated it to new destination q\n");
3226                                 goto free_filter;
3227                         }
3228                 }
3229                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3230                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3231                         ret = -ENOENT;
3232                         goto free_filter;
3233                 }
3234
3235                 if (filter_op == RTE_ETH_FILTER_ADD) {
3236                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3237                                                           filter->dst_id,
3238                                                           filter);
3239                         if (ret)
3240                                 goto free_filter;
3241                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3242                 } else {
3243                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3244                         STAILQ_REMOVE(&vnic->filter, match,
3245                                       bnxt_filter_info, next);
3246                         bnxt_free_filter(bp, match);
3247                         bnxt_free_filter(bp, filter);
3248                 }
3249                 break;
3250         case RTE_ETH_FILTER_FLUSH:
3251                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3252                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3253
3254                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3255                                 if (filter->filter_type ==
3256                                     HWRM_CFA_NTUPLE_FILTER) {
3257                                         ret =
3258                                         bnxt_hwrm_clear_ntuple_filter(bp,
3259                                                                       filter);
3260                                         STAILQ_REMOVE(&vnic->filter, filter,
3261                                                       bnxt_filter_info, next);
3262                                 }
3263                         }
3264                 }
3265                 return ret;
3266         case RTE_ETH_FILTER_UPDATE:
3267         case RTE_ETH_FILTER_STATS:
3268         case RTE_ETH_FILTER_INFO:
3269                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3270                 break;
3271         default:
3272                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3273                 ret = -EINVAL;
3274                 break;
3275         }
3276         return ret;
3277
3278 free_filter:
3279         bnxt_free_filter(bp, filter);
3280         return ret;
3281 }
3282
3283 static int
3284 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3285                     enum rte_filter_type filter_type,
3286                     enum rte_filter_op filter_op, void *arg)
3287 {
3288         int ret = 0;
3289
3290         ret = is_bnxt_in_error(dev->data->dev_private);
3291         if (ret)
3292                 return ret;
3293
3294         switch (filter_type) {
3295         case RTE_ETH_FILTER_TUNNEL:
3296                 PMD_DRV_LOG(ERR,
3297                         "filter type: %d: To be implemented\n", filter_type);
3298                 break;
3299         case RTE_ETH_FILTER_FDIR:
3300                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3301                 break;
3302         case RTE_ETH_FILTER_NTUPLE:
3303                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3304                 break;
3305         case RTE_ETH_FILTER_ETHERTYPE:
3306                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3307                 break;
3308         case RTE_ETH_FILTER_GENERIC:
3309                 if (filter_op != RTE_ETH_FILTER_GET)
3310                         return -EINVAL;
3311                 *(const void **)arg = &bnxt_flow_ops;
3312                 break;
3313         default:
3314                 PMD_DRV_LOG(ERR,
3315                         "Filter type (%d) not supported", filter_type);
3316                 ret = -EINVAL;
3317                 break;
3318         }
3319         return ret;
3320 }
3321
3322 static const uint32_t *
3323 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3324 {
3325         static const uint32_t ptypes[] = {
3326                 RTE_PTYPE_L2_ETHER_VLAN,
3327                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3328                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3329                 RTE_PTYPE_L4_ICMP,
3330                 RTE_PTYPE_L4_TCP,
3331                 RTE_PTYPE_L4_UDP,
3332                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3333                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3334                 RTE_PTYPE_INNER_L4_ICMP,
3335                 RTE_PTYPE_INNER_L4_TCP,
3336                 RTE_PTYPE_INNER_L4_UDP,
3337                 RTE_PTYPE_UNKNOWN
3338         };
3339
3340         if (!dev->rx_pkt_burst)
3341                 return NULL;
3342
3343         return ptypes;
3344 }
3345
3346 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3347                          int reg_win)
3348 {
3349         uint32_t reg_base = *reg_arr & 0xfffff000;
3350         uint32_t win_off;
3351         int i;
3352
3353         for (i = 0; i < count; i++) {
3354                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3355                         return -ERANGE;
3356         }
3357         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3358         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3359         return 0;
3360 }
3361
3362 static int bnxt_map_ptp_regs(struct bnxt *bp)
3363 {
3364         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3365         uint32_t *reg_arr;
3366         int rc, i;
3367
3368         reg_arr = ptp->rx_regs;
3369         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3370         if (rc)
3371                 return rc;
3372
3373         reg_arr = ptp->tx_regs;
3374         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3375         if (rc)
3376                 return rc;
3377
3378         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3379                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3380
3381         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3382                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3383
3384         return 0;
3385 }
3386
3387 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3388 {
3389         rte_write32(0, (uint8_t *)bp->bar0 +
3390                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3391         rte_write32(0, (uint8_t *)bp->bar0 +
3392                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3393 }
3394
3395 static uint64_t bnxt_cc_read(struct bnxt *bp)
3396 {
3397         uint64_t ns;
3398
3399         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3400                               BNXT_GRCPF_REG_SYNC_TIME));
3401         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3402                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3403         return ns;
3404 }
3405
3406 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3407 {
3408         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3409         uint32_t fifo;
3410
3411         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3412                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3413         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3414                 return -EAGAIN;
3415
3416         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3417                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3418         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3419                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3420         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3421                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3422
3423         return 0;
3424 }
3425
3426 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3427 {
3428         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3429         struct bnxt_pf_info *pf = &bp->pf;
3430         uint16_t port_id;
3431         uint32_t fifo;
3432
3433         if (!ptp)
3434                 return -ENODEV;
3435
3436         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3437                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3438         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3439                 return -EAGAIN;
3440
3441         port_id = pf->port_id;
3442         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3443                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3444
3445         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3446                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3447         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3448 /*              bnxt_clr_rx_ts(bp);       TBD  */
3449                 return -EBUSY;
3450         }
3451
3452         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3453                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3454         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3455                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3456
3457         return 0;
3458 }
3459
3460 static int
3461 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3462 {
3463         uint64_t ns;
3464         struct bnxt *bp = dev->data->dev_private;
3465         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3466
3467         if (!ptp)
3468                 return 0;
3469
3470         ns = rte_timespec_to_ns(ts);
3471         /* Set the timecounters to a new value. */
3472         ptp->tc.nsec = ns;
3473
3474         return 0;
3475 }
3476
3477 static int
3478 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3479 {
3480         struct bnxt *bp = dev->data->dev_private;
3481         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3482         uint64_t ns, systime_cycles = 0;
3483         int rc = 0;
3484
3485         if (!ptp)
3486                 return 0;
3487
3488         if (BNXT_CHIP_THOR(bp))
3489                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3490                                              &systime_cycles);
3491         else
3492                 systime_cycles = bnxt_cc_read(bp);
3493
3494         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3495         *ts = rte_ns_to_timespec(ns);
3496
3497         return rc;
3498 }
3499 static int
3500 bnxt_timesync_enable(struct rte_eth_dev *dev)
3501 {
3502         struct bnxt *bp = dev->data->dev_private;
3503         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3504         uint32_t shift = 0;
3505         int rc;
3506
3507         if (!ptp)
3508                 return 0;
3509
3510         ptp->rx_filter = 1;
3511         ptp->tx_tstamp_en = 1;
3512         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3513
3514         rc = bnxt_hwrm_ptp_cfg(bp);
3515         if (rc)
3516                 return rc;
3517
3518         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3519         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3520         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3521
3522         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3523         ptp->tc.cc_shift = shift;
3524         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3525
3526         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3527         ptp->rx_tstamp_tc.cc_shift = shift;
3528         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3529
3530         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3531         ptp->tx_tstamp_tc.cc_shift = shift;
3532         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3533
3534         if (!BNXT_CHIP_THOR(bp))
3535                 bnxt_map_ptp_regs(bp);
3536
3537         return 0;
3538 }
3539
3540 static int
3541 bnxt_timesync_disable(struct rte_eth_dev *dev)
3542 {
3543         struct bnxt *bp = dev->data->dev_private;
3544         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3545
3546         if (!ptp)
3547                 return 0;
3548
3549         ptp->rx_filter = 0;
3550         ptp->tx_tstamp_en = 0;
3551         ptp->rxctl = 0;
3552
3553         bnxt_hwrm_ptp_cfg(bp);
3554
3555         if (!BNXT_CHIP_THOR(bp))
3556                 bnxt_unmap_ptp_regs(bp);
3557
3558         return 0;
3559 }
3560
3561 static int
3562 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3563                                  struct timespec *timestamp,
3564                                  uint32_t flags __rte_unused)
3565 {
3566         struct bnxt *bp = dev->data->dev_private;
3567         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3568         uint64_t rx_tstamp_cycles = 0;
3569         uint64_t ns;
3570
3571         if (!ptp)
3572                 return 0;
3573
3574         if (BNXT_CHIP_THOR(bp))
3575                 rx_tstamp_cycles = ptp->rx_timestamp;
3576         else
3577                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3578
3579         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3580         *timestamp = rte_ns_to_timespec(ns);
3581         return  0;
3582 }
3583
3584 static int
3585 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3586                                  struct timespec *timestamp)
3587 {
3588         struct bnxt *bp = dev->data->dev_private;
3589         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3590         uint64_t tx_tstamp_cycles = 0;
3591         uint64_t ns;
3592         int rc = 0;
3593
3594         if (!ptp)
3595                 return 0;
3596
3597         if (BNXT_CHIP_THOR(bp))
3598                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3599                                              &tx_tstamp_cycles);
3600         else
3601                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3602
3603         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3604         *timestamp = rte_ns_to_timespec(ns);
3605
3606         return rc;
3607 }
3608
3609 static int
3610 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3611 {
3612         struct bnxt *bp = dev->data->dev_private;
3613         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3614
3615         if (!ptp)
3616                 return 0;
3617
3618         ptp->tc.nsec += delta;
3619
3620         return 0;
3621 }
3622
3623 static int
3624 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3625 {
3626         struct bnxt *bp = dev->data->dev_private;
3627         int rc;
3628         uint32_t dir_entries;
3629         uint32_t entry_length;
3630
3631         rc = is_bnxt_in_error(bp);
3632         if (rc)
3633                 return rc;
3634
3635         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3636                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3637                     bp->pdev->addr.devid, bp->pdev->addr.function);
3638
3639         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3640         if (rc != 0)
3641                 return rc;
3642
3643         return dir_entries * entry_length;
3644 }
3645
3646 static int
3647 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3648                 struct rte_dev_eeprom_info *in_eeprom)
3649 {
3650         struct bnxt *bp = dev->data->dev_private;
3651         uint32_t index;
3652         uint32_t offset;
3653         int rc;
3654
3655         rc = is_bnxt_in_error(bp);
3656         if (rc)
3657                 return rc;
3658
3659         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3660                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3661                     bp->pdev->addr.devid, bp->pdev->addr.function,
3662                     in_eeprom->offset, in_eeprom->length);
3663
3664         if (in_eeprom->offset == 0) /* special offset value to get directory */
3665                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3666                                                 in_eeprom->data);
3667
3668         index = in_eeprom->offset >> 24;
3669         offset = in_eeprom->offset & 0xffffff;
3670
3671         if (index != 0)
3672                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3673                                            in_eeprom->length, in_eeprom->data);
3674
3675         return 0;
3676 }
3677
3678 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3679 {
3680         switch (dir_type) {
3681         case BNX_DIR_TYPE_CHIMP_PATCH:
3682         case BNX_DIR_TYPE_BOOTCODE:
3683         case BNX_DIR_TYPE_BOOTCODE_2:
3684         case BNX_DIR_TYPE_APE_FW:
3685         case BNX_DIR_TYPE_APE_PATCH:
3686         case BNX_DIR_TYPE_KONG_FW:
3687         case BNX_DIR_TYPE_KONG_PATCH:
3688         case BNX_DIR_TYPE_BONO_FW:
3689         case BNX_DIR_TYPE_BONO_PATCH:
3690                 /* FALLTHROUGH */
3691                 return true;
3692         }
3693
3694         return false;
3695 }
3696
3697 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3698 {
3699         switch (dir_type) {
3700         case BNX_DIR_TYPE_AVS:
3701         case BNX_DIR_TYPE_EXP_ROM_MBA:
3702         case BNX_DIR_TYPE_PCIE:
3703         case BNX_DIR_TYPE_TSCF_UCODE:
3704         case BNX_DIR_TYPE_EXT_PHY:
3705         case BNX_DIR_TYPE_CCM:
3706         case BNX_DIR_TYPE_ISCSI_BOOT:
3707         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3708         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3709                 /* FALLTHROUGH */
3710                 return true;
3711         }
3712
3713         return false;
3714 }
3715
3716 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3717 {
3718         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3719                 bnxt_dir_type_is_other_exec_format(dir_type);
3720 }
3721
3722 static int
3723 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3724                 struct rte_dev_eeprom_info *in_eeprom)
3725 {
3726         struct bnxt *bp = dev->data->dev_private;
3727         uint8_t index, dir_op;
3728         uint16_t type, ext, ordinal, attr;
3729         int rc;
3730
3731         rc = is_bnxt_in_error(bp);
3732         if (rc)
3733                 return rc;
3734
3735         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3736                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3737                     bp->pdev->addr.devid, bp->pdev->addr.function,
3738                     in_eeprom->offset, in_eeprom->length);
3739
3740         if (!BNXT_PF(bp)) {
3741                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3742                 return -EINVAL;
3743         }
3744
3745         type = in_eeprom->magic >> 16;
3746
3747         if (type == 0xffff) { /* special value for directory operations */
3748                 index = in_eeprom->magic & 0xff;
3749                 dir_op = in_eeprom->magic >> 8;
3750                 if (index == 0)
3751                         return -EINVAL;
3752                 switch (dir_op) {
3753                 case 0x0e: /* erase */
3754                         if (in_eeprom->offset != ~in_eeprom->magic)
3755                                 return -EINVAL;
3756                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3757                 default:
3758                         return -EINVAL;
3759                 }
3760         }
3761
3762         /* Create or re-write an NVM item: */
3763         if (bnxt_dir_type_is_executable(type) == true)
3764                 return -EOPNOTSUPP;
3765         ext = in_eeprom->magic & 0xffff;
3766         ordinal = in_eeprom->offset >> 16;
3767         attr = in_eeprom->offset & 0xffff;
3768
3769         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3770                                      in_eeprom->data, in_eeprom->length);
3771 }
3772
3773 /*
3774  * Initialization
3775  */
3776
3777 static const struct eth_dev_ops bnxt_dev_ops = {
3778         .dev_infos_get = bnxt_dev_info_get_op,
3779         .dev_close = bnxt_dev_close_op,
3780         .dev_configure = bnxt_dev_configure_op,
3781         .dev_start = bnxt_dev_start_op,
3782         .dev_stop = bnxt_dev_stop_op,
3783         .dev_set_link_up = bnxt_dev_set_link_up_op,
3784         .dev_set_link_down = bnxt_dev_set_link_down_op,
3785         .stats_get = bnxt_stats_get_op,
3786         .stats_reset = bnxt_stats_reset_op,
3787         .rx_queue_setup = bnxt_rx_queue_setup_op,
3788         .rx_queue_release = bnxt_rx_queue_release_op,
3789         .tx_queue_setup = bnxt_tx_queue_setup_op,
3790         .tx_queue_release = bnxt_tx_queue_release_op,
3791         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3792         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3793         .reta_update = bnxt_reta_update_op,
3794         .reta_query = bnxt_reta_query_op,
3795         .rss_hash_update = bnxt_rss_hash_update_op,
3796         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3797         .link_update = bnxt_link_update_op,
3798         .promiscuous_enable = bnxt_promiscuous_enable_op,
3799         .promiscuous_disable = bnxt_promiscuous_disable_op,
3800         .allmulticast_enable = bnxt_allmulticast_enable_op,
3801         .allmulticast_disable = bnxt_allmulticast_disable_op,
3802         .mac_addr_add = bnxt_mac_addr_add_op,
3803         .mac_addr_remove = bnxt_mac_addr_remove_op,
3804         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3805         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3806         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3807         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3808         .vlan_filter_set = bnxt_vlan_filter_set_op,
3809         .vlan_offload_set = bnxt_vlan_offload_set_op,
3810         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3811         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3812         .mtu_set = bnxt_mtu_set_op,
3813         .mac_addr_set = bnxt_set_default_mac_addr_op,
3814         .xstats_get = bnxt_dev_xstats_get_op,
3815         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3816         .xstats_reset = bnxt_dev_xstats_reset_op,
3817         .fw_version_get = bnxt_fw_version_get,
3818         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3819         .rxq_info_get = bnxt_rxq_info_get_op,
3820         .txq_info_get = bnxt_txq_info_get_op,
3821         .dev_led_on = bnxt_dev_led_on_op,
3822         .dev_led_off = bnxt_dev_led_off_op,
3823         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3824         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3825         .rx_queue_count = bnxt_rx_queue_count_op,
3826         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3827         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3828         .rx_queue_start = bnxt_rx_queue_start,
3829         .rx_queue_stop = bnxt_rx_queue_stop,
3830         .tx_queue_start = bnxt_tx_queue_start,
3831         .tx_queue_stop = bnxt_tx_queue_stop,
3832         .filter_ctrl = bnxt_filter_ctrl_op,
3833         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3834         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3835         .get_eeprom           = bnxt_get_eeprom_op,
3836         .set_eeprom           = bnxt_set_eeprom_op,
3837         .timesync_enable      = bnxt_timesync_enable,
3838         .timesync_disable     = bnxt_timesync_disable,
3839         .timesync_read_time   = bnxt_timesync_read_time,
3840         .timesync_write_time   = bnxt_timesync_write_time,
3841         .timesync_adjust_time = bnxt_timesync_adjust_time,
3842         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3843         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3844 };
3845
3846 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3847 {
3848         uint32_t offset;
3849
3850         /* Only pre-map the reset GRC registers using window 3 */
3851         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3852                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3853
3854         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3855
3856         return offset;
3857 }
3858
3859 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3860 {
3861         struct bnxt_error_recovery_info *info = bp->recovery_info;
3862         uint32_t reg_base = 0xffffffff;
3863         int i;
3864
3865         /* Only pre-map the monitoring GRC registers using window 2 */
3866         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3867                 uint32_t reg = info->status_regs[i];
3868
3869                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3870                         continue;
3871
3872                 if (reg_base == 0xffffffff)
3873                         reg_base = reg & 0xfffff000;
3874                 if ((reg & 0xfffff000) != reg_base)
3875                         return -ERANGE;
3876
3877                 /* Use mask 0xffc as the Lower 2 bits indicates
3878                  * address space location
3879                  */
3880                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3881                                                 (reg & 0xffc);
3882         }
3883
3884         if (reg_base == 0xffffffff)
3885                 return 0;
3886
3887         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3888                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3889
3890         return 0;
3891 }
3892
3893 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3894 {
3895         struct bnxt_error_recovery_info *info = bp->recovery_info;
3896         uint32_t delay = info->delay_after_reset[index];
3897         uint32_t val = info->reset_reg_val[index];
3898         uint32_t reg = info->reset_reg[index];
3899         uint32_t type, offset;
3900
3901         type = BNXT_FW_STATUS_REG_TYPE(reg);
3902         offset = BNXT_FW_STATUS_REG_OFF(reg);
3903
3904         switch (type) {
3905         case BNXT_FW_STATUS_REG_TYPE_CFG:
3906                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3907                 break;
3908         case BNXT_FW_STATUS_REG_TYPE_GRC:
3909                 offset = bnxt_map_reset_regs(bp, offset);
3910                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3911                 break;
3912         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3913                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3914                 break;
3915         }
3916         /* wait on a specific interval of time until core reset is complete */
3917         if (delay)
3918                 rte_delay_ms(delay);
3919 }
3920
3921 static void bnxt_dev_cleanup(struct bnxt *bp)
3922 {
3923         bnxt_set_hwrm_link_config(bp, false);
3924         bp->link_info.link_up = 0;
3925         if (bp->eth_dev->data->dev_started)
3926                 bnxt_dev_stop_op(bp->eth_dev);
3927
3928         bnxt_uninit_resources(bp, true);
3929 }
3930
3931 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3932 {
3933         struct rte_eth_dev *dev = bp->eth_dev;
3934         struct rte_vlan_filter_conf *vfc;
3935         int vidx, vbit, rc;
3936         uint16_t vlan_id;
3937
3938         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3939                 vfc = &dev->data->vlan_filter_conf;
3940                 vidx = vlan_id / 64;
3941                 vbit = vlan_id % 64;
3942
3943                 /* Each bit corresponds to a VLAN id */
3944                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3945                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3946                         if (rc)
3947                                 return rc;
3948                 }
3949         }
3950
3951         return 0;
3952 }
3953
3954 static int bnxt_restore_mac_filters(struct bnxt *bp)
3955 {
3956         struct rte_eth_dev *dev = bp->eth_dev;
3957         struct rte_eth_dev_info dev_info;
3958         struct rte_ether_addr *addr;
3959         uint64_t pool_mask;
3960         uint32_t pool = 0;
3961         uint16_t i;
3962         int rc;
3963
3964         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
3965                 return 0;
3966
3967         rc = bnxt_dev_info_get_op(dev, &dev_info);
3968         if (rc)
3969                 return rc;
3970
3971         /* replay MAC address configuration */
3972         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3973                 addr = &dev->data->mac_addrs[i];
3974
3975                 /* skip zero address */
3976                 if (rte_is_zero_ether_addr(addr))
3977                         continue;
3978
3979                 pool = 0;
3980                 pool_mask = dev->data->mac_pool_sel[i];
3981
3982                 do {
3983                         if (pool_mask & 1ULL) {
3984                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3985                                 if (rc)
3986                                         return rc;
3987                         }
3988                         pool_mask >>= 1;
3989                         pool++;
3990                 } while (pool_mask);
3991         }
3992
3993         return 0;
3994 }
3995
3996 static int bnxt_restore_filters(struct bnxt *bp)
3997 {
3998         struct rte_eth_dev *dev = bp->eth_dev;
3999         int ret = 0;
4000
4001         if (dev->data->all_multicast) {
4002                 ret = bnxt_allmulticast_enable_op(dev);
4003                 if (ret)
4004                         return ret;
4005         }
4006         if (dev->data->promiscuous) {
4007                 ret = bnxt_promiscuous_enable_op(dev);
4008                 if (ret)
4009                         return ret;
4010         }
4011
4012         ret = bnxt_restore_mac_filters(bp);
4013         if (ret)
4014                 return ret;
4015
4016         ret = bnxt_restore_vlan_filters(bp);
4017         /* TODO restore other filters as well */
4018         return ret;
4019 }
4020
4021 static void bnxt_dev_recover(void *arg)
4022 {
4023         struct bnxt *bp = arg;
4024         int timeout = bp->fw_reset_max_msecs;
4025         int rc = 0;
4026
4027         /* Clear Error flag so that device re-init should happen */
4028         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4029
4030         do {
4031                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4032                 if (rc == 0)
4033                         break;
4034                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4035                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4036         } while (rc && timeout);
4037
4038         if (rc) {
4039                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4040                 goto err;
4041         }
4042
4043         rc = bnxt_init_resources(bp, true);
4044         if (rc) {
4045                 PMD_DRV_LOG(ERR,
4046                             "Failed to initialize resources after reset\n");
4047                 goto err;
4048         }
4049         /* clear reset flag as the device is initialized now */
4050         bp->flags &= ~BNXT_FLAG_FW_RESET;
4051
4052         rc = bnxt_dev_start_op(bp->eth_dev);
4053         if (rc) {
4054                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4055                 goto err_start;
4056         }
4057
4058         rc = bnxt_restore_filters(bp);
4059         if (rc)
4060                 goto err_start;
4061
4062         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4063         return;
4064 err_start:
4065         bnxt_dev_stop_op(bp->eth_dev);
4066 err:
4067         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4068         bnxt_uninit_resources(bp, false);
4069         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4070 }
4071
4072 void bnxt_dev_reset_and_resume(void *arg)
4073 {
4074         struct bnxt *bp = arg;
4075         int rc;
4076
4077         bnxt_dev_cleanup(bp);
4078
4079         bnxt_wait_for_device_shutdown(bp);
4080
4081         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4082                                bnxt_dev_recover, (void *)bp);
4083         if (rc)
4084                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4085 }
4086
4087 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4088 {
4089         struct bnxt_error_recovery_info *info = bp->recovery_info;
4090         uint32_t reg = info->status_regs[index];
4091         uint32_t type, offset, val = 0;
4092
4093         type = BNXT_FW_STATUS_REG_TYPE(reg);
4094         offset = BNXT_FW_STATUS_REG_OFF(reg);
4095
4096         switch (type) {
4097         case BNXT_FW_STATUS_REG_TYPE_CFG:
4098                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4099                 break;
4100         case BNXT_FW_STATUS_REG_TYPE_GRC:
4101                 offset = info->mapped_status_regs[index];
4102                 /* FALLTHROUGH */
4103         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4104                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4105                                        offset));
4106                 break;
4107         }
4108
4109         return val;
4110 }
4111
4112 static int bnxt_fw_reset_all(struct bnxt *bp)
4113 {
4114         struct bnxt_error_recovery_info *info = bp->recovery_info;
4115         uint32_t i;
4116         int rc = 0;
4117
4118         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4119                 /* Reset through master function driver */
4120                 for (i = 0; i < info->reg_array_cnt; i++)
4121                         bnxt_write_fw_reset_reg(bp, i);
4122                 /* Wait for time specified by FW after triggering reset */
4123                 rte_delay_ms(info->master_func_wait_period_after_reset);
4124         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4125                 /* Reset with the help of Kong processor */
4126                 rc = bnxt_hwrm_fw_reset(bp);
4127                 if (rc)
4128                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4129         }
4130
4131         return rc;
4132 }
4133
4134 static void bnxt_fw_reset_cb(void *arg)
4135 {
4136         struct bnxt *bp = arg;
4137         struct bnxt_error_recovery_info *info = bp->recovery_info;
4138         int rc = 0;
4139
4140         /* Only Master function can do FW reset */
4141         if (bnxt_is_master_func(bp) &&
4142             bnxt_is_recovery_enabled(bp)) {
4143                 rc = bnxt_fw_reset_all(bp);
4144                 if (rc) {
4145                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4146                         return;
4147                 }
4148         }
4149
4150         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4151          * EXCEPTION_FATAL_ASYNC event to all the functions
4152          * (including MASTER FUNC). After receiving this Async, all the active
4153          * drivers should treat this case as FW initiated recovery
4154          */
4155         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4156                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4157                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4158
4159                 /* To recover from error */
4160                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4161                                   (void *)bp);
4162         }
4163 }
4164
4165 /* Driver should poll FW heartbeat, reset_counter with the frequency
4166  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4167  * When the driver detects heartbeat stop or change in reset_counter,
4168  * it has to trigger a reset to recover from the error condition.
4169  * A “master PF” is the function who will have the privilege to
4170  * initiate the chimp reset. The master PF will be elected by the
4171  * firmware and will be notified through async message.
4172  */
4173 static void bnxt_check_fw_health(void *arg)
4174 {
4175         struct bnxt *bp = arg;
4176         struct bnxt_error_recovery_info *info = bp->recovery_info;
4177         uint32_t val = 0, wait_msec;
4178
4179         if (!info || !bnxt_is_recovery_enabled(bp) ||
4180             is_bnxt_in_error(bp))
4181                 return;
4182
4183         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4184         if (val == info->last_heart_beat)
4185                 goto reset;
4186
4187         info->last_heart_beat = val;
4188
4189         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4190         if (val != info->last_reset_counter)
4191                 goto reset;
4192
4193         info->last_reset_counter = val;
4194
4195         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4196                           bnxt_check_fw_health, (void *)bp);
4197
4198         return;
4199 reset:
4200         /* Stop DMA to/from device */
4201         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4202         bp->flags |= BNXT_FLAG_FW_RESET;
4203
4204         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4205
4206         if (bnxt_is_master_func(bp))
4207                 wait_msec = info->master_func_wait_period;
4208         else
4209                 wait_msec = info->normal_func_wait_period;
4210
4211         rte_eal_alarm_set(US_PER_MS * wait_msec,
4212                           bnxt_fw_reset_cb, (void *)bp);
4213 }
4214
4215 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4216 {
4217         uint32_t polling_freq;
4218
4219         if (!bnxt_is_recovery_enabled(bp))
4220                 return;
4221
4222         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4223                 return;
4224
4225         polling_freq = bp->recovery_info->driver_polling_freq;
4226
4227         rte_eal_alarm_set(US_PER_MS * polling_freq,
4228                           bnxt_check_fw_health, (void *)bp);
4229         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4230 }
4231
4232 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4233 {
4234         if (!bnxt_is_recovery_enabled(bp))
4235                 return;
4236
4237         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4238         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4239 }
4240
4241 static bool bnxt_vf_pciid(uint16_t device_id)
4242 {
4243         switch (device_id) {
4244         case BROADCOM_DEV_ID_57304_VF:
4245         case BROADCOM_DEV_ID_57406_VF:
4246         case BROADCOM_DEV_ID_5731X_VF:
4247         case BROADCOM_DEV_ID_5741X_VF:
4248         case BROADCOM_DEV_ID_57414_VF:
4249         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4250         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4251         case BROADCOM_DEV_ID_58802_VF:
4252         case BROADCOM_DEV_ID_57500_VF1:
4253         case BROADCOM_DEV_ID_57500_VF2:
4254                 /* FALLTHROUGH */
4255                 return true;
4256         default:
4257                 return false;
4258         }
4259 }
4260
4261 static bool bnxt_thor_device(uint16_t device_id)
4262 {
4263         switch (device_id) {
4264         case BROADCOM_DEV_ID_57508:
4265         case BROADCOM_DEV_ID_57504:
4266         case BROADCOM_DEV_ID_57502:
4267         case BROADCOM_DEV_ID_57508_MF1:
4268         case BROADCOM_DEV_ID_57504_MF1:
4269         case BROADCOM_DEV_ID_57502_MF1:
4270         case BROADCOM_DEV_ID_57508_MF2:
4271         case BROADCOM_DEV_ID_57504_MF2:
4272         case BROADCOM_DEV_ID_57502_MF2:
4273         case BROADCOM_DEV_ID_57500_VF1:
4274         case BROADCOM_DEV_ID_57500_VF2:
4275                 /* FALLTHROUGH */
4276                 return true;
4277         default:
4278                 return false;
4279         }
4280 }
4281
4282 bool bnxt_stratus_device(struct bnxt *bp)
4283 {
4284         uint16_t device_id = bp->pdev->id.device_id;
4285
4286         switch (device_id) {
4287         case BROADCOM_DEV_ID_STRATUS_NIC:
4288         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4289         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4290                 /* FALLTHROUGH */
4291                 return true;
4292         default:
4293                 return false;
4294         }
4295 }
4296
4297 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4298 {
4299         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4300         struct bnxt *bp = eth_dev->data->dev_private;
4301
4302         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4303         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4304         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4305         if (!bp->bar0 || !bp->doorbell_base) {
4306                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4307                 return -ENODEV;
4308         }
4309
4310         bp->eth_dev = eth_dev;
4311         bp->pdev = pci_dev;
4312
4313         return 0;
4314 }
4315
4316 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4317                                   struct bnxt_ctx_pg_info *ctx_pg,
4318                                   uint32_t mem_size,
4319                                   const char *suffix,
4320                                   uint16_t idx)
4321 {
4322         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4323         const struct rte_memzone *mz = NULL;
4324         char mz_name[RTE_MEMZONE_NAMESIZE];
4325         rte_iova_t mz_phys_addr;
4326         uint64_t valid_bits = 0;
4327         uint32_t sz;
4328         int i;
4329
4330         if (!mem_size)
4331                 return 0;
4332
4333         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4334                          BNXT_PAGE_SIZE;
4335         rmem->page_size = BNXT_PAGE_SIZE;
4336         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4337         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4338         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4339
4340         valid_bits = PTU_PTE_VALID;
4341
4342         if (rmem->nr_pages > 1) {
4343                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4344                          "bnxt_ctx_pg_tbl%s_%x_%d",
4345                          suffix, idx, bp->eth_dev->data->port_id);
4346                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4347                 mz = rte_memzone_lookup(mz_name);
4348                 if (!mz) {
4349                         mz = rte_memzone_reserve_aligned(mz_name,
4350                                                 rmem->nr_pages * 8,
4351                                                 SOCKET_ID_ANY,
4352                                                 RTE_MEMZONE_2MB |
4353                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4354                                                 RTE_MEMZONE_IOVA_CONTIG,
4355                                                 BNXT_PAGE_SIZE);
4356                         if (mz == NULL)
4357                                 return -ENOMEM;
4358                 }
4359
4360                 memset(mz->addr, 0, mz->len);
4361                 mz_phys_addr = mz->iova;
4362
4363                 rmem->pg_tbl = mz->addr;
4364                 rmem->pg_tbl_map = mz_phys_addr;
4365                 rmem->pg_tbl_mz = mz;
4366         }
4367
4368         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4369                  suffix, idx, bp->eth_dev->data->port_id);
4370         mz = rte_memzone_lookup(mz_name);
4371         if (!mz) {
4372                 mz = rte_memzone_reserve_aligned(mz_name,
4373                                                  mem_size,
4374                                                  SOCKET_ID_ANY,
4375                                                  RTE_MEMZONE_1GB |
4376                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4377                                                  RTE_MEMZONE_IOVA_CONTIG,
4378                                                  BNXT_PAGE_SIZE);
4379                 if (mz == NULL)
4380                         return -ENOMEM;
4381         }
4382
4383         memset(mz->addr, 0, mz->len);
4384         mz_phys_addr = mz->iova;
4385
4386         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4387                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4388                 rmem->dma_arr[i] = mz_phys_addr + sz;
4389
4390                 if (rmem->nr_pages > 1) {
4391                         if (i == rmem->nr_pages - 2 &&
4392                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4393                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4394                         else if (i == rmem->nr_pages - 1 &&
4395                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4396                                 valid_bits |= PTU_PTE_LAST;
4397
4398                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4399                                                            valid_bits);
4400                 }
4401         }
4402
4403         rmem->mz = mz;
4404         if (rmem->vmem_size)
4405                 rmem->vmem = (void **)mz->addr;
4406         rmem->dma_arr[0] = mz_phys_addr;
4407         return 0;
4408 }
4409
4410 static void bnxt_free_ctx_mem(struct bnxt *bp)
4411 {
4412         int i;
4413
4414         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4415                 return;
4416
4417         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4418         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4419         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4420         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4421         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4422         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4423         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4424         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4425         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4426         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4427         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4428
4429         for (i = 0; i < BNXT_MAX_Q; i++) {
4430                 if (bp->ctx->tqm_mem[i])
4431                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4432         }
4433
4434         rte_free(bp->ctx);
4435         bp->ctx = NULL;
4436 }
4437
4438 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4439
4440 #define min_t(type, x, y) ({                    \
4441         type __min1 = (x);                      \
4442         type __min2 = (y);                      \
4443         __min1 < __min2 ? __min1 : __min2; })
4444
4445 #define max_t(type, x, y) ({                    \
4446         type __max1 = (x);                      \
4447         type __max2 = (y);                      \
4448         __max1 > __max2 ? __max1 : __max2; })
4449
4450 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4451
4452 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4453 {
4454         struct bnxt_ctx_pg_info *ctx_pg;
4455         struct bnxt_ctx_mem_info *ctx;
4456         uint32_t mem_size, ena, entries;
4457         int i, rc;
4458
4459         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4460         if (rc) {
4461                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4462                 return rc;
4463         }
4464         ctx = bp->ctx;
4465         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4466                 return 0;
4467
4468         ctx_pg = &ctx->qp_mem;
4469         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4470         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4471         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4472         if (rc)
4473                 return rc;
4474
4475         ctx_pg = &ctx->srq_mem;
4476         ctx_pg->entries = ctx->srq_max_l2_entries;
4477         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4478         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4479         if (rc)
4480                 return rc;
4481
4482         ctx_pg = &ctx->cq_mem;
4483         ctx_pg->entries = ctx->cq_max_l2_entries;
4484         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4485         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4486         if (rc)
4487                 return rc;
4488
4489         ctx_pg = &ctx->vnic_mem;
4490         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4491                 ctx->vnic_max_ring_table_entries;
4492         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4493         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4494         if (rc)
4495                 return rc;
4496
4497         ctx_pg = &ctx->stat_mem;
4498         ctx_pg->entries = ctx->stat_max_entries;
4499         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4500         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4501         if (rc)
4502                 return rc;
4503
4504         entries = ctx->qp_max_l2_entries +
4505                   ctx->vnic_max_vnic_entries +
4506                   ctx->tqm_min_entries_per_ring;
4507         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4508         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4509                           ctx->tqm_max_entries_per_ring);
4510         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4511                 ctx_pg = ctx->tqm_mem[i];
4512                 /* use min tqm entries for now. */
4513                 ctx_pg->entries = entries;
4514                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4515                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4516                 if (rc)
4517                         return rc;
4518                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4519         }
4520
4521         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4522         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4523         if (rc)
4524                 PMD_DRV_LOG(ERR,
4525                             "Failed to configure context mem: rc = %d\n", rc);
4526         else
4527                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4528
4529         return rc;
4530 }
4531
4532 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4533 {
4534         struct rte_pci_device *pci_dev = bp->pdev;
4535         char mz_name[RTE_MEMZONE_NAMESIZE];
4536         const struct rte_memzone *mz = NULL;
4537         uint32_t total_alloc_len;
4538         rte_iova_t mz_phys_addr;
4539
4540         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4541                 return 0;
4542
4543         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4544                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4545                  pci_dev->addr.bus, pci_dev->addr.devid,
4546                  pci_dev->addr.function, "rx_port_stats");
4547         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4548         mz = rte_memzone_lookup(mz_name);
4549         total_alloc_len =
4550                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4551                                        sizeof(struct rx_port_stats_ext) + 512);
4552         if (!mz) {
4553                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4554                                          SOCKET_ID_ANY,
4555                                          RTE_MEMZONE_2MB |
4556                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4557                                          RTE_MEMZONE_IOVA_CONTIG);
4558                 if (mz == NULL)
4559                         return -ENOMEM;
4560         }
4561         memset(mz->addr, 0, mz->len);
4562         mz_phys_addr = mz->iova;
4563
4564         bp->rx_mem_zone = (const void *)mz;
4565         bp->hw_rx_port_stats = mz->addr;
4566         bp->hw_rx_port_stats_map = mz_phys_addr;
4567
4568         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4569                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4570                  pci_dev->addr.bus, pci_dev->addr.devid,
4571                  pci_dev->addr.function, "tx_port_stats");
4572         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4573         mz = rte_memzone_lookup(mz_name);
4574         total_alloc_len =
4575                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4576                                        sizeof(struct tx_port_stats_ext) + 512);
4577         if (!mz) {
4578                 mz = rte_memzone_reserve(mz_name,
4579                                          total_alloc_len,
4580                                          SOCKET_ID_ANY,
4581                                          RTE_MEMZONE_2MB |
4582                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4583                                          RTE_MEMZONE_IOVA_CONTIG);
4584                 if (mz == NULL)
4585                         return -ENOMEM;
4586         }
4587         memset(mz->addr, 0, mz->len);
4588         mz_phys_addr = mz->iova;
4589
4590         bp->tx_mem_zone = (const void *)mz;
4591         bp->hw_tx_port_stats = mz->addr;
4592         bp->hw_tx_port_stats_map = mz_phys_addr;
4593         bp->flags |= BNXT_FLAG_PORT_STATS;
4594
4595         /* Display extended statistics if FW supports it */
4596         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4597             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4598             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4599                 return 0;
4600
4601         bp->hw_rx_port_stats_ext = (void *)
4602                 ((uint8_t *)bp->hw_rx_port_stats +
4603                  sizeof(struct rx_port_stats));
4604         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4605                 sizeof(struct rx_port_stats);
4606         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4607
4608         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4609             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4610                 bp->hw_tx_port_stats_ext = (void *)
4611                         ((uint8_t *)bp->hw_tx_port_stats +
4612                          sizeof(struct tx_port_stats));
4613                 bp->hw_tx_port_stats_ext_map =
4614                         bp->hw_tx_port_stats_map +
4615                         sizeof(struct tx_port_stats);
4616                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4617         }
4618
4619         return 0;
4620 }
4621
4622 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4623 {
4624         struct bnxt *bp = eth_dev->data->dev_private;
4625         int rc = 0;
4626
4627         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4628                                                RTE_ETHER_ADDR_LEN *
4629                                                bp->max_l2_ctx,
4630                                                0);
4631         if (eth_dev->data->mac_addrs == NULL) {
4632                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4633                 return -ENOMEM;
4634         }
4635
4636         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4637                 if (BNXT_PF(bp))
4638                         return -EINVAL;
4639
4640                 /* Generate a random MAC address, if none was assigned by PF */
4641                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4642                 bnxt_eth_hw_addr_random(bp->mac_addr);
4643                 PMD_DRV_LOG(INFO,
4644                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4645                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4646                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4647
4648                 rc = bnxt_hwrm_set_mac(bp);
4649                 if (!rc)
4650                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4651                                RTE_ETHER_ADDR_LEN);
4652                 return rc;
4653         }
4654
4655         /* Copy the permanent MAC from the FUNC_QCAPS response */
4656         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4657         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4658
4659         return rc;
4660 }
4661
4662 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4663 {
4664         int rc = 0;
4665
4666         /* MAC is already configured in FW */
4667         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4668                 return 0;
4669
4670         /* Restore the old MAC configured */
4671         rc = bnxt_hwrm_set_mac(bp);
4672         if (rc)
4673                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4674
4675         return rc;
4676 }
4677
4678 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4679 {
4680         if (!BNXT_PF(bp))
4681                 return;
4682
4683 #define ALLOW_FUNC(x)   \
4684         { \
4685                 uint32_t arg = (x); \
4686                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4687                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4688         }
4689
4690         /* Forward all requests if firmware is new enough */
4691         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4692              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4693             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4694                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4695         } else {
4696                 PMD_DRV_LOG(WARNING,
4697                             "Firmware too old for VF mailbox functionality\n");
4698                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4699         }
4700
4701         /*
4702          * The following are used for driver cleanup. If we disallow these,
4703          * VF drivers can't clean up cleanly.
4704          */
4705         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4706         ALLOW_FUNC(HWRM_VNIC_FREE);
4707         ALLOW_FUNC(HWRM_RING_FREE);
4708         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4709         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4710         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4711         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4712         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4713         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4714 }
4715
4716 uint16_t
4717 bnxt_get_svif(uint16_t port_id, bool func_svif)
4718 {
4719         struct rte_eth_dev *eth_dev;
4720         struct bnxt *bp;
4721
4722         eth_dev = &rte_eth_devices[port_id];
4723         bp = eth_dev->data->dev_private;
4724
4725         return func_svif ? bp->func_svif : bp->port_svif;
4726 }
4727
4728 uint16_t
4729 bnxt_get_vnic_id(uint16_t port)
4730 {
4731         struct rte_eth_dev *eth_dev;
4732         struct bnxt_vnic_info *vnic;
4733         struct bnxt *bp;
4734
4735         eth_dev = &rte_eth_devices[port];
4736         bp = eth_dev->data->dev_private;
4737
4738         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4739
4740         return vnic->fw_vnic_id;
4741 }
4742
4743 static int bnxt_init_fw(struct bnxt *bp)
4744 {
4745         uint16_t mtu;
4746         int rc = 0;
4747
4748         bp->fw_cap = 0;
4749
4750         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4751         if (rc)
4752                 return rc;
4753
4754         rc = bnxt_hwrm_func_reset(bp);
4755         if (rc)
4756                 return -EIO;
4757
4758         rc = bnxt_hwrm_vnic_qcaps(bp);
4759         if (rc)
4760                 return rc;
4761
4762         rc = bnxt_hwrm_queue_qportcfg(bp);
4763         if (rc)
4764                 return rc;
4765
4766         /* Get the MAX capabilities for this function.
4767          * This function also allocates context memory for TQM rings and
4768          * informs the firmware about this allocated backing store memory.
4769          */
4770         rc = bnxt_hwrm_func_qcaps(bp);
4771         if (rc)
4772                 return rc;
4773
4774         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4775         if (rc)
4776                 return rc;
4777
4778         bnxt_hwrm_port_mac_qcfg(bp);
4779
4780         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4781         if (rc)
4782                 return rc;
4783
4784         /* Get the adapter error recovery support info */
4785         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4786         if (rc)
4787                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4788
4789         bnxt_hwrm_port_led_qcaps(bp);
4790
4791         return 0;
4792 }
4793
4794 static int
4795 bnxt_init_locks(struct bnxt *bp)
4796 {
4797         int err;
4798
4799         err = pthread_mutex_init(&bp->flow_lock, NULL);
4800         if (err) {
4801                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4802                 return err;
4803         }
4804
4805         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4806         if (err)
4807                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4808         return err;
4809 }
4810
4811 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4812 {
4813         int rc;
4814
4815         rc = bnxt_init_fw(bp);
4816         if (rc)
4817                 return rc;
4818
4819         if (!reconfig_dev) {
4820                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4821                 if (rc)
4822                         return rc;
4823         } else {
4824                 rc = bnxt_restore_dflt_mac(bp);
4825                 if (rc)
4826                         return rc;
4827         }
4828
4829         bnxt_config_vf_req_fwd(bp);
4830
4831         rc = bnxt_hwrm_func_driver_register(bp);
4832         if (rc) {
4833                 PMD_DRV_LOG(ERR, "Failed to register driver");
4834                 return -EBUSY;
4835         }
4836
4837         if (BNXT_PF(bp)) {
4838                 if (bp->pdev->max_vfs) {
4839                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4840                         if (rc) {
4841                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4842                                 return rc;
4843                         }
4844                 } else {
4845                         rc = bnxt_hwrm_allocate_pf_only(bp);
4846                         if (rc) {
4847                                 PMD_DRV_LOG(ERR,
4848                                             "Failed to allocate PF resources");
4849                                 return rc;
4850                         }
4851                 }
4852         }
4853
4854         rc = bnxt_alloc_mem(bp, reconfig_dev);
4855         if (rc)
4856                 return rc;
4857
4858         rc = bnxt_setup_int(bp);
4859         if (rc)
4860                 return rc;
4861
4862         rc = bnxt_request_int(bp);
4863         if (rc)
4864                 return rc;
4865
4866         rc = bnxt_init_locks(bp);
4867         if (rc)
4868                 return rc;
4869
4870         return 0;
4871 }
4872
4873 static int
4874 bnxt_parse_devarg_truflow(__rte_unused const char *key,
4875                           const char *value, void *opaque_arg)
4876 {
4877         struct bnxt *bp = opaque_arg;
4878         unsigned long truflow;
4879         char *end = NULL;
4880
4881         if (!value || !opaque_arg) {
4882                 PMD_DRV_LOG(ERR,
4883                             "Invalid parameter passed to truflow devargs.\n");
4884                 return -EINVAL;
4885         }
4886
4887         truflow = strtoul(value, &end, 10);
4888         if (end == NULL || *end != '\0' ||
4889             (truflow == ULONG_MAX && errno == ERANGE)) {
4890                 PMD_DRV_LOG(ERR,
4891                             "Invalid parameter passed to truflow devargs.\n");
4892                 return -EINVAL;
4893         }
4894
4895         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
4896                 PMD_DRV_LOG(ERR,
4897                             "Invalid value passed to truflow devargs.\n");
4898                 return -EINVAL;
4899         }
4900
4901         bp->truflow = truflow;
4902         if (bp->truflow)
4903                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
4904
4905         return 0;
4906 }
4907
4908 static void
4909 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
4910 {
4911         struct rte_kvargs *kvlist;
4912
4913         if (devargs == NULL)
4914                 return;
4915
4916         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
4917         if (kvlist == NULL)
4918                 return;
4919
4920         /*
4921          * Handler for "truflow" devarg.
4922          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1”
4923          */
4924         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
4925                            bnxt_parse_devarg_truflow, bp);
4926
4927         rte_kvargs_free(kvlist);
4928 }
4929
4930 static int
4931 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4932 {
4933         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4934         static int version_printed;
4935         struct bnxt *bp;
4936         int rc;
4937
4938         if (version_printed++ == 0)
4939                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4940
4941         eth_dev->dev_ops = &bnxt_dev_ops;
4942         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4943         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4944
4945         /*
4946          * For secondary processes, we don't initialise any further
4947          * as primary has already done this work.
4948          */
4949         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4950                 return 0;
4951
4952         rte_eth_copy_pci_info(eth_dev, pci_dev);
4953
4954         bp = eth_dev->data->dev_private;
4955
4956         /* Parse dev arguments passed on when starting the DPDK application. */
4957         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
4958
4959         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
4960
4961         if (bnxt_vf_pciid(pci_dev->id.device_id))
4962                 bp->flags |= BNXT_FLAG_VF;
4963
4964         if (bnxt_thor_device(pci_dev->id.device_id))
4965                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4966
4967         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4968             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4969             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4970             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4971                 bp->flags |= BNXT_FLAG_STINGRAY;
4972
4973         rc = bnxt_init_board(eth_dev);
4974         if (rc) {
4975                 PMD_DRV_LOG(ERR,
4976                             "Failed to initialize board rc: %x\n", rc);
4977                 return rc;
4978         }
4979
4980         rc = bnxt_alloc_hwrm_resources(bp);
4981         if (rc) {
4982                 PMD_DRV_LOG(ERR,
4983                             "Failed to allocate hwrm resource rc: %x\n", rc);
4984                 goto error_free;
4985         }
4986         rc = bnxt_init_resources(bp, false);
4987         if (rc)
4988                 goto error_free;
4989
4990         rc = bnxt_alloc_stats_mem(bp);
4991         if (rc)
4992                 goto error_free;
4993
4994         /* Pass the information to the rte_eth_dev_close() that it should also
4995          * release the private port resources.
4996          */
4997         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
4998
4999         PMD_DRV_LOG(INFO,
5000                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5001                     pci_dev->mem_resource[0].phys_addr,
5002                     pci_dev->mem_resource[0].addr);
5003
5004         return 0;
5005
5006 error_free:
5007         bnxt_dev_uninit(eth_dev);
5008         return rc;
5009 }
5010
5011 static void
5012 bnxt_uninit_locks(struct bnxt *bp)
5013 {
5014         pthread_mutex_destroy(&bp->flow_lock);
5015         pthread_mutex_destroy(&bp->def_cp_lock);
5016 }
5017
5018 static int
5019 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5020 {
5021         int rc;
5022
5023         bnxt_free_int(bp);
5024         bnxt_free_mem(bp, reconfig_dev);
5025         bnxt_hwrm_func_buf_unrgtr(bp);
5026         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5027         bp->flags &= ~BNXT_FLAG_REGISTERED;
5028         bnxt_free_ctx_mem(bp);
5029         if (!reconfig_dev) {
5030                 bnxt_free_hwrm_resources(bp);
5031
5032                 if (bp->recovery_info != NULL) {
5033                         rte_free(bp->recovery_info);
5034                         bp->recovery_info = NULL;
5035                 }
5036         }
5037
5038         bnxt_uninit_locks(bp);
5039         rte_free(bp->ptp_cfg);
5040         bp->ptp_cfg = NULL;
5041         return rc;
5042 }
5043
5044 static int
5045 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5046 {
5047         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5048                 return -EPERM;
5049
5050         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5051
5052         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5053                 bnxt_dev_close_op(eth_dev);
5054
5055         return 0;
5056 }
5057
5058 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5059         struct rte_pci_device *pci_dev)
5060 {
5061         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
5062                 bnxt_dev_init);
5063 }
5064
5065 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5066 {
5067         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
5068                 return rte_eth_dev_pci_generic_remove(pci_dev,
5069                                 bnxt_dev_uninit);
5070         else
5071                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5072 }
5073
5074 static struct rte_pci_driver bnxt_rte_pmd = {
5075         .id_table = bnxt_pci_id_map,
5076         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5077         .probe = bnxt_pci_probe,
5078         .remove = bnxt_pci_remove,
5079 };
5080
5081 static bool
5082 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5083 {
5084         if (strcmp(dev->device->driver->name, drv->driver.name))
5085                 return false;
5086
5087         return true;
5088 }
5089
5090 bool is_bnxt_supported(struct rte_eth_dev *dev)
5091 {
5092         return is_device_supported(dev, &bnxt_rte_pmd);
5093 }
5094
5095 RTE_INIT(bnxt_init_log)
5096 {
5097         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
5098         if (bnxt_logtype_driver >= 0)
5099                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
5100 }
5101
5102 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5103 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5104 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");