drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_cpr.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30 #include "bnxt_util.h"
  31
  32 #define DRV_MODULE_NAME         "bnxt"
  33 static const char bnxt_version[] =
  34         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  35 int bnxt_logtype_driver;
  36
  37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  38
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  43 #define BROADCOM_DEV_ID_57301 0x16c8
  44 #define BROADCOM_DEV_ID_57302 0x16c9
  45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  48 #define BROADCOM_DEV_ID_NS2 0x16cd
  49 #define BROADCOM_DEV_ID_57311 0x16ce
  50 #define BROADCOM_DEV_ID_57312 0x16cf
  51 #define BROADCOM_DEV_ID_57402 0x16d0
  52 #define BROADCOM_DEV_ID_57404 0x16d1
  53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  57 #define BROADCOM_DEV_ID_57412 0x16d6
  58 #define BROADCOM_DEV_ID_57414 0x16d7
  59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  62 #define BROADCOM_DEV_ID_57412_MF 0x16de
  63 #define BROADCOM_DEV_ID_57314 0x16df
  64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  75 #define BROADCOM_DEV_ID_57508 0x1750
  76 #define BROADCOM_DEV_ID_57504 0x1751
  77 #define BROADCOM_DEV_ID_57502 0x1752
  78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
  79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
  80 #define BROADCOM_DEV_ID_58802 0xd802
  81 #define BROADCOM_DEV_ID_58804 0xd804
  82 #define BROADCOM_DEV_ID_58808 0x16f0
  83 #define BROADCOM_DEV_ID_58802_VF 0xd800
  84
  85 static const struct rte_pci_id bnxt_pci_id_map[] = {
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  87                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  89                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 130         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 131         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
 132         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
 133         { .vendor_id = 0, /* sentinel */ },
 134 };
 135
 136 #define BNXT_ETH_RSS_SUPPORT (  \
 137         ETH_RSS_IPV4 |          \
 138         ETH_RSS_NONFRAG_IPV4_TCP |      \
 139         ETH_RSS_NONFRAG_IPV4_UDP |      \
 140         ETH_RSS_IPV6 |          \
 141         ETH_RSS_NONFRAG_IPV6_TCP |      \
 142         ETH_RSS_NONFRAG_IPV6_UDP)
 143
 144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 145                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 146                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 147                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 148                                      DEV_TX_OFFLOAD_TCP_TSO | \
 149                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 150                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 152                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 153                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 154                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 155
 156 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 157                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 158                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 159                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 160                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 161                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 162                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 163                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 164                                      DEV_RX_OFFLOAD_TCP_LRO)
 165
 166 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 167 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 168 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 169 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 170 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 171 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 172 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 173
 174 int is_bnxt_in_error(struct bnxt *bp)
 175 {
 176         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 177                 return -EIO;
 178         if (bp->flags & BNXT_FLAG_FW_RESET)
 179                 return -EBUSY;
 180
 181         return 0;
 182 }
 183
 184 /***********************/
 185
 186 /*
 187  * High level utility functions
 188  */
 189
 190 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 191 {
 192         if (!BNXT_CHIP_THOR(bp))
 193                 return 1;
 194
 195         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 196                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 197                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 198 }
 199
 200 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 201 {
 202         if (!BNXT_CHIP_THOR(bp))
 203                 return HW_HASH_INDEX_SIZE;
 204
 205         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 206 }
 207
 208 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 209 {
 210         bnxt_free_filter_mem(bp);
 211         bnxt_free_vnic_attributes(bp);
 212         bnxt_free_vnic_mem(bp);
 213
 214         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 215          * If the number of rings change across fw update,
 216          * we don't have much choice except to warn the user.
 217          */
 218         if (!reconfig) {
 219                 bnxt_free_stats(bp);
 220                 bnxt_free_tx_rings(bp);
 221                 bnxt_free_rx_rings(bp);
 222         }
 223         bnxt_free_async_cp_ring(bp);
 224 }
 225
 226 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 227 {
 228         int rc;
 229
 230         rc = bnxt_alloc_ring_grps(bp);
 231         if (rc)
 232                 goto alloc_mem_err;
 233
 234         rc = bnxt_alloc_async_ring_struct(bp);
 235         if (rc)
 236                 goto alloc_mem_err;
 237
 238         rc = bnxt_alloc_vnic_mem(bp);
 239         if (rc)
 240                 goto alloc_mem_err;
 241
 242         rc = bnxt_alloc_vnic_attributes(bp);
 243         if (rc)
 244                 goto alloc_mem_err;
 245
 246         rc = bnxt_alloc_filter_mem(bp);
 247         if (rc)
 248                 goto alloc_mem_err;
 249
 250         rc = bnxt_alloc_async_cp_ring(bp);
 251         if (rc)
 252                 goto alloc_mem_err;
 253
 254         return 0;
 255
 256 alloc_mem_err:
 257         bnxt_free_mem(bp, reconfig);
 258         return rc;
 259 }
 260
 261 static int bnxt_init_chip(struct bnxt *bp)
 262 {
 263         struct bnxt_rx_queue *rxq;
 264         struct rte_eth_link new;
 265         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 266         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 267         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 268         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 269         uint32_t intr_vector = 0;
 270         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 271         uint32_t vec = BNXT_MISC_VEC_ID;
 272         unsigned int i, j;
 273         int rc;
 274
 275         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 276                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 277                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 278                 bp->flags |= BNXT_FLAG_JUMBO;
 279         } else {
 280                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 281                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 282                 bp->flags &= ~BNXT_FLAG_JUMBO;
 283         }
 284
 285         /* THOR does not support ring groups.
 286          * But we will use the array to save RSS context IDs.
 287          */
 288         if (BNXT_CHIP_THOR(bp))
 289                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 290
 291         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 292         if (rc) {
 293                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 294                 goto err_out;
 295         }
 296
 297         rc = bnxt_alloc_hwrm_rings(bp);
 298         if (rc) {
 299                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 300                 goto err_out;
 301         }
 302
 303         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 304         if (rc) {
 305                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 306                 goto err_out;
 307         }
 308
 309         rc = bnxt_mq_rx_configure(bp);
 310         if (rc) {
 311                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 312                 goto err_out;
 313         }
 314
 315         /* VNIC configuration */
 316         for (i = 0; i < bp->nr_vnics; i++) {
 317                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 318                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 319                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 320
 321                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 322                 if (!vnic->fw_grp_ids) {
 323                         PMD_DRV_LOG(ERR,
 324                                     "Failed to alloc %d bytes for group ids\n",
 325                                     size);
 326                         rc = -ENOMEM;
 327                         goto err_out;
 328                 }
 329                 memset(vnic->fw_grp_ids, -1, size);
 330
 331                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 332                             i, vnic, vnic->fw_grp_ids);
 333
 334                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 335                 if (rc) {
 336                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 337                                 i, rc);
 338                         goto err_out;
 339                 }
 340
 341                 /* Alloc RSS context only if RSS mode is enabled */
 342                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 343                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 344
 345                         rc = 0;
 346                         for (j = 0; j < nr_ctxs; j++) {
 347                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 348                                 if (rc)
 349                                         break;
 350                         }
 351                         if (rc) {
 352                                 PMD_DRV_LOG(ERR,
 353                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 354                                   i, j, rc);
 355                                 goto err_out;
 356                         }
 357                         vnic->num_lb_ctxts = nr_ctxs;
 358                 }
 359
 360                 /*
 361                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 362                  * setting is not available at this time, it will not be
 363                  * configured correctly in the CFA.
 364                  */
 365                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 366                         vnic->vlan_strip = true;
 367                 else
 368                         vnic->vlan_strip = false;
 369
 370                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 371                 if (rc) {
 372                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 373                                 i, rc);
 374                         goto err_out;
 375                 }
 376
 377                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 378                 if (rc) {
 379                         PMD_DRV_LOG(ERR,
 380                                 "HWRM vnic %d filter failure rc: %x\n",
 381                                 i, rc);
 382                         goto err_out;
 383                 }
 384
 385                 for (j = 0; j < bp->rx_nr_rings; j++) {
 386                         rxq = bp->eth_dev->data->rx_queues[j];
 387
 388                         PMD_DRV_LOG(DEBUG,
 389                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 390                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 391
 392                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 393                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 394                 }
 395
 396                 rc = bnxt_vnic_rss_configure(bp, vnic);
 397                 if (rc) {
 398                         PMD_DRV_LOG(ERR,
 399                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 400                         goto err_out;
 401                 }
 402
 403                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 404
 405                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 406                     DEV_RX_OFFLOAD_TCP_LRO)
 407                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 408                 else
 409                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 410         }
 411         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 412         if (rc) {
 413                 PMD_DRV_LOG(ERR,
 414                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 415                 goto err_out;
 416         }
 417
 418         /* check and configure queue intr-vector mapping */
 419         if ((rte_intr_cap_multiple(intr_handle) ||
 420              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 421             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 422                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 423                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 424                 if (intr_vector > bp->rx_cp_nr_rings) {
 425                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 426                                         bp->rx_cp_nr_rings);
 427                         return -ENOTSUP;
 428                 }
 429                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 430                 if (rc)
 431                         return rc;
 432         }
 433
 434         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 435                 intr_handle->intr_vec =
 436                         rte_zmalloc("intr_vec",
 437                                     bp->eth_dev->data->nb_rx_queues *
 438                                     sizeof(int), 0);
 439                 if (intr_handle->intr_vec == NULL) {
 440                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 441                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 442                         rc = -ENOMEM;
 443                         goto err_disable;
 444                 }
 445                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 446                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 447                          intr_handle->intr_vec, intr_handle->nb_efd,
 448                         intr_handle->max_intr);
 449                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 450                      queue_id++) {
 451                         intr_handle->intr_vec[queue_id] =
 452                                                         vec + BNXT_RX_VEC_START;
 453                         if (vec < base + intr_handle->nb_efd - 1)
 454                                 vec++;
 455                 }
 456         }
 457
 458         /* enable uio/vfio intr/eventfd mapping */
 459         rc = rte_intr_enable(intr_handle);
 460         if (rc)
 461                 goto err_free;
 462
 463         rc = bnxt_get_hwrm_link_config(bp, &new);
 464         if (rc) {
 465                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 466                 goto err_free;
 467         }
 468
 469         if (!bp->link_info.link_up) {
 470                 rc = bnxt_set_hwrm_link_config(bp, true);
 471                 if (rc) {
 472                         PMD_DRV_LOG(ERR,
 473                                 "HWRM link config failure rc: %x\n", rc);
 474                         goto err_free;
 475                 }
 476         }
 477         bnxt_print_link_info(bp->eth_dev);
 478
 479         return 0;
 480
 481 err_free:
 482         rte_free(intr_handle->intr_vec);
 483 err_disable:
 484         rte_intr_efd_disable(intr_handle);
 485 err_out:
 486         /* Some of the error status returned by FW may not be from errno.h */
 487         if (rc > 0)
 488                 rc = -EIO;
 489
 490         return rc;
 491 }
 492
 493 static int bnxt_shutdown_nic(struct bnxt *bp)
 494 {
 495         bnxt_free_all_hwrm_resources(bp);
 496         bnxt_free_all_filters(bp);
 497         bnxt_free_all_vnics(bp);
 498         return 0;
 499 }
 500
 501 static int bnxt_init_nic(struct bnxt *bp)
 502 {
 503         int rc;
 504
 505         if (BNXT_HAS_RING_GRPS(bp)) {
 506                 rc = bnxt_init_ring_grps(bp);
 507                 if (rc)
 508                         return rc;
 509         }
 510
 511         bnxt_init_vnics(bp);
 512         bnxt_init_filters(bp);
 513
 514         return 0;
 515 }
 516
 517 /*
 518  * Device configuration and status function
 519  */
 520
 521 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 522                                 struct rte_eth_dev_info *dev_info)
 523 {
 524         struct bnxt *bp = eth_dev->data->dev_private;
 525         uint16_t max_vnics, i, j, vpool, vrxq;
 526         unsigned int max_rx_rings;
 527         int rc;
 528
 529         rc = is_bnxt_in_error(bp);
 530         if (rc)
 531                 return rc;
 532
 533         /* MAC Specifics */
 534         dev_info->max_mac_addrs = bp->max_l2_ctx;
 535         dev_info->max_hash_mac_addrs = 0;
 536
 537         /* PF/VF specifics */
 538         if (BNXT_PF(bp))
 539                 dev_info->max_vfs = bp->pdev->max_vfs;
 540         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 541         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 542         dev_info->max_rx_queues = max_rx_rings;
 543         dev_info->max_tx_queues = max_rx_rings;
 544         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 545         dev_info->hash_key_size = 40;
 546         max_vnics = bp->max_vnics;
 547
 548         /* Fast path specifics */
 549         dev_info->min_rx_bufsize = 1;
 550         dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
 551                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
 552
 553         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 554         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 555                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 556         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 557         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 558
 559         /* *INDENT-OFF* */
 560         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 561                 .rx_thresh = {
 562                         .pthresh = 8,
 563                         .hthresh = 8,
 564                         .wthresh = 0,
 565                 },
 566                 .rx_free_thresh = 32,
 567                 /* If no descriptors available, pkts are dropped by default */
 568                 .rx_drop_en = 1,
 569         };
 570
 571         dev_info->default_txconf = (struct rte_eth_txconf) {
 572                 .tx_thresh = {
 573                         .pthresh = 32,
 574                         .hthresh = 0,
 575                         .wthresh = 0,
 576                 },
 577                 .tx_free_thresh = 32,
 578                 .tx_rs_thresh = 32,
 579         };
 580         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 581
 582         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 583         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 584         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 585         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 586         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 587
 588         /* *INDENT-ON* */
 589
 590         /*
 591          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 592          *       need further investigation.
 593          */
 594
 595         /* VMDq resources */
 596         vpool = 64; /* ETH_64_POOLS */
 597         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 598         for (i = 0; i < 4; vpool >>= 1, i++) {
 599                 if (max_vnics > vpool) {
 600                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 601                                 if (dev_info->max_rx_queues > vrxq) {
 602                                         if (vpool > vrxq)
 603                                                 vpool = vrxq;
 604                                         goto found;
 605                                 }
 606                         }
 607                         /* Not enough resources to support VMDq */
 608                         break;
 609                 }
 610         }
 611         /* Not enough resources to support VMDq */
 612         vpool = 0;
 613         vrxq = 0;
 614 found:
 615         dev_info->max_vmdq_pools = vpool;
 616         dev_info->vmdq_queue_num = vrxq;
 617
 618         dev_info->vmdq_pool_base = 0;
 619         dev_info->vmdq_queue_base = 0;
 620
 621         return 0;
 622 }
 623
 624 /* Configure the device based on the configuration provided */
 625 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 626 {
 627         struct bnxt *bp = eth_dev->data->dev_private;
 628         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 629         int rc;
 630
 631         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 632         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 633         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 634         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 635
 636         rc = is_bnxt_in_error(bp);
 637         if (rc)
 638                 return rc;
 639
 640         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 641                 rc = bnxt_hwrm_check_vf_rings(bp);
 642                 if (rc) {
 643                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 644                         return -ENOSPC;
 645                 }
 646
 647                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 648                 if (rc) {
 649                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 650                         return -ENOSPC;
 651                 }
 652         } else {
 653                 /* legacy driver needs to get updated values */
 654                 rc = bnxt_hwrm_func_qcaps(bp);
 655                 if (rc) {
 656                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 657                         return rc;
 658                 }
 659         }
 660
 661         /* Inherit new configurations */
 662         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 663             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 664             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 665                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 666             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 667             bp->max_stat_ctx)
 668                 goto resource_error;
 669
 670         if (BNXT_HAS_RING_GRPS(bp) &&
 671             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 672                 goto resource_error;
 673
 674         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 675             bp->max_vnics < eth_dev->data->nb_rx_queues)
 676                 goto resource_error;
 677
 678         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 679         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 680
 681         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 682                 eth_dev->data->mtu =
 683                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 684                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 685                         BNXT_NUM_VLANS;
 686                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 687         }
 688         return 0;
 689
 690 resource_error:
 691         PMD_DRV_LOG(ERR,
 692                     "Insufficient resources to support requested config\n");
 693         PMD_DRV_LOG(ERR,
 694                     "Num Queues Requested: Tx %d, Rx %d\n",
 695                     eth_dev->data->nb_tx_queues,
 696                     eth_dev->data->nb_rx_queues);
 697         PMD_DRV_LOG(ERR,
 698                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 699                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 700                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 701         return -ENOSPC;
 702 }
 703
 704 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 705 {
 706         struct rte_eth_link *link = &eth_dev->data->dev_link;
 707
 708         if (link->link_status)
 709                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 710                         eth_dev->data->port_id,
 711                         (uint32_t)link->link_speed,
 712                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 713                         ("full-duplex") : ("half-duplex\n"));
 714         else
 715                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 716                         eth_dev->data->port_id);
 717 }
 718
 719 /*
 720  * Determine whether the current configuration requires support for scattered
 721  * receive; return 1 if scattered receive is required and 0 if not.
 722  */
 723 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 724 {
 725         uint16_t buf_size;
 726         int i;
 727
 728         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 729                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 730
 731                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 732                                       RTE_PKTMBUF_HEADROOM);
 733                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 734                         return 1;
 735         }
 736         return 0;
 737 }
 738
 739 static eth_rx_burst_t
 740 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 741 {
 742 #ifdef RTE_ARCH_X86
 743         /*
 744          * Vector mode receive can be enabled only if scatter rx is not
 745          * in use and rx offloads are limited to VLAN stripping and
 746          * CRC stripping.
 747          */
 748         if (!eth_dev->data->scattered_rx &&
 749             !(eth_dev->data->dev_conf.rxmode.offloads &
 750               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 751                 DEV_RX_OFFLOAD_KEEP_CRC |
 752                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 753                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 754                 DEV_RX_OFFLOAD_UDP_CKSUM |
 755                 DEV_RX_OFFLOAD_TCP_CKSUM |
 756                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 757                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 758                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 759                             eth_dev->data->port_id);
 760                 return bnxt_recv_pkts_vec;
 761         }
 762         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 763                     eth_dev->data->port_id);
 764         PMD_DRV_LOG(INFO,
 765                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 766                     eth_dev->data->port_id,
 767                     eth_dev->data->scattered_rx,
 768                     eth_dev->data->dev_conf.rxmode.offloads);
 769 #endif
 770         return bnxt_recv_pkts;
 771 }
 772
 773 static eth_tx_burst_t
 774 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 775 {
 776 #ifdef RTE_ARCH_X86
 777         /*
 778          * Vector mode transmit can be enabled only if not using scatter rx
 779          * or tx offloads.
 780          */
 781         if (!eth_dev->data->scattered_rx &&
 782             !eth_dev->data->dev_conf.txmode.offloads) {
 783                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 784                             eth_dev->data->port_id);
 785                 return bnxt_xmit_pkts_vec;
 786         }
 787         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 788                     eth_dev->data->port_id);
 789         PMD_DRV_LOG(INFO,
 790                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 791                     eth_dev->data->port_id,
 792                     eth_dev->data->scattered_rx,
 793                     eth_dev->data->dev_conf.txmode.offloads);
 794 #endif
 795         return bnxt_xmit_pkts;
 796 }
 797
 798 static int bnxt_handle_if_change_status(struct bnxt *bp)
 799 {
 800         int rc;
 801
 802         /* Since fw has undergone a reset and lost all contexts,
 803          * set fatal flag to not issue hwrm during cleanup
 804          */
 805         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 806         bnxt_uninit_resources(bp, true);
 807
 808         /* clear fatal flag so that re-init happens */
 809         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 810         rc = bnxt_init_resources(bp, true);
 811
 812         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 813
 814         return rc;
 815 }
 816
 817 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 818 {
 819         struct bnxt *bp = eth_dev->data->dev_private;
 820         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 821         int vlan_mask = 0;
 822         int rc;
 823
 824         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 825                 PMD_DRV_LOG(ERR,
 826                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 827                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 828         }
 829
 830         rc = bnxt_hwrm_if_change(bp, 1);
 831         if (!rc) {
 832                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 833                         rc = bnxt_handle_if_change_status(bp);
 834                         if (rc)
 835                                 return rc;
 836                 }
 837         }
 838
 839         rc = bnxt_init_chip(bp);
 840         if (rc)
 841                 goto error;
 842
 843         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 844
 845         bnxt_link_update_op(eth_dev, 1);
 846
 847         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 848                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 849         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 850                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 851         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 852         if (rc)
 853                 goto error;
 854
 855         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 856         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 857
 858         bnxt_enable_int(bp);
 859         bp->flags |= BNXT_FLAG_INIT_DONE;
 860         eth_dev->data->dev_started = 1;
 861         bp->dev_stopped = 0;
 862         bnxt_schedule_fw_health_check(bp);
 863         return 0;
 864
 865 error:
 866         bnxt_hwrm_if_change(bp, 0);
 867         bnxt_shutdown_nic(bp);
 868         bnxt_free_tx_mbufs(bp);
 869         bnxt_free_rx_mbufs(bp);
 870         return rc;
 871 }
 872
 873 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 874 {
 875         struct bnxt *bp = eth_dev->data->dev_private;
 876         int rc = 0;
 877
 878         if (!bp->link_info.link_up)
 879                 rc = bnxt_set_hwrm_link_config(bp, true);
 880         if (!rc)
 881                 eth_dev->data->dev_link.link_status = 1;
 882
 883         bnxt_print_link_info(eth_dev);
 884         return 0;
 885 }
 886
 887 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 888 {
 889         struct bnxt *bp = eth_dev->data->dev_private;
 890
 891         eth_dev->data->dev_link.link_status = 0;
 892         bnxt_set_hwrm_link_config(bp, false);
 893         bp->link_info.link_up = 0;
 894
 895         return 0;
 896 }
 897
 898 /* Unload the driver, release resources */
 899 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 900 {
 901         struct bnxt *bp = eth_dev->data->dev_private;
 902         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 903         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 904
 905         eth_dev->data->dev_started = 0;
 906         /* Prevent crashes when queues are still in use */
 907         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 908         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 909
 910         bnxt_disable_int(bp);
 911
 912         /* disable uio/vfio intr/eventfd mapping */
 913         rte_intr_disable(intr_handle);
 914
 915         bnxt_cancel_fw_health_check(bp);
 916
 917         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 918         if (bp->eth_dev->data->dev_started) {
 919                 /* TBD: STOP HW queues DMA */
 920                 eth_dev->data->dev_link.link_status = 0;
 921         }
 922         bnxt_set_hwrm_link_config(bp, false);
 923
 924         /* Clean queue intr-vector mapping */
 925         rte_intr_efd_disable(intr_handle);
 926         if (intr_handle->intr_vec != NULL) {
 927                 rte_free(intr_handle->intr_vec);
 928                 intr_handle->intr_vec = NULL;
 929         }
 930
 931         bnxt_hwrm_port_clr_stats(bp);
 932         bnxt_free_tx_mbufs(bp);
 933         bnxt_free_rx_mbufs(bp);
 934         bnxt_shutdown_nic(bp);
 935         bnxt_hwrm_if_change(bp, 0);
 936         bp->dev_stopped = 1;
 937 }
 938
 939 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 940 {
 941         struct bnxt *bp = eth_dev->data->dev_private;
 942
 943         if (bp->dev_stopped == 0)
 944                 bnxt_dev_stop_op(eth_dev);
 945
 946         if (eth_dev->data->mac_addrs != NULL) {
 947                 rte_free(eth_dev->data->mac_addrs);
 948                 eth_dev->data->mac_addrs = NULL;
 949         }
 950         if (bp->grp_info != NULL) {
 951                 rte_free(bp->grp_info);
 952                 bp->grp_info = NULL;
 953         }
 954
 955         bnxt_dev_uninit(eth_dev);
 956 }
 957
 958 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 959                                     uint32_t index)
 960 {
 961         struct bnxt *bp = eth_dev->data->dev_private;
 962         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 963         struct bnxt_vnic_info *vnic;
 964         struct bnxt_filter_info *filter, *temp_filter;
 965         uint32_t i;
 966
 967         if (is_bnxt_in_error(bp))
 968                 return;
 969
 970         /*
 971          * Loop through all VNICs from the specified filter flow pools to
 972          * remove the corresponding MAC addr filter
 973          */
 974         for (i = 0; i < bp->nr_vnics; i++) {
 975                 if (!(pool_mask & (1ULL << i)))
 976                         continue;
 977
 978                 vnic = &bp->vnic_info[i];
 979                 filter = STAILQ_FIRST(&vnic->filter);
 980                 while (filter) {
 981                         temp_filter = STAILQ_NEXT(filter, next);
 982                         if (filter->mac_index == index) {
 983                                 STAILQ_REMOVE(&vnic->filter, filter,
 984                                                 bnxt_filter_info, next);
 985                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 986                                 filter->mac_index = INVALID_MAC_INDEX;
 987                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 988                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 989                                                    filter, next);
 990                         }
 991                         filter = temp_filter;
 992                 }
 993         }
 994 }
 995
 996 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 997                                 struct rte_ether_addr *mac_addr,
 998                                 uint32_t index, uint32_t pool)
 999 {
1000         struct bnxt *bp = eth_dev->data->dev_private;
1001         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1002         struct bnxt_filter_info *filter;
1003         int rc = 0;
1004
1005         rc = is_bnxt_in_error(bp);
1006         if (rc)
1007                 return rc;
1008
1009         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1010                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1011                 return -ENOTSUP;
1012         }
1013
1014         if (!vnic) {
1015                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1016                 return -EINVAL;
1017         }
1018         /* Attach requested MAC address to the new l2_filter */
1019         STAILQ_FOREACH(filter, &vnic->filter, next) {
1020                 if (filter->mac_index == index) {
1021                         PMD_DRV_LOG(ERR,
1022                                 "MAC addr already existed for pool %d\n", pool);
1023                         return 0;
1024                 }
1025         }
1026         filter = bnxt_alloc_filter(bp);
1027         if (!filter) {
1028                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1029                 return -ENODEV;
1030         }
1031
1032         filter->mac_index = index;
1033         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1034
1035         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1036         if (!rc) {
1037                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1038         } else {
1039                 filter->mac_index = INVALID_MAC_INDEX;
1040                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1041                 bnxt_free_filter(bp, filter);
1042         }
1043
1044         return rc;
1045 }
1046
1047 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1048 {
1049         int rc = 0;
1050         struct bnxt *bp = eth_dev->data->dev_private;
1051         struct rte_eth_link new;
1052         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1053
1054         rc = is_bnxt_in_error(bp);
1055         if (rc)
1056                 return rc;
1057
1058         memset(&new, 0, sizeof(new));
1059         do {
1060                 /* Retrieve link info from hardware */
1061                 rc = bnxt_get_hwrm_link_config(bp, &new);
1062                 if (rc) {
1063                         new.link_speed = ETH_LINK_SPEED_100M;
1064                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1065                         PMD_DRV_LOG(ERR,
1066                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1067                         goto out;
1068                 }
1069
1070                 if (!wait_to_complete || new.link_status)
1071                         break;
1072
1073                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1074         } while (cnt--);
1075
1076 out:
1077         /* Timed out or success */
1078         if (new.link_status != eth_dev->data->dev_link.link_status ||
1079         new.link_speed != eth_dev->data->dev_link.link_speed) {
1080                 memcpy(&eth_dev->data->dev_link, &new,
1081                         sizeof(struct rte_eth_link));
1082
1083                 _rte_eth_dev_callback_process(eth_dev,
1084                                               RTE_ETH_EVENT_INTR_LSC,
1085                                               NULL);
1086
1087                 bnxt_print_link_info(eth_dev);
1088         }
1089
1090         return rc;
1091 }
1092
1093 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1094 {
1095         struct bnxt *bp = eth_dev->data->dev_private;
1096         struct bnxt_vnic_info *vnic;
1097         uint32_t old_flags;
1098         int rc;
1099
1100         rc = is_bnxt_in_error(bp);
1101         if (rc)
1102                 return rc;
1103
1104         if (bp->vnic_info == NULL)
1105                 return 0;
1106
1107         vnic = &bp->vnic_info[0];
1108
1109         old_flags = vnic->flags;
1110         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1111         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1112         if (rc != 0)
1113                 vnic->flags = old_flags;
1114
1115         return rc;
1116 }
1117
1118 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1119 {
1120         struct bnxt *bp = eth_dev->data->dev_private;
1121         struct bnxt_vnic_info *vnic;
1122         uint32_t old_flags;
1123         int rc;
1124
1125         rc = is_bnxt_in_error(bp);
1126         if (rc)
1127                 return rc;
1128
1129         if (bp->vnic_info == NULL)
1130                 return 0;
1131
1132         vnic = &bp->vnic_info[0];
1133
1134         old_flags = vnic->flags;
1135         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1136         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1137         if (rc != 0)
1138                 vnic->flags = old_flags;
1139
1140         return rc;
1141 }
1142
1143 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1144 {
1145         struct bnxt *bp = eth_dev->data->dev_private;
1146         struct bnxt_vnic_info *vnic;
1147         uint32_t old_flags;
1148         int rc;
1149
1150         rc = is_bnxt_in_error(bp);
1151         if (rc)
1152                 return rc;
1153
1154         if (bp->vnic_info == NULL)
1155                 return 0;
1156
1157         vnic = &bp->vnic_info[0];
1158
1159         old_flags = vnic->flags;
1160         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1161         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1162         if (rc != 0)
1163                 vnic->flags = old_flags;
1164
1165         return rc;
1166 }
1167
1168 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1169 {
1170         struct bnxt *bp = eth_dev->data->dev_private;
1171         struct bnxt_vnic_info *vnic;
1172         uint32_t old_flags;
1173         int rc;
1174
1175         rc = is_bnxt_in_error(bp);
1176         if (rc)
1177                 return rc;
1178
1179         if (bp->vnic_info == NULL)
1180                 return 0;
1181
1182         vnic = &bp->vnic_info[0];
1183
1184         old_flags = vnic->flags;
1185         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1186         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1187         if (rc != 0)
1188                 vnic->flags = old_flags;
1189
1190         return rc;
1191 }
1192
1193 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1194 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1195 {
1196         if (qid >= bp->rx_nr_rings)
1197                 return NULL;
1198
1199         return bp->eth_dev->data->rx_queues[qid];
1200 }
1201
1202 /* Return rxq corresponding to a given rss table ring/group ID. */
1203 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1204 {
1205         struct bnxt_rx_queue *rxq;
1206         unsigned int i;
1207
1208         if (!BNXT_HAS_RING_GRPS(bp)) {
1209                 for (i = 0; i < bp->rx_nr_rings; i++) {
1210                         rxq = bp->eth_dev->data->rx_queues[i];
1211                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1212                                 return rxq->index;
1213                 }
1214         } else {
1215                 for (i = 0; i < bp->rx_nr_rings; i++) {
1216                         if (bp->grp_info[i].fw_grp_id == fwr)
1217                                 return i;
1218                 }
1219         }
1220
1221         return INVALID_HW_RING_ID;
1222 }
1223
1224 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1225                             struct rte_eth_rss_reta_entry64 *reta_conf,
1226                             uint16_t reta_size)
1227 {
1228         struct bnxt *bp = eth_dev->data->dev_private;
1229         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1230         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1231         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1232         uint16_t idx, sft;
1233         int i, rc;
1234
1235         rc = is_bnxt_in_error(bp);
1236         if (rc)
1237                 return rc;
1238
1239         if (!vnic->rss_table)
1240                 return -EINVAL;
1241
1242         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1243                 return -EINVAL;
1244
1245         if (reta_size != tbl_size) {
1246                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1247                         "(%d) must equal the size supported by the hardware "
1248                         "(%d)\n", reta_size, tbl_size);
1249                 return -EINVAL;
1250         }
1251
1252         for (i = 0; i < reta_size; i++) {
1253                 struct bnxt_rx_queue *rxq;
1254
1255                 idx = i / RTE_RETA_GROUP_SIZE;
1256                 sft = i % RTE_RETA_GROUP_SIZE;
1257
1258                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1259                         continue;
1260
1261                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1262                 if (!rxq) {
1263                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1264                         return -EINVAL;
1265                 }
1266
1267                 if (BNXT_CHIP_THOR(bp)) {
1268                         vnic->rss_table[i * 2] =
1269                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1270                         vnic->rss_table[i * 2 + 1] =
1271                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1272                 } else {
1273                         vnic->rss_table[i] =
1274                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1275                 }
1276
1277                 vnic->rss_table[i] =
1278                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1279         }
1280
1281         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1282         return 0;
1283 }
1284
1285 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1286                               struct rte_eth_rss_reta_entry64 *reta_conf,
1287                               uint16_t reta_size)
1288 {
1289         struct bnxt *bp = eth_dev->data->dev_private;
1290         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1291         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1292         uint16_t idx, sft, i;
1293         int rc;
1294
1295         rc = is_bnxt_in_error(bp);
1296         if (rc)
1297                 return rc;
1298
1299         /* Retrieve from the default VNIC */
1300         if (!vnic)
1301                 return -EINVAL;
1302         if (!vnic->rss_table)
1303                 return -EINVAL;
1304
1305         if (reta_size != tbl_size) {
1306                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1307                         "(%d) must equal the size supported by the hardware "
1308                         "(%d)\n", reta_size, tbl_size);
1309                 return -EINVAL;
1310         }
1311
1312         for (idx = 0, i = 0; i < reta_size; i++) {
1313                 idx = i / RTE_RETA_GROUP_SIZE;
1314                 sft = i % RTE_RETA_GROUP_SIZE;
1315
1316                 if (reta_conf[idx].mask & (1ULL << sft)) {
1317                         uint16_t qid;
1318
1319                         if (BNXT_CHIP_THOR(bp))
1320                                 qid = bnxt_rss_to_qid(bp,
1321                                                       vnic->rss_table[i * 2]);
1322                         else
1323                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1324
1325                         if (qid == INVALID_HW_RING_ID) {
1326                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1327                                 return -EINVAL;
1328                         }
1329                         reta_conf[idx].reta[sft] = qid;
1330                 }
1331         }
1332
1333         return 0;
1334 }
1335
1336 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1337                                    struct rte_eth_rss_conf *rss_conf)
1338 {
1339         struct bnxt *bp = eth_dev->data->dev_private;
1340         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1341         struct bnxt_vnic_info *vnic;
1342         uint16_t hash_type = 0;
1343         unsigned int i;
1344         int rc;
1345
1346         rc = is_bnxt_in_error(bp);
1347         if (rc)
1348                 return rc;
1349
1350         /*
1351          * If RSS enablement were different than dev_configure,
1352          * then return -EINVAL
1353          */
1354         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1355                 if (!rss_conf->rss_hf)
1356                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1357         } else {
1358                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1359                         return -EINVAL;
1360         }
1361
1362         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1363         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1364
1365         if (rss_conf->rss_hf & ETH_RSS_IPV4)
1366                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1367         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1368                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1369         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1370                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1371         if (rss_conf->rss_hf & ETH_RSS_IPV6)
1372                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1373         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1374                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1375         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1376                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1377
1378         /* Update the RSS VNIC(s) */
1379         for (i = 0; i < bp->nr_vnics; i++) {
1380                 vnic = &bp->vnic_info[i];
1381                 vnic->hash_type = hash_type;
1382
1383                 /*
1384                  * Use the supplied key if the key length is
1385                  * acceptable and the rss_key is not NULL
1386                  */
1387                 if (rss_conf->rss_key &&
1388                     rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1389                         memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1390                                rss_conf->rss_key_len);
1391
1392                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1393         }
1394         return 0;
1395 }
1396
1397 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1398                                      struct rte_eth_rss_conf *rss_conf)
1399 {
1400         struct bnxt *bp = eth_dev->data->dev_private;
1401         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1402         int len, rc;
1403         uint32_t hash_types;
1404
1405         rc = is_bnxt_in_error(bp);
1406         if (rc)
1407                 return rc;
1408
1409         /* RSS configuration is the same for all VNICs */
1410         if (vnic && vnic->rss_hash_key) {
1411                 if (rss_conf->rss_key) {
1412                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1413                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1414                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1415                 }
1416
1417                 hash_types = vnic->hash_type;
1418                 rss_conf->rss_hf = 0;
1419                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1420                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1421                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1422                 }
1423                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1424                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1425                         hash_types &=
1426                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1427                 }
1428                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1429                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1430                         hash_types &=
1431                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1432                 }
1433                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1434                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1435                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1436                 }
1437                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1438                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1439                         hash_types &=
1440                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1441                 }
1442                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1443                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1444                         hash_types &=
1445                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1446                 }
1447                 if (hash_types) {
1448                         PMD_DRV_LOG(ERR,
1449                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1450                                 vnic->hash_type);
1451                         return -ENOTSUP;
1452                 }
1453         } else {
1454                 rss_conf->rss_hf = 0;
1455         }
1456         return 0;
1457 }
1458
1459 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1460                                struct rte_eth_fc_conf *fc_conf)
1461 {
1462         struct bnxt *bp = dev->data->dev_private;
1463         struct rte_eth_link link_info;
1464         int rc;
1465
1466         rc = is_bnxt_in_error(bp);
1467         if (rc)
1468                 return rc;
1469
1470         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1471         if (rc)
1472                 return rc;
1473
1474         memset(fc_conf, 0, sizeof(*fc_conf));
1475         if (bp->link_info.auto_pause)
1476                 fc_conf->autoneg = 1;
1477         switch (bp->link_info.pause) {
1478         case 0:
1479                 fc_conf->mode = RTE_FC_NONE;
1480                 break;
1481         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1482                 fc_conf->mode = RTE_FC_TX_PAUSE;
1483                 break;
1484         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1485                 fc_conf->mode = RTE_FC_RX_PAUSE;
1486                 break;
1487         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1488                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1489                 fc_conf->mode = RTE_FC_FULL;
1490                 break;
1491         }
1492         return 0;
1493 }
1494
1495 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1496                                struct rte_eth_fc_conf *fc_conf)
1497 {
1498         struct bnxt *bp = dev->data->dev_private;
1499         int rc;
1500
1501         rc = is_bnxt_in_error(bp);
1502         if (rc)
1503                 return rc;
1504
1505         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1506                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1507                 return -ENOTSUP;
1508         }
1509
1510         switch (fc_conf->mode) {
1511         case RTE_FC_NONE:
1512                 bp->link_info.auto_pause = 0;
1513                 bp->link_info.force_pause = 0;
1514                 break;
1515         case RTE_FC_RX_PAUSE:
1516                 if (fc_conf->autoneg) {
1517                         bp->link_info.auto_pause =
1518                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1519                         bp->link_info.force_pause = 0;
1520                 } else {
1521                         bp->link_info.auto_pause = 0;
1522                         bp->link_info.force_pause =
1523                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1524                 }
1525                 break;
1526         case RTE_FC_TX_PAUSE:
1527                 if (fc_conf->autoneg) {
1528                         bp->link_info.auto_pause =
1529                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1530                         bp->link_info.force_pause = 0;
1531                 } else {
1532                         bp->link_info.auto_pause = 0;
1533                         bp->link_info.force_pause =
1534                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1535                 }
1536                 break;
1537         case RTE_FC_FULL:
1538                 if (fc_conf->autoneg) {
1539                         bp->link_info.auto_pause =
1540                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1541                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1542                         bp->link_info.force_pause = 0;
1543                 } else {
1544                         bp->link_info.auto_pause = 0;
1545                         bp->link_info.force_pause =
1546                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1547                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1548                 }
1549                 break;
1550         }
1551         return bnxt_set_hwrm_link_config(bp, true);
1552 }
1553
1554 /* Add UDP tunneling port */
1555 static int
1556 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1557                          struct rte_eth_udp_tunnel *udp_tunnel)
1558 {
1559         struct bnxt *bp = eth_dev->data->dev_private;
1560         uint16_t tunnel_type = 0;
1561         int rc = 0;
1562
1563         rc = is_bnxt_in_error(bp);
1564         if (rc)
1565                 return rc;
1566
1567         switch (udp_tunnel->prot_type) {
1568         case RTE_TUNNEL_TYPE_VXLAN:
1569                 if (bp->vxlan_port_cnt) {
1570                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1571                                 udp_tunnel->udp_port);
1572                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1573                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1574                                 return -ENOSPC;
1575                         }
1576                         bp->vxlan_port_cnt++;
1577                         return 0;
1578                 }
1579                 tunnel_type =
1580                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1581                 bp->vxlan_port_cnt++;
1582                 break;
1583         case RTE_TUNNEL_TYPE_GENEVE:
1584                 if (bp->geneve_port_cnt) {
1585                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1586                                 udp_tunnel->udp_port);
1587                         if (bp->geneve_port != udp_tunnel->udp_port) {
1588                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1589                                 return -ENOSPC;
1590                         }
1591                         bp->geneve_port_cnt++;
1592                         return 0;
1593                 }
1594                 tunnel_type =
1595                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1596                 bp->geneve_port_cnt++;
1597                 break;
1598         default:
1599                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1600                 return -ENOTSUP;
1601         }
1602         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1603                                              tunnel_type);
1604         return rc;
1605 }
1606
1607 static int
1608 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1609                          struct rte_eth_udp_tunnel *udp_tunnel)
1610 {
1611         struct bnxt *bp = eth_dev->data->dev_private;
1612         uint16_t tunnel_type = 0;
1613         uint16_t port = 0;
1614         int rc = 0;
1615
1616         rc = is_bnxt_in_error(bp);
1617         if (rc)
1618                 return rc;
1619
1620         switch (udp_tunnel->prot_type) {
1621         case RTE_TUNNEL_TYPE_VXLAN:
1622                 if (!bp->vxlan_port_cnt) {
1623                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1624                         return -EINVAL;
1625                 }
1626                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1627                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1628                                 udp_tunnel->udp_port, bp->vxlan_port);
1629                         return -EINVAL;
1630                 }
1631                 if (--bp->vxlan_port_cnt)
1632                         return 0;
1633
1634                 tunnel_type =
1635                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1636                 port = bp->vxlan_fw_dst_port_id;
1637                 break;
1638         case RTE_TUNNEL_TYPE_GENEVE:
1639                 if (!bp->geneve_port_cnt) {
1640                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1641                         return -EINVAL;
1642                 }
1643                 if (bp->geneve_port != udp_tunnel->udp_port) {
1644                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1645                                 udp_tunnel->udp_port, bp->geneve_port);
1646                         return -EINVAL;
1647                 }
1648                 if (--bp->geneve_port_cnt)
1649                         return 0;
1650
1651                 tunnel_type =
1652                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1653                 port = bp->geneve_fw_dst_port_id;
1654                 break;
1655         default:
1656                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1657                 return -ENOTSUP;
1658         }
1659
1660         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1661         if (!rc) {
1662                 if (tunnel_type ==
1663                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1664                         bp->vxlan_port = 0;
1665                 if (tunnel_type ==
1666                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1667                         bp->geneve_port = 0;
1668         }
1669         return rc;
1670 }
1671
1672 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1673 {
1674         struct bnxt_filter_info *filter;
1675         struct bnxt_vnic_info *vnic;
1676         int rc = 0;
1677         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1678
1679         /* if VLAN exists && VLAN matches vlan_id
1680          *      remove the MAC+VLAN filter
1681          *      add a new MAC only filter
1682          * else
1683          *      VLAN filter doesn't exist, just skip and continue
1684          */
1685         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1686         filter = STAILQ_FIRST(&vnic->filter);
1687         while (filter) {
1688                 /* Search for this matching MAC+VLAN filter */
1689                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1690                     !memcmp(filter->l2_addr,
1691                             bp->mac_addr,
1692                             RTE_ETHER_ADDR_LEN)) {
1693                         /* Delete the filter */
1694                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1695                         if (rc)
1696                                 return rc;
1697                         STAILQ_REMOVE(&vnic->filter, filter,
1698                                       bnxt_filter_info, next);
1699                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1700
1701                         PMD_DRV_LOG(INFO,
1702                                     "Del Vlan filter for %d\n",
1703                                     vlan_id);
1704                         return rc;
1705                 }
1706                 filter = STAILQ_NEXT(filter, next);
1707         }
1708         return -ENOENT;
1709 }
1710
1711 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1712 {
1713         struct bnxt_filter_info *filter;
1714         struct bnxt_vnic_info *vnic;
1715         int rc = 0;
1716         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1717                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1718         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1719
1720         /* Implementation notes on the use of VNIC in this command:
1721          *
1722          * By default, these filters belong to default vnic for the function.
1723          * Once these filters are set up, only destination VNIC can be modified.
1724          * If the destination VNIC is not specified in this command,
1725          * then the HWRM shall only create an l2 context id.
1726          */
1727
1728         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1729         filter = STAILQ_FIRST(&vnic->filter);
1730         /* Check if the VLAN has already been added */
1731         while (filter) {
1732                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1733                     !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1734                         return -EEXIST;
1735
1736                 filter = STAILQ_NEXT(filter, next);
1737         }
1738
1739         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1740          * command to create MAC+VLAN filter with the right flags, enables set.
1741          */
1742         filter = bnxt_alloc_filter(bp);
1743         if (!filter) {
1744                 PMD_DRV_LOG(ERR,
1745                             "MAC/VLAN filter alloc failed\n");
1746                 return -ENOMEM;
1747         }
1748         /* MAC + VLAN ID filter */
1749         filter->l2_ivlan = vlan_id;
1750         filter->l2_ivlan_mask = 0x0FFF;
1751         filter->enables |= en;
1752         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1753         if (rc) {
1754                 /* Free the newly allocated filter as we were
1755                  * not able to create the filter in hardware.
1756                  */
1757                 filter->fw_l2_filter_id = UINT64_MAX;
1758                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1759                 return rc;
1760         }
1761
1762         /* Add this new filter to the list */
1763         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1764         PMD_DRV_LOG(INFO,
1765                     "Added Vlan filter for %d\n", vlan_id);
1766         return rc;
1767 }
1768
1769 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1770                 uint16_t vlan_id, int on)
1771 {
1772         struct bnxt *bp = eth_dev->data->dev_private;
1773         int rc;
1774
1775         rc = is_bnxt_in_error(bp);
1776         if (rc)
1777                 return rc;
1778
1779         /* These operations apply to ALL existing MAC/VLAN filters */
1780         if (on)
1781                 return bnxt_add_vlan_filter(bp, vlan_id);
1782         else
1783                 return bnxt_del_vlan_filter(bp, vlan_id);
1784 }
1785
1786 static int
1787 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1788 {
1789         struct bnxt *bp = dev->data->dev_private;
1790         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1791         unsigned int i;
1792         int rc;
1793
1794         rc = is_bnxt_in_error(bp);
1795         if (rc)
1796                 return rc;
1797
1798         if (mask & ETH_VLAN_FILTER_MASK) {
1799                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1800                         /* Remove any VLAN filters programmed */
1801                         for (i = 0; i < 4095; i++)
1802                                 bnxt_del_vlan_filter(bp, i);
1803                 }
1804                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1805                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1806         }
1807
1808         if (mask & ETH_VLAN_STRIP_MASK) {
1809                 /* Enable or disable VLAN stripping */
1810                 for (i = 0; i < bp->nr_vnics; i++) {
1811                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1812                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1813                                 vnic->vlan_strip = true;
1814                         else
1815                                 vnic->vlan_strip = false;
1816                         bnxt_hwrm_vnic_cfg(bp, vnic);
1817                 }
1818                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1819                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1820         }
1821
1822         if (mask & ETH_VLAN_EXTEND_MASK)
1823                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1824
1825         return 0;
1826 }
1827
1828 static int
1829 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1830                         struct rte_ether_addr *addr)
1831 {
1832         struct bnxt *bp = dev->data->dev_private;
1833         /* Default Filter is tied to VNIC 0 */
1834         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1835         struct bnxt_filter_info *filter;
1836         int rc;
1837
1838         rc = is_bnxt_in_error(bp);
1839         if (rc)
1840                 return rc;
1841
1842         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1843                 return -EPERM;
1844
1845         if (rte_is_zero_ether_addr(addr))
1846                 return -EINVAL;
1847
1848         STAILQ_FOREACH(filter, &vnic->filter, next) {
1849                 /* Default Filter is at Index 0 */
1850                 if (filter->mac_index != 0)
1851                         continue;
1852
1853                 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1854                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1855                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1856                 filter->enables |=
1857                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1858                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1859
1860                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1861                 if (rc)
1862                         return rc;
1863
1864                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1865                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1866                 return 0;
1867         }
1868
1869         return 0;
1870 }
1871
1872 static int
1873 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1874                           struct rte_ether_addr *mc_addr_set,
1875                           uint32_t nb_mc_addr)
1876 {
1877         struct bnxt *bp = eth_dev->data->dev_private;
1878         char *mc_addr_list = (char *)mc_addr_set;
1879         struct bnxt_vnic_info *vnic;
1880         uint32_t off = 0, i = 0;
1881         int rc;
1882
1883         rc = is_bnxt_in_error(bp);
1884         if (rc)
1885                 return rc;
1886
1887         vnic = &bp->vnic_info[0];
1888
1889         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1890                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1891                 goto allmulti;
1892         }
1893
1894         /* TODO Check for Duplicate mcast addresses */
1895         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1896         for (i = 0; i < nb_mc_addr; i++) {
1897                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1898                         RTE_ETHER_ADDR_LEN);
1899                 off += RTE_ETHER_ADDR_LEN;
1900         }
1901
1902         vnic->mc_addr_cnt = i;
1903
1904 allmulti:
1905         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1906 }
1907
1908 static int
1909 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1910 {
1911         struct bnxt *bp = dev->data->dev_private;
1912         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1913         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1914         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1915         int ret;
1916
1917         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1918                         fw_major, fw_minor, fw_updt);
1919
1920         ret += 1; /* add the size of '\0' */
1921         if (fw_size < (uint32_t)ret)
1922                 return ret;
1923         else
1924                 return 0;
1925 }
1926
1927 static void
1928 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1929         struct rte_eth_rxq_info *qinfo)
1930 {
1931         struct bnxt_rx_queue *rxq;
1932
1933         rxq = dev->data->rx_queues[queue_id];
1934
1935         qinfo->mp = rxq->mb_pool;
1936         qinfo->scattered_rx = dev->data->scattered_rx;
1937         qinfo->nb_desc = rxq->nb_rx_desc;
1938
1939         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1940         qinfo->conf.rx_drop_en = 0;
1941         qinfo->conf.rx_deferred_start = 0;
1942 }
1943
1944 static void
1945 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1946         struct rte_eth_txq_info *qinfo)
1947 {
1948         struct bnxt_tx_queue *txq;
1949
1950         txq = dev->data->tx_queues[queue_id];
1951
1952         qinfo->nb_desc = txq->nb_tx_desc;
1953
1954         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1955         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1956         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1957
1958         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1959         qinfo->conf.tx_rs_thresh = 0;
1960         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1961 }
1962
1963 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1964 {
1965         struct bnxt *bp = eth_dev->data->dev_private;
1966         struct rte_eth_dev_info dev_info;
1967         uint32_t new_pkt_size;
1968         uint32_t rc = 0;
1969         uint32_t i;
1970
1971         rc = is_bnxt_in_error(bp);
1972         if (rc)
1973                 return rc;
1974
1975         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1976                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1977
1978         rc = bnxt_dev_info_get_op(eth_dev, &dev_info);
1979         if (rc != 0) {
1980                 PMD_DRV_LOG(ERR, "Error during getting ethernet device info\n");
1981                 return rc;
1982         }
1983
1984         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1985                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1986                         RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1987                 return -EINVAL;
1988         }
1989
1990 #ifdef RTE_ARCH_X86
1991         /*
1992          * If vector-mode tx/rx is active, disallow any MTU change that would
1993          * require scattered receive support.
1994          */
1995         if (eth_dev->data->dev_started &&
1996             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1997              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1998             (new_pkt_size >
1999              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2000                 PMD_DRV_LOG(ERR,
2001                             "MTU change would require scattered rx support. ");
2002                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2003                 return -EINVAL;
2004         }
2005 #endif
2006
2007         if (new_mtu > RTE_ETHER_MTU) {
2008                 bp->flags |= BNXT_FLAG_JUMBO;
2009                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2010                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2011         } else {
2012                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2013                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2014                 bp->flags &= ~BNXT_FLAG_JUMBO;
2015         }
2016
2017         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2018
2019         eth_dev->data->mtu = new_mtu;
2020         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
2021
2022         for (i = 0; i < bp->nr_vnics; i++) {
2023                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2024                 uint16_t size = 0;
2025
2026                 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2027                                         RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2028                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2029                 if (rc)
2030                         break;
2031
2032                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2033                 size -= RTE_PKTMBUF_HEADROOM;
2034
2035                 if (size < new_mtu) {
2036                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2037                         if (rc)
2038                                 return rc;
2039                 }
2040         }
2041
2042         return rc;
2043 }
2044
2045 static int
2046 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2047 {
2048         struct bnxt *bp = dev->data->dev_private;
2049         uint16_t vlan = bp->vlan;
2050         int rc;
2051
2052         rc = is_bnxt_in_error(bp);
2053         if (rc)
2054                 return rc;
2055
2056         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2057                 PMD_DRV_LOG(ERR,
2058                         "PVID cannot be modified for this function\n");
2059                 return -ENOTSUP;
2060         }
2061         bp->vlan = on ? pvid : 0;
2062
2063         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2064         if (rc)
2065                 bp->vlan = vlan;
2066         return rc;
2067 }
2068
2069 static int
2070 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2071 {
2072         struct bnxt *bp = dev->data->dev_private;
2073         int rc;
2074
2075         rc = is_bnxt_in_error(bp);
2076         if (rc)
2077                 return rc;
2078
2079         return bnxt_hwrm_port_led_cfg(bp, true);
2080 }
2081
2082 static int
2083 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2084 {
2085         struct bnxt *bp = dev->data->dev_private;
2086         int rc;
2087
2088         rc = is_bnxt_in_error(bp);
2089         if (rc)
2090                 return rc;
2091
2092         return bnxt_hwrm_port_led_cfg(bp, false);
2093 }
2094
2095 static uint32_t
2096 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2097 {
2098         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2099         uint32_t desc = 0, raw_cons = 0, cons;
2100         struct bnxt_cp_ring_info *cpr;
2101         struct bnxt_rx_queue *rxq;
2102         struct rx_pkt_cmpl *rxcmp;
2103         uint16_t cmp_type;
2104         uint8_t cmp = 1;
2105         bool valid;
2106         int rc;
2107
2108         rc = is_bnxt_in_error(bp);
2109         if (rc)
2110                 return rc;
2111
2112         rxq = dev->data->rx_queues[rx_queue_id];
2113         cpr = rxq->cp_ring;
2114         valid = cpr->valid;
2115
2116         while (raw_cons < rxq->nb_rx_desc) {
2117                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2118                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2119
2120                 if (!CMPL_VALID(rxcmp, valid))
2121                         goto nothing_to_do;
2122                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
2123                 cmp_type = CMP_TYPE(rxcmp);
2124                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
2125                         cmp = (rte_le_to_cpu_32(
2126                                         ((struct rx_tpa_end_cmpl *)
2127                                          (rxcmp))->agg_bufs_v1) &
2128                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
2129                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
2130                         desc++;
2131                 } else if (cmp_type == 0x11) {
2132                         desc++;
2133                         cmp = (rxcmp->agg_bufs_v1 &
2134                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
2135                                 RX_PKT_CMPL_AGG_BUFS_SFT;
2136                 } else {
2137                         cmp = 1;
2138                 }
2139 nothing_to_do:
2140                 raw_cons += cmp ? cmp : 2;
2141         }
2142
2143         return desc;
2144 }
2145
2146 static int
2147 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2148 {
2149         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2150         struct bnxt_rx_ring_info *rxr;
2151         struct bnxt_cp_ring_info *cpr;
2152         struct bnxt_sw_rx_bd *rx_buf;
2153         struct rx_pkt_cmpl *rxcmp;
2154         uint32_t cons, cp_cons;
2155         int rc;
2156
2157         if (!rxq)
2158                 return -EINVAL;
2159
2160         rc = is_bnxt_in_error(rxq->bp);
2161         if (rc)
2162                 return rc;
2163
2164         cpr = rxq->cp_ring;
2165         rxr = rxq->rx_ring;
2166
2167         if (offset >= rxq->nb_rx_desc)
2168                 return -EINVAL;
2169
2170         cons = RING_CMP(cpr->cp_ring_struct, offset);
2171         cp_cons = cpr->cp_raw_cons;
2172         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2173
2174         if (cons > cp_cons) {
2175                 if (CMPL_VALID(rxcmp, cpr->valid))
2176                         return RTE_ETH_RX_DESC_DONE;
2177         } else {
2178                 if (CMPL_VALID(rxcmp, !cpr->valid))
2179                         return RTE_ETH_RX_DESC_DONE;
2180         }
2181         rx_buf = &rxr->rx_buf_ring[cons];
2182         if (rx_buf->mbuf == NULL)
2183                 return RTE_ETH_RX_DESC_UNAVAIL;
2184
2185
2186         return RTE_ETH_RX_DESC_AVAIL;
2187 }
2188
2189 static int
2190 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2191 {
2192         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2193         struct bnxt_tx_ring_info *txr;
2194         struct bnxt_cp_ring_info *cpr;
2195         struct bnxt_sw_tx_bd *tx_buf;
2196         struct tx_pkt_cmpl *txcmp;
2197         uint32_t cons, cp_cons;
2198         int rc;
2199
2200         if (!txq)
2201                 return -EINVAL;
2202
2203         rc = is_bnxt_in_error(txq->bp);
2204         if (rc)
2205                 return rc;
2206
2207         cpr = txq->cp_ring;
2208         txr = txq->tx_ring;
2209
2210         if (offset >= txq->nb_tx_desc)
2211                 return -EINVAL;
2212
2213         cons = RING_CMP(cpr->cp_ring_struct, offset);
2214         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2215         cp_cons = cpr->cp_raw_cons;
2216
2217         if (cons > cp_cons) {
2218                 if (CMPL_VALID(txcmp, cpr->valid))
2219                         return RTE_ETH_TX_DESC_UNAVAIL;
2220         } else {
2221                 if (CMPL_VALID(txcmp, !cpr->valid))
2222                         return RTE_ETH_TX_DESC_UNAVAIL;
2223         }
2224         tx_buf = &txr->tx_buf_ring[cons];
2225         if (tx_buf->mbuf == NULL)
2226                 return RTE_ETH_TX_DESC_DONE;
2227
2228         return RTE_ETH_TX_DESC_FULL;
2229 }
2230
2231 static struct bnxt_filter_info *
2232 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2233                                 struct rte_eth_ethertype_filter *efilter,
2234                                 struct bnxt_vnic_info *vnic0,
2235                                 struct bnxt_vnic_info *vnic,
2236                                 int *ret)
2237 {
2238         struct bnxt_filter_info *mfilter = NULL;
2239         int match = 0;
2240         *ret = 0;
2241
2242         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2243                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2244                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2245                         " ethertype filter.", efilter->ether_type);
2246                 *ret = -EINVAL;
2247                 goto exit;
2248         }
2249         if (efilter->queue >= bp->rx_nr_rings) {
2250                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2251                 *ret = -EINVAL;
2252                 goto exit;
2253         }
2254
2255         vnic0 = &bp->vnic_info[0];
2256         vnic = &bp->vnic_info[efilter->queue];
2257         if (vnic == NULL) {
2258                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2259                 *ret = -EINVAL;
2260                 goto exit;
2261         }
2262
2263         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2264                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2265                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2266                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2267                              mfilter->flags ==
2268                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2269                              mfilter->ethertype == efilter->ether_type)) {
2270                                 match = 1;
2271                                 break;
2272                         }
2273                 }
2274         } else {
2275                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2276                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2277                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2278                              mfilter->ethertype == efilter->ether_type &&
2279                              mfilter->flags ==
2280                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2281                                 match = 1;
2282                                 break;
2283                         }
2284         }
2285
2286         if (match)
2287                 *ret = -EEXIST;
2288
2289 exit:
2290         return mfilter;
2291 }
2292
2293 static int
2294 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2295                         enum rte_filter_op filter_op,
2296                         void *arg)
2297 {
2298         struct bnxt *bp = dev->data->dev_private;
2299         struct rte_eth_ethertype_filter *efilter =
2300                         (struct rte_eth_ethertype_filter *)arg;
2301         struct bnxt_filter_info *bfilter, *filter1;
2302         struct bnxt_vnic_info *vnic, *vnic0;
2303         int ret;
2304
2305         if (filter_op == RTE_ETH_FILTER_NOP)
2306                 return 0;
2307
2308         if (arg == NULL) {
2309                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2310                             filter_op);
2311                 return -EINVAL;
2312         }
2313
2314         vnic0 = &bp->vnic_info[0];
2315         vnic = &bp->vnic_info[efilter->queue];
2316
2317         switch (filter_op) {
2318         case RTE_ETH_FILTER_ADD:
2319                 bnxt_match_and_validate_ether_filter(bp, efilter,
2320                                                         vnic0, vnic, &ret);
2321                 if (ret < 0)
2322                         return ret;
2323
2324                 bfilter = bnxt_get_unused_filter(bp);
2325                 if (bfilter == NULL) {
2326                         PMD_DRV_LOG(ERR,
2327                                 "Not enough resources for a new filter.\n");
2328                         return -ENOMEM;
2329                 }
2330                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2331                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2332                        RTE_ETHER_ADDR_LEN);
2333                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2334                        RTE_ETHER_ADDR_LEN);
2335                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2336                 bfilter->ethertype = efilter->ether_type;
2337                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2338
2339                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2340                 if (filter1 == NULL) {
2341                         ret = -EINVAL;
2342                         goto cleanup;
2343                 }
2344                 bfilter->enables |=
2345                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2346                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2347
2348                 bfilter->dst_id = vnic->fw_vnic_id;
2349
2350                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2351                         bfilter->flags =
2352                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2353                 }
2354
2355                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2356                 if (ret)
2357                         goto cleanup;
2358                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2359                 break;
2360         case RTE_ETH_FILTER_DELETE:
2361                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2362                                                         vnic0, vnic, &ret);
2363                 if (ret == -EEXIST) {
2364                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2365
2366                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2367                                       next);
2368                         bnxt_free_filter(bp, filter1);
2369                 } else if (ret == 0) {
2370                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2371                 }
2372                 break;
2373         default:
2374                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2375                 ret = -EINVAL;
2376                 goto error;
2377         }
2378         return ret;
2379 cleanup:
2380         bnxt_free_filter(bp, bfilter);
2381 error:
2382         return ret;
2383 }
2384
2385 static inline int
2386 parse_ntuple_filter(struct bnxt *bp,
2387                     struct rte_eth_ntuple_filter *nfilter,
2388                     struct bnxt_filter_info *bfilter)
2389 {
2390         uint32_t en = 0;
2391
2392         if (nfilter->queue >= bp->rx_nr_rings) {
2393                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2394                 return -EINVAL;
2395         }
2396
2397         switch (nfilter->dst_port_mask) {
2398         case UINT16_MAX:
2399                 bfilter->dst_port_mask = -1;
2400                 bfilter->dst_port = nfilter->dst_port;
2401                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2402                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2403                 break;
2404         default:
2405                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2406                 return -EINVAL;
2407         }
2408
2409         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2410         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2411
2412         switch (nfilter->proto_mask) {
2413         case UINT8_MAX:
2414                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2415                         bfilter->ip_protocol = 17;
2416                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2417                         bfilter->ip_protocol = 6;
2418                 else
2419                         return -EINVAL;
2420                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2421                 break;
2422         default:
2423                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2424                 return -EINVAL;
2425         }
2426
2427         switch (nfilter->dst_ip_mask) {
2428         case UINT32_MAX:
2429                 bfilter->dst_ipaddr_mask[0] = -1;
2430                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2431                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2432                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2433                 break;
2434         default:
2435                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2436                 return -EINVAL;
2437         }
2438
2439         switch (nfilter->src_ip_mask) {
2440         case UINT32_MAX:
2441                 bfilter->src_ipaddr_mask[0] = -1;
2442                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2443                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2444                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2445                 break;
2446         default:
2447                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2448                 return -EINVAL;
2449         }
2450
2451         switch (nfilter->src_port_mask) {
2452         case UINT16_MAX:
2453                 bfilter->src_port_mask = -1;
2454                 bfilter->src_port = nfilter->src_port;
2455                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2456                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2457                 break;
2458         default:
2459                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2460                 return -EINVAL;
2461         }
2462
2463         //TODO Priority
2464         //nfilter->priority = (uint8_t)filter->priority;
2465
2466         bfilter->enables = en;
2467         return 0;
2468 }
2469
2470 static struct bnxt_filter_info*
2471 bnxt_match_ntuple_filter(struct bnxt *bp,
2472                          struct bnxt_filter_info *bfilter,
2473                          struct bnxt_vnic_info **mvnic)
2474 {
2475         struct bnxt_filter_info *mfilter = NULL;
2476         int i;
2477
2478         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2479                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2480                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2481                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2482                             bfilter->src_ipaddr_mask[0] ==
2483                             mfilter->src_ipaddr_mask[0] &&
2484                             bfilter->src_port == mfilter->src_port &&
2485                             bfilter->src_port_mask == mfilter->src_port_mask &&
2486                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2487                             bfilter->dst_ipaddr_mask[0] ==
2488                             mfilter->dst_ipaddr_mask[0] &&
2489                             bfilter->dst_port == mfilter->dst_port &&
2490                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2491                             bfilter->flags == mfilter->flags &&
2492                             bfilter->enables == mfilter->enables) {
2493                                 if (mvnic)
2494                                         *mvnic = vnic;
2495                                 return mfilter;
2496                         }
2497                 }
2498         }
2499         return NULL;
2500 }
2501
2502 static int
2503 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2504                        struct rte_eth_ntuple_filter *nfilter,
2505                        enum rte_filter_op filter_op)
2506 {
2507         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2508         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2509         int ret;
2510
2511         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2512                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2513                 return -EINVAL;
2514         }
2515
2516         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2517                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2518                 return -EINVAL;
2519         }
2520
2521         bfilter = bnxt_get_unused_filter(bp);
2522         if (bfilter == NULL) {
2523                 PMD_DRV_LOG(ERR,
2524                         "Not enough resources for a new filter.\n");
2525                 return -ENOMEM;
2526         }
2527         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2528         if (ret < 0)
2529                 goto free_filter;
2530
2531         vnic = &bp->vnic_info[nfilter->queue];
2532         vnic0 = &bp->vnic_info[0];
2533         filter1 = STAILQ_FIRST(&vnic0->filter);
2534         if (filter1 == NULL) {
2535                 ret = -EINVAL;
2536                 goto free_filter;
2537         }
2538
2539         bfilter->dst_id = vnic->fw_vnic_id;
2540         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2541         bfilter->enables |=
2542                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2543         bfilter->ethertype = 0x800;
2544         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2545
2546         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2547
2548         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2549             bfilter->dst_id == mfilter->dst_id) {
2550                 PMD_DRV_LOG(ERR, "filter exists.\n");
2551                 ret = -EEXIST;
2552                 goto free_filter;
2553         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2554                    bfilter->dst_id != mfilter->dst_id) {
2555                 mfilter->dst_id = vnic->fw_vnic_id;
2556                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2557                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2558                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2559                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2560                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2561                 goto free_filter;
2562         }
2563         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2564                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2565                 ret = -ENOENT;
2566                 goto free_filter;
2567         }
2568
2569         if (filter_op == RTE_ETH_FILTER_ADD) {
2570                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2571                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2572                 if (ret)
2573                         goto free_filter;
2574                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2575         } else {
2576                 if (mfilter == NULL) {
2577                         /* This should not happen. But for Coverity! */
2578                         ret = -ENOENT;
2579                         goto free_filter;
2580                 }
2581                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2582
2583                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2584                 bnxt_free_filter(bp, mfilter);
2585                 mfilter->fw_l2_filter_id = -1;
2586                 bnxt_free_filter(bp, bfilter);
2587                 bfilter->fw_l2_filter_id = -1;
2588         }
2589
2590         return 0;
2591 free_filter:
2592         bfilter->fw_l2_filter_id = -1;
2593         bnxt_free_filter(bp, bfilter);
2594         return ret;
2595 }
2596
2597 static int
2598 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2599                         enum rte_filter_op filter_op,
2600                         void *arg)
2601 {
2602         struct bnxt *bp = dev->data->dev_private;
2603         int ret;
2604
2605         if (filter_op == RTE_ETH_FILTER_NOP)
2606                 return 0;
2607
2608         if (arg == NULL) {
2609                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2610                             filter_op);
2611                 return -EINVAL;
2612         }
2613
2614         switch (filter_op) {
2615         case RTE_ETH_FILTER_ADD:
2616                 ret = bnxt_cfg_ntuple_filter(bp,
2617                         (struct rte_eth_ntuple_filter *)arg,
2618                         filter_op);
2619                 break;
2620         case RTE_ETH_FILTER_DELETE:
2621                 ret = bnxt_cfg_ntuple_filter(bp,
2622                         (struct rte_eth_ntuple_filter *)arg,
2623                         filter_op);
2624                 break;
2625         default:
2626                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2627                 ret = -EINVAL;
2628                 break;
2629         }
2630         return ret;
2631 }
2632
2633 static int
2634 bnxt_parse_fdir_filter(struct bnxt *bp,
2635                        struct rte_eth_fdir_filter *fdir,
2636                        struct bnxt_filter_info *filter)
2637 {
2638         enum rte_fdir_mode fdir_mode =
2639                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2640         struct bnxt_vnic_info *vnic0, *vnic;
2641         struct bnxt_filter_info *filter1;
2642         uint32_t en = 0;
2643         int i;
2644
2645         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2646                 return -EINVAL;
2647
2648         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2649         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2650
2651         switch (fdir->input.flow_type) {
2652         case RTE_ETH_FLOW_IPV4:
2653         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2654                 /* FALLTHROUGH */
2655                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2656                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2657                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2658                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2659                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2660                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2661                 filter->ip_addr_type =
2662                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2663                 filter->src_ipaddr_mask[0] = 0xffffffff;
2664                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2665                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2666                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2667                 filter->ethertype = 0x800;
2668                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2669                 break;
2670         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2671                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2672                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2673                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2674                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2675                 filter->dst_port_mask = 0xffff;
2676                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2677                 filter->src_port_mask = 0xffff;
2678                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2679                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2680                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2681                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2682                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2683                 filter->ip_protocol = 6;
2684                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2685                 filter->ip_addr_type =
2686                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2687                 filter->src_ipaddr_mask[0] = 0xffffffff;
2688                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2689                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2690                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2691                 filter->ethertype = 0x800;
2692                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2693                 break;
2694         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2695                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2696                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2697                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2698                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2699                 filter->dst_port_mask = 0xffff;
2700                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2701                 filter->src_port_mask = 0xffff;
2702                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2703                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2704                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2705                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2706                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2707                 filter->ip_protocol = 17;
2708                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2709                 filter->ip_addr_type =
2710                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2711                 filter->src_ipaddr_mask[0] = 0xffffffff;
2712                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2713                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2714                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2715                 filter->ethertype = 0x800;
2716                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2717                 break;
2718         case RTE_ETH_FLOW_IPV6:
2719         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2720                 /* FALLTHROUGH */
2721                 filter->ip_addr_type =
2722                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2723                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2724                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2725                 rte_memcpy(filter->src_ipaddr,
2726                            fdir->input.flow.ipv6_flow.src_ip, 16);
2727                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2728                 rte_memcpy(filter->dst_ipaddr,
2729                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2730                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2731                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2732                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2733                 memset(filter->src_ipaddr_mask, 0xff, 16);
2734                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2735                 filter->ethertype = 0x86dd;
2736                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2737                 break;
2738         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2739                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2740                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2741                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2742                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2743                 filter->dst_port_mask = 0xffff;
2744                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2745                 filter->src_port_mask = 0xffff;
2746                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2747                 filter->ip_addr_type =
2748                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2749                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2750                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2751                 rte_memcpy(filter->src_ipaddr,
2752                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2753                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2754                 rte_memcpy(filter->dst_ipaddr,
2755                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2756                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2757                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2758                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2759                 memset(filter->src_ipaddr_mask, 0xff, 16);
2760                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2761                 filter->ethertype = 0x86dd;
2762                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2763                 break;
2764         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2765                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2766                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2767                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2768                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2769                 filter->dst_port_mask = 0xffff;
2770                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2771                 filter->src_port_mask = 0xffff;
2772                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2773                 filter->ip_addr_type =
2774                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2775                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2776                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2777                 rte_memcpy(filter->src_ipaddr,
2778                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2779                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2780                 rte_memcpy(filter->dst_ipaddr,
2781                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2782                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2783                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2784                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2785                 memset(filter->src_ipaddr_mask, 0xff, 16);
2786                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2787                 filter->ethertype = 0x86dd;
2788                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2789                 break;
2790         case RTE_ETH_FLOW_L2_PAYLOAD:
2791                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2792                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2793                 break;
2794         case RTE_ETH_FLOW_VXLAN:
2795                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2796                         return -EINVAL;
2797                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2798                 filter->tunnel_type =
2799                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2800                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2801                 break;
2802         case RTE_ETH_FLOW_NVGRE:
2803                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2804                         return -EINVAL;
2805                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2806                 filter->tunnel_type =
2807                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2808                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2809                 break;
2810         case RTE_ETH_FLOW_UNKNOWN:
2811         case RTE_ETH_FLOW_RAW:
2812         case RTE_ETH_FLOW_FRAG_IPV4:
2813         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2814         case RTE_ETH_FLOW_FRAG_IPV6:
2815         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2816         case RTE_ETH_FLOW_IPV6_EX:
2817         case RTE_ETH_FLOW_IPV6_TCP_EX:
2818         case RTE_ETH_FLOW_IPV6_UDP_EX:
2819         case RTE_ETH_FLOW_GENEVE:
2820                 /* FALLTHROUGH */
2821         default:
2822                 return -EINVAL;
2823         }
2824
2825         vnic0 = &bp->vnic_info[0];
2826         vnic = &bp->vnic_info[fdir->action.rx_queue];
2827         if (vnic == NULL) {
2828                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2829                 return -EINVAL;
2830         }
2831
2832
2833         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2834                 rte_memcpy(filter->dst_macaddr,
2835                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2836                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2837         }
2838
2839         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2840                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2841                 filter1 = STAILQ_FIRST(&vnic0->filter);
2842                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2843         } else {
2844                 filter->dst_id = vnic->fw_vnic_id;
2845                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2846                         if (filter->dst_macaddr[i] == 0x00)
2847                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2848                         else
2849                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2850         }
2851
2852         if (filter1 == NULL)
2853                 return -EINVAL;
2854
2855         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2856         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2857
2858         filter->enables = en;
2859
2860         return 0;
2861 }
2862
2863 static struct bnxt_filter_info *
2864 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2865                 struct bnxt_vnic_info **mvnic)
2866 {
2867         struct bnxt_filter_info *mf = NULL;
2868         int i;
2869
2870         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2871                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2872
2873                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2874                         if (mf->filter_type == nf->filter_type &&
2875                             mf->flags == nf->flags &&
2876                             mf->src_port == nf->src_port &&
2877                             mf->src_port_mask == nf->src_port_mask &&
2878                             mf->dst_port == nf->dst_port &&
2879                             mf->dst_port_mask == nf->dst_port_mask &&
2880                             mf->ip_protocol == nf->ip_protocol &&
2881                             mf->ip_addr_type == nf->ip_addr_type &&
2882                             mf->ethertype == nf->ethertype &&
2883                             mf->vni == nf->vni &&
2884                             mf->tunnel_type == nf->tunnel_type &&
2885                             mf->l2_ovlan == nf->l2_ovlan &&
2886                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2887                             mf->l2_ivlan == nf->l2_ivlan &&
2888                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2889                             !memcmp(mf->l2_addr, nf->l2_addr,
2890                                     RTE_ETHER_ADDR_LEN) &&
2891                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2892                                     RTE_ETHER_ADDR_LEN) &&
2893                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2894                                     RTE_ETHER_ADDR_LEN) &&
2895                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2896                                     RTE_ETHER_ADDR_LEN) &&
2897                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2898                                     sizeof(nf->src_ipaddr)) &&
2899                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2900                                     sizeof(nf->src_ipaddr_mask)) &&
2901                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2902                                     sizeof(nf->dst_ipaddr)) &&
2903                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2904                                     sizeof(nf->dst_ipaddr_mask))) {
2905                                 if (mvnic)
2906                                         *mvnic = vnic;
2907                                 return mf;
2908                         }
2909                 }
2910         }
2911         return NULL;
2912 }
2913
2914 static int
2915 bnxt_fdir_filter(struct rte_eth_dev *dev,
2916                  enum rte_filter_op filter_op,
2917                  void *arg)
2918 {
2919         struct bnxt *bp = dev->data->dev_private;
2920         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2921         struct bnxt_filter_info *filter, *match;
2922         struct bnxt_vnic_info *vnic, *mvnic;
2923         int ret = 0, i;
2924
2925         if (filter_op == RTE_ETH_FILTER_NOP)
2926                 return 0;
2927
2928         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2929                 return -EINVAL;
2930
2931         switch (filter_op) {
2932         case RTE_ETH_FILTER_ADD:
2933         case RTE_ETH_FILTER_DELETE:
2934                 /* FALLTHROUGH */
2935                 filter = bnxt_get_unused_filter(bp);
2936                 if (filter == NULL) {
2937                         PMD_DRV_LOG(ERR,
2938                                 "Not enough resources for a new flow.\n");
2939                         return -ENOMEM;
2940                 }
2941
2942                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2943                 if (ret != 0)
2944                         goto free_filter;
2945                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2946
2947                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2948                         vnic = &bp->vnic_info[0];
2949                 else
2950                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2951
2952                 match = bnxt_match_fdir(bp, filter, &mvnic);
2953                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2954                         if (match->dst_id == vnic->fw_vnic_id) {
2955                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2956                                 ret = -EEXIST;
2957                                 goto free_filter;
2958                         } else {
2959                                 match->dst_id = vnic->fw_vnic_id;
2960                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2961                                                                   match->dst_id,
2962                                                                   match);
2963                                 STAILQ_REMOVE(&mvnic->filter, match,
2964                                               bnxt_filter_info, next);
2965                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2966                                 PMD_DRV_LOG(ERR,
2967                                         "Filter with matching pattern exist\n");
2968                                 PMD_DRV_LOG(ERR,
2969                                         "Updated it to new destination q\n");
2970                                 goto free_filter;
2971                         }
2972                 }
2973                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2974                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2975                         ret = -ENOENT;
2976                         goto free_filter;
2977                 }
2978
2979                 if (filter_op == RTE_ETH_FILTER_ADD) {
2980                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2981                                                           filter->dst_id,
2982                                                           filter);
2983                         if (ret)
2984                                 goto free_filter;
2985                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2986                 } else {
2987                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2988                         STAILQ_REMOVE(&vnic->filter, match,
2989                                       bnxt_filter_info, next);
2990                         bnxt_free_filter(bp, match);
2991                         filter->fw_l2_filter_id = -1;
2992                         bnxt_free_filter(bp, filter);
2993                 }
2994                 break;
2995         case RTE_ETH_FILTER_FLUSH:
2996                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2997                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2998
2999                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3000                                 if (filter->filter_type ==
3001                                     HWRM_CFA_NTUPLE_FILTER) {
3002                                         ret =
3003                                         bnxt_hwrm_clear_ntuple_filter(bp,
3004                                                                       filter);
3005                                         STAILQ_REMOVE(&vnic->filter, filter,
3006                                                       bnxt_filter_info, next);
3007                                 }
3008                         }
3009                 }
3010                 return ret;
3011         case RTE_ETH_FILTER_UPDATE:
3012         case RTE_ETH_FILTER_STATS:
3013         case RTE_ETH_FILTER_INFO:
3014                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3015                 break;
3016         default:
3017                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3018                 ret = -EINVAL;
3019                 break;
3020         }
3021         return ret;
3022
3023 free_filter:
3024         filter->fw_l2_filter_id = -1;
3025         bnxt_free_filter(bp, filter);
3026         return ret;
3027 }
3028
3029 static int
3030 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3031                     enum rte_filter_type filter_type,
3032                     enum rte_filter_op filter_op, void *arg)
3033 {
3034         int ret = 0;
3035
3036         ret = is_bnxt_in_error(dev->data->dev_private);
3037         if (ret)
3038                 return ret;
3039
3040         switch (filter_type) {
3041         case RTE_ETH_FILTER_TUNNEL:
3042                 PMD_DRV_LOG(ERR,
3043                         "filter type: %d: To be implemented\n", filter_type);
3044                 break;
3045         case RTE_ETH_FILTER_FDIR:
3046                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3047                 break;
3048         case RTE_ETH_FILTER_NTUPLE:
3049                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3050                 break;
3051         case RTE_ETH_FILTER_ETHERTYPE:
3052                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3053                 break;
3054         case RTE_ETH_FILTER_GENERIC:
3055                 if (filter_op != RTE_ETH_FILTER_GET)
3056                         return -EINVAL;
3057                 *(const void **)arg = &bnxt_flow_ops;
3058                 break;
3059         default:
3060                 PMD_DRV_LOG(ERR,
3061                         "Filter type (%d) not supported", filter_type);
3062                 ret = -EINVAL;
3063                 break;
3064         }
3065         return ret;
3066 }
3067
3068 static const uint32_t *
3069 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3070 {
3071         static const uint32_t ptypes[] = {
3072                 RTE_PTYPE_L2_ETHER_VLAN,
3073                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3074                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3075                 RTE_PTYPE_L4_ICMP,
3076                 RTE_PTYPE_L4_TCP,
3077                 RTE_PTYPE_L4_UDP,
3078                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3079                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3080                 RTE_PTYPE_INNER_L4_ICMP,
3081                 RTE_PTYPE_INNER_L4_TCP,
3082                 RTE_PTYPE_INNER_L4_UDP,
3083                 RTE_PTYPE_UNKNOWN
3084         };
3085
3086         if (!dev->rx_pkt_burst)
3087                 return NULL;
3088
3089         return ptypes;
3090 }
3091
3092 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3093                          int reg_win)
3094 {
3095         uint32_t reg_base = *reg_arr & 0xfffff000;
3096         uint32_t win_off;
3097         int i;
3098
3099         for (i = 0; i < count; i++) {
3100                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3101                         return -ERANGE;
3102         }
3103         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3104         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3105         return 0;
3106 }
3107
3108 static int bnxt_map_ptp_regs(struct bnxt *bp)
3109 {
3110         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3111         uint32_t *reg_arr;
3112         int rc, i;
3113
3114         reg_arr = ptp->rx_regs;
3115         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3116         if (rc)
3117                 return rc;
3118
3119         reg_arr = ptp->tx_regs;
3120         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3121         if (rc)
3122                 return rc;
3123
3124         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3125                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3126
3127         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3128                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3129
3130         return 0;
3131 }
3132
3133 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3134 {
3135         rte_write32(0, (uint8_t *)bp->bar0 +
3136                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3137         rte_write32(0, (uint8_t *)bp->bar0 +
3138                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3139 }
3140
3141 static uint64_t bnxt_cc_read(struct bnxt *bp)
3142 {
3143         uint64_t ns;
3144
3145         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3146                               BNXT_GRCPF_REG_SYNC_TIME));
3147         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3148                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3149         return ns;
3150 }
3151
3152 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3153 {
3154         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3155         uint32_t fifo;
3156
3157         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3158                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3159         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3160                 return -EAGAIN;
3161
3162         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3163                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3164         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3165                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3166         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3167                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3168
3169         return 0;
3170 }
3171
3172 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3173 {
3174         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3175         struct bnxt_pf_info *pf = &bp->pf;
3176         uint16_t port_id;
3177         uint32_t fifo;
3178
3179         if (!ptp)
3180                 return -ENODEV;
3181
3182         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3183                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3184         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3185                 return -EAGAIN;
3186
3187         port_id = pf->port_id;
3188         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3189                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3190
3191         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3192                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3193         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3194 /*              bnxt_clr_rx_ts(bp);       TBD  */
3195                 return -EBUSY;
3196         }
3197
3198         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3199                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3200         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3201                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3202
3203         return 0;
3204 }
3205
3206 static int
3207 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3208 {
3209         uint64_t ns;
3210         struct bnxt *bp = dev->data->dev_private;
3211         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3212
3213         if (!ptp)
3214                 return 0;
3215
3216         ns = rte_timespec_to_ns(ts);
3217         /* Set the timecounters to a new value. */
3218         ptp->tc.nsec = ns;
3219
3220         return 0;
3221 }
3222
3223 static int
3224 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3225 {
3226         uint64_t ns, systime_cycles;
3227         struct bnxt *bp = dev->data->dev_private;
3228         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3229
3230         if (!ptp)
3231                 return 0;
3232
3233         systime_cycles = bnxt_cc_read(bp);
3234         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3235         *ts = rte_ns_to_timespec(ns);
3236
3237         return 0;
3238 }
3239 static int
3240 bnxt_timesync_enable(struct rte_eth_dev *dev)
3241 {
3242         struct bnxt *bp = dev->data->dev_private;
3243         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3244         uint32_t shift = 0;
3245
3246         if (!ptp)
3247                 return 0;
3248
3249         ptp->rx_filter = 1;
3250         ptp->tx_tstamp_en = 1;
3251         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3252
3253         if (!bnxt_hwrm_ptp_cfg(bp))
3254                 bnxt_map_ptp_regs(bp);
3255
3256         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3257         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3258         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3259
3260         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3261         ptp->tc.cc_shift = shift;
3262         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3263
3264         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3265         ptp->rx_tstamp_tc.cc_shift = shift;
3266         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3267
3268         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3269         ptp->tx_tstamp_tc.cc_shift = shift;
3270         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3271
3272         return 0;
3273 }
3274
3275 static int
3276 bnxt_timesync_disable(struct rte_eth_dev *dev)
3277 {
3278         struct bnxt *bp = dev->data->dev_private;
3279         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3280
3281         if (!ptp)
3282                 return 0;
3283
3284         ptp->rx_filter = 0;
3285         ptp->tx_tstamp_en = 0;
3286         ptp->rxctl = 0;
3287
3288         bnxt_hwrm_ptp_cfg(bp);
3289
3290         bnxt_unmap_ptp_regs(bp);
3291
3292         return 0;
3293 }
3294
3295 static int
3296 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3297                                  struct timespec *timestamp,
3298                                  uint32_t flags __rte_unused)
3299 {
3300         struct bnxt *bp = dev->data->dev_private;
3301         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3302         uint64_t rx_tstamp_cycles = 0;
3303         uint64_t ns;
3304
3305         if (!ptp)
3306                 return 0;
3307
3308         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3309         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3310         *timestamp = rte_ns_to_timespec(ns);
3311         return  0;
3312 }
3313
3314 static int
3315 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3316                                  struct timespec *timestamp)
3317 {
3318         struct bnxt *bp = dev->data->dev_private;
3319         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3320         uint64_t tx_tstamp_cycles = 0;
3321         uint64_t ns;
3322
3323         if (!ptp)
3324                 return 0;
3325
3326         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3327         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3328         *timestamp = rte_ns_to_timespec(ns);
3329
3330         return 0;
3331 }
3332
3333 static int
3334 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3335 {
3336         struct bnxt *bp = dev->data->dev_private;
3337         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3338
3339         if (!ptp)
3340                 return 0;
3341
3342         ptp->tc.nsec += delta;
3343
3344         return 0;
3345 }
3346
3347 static int
3348 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3349 {
3350         struct bnxt *bp = dev->data->dev_private;
3351         int rc;
3352         uint32_t dir_entries;
3353         uint32_t entry_length;
3354
3355         rc = is_bnxt_in_error(bp);
3356         if (rc)
3357                 return rc;
3358
3359         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3360                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3361                 bp->pdev->addr.devid, bp->pdev->addr.function);
3362
3363         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3364         if (rc != 0)
3365                 return rc;
3366
3367         return dir_entries * entry_length;
3368 }
3369
3370 static int
3371 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3372                 struct rte_dev_eeprom_info *in_eeprom)
3373 {
3374         struct bnxt *bp = dev->data->dev_private;
3375         uint32_t index;
3376         uint32_t offset;
3377         int rc;
3378
3379         rc = is_bnxt_in_error(bp);
3380         if (rc)
3381                 return rc;
3382
3383         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3384                 "len = %d\n", bp->pdev->addr.domain,
3385                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3386                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3387
3388         if (in_eeprom->offset == 0) /* special offset value to get directory */
3389                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3390                                                 in_eeprom->data);
3391
3392         index = in_eeprom->offset >> 24;
3393         offset = in_eeprom->offset & 0xffffff;
3394
3395         if (index != 0)
3396                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3397                                            in_eeprom->length, in_eeprom->data);
3398
3399         return 0;
3400 }
3401
3402 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3403 {
3404         switch (dir_type) {
3405         case BNX_DIR_TYPE_CHIMP_PATCH:
3406         case BNX_DIR_TYPE_BOOTCODE:
3407         case BNX_DIR_TYPE_BOOTCODE_2:
3408         case BNX_DIR_TYPE_APE_FW:
3409         case BNX_DIR_TYPE_APE_PATCH:
3410         case BNX_DIR_TYPE_KONG_FW:
3411         case BNX_DIR_TYPE_KONG_PATCH:
3412         case BNX_DIR_TYPE_BONO_FW:
3413         case BNX_DIR_TYPE_BONO_PATCH:
3414                 /* FALLTHROUGH */
3415                 return true;
3416         }
3417
3418         return false;
3419 }
3420
3421 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3422 {
3423         switch (dir_type) {
3424         case BNX_DIR_TYPE_AVS:
3425         case BNX_DIR_TYPE_EXP_ROM_MBA:
3426         case BNX_DIR_TYPE_PCIE:
3427         case BNX_DIR_TYPE_TSCF_UCODE:
3428         case BNX_DIR_TYPE_EXT_PHY:
3429         case BNX_DIR_TYPE_CCM:
3430         case BNX_DIR_TYPE_ISCSI_BOOT:
3431         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3432         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3433                 /* FALLTHROUGH */
3434                 return true;
3435         }
3436
3437         return false;
3438 }
3439
3440 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3441 {
3442         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3443                 bnxt_dir_type_is_other_exec_format(dir_type);
3444 }
3445
3446 static int
3447 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3448                 struct rte_dev_eeprom_info *in_eeprom)
3449 {
3450         struct bnxt *bp = dev->data->dev_private;
3451         uint8_t index, dir_op;
3452         uint16_t type, ext, ordinal, attr;
3453         int rc;
3454
3455         rc = is_bnxt_in_error(bp);
3456         if (rc)
3457                 return rc;
3458
3459         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3460                 "len = %d\n", bp->pdev->addr.domain,
3461                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3462                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3463
3464         if (!BNXT_PF(bp)) {
3465                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3466                 return -EINVAL;
3467         }
3468
3469         type = in_eeprom->magic >> 16;
3470
3471         if (type == 0xffff) { /* special value for directory operations */
3472                 index = in_eeprom->magic & 0xff;
3473                 dir_op = in_eeprom->magic >> 8;
3474                 if (index == 0)
3475                         return -EINVAL;
3476                 switch (dir_op) {
3477                 case 0x0e: /* erase */
3478                         if (in_eeprom->offset != ~in_eeprom->magic)
3479                                 return -EINVAL;
3480                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3481                 default:
3482                         return -EINVAL;
3483                 }
3484         }
3485
3486         /* Create or re-write an NVM item: */
3487         if (bnxt_dir_type_is_executable(type) == true)
3488                 return -EOPNOTSUPP;
3489         ext = in_eeprom->magic & 0xffff;
3490         ordinal = in_eeprom->offset >> 16;
3491         attr = in_eeprom->offset & 0xffff;
3492
3493         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3494                                      in_eeprom->data, in_eeprom->length);
3495 }
3496
3497 /*
3498  * Initialization
3499  */
3500
3501 static const struct eth_dev_ops bnxt_dev_ops = {
3502         .dev_infos_get = bnxt_dev_info_get_op,
3503         .dev_close = bnxt_dev_close_op,
3504         .dev_configure = bnxt_dev_configure_op,
3505         .dev_start = bnxt_dev_start_op,
3506         .dev_stop = bnxt_dev_stop_op,
3507         .dev_set_link_up = bnxt_dev_set_link_up_op,
3508         .dev_set_link_down = bnxt_dev_set_link_down_op,
3509         .stats_get = bnxt_stats_get_op,
3510         .stats_reset = bnxt_stats_reset_op,
3511         .rx_queue_setup = bnxt_rx_queue_setup_op,
3512         .rx_queue_release = bnxt_rx_queue_release_op,
3513         .tx_queue_setup = bnxt_tx_queue_setup_op,
3514         .tx_queue_release = bnxt_tx_queue_release_op,
3515         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3516         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3517         .reta_update = bnxt_reta_update_op,
3518         .reta_query = bnxt_reta_query_op,
3519         .rss_hash_update = bnxt_rss_hash_update_op,
3520         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3521         .link_update = bnxt_link_update_op,
3522         .promiscuous_enable = bnxt_promiscuous_enable_op,
3523         .promiscuous_disable = bnxt_promiscuous_disable_op,
3524         .allmulticast_enable = bnxt_allmulticast_enable_op,
3525         .allmulticast_disable = bnxt_allmulticast_disable_op,
3526         .mac_addr_add = bnxt_mac_addr_add_op,
3527         .mac_addr_remove = bnxt_mac_addr_remove_op,
3528         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3529         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3530         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3531         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3532         .vlan_filter_set = bnxt_vlan_filter_set_op,
3533         .vlan_offload_set = bnxt_vlan_offload_set_op,
3534         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3535         .mtu_set = bnxt_mtu_set_op,
3536         .mac_addr_set = bnxt_set_default_mac_addr_op,
3537         .xstats_get = bnxt_dev_xstats_get_op,
3538         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3539         .xstats_reset = bnxt_dev_xstats_reset_op,
3540         .fw_version_get = bnxt_fw_version_get,
3541         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3542         .rxq_info_get = bnxt_rxq_info_get_op,
3543         .txq_info_get = bnxt_txq_info_get_op,
3544         .dev_led_on = bnxt_dev_led_on_op,
3545         .dev_led_off = bnxt_dev_led_off_op,
3546         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3547         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3548         .rx_queue_count = bnxt_rx_queue_count_op,
3549         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3550         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3551         .rx_queue_start = bnxt_rx_queue_start,
3552         .rx_queue_stop = bnxt_rx_queue_stop,
3553         .tx_queue_start = bnxt_tx_queue_start,
3554         .tx_queue_stop = bnxt_tx_queue_stop,
3555         .filter_ctrl = bnxt_filter_ctrl_op,
3556         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3557         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3558         .get_eeprom           = bnxt_get_eeprom_op,
3559         .set_eeprom           = bnxt_set_eeprom_op,
3560         .timesync_enable      = bnxt_timesync_enable,
3561         .timesync_disable     = bnxt_timesync_disable,
3562         .timesync_read_time   = bnxt_timesync_read_time,
3563         .timesync_write_time   = bnxt_timesync_write_time,
3564         .timesync_adjust_time = bnxt_timesync_adjust_time,
3565         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3566         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3567 };
3568
3569 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3570 {
3571         uint32_t offset;
3572
3573         /* Only pre-map the reset GRC registers using window 3 */
3574         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3575                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3576
3577         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3578
3579         return offset;
3580 }
3581
3582 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3583 {
3584         struct bnxt_error_recovery_info *info = bp->recovery_info;
3585         uint32_t reg_base = 0xffffffff;
3586         int i;
3587
3588         /* Only pre-map the monitoring GRC registers using window 2 */
3589         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3590                 uint32_t reg = info->status_regs[i];
3591
3592                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3593                         continue;
3594
3595                 if (reg_base == 0xffffffff)
3596                         reg_base = reg & 0xfffff000;
3597                 if ((reg & 0xfffff000) != reg_base)
3598                         return -ERANGE;
3599
3600                 /* Use mask 0xffc as the Lower 2 bits indicates
3601                  * address space location
3602                  */
3603                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3604                                                 (reg & 0xffc);
3605         }
3606
3607         if (reg_base == 0xffffffff)
3608                 return 0;
3609
3610         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3611                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3612
3613         return 0;
3614 }
3615
3616 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3617 {
3618         struct bnxt_error_recovery_info *info = bp->recovery_info;
3619         uint32_t delay = info->delay_after_reset[index];
3620         uint32_t val = info->reset_reg_val[index];
3621         uint32_t reg = info->reset_reg[index];
3622         uint32_t type, offset;
3623
3624         type = BNXT_FW_STATUS_REG_TYPE(reg);
3625         offset = BNXT_FW_STATUS_REG_OFF(reg);
3626
3627         switch (type) {
3628         case BNXT_FW_STATUS_REG_TYPE_CFG:
3629                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3630                 break;
3631         case BNXT_FW_STATUS_REG_TYPE_GRC:
3632                 offset = bnxt_map_reset_regs(bp, offset);
3633                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3634                 break;
3635         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3636                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3637                 break;
3638         }
3639         /* wait on a specific interval of time until core reset is complete */
3640         if (delay)
3641                 rte_delay_ms(delay);
3642 }
3643
3644 static void bnxt_dev_cleanup(struct bnxt *bp)
3645 {
3646         bnxt_set_hwrm_link_config(bp, false);
3647         bp->link_info.link_up = 0;
3648         if (bp->dev_stopped == 0)
3649                 bnxt_dev_stop_op(bp->eth_dev);
3650
3651         bnxt_uninit_resources(bp, true);
3652 }
3653
3654 static int bnxt_restore_filters(struct bnxt *bp)
3655 {
3656         struct rte_eth_dev *dev = bp->eth_dev;
3657         int ret = 0;
3658
3659         if (dev->data->all_multicast)
3660                 ret = bnxt_allmulticast_enable_op(dev);
3661         if (dev->data->promiscuous)
3662                 ret = bnxt_promiscuous_enable_op(dev);
3663
3664         /* TODO restore other filters as well */
3665         return ret;
3666 }
3667
3668 static void bnxt_dev_recover(void *arg)
3669 {
3670         struct bnxt *bp = arg;
3671         int timeout = bp->fw_reset_max_msecs;
3672         int rc = 0;
3673
3674         /* Clear Error flag so that device re-init should happen */
3675         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3676
3677         do {
3678                 rc = bnxt_hwrm_ver_get(bp);
3679                 if (rc == 0)
3680                         break;
3681                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3682                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3683         } while (rc && timeout);
3684
3685         if (rc) {
3686                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3687                 goto err;
3688         }
3689
3690         rc = bnxt_init_resources(bp, true);
3691         if (rc) {
3692                 PMD_DRV_LOG(ERR,
3693                             "Failed to initialize resources after reset\n");
3694                 goto err;
3695         }
3696         /* clear reset flag as the device is initialized now */
3697         bp->flags &= ~BNXT_FLAG_FW_RESET;
3698
3699         rc = bnxt_dev_start_op(bp->eth_dev);
3700         if (rc) {
3701                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3702                 goto err;
3703         }
3704
3705         rc = bnxt_restore_filters(bp);
3706         if (rc)
3707                 goto err;
3708
3709         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3710         return;
3711 err:
3712         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3713         bnxt_uninit_resources(bp, false);
3714         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3715 }
3716
3717 void bnxt_dev_reset_and_resume(void *arg)
3718 {
3719         struct bnxt *bp = arg;
3720         int rc;
3721
3722         bnxt_dev_cleanup(bp);
3723
3724         bnxt_wait_for_device_shutdown(bp);
3725
3726         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3727                                bnxt_dev_recover, (void *)bp);
3728         if (rc)
3729                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3730 }
3731
3732 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3733 {
3734         struct bnxt_error_recovery_info *info = bp->recovery_info;
3735         uint32_t reg = info->status_regs[index];
3736         uint32_t type, offset, val = 0;
3737
3738         type = BNXT_FW_STATUS_REG_TYPE(reg);
3739         offset = BNXT_FW_STATUS_REG_OFF(reg);
3740
3741         switch (type) {
3742         case BNXT_FW_STATUS_REG_TYPE_CFG:
3743                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3744                 break;
3745         case BNXT_FW_STATUS_REG_TYPE_GRC:
3746                 offset = info->mapped_status_regs[index];
3747                 /* FALLTHROUGH */
3748         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3749                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3750                                        offset));
3751                 break;
3752         }
3753
3754         return val;
3755 }
3756
3757 static int bnxt_fw_reset_all(struct bnxt *bp)
3758 {
3759         struct bnxt_error_recovery_info *info = bp->recovery_info;
3760         uint32_t i;
3761         int rc = 0;
3762
3763         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3764                 /* Reset through master function driver */
3765                 for (i = 0; i < info->reg_array_cnt; i++)
3766                         bnxt_write_fw_reset_reg(bp, i);
3767                 /* Wait for time specified by FW after triggering reset */
3768                 rte_delay_ms(info->master_func_wait_period_after_reset);
3769         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3770                 /* Reset with the help of Kong processor */
3771                 rc = bnxt_hwrm_fw_reset(bp);
3772                 if (rc)
3773                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3774         }
3775
3776         return rc;
3777 }
3778
3779 static void bnxt_fw_reset_cb(void *arg)
3780 {
3781         struct bnxt *bp = arg;
3782         struct bnxt_error_recovery_info *info = bp->recovery_info;
3783         int rc = 0;
3784
3785         /* Only Master function can do FW reset */
3786         if (bnxt_is_master_func(bp) &&
3787             bnxt_is_recovery_enabled(bp)) {
3788                 rc = bnxt_fw_reset_all(bp);
3789                 if (rc) {
3790                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3791                         return;
3792                 }
3793         }
3794
3795         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3796          * EXCEPTION_FATAL_ASYNC event to all the functions
3797          * (including MASTER FUNC). After receiving this Async, all the active
3798          * drivers should treat this case as FW initiated recovery
3799          */
3800         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3801                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3802                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3803
3804                 /* To recover from error */
3805                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3806                                   (void *)bp);
3807         }
3808 }
3809
3810 /* Driver should poll FW heartbeat, reset_counter with the frequency
3811  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3812  * When the driver detects heartbeat stop or change in reset_counter,
3813  * it has to trigger a reset to recover from the error condition.
3814  * A “master PF” is the function who will have the privilege to
3815  * initiate the chimp reset. The master PF will be elected by the
3816  * firmware and will be notified through async message.
3817  */
3818 static void bnxt_check_fw_health(void *arg)
3819 {
3820         struct bnxt *bp = arg;
3821         struct bnxt_error_recovery_info *info = bp->recovery_info;
3822         uint32_t val = 0, wait_msec;
3823
3824         if (!info || !bnxt_is_recovery_enabled(bp) ||
3825             is_bnxt_in_error(bp))
3826                 return;
3827
3828         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3829         if (val == info->last_heart_beat)
3830                 goto reset;
3831
3832         info->last_heart_beat = val;
3833
3834         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3835         if (val != info->last_reset_counter)
3836                 goto reset;
3837
3838         info->last_reset_counter = val;
3839
3840         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3841                           bnxt_check_fw_health, (void *)bp);
3842
3843         return;
3844 reset:
3845         /* Stop DMA to/from device */
3846         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3847         bp->flags |= BNXT_FLAG_FW_RESET;
3848
3849         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3850
3851         if (bnxt_is_master_func(bp))
3852                 wait_msec = info->master_func_wait_period;
3853         else
3854                 wait_msec = info->normal_func_wait_period;
3855
3856         rte_eal_alarm_set(US_PER_MS * wait_msec,
3857                           bnxt_fw_reset_cb, (void *)bp);
3858 }
3859
3860 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3861 {
3862         uint32_t polling_freq;
3863
3864         if (!bnxt_is_recovery_enabled(bp))
3865                 return;
3866
3867         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3868                 return;
3869
3870         polling_freq = bp->recovery_info->driver_polling_freq;
3871
3872         rte_eal_alarm_set(US_PER_MS * polling_freq,
3873                           bnxt_check_fw_health, (void *)bp);
3874         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3875 }
3876
3877 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3878 {
3879         if (!bnxt_is_recovery_enabled(bp))
3880                 return;
3881
3882         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3883         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3884 }
3885
3886 static bool bnxt_vf_pciid(uint16_t id)
3887 {
3888         if (id == BROADCOM_DEV_ID_57304_VF ||
3889             id == BROADCOM_DEV_ID_57406_VF ||
3890             id == BROADCOM_DEV_ID_5731X_VF ||
3891             id == BROADCOM_DEV_ID_5741X_VF ||
3892             id == BROADCOM_DEV_ID_57414_VF ||
3893             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3894             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3895             id == BROADCOM_DEV_ID_58802_VF ||
3896             id == BROADCOM_DEV_ID_57500_VF1 ||
3897             id == BROADCOM_DEV_ID_57500_VF2)
3898                 return true;
3899         return false;
3900 }
3901
3902 bool bnxt_stratus_device(struct bnxt *bp)
3903 {
3904         uint16_t id = bp->pdev->id.device_id;
3905
3906         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3907             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3908             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3909                 return true;
3910         return false;
3911 }
3912
3913 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3914 {
3915         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3916         struct bnxt *bp = eth_dev->data->dev_private;
3917
3918         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3919         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3920         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3921         if (!bp->bar0 || !bp->doorbell_base) {
3922                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3923                 return -ENODEV;
3924         }
3925
3926         bp->eth_dev = eth_dev;
3927         bp->pdev = pci_dev;
3928
3929         return 0;
3930 }
3931
3932 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3933                                   struct bnxt_ctx_pg_info *ctx_pg,
3934                                   uint32_t mem_size,
3935                                   const char *suffix,
3936                                   uint16_t idx)
3937 {
3938         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3939         const struct rte_memzone *mz = NULL;
3940         char mz_name[RTE_MEMZONE_NAMESIZE];
3941         rte_iova_t mz_phys_addr;
3942         uint64_t valid_bits = 0;
3943         uint32_t sz;
3944         int i;
3945
3946         if (!mem_size)
3947                 return 0;
3948
3949         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3950                          BNXT_PAGE_SIZE;
3951         rmem->page_size = BNXT_PAGE_SIZE;
3952         rmem->pg_arr = ctx_pg->ctx_pg_arr;
3953         rmem->dma_arr = ctx_pg->ctx_dma_arr;
3954         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3955
3956         valid_bits = PTU_PTE_VALID;
3957
3958         if (rmem->nr_pages > 1) {
3959                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3960                          "bnxt_ctx_pg_tbl%s_%x_%d",
3961                          suffix, idx, bp->eth_dev->data->port_id);
3962                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3963                 mz = rte_memzone_lookup(mz_name);
3964                 if (!mz) {
3965                         mz = rte_memzone_reserve_aligned(mz_name,
3966                                                 rmem->nr_pages * 8,
3967                                                 SOCKET_ID_ANY,
3968                                                 RTE_MEMZONE_2MB |
3969                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
3970                                                 RTE_MEMZONE_IOVA_CONTIG,
3971                                                 BNXT_PAGE_SIZE);
3972                         if (mz == NULL)
3973                                 return -ENOMEM;
3974                 }
3975
3976                 memset(mz->addr, 0, mz->len);
3977                 mz_phys_addr = mz->iova;
3978                 if ((unsigned long)mz->addr == mz_phys_addr) {
3979                         PMD_DRV_LOG(DEBUG,
3980                                     "physical address same as virtual\n");
3981                         PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
3982                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3983                         if (mz_phys_addr == RTE_BAD_IOVA) {
3984                                 PMD_DRV_LOG(ERR,
3985                                         "unable to map addr to phys memory\n");
3986                                 return -ENOMEM;
3987                         }
3988                 }
3989                 rte_mem_lock_page(((char *)mz->addr));
3990
3991                 rmem->pg_tbl = mz->addr;
3992                 rmem->pg_tbl_map = mz_phys_addr;
3993                 rmem->pg_tbl_mz = mz;
3994         }
3995
3996         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
3997                  suffix, idx, bp->eth_dev->data->port_id);
3998         mz = rte_memzone_lookup(mz_name);
3999         if (!mz) {
4000                 mz = rte_memzone_reserve_aligned(mz_name,
4001                                                  mem_size,
4002                                                  SOCKET_ID_ANY,
4003                                                  RTE_MEMZONE_1GB |
4004                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4005                                                  RTE_MEMZONE_IOVA_CONTIG,
4006                                                  BNXT_PAGE_SIZE);
4007                 if (mz == NULL)
4008                         return -ENOMEM;
4009         }
4010
4011         memset(mz->addr, 0, mz->len);
4012         mz_phys_addr = mz->iova;
4013         if ((unsigned long)mz->addr == mz_phys_addr) {
4014                 PMD_DRV_LOG(DEBUG,
4015                             "Memzone physical address same as virtual.\n");
4016                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4017                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4018                         rte_mem_lock_page(((char *)mz->addr) + sz);
4019                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4020                 if (mz_phys_addr == RTE_BAD_IOVA) {
4021                         PMD_DRV_LOG(ERR,
4022                                     "unable to map addr to phys memory\n");
4023                         return -ENOMEM;
4024                 }
4025         }
4026
4027         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4028                 rte_mem_lock_page(((char *)mz->addr) + sz);
4029                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4030                 rmem->dma_arr[i] = mz_phys_addr + sz;
4031
4032                 if (rmem->nr_pages > 1) {
4033                         if (i == rmem->nr_pages - 2 &&
4034                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4035                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4036                         else if (i == rmem->nr_pages - 1 &&
4037                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4038                                 valid_bits |= PTU_PTE_LAST;
4039
4040                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4041                                                            valid_bits);
4042                 }
4043         }
4044
4045         rmem->mz = mz;
4046         if (rmem->vmem_size)
4047                 rmem->vmem = (void **)mz->addr;
4048         rmem->dma_arr[0] = mz_phys_addr;
4049         return 0;
4050 }
4051
4052 static void bnxt_free_ctx_mem(struct bnxt *bp)
4053 {
4054         int i;
4055
4056         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4057                 return;
4058
4059         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4060         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4061         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4062         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4063         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4064         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4065         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4066         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4067         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4068         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4069         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4070
4071         for (i = 0; i < BNXT_MAX_Q; i++) {
4072                 if (bp->ctx->tqm_mem[i])
4073                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4074         }
4075
4076         rte_free(bp->ctx);
4077         bp->ctx = NULL;
4078 }
4079
4080 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4081
4082 #define min_t(type, x, y) ({                    \
4083         type __min1 = (x);                      \
4084         type __min2 = (y);                      \
4085         __min1 < __min2 ? __min1 : __min2; })
4086
4087 #define max_t(type, x, y) ({                    \
4088         type __max1 = (x);                      \
4089         type __max2 = (y);                      \
4090         __max1 > __max2 ? __max1 : __max2; })
4091
4092 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4093
4094 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4095 {
4096         struct bnxt_ctx_pg_info *ctx_pg;
4097         struct bnxt_ctx_mem_info *ctx;
4098         uint32_t mem_size, ena, entries;
4099         int i, rc;
4100
4101         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4102         if (rc) {
4103                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4104                 return rc;
4105         }
4106         ctx = bp->ctx;
4107         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4108                 return 0;
4109
4110         ctx_pg = &ctx->qp_mem;
4111         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4112         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4113         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4114         if (rc)
4115                 return rc;
4116
4117         ctx_pg = &ctx->srq_mem;
4118         ctx_pg->entries = ctx->srq_max_l2_entries;
4119         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4120         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4121         if (rc)
4122                 return rc;
4123
4124         ctx_pg = &ctx->cq_mem;
4125         ctx_pg->entries = ctx->cq_max_l2_entries;
4126         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4127         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4128         if (rc)
4129                 return rc;
4130
4131         ctx_pg = &ctx->vnic_mem;
4132         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4133                 ctx->vnic_max_ring_table_entries;
4134         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4135         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4136         if (rc)
4137                 return rc;
4138
4139         ctx_pg = &ctx->stat_mem;
4140         ctx_pg->entries = ctx->stat_max_entries;
4141         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4142         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4143         if (rc)
4144                 return rc;
4145
4146         entries = ctx->qp_max_l2_entries;
4147         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4148         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4149                           ctx->tqm_max_entries_per_ring);
4150         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4151                 ctx_pg = ctx->tqm_mem[i];
4152                 /* use min tqm entries for now. */
4153                 ctx_pg->entries = entries;
4154                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4155                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4156                 if (rc)
4157                         return rc;
4158                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4159         }
4160
4161         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4162         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4163         if (rc)
4164                 PMD_DRV_LOG(ERR,
4165                             "Failed to configure context mem: rc = %d\n", rc);
4166         else
4167                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4168
4169         return rc;
4170 }
4171
4172 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4173 {
4174         struct rte_pci_device *pci_dev = bp->pdev;
4175         char mz_name[RTE_MEMZONE_NAMESIZE];
4176         const struct rte_memzone *mz = NULL;
4177         uint32_t total_alloc_len;
4178         rte_iova_t mz_phys_addr;
4179
4180         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4181                 return 0;
4182
4183         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4184                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4185                  pci_dev->addr.bus, pci_dev->addr.devid,
4186                  pci_dev->addr.function, "rx_port_stats");
4187         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4188         mz = rte_memzone_lookup(mz_name);
4189         total_alloc_len =
4190                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4191                                        sizeof(struct rx_port_stats_ext) + 512);
4192         if (!mz) {
4193                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4194                                          SOCKET_ID_ANY,
4195                                          RTE_MEMZONE_2MB |
4196                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4197                                          RTE_MEMZONE_IOVA_CONTIG);
4198                 if (mz == NULL)
4199                         return -ENOMEM;
4200         }
4201         memset(mz->addr, 0, mz->len);
4202         mz_phys_addr = mz->iova;
4203         if ((unsigned long)mz->addr == mz_phys_addr) {
4204                 PMD_DRV_LOG(DEBUG,
4205                             "Memzone physical address same as virtual.\n");
4206                 PMD_DRV_LOG(DEBUG,
4207                             "Using rte_mem_virt2iova()\n");
4208                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4209                 if (mz_phys_addr == RTE_BAD_IOVA) {
4210                         PMD_DRV_LOG(ERR,
4211                                     "Can't map address to physical memory\n");
4212                         return -ENOMEM;
4213                 }
4214         }
4215
4216         bp->rx_mem_zone = (const void *)mz;
4217         bp->hw_rx_port_stats = mz->addr;
4218         bp->hw_rx_port_stats_map = mz_phys_addr;
4219
4220         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4221                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4222                  pci_dev->addr.bus, pci_dev->addr.devid,
4223                  pci_dev->addr.function, "tx_port_stats");
4224         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4225         mz = rte_memzone_lookup(mz_name);
4226         total_alloc_len =
4227                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4228                                        sizeof(struct tx_port_stats_ext) + 512);
4229         if (!mz) {
4230                 mz = rte_memzone_reserve(mz_name,
4231                                          total_alloc_len,
4232                                          SOCKET_ID_ANY,
4233                                          RTE_MEMZONE_2MB |
4234                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4235                                          RTE_MEMZONE_IOVA_CONTIG);
4236                 if (mz == NULL)
4237                         return -ENOMEM;
4238         }
4239         memset(mz->addr, 0, mz->len);
4240         mz_phys_addr = mz->iova;
4241         if ((unsigned long)mz->addr == mz_phys_addr) {
4242                 PMD_DRV_LOG(DEBUG,
4243                             "Memzone physical address same as virtual\n");
4244                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4245                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4246                 if (mz_phys_addr == RTE_BAD_IOVA) {
4247                         PMD_DRV_LOG(ERR,
4248                                     "Can't map address to physical memory\n");
4249                         return -ENOMEM;
4250                 }
4251         }
4252
4253         bp->tx_mem_zone = (const void *)mz;
4254         bp->hw_tx_port_stats = mz->addr;
4255         bp->hw_tx_port_stats_map = mz_phys_addr;
4256         bp->flags |= BNXT_FLAG_PORT_STATS;
4257
4258         /* Display extended statistics if FW supports it */
4259         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4260             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4261             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4262                 return 0;
4263
4264         bp->hw_rx_port_stats_ext = (void *)
4265                 ((uint8_t *)bp->hw_rx_port_stats +
4266                  sizeof(struct rx_port_stats));
4267         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4268                 sizeof(struct rx_port_stats);
4269         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4270
4271         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4272             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4273                 bp->hw_tx_port_stats_ext = (void *)
4274                         ((uint8_t *)bp->hw_tx_port_stats +
4275                          sizeof(struct tx_port_stats));
4276                 bp->hw_tx_port_stats_ext_map =
4277                         bp->hw_tx_port_stats_map +
4278                         sizeof(struct tx_port_stats);
4279                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4280         }
4281
4282         return 0;
4283 }
4284
4285 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4286 {
4287         struct bnxt *bp = eth_dev->data->dev_private;
4288         int rc = 0;
4289
4290         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4291                                                RTE_ETHER_ADDR_LEN *
4292                                                bp->max_l2_ctx,
4293                                                0);
4294         if (eth_dev->data->mac_addrs == NULL) {
4295                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4296                 return -ENOMEM;
4297         }
4298
4299         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4300                 if (BNXT_PF(bp))
4301                         return -EINVAL;
4302
4303                 /* Generate a random MAC address, if none was assigned by PF */
4304                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4305                 bnxt_eth_hw_addr_random(bp->mac_addr);
4306                 PMD_DRV_LOG(INFO,
4307                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4308                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4309                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4310
4311                 rc = bnxt_hwrm_set_mac(bp);
4312                 if (!rc)
4313                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4314                                RTE_ETHER_ADDR_LEN);
4315                 return rc;
4316         }
4317
4318         /* Copy the permanent MAC from the FUNC_QCAPS response */
4319         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4320         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4321
4322         return rc;
4323 }
4324
4325 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4326 {
4327         int rc = 0;
4328
4329         /* MAC is already configured in FW */
4330         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4331                 return 0;
4332
4333         /* Restore the old MAC configured */
4334         rc = bnxt_hwrm_set_mac(bp);
4335         if (rc)
4336                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4337
4338         return rc;
4339 }
4340
4341 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4342 {
4343         if (!BNXT_PF(bp))
4344                 return;
4345
4346 #define ALLOW_FUNC(x)   \
4347         { \
4348                 uint32_t arg = (x); \
4349                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4350                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4351         }
4352
4353         /* Forward all requests if firmware is new enough */
4354         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4355              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4356             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4357                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4358         } else {
4359                 PMD_DRV_LOG(WARNING,
4360                             "Firmware too old for VF mailbox functionality\n");
4361                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4362         }
4363
4364         /*
4365          * The following are used for driver cleanup. If we disallow these,
4366          * VF drivers can't clean up cleanly.
4367          */
4368         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4369         ALLOW_FUNC(HWRM_VNIC_FREE);
4370         ALLOW_FUNC(HWRM_RING_FREE);
4371         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4372         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4373         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4374         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4375         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4376         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4377 }
4378
4379 static int bnxt_init_fw(struct bnxt *bp)
4380 {
4381         uint16_t mtu;
4382         int rc = 0;
4383
4384         rc = bnxt_hwrm_ver_get(bp);
4385         if (rc)
4386                 return rc;
4387
4388         rc = bnxt_hwrm_func_reset(bp);
4389         if (rc)
4390                 return -EIO;
4391
4392         rc = bnxt_hwrm_queue_qportcfg(bp);
4393         if (rc)
4394                 return rc;
4395
4396         /* Get the MAX capabilities for this function */
4397         rc = bnxt_hwrm_func_qcaps(bp);
4398         if (rc)
4399                 return rc;
4400
4401         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4402         if (rc)
4403                 return rc;
4404
4405         /* Get the adapter error recovery support info */
4406         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4407         if (rc)
4408                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4409
4410         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4411             mtu != bp->eth_dev->data->mtu)
4412                 bp->eth_dev->data->mtu = mtu;
4413
4414         bnxt_hwrm_port_led_qcaps(bp);
4415
4416         return 0;
4417 }
4418
4419 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4420 {
4421         int rc;
4422
4423         rc = bnxt_init_fw(bp);
4424         if (rc)
4425                 return rc;
4426
4427         if (!reconfig_dev) {
4428                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4429                 if (rc)
4430                         return rc;
4431         } else {
4432                 rc = bnxt_restore_dflt_mac(bp);
4433                 if (rc)
4434                         return rc;
4435         }
4436
4437         bnxt_config_vf_req_fwd(bp);
4438
4439         rc = bnxt_hwrm_func_driver_register(bp);
4440         if (rc) {
4441                 PMD_DRV_LOG(ERR, "Failed to register driver");
4442                 return -EBUSY;
4443         }
4444
4445         if (BNXT_PF(bp)) {
4446                 if (bp->pdev->max_vfs) {
4447                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4448                         if (rc) {
4449                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4450                                 return rc;
4451                         }
4452                 } else {
4453                         rc = bnxt_hwrm_allocate_pf_only(bp);
4454                         if (rc) {
4455                                 PMD_DRV_LOG(ERR,
4456                                             "Failed to allocate PF resources");
4457                                 return rc;
4458                         }
4459                 }
4460         }
4461
4462         rc = bnxt_alloc_mem(bp, reconfig_dev);
4463         if (rc)
4464                 return rc;
4465
4466         rc = bnxt_setup_int(bp);
4467         if (rc)
4468                 return rc;
4469
4470         bnxt_init_nic(bp);
4471
4472         rc = bnxt_request_int(bp);
4473         if (rc)
4474                 return rc;
4475
4476         return 0;
4477 }
4478
4479 static int
4480 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4481 {
4482         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4483         static int version_printed;
4484         struct bnxt *bp;
4485         int rc;
4486
4487         if (version_printed++ == 0)
4488                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4489
4490         rte_eth_copy_pci_info(eth_dev, pci_dev);
4491
4492         bp = eth_dev->data->dev_private;
4493
4494         bp->dev_stopped = 1;
4495
4496         eth_dev->dev_ops = &bnxt_dev_ops;
4497         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4498         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4499
4500         /*
4501          * For secondary processes, we don't initialise any further
4502          * as primary has already done this work.
4503          */
4504         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4505                 return 0;
4506
4507         if (bnxt_vf_pciid(pci_dev->id.device_id))
4508                 bp->flags |= BNXT_FLAG_VF;
4509
4510         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4511             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4512             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4513             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4514             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4515                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4516
4517         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4518             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4519             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4520             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4521                 bp->flags |= BNXT_FLAG_STINGRAY;
4522
4523         rc = bnxt_init_board(eth_dev);
4524         if (rc) {
4525                 PMD_DRV_LOG(ERR,
4526                             "Failed to initialize board rc: %x\n", rc);
4527                 return rc;
4528         }
4529
4530         rc = bnxt_alloc_hwrm_resources(bp);
4531         if (rc) {
4532                 PMD_DRV_LOG(ERR,
4533                             "Failed to allocate hwrm resource rc: %x\n", rc);
4534                 goto error_free;
4535         }
4536         rc = bnxt_init_resources(bp, false);
4537         if (rc)
4538                 goto error_free;
4539
4540         rc = bnxt_alloc_stats_mem(bp);
4541         if (rc)
4542                 goto error_free;
4543
4544         PMD_DRV_LOG(INFO,
4545                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4546                     pci_dev->mem_resource[0].phys_addr,
4547                     pci_dev->mem_resource[0].addr);
4548
4549         return 0;
4550
4551 error_free:
4552         bnxt_dev_uninit(eth_dev);
4553         return rc;
4554 }
4555
4556 static int
4557 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4558 {
4559         int rc;
4560
4561         bnxt_disable_int(bp);
4562         bnxt_free_int(bp);
4563         bnxt_free_mem(bp, reconfig_dev);
4564         bnxt_hwrm_func_buf_unrgtr(bp);
4565         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4566         bp->flags &= ~BNXT_FLAG_REGISTERED;
4567         bnxt_free_ctx_mem(bp);
4568         if (!reconfig_dev) {
4569                 bnxt_free_hwrm_resources(bp);
4570
4571                 if (bp->recovery_info != NULL) {
4572                         rte_free(bp->recovery_info);
4573                         bp->recovery_info = NULL;
4574                 }
4575         }
4576
4577         return rc;
4578 }
4579
4580 static int
4581 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4582 {
4583         struct bnxt *bp = eth_dev->data->dev_private;
4584         int rc;
4585
4586         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4587                 return -EPERM;
4588
4589         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4590
4591         rc = bnxt_uninit_resources(bp, false);
4592
4593         if (bp->grp_info != NULL) {
4594                 rte_free(bp->grp_info);
4595                 bp->grp_info = NULL;
4596         }
4597
4598         if (bp->tx_mem_zone) {
4599                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4600                 bp->tx_mem_zone = NULL;
4601         }
4602
4603         if (bp->rx_mem_zone) {
4604                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4605                 bp->rx_mem_zone = NULL;
4606         }
4607
4608         if (bp->dev_stopped == 0)
4609                 bnxt_dev_close_op(eth_dev);
4610         if (bp->pf.vf_info)
4611                 rte_free(bp->pf.vf_info);
4612         eth_dev->dev_ops = NULL;
4613         eth_dev->rx_pkt_burst = NULL;
4614         eth_dev->tx_pkt_burst = NULL;
4615
4616         return rc;
4617 }
4618
4619 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4620         struct rte_pci_device *pci_dev)
4621 {
4622         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4623                 bnxt_dev_init);
4624 }
4625
4626 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4627 {
4628         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4629                 return rte_eth_dev_pci_generic_remove(pci_dev,
4630                                 bnxt_dev_uninit);
4631         else
4632                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4633 }
4634
4635 static struct rte_pci_driver bnxt_rte_pmd = {
4636         .id_table = bnxt_pci_id_map,
4637         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4638         .probe = bnxt_pci_probe,
4639         .remove = bnxt_pci_remove,
4640 };
4641
4642 static bool
4643 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4644 {
4645         if (strcmp(dev->device->driver->name, drv->driver.name))
4646                 return false;
4647
4648         return true;
4649 }
4650
4651 bool is_bnxt_supported(struct rte_eth_dev *dev)
4652 {
4653         return is_device_supported(dev, &bnxt_rte_pmd);
4654 }
4655
4656 RTE_INIT(bnxt_init_log)
4657 {
4658         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4659         if (bnxt_logtype_driver >= 0)
4660                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4661 }
4662
4663 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4664 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4665 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");