drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29
  30 #define DRV_MODULE_NAME         "bnxt"
  31 static const char bnxt_version[] =
  32         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  33 int bnxt_logtype_driver;
  34
  35 /*
  36  * The set of PCI devices this driver supports
  37  */
  38 static const struct rte_pci_id bnxt_pci_id_map[] = {
  39         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  40                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  41         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  42                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  43         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  92         { .vendor_id = 0, /* sentinel */ },
  93 };
  94
  95 #define BNXT_ETH_RSS_SUPPORT (  \
  96         ETH_RSS_IPV4 |          \
  97         ETH_RSS_NONFRAG_IPV4_TCP |      \
  98         ETH_RSS_NONFRAG_IPV4_UDP |      \
  99         ETH_RSS_IPV6 |          \
 100         ETH_RSS_NONFRAG_IPV6_TCP |      \
 101         ETH_RSS_NONFRAG_IPV6_UDP)
 102
 103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 104                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 105                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 106                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_TCP_TSO | \
 108                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 109                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 110                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 114                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 115
 116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 117                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 118                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 119                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 120                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 122                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 123                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 124                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 125                                      DEV_RX_OFFLOAD_TCP_LRO | \
 126                                      DEV_RX_OFFLOAD_SCATTER | \
 127                                      DEV_RX_OFFLOAD_RSS_HASH)
 128
 129 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 130 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 131 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 132 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 133 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 134 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 135
 136 int is_bnxt_in_error(struct bnxt *bp)
 137 {
 138         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 139                 return -EIO;
 140         if (bp->flags & BNXT_FLAG_FW_RESET)
 141                 return -EBUSY;
 142
 143         return 0;
 144 }
 145
 146 /***********************/
 147
 148 /*
 149  * High level utility functions
 150  */
 151
 152 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 153 {
 154         if (!BNXT_CHIP_THOR(bp))
 155                 return 1;
 156
 157         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 158                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 159                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 160 }
 161
 162 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 163 {
 164         if (!BNXT_CHIP_THOR(bp))
 165                 return HW_HASH_INDEX_SIZE;
 166
 167         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 168 }
 169
 170 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 171 {
 172         bnxt_free_filter_mem(bp);
 173         bnxt_free_vnic_attributes(bp);
 174         bnxt_free_vnic_mem(bp);
 175
 176         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 177          * If the number of rings change across fw update,
 178          * we don't have much choice except to warn the user.
 179          */
 180         if (!reconfig) {
 181                 bnxt_free_stats(bp);
 182                 bnxt_free_tx_rings(bp);
 183                 bnxt_free_rx_rings(bp);
 184         }
 185         bnxt_free_async_cp_ring(bp);
 186         bnxt_free_rxtx_nq_ring(bp);
 187
 188         rte_free(bp->grp_info);
 189         bp->grp_info = NULL;
 190 }
 191
 192 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 193 {
 194         int rc;
 195
 196         rc = bnxt_alloc_ring_grps(bp);
 197         if (rc)
 198                 goto alloc_mem_err;
 199
 200         rc = bnxt_alloc_async_ring_struct(bp);
 201         if (rc)
 202                 goto alloc_mem_err;
 203
 204         rc = bnxt_alloc_vnic_mem(bp);
 205         if (rc)
 206                 goto alloc_mem_err;
 207
 208         rc = bnxt_alloc_vnic_attributes(bp);
 209         if (rc)
 210                 goto alloc_mem_err;
 211
 212         rc = bnxt_alloc_filter_mem(bp);
 213         if (rc)
 214                 goto alloc_mem_err;
 215
 216         rc = bnxt_alloc_async_cp_ring(bp);
 217         if (rc)
 218                 goto alloc_mem_err;
 219
 220         rc = bnxt_alloc_rxtx_nq_ring(bp);
 221         if (rc)
 222                 goto alloc_mem_err;
 223
 224         return 0;
 225
 226 alloc_mem_err:
 227         bnxt_free_mem(bp, reconfig);
 228         return rc;
 229 }
 230
 231 static int bnxt_init_chip(struct bnxt *bp)
 232 {
 233         struct bnxt_rx_queue *rxq;
 234         struct rte_eth_link new;
 235         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 236         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 237         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 238         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 239         uint32_t intr_vector = 0;
 240         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 241         uint32_t vec = BNXT_MISC_VEC_ID;
 242         unsigned int i, j;
 243         int rc;
 244
 245         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 246                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 247                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 248                 bp->flags |= BNXT_FLAG_JUMBO;
 249         } else {
 250                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 251                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 252                 bp->flags &= ~BNXT_FLAG_JUMBO;
 253         }
 254
 255         /* THOR does not support ring groups.
 256          * But we will use the array to save RSS context IDs.
 257          */
 258         if (BNXT_CHIP_THOR(bp))
 259                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 260
 261         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 262         if (rc) {
 263                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 264                 goto err_out;
 265         }
 266
 267         rc = bnxt_alloc_hwrm_rings(bp);
 268         if (rc) {
 269                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 270                 goto err_out;
 271         }
 272
 273         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 274         if (rc) {
 275                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 276                 goto err_out;
 277         }
 278
 279         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 280                 goto skip_cosq_cfg;
 281
 282         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 283                 if (bp->rx_cos_queue[i].id != 0xff) {
 284                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 285
 286                         if (!vnic) {
 287                                 PMD_DRV_LOG(ERR,
 288                                             "Num pools more than FW profile\n");
 289                                 rc = -EINVAL;
 290                                 goto err_out;
 291                         }
 292                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 293                         bp->rx_cosq_cnt++;
 294                 }
 295         }
 296
 297 skip_cosq_cfg:
 298         rc = bnxt_mq_rx_configure(bp);
 299         if (rc) {
 300                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 301                 goto err_out;
 302         }
 303
 304         /* VNIC configuration */
 305         for (i = 0; i < bp->nr_vnics; i++) {
 306                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 307                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 308
 309                 rc = bnxt_vnic_grp_alloc(bp, vnic);
 310                 if (rc)
 311                         goto err_out;
 312
 313                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 314                             i, vnic, vnic->fw_grp_ids);
 315
 316                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 317                 if (rc) {
 318                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 319                                 i, rc);
 320                         goto err_out;
 321                 }
 322
 323                 /* Alloc RSS context only if RSS mode is enabled */
 324                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 325                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 326
 327                         rc = 0;
 328                         for (j = 0; j < nr_ctxs; j++) {
 329                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 330                                 if (rc)
 331                                         break;
 332                         }
 333                         if (rc) {
 334                                 PMD_DRV_LOG(ERR,
 335                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 336                                   i, j, rc);
 337                                 goto err_out;
 338                         }
 339                         vnic->num_lb_ctxts = nr_ctxs;
 340                 }
 341
 342                 /*
 343                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 344                  * setting is not available at this time, it will not be
 345                  * configured correctly in the CFA.
 346                  */
 347                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 348                         vnic->vlan_strip = true;
 349                 else
 350                         vnic->vlan_strip = false;
 351
 352                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 353                 if (rc) {
 354                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 355                                 i, rc);
 356                         goto err_out;
 357                 }
 358
 359                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 360                 if (rc) {
 361                         PMD_DRV_LOG(ERR,
 362                                 "HWRM vnic %d filter failure rc: %x\n",
 363                                 i, rc);
 364                         goto err_out;
 365                 }
 366
 367                 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 368                         rxq = bp->eth_dev->data->rx_queues[j];
 369
 370                         PMD_DRV_LOG(DEBUG,
 371                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 372                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 373
 374                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 375                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 376                 }
 377
 378                 rc = bnxt_vnic_rss_configure(bp, vnic);
 379                 if (rc) {
 380                         PMD_DRV_LOG(ERR,
 381                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 382                         goto err_out;
 383                 }
 384
 385                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 386
 387                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 388                     DEV_RX_OFFLOAD_TCP_LRO)
 389                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 390                 else
 391                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 392         }
 393         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 394         if (rc) {
 395                 PMD_DRV_LOG(ERR,
 396                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 397                 goto err_out;
 398         }
 399
 400         /* check and configure queue intr-vector mapping */
 401         if ((rte_intr_cap_multiple(intr_handle) ||
 402              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 403             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 404                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 405                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 406                 if (intr_vector > bp->rx_cp_nr_rings) {
 407                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 408                                         bp->rx_cp_nr_rings);
 409                         return -ENOTSUP;
 410                 }
 411                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 412                 if (rc)
 413                         return rc;
 414         }
 415
 416         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 417                 intr_handle->intr_vec =
 418                         rte_zmalloc("intr_vec",
 419                                     bp->eth_dev->data->nb_rx_queues *
 420                                     sizeof(int), 0);
 421                 if (intr_handle->intr_vec == NULL) {
 422                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 423                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 424                         rc = -ENOMEM;
 425                         goto err_disable;
 426                 }
 427                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 428                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 429                          intr_handle->intr_vec, intr_handle->nb_efd,
 430                         intr_handle->max_intr);
 431                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 432                      queue_id++) {
 433                         intr_handle->intr_vec[queue_id] =
 434                                                         vec + BNXT_RX_VEC_START;
 435                         if (vec < base + intr_handle->nb_efd - 1)
 436                                 vec++;
 437                 }
 438         }
 439
 440         /* enable uio/vfio intr/eventfd mapping */
 441         rc = rte_intr_enable(intr_handle);
 442         if (rc)
 443                 goto err_free;
 444
 445         rc = bnxt_get_hwrm_link_config(bp, &new);
 446         if (rc) {
 447                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 448                 goto err_free;
 449         }
 450
 451         if (!bp->link_info.link_up) {
 452                 rc = bnxt_set_hwrm_link_config(bp, true);
 453                 if (rc) {
 454                         PMD_DRV_LOG(ERR,
 455                                 "HWRM link config failure rc: %x\n", rc);
 456                         goto err_free;
 457                 }
 458         }
 459         bnxt_print_link_info(bp->eth_dev);
 460
 461         return 0;
 462
 463 err_free:
 464         rte_free(intr_handle->intr_vec);
 465 err_disable:
 466         rte_intr_efd_disable(intr_handle);
 467 err_out:
 468         /* Some of the error status returned by FW may not be from errno.h */
 469         if (rc > 0)
 470                 rc = -EIO;
 471
 472         return rc;
 473 }
 474
 475 static int bnxt_shutdown_nic(struct bnxt *bp)
 476 {
 477         bnxt_free_all_hwrm_resources(bp);
 478         bnxt_free_all_filters(bp);
 479         bnxt_free_all_vnics(bp);
 480         return 0;
 481 }
 482
 483 /*
 484  * Device configuration and status function
 485  */
 486
 487 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 488                                 struct rte_eth_dev_info *dev_info)
 489 {
 490         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 491         struct bnxt *bp = eth_dev->data->dev_private;
 492         uint16_t max_vnics, i, j, vpool, vrxq;
 493         unsigned int max_rx_rings;
 494         int rc;
 495
 496         rc = is_bnxt_in_error(bp);
 497         if (rc)
 498                 return rc;
 499
 500         /* MAC Specifics */
 501         dev_info->max_mac_addrs = bp->max_l2_ctx;
 502         dev_info->max_hash_mac_addrs = 0;
 503
 504         /* PF/VF specifics */
 505         if (BNXT_PF(bp))
 506                 dev_info->max_vfs = pdev->max_vfs;
 507
 508         max_rx_rings = BNXT_MAX_RINGS(bp);
 509         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 510         dev_info->max_rx_queues = max_rx_rings;
 511         dev_info->max_tx_queues = max_rx_rings;
 512         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 513         dev_info->hash_key_size = 40;
 514         max_vnics = bp->max_vnics;
 515
 516         /* MTU specifics */
 517         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 518         dev_info->max_mtu = BNXT_MAX_MTU;
 519
 520         /* Fast path specifics */
 521         dev_info->min_rx_bufsize = 1;
 522         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 523
 524         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 525         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 526                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 527         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 528         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 529
 530         /* *INDENT-OFF* */
 531         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 532                 .rx_thresh = {
 533                         .pthresh = 8,
 534                         .hthresh = 8,
 535                         .wthresh = 0,
 536                 },
 537                 .rx_free_thresh = 32,
 538                 /* If no descriptors available, pkts are dropped by default */
 539                 .rx_drop_en = 1,
 540         };
 541
 542         dev_info->default_txconf = (struct rte_eth_txconf) {
 543                 .tx_thresh = {
 544                         .pthresh = 32,
 545                         .hthresh = 0,
 546                         .wthresh = 0,
 547                 },
 548                 .tx_free_thresh = 32,
 549                 .tx_rs_thresh = 32,
 550         };
 551         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 552
 553         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 554         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 555         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 556         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 557         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 558
 559         /* *INDENT-ON* */
 560
 561         /*
 562          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 563          *       need further investigation.
 564          */
 565
 566         /* VMDq resources */
 567         vpool = 64; /* ETH_64_POOLS */
 568         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 569         for (i = 0; i < 4; vpool >>= 1, i++) {
 570                 if (max_vnics > vpool) {
 571                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 572                                 if (dev_info->max_rx_queues > vrxq) {
 573                                         if (vpool > vrxq)
 574                                                 vpool = vrxq;
 575                                         goto found;
 576                                 }
 577                         }
 578                         /* Not enough resources to support VMDq */
 579                         break;
 580                 }
 581         }
 582         /* Not enough resources to support VMDq */
 583         vpool = 0;
 584         vrxq = 0;
 585 found:
 586         dev_info->max_vmdq_pools = vpool;
 587         dev_info->vmdq_queue_num = vrxq;
 588
 589         dev_info->vmdq_pool_base = 0;
 590         dev_info->vmdq_queue_base = 0;
 591
 592         return 0;
 593 }
 594
 595 /* Configure the device based on the configuration provided */
 596 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 597 {
 598         struct bnxt *bp = eth_dev->data->dev_private;
 599         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 600         int rc;
 601
 602         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 603         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 604         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 605         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 606
 607         rc = is_bnxt_in_error(bp);
 608         if (rc)
 609                 return rc;
 610
 611         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 612                 rc = bnxt_hwrm_check_vf_rings(bp);
 613                 if (rc) {
 614                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 615                         return -ENOSPC;
 616                 }
 617
 618                 /* If a resource has already been allocated - in this case
 619                  * it is the async completion ring, free it. Reallocate it after
 620                  * resource reservation. This will ensure the resource counts
 621                  * are calculated correctly.
 622                  */
 623
 624                 pthread_mutex_lock(&bp->def_cp_lock);
 625
 626                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 627                         bnxt_disable_int(bp);
 628                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 629                 }
 630
 631                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 632                 if (rc) {
 633                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 634                         pthread_mutex_unlock(&bp->def_cp_lock);
 635                         return -ENOSPC;
 636                 }
 637
 638                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 639                         rc = bnxt_alloc_async_cp_ring(bp);
 640                         if (rc) {
 641                                 pthread_mutex_unlock(&bp->def_cp_lock);
 642                                 return rc;
 643                         }
 644                         bnxt_enable_int(bp);
 645                 }
 646
 647                 pthread_mutex_unlock(&bp->def_cp_lock);
 648         } else {
 649                 /* legacy driver needs to get updated values */
 650                 rc = bnxt_hwrm_func_qcaps(bp);
 651                 if (rc) {
 652                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 653                         return rc;
 654                 }
 655         }
 656
 657         /* Inherit new configurations */
 658         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 659             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 660             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 661                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 662             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 663             bp->max_stat_ctx)
 664                 goto resource_error;
 665
 666         if (BNXT_HAS_RING_GRPS(bp) &&
 667             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 668                 goto resource_error;
 669
 670         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 671             bp->max_vnics < eth_dev->data->nb_rx_queues)
 672                 goto resource_error;
 673
 674         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 675         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 676
 677         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 678                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 679         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
 680
 681         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 682                 eth_dev->data->mtu =
 683                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 684                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 685                         BNXT_NUM_VLANS;
 686                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 687         }
 688         return 0;
 689
 690 resource_error:
 691         PMD_DRV_LOG(ERR,
 692                     "Insufficient resources to support requested config\n");
 693         PMD_DRV_LOG(ERR,
 694                     "Num Queues Requested: Tx %d, Rx %d\n",
 695                     eth_dev->data->nb_tx_queues,
 696                     eth_dev->data->nb_rx_queues);
 697         PMD_DRV_LOG(ERR,
 698                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 699                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 700                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 701         return -ENOSPC;
 702 }
 703
 704 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 705 {
 706         struct rte_eth_link *link = &eth_dev->data->dev_link;
 707
 708         if (link->link_status)
 709                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 710                         eth_dev->data->port_id,
 711                         (uint32_t)link->link_speed,
 712                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 713                         ("full-duplex") : ("half-duplex\n"));
 714         else
 715                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 716                         eth_dev->data->port_id);
 717 }
 718
 719 /*
 720  * Determine whether the current configuration requires support for scattered
 721  * receive; return 1 if scattered receive is required and 0 if not.
 722  */
 723 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 724 {
 725         uint16_t buf_size;
 726         int i;
 727
 728         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 729                 return 1;
 730
 731         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 732                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 733
 734                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 735                                       RTE_PKTMBUF_HEADROOM);
 736                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 737                         return 1;
 738         }
 739         return 0;
 740 }
 741
 742 static eth_rx_burst_t
 743 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 744 {
 745 #ifdef RTE_ARCH_X86
 746 #ifndef RTE_LIBRTE_IEEE1588
 747         /*
 748          * Vector mode receive can be enabled only if scatter rx is not
 749          * in use and rx offloads are limited to VLAN stripping and
 750          * CRC stripping.
 751          */
 752         if (!eth_dev->data->scattered_rx &&
 753             !(eth_dev->data->dev_conf.rxmode.offloads &
 754               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 755                 DEV_RX_OFFLOAD_KEEP_CRC |
 756                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 757                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 758                 DEV_RX_OFFLOAD_UDP_CKSUM |
 759                 DEV_RX_OFFLOAD_TCP_CKSUM |
 760                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 761                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 762                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 763                             eth_dev->data->port_id);
 764                 return bnxt_recv_pkts_vec;
 765         }
 766         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 767                     eth_dev->data->port_id);
 768         PMD_DRV_LOG(INFO,
 769                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 770                     eth_dev->data->port_id,
 771                     eth_dev->data->scattered_rx,
 772                     eth_dev->data->dev_conf.rxmode.offloads);
 773 #endif
 774 #endif
 775         return bnxt_recv_pkts;
 776 }
 777
 778 static eth_tx_burst_t
 779 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 780 {
 781 #ifdef RTE_ARCH_X86
 782 #ifndef RTE_LIBRTE_IEEE1588
 783         /*
 784          * Vector mode transmit can be enabled only if not using scatter rx
 785          * or tx offloads.
 786          */
 787         if (!eth_dev->data->scattered_rx &&
 788             !eth_dev->data->dev_conf.txmode.offloads) {
 789                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 790                             eth_dev->data->port_id);
 791                 return bnxt_xmit_pkts_vec;
 792         }
 793         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 794                     eth_dev->data->port_id);
 795         PMD_DRV_LOG(INFO,
 796                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 797                     eth_dev->data->port_id,
 798                     eth_dev->data->scattered_rx,
 799                     eth_dev->data->dev_conf.txmode.offloads);
 800 #endif
 801 #endif
 802         return bnxt_xmit_pkts;
 803 }
 804
 805 static int bnxt_handle_if_change_status(struct bnxt *bp)
 806 {
 807         int rc;
 808
 809         /* Since fw has undergone a reset and lost all contexts,
 810          * set fatal flag to not issue hwrm during cleanup
 811          */
 812         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 813         bnxt_uninit_resources(bp, true);
 814
 815         /* clear fatal flag so that re-init happens */
 816         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 817         rc = bnxt_init_resources(bp, true);
 818
 819         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 820
 821         return rc;
 822 }
 823
 824 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 825 {
 826         struct bnxt *bp = eth_dev->data->dev_private;
 827         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 828         int vlan_mask = 0;
 829         int rc;
 830
 831         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
 832                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
 833                 return -EINVAL;
 834         }
 835
 836         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 837                 PMD_DRV_LOG(ERR,
 838                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 839                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 840         }
 841
 842         rc = bnxt_hwrm_if_change(bp, 1);
 843         if (!rc) {
 844                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 845                         rc = bnxt_handle_if_change_status(bp);
 846                         if (rc)
 847                                 return rc;
 848                 }
 849         }
 850         bnxt_enable_int(bp);
 851
 852         rc = bnxt_init_chip(bp);
 853         if (rc)
 854                 goto error;
 855
 856         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 857
 858         bnxt_link_update_op(eth_dev, 1);
 859
 860         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 861                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 862         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 863                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 864         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 865         if (rc)
 866                 goto error;
 867
 868         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 869         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 870
 871         bp->flags |= BNXT_FLAG_INIT_DONE;
 872         eth_dev->data->dev_started = 1;
 873         bp->dev_stopped = 0;
 874         pthread_mutex_lock(&bp->def_cp_lock);
 875         bnxt_schedule_fw_health_check(bp);
 876         pthread_mutex_unlock(&bp->def_cp_lock);
 877         return 0;
 878
 879 error:
 880         bnxt_hwrm_if_change(bp, 0);
 881         bnxt_shutdown_nic(bp);
 882         bnxt_free_tx_mbufs(bp);
 883         bnxt_free_rx_mbufs(bp);
 884         return rc;
 885 }
 886
 887 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 888 {
 889         struct bnxt *bp = eth_dev->data->dev_private;
 890         int rc = 0;
 891
 892         if (!bp->link_info.link_up)
 893                 rc = bnxt_set_hwrm_link_config(bp, true);
 894         if (!rc)
 895                 eth_dev->data->dev_link.link_status = 1;
 896
 897         bnxt_print_link_info(eth_dev);
 898         return rc;
 899 }
 900
 901 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 902 {
 903         struct bnxt *bp = eth_dev->data->dev_private;
 904
 905         eth_dev->data->dev_link.link_status = 0;
 906         bnxt_set_hwrm_link_config(bp, false);
 907         bp->link_info.link_up = 0;
 908
 909         return 0;
 910 }
 911
 912 /* Unload the driver, release resources */
 913 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 914 {
 915         struct bnxt *bp = eth_dev->data->dev_private;
 916         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 917         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 918
 919         eth_dev->data->dev_started = 0;
 920         /* Prevent crashes when queues are still in use */
 921         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 922         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 923
 924         bnxt_disable_int(bp);
 925
 926         /* disable uio/vfio intr/eventfd mapping */
 927         rte_intr_disable(intr_handle);
 928
 929         bnxt_cancel_fw_health_check(bp);
 930
 931         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 932         if (bp->eth_dev->data->dev_started) {
 933                 /* TBD: STOP HW queues DMA */
 934                 eth_dev->data->dev_link.link_status = 0;
 935         }
 936         bnxt_dev_set_link_down_op(eth_dev);
 937
 938         /* Wait for link to be reset and the async notification to process.
 939          * During reset recovery, there is no need to wait
 940          */
 941         if (!is_bnxt_in_error(bp))
 942                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
 943
 944         /* Clean queue intr-vector mapping */
 945         rte_intr_efd_disable(intr_handle);
 946         if (intr_handle->intr_vec != NULL) {
 947                 rte_free(intr_handle->intr_vec);
 948                 intr_handle->intr_vec = NULL;
 949         }
 950
 951         bnxt_hwrm_port_clr_stats(bp);
 952         bnxt_free_tx_mbufs(bp);
 953         bnxt_free_rx_mbufs(bp);
 954         /* Process any remaining notifications in default completion queue */
 955         bnxt_int_handler(eth_dev);
 956         bnxt_shutdown_nic(bp);
 957         bnxt_hwrm_if_change(bp, 0);
 958         bp->dev_stopped = 1;
 959         bp->rx_cosq_cnt = 0;
 960 }
 961
 962 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 963 {
 964         struct bnxt *bp = eth_dev->data->dev_private;
 965
 966         if (bp->dev_stopped == 0)
 967                 bnxt_dev_stop_op(eth_dev);
 968
 969         if (eth_dev->data->mac_addrs != NULL) {
 970                 rte_free(eth_dev->data->mac_addrs);
 971                 eth_dev->data->mac_addrs = NULL;
 972         }
 973         if (bp->grp_info != NULL) {
 974                 rte_free(bp->grp_info);
 975                 bp->grp_info = NULL;
 976         }
 977
 978         bnxt_dev_uninit(eth_dev);
 979 }
 980
 981 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 982                                     uint32_t index)
 983 {
 984         struct bnxt *bp = eth_dev->data->dev_private;
 985         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 986         struct bnxt_vnic_info *vnic;
 987         struct bnxt_filter_info *filter, *temp_filter;
 988         uint32_t i;
 989
 990         if (is_bnxt_in_error(bp))
 991                 return;
 992
 993         /*
 994          * Loop through all VNICs from the specified filter flow pools to
 995          * remove the corresponding MAC addr filter
 996          */
 997         for (i = 0; i < bp->nr_vnics; i++) {
 998                 if (!(pool_mask & (1ULL << i)))
 999                         continue;
1000
1001                 vnic = &bp->vnic_info[i];
1002                 filter = STAILQ_FIRST(&vnic->filter);
1003                 while (filter) {
1004                         temp_filter = STAILQ_NEXT(filter, next);
1005                         if (filter->mac_index == index) {
1006                                 STAILQ_REMOVE(&vnic->filter, filter,
1007                                                 bnxt_filter_info, next);
1008                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1009                                 filter->mac_index = INVALID_MAC_INDEX;
1010                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1011                                 bnxt_free_filter(bp, filter);
1012                         }
1013                         filter = temp_filter;
1014                 }
1015         }
1016 }
1017
1018 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1019                                struct rte_ether_addr *mac_addr, uint32_t index,
1020                                uint32_t pool)
1021 {
1022         struct bnxt_filter_info *filter;
1023         int rc = 0;
1024
1025         /* Attach requested MAC address to the new l2_filter */
1026         STAILQ_FOREACH(filter, &vnic->filter, next) {
1027                 if (filter->mac_index == index) {
1028                         PMD_DRV_LOG(DEBUG,
1029                                     "MAC addr already existed for pool %d\n",
1030                                     pool);
1031                         return 0;
1032                 }
1033         }
1034
1035         filter = bnxt_alloc_filter(bp);
1036         if (!filter) {
1037                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1038                 return -ENODEV;
1039         }
1040
1041         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1042          * if the MAC that's been programmed now is a different one, then,
1043          * copy that addr to filter->l2_addr
1044          */
1045         if (mac_addr)
1046                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1047         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1048
1049         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1050         if (!rc) {
1051                 filter->mac_index = index;
1052                 if (filter->mac_index == 0)
1053                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1054                 else
1055                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1056         } else {
1057                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1058                 bnxt_free_filter(bp, filter);
1059         }
1060
1061         return rc;
1062 }
1063
1064 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1065                                 struct rte_ether_addr *mac_addr,
1066                                 uint32_t index, uint32_t pool)
1067 {
1068         struct bnxt *bp = eth_dev->data->dev_private;
1069         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1070         int rc = 0;
1071
1072         rc = is_bnxt_in_error(bp);
1073         if (rc)
1074                 return rc;
1075
1076         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1077                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1078                 return -ENOTSUP;
1079         }
1080
1081         if (!vnic) {
1082                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1083                 return -EINVAL;
1084         }
1085
1086         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1087
1088         return rc;
1089 }
1090
1091 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1092 {
1093         int rc = 0;
1094         struct bnxt *bp = eth_dev->data->dev_private;
1095         struct rte_eth_link new;
1096         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1097
1098         rc = is_bnxt_in_error(bp);
1099         if (rc)
1100                 return rc;
1101
1102         memset(&new, 0, sizeof(new));
1103         do {
1104                 /* Retrieve link info from hardware */
1105                 rc = bnxt_get_hwrm_link_config(bp, &new);
1106                 if (rc) {
1107                         new.link_speed = ETH_LINK_SPEED_100M;
1108                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1109                         PMD_DRV_LOG(ERR,
1110                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1111                         goto out;
1112                 }
1113
1114                 if (!wait_to_complete || new.link_status)
1115                         break;
1116
1117                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1118         } while (cnt--);
1119
1120 out:
1121         /* Timed out or success */
1122         if (new.link_status != eth_dev->data->dev_link.link_status ||
1123         new.link_speed != eth_dev->data->dev_link.link_speed) {
1124                 rte_eth_linkstatus_set(eth_dev, &new);
1125
1126                 _rte_eth_dev_callback_process(eth_dev,
1127                                               RTE_ETH_EVENT_INTR_LSC,
1128                                               NULL);
1129
1130                 bnxt_print_link_info(eth_dev);
1131         }
1132
1133         return rc;
1134 }
1135
1136 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1137 {
1138         struct bnxt *bp = eth_dev->data->dev_private;
1139         struct bnxt_vnic_info *vnic;
1140         uint32_t old_flags;
1141         int rc;
1142
1143         rc = is_bnxt_in_error(bp);
1144         if (rc)
1145                 return rc;
1146
1147         if (bp->vnic_info == NULL)
1148                 return 0;
1149
1150         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1151
1152         old_flags = vnic->flags;
1153         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1154         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1155         if (rc != 0)
1156                 vnic->flags = old_flags;
1157
1158         return rc;
1159 }
1160
1161 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1162 {
1163         struct bnxt *bp = eth_dev->data->dev_private;
1164         struct bnxt_vnic_info *vnic;
1165         uint32_t old_flags;
1166         int rc;
1167
1168         rc = is_bnxt_in_error(bp);
1169         if (rc)
1170                 return rc;
1171
1172         if (bp->vnic_info == NULL)
1173                 return 0;
1174
1175         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1176
1177         old_flags = vnic->flags;
1178         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1179         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1180         if (rc != 0)
1181                 vnic->flags = old_flags;
1182
1183         return rc;
1184 }
1185
1186 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1187 {
1188         struct bnxt *bp = eth_dev->data->dev_private;
1189         struct bnxt_vnic_info *vnic;
1190         uint32_t old_flags;
1191         int rc;
1192
1193         rc = is_bnxt_in_error(bp);
1194         if (rc)
1195                 return rc;
1196
1197         if (bp->vnic_info == NULL)
1198                 return 0;
1199
1200         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1201
1202         old_flags = vnic->flags;
1203         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1204         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1205         if (rc != 0)
1206                 vnic->flags = old_flags;
1207
1208         return rc;
1209 }
1210
1211 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1212 {
1213         struct bnxt *bp = eth_dev->data->dev_private;
1214         struct bnxt_vnic_info *vnic;
1215         uint32_t old_flags;
1216         int rc;
1217
1218         rc = is_bnxt_in_error(bp);
1219         if (rc)
1220                 return rc;
1221
1222         if (bp->vnic_info == NULL)
1223                 return 0;
1224
1225         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1226
1227         old_flags = vnic->flags;
1228         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1229         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1230         if (rc != 0)
1231                 vnic->flags = old_flags;
1232
1233         return rc;
1234 }
1235
1236 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1237 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1238 {
1239         if (qid >= bp->rx_nr_rings)
1240                 return NULL;
1241
1242         return bp->eth_dev->data->rx_queues[qid];
1243 }
1244
1245 /* Return rxq corresponding to a given rss table ring/group ID. */
1246 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1247 {
1248         struct bnxt_rx_queue *rxq;
1249         unsigned int i;
1250
1251         if (!BNXT_HAS_RING_GRPS(bp)) {
1252                 for (i = 0; i < bp->rx_nr_rings; i++) {
1253                         rxq = bp->eth_dev->data->rx_queues[i];
1254                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1255                                 return rxq->index;
1256                 }
1257         } else {
1258                 for (i = 0; i < bp->rx_nr_rings; i++) {
1259                         if (bp->grp_info[i].fw_grp_id == fwr)
1260                                 return i;
1261                 }
1262         }
1263
1264         return INVALID_HW_RING_ID;
1265 }
1266
1267 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1268                             struct rte_eth_rss_reta_entry64 *reta_conf,
1269                             uint16_t reta_size)
1270 {
1271         struct bnxt *bp = eth_dev->data->dev_private;
1272         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1273         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1274         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1275         uint16_t idx, sft;
1276         int i, rc;
1277
1278         rc = is_bnxt_in_error(bp);
1279         if (rc)
1280                 return rc;
1281
1282         if (!vnic->rss_table)
1283                 return -EINVAL;
1284
1285         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1286                 return -EINVAL;
1287
1288         if (reta_size != tbl_size) {
1289                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1290                         "(%d) must equal the size supported by the hardware "
1291                         "(%d)\n", reta_size, tbl_size);
1292                 return -EINVAL;
1293         }
1294
1295         for (i = 0; i < reta_size; i++) {
1296                 struct bnxt_rx_queue *rxq;
1297
1298                 idx = i / RTE_RETA_GROUP_SIZE;
1299                 sft = i % RTE_RETA_GROUP_SIZE;
1300
1301                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1302                         continue;
1303
1304                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1305                 if (!rxq) {
1306                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1307                         return -EINVAL;
1308                 }
1309
1310                 if (BNXT_CHIP_THOR(bp)) {
1311                         vnic->rss_table[i * 2] =
1312                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1313                         vnic->rss_table[i * 2 + 1] =
1314                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1315                 } else {
1316                         vnic->rss_table[i] =
1317                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1318                 }
1319         }
1320
1321         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1322         return 0;
1323 }
1324
1325 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1326                               struct rte_eth_rss_reta_entry64 *reta_conf,
1327                               uint16_t reta_size)
1328 {
1329         struct bnxt *bp = eth_dev->data->dev_private;
1330         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1331         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1332         uint16_t idx, sft, i;
1333         int rc;
1334
1335         rc = is_bnxt_in_error(bp);
1336         if (rc)
1337                 return rc;
1338
1339         /* Retrieve from the default VNIC */
1340         if (!vnic)
1341                 return -EINVAL;
1342         if (!vnic->rss_table)
1343                 return -EINVAL;
1344
1345         if (reta_size != tbl_size) {
1346                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1347                         "(%d) must equal the size supported by the hardware "
1348                         "(%d)\n", reta_size, tbl_size);
1349                 return -EINVAL;
1350         }
1351
1352         for (idx = 0, i = 0; i < reta_size; i++) {
1353                 idx = i / RTE_RETA_GROUP_SIZE;
1354                 sft = i % RTE_RETA_GROUP_SIZE;
1355
1356                 if (reta_conf[idx].mask & (1ULL << sft)) {
1357                         uint16_t qid;
1358
1359                         if (BNXT_CHIP_THOR(bp))
1360                                 qid = bnxt_rss_to_qid(bp,
1361                                                       vnic->rss_table[i * 2]);
1362                         else
1363                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1364
1365                         if (qid == INVALID_HW_RING_ID) {
1366                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1367                                 return -EINVAL;
1368                         }
1369                         reta_conf[idx].reta[sft] = qid;
1370                 }
1371         }
1372
1373         return 0;
1374 }
1375
1376 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1377                                    struct rte_eth_rss_conf *rss_conf)
1378 {
1379         struct bnxt *bp = eth_dev->data->dev_private;
1380         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1381         struct bnxt_vnic_info *vnic;
1382         int rc;
1383
1384         rc = is_bnxt_in_error(bp);
1385         if (rc)
1386                 return rc;
1387
1388         /*
1389          * If RSS enablement were different than dev_configure,
1390          * then return -EINVAL
1391          */
1392         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1393                 if (!rss_conf->rss_hf)
1394                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1395         } else {
1396                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1397                         return -EINVAL;
1398         }
1399
1400         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1401         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1402
1403         /* Update the default RSS VNIC(s) */
1404         vnic = &bp->vnic_info[0];
1405         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1406
1407         /*
1408          * If hashkey is not specified, use the previously configured
1409          * hashkey
1410          */
1411         if (!rss_conf->rss_key)
1412                 goto rss_config;
1413
1414         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1415                 PMD_DRV_LOG(ERR,
1416                             "Invalid hashkey length, should be 16 bytes\n");
1417                 return -EINVAL;
1418         }
1419         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1420
1421 rss_config:
1422         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1423         return 0;
1424 }
1425
1426 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1427                                      struct rte_eth_rss_conf *rss_conf)
1428 {
1429         struct bnxt *bp = eth_dev->data->dev_private;
1430         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1431         int len, rc;
1432         uint32_t hash_types;
1433
1434         rc = is_bnxt_in_error(bp);
1435         if (rc)
1436                 return rc;
1437
1438         /* RSS configuration is the same for all VNICs */
1439         if (vnic && vnic->rss_hash_key) {
1440                 if (rss_conf->rss_key) {
1441                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1442                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1443                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1444                 }
1445
1446                 hash_types = vnic->hash_type;
1447                 rss_conf->rss_hf = 0;
1448                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1449                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1450                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1451                 }
1452                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1453                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1454                         hash_types &=
1455                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1456                 }
1457                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1458                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1459                         hash_types &=
1460                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1461                 }
1462                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1463                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1464                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1465                 }
1466                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1467                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1468                         hash_types &=
1469                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1470                 }
1471                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1472                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1473                         hash_types &=
1474                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1475                 }
1476                 if (hash_types) {
1477                         PMD_DRV_LOG(ERR,
1478                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1479                                 vnic->hash_type);
1480                         return -ENOTSUP;
1481                 }
1482         } else {
1483                 rss_conf->rss_hf = 0;
1484         }
1485         return 0;
1486 }
1487
1488 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1489                                struct rte_eth_fc_conf *fc_conf)
1490 {
1491         struct bnxt *bp = dev->data->dev_private;
1492         struct rte_eth_link link_info;
1493         int rc;
1494
1495         rc = is_bnxt_in_error(bp);
1496         if (rc)
1497                 return rc;
1498
1499         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1500         if (rc)
1501                 return rc;
1502
1503         memset(fc_conf, 0, sizeof(*fc_conf));
1504         if (bp->link_info.auto_pause)
1505                 fc_conf->autoneg = 1;
1506         switch (bp->link_info.pause) {
1507         case 0:
1508                 fc_conf->mode = RTE_FC_NONE;
1509                 break;
1510         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1511                 fc_conf->mode = RTE_FC_TX_PAUSE;
1512                 break;
1513         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1514                 fc_conf->mode = RTE_FC_RX_PAUSE;
1515                 break;
1516         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1517                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1518                 fc_conf->mode = RTE_FC_FULL;
1519                 break;
1520         }
1521         return 0;
1522 }
1523
1524 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1525                                struct rte_eth_fc_conf *fc_conf)
1526 {
1527         struct bnxt *bp = dev->data->dev_private;
1528         int rc;
1529
1530         rc = is_bnxt_in_error(bp);
1531         if (rc)
1532                 return rc;
1533
1534         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1535                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1536                 return -ENOTSUP;
1537         }
1538
1539         switch (fc_conf->mode) {
1540         case RTE_FC_NONE:
1541                 bp->link_info.auto_pause = 0;
1542                 bp->link_info.force_pause = 0;
1543                 break;
1544         case RTE_FC_RX_PAUSE:
1545                 if (fc_conf->autoneg) {
1546                         bp->link_info.auto_pause =
1547                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1548                         bp->link_info.force_pause = 0;
1549                 } else {
1550                         bp->link_info.auto_pause = 0;
1551                         bp->link_info.force_pause =
1552                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1553                 }
1554                 break;
1555         case RTE_FC_TX_PAUSE:
1556                 if (fc_conf->autoneg) {
1557                         bp->link_info.auto_pause =
1558                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1559                         bp->link_info.force_pause = 0;
1560                 } else {
1561                         bp->link_info.auto_pause = 0;
1562                         bp->link_info.force_pause =
1563                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1564                 }
1565                 break;
1566         case RTE_FC_FULL:
1567                 if (fc_conf->autoneg) {
1568                         bp->link_info.auto_pause =
1569                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1570                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1571                         bp->link_info.force_pause = 0;
1572                 } else {
1573                         bp->link_info.auto_pause = 0;
1574                         bp->link_info.force_pause =
1575                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1576                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1577                 }
1578                 break;
1579         }
1580         return bnxt_set_hwrm_link_config(bp, true);
1581 }
1582
1583 /* Add UDP tunneling port */
1584 static int
1585 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1586                          struct rte_eth_udp_tunnel *udp_tunnel)
1587 {
1588         struct bnxt *bp = eth_dev->data->dev_private;
1589         uint16_t tunnel_type = 0;
1590         int rc = 0;
1591
1592         rc = is_bnxt_in_error(bp);
1593         if (rc)
1594                 return rc;
1595
1596         switch (udp_tunnel->prot_type) {
1597         case RTE_TUNNEL_TYPE_VXLAN:
1598                 if (bp->vxlan_port_cnt) {
1599                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1600                                 udp_tunnel->udp_port);
1601                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1602                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1603                                 return -ENOSPC;
1604                         }
1605                         bp->vxlan_port_cnt++;
1606                         return 0;
1607                 }
1608                 tunnel_type =
1609                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1610                 bp->vxlan_port_cnt++;
1611                 break;
1612         case RTE_TUNNEL_TYPE_GENEVE:
1613                 if (bp->geneve_port_cnt) {
1614                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1615                                 udp_tunnel->udp_port);
1616                         if (bp->geneve_port != udp_tunnel->udp_port) {
1617                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1618                                 return -ENOSPC;
1619                         }
1620                         bp->geneve_port_cnt++;
1621                         return 0;
1622                 }
1623                 tunnel_type =
1624                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1625                 bp->geneve_port_cnt++;
1626                 break;
1627         default:
1628                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1629                 return -ENOTSUP;
1630         }
1631         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1632                                              tunnel_type);
1633         return rc;
1634 }
1635
1636 static int
1637 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1638                          struct rte_eth_udp_tunnel *udp_tunnel)
1639 {
1640         struct bnxt *bp = eth_dev->data->dev_private;
1641         uint16_t tunnel_type = 0;
1642         uint16_t port = 0;
1643         int rc = 0;
1644
1645         rc = is_bnxt_in_error(bp);
1646         if (rc)
1647                 return rc;
1648
1649         switch (udp_tunnel->prot_type) {
1650         case RTE_TUNNEL_TYPE_VXLAN:
1651                 if (!bp->vxlan_port_cnt) {
1652                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1653                         return -EINVAL;
1654                 }
1655                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1656                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1657                                 udp_tunnel->udp_port, bp->vxlan_port);
1658                         return -EINVAL;
1659                 }
1660                 if (--bp->vxlan_port_cnt)
1661                         return 0;
1662
1663                 tunnel_type =
1664                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1665                 port = bp->vxlan_fw_dst_port_id;
1666                 break;
1667         case RTE_TUNNEL_TYPE_GENEVE:
1668                 if (!bp->geneve_port_cnt) {
1669                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1670                         return -EINVAL;
1671                 }
1672                 if (bp->geneve_port != udp_tunnel->udp_port) {
1673                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1674                                 udp_tunnel->udp_port, bp->geneve_port);
1675                         return -EINVAL;
1676                 }
1677                 if (--bp->geneve_port_cnt)
1678                         return 0;
1679
1680                 tunnel_type =
1681                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1682                 port = bp->geneve_fw_dst_port_id;
1683                 break;
1684         default:
1685                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1686                 return -ENOTSUP;
1687         }
1688
1689         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1690         if (!rc) {
1691                 if (tunnel_type ==
1692                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1693                         bp->vxlan_port = 0;
1694                 if (tunnel_type ==
1695                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1696                         bp->geneve_port = 0;
1697         }
1698         return rc;
1699 }
1700
1701 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1702 {
1703         struct bnxt_filter_info *filter;
1704         struct bnxt_vnic_info *vnic;
1705         int rc = 0;
1706         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1707
1708         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1709         filter = STAILQ_FIRST(&vnic->filter);
1710         while (filter) {
1711                 /* Search for this matching MAC+VLAN filter */
1712                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1713                         /* Delete the filter */
1714                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1715                         if (rc)
1716                                 return rc;
1717                         STAILQ_REMOVE(&vnic->filter, filter,
1718                                       bnxt_filter_info, next);
1719                         bnxt_free_filter(bp, filter);
1720                         PMD_DRV_LOG(INFO,
1721                                     "Deleted vlan filter for %d\n",
1722                                     vlan_id);
1723                         return 0;
1724                 }
1725                 filter = STAILQ_NEXT(filter, next);
1726         }
1727         return -ENOENT;
1728 }
1729
1730 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1731 {
1732         struct bnxt_filter_info *filter;
1733         struct bnxt_vnic_info *vnic;
1734         int rc = 0;
1735         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1736                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1737         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1738
1739         /* Implementation notes on the use of VNIC in this command:
1740          *
1741          * By default, these filters belong to default vnic for the function.
1742          * Once these filters are set up, only destination VNIC can be modified.
1743          * If the destination VNIC is not specified in this command,
1744          * then the HWRM shall only create an l2 context id.
1745          */
1746
1747         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1748         filter = STAILQ_FIRST(&vnic->filter);
1749         /* Check if the VLAN has already been added */
1750         while (filter) {
1751                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1752                         return -EEXIST;
1753
1754                 filter = STAILQ_NEXT(filter, next);
1755         }
1756
1757         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1758          * command to create MAC+VLAN filter with the right flags, enables set.
1759          */
1760         filter = bnxt_alloc_filter(bp);
1761         if (!filter) {
1762                 PMD_DRV_LOG(ERR,
1763                             "MAC/VLAN filter alloc failed\n");
1764                 return -ENOMEM;
1765         }
1766         /* MAC + VLAN ID filter */
1767         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1768          * untagged packets are received
1769          *
1770          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1771          * packets and only the programmed vlan's packets are received
1772          */
1773         filter->l2_ivlan = vlan_id;
1774         filter->l2_ivlan_mask = 0x0FFF;
1775         filter->enables |= en;
1776         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1777
1778         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1779         if (rc) {
1780                 /* Free the newly allocated filter as we were
1781                  * not able to create the filter in hardware.
1782                  */
1783                 filter->fw_l2_filter_id = UINT64_MAX;
1784                 bnxt_free_filter(bp, filter);
1785                 return rc;
1786         }
1787
1788         filter->mac_index = 0;
1789         /* Add this new filter to the list */
1790         if (vlan_id == 0)
1791                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1792         else
1793                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1794
1795         PMD_DRV_LOG(INFO,
1796                     "Added Vlan filter for %d\n", vlan_id);
1797         return rc;
1798 }
1799
1800 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1801                 uint16_t vlan_id, int on)
1802 {
1803         struct bnxt *bp = eth_dev->data->dev_private;
1804         int rc;
1805
1806         rc = is_bnxt_in_error(bp);
1807         if (rc)
1808                 return rc;
1809
1810         /* These operations apply to ALL existing MAC/VLAN filters */
1811         if (on)
1812                 return bnxt_add_vlan_filter(bp, vlan_id);
1813         else
1814                 return bnxt_del_vlan_filter(bp, vlan_id);
1815 }
1816
1817 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1818                                     struct bnxt_vnic_info *vnic)
1819 {
1820         struct bnxt_filter_info *filter;
1821         int rc;
1822
1823         filter = STAILQ_FIRST(&vnic->filter);
1824         while (filter) {
1825                 if (filter->mac_index == 0 &&
1826                     !memcmp(filter->l2_addr, bp->mac_addr,
1827                             RTE_ETHER_ADDR_LEN)) {
1828                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1829                         if (!rc) {
1830                                 STAILQ_REMOVE(&vnic->filter, filter,
1831                                               bnxt_filter_info, next);
1832                                 bnxt_free_filter(bp, filter);
1833                                 filter->fw_l2_filter_id = UINT64_MAX;
1834                         }
1835                         return rc;
1836                 }
1837                 filter = STAILQ_NEXT(filter, next);
1838         }
1839         return 0;
1840 }
1841
1842 static int
1843 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1844 {
1845         struct bnxt *bp = dev->data->dev_private;
1846         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1847         struct bnxt_vnic_info *vnic;
1848         unsigned int i;
1849         int rc;
1850
1851         rc = is_bnxt_in_error(bp);
1852         if (rc)
1853                 return rc;
1854
1855         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1856         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1857                 /* Remove any VLAN filters programmed */
1858                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1859                         bnxt_del_vlan_filter(bp, i);
1860
1861                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1862                 if (rc)
1863                         return rc;
1864         } else {
1865                 /* Default filter will allow packets that match the
1866                  * dest mac. So, it has to be deleted, otherwise, we
1867                  * will endup receiving vlan packets for which the
1868                  * filter is not programmed, when hw-vlan-filter
1869                  * configuration is ON
1870                  */
1871                 bnxt_del_dflt_mac_filter(bp, vnic);
1872                 /* This filter will allow only untagged packets */
1873                 bnxt_add_vlan_filter(bp, 0);
1874         }
1875         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1876                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1877
1878         if (mask & ETH_VLAN_STRIP_MASK) {
1879                 /* Enable or disable VLAN stripping */
1880                 for (i = 0; i < bp->nr_vnics; i++) {
1881                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1882                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1883                                 vnic->vlan_strip = true;
1884                         else
1885                                 vnic->vlan_strip = false;
1886                         bnxt_hwrm_vnic_cfg(bp, vnic);
1887                 }
1888                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1889                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1890         }
1891
1892         if (mask & ETH_VLAN_EXTEND_MASK) {
1893                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1894                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1895                 else
1896                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1897         }
1898
1899         return 0;
1900 }
1901
1902 static int
1903 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1904                       uint16_t tpid)
1905 {
1906         struct bnxt *bp = dev->data->dev_private;
1907         int qinq = dev->data->dev_conf.rxmode.offloads &
1908                    DEV_RX_OFFLOAD_VLAN_EXTEND;
1909
1910         if (vlan_type != ETH_VLAN_TYPE_INNER &&
1911             vlan_type != ETH_VLAN_TYPE_OUTER) {
1912                 PMD_DRV_LOG(ERR,
1913                             "Unsupported vlan type.");
1914                 return -EINVAL;
1915         }
1916         if (!qinq) {
1917                 PMD_DRV_LOG(ERR,
1918                             "QinQ not enabled. Needs to be ON as we can "
1919                             "accelerate only outer vlan\n");
1920                 return -EINVAL;
1921         }
1922
1923         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1924                 switch (tpid) {
1925                 case RTE_ETHER_TYPE_QINQ:
1926                         bp->outer_tpid_bd =
1927                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1928                                 break;
1929                 case RTE_ETHER_TYPE_VLAN:
1930                         bp->outer_tpid_bd =
1931                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1932                                 break;
1933                 case 0x9100:
1934                         bp->outer_tpid_bd =
1935                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1936                                 break;
1937                 case 0x9200:
1938                         bp->outer_tpid_bd =
1939                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1940                                 break;
1941                 case 0x9300:
1942                         bp->outer_tpid_bd =
1943                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1944                                 break;
1945                 default:
1946                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1947                         return -EINVAL;
1948                 }
1949                 bp->outer_tpid_bd |= tpid;
1950                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1951         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1952                 PMD_DRV_LOG(ERR,
1953                             "Can accelerate only outer vlan in QinQ\n");
1954                 return -EINVAL;
1955         }
1956
1957         return 0;
1958 }
1959
1960 static int
1961 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1962                              struct rte_ether_addr *addr)
1963 {
1964         struct bnxt *bp = dev->data->dev_private;
1965         /* Default Filter is tied to VNIC 0 */
1966         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1967         struct bnxt_filter_info *filter;
1968         int rc;
1969
1970         rc = is_bnxt_in_error(bp);
1971         if (rc)
1972                 return rc;
1973
1974         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1975                 return -EPERM;
1976
1977         if (rte_is_zero_ether_addr(addr))
1978                 return -EINVAL;
1979
1980         STAILQ_FOREACH(filter, &vnic->filter, next) {
1981                 /* Default Filter is at Index 0 */
1982                 if (filter->mac_index != 0)
1983                         continue;
1984
1985                 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
1986                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1987                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
1988                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1989                 filter->enables |=
1990                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1991                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1992
1993                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1994                 if (rc) {
1995                         memcpy(filter->l2_addr, bp->mac_addr,
1996                                RTE_ETHER_ADDR_LEN);
1997                         return rc;
1998                 }
1999
2000                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2001                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2002                 return 0;
2003         }
2004
2005         return 0;
2006 }
2007
2008 static int
2009 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2010                           struct rte_ether_addr *mc_addr_set,
2011                           uint32_t nb_mc_addr)
2012 {
2013         struct bnxt *bp = eth_dev->data->dev_private;
2014         char *mc_addr_list = (char *)mc_addr_set;
2015         struct bnxt_vnic_info *vnic;
2016         uint32_t off = 0, i = 0;
2017         int rc;
2018
2019         rc = is_bnxt_in_error(bp);
2020         if (rc)
2021                 return rc;
2022
2023         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2024
2025         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2026                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2027                 goto allmulti;
2028         }
2029
2030         /* TODO Check for Duplicate mcast addresses */
2031         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2032         for (i = 0; i < nb_mc_addr; i++) {
2033                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2034                         RTE_ETHER_ADDR_LEN);
2035                 off += RTE_ETHER_ADDR_LEN;
2036         }
2037
2038         vnic->mc_addr_cnt = i;
2039         if (vnic->mc_addr_cnt)
2040                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2041         else
2042                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2043
2044 allmulti:
2045         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2046 }
2047
2048 static int
2049 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2050 {
2051         struct bnxt *bp = dev->data->dev_private;
2052         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2053         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2054         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2055         int ret;
2056
2057         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2058                         fw_major, fw_minor, fw_updt);
2059
2060         ret += 1; /* add the size of '\0' */
2061         if (fw_size < (uint32_t)ret)
2062                 return ret;
2063         else
2064                 return 0;
2065 }
2066
2067 static void
2068 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2069         struct rte_eth_rxq_info *qinfo)
2070 {
2071         struct bnxt *bp = dev->data->dev_private;
2072         struct bnxt_rx_queue *rxq;
2073
2074         if (is_bnxt_in_error(bp))
2075                 return;
2076
2077         rxq = dev->data->rx_queues[queue_id];
2078
2079         qinfo->mp = rxq->mb_pool;
2080         qinfo->scattered_rx = dev->data->scattered_rx;
2081         qinfo->nb_desc = rxq->nb_rx_desc;
2082
2083         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2084         qinfo->conf.rx_drop_en = 0;
2085         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2086 }
2087
2088 static void
2089 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2090         struct rte_eth_txq_info *qinfo)
2091 {
2092         struct bnxt *bp = dev->data->dev_private;
2093         struct bnxt_tx_queue *txq;
2094
2095         if (is_bnxt_in_error(bp))
2096                 return;
2097
2098         txq = dev->data->tx_queues[queue_id];
2099
2100         qinfo->nb_desc = txq->nb_tx_desc;
2101
2102         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2103         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2104         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2105
2106         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2107         qinfo->conf.tx_rs_thresh = 0;
2108         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2109 }
2110
2111 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2112 {
2113         struct bnxt *bp = eth_dev->data->dev_private;
2114         uint32_t new_pkt_size;
2115         uint32_t rc = 0;
2116         uint32_t i;
2117
2118         rc = is_bnxt_in_error(bp);
2119         if (rc)
2120                 return rc;
2121
2122         /* Exit if receive queues are not configured yet */
2123         if (!eth_dev->data->nb_rx_queues)
2124                 return rc;
2125
2126         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2127                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2128
2129 #ifdef RTE_ARCH_X86
2130         /*
2131          * If vector-mode tx/rx is active, disallow any MTU change that would
2132          * require scattered receive support.
2133          */
2134         if (eth_dev->data->dev_started &&
2135             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2136              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2137             (new_pkt_size >
2138              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2139                 PMD_DRV_LOG(ERR,
2140                             "MTU change would require scattered rx support. ");
2141                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2142                 return -EINVAL;
2143         }
2144 #endif
2145
2146         if (new_mtu > RTE_ETHER_MTU) {
2147                 bp->flags |= BNXT_FLAG_JUMBO;
2148                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2149                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2150         } else {
2151                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2152                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2153                 bp->flags &= ~BNXT_FLAG_JUMBO;
2154         }
2155
2156         /* Is there a change in mtu setting? */
2157         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2158                 return rc;
2159
2160         for (i = 0; i < bp->nr_vnics; i++) {
2161                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2162                 uint16_t size = 0;
2163
2164                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2165                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2166                 if (rc)
2167                         break;
2168
2169                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2170                 size -= RTE_PKTMBUF_HEADROOM;
2171
2172                 if (size < new_mtu) {
2173                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2174                         if (rc)
2175                                 return rc;
2176                 }
2177         }
2178
2179         if (!rc)
2180                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2181
2182         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2183
2184         return rc;
2185 }
2186
2187 static int
2188 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2189 {
2190         struct bnxt *bp = dev->data->dev_private;
2191         uint16_t vlan = bp->vlan;
2192         int rc;
2193
2194         rc = is_bnxt_in_error(bp);
2195         if (rc)
2196                 return rc;
2197
2198         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2199                 PMD_DRV_LOG(ERR,
2200                         "PVID cannot be modified for this function\n");
2201                 return -ENOTSUP;
2202         }
2203         bp->vlan = on ? pvid : 0;
2204
2205         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2206         if (rc)
2207                 bp->vlan = vlan;
2208         return rc;
2209 }
2210
2211 static int
2212 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2213 {
2214         struct bnxt *bp = dev->data->dev_private;
2215         int rc;
2216
2217         rc = is_bnxt_in_error(bp);
2218         if (rc)
2219                 return rc;
2220
2221         return bnxt_hwrm_port_led_cfg(bp, true);
2222 }
2223
2224 static int
2225 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2226 {
2227         struct bnxt *bp = dev->data->dev_private;
2228         int rc;
2229
2230         rc = is_bnxt_in_error(bp);
2231         if (rc)
2232                 return rc;
2233
2234         return bnxt_hwrm_port_led_cfg(bp, false);
2235 }
2236
2237 static uint32_t
2238 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2239 {
2240         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2241         uint32_t desc = 0, raw_cons = 0, cons;
2242         struct bnxt_cp_ring_info *cpr;
2243         struct bnxt_rx_queue *rxq;
2244         struct rx_pkt_cmpl *rxcmp;
2245         int rc;
2246
2247         rc = is_bnxt_in_error(bp);
2248         if (rc)
2249                 return rc;
2250
2251         rxq = dev->data->rx_queues[rx_queue_id];
2252         cpr = rxq->cp_ring;
2253         raw_cons = cpr->cp_raw_cons;
2254
2255         while (1) {
2256                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2257                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2258                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2259
2260                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2261                         break;
2262                 } else {
2263                         raw_cons++;
2264                         desc++;
2265                 }
2266         }
2267
2268         return desc;
2269 }
2270
2271 static int
2272 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2273 {
2274         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2275         struct bnxt_rx_ring_info *rxr;
2276         struct bnxt_cp_ring_info *cpr;
2277         struct bnxt_sw_rx_bd *rx_buf;
2278         struct rx_pkt_cmpl *rxcmp;
2279         uint32_t cons, cp_cons;
2280         int rc;
2281
2282         if (!rxq)
2283                 return -EINVAL;
2284
2285         rc = is_bnxt_in_error(rxq->bp);
2286         if (rc)
2287                 return rc;
2288
2289         cpr = rxq->cp_ring;
2290         rxr = rxq->rx_ring;
2291
2292         if (offset >= rxq->nb_rx_desc)
2293                 return -EINVAL;
2294
2295         cons = RING_CMP(cpr->cp_ring_struct, offset);
2296         cp_cons = cpr->cp_raw_cons;
2297         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2298
2299         if (cons > cp_cons) {
2300                 if (CMPL_VALID(rxcmp, cpr->valid))
2301                         return RTE_ETH_RX_DESC_DONE;
2302         } else {
2303                 if (CMPL_VALID(rxcmp, !cpr->valid))
2304                         return RTE_ETH_RX_DESC_DONE;
2305         }
2306         rx_buf = &rxr->rx_buf_ring[cons];
2307         if (rx_buf->mbuf == NULL)
2308                 return RTE_ETH_RX_DESC_UNAVAIL;
2309
2310
2311         return RTE_ETH_RX_DESC_AVAIL;
2312 }
2313
2314 static int
2315 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2316 {
2317         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2318         struct bnxt_tx_ring_info *txr;
2319         struct bnxt_cp_ring_info *cpr;
2320         struct bnxt_sw_tx_bd *tx_buf;
2321         struct tx_pkt_cmpl *txcmp;
2322         uint32_t cons, cp_cons;
2323         int rc;
2324
2325         if (!txq)
2326                 return -EINVAL;
2327
2328         rc = is_bnxt_in_error(txq->bp);
2329         if (rc)
2330                 return rc;
2331
2332         cpr = txq->cp_ring;
2333         txr = txq->tx_ring;
2334
2335         if (offset >= txq->nb_tx_desc)
2336                 return -EINVAL;
2337
2338         cons = RING_CMP(cpr->cp_ring_struct, offset);
2339         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2340         cp_cons = cpr->cp_raw_cons;
2341
2342         if (cons > cp_cons) {
2343                 if (CMPL_VALID(txcmp, cpr->valid))
2344                         return RTE_ETH_TX_DESC_UNAVAIL;
2345         } else {
2346                 if (CMPL_VALID(txcmp, !cpr->valid))
2347                         return RTE_ETH_TX_DESC_UNAVAIL;
2348         }
2349         tx_buf = &txr->tx_buf_ring[cons];
2350         if (tx_buf->mbuf == NULL)
2351                 return RTE_ETH_TX_DESC_DONE;
2352
2353         return RTE_ETH_TX_DESC_FULL;
2354 }
2355
2356 static struct bnxt_filter_info *
2357 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2358                                 struct rte_eth_ethertype_filter *efilter,
2359                                 struct bnxt_vnic_info *vnic0,
2360                                 struct bnxt_vnic_info *vnic,
2361                                 int *ret)
2362 {
2363         struct bnxt_filter_info *mfilter = NULL;
2364         int match = 0;
2365         *ret = 0;
2366
2367         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2368                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2369                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2370                         " ethertype filter.", efilter->ether_type);
2371                 *ret = -EINVAL;
2372                 goto exit;
2373         }
2374         if (efilter->queue >= bp->rx_nr_rings) {
2375                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2376                 *ret = -EINVAL;
2377                 goto exit;
2378         }
2379
2380         vnic0 = &bp->vnic_info[0];
2381         vnic = &bp->vnic_info[efilter->queue];
2382         if (vnic == NULL) {
2383                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2384                 *ret = -EINVAL;
2385                 goto exit;
2386         }
2387
2388         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2389                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2390                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2391                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2392                              mfilter->flags ==
2393                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2394                              mfilter->ethertype == efilter->ether_type)) {
2395                                 match = 1;
2396                                 break;
2397                         }
2398                 }
2399         } else {
2400                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2401                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2402                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2403                              mfilter->ethertype == efilter->ether_type &&
2404                              mfilter->flags ==
2405                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2406                                 match = 1;
2407                                 break;
2408                         }
2409         }
2410
2411         if (match)
2412                 *ret = -EEXIST;
2413
2414 exit:
2415         return mfilter;
2416 }
2417
2418 static int
2419 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2420                         enum rte_filter_op filter_op,
2421                         void *arg)
2422 {
2423         struct bnxt *bp = dev->data->dev_private;
2424         struct rte_eth_ethertype_filter *efilter =
2425                         (struct rte_eth_ethertype_filter *)arg;
2426         struct bnxt_filter_info *bfilter, *filter1;
2427         struct bnxt_vnic_info *vnic, *vnic0;
2428         int ret;
2429
2430         if (filter_op == RTE_ETH_FILTER_NOP)
2431                 return 0;
2432
2433         if (arg == NULL) {
2434                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2435                             filter_op);
2436                 return -EINVAL;
2437         }
2438
2439         vnic0 = &bp->vnic_info[0];
2440         vnic = &bp->vnic_info[efilter->queue];
2441
2442         switch (filter_op) {
2443         case RTE_ETH_FILTER_ADD:
2444                 bnxt_match_and_validate_ether_filter(bp, efilter,
2445                                                         vnic0, vnic, &ret);
2446                 if (ret < 0)
2447                         return ret;
2448
2449                 bfilter = bnxt_get_unused_filter(bp);
2450                 if (bfilter == NULL) {
2451                         PMD_DRV_LOG(ERR,
2452                                 "Not enough resources for a new filter.\n");
2453                         return -ENOMEM;
2454                 }
2455                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2456                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2457                        RTE_ETHER_ADDR_LEN);
2458                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2459                        RTE_ETHER_ADDR_LEN);
2460                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2461                 bfilter->ethertype = efilter->ether_type;
2462                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2463
2464                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2465                 if (filter1 == NULL) {
2466                         ret = -EINVAL;
2467                         goto cleanup;
2468                 }
2469                 bfilter->enables |=
2470                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2471                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2472
2473                 bfilter->dst_id = vnic->fw_vnic_id;
2474
2475                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2476                         bfilter->flags =
2477                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2478                 }
2479
2480                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2481                 if (ret)
2482                         goto cleanup;
2483                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2484                 break;
2485         case RTE_ETH_FILTER_DELETE:
2486                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2487                                                         vnic0, vnic, &ret);
2488                 if (ret == -EEXIST) {
2489                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2490
2491                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2492                                       next);
2493                         bnxt_free_filter(bp, filter1);
2494                 } else if (ret == 0) {
2495                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2496                 }
2497                 break;
2498         default:
2499                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2500                 ret = -EINVAL;
2501                 goto error;
2502         }
2503         return ret;
2504 cleanup:
2505         bnxt_free_filter(bp, bfilter);
2506 error:
2507         return ret;
2508 }
2509
2510 static inline int
2511 parse_ntuple_filter(struct bnxt *bp,
2512                     struct rte_eth_ntuple_filter *nfilter,
2513                     struct bnxt_filter_info *bfilter)
2514 {
2515         uint32_t en = 0;
2516
2517         if (nfilter->queue >= bp->rx_nr_rings) {
2518                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2519                 return -EINVAL;
2520         }
2521
2522         switch (nfilter->dst_port_mask) {
2523         case UINT16_MAX:
2524                 bfilter->dst_port_mask = -1;
2525                 bfilter->dst_port = nfilter->dst_port;
2526                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2527                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2528                 break;
2529         default:
2530                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2531                 return -EINVAL;
2532         }
2533
2534         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2535         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2536
2537         switch (nfilter->proto_mask) {
2538         case UINT8_MAX:
2539                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2540                         bfilter->ip_protocol = 17;
2541                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2542                         bfilter->ip_protocol = 6;
2543                 else
2544                         return -EINVAL;
2545                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2546                 break;
2547         default:
2548                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2549                 return -EINVAL;
2550         }
2551
2552         switch (nfilter->dst_ip_mask) {
2553         case UINT32_MAX:
2554                 bfilter->dst_ipaddr_mask[0] = -1;
2555                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2556                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2557                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2558                 break;
2559         default:
2560                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2561                 return -EINVAL;
2562         }
2563
2564         switch (nfilter->src_ip_mask) {
2565         case UINT32_MAX:
2566                 bfilter->src_ipaddr_mask[0] = -1;
2567                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2568                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2569                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2570                 break;
2571         default:
2572                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2573                 return -EINVAL;
2574         }
2575
2576         switch (nfilter->src_port_mask) {
2577         case UINT16_MAX:
2578                 bfilter->src_port_mask = -1;
2579                 bfilter->src_port = nfilter->src_port;
2580                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2581                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2582                 break;
2583         default:
2584                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2585                 return -EINVAL;
2586         }
2587
2588         bfilter->enables = en;
2589         return 0;
2590 }
2591
2592 static struct bnxt_filter_info*
2593 bnxt_match_ntuple_filter(struct bnxt *bp,
2594                          struct bnxt_filter_info *bfilter,
2595                          struct bnxt_vnic_info **mvnic)
2596 {
2597         struct bnxt_filter_info *mfilter = NULL;
2598         int i;
2599
2600         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2601                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2602                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2603                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2604                             bfilter->src_ipaddr_mask[0] ==
2605                             mfilter->src_ipaddr_mask[0] &&
2606                             bfilter->src_port == mfilter->src_port &&
2607                             bfilter->src_port_mask == mfilter->src_port_mask &&
2608                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2609                             bfilter->dst_ipaddr_mask[0] ==
2610                             mfilter->dst_ipaddr_mask[0] &&
2611                             bfilter->dst_port == mfilter->dst_port &&
2612                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2613                             bfilter->flags == mfilter->flags &&
2614                             bfilter->enables == mfilter->enables) {
2615                                 if (mvnic)
2616                                         *mvnic = vnic;
2617                                 return mfilter;
2618                         }
2619                 }
2620         }
2621         return NULL;
2622 }
2623
2624 static int
2625 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2626                        struct rte_eth_ntuple_filter *nfilter,
2627                        enum rte_filter_op filter_op)
2628 {
2629         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2630         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2631         int ret;
2632
2633         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2634                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2635                 return -EINVAL;
2636         }
2637
2638         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2639                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2640                 return -EINVAL;
2641         }
2642
2643         bfilter = bnxt_get_unused_filter(bp);
2644         if (bfilter == NULL) {
2645                 PMD_DRV_LOG(ERR,
2646                         "Not enough resources for a new filter.\n");
2647                 return -ENOMEM;
2648         }
2649         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2650         if (ret < 0)
2651                 goto free_filter;
2652
2653         vnic = &bp->vnic_info[nfilter->queue];
2654         vnic0 = &bp->vnic_info[0];
2655         filter1 = STAILQ_FIRST(&vnic0->filter);
2656         if (filter1 == NULL) {
2657                 ret = -EINVAL;
2658                 goto free_filter;
2659         }
2660
2661         bfilter->dst_id = vnic->fw_vnic_id;
2662         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2663         bfilter->enables |=
2664                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2665         bfilter->ethertype = 0x800;
2666         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2667
2668         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2669
2670         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2671             bfilter->dst_id == mfilter->dst_id) {
2672                 PMD_DRV_LOG(ERR, "filter exists.\n");
2673                 ret = -EEXIST;
2674                 goto free_filter;
2675         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2676                    bfilter->dst_id != mfilter->dst_id) {
2677                 mfilter->dst_id = vnic->fw_vnic_id;
2678                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2679                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2680                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2681                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2682                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2683                 goto free_filter;
2684         }
2685         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2686                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2687                 ret = -ENOENT;
2688                 goto free_filter;
2689         }
2690
2691         if (filter_op == RTE_ETH_FILTER_ADD) {
2692                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2693                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2694                 if (ret)
2695                         goto free_filter;
2696                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2697         } else {
2698                 if (mfilter == NULL) {
2699                         /* This should not happen. But for Coverity! */
2700                         ret = -ENOENT;
2701                         goto free_filter;
2702                 }
2703                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2704
2705                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2706                 bnxt_free_filter(bp, mfilter);
2707                 mfilter->fw_l2_filter_id = -1;
2708                 bnxt_free_filter(bp, bfilter);
2709                 bfilter->fw_l2_filter_id = -1;
2710         }
2711
2712         return 0;
2713 free_filter:
2714         bfilter->fw_l2_filter_id = -1;
2715         bnxt_free_filter(bp, bfilter);
2716         return ret;
2717 }
2718
2719 static int
2720 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2721                         enum rte_filter_op filter_op,
2722                         void *arg)
2723 {
2724         struct bnxt *bp = dev->data->dev_private;
2725         int ret;
2726
2727         if (filter_op == RTE_ETH_FILTER_NOP)
2728                 return 0;
2729
2730         if (arg == NULL) {
2731                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2732                             filter_op);
2733                 return -EINVAL;
2734         }
2735
2736         switch (filter_op) {
2737         case RTE_ETH_FILTER_ADD:
2738                 ret = bnxt_cfg_ntuple_filter(bp,
2739                         (struct rte_eth_ntuple_filter *)arg,
2740                         filter_op);
2741                 break;
2742         case RTE_ETH_FILTER_DELETE:
2743                 ret = bnxt_cfg_ntuple_filter(bp,
2744                         (struct rte_eth_ntuple_filter *)arg,
2745                         filter_op);
2746                 break;
2747         default:
2748                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2749                 ret = -EINVAL;
2750                 break;
2751         }
2752         return ret;
2753 }
2754
2755 static int
2756 bnxt_parse_fdir_filter(struct bnxt *bp,
2757                        struct rte_eth_fdir_filter *fdir,
2758                        struct bnxt_filter_info *filter)
2759 {
2760         enum rte_fdir_mode fdir_mode =
2761                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2762         struct bnxt_vnic_info *vnic0, *vnic;
2763         struct bnxt_filter_info *filter1;
2764         uint32_t en = 0;
2765         int i;
2766
2767         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2768                 return -EINVAL;
2769
2770         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2771         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2772
2773         switch (fdir->input.flow_type) {
2774         case RTE_ETH_FLOW_IPV4:
2775         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2776                 /* FALLTHROUGH */
2777                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2778                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2779                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2780                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2781                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2782                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2783                 filter->ip_addr_type =
2784                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2785                 filter->src_ipaddr_mask[0] = 0xffffffff;
2786                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2787                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2788                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2789                 filter->ethertype = 0x800;
2790                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2791                 break;
2792         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2793                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2794                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2795                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2796                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2797                 filter->dst_port_mask = 0xffff;
2798                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2799                 filter->src_port_mask = 0xffff;
2800                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2801                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2802                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2803                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2804                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2805                 filter->ip_protocol = 6;
2806                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2807                 filter->ip_addr_type =
2808                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2809                 filter->src_ipaddr_mask[0] = 0xffffffff;
2810                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2811                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2812                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2813                 filter->ethertype = 0x800;
2814                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2815                 break;
2816         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2817                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2818                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2819                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2820                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2821                 filter->dst_port_mask = 0xffff;
2822                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2823                 filter->src_port_mask = 0xffff;
2824                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2825                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2826                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2827                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2828                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2829                 filter->ip_protocol = 17;
2830                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2831                 filter->ip_addr_type =
2832                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2833                 filter->src_ipaddr_mask[0] = 0xffffffff;
2834                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2835                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2836                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2837                 filter->ethertype = 0x800;
2838                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2839                 break;
2840         case RTE_ETH_FLOW_IPV6:
2841         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2842                 /* FALLTHROUGH */
2843                 filter->ip_addr_type =
2844                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2845                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2846                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2847                 rte_memcpy(filter->src_ipaddr,
2848                            fdir->input.flow.ipv6_flow.src_ip, 16);
2849                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2850                 rte_memcpy(filter->dst_ipaddr,
2851                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2852                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2853                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2854                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2855                 memset(filter->src_ipaddr_mask, 0xff, 16);
2856                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2857                 filter->ethertype = 0x86dd;
2858                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2859                 break;
2860         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2861                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2862                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2863                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2864                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2865                 filter->dst_port_mask = 0xffff;
2866                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2867                 filter->src_port_mask = 0xffff;
2868                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2869                 filter->ip_addr_type =
2870                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2871                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2872                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2873                 rte_memcpy(filter->src_ipaddr,
2874                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2875                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2876                 rte_memcpy(filter->dst_ipaddr,
2877                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2878                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2879                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2880                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2881                 memset(filter->src_ipaddr_mask, 0xff, 16);
2882                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2883                 filter->ethertype = 0x86dd;
2884                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2885                 break;
2886         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2887                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2888                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2889                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2890                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2891                 filter->dst_port_mask = 0xffff;
2892                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2893                 filter->src_port_mask = 0xffff;
2894                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2895                 filter->ip_addr_type =
2896                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2897                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2898                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2899                 rte_memcpy(filter->src_ipaddr,
2900                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2901                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2902                 rte_memcpy(filter->dst_ipaddr,
2903                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2904                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2905                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2906                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2907                 memset(filter->src_ipaddr_mask, 0xff, 16);
2908                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2909                 filter->ethertype = 0x86dd;
2910                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2911                 break;
2912         case RTE_ETH_FLOW_L2_PAYLOAD:
2913                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2914                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2915                 break;
2916         case RTE_ETH_FLOW_VXLAN:
2917                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2918                         return -EINVAL;
2919                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2920                 filter->tunnel_type =
2921                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2922                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2923                 break;
2924         case RTE_ETH_FLOW_NVGRE:
2925                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2926                         return -EINVAL;
2927                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2928                 filter->tunnel_type =
2929                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2930                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2931                 break;
2932         case RTE_ETH_FLOW_UNKNOWN:
2933         case RTE_ETH_FLOW_RAW:
2934         case RTE_ETH_FLOW_FRAG_IPV4:
2935         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2936         case RTE_ETH_FLOW_FRAG_IPV6:
2937         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2938         case RTE_ETH_FLOW_IPV6_EX:
2939         case RTE_ETH_FLOW_IPV6_TCP_EX:
2940         case RTE_ETH_FLOW_IPV6_UDP_EX:
2941         case RTE_ETH_FLOW_GENEVE:
2942                 /* FALLTHROUGH */
2943         default:
2944                 return -EINVAL;
2945         }
2946
2947         vnic0 = &bp->vnic_info[0];
2948         vnic = &bp->vnic_info[fdir->action.rx_queue];
2949         if (vnic == NULL) {
2950                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2951                 return -EINVAL;
2952         }
2953
2954         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2955                 rte_memcpy(filter->dst_macaddr,
2956                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2957                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2958         }
2959
2960         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2961                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2962                 filter1 = STAILQ_FIRST(&vnic0->filter);
2963                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2964         } else {
2965                 filter->dst_id = vnic->fw_vnic_id;
2966                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2967                         if (filter->dst_macaddr[i] == 0x00)
2968                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2969                         else
2970                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2971         }
2972
2973         if (filter1 == NULL)
2974                 return -EINVAL;
2975
2976         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2977         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2978
2979         filter->enables = en;
2980
2981         return 0;
2982 }
2983
2984 static struct bnxt_filter_info *
2985 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2986                 struct bnxt_vnic_info **mvnic)
2987 {
2988         struct bnxt_filter_info *mf = NULL;
2989         int i;
2990
2991         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2992                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2993
2994                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2995                         if (mf->filter_type == nf->filter_type &&
2996                             mf->flags == nf->flags &&
2997                             mf->src_port == nf->src_port &&
2998                             mf->src_port_mask == nf->src_port_mask &&
2999                             mf->dst_port == nf->dst_port &&
3000                             mf->dst_port_mask == nf->dst_port_mask &&
3001                             mf->ip_protocol == nf->ip_protocol &&
3002                             mf->ip_addr_type == nf->ip_addr_type &&
3003                             mf->ethertype == nf->ethertype &&
3004                             mf->vni == nf->vni &&
3005                             mf->tunnel_type == nf->tunnel_type &&
3006                             mf->l2_ovlan == nf->l2_ovlan &&
3007                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3008                             mf->l2_ivlan == nf->l2_ivlan &&
3009                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3010                             !memcmp(mf->l2_addr, nf->l2_addr,
3011                                     RTE_ETHER_ADDR_LEN) &&
3012                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3013                                     RTE_ETHER_ADDR_LEN) &&
3014                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3015                                     RTE_ETHER_ADDR_LEN) &&
3016                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3017                                     RTE_ETHER_ADDR_LEN) &&
3018                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3019                                     sizeof(nf->src_ipaddr)) &&
3020                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3021                                     sizeof(nf->src_ipaddr_mask)) &&
3022                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3023                                     sizeof(nf->dst_ipaddr)) &&
3024                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3025                                     sizeof(nf->dst_ipaddr_mask))) {
3026                                 if (mvnic)
3027                                         *mvnic = vnic;
3028                                 return mf;
3029                         }
3030                 }
3031         }
3032         return NULL;
3033 }
3034
3035 static int
3036 bnxt_fdir_filter(struct rte_eth_dev *dev,
3037                  enum rte_filter_op filter_op,
3038                  void *arg)
3039 {
3040         struct bnxt *bp = dev->data->dev_private;
3041         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3042         struct bnxt_filter_info *filter, *match;
3043         struct bnxt_vnic_info *vnic, *mvnic;
3044         int ret = 0, i;
3045
3046         if (filter_op == RTE_ETH_FILTER_NOP)
3047                 return 0;
3048
3049         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3050                 return -EINVAL;
3051
3052         switch (filter_op) {
3053         case RTE_ETH_FILTER_ADD:
3054         case RTE_ETH_FILTER_DELETE:
3055                 /* FALLTHROUGH */
3056                 filter = bnxt_get_unused_filter(bp);
3057                 if (filter == NULL) {
3058                         PMD_DRV_LOG(ERR,
3059                                 "Not enough resources for a new flow.\n");
3060                         return -ENOMEM;
3061                 }
3062
3063                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3064                 if (ret != 0)
3065                         goto free_filter;
3066                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3067
3068                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3069                         vnic = &bp->vnic_info[0];
3070                 else
3071                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3072
3073                 match = bnxt_match_fdir(bp, filter, &mvnic);
3074                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3075                         if (match->dst_id == vnic->fw_vnic_id) {
3076                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3077                                 ret = -EEXIST;
3078                                 goto free_filter;
3079                         } else {
3080                                 match->dst_id = vnic->fw_vnic_id;
3081                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3082                                                                   match->dst_id,
3083                                                                   match);
3084                                 STAILQ_REMOVE(&mvnic->filter, match,
3085                                               bnxt_filter_info, next);
3086                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3087                                 PMD_DRV_LOG(ERR,
3088                                         "Filter with matching pattern exist\n");
3089                                 PMD_DRV_LOG(ERR,
3090                                         "Updated it to new destination q\n");
3091                                 goto free_filter;
3092                         }
3093                 }
3094                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3095                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3096                         ret = -ENOENT;
3097                         goto free_filter;
3098                 }
3099
3100                 if (filter_op == RTE_ETH_FILTER_ADD) {
3101                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3102                                                           filter->dst_id,
3103                                                           filter);
3104                         if (ret)
3105                                 goto free_filter;
3106                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3107                 } else {
3108                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3109                         STAILQ_REMOVE(&vnic->filter, match,
3110                                       bnxt_filter_info, next);
3111                         bnxt_free_filter(bp, match);
3112                         filter->fw_l2_filter_id = -1;
3113                         bnxt_free_filter(bp, filter);
3114                 }
3115                 break;
3116         case RTE_ETH_FILTER_FLUSH:
3117                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3118                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3119
3120                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3121                                 if (filter->filter_type ==
3122                                     HWRM_CFA_NTUPLE_FILTER) {
3123                                         ret =
3124                                         bnxt_hwrm_clear_ntuple_filter(bp,
3125                                                                       filter);
3126                                         STAILQ_REMOVE(&vnic->filter, filter,
3127                                                       bnxt_filter_info, next);
3128                                 }
3129                         }
3130                 }
3131                 return ret;
3132         case RTE_ETH_FILTER_UPDATE:
3133         case RTE_ETH_FILTER_STATS:
3134         case RTE_ETH_FILTER_INFO:
3135                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3136                 break;
3137         default:
3138                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3139                 ret = -EINVAL;
3140                 break;
3141         }
3142         return ret;
3143
3144 free_filter:
3145         filter->fw_l2_filter_id = -1;
3146         bnxt_free_filter(bp, filter);
3147         return ret;
3148 }
3149
3150 static int
3151 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3152                     enum rte_filter_type filter_type,
3153                     enum rte_filter_op filter_op, void *arg)
3154 {
3155         int ret = 0;
3156
3157         ret = is_bnxt_in_error(dev->data->dev_private);
3158         if (ret)
3159                 return ret;
3160
3161         switch (filter_type) {
3162         case RTE_ETH_FILTER_TUNNEL:
3163                 PMD_DRV_LOG(ERR,
3164                         "filter type: %d: To be implemented\n", filter_type);
3165                 break;
3166         case RTE_ETH_FILTER_FDIR:
3167                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3168                 break;
3169         case RTE_ETH_FILTER_NTUPLE:
3170                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3171                 break;
3172         case RTE_ETH_FILTER_ETHERTYPE:
3173                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3174                 break;
3175         case RTE_ETH_FILTER_GENERIC:
3176                 if (filter_op != RTE_ETH_FILTER_GET)
3177                         return -EINVAL;
3178                 *(const void **)arg = &bnxt_flow_ops;
3179                 break;
3180         default:
3181                 PMD_DRV_LOG(ERR,
3182                         "Filter type (%d) not supported", filter_type);
3183                 ret = -EINVAL;
3184                 break;
3185         }
3186         return ret;
3187 }
3188
3189 static const uint32_t *
3190 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3191 {
3192         static const uint32_t ptypes[] = {
3193                 RTE_PTYPE_L2_ETHER_VLAN,
3194                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3195                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3196                 RTE_PTYPE_L4_ICMP,
3197                 RTE_PTYPE_L4_TCP,
3198                 RTE_PTYPE_L4_UDP,
3199                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3200                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3201                 RTE_PTYPE_INNER_L4_ICMP,
3202                 RTE_PTYPE_INNER_L4_TCP,
3203                 RTE_PTYPE_INNER_L4_UDP,
3204                 RTE_PTYPE_UNKNOWN
3205         };
3206
3207         if (!dev->rx_pkt_burst)
3208                 return NULL;
3209
3210         return ptypes;
3211 }
3212
3213 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3214                          int reg_win)
3215 {
3216         uint32_t reg_base = *reg_arr & 0xfffff000;
3217         uint32_t win_off;
3218         int i;
3219
3220         for (i = 0; i < count; i++) {
3221                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3222                         return -ERANGE;
3223         }
3224         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3225         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3226         return 0;
3227 }
3228
3229 static int bnxt_map_ptp_regs(struct bnxt *bp)
3230 {
3231         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3232         uint32_t *reg_arr;
3233         int rc, i;
3234
3235         reg_arr = ptp->rx_regs;
3236         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3237         if (rc)
3238                 return rc;
3239
3240         reg_arr = ptp->tx_regs;
3241         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3242         if (rc)
3243                 return rc;
3244
3245         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3246                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3247
3248         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3249                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3250
3251         return 0;
3252 }
3253
3254 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3255 {
3256         rte_write32(0, (uint8_t *)bp->bar0 +
3257                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3258         rte_write32(0, (uint8_t *)bp->bar0 +
3259                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3260 }
3261
3262 static uint64_t bnxt_cc_read(struct bnxt *bp)
3263 {
3264         uint64_t ns;
3265
3266         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3267                               BNXT_GRCPF_REG_SYNC_TIME));
3268         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3269                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3270         return ns;
3271 }
3272
3273 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3274 {
3275         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3276         uint32_t fifo;
3277
3278         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3279                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3280         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3281                 return -EAGAIN;
3282
3283         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3284                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3285         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3286                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3287         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3288                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3289
3290         return 0;
3291 }
3292
3293 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3294 {
3295         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3296         struct bnxt_pf_info *pf = &bp->pf;
3297         uint16_t port_id;
3298         uint32_t fifo;
3299
3300         if (!ptp)
3301                 return -ENODEV;
3302
3303         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3304                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3305         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3306                 return -EAGAIN;
3307
3308         port_id = pf->port_id;
3309         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3310                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3311
3312         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3313                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3314         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3315 /*              bnxt_clr_rx_ts(bp);       TBD  */
3316                 return -EBUSY;
3317         }
3318
3319         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3320                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3321         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3322                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3323
3324         return 0;
3325 }
3326
3327 static int
3328 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3329 {
3330         uint64_t ns;
3331         struct bnxt *bp = dev->data->dev_private;
3332         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3333
3334         if (!ptp)
3335                 return 0;
3336
3337         ns = rte_timespec_to_ns(ts);
3338         /* Set the timecounters to a new value. */
3339         ptp->tc.nsec = ns;
3340
3341         return 0;
3342 }
3343
3344 static int
3345 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3346 {
3347         struct bnxt *bp = dev->data->dev_private;
3348         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3349         uint64_t ns, systime_cycles = 0;
3350         int rc = 0;
3351
3352         if (!ptp)
3353                 return 0;
3354
3355         if (BNXT_CHIP_THOR(bp))
3356                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3357                                              &systime_cycles);
3358         else
3359                 systime_cycles = bnxt_cc_read(bp);
3360
3361         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3362         *ts = rte_ns_to_timespec(ns);
3363
3364         return rc;
3365 }
3366 static int
3367 bnxt_timesync_enable(struct rte_eth_dev *dev)
3368 {
3369         struct bnxt *bp = dev->data->dev_private;
3370         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3371         uint32_t shift = 0;
3372         int rc;
3373
3374         if (!ptp)
3375                 return 0;
3376
3377         ptp->rx_filter = 1;
3378         ptp->tx_tstamp_en = 1;
3379         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3380
3381         rc = bnxt_hwrm_ptp_cfg(bp);
3382         if (rc)
3383                 return rc;
3384
3385         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3386         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3387         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3388
3389         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3390         ptp->tc.cc_shift = shift;
3391         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3392
3393         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3394         ptp->rx_tstamp_tc.cc_shift = shift;
3395         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3396
3397         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3398         ptp->tx_tstamp_tc.cc_shift = shift;
3399         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3400
3401         if (!BNXT_CHIP_THOR(bp))
3402                 bnxt_map_ptp_regs(bp);
3403
3404         return 0;
3405 }
3406
3407 static int
3408 bnxt_timesync_disable(struct rte_eth_dev *dev)
3409 {
3410         struct bnxt *bp = dev->data->dev_private;
3411         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3412
3413         if (!ptp)
3414                 return 0;
3415
3416         ptp->rx_filter = 0;
3417         ptp->tx_tstamp_en = 0;
3418         ptp->rxctl = 0;
3419
3420         bnxt_hwrm_ptp_cfg(bp);
3421
3422         if (!BNXT_CHIP_THOR(bp))
3423                 bnxt_unmap_ptp_regs(bp);
3424
3425         return 0;
3426 }
3427
3428 static int
3429 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3430                                  struct timespec *timestamp,
3431                                  uint32_t flags __rte_unused)
3432 {
3433         struct bnxt *bp = dev->data->dev_private;
3434         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3435         uint64_t rx_tstamp_cycles = 0;
3436         uint64_t ns;
3437
3438         if (!ptp)
3439                 return 0;
3440
3441         if (BNXT_CHIP_THOR(bp))
3442                 rx_tstamp_cycles = ptp->rx_timestamp;
3443         else
3444                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3445
3446         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3447         *timestamp = rte_ns_to_timespec(ns);
3448         return  0;
3449 }
3450
3451 static int
3452 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3453                                  struct timespec *timestamp)
3454 {
3455         struct bnxt *bp = dev->data->dev_private;
3456         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3457         uint64_t tx_tstamp_cycles = 0;
3458         uint64_t ns;
3459         int rc = 0;
3460
3461         if (!ptp)
3462                 return 0;
3463
3464         if (BNXT_CHIP_THOR(bp))
3465                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3466                                              &tx_tstamp_cycles);
3467         else
3468                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3469
3470         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3471         *timestamp = rte_ns_to_timespec(ns);
3472
3473         return rc;
3474 }
3475
3476 static int
3477 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3478 {
3479         struct bnxt *bp = dev->data->dev_private;
3480         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3481
3482         if (!ptp)
3483                 return 0;
3484
3485         ptp->tc.nsec += delta;
3486
3487         return 0;
3488 }
3489
3490 static int
3491 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3492 {
3493         struct bnxt *bp = dev->data->dev_private;
3494         int rc;
3495         uint32_t dir_entries;
3496         uint32_t entry_length;
3497
3498         rc = is_bnxt_in_error(bp);
3499         if (rc)
3500                 return rc;
3501
3502         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3503                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3504                 bp->pdev->addr.devid, bp->pdev->addr.function);
3505
3506         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3507         if (rc != 0)
3508                 return rc;
3509
3510         return dir_entries * entry_length;
3511 }
3512
3513 static int
3514 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3515                 struct rte_dev_eeprom_info *in_eeprom)
3516 {
3517         struct bnxt *bp = dev->data->dev_private;
3518         uint32_t index;
3519         uint32_t offset;
3520         int rc;
3521
3522         rc = is_bnxt_in_error(bp);
3523         if (rc)
3524                 return rc;
3525
3526         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3527                 "len = %d\n", bp->pdev->addr.domain,
3528                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3529                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3530
3531         if (in_eeprom->offset == 0) /* special offset value to get directory */
3532                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3533                                                 in_eeprom->data);
3534
3535         index = in_eeprom->offset >> 24;
3536         offset = in_eeprom->offset & 0xffffff;
3537
3538         if (index != 0)
3539                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3540                                            in_eeprom->length, in_eeprom->data);
3541
3542         return 0;
3543 }
3544
3545 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3546 {
3547         switch (dir_type) {
3548         case BNX_DIR_TYPE_CHIMP_PATCH:
3549         case BNX_DIR_TYPE_BOOTCODE:
3550         case BNX_DIR_TYPE_BOOTCODE_2:
3551         case BNX_DIR_TYPE_APE_FW:
3552         case BNX_DIR_TYPE_APE_PATCH:
3553         case BNX_DIR_TYPE_KONG_FW:
3554         case BNX_DIR_TYPE_KONG_PATCH:
3555         case BNX_DIR_TYPE_BONO_FW:
3556         case BNX_DIR_TYPE_BONO_PATCH:
3557                 /* FALLTHROUGH */
3558                 return true;
3559         }
3560
3561         return false;
3562 }
3563
3564 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3565 {
3566         switch (dir_type) {
3567         case BNX_DIR_TYPE_AVS:
3568         case BNX_DIR_TYPE_EXP_ROM_MBA:
3569         case BNX_DIR_TYPE_PCIE:
3570         case BNX_DIR_TYPE_TSCF_UCODE:
3571         case BNX_DIR_TYPE_EXT_PHY:
3572         case BNX_DIR_TYPE_CCM:
3573         case BNX_DIR_TYPE_ISCSI_BOOT:
3574         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3575         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3576                 /* FALLTHROUGH */
3577                 return true;
3578         }
3579
3580         return false;
3581 }
3582
3583 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3584 {
3585         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3586                 bnxt_dir_type_is_other_exec_format(dir_type);
3587 }
3588
3589 static int
3590 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3591                 struct rte_dev_eeprom_info *in_eeprom)
3592 {
3593         struct bnxt *bp = dev->data->dev_private;
3594         uint8_t index, dir_op;
3595         uint16_t type, ext, ordinal, attr;
3596         int rc;
3597
3598         rc = is_bnxt_in_error(bp);
3599         if (rc)
3600                 return rc;
3601
3602         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3603                 "len = %d\n", bp->pdev->addr.domain,
3604                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3605                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3606
3607         if (!BNXT_PF(bp)) {
3608                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3609                 return -EINVAL;
3610         }
3611
3612         type = in_eeprom->magic >> 16;
3613
3614         if (type == 0xffff) { /* special value for directory operations */
3615                 index = in_eeprom->magic & 0xff;
3616                 dir_op = in_eeprom->magic >> 8;
3617                 if (index == 0)
3618                         return -EINVAL;
3619                 switch (dir_op) {
3620                 case 0x0e: /* erase */
3621                         if (in_eeprom->offset != ~in_eeprom->magic)
3622                                 return -EINVAL;
3623                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3624                 default:
3625                         return -EINVAL;
3626                 }
3627         }
3628
3629         /* Create or re-write an NVM item: */
3630         if (bnxt_dir_type_is_executable(type) == true)
3631                 return -EOPNOTSUPP;
3632         ext = in_eeprom->magic & 0xffff;
3633         ordinal = in_eeprom->offset >> 16;
3634         attr = in_eeprom->offset & 0xffff;
3635
3636         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3637                                      in_eeprom->data, in_eeprom->length);
3638 }
3639
3640 /*
3641  * Initialization
3642  */
3643
3644 static const struct eth_dev_ops bnxt_dev_ops = {
3645         .dev_infos_get = bnxt_dev_info_get_op,
3646         .dev_close = bnxt_dev_close_op,
3647         .dev_configure = bnxt_dev_configure_op,
3648         .dev_start = bnxt_dev_start_op,
3649         .dev_stop = bnxt_dev_stop_op,
3650         .dev_set_link_up = bnxt_dev_set_link_up_op,
3651         .dev_set_link_down = bnxt_dev_set_link_down_op,
3652         .stats_get = bnxt_stats_get_op,
3653         .stats_reset = bnxt_stats_reset_op,
3654         .rx_queue_setup = bnxt_rx_queue_setup_op,
3655         .rx_queue_release = bnxt_rx_queue_release_op,
3656         .tx_queue_setup = bnxt_tx_queue_setup_op,
3657         .tx_queue_release = bnxt_tx_queue_release_op,
3658         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3659         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3660         .reta_update = bnxt_reta_update_op,
3661         .reta_query = bnxt_reta_query_op,
3662         .rss_hash_update = bnxt_rss_hash_update_op,
3663         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3664         .link_update = bnxt_link_update_op,
3665         .promiscuous_enable = bnxt_promiscuous_enable_op,
3666         .promiscuous_disable = bnxt_promiscuous_disable_op,
3667         .allmulticast_enable = bnxt_allmulticast_enable_op,
3668         .allmulticast_disable = bnxt_allmulticast_disable_op,
3669         .mac_addr_add = bnxt_mac_addr_add_op,
3670         .mac_addr_remove = bnxt_mac_addr_remove_op,
3671         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3672         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3673         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3674         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3675         .vlan_filter_set = bnxt_vlan_filter_set_op,
3676         .vlan_offload_set = bnxt_vlan_offload_set_op,
3677         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3678         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3679         .mtu_set = bnxt_mtu_set_op,
3680         .mac_addr_set = bnxt_set_default_mac_addr_op,
3681         .xstats_get = bnxt_dev_xstats_get_op,
3682         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3683         .xstats_reset = bnxt_dev_xstats_reset_op,
3684         .fw_version_get = bnxt_fw_version_get,
3685         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3686         .rxq_info_get = bnxt_rxq_info_get_op,
3687         .txq_info_get = bnxt_txq_info_get_op,
3688         .dev_led_on = bnxt_dev_led_on_op,
3689         .dev_led_off = bnxt_dev_led_off_op,
3690         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3691         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3692         .rx_queue_count = bnxt_rx_queue_count_op,
3693         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3694         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3695         .rx_queue_start = bnxt_rx_queue_start,
3696         .rx_queue_stop = bnxt_rx_queue_stop,
3697         .tx_queue_start = bnxt_tx_queue_start,
3698         .tx_queue_stop = bnxt_tx_queue_stop,
3699         .filter_ctrl = bnxt_filter_ctrl_op,
3700         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3701         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3702         .get_eeprom           = bnxt_get_eeprom_op,
3703         .set_eeprom           = bnxt_set_eeprom_op,
3704         .timesync_enable      = bnxt_timesync_enable,
3705         .timesync_disable     = bnxt_timesync_disable,
3706         .timesync_read_time   = bnxt_timesync_read_time,
3707         .timesync_write_time   = bnxt_timesync_write_time,
3708         .timesync_adjust_time = bnxt_timesync_adjust_time,
3709         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3710         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3711 };
3712
3713 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3714 {
3715         uint32_t offset;
3716
3717         /* Only pre-map the reset GRC registers using window 3 */
3718         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3719                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3720
3721         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3722
3723         return offset;
3724 }
3725
3726 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3727 {
3728         struct bnxt_error_recovery_info *info = bp->recovery_info;
3729         uint32_t reg_base = 0xffffffff;
3730         int i;
3731
3732         /* Only pre-map the monitoring GRC registers using window 2 */
3733         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3734                 uint32_t reg = info->status_regs[i];
3735
3736                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3737                         continue;
3738
3739                 if (reg_base == 0xffffffff)
3740                         reg_base = reg & 0xfffff000;
3741                 if ((reg & 0xfffff000) != reg_base)
3742                         return -ERANGE;
3743
3744                 /* Use mask 0xffc as the Lower 2 bits indicates
3745                  * address space location
3746                  */
3747                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3748                                                 (reg & 0xffc);
3749         }
3750
3751         if (reg_base == 0xffffffff)
3752                 return 0;
3753
3754         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3755                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3756
3757         return 0;
3758 }
3759
3760 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3761 {
3762         struct bnxt_error_recovery_info *info = bp->recovery_info;
3763         uint32_t delay = info->delay_after_reset[index];
3764         uint32_t val = info->reset_reg_val[index];
3765         uint32_t reg = info->reset_reg[index];
3766         uint32_t type, offset;
3767
3768         type = BNXT_FW_STATUS_REG_TYPE(reg);
3769         offset = BNXT_FW_STATUS_REG_OFF(reg);
3770
3771         switch (type) {
3772         case BNXT_FW_STATUS_REG_TYPE_CFG:
3773                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3774                 break;
3775         case BNXT_FW_STATUS_REG_TYPE_GRC:
3776                 offset = bnxt_map_reset_regs(bp, offset);
3777                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3778                 break;
3779         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3780                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3781                 break;
3782         }
3783         /* wait on a specific interval of time until core reset is complete */
3784         if (delay)
3785                 rte_delay_ms(delay);
3786 }
3787
3788 static void bnxt_dev_cleanup(struct bnxt *bp)
3789 {
3790         bnxt_set_hwrm_link_config(bp, false);
3791         bp->link_info.link_up = 0;
3792         if (bp->dev_stopped == 0)
3793                 bnxt_dev_stop_op(bp->eth_dev);
3794
3795         bnxt_uninit_resources(bp, true);
3796 }
3797
3798 static int bnxt_restore_filters(struct bnxt *bp)
3799 {
3800         struct rte_eth_dev *dev = bp->eth_dev;
3801         int ret = 0;
3802
3803         if (dev->data->all_multicast)
3804                 ret = bnxt_allmulticast_enable_op(dev);
3805         if (dev->data->promiscuous)
3806                 ret = bnxt_promiscuous_enable_op(dev);
3807
3808         /* TODO restore other filters as well */
3809         return ret;
3810 }
3811
3812 static void bnxt_dev_recover(void *arg)
3813 {
3814         struct bnxt *bp = arg;
3815         int timeout = bp->fw_reset_max_msecs;
3816         int rc = 0;
3817
3818         /* Clear Error flag so that device re-init should happen */
3819         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3820
3821         do {
3822                 rc = bnxt_hwrm_ver_get(bp);
3823                 if (rc == 0)
3824                         break;
3825                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3826                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3827         } while (rc && timeout);
3828
3829         if (rc) {
3830                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3831                 goto err;
3832         }
3833
3834         rc = bnxt_init_resources(bp, true);
3835         if (rc) {
3836                 PMD_DRV_LOG(ERR,
3837                             "Failed to initialize resources after reset\n");
3838                 goto err;
3839         }
3840         /* clear reset flag as the device is initialized now */
3841         bp->flags &= ~BNXT_FLAG_FW_RESET;
3842
3843         rc = bnxt_dev_start_op(bp->eth_dev);
3844         if (rc) {
3845                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3846                 goto err;
3847         }
3848
3849         rc = bnxt_restore_filters(bp);
3850         if (rc)
3851                 goto err;
3852
3853         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3854         return;
3855 err:
3856         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3857         bnxt_uninit_resources(bp, false);
3858         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3859 }
3860
3861 void bnxt_dev_reset_and_resume(void *arg)
3862 {
3863         struct bnxt *bp = arg;
3864         int rc;
3865
3866         bnxt_dev_cleanup(bp);
3867
3868         bnxt_wait_for_device_shutdown(bp);
3869
3870         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3871                                bnxt_dev_recover, (void *)bp);
3872         if (rc)
3873                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3874 }
3875
3876 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3877 {
3878         struct bnxt_error_recovery_info *info = bp->recovery_info;
3879         uint32_t reg = info->status_regs[index];
3880         uint32_t type, offset, val = 0;
3881
3882         type = BNXT_FW_STATUS_REG_TYPE(reg);
3883         offset = BNXT_FW_STATUS_REG_OFF(reg);
3884
3885         switch (type) {
3886         case BNXT_FW_STATUS_REG_TYPE_CFG:
3887                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3888                 break;
3889         case BNXT_FW_STATUS_REG_TYPE_GRC:
3890                 offset = info->mapped_status_regs[index];
3891                 /* FALLTHROUGH */
3892         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3893                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3894                                        offset));
3895                 break;
3896         }
3897
3898         return val;
3899 }
3900
3901 static int bnxt_fw_reset_all(struct bnxt *bp)
3902 {
3903         struct bnxt_error_recovery_info *info = bp->recovery_info;
3904         uint32_t i;
3905         int rc = 0;
3906
3907         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3908                 /* Reset through master function driver */
3909                 for (i = 0; i < info->reg_array_cnt; i++)
3910                         bnxt_write_fw_reset_reg(bp, i);
3911                 /* Wait for time specified by FW after triggering reset */
3912                 rte_delay_ms(info->master_func_wait_period_after_reset);
3913         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3914                 /* Reset with the help of Kong processor */
3915                 rc = bnxt_hwrm_fw_reset(bp);
3916                 if (rc)
3917                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3918         }
3919
3920         return rc;
3921 }
3922
3923 static void bnxt_fw_reset_cb(void *arg)
3924 {
3925         struct bnxt *bp = arg;
3926         struct bnxt_error_recovery_info *info = bp->recovery_info;
3927         int rc = 0;
3928
3929         /* Only Master function can do FW reset */
3930         if (bnxt_is_master_func(bp) &&
3931             bnxt_is_recovery_enabled(bp)) {
3932                 rc = bnxt_fw_reset_all(bp);
3933                 if (rc) {
3934                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3935                         return;
3936                 }
3937         }
3938
3939         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3940          * EXCEPTION_FATAL_ASYNC event to all the functions
3941          * (including MASTER FUNC). After receiving this Async, all the active
3942          * drivers should treat this case as FW initiated recovery
3943          */
3944         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3945                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3946                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3947
3948                 /* To recover from error */
3949                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3950                                   (void *)bp);
3951         }
3952 }
3953
3954 /* Driver should poll FW heartbeat, reset_counter with the frequency
3955  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3956  * When the driver detects heartbeat stop or change in reset_counter,
3957  * it has to trigger a reset to recover from the error condition.
3958  * A “master PF” is the function who will have the privilege to
3959  * initiate the chimp reset. The master PF will be elected by the
3960  * firmware and will be notified through async message.
3961  */
3962 static void bnxt_check_fw_health(void *arg)
3963 {
3964         struct bnxt *bp = arg;
3965         struct bnxt_error_recovery_info *info = bp->recovery_info;
3966         uint32_t val = 0, wait_msec;
3967
3968         if (!info || !bnxt_is_recovery_enabled(bp) ||
3969             is_bnxt_in_error(bp))
3970                 return;
3971
3972         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3973         if (val == info->last_heart_beat)
3974                 goto reset;
3975
3976         info->last_heart_beat = val;
3977
3978         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3979         if (val != info->last_reset_counter)
3980                 goto reset;
3981
3982         info->last_reset_counter = val;
3983
3984         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3985                           bnxt_check_fw_health, (void *)bp);
3986
3987         return;
3988 reset:
3989         /* Stop DMA to/from device */
3990         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3991         bp->flags |= BNXT_FLAG_FW_RESET;
3992
3993         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3994
3995         if (bnxt_is_master_func(bp))
3996                 wait_msec = info->master_func_wait_period;
3997         else
3998                 wait_msec = info->normal_func_wait_period;
3999
4000         rte_eal_alarm_set(US_PER_MS * wait_msec,
4001                           bnxt_fw_reset_cb, (void *)bp);
4002 }
4003
4004 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4005 {
4006         uint32_t polling_freq;
4007
4008         if (!bnxt_is_recovery_enabled(bp))
4009                 return;
4010
4011         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4012                 return;
4013
4014         polling_freq = bp->recovery_info->driver_polling_freq;
4015
4016         rte_eal_alarm_set(US_PER_MS * polling_freq,
4017                           bnxt_check_fw_health, (void *)bp);
4018         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4019 }
4020
4021 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4022 {
4023         if (!bnxt_is_recovery_enabled(bp))
4024                 return;
4025
4026         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4027         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4028 }
4029
4030 static bool bnxt_vf_pciid(uint16_t id)
4031 {
4032         if (id == BROADCOM_DEV_ID_57304_VF ||
4033             id == BROADCOM_DEV_ID_57406_VF ||
4034             id == BROADCOM_DEV_ID_5731X_VF ||
4035             id == BROADCOM_DEV_ID_5741X_VF ||
4036             id == BROADCOM_DEV_ID_57414_VF ||
4037             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4038             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
4039             id == BROADCOM_DEV_ID_58802_VF ||
4040             id == BROADCOM_DEV_ID_57500_VF1 ||
4041             id == BROADCOM_DEV_ID_57500_VF2)
4042                 return true;
4043         return false;
4044 }
4045
4046 static bool bnxt_thor_device(uint16_t id)
4047 {
4048         if (id == BROADCOM_DEV_ID_57508 ||
4049             id == BROADCOM_DEV_ID_57504 ||
4050             id == BROADCOM_DEV_ID_57502 ||
4051             id == BROADCOM_DEV_ID_57508_MF1 ||
4052             id == BROADCOM_DEV_ID_57504_MF1 ||
4053             id == BROADCOM_DEV_ID_57502_MF1 ||
4054             id == BROADCOM_DEV_ID_57508_MF2 ||
4055             id == BROADCOM_DEV_ID_57504_MF2 ||
4056             id == BROADCOM_DEV_ID_57502_MF2 ||
4057             id == BROADCOM_DEV_ID_57500_VF1 ||
4058             id == BROADCOM_DEV_ID_57500_VF2)
4059                 return true;
4060
4061         return false;
4062 }
4063
4064 bool bnxt_stratus_device(struct bnxt *bp)
4065 {
4066         uint16_t id = bp->pdev->id.device_id;
4067
4068         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
4069             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4070             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
4071                 return true;
4072         return false;
4073 }
4074
4075 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4076 {
4077         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4078         struct bnxt *bp = eth_dev->data->dev_private;
4079
4080         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4081         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4082         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4083         if (!bp->bar0 || !bp->doorbell_base) {
4084                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4085                 return -ENODEV;
4086         }
4087
4088         bp->eth_dev = eth_dev;
4089         bp->pdev = pci_dev;
4090
4091         return 0;
4092 }
4093
4094 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
4095                                   struct bnxt_ctx_pg_info *ctx_pg,
4096                                   uint32_t mem_size,
4097                                   const char *suffix,
4098                                   uint16_t idx)
4099 {
4100         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4101         const struct rte_memzone *mz = NULL;
4102         char mz_name[RTE_MEMZONE_NAMESIZE];
4103         rte_iova_t mz_phys_addr;
4104         uint64_t valid_bits = 0;
4105         uint32_t sz;
4106         int i;
4107
4108         if (!mem_size)
4109                 return 0;
4110
4111         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4112                          BNXT_PAGE_SIZE;
4113         rmem->page_size = BNXT_PAGE_SIZE;
4114         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4115         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4116         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4117
4118         valid_bits = PTU_PTE_VALID;
4119
4120         if (rmem->nr_pages > 1) {
4121                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4122                          "bnxt_ctx_pg_tbl%s_%x_%d",
4123                          suffix, idx, bp->eth_dev->data->port_id);
4124                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4125                 mz = rte_memzone_lookup(mz_name);
4126                 if (!mz) {
4127                         mz = rte_memzone_reserve_aligned(mz_name,
4128                                                 rmem->nr_pages * 8,
4129                                                 SOCKET_ID_ANY,
4130                                                 RTE_MEMZONE_2MB |
4131                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4132                                                 RTE_MEMZONE_IOVA_CONTIG,
4133                                                 BNXT_PAGE_SIZE);
4134                         if (mz == NULL)
4135                                 return -ENOMEM;
4136                 }
4137
4138                 memset(mz->addr, 0, mz->len);
4139                 mz_phys_addr = mz->iova;
4140                 if ((unsigned long)mz->addr == mz_phys_addr) {
4141                         PMD_DRV_LOG(DEBUG,
4142                                     "physical address same as virtual\n");
4143                         PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4144                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
4145                         if (mz_phys_addr == RTE_BAD_IOVA) {
4146                                 PMD_DRV_LOG(ERR,
4147                                         "unable to map addr to phys memory\n");
4148                                 return -ENOMEM;
4149                         }
4150                 }
4151                 rte_mem_lock_page(((char *)mz->addr));
4152
4153                 rmem->pg_tbl = mz->addr;
4154                 rmem->pg_tbl_map = mz_phys_addr;
4155                 rmem->pg_tbl_mz = mz;
4156         }
4157
4158         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4159                  suffix, idx, bp->eth_dev->data->port_id);
4160         mz = rte_memzone_lookup(mz_name);
4161         if (!mz) {
4162                 mz = rte_memzone_reserve_aligned(mz_name,
4163                                                  mem_size,
4164                                                  SOCKET_ID_ANY,
4165                                                  RTE_MEMZONE_1GB |
4166                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4167                                                  RTE_MEMZONE_IOVA_CONTIG,
4168                                                  BNXT_PAGE_SIZE);
4169                 if (mz == NULL)
4170                         return -ENOMEM;
4171         }
4172
4173         memset(mz->addr, 0, mz->len);
4174         mz_phys_addr = mz->iova;
4175         if ((unsigned long)mz->addr == mz_phys_addr) {
4176                 PMD_DRV_LOG(DEBUG,
4177                             "Memzone physical address same as virtual.\n");
4178                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4179                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4180                         rte_mem_lock_page(((char *)mz->addr) + sz);
4181                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4182                 if (mz_phys_addr == RTE_BAD_IOVA) {
4183                         PMD_DRV_LOG(ERR,
4184                                     "unable to map addr to phys memory\n");
4185                         return -ENOMEM;
4186                 }
4187         }
4188
4189         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4190                 rte_mem_lock_page(((char *)mz->addr) + sz);
4191                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4192                 rmem->dma_arr[i] = mz_phys_addr + sz;
4193
4194                 if (rmem->nr_pages > 1) {
4195                         if (i == rmem->nr_pages - 2 &&
4196                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4197                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4198                         else if (i == rmem->nr_pages - 1 &&
4199                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4200                                 valid_bits |= PTU_PTE_LAST;
4201
4202                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4203                                                            valid_bits);
4204                 }
4205         }
4206
4207         rmem->mz = mz;
4208         if (rmem->vmem_size)
4209                 rmem->vmem = (void **)mz->addr;
4210         rmem->dma_arr[0] = mz_phys_addr;
4211         return 0;
4212 }
4213
4214 static void bnxt_free_ctx_mem(struct bnxt *bp)
4215 {
4216         int i;
4217
4218         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4219                 return;
4220
4221         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4222         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4223         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4224         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4225         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4226         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4227         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4228         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4229         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4230         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4231         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4232
4233         for (i = 0; i < BNXT_MAX_Q; i++) {
4234                 if (bp->ctx->tqm_mem[i])
4235                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4236         }
4237
4238         rte_free(bp->ctx);
4239         bp->ctx = NULL;
4240 }
4241
4242 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4243
4244 #define min_t(type, x, y) ({                    \
4245         type __min1 = (x);                      \
4246         type __min2 = (y);                      \
4247         __min1 < __min2 ? __min1 : __min2; })
4248
4249 #define max_t(type, x, y) ({                    \
4250         type __max1 = (x);                      \
4251         type __max2 = (y);                      \
4252         __max1 > __max2 ? __max1 : __max2; })
4253
4254 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4255
4256 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4257 {
4258         struct bnxt_ctx_pg_info *ctx_pg;
4259         struct bnxt_ctx_mem_info *ctx;
4260         uint32_t mem_size, ena, entries;
4261         int i, rc;
4262
4263         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4264         if (rc) {
4265                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4266                 return rc;
4267         }
4268         ctx = bp->ctx;
4269         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4270                 return 0;
4271
4272         ctx_pg = &ctx->qp_mem;
4273         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4274         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4275         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4276         if (rc)
4277                 return rc;
4278
4279         ctx_pg = &ctx->srq_mem;
4280         ctx_pg->entries = ctx->srq_max_l2_entries;
4281         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4282         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4283         if (rc)
4284                 return rc;
4285
4286         ctx_pg = &ctx->cq_mem;
4287         ctx_pg->entries = ctx->cq_max_l2_entries;
4288         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4289         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4290         if (rc)
4291                 return rc;
4292
4293         ctx_pg = &ctx->vnic_mem;
4294         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4295                 ctx->vnic_max_ring_table_entries;
4296         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4297         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4298         if (rc)
4299                 return rc;
4300
4301         ctx_pg = &ctx->stat_mem;
4302         ctx_pg->entries = ctx->stat_max_entries;
4303         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4304         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4305         if (rc)
4306                 return rc;
4307
4308         entries = ctx->qp_max_l2_entries +
4309                   ctx->vnic_max_vnic_entries +
4310                   ctx->tqm_min_entries_per_ring;
4311         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4312         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4313                           ctx->tqm_max_entries_per_ring);
4314         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4315                 ctx_pg = ctx->tqm_mem[i];
4316                 /* use min tqm entries for now. */
4317                 ctx_pg->entries = entries;
4318                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4319                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4320                 if (rc)
4321                         return rc;
4322                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4323         }
4324
4325         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4326         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4327         if (rc)
4328                 PMD_DRV_LOG(ERR,
4329                             "Failed to configure context mem: rc = %d\n", rc);
4330         else
4331                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4332
4333         return rc;
4334 }
4335
4336 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4337 {
4338         struct rte_pci_device *pci_dev = bp->pdev;
4339         char mz_name[RTE_MEMZONE_NAMESIZE];
4340         const struct rte_memzone *mz = NULL;
4341         uint32_t total_alloc_len;
4342         rte_iova_t mz_phys_addr;
4343
4344         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4345                 return 0;
4346
4347         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4348                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4349                  pci_dev->addr.bus, pci_dev->addr.devid,
4350                  pci_dev->addr.function, "rx_port_stats");
4351         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4352         mz = rte_memzone_lookup(mz_name);
4353         total_alloc_len =
4354                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4355                                        sizeof(struct rx_port_stats_ext) + 512);
4356         if (!mz) {
4357                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4358                                          SOCKET_ID_ANY,
4359                                          RTE_MEMZONE_2MB |
4360                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4361                                          RTE_MEMZONE_IOVA_CONTIG);
4362                 if (mz == NULL)
4363                         return -ENOMEM;
4364         }
4365         memset(mz->addr, 0, mz->len);
4366         mz_phys_addr = mz->iova;
4367         if ((unsigned long)mz->addr == mz_phys_addr) {
4368                 PMD_DRV_LOG(DEBUG,
4369                             "Memzone physical address same as virtual.\n");
4370                 PMD_DRV_LOG(DEBUG,
4371                             "Using rte_mem_virt2iova()\n");
4372                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4373                 if (mz_phys_addr == RTE_BAD_IOVA) {
4374                         PMD_DRV_LOG(ERR,
4375                                     "Can't map address to physical memory\n");
4376                         return -ENOMEM;
4377                 }
4378         }
4379
4380         bp->rx_mem_zone = (const void *)mz;
4381         bp->hw_rx_port_stats = mz->addr;
4382         bp->hw_rx_port_stats_map = mz_phys_addr;
4383
4384         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4385                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4386                  pci_dev->addr.bus, pci_dev->addr.devid,
4387                  pci_dev->addr.function, "tx_port_stats");
4388         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4389         mz = rte_memzone_lookup(mz_name);
4390         total_alloc_len =
4391                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4392                                        sizeof(struct tx_port_stats_ext) + 512);
4393         if (!mz) {
4394                 mz = rte_memzone_reserve(mz_name,
4395                                          total_alloc_len,
4396                                          SOCKET_ID_ANY,
4397                                          RTE_MEMZONE_2MB |
4398                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4399                                          RTE_MEMZONE_IOVA_CONTIG);
4400                 if (mz == NULL)
4401                         return -ENOMEM;
4402         }
4403         memset(mz->addr, 0, mz->len);
4404         mz_phys_addr = mz->iova;
4405         if ((unsigned long)mz->addr == mz_phys_addr) {
4406                 PMD_DRV_LOG(DEBUG,
4407                             "Memzone physical address same as virtual\n");
4408                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4409                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4410                 if (mz_phys_addr == RTE_BAD_IOVA) {
4411                         PMD_DRV_LOG(ERR,
4412                                     "Can't map address to physical memory\n");
4413                         return -ENOMEM;
4414                 }
4415         }
4416
4417         bp->tx_mem_zone = (const void *)mz;
4418         bp->hw_tx_port_stats = mz->addr;
4419         bp->hw_tx_port_stats_map = mz_phys_addr;
4420         bp->flags |= BNXT_FLAG_PORT_STATS;
4421
4422         /* Display extended statistics if FW supports it */
4423         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4424             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4425             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4426                 return 0;
4427
4428         bp->hw_rx_port_stats_ext = (void *)
4429                 ((uint8_t *)bp->hw_rx_port_stats +
4430                  sizeof(struct rx_port_stats));
4431         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4432                 sizeof(struct rx_port_stats);
4433         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4434
4435         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4436             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4437                 bp->hw_tx_port_stats_ext = (void *)
4438                         ((uint8_t *)bp->hw_tx_port_stats +
4439                          sizeof(struct tx_port_stats));
4440                 bp->hw_tx_port_stats_ext_map =
4441                         bp->hw_tx_port_stats_map +
4442                         sizeof(struct tx_port_stats);
4443                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4444         }
4445
4446         return 0;
4447 }
4448
4449 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4450 {
4451         struct bnxt *bp = eth_dev->data->dev_private;
4452         int rc = 0;
4453
4454         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4455                                                RTE_ETHER_ADDR_LEN *
4456                                                bp->max_l2_ctx,
4457                                                0);
4458         if (eth_dev->data->mac_addrs == NULL) {
4459                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4460                 return -ENOMEM;
4461         }
4462
4463         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4464                 if (BNXT_PF(bp))
4465                         return -EINVAL;
4466
4467                 /* Generate a random MAC address, if none was assigned by PF */
4468                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4469                 bnxt_eth_hw_addr_random(bp->mac_addr);
4470                 PMD_DRV_LOG(INFO,
4471                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4472                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4473                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4474
4475                 rc = bnxt_hwrm_set_mac(bp);
4476                 if (!rc)
4477                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4478                                RTE_ETHER_ADDR_LEN);
4479                 return rc;
4480         }
4481
4482         /* Copy the permanent MAC from the FUNC_QCAPS response */
4483         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4484         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4485
4486         return rc;
4487 }
4488
4489 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4490 {
4491         int rc = 0;
4492
4493         /* MAC is already configured in FW */
4494         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4495                 return 0;
4496
4497         /* Restore the old MAC configured */
4498         rc = bnxt_hwrm_set_mac(bp);
4499         if (rc)
4500                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4501
4502         return rc;
4503 }
4504
4505 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4506 {
4507         if (!BNXT_PF(bp))
4508                 return;
4509
4510 #define ALLOW_FUNC(x)   \
4511         { \
4512                 uint32_t arg = (x); \
4513                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4514                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4515         }
4516
4517         /* Forward all requests if firmware is new enough */
4518         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4519              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4520             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4521                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4522         } else {
4523                 PMD_DRV_LOG(WARNING,
4524                             "Firmware too old for VF mailbox functionality\n");
4525                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4526         }
4527
4528         /*
4529          * The following are used for driver cleanup. If we disallow these,
4530          * VF drivers can't clean up cleanly.
4531          */
4532         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4533         ALLOW_FUNC(HWRM_VNIC_FREE);
4534         ALLOW_FUNC(HWRM_RING_FREE);
4535         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4536         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4537         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4538         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4539         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4540         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4541 }
4542
4543 static int bnxt_init_fw(struct bnxt *bp)
4544 {
4545         uint16_t mtu;
4546         int rc = 0;
4547
4548         rc = bnxt_hwrm_ver_get(bp);
4549         if (rc)
4550                 return rc;
4551
4552         rc = bnxt_hwrm_func_reset(bp);
4553         if (rc)
4554                 return -EIO;
4555
4556         rc = bnxt_hwrm_vnic_qcaps(bp);
4557         if (rc)
4558                 return rc;
4559
4560         rc = bnxt_hwrm_queue_qportcfg(bp);
4561         if (rc)
4562                 return rc;
4563
4564         /* Get the MAX capabilities for this function.
4565          * This function also allocates context memory for TQM rings and
4566          * informs the firmware about this allocated backing store memory.
4567          */
4568         rc = bnxt_hwrm_func_qcaps(bp);
4569         if (rc)
4570                 return rc;
4571
4572         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4573         if (rc)
4574                 return rc;
4575
4576         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4577         if (rc)
4578                 return rc;
4579
4580         /* Get the adapter error recovery support info */
4581         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4582         if (rc)
4583                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4584
4585         bnxt_hwrm_port_led_qcaps(bp);
4586
4587         return 0;
4588 }
4589
4590 static int
4591 bnxt_init_locks(struct bnxt *bp)
4592 {
4593         int err;
4594
4595         err = pthread_mutex_init(&bp->flow_lock, NULL);
4596         if (err) {
4597                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4598                 return err;
4599         }
4600
4601         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4602         if (err)
4603                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4604         return err;
4605 }
4606
4607 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4608 {
4609         int rc;
4610
4611         rc = bnxt_init_fw(bp);
4612         if (rc)
4613                 return rc;
4614
4615         if (!reconfig_dev) {
4616                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4617                 if (rc)
4618                         return rc;
4619         } else {
4620                 rc = bnxt_restore_dflt_mac(bp);
4621                 if (rc)
4622                         return rc;
4623         }
4624
4625         bnxt_config_vf_req_fwd(bp);
4626
4627         rc = bnxt_hwrm_func_driver_register(bp);
4628         if (rc) {
4629                 PMD_DRV_LOG(ERR, "Failed to register driver");
4630                 return -EBUSY;
4631         }
4632
4633         if (BNXT_PF(bp)) {
4634                 if (bp->pdev->max_vfs) {
4635                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4636                         if (rc) {
4637                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4638                                 return rc;
4639                         }
4640                 } else {
4641                         rc = bnxt_hwrm_allocate_pf_only(bp);
4642                         if (rc) {
4643                                 PMD_DRV_LOG(ERR,
4644                                             "Failed to allocate PF resources");
4645                                 return rc;
4646                         }
4647                 }
4648         }
4649
4650         rc = bnxt_alloc_mem(bp, reconfig_dev);
4651         if (rc)
4652                 return rc;
4653
4654         rc = bnxt_setup_int(bp);
4655         if (rc)
4656                 return rc;
4657
4658         rc = bnxt_request_int(bp);
4659         if (rc)
4660                 return rc;
4661
4662         rc = bnxt_init_locks(bp);
4663         if (rc)
4664                 return rc;
4665
4666         return 0;
4667 }
4668
4669 static int
4670 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4671 {
4672         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4673         static int version_printed;
4674         struct bnxt *bp;
4675         int rc;
4676
4677         if (version_printed++ == 0)
4678                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4679
4680         eth_dev->dev_ops = &bnxt_dev_ops;
4681         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4682         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4683
4684         /*
4685          * For secondary processes, we don't initialise any further
4686          * as primary has already done this work.
4687          */
4688         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4689                 return 0;
4690
4691         rte_eth_copy_pci_info(eth_dev, pci_dev);
4692
4693         bp = eth_dev->data->dev_private;
4694
4695         bp->dev_stopped = 1;
4696
4697         if (bnxt_vf_pciid(pci_dev->id.device_id))
4698                 bp->flags |= BNXT_FLAG_VF;
4699
4700         if (bnxt_thor_device(pci_dev->id.device_id))
4701                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4702
4703         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4704             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4705             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4706             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4707                 bp->flags |= BNXT_FLAG_STINGRAY;
4708
4709         rc = bnxt_init_board(eth_dev);
4710         if (rc) {
4711                 PMD_DRV_LOG(ERR,
4712                             "Failed to initialize board rc: %x\n", rc);
4713                 return rc;
4714         }
4715
4716         rc = bnxt_alloc_hwrm_resources(bp);
4717         if (rc) {
4718                 PMD_DRV_LOG(ERR,
4719                             "Failed to allocate hwrm resource rc: %x\n", rc);
4720                 goto error_free;
4721         }
4722         rc = bnxt_init_resources(bp, false);
4723         if (rc)
4724                 goto error_free;
4725
4726         rc = bnxt_alloc_stats_mem(bp);
4727         if (rc)
4728                 goto error_free;
4729
4730         PMD_DRV_LOG(INFO,
4731                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4732                     pci_dev->mem_resource[0].phys_addr,
4733                     pci_dev->mem_resource[0].addr);
4734
4735         return 0;
4736
4737 error_free:
4738         bnxt_dev_uninit(eth_dev);
4739         return rc;
4740 }
4741
4742 static void
4743 bnxt_uninit_locks(struct bnxt *bp)
4744 {
4745         pthread_mutex_destroy(&bp->flow_lock);
4746         pthread_mutex_destroy(&bp->def_cp_lock);
4747 }
4748
4749 static int
4750 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4751 {
4752         int rc;
4753
4754         bnxt_free_int(bp);
4755         bnxt_free_mem(bp, reconfig_dev);
4756         bnxt_hwrm_func_buf_unrgtr(bp);
4757         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4758         bp->flags &= ~BNXT_FLAG_REGISTERED;
4759         bnxt_free_ctx_mem(bp);
4760         if (!reconfig_dev) {
4761                 bnxt_free_hwrm_resources(bp);
4762
4763                 if (bp->recovery_info != NULL) {
4764                         rte_free(bp->recovery_info);
4765                         bp->recovery_info = NULL;
4766                 }
4767         }
4768
4769         bnxt_uninit_locks(bp);
4770         rte_free(bp->ptp_cfg);
4771         bp->ptp_cfg = NULL;
4772         return rc;
4773 }
4774
4775 static int
4776 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4777 {
4778         struct bnxt *bp = eth_dev->data->dev_private;
4779         int rc;
4780
4781         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4782                 return -EPERM;
4783
4784         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4785
4786         rc = bnxt_uninit_resources(bp, false);
4787
4788         if (bp->tx_mem_zone) {
4789                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4790                 bp->tx_mem_zone = NULL;
4791         }
4792
4793         if (bp->rx_mem_zone) {
4794                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4795                 bp->rx_mem_zone = NULL;
4796         }
4797
4798         if (bp->dev_stopped == 0)
4799                 bnxt_dev_close_op(eth_dev);
4800         if (bp->pf.vf_info)
4801                 rte_free(bp->pf.vf_info);
4802         eth_dev->dev_ops = NULL;
4803         eth_dev->rx_pkt_burst = NULL;
4804         eth_dev->tx_pkt_burst = NULL;
4805
4806         return rc;
4807 }
4808
4809 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4810         struct rte_pci_device *pci_dev)
4811 {
4812         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4813                 bnxt_dev_init);
4814 }
4815
4816 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4817 {
4818         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4819                 return rte_eth_dev_pci_generic_remove(pci_dev,
4820                                 bnxt_dev_uninit);
4821         else
4822                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4823 }
4824
4825 static struct rte_pci_driver bnxt_rte_pmd = {
4826         .id_table = bnxt_pci_id_map,
4827         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4828         .probe = bnxt_pci_probe,
4829         .remove = bnxt_pci_remove,
4830 };
4831
4832 static bool
4833 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4834 {
4835         if (strcmp(dev->device->driver->name, drv->driver.name))
4836                 return false;
4837
4838         return true;
4839 }
4840
4841 bool is_bnxt_supported(struct rte_eth_dev *dev)
4842 {
4843         return is_device_supported(dev, &bnxt_rte_pmd);
4844 }
4845
4846 RTE_INIT(bnxt_init_log)
4847 {
4848         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4849         if (bnxt_logtype_driver >= 0)
4850                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4851 }
4852
4853 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4854 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4855 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");