drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29
  30 #define DRV_MODULE_NAME         "bnxt"
  31 static const char bnxt_version[] =
  32         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  33 int bnxt_logtype_driver;
  34
  35 /*
  36  * The set of PCI devices this driver supports
  37  */
  38 static const struct rte_pci_id bnxt_pci_id_map[] = {
  39         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  40                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  41         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  42                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  43         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  92         { .vendor_id = 0, /* sentinel */ },
  93 };
  94
  95 #define BNXT_ETH_RSS_SUPPORT (  \
  96         ETH_RSS_IPV4 |          \
  97         ETH_RSS_NONFRAG_IPV4_TCP |      \
  98         ETH_RSS_NONFRAG_IPV4_UDP |      \
  99         ETH_RSS_IPV6 |          \
 100         ETH_RSS_NONFRAG_IPV6_TCP |      \
 101         ETH_RSS_NONFRAG_IPV6_UDP)
 102
 103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 104                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 105                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 106                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_TCP_TSO | \
 108                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 109                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 110                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 114                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 115
 116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 117                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 118                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 119                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 120                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 122                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 123                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 124                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 125                                      DEV_RX_OFFLOAD_TCP_LRO | \
 126                                      DEV_RX_OFFLOAD_SCATTER | \
 127                                      DEV_RX_OFFLOAD_RSS_HASH)
 128
 129 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 130 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 131 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 132 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 133 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 134 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 135 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 136 static void bnxt_dev_recover(void *arg);
 137
 138 int is_bnxt_in_error(struct bnxt *bp)
 139 {
 140         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 141                 return -EIO;
 142         if (bp->flags & BNXT_FLAG_FW_RESET)
 143                 return -EBUSY;
 144
 145         return 0;
 146 }
 147
 148 /***********************/
 149
 150 /*
 151  * High level utility functions
 152  */
 153
 154 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 155 {
 156         if (!BNXT_CHIP_THOR(bp))
 157                 return 1;
 158
 159         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 160                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 161                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 162 }
 163
 164 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 165 {
 166         if (!BNXT_CHIP_THOR(bp))
 167                 return HW_HASH_INDEX_SIZE;
 168
 169         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 170 }
 171
 172 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 173 {
 174         bnxt_free_filter_mem(bp);
 175         bnxt_free_vnic_attributes(bp);
 176         bnxt_free_vnic_mem(bp);
 177
 178         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 179          * If the number of rings change across fw update,
 180          * we don't have much choice except to warn the user.
 181          */
 182         if (!reconfig) {
 183                 bnxt_free_stats(bp);
 184                 bnxt_free_tx_rings(bp);
 185                 bnxt_free_rx_rings(bp);
 186         }
 187         bnxt_free_async_cp_ring(bp);
 188         bnxt_free_rxtx_nq_ring(bp);
 189
 190         rte_free(bp->grp_info);
 191         bp->grp_info = NULL;
 192 }
 193
 194 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 195 {
 196         int rc;
 197
 198         rc = bnxt_alloc_ring_grps(bp);
 199         if (rc)
 200                 goto alloc_mem_err;
 201
 202         rc = bnxt_alloc_async_ring_struct(bp);
 203         if (rc)
 204                 goto alloc_mem_err;
 205
 206         rc = bnxt_alloc_vnic_mem(bp);
 207         if (rc)
 208                 goto alloc_mem_err;
 209
 210         rc = bnxt_alloc_vnic_attributes(bp);
 211         if (rc)
 212                 goto alloc_mem_err;
 213
 214         rc = bnxt_alloc_filter_mem(bp);
 215         if (rc)
 216                 goto alloc_mem_err;
 217
 218         rc = bnxt_alloc_async_cp_ring(bp);
 219         if (rc)
 220                 goto alloc_mem_err;
 221
 222         rc = bnxt_alloc_rxtx_nq_ring(bp);
 223         if (rc)
 224                 goto alloc_mem_err;
 225
 226         return 0;
 227
 228 alloc_mem_err:
 229         bnxt_free_mem(bp, reconfig);
 230         return rc;
 231 }
 232
 233 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 234 {
 235         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 236         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 237         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 238         struct bnxt_rx_queue *rxq;
 239         unsigned int j;
 240         int rc;
 241
 242         rc = bnxt_vnic_grp_alloc(bp, vnic);
 243         if (rc)
 244                 goto err_out;
 245
 246         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 247                     vnic_id, vnic, vnic->fw_grp_ids);
 248
 249         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 250         if (rc)
 251                 goto err_out;
 252
 253         /* Alloc RSS context only if RSS mode is enabled */
 254         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 255                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 256
 257                 rc = 0;
 258                 for (j = 0; j < nr_ctxs; j++) {
 259                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 260                         if (rc)
 261                                 break;
 262                 }
 263                 if (rc) {
 264                         PMD_DRV_LOG(ERR,
 265                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 266                                     vnic_id, j, rc);
 267                         goto err_out;
 268                 }
 269                 vnic->num_lb_ctxts = nr_ctxs;
 270         }
 271
 272         /*
 273          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 274          * setting is not available at this time, it will not be
 275          * configured correctly in the CFA.
 276          */
 277         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 278                 vnic->vlan_strip = true;
 279         else
 280                 vnic->vlan_strip = false;
 281
 282         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 283         if (rc)
 284                 goto err_out;
 285
 286         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 287         if (rc)
 288                 goto err_out;
 289
 290         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 291                 rxq = bp->eth_dev->data->rx_queues[j];
 292
 293                 PMD_DRV_LOG(DEBUG,
 294                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 295                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 296
 297                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 298                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 299                 else
 300                         vnic->rx_queue_cnt++;
 301         }
 302
 303         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 304
 305         rc = bnxt_vnic_rss_configure(bp, vnic);
 306         if (rc)
 307                 goto err_out;
 308
 309         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 310
 311         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 312                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 313         else
 314                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 315
 316         return 0;
 317 err_out:
 318         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 319                     vnic_id, rc);
 320         return rc;
 321 }
 322
 323 static int bnxt_init_chip(struct bnxt *bp)
 324 {
 325         struct rte_eth_link new;
 326         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 327         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 328         uint32_t intr_vector = 0;
 329         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 330         uint32_t vec = BNXT_MISC_VEC_ID;
 331         unsigned int i, j;
 332         int rc;
 333
 334         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 335                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 336                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 337                 bp->flags |= BNXT_FLAG_JUMBO;
 338         } else {
 339                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 340                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 341                 bp->flags &= ~BNXT_FLAG_JUMBO;
 342         }
 343
 344         /* THOR does not support ring groups.
 345          * But we will use the array to save RSS context IDs.
 346          */
 347         if (BNXT_CHIP_THOR(bp))
 348                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 349
 350         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 351         if (rc) {
 352                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 353                 goto err_out;
 354         }
 355
 356         rc = bnxt_alloc_hwrm_rings(bp);
 357         if (rc) {
 358                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 359                 goto err_out;
 360         }
 361
 362         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 363         if (rc) {
 364                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 365                 goto err_out;
 366         }
 367
 368         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 369                 goto skip_cosq_cfg;
 370
 371         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 372                 if (bp->rx_cos_queue[i].id != 0xff) {
 373                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 374
 375                         if (!vnic) {
 376                                 PMD_DRV_LOG(ERR,
 377                                             "Num pools more than FW profile\n");
 378                                 rc = -EINVAL;
 379                                 goto err_out;
 380                         }
 381                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 382                         bp->rx_cosq_cnt++;
 383                 }
 384         }
 385
 386 skip_cosq_cfg:
 387         rc = bnxt_mq_rx_configure(bp);
 388         if (rc) {
 389                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 390                 goto err_out;
 391         }
 392
 393         /* VNIC configuration */
 394         for (i = 0; i < bp->nr_vnics; i++) {
 395                 rc = bnxt_setup_one_vnic(bp, i);
 396                 if (rc)
 397                         goto err_out;
 398         }
 399
 400         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 401         if (rc) {
 402                 PMD_DRV_LOG(ERR,
 403                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 404                 goto err_out;
 405         }
 406
 407         /* check and configure queue intr-vector mapping */
 408         if ((rte_intr_cap_multiple(intr_handle) ||
 409              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 410             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 411                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 412                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 413                 if (intr_vector > bp->rx_cp_nr_rings) {
 414                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 415                                         bp->rx_cp_nr_rings);
 416                         return -ENOTSUP;
 417                 }
 418                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 419                 if (rc)
 420                         return rc;
 421         }
 422
 423         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 424                 intr_handle->intr_vec =
 425                         rte_zmalloc("intr_vec",
 426                                     bp->eth_dev->data->nb_rx_queues *
 427                                     sizeof(int), 0);
 428                 if (intr_handle->intr_vec == NULL) {
 429                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 430                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 431                         rc = -ENOMEM;
 432                         goto err_disable;
 433                 }
 434                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 435                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 436                          intr_handle->intr_vec, intr_handle->nb_efd,
 437                         intr_handle->max_intr);
 438                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 439                      queue_id++) {
 440                         intr_handle->intr_vec[queue_id] =
 441                                                         vec + BNXT_RX_VEC_START;
 442                         if (vec < base + intr_handle->nb_efd - 1)
 443                                 vec++;
 444                 }
 445         }
 446
 447         /* enable uio/vfio intr/eventfd mapping */
 448         rc = rte_intr_enable(intr_handle);
 449 #ifndef RTE_EXEC_ENV_FREEBSD
 450         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 451         if (rc)
 452                 goto err_free;
 453 #endif
 454
 455         rc = bnxt_get_hwrm_link_config(bp, &new);
 456         if (rc) {
 457                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 458                 goto err_free;
 459         }
 460
 461         if (!bp->link_info.link_up) {
 462                 rc = bnxt_set_hwrm_link_config(bp, true);
 463                 if (rc) {
 464                         PMD_DRV_LOG(ERR,
 465                                 "HWRM link config failure rc: %x\n", rc);
 466                         goto err_free;
 467                 }
 468         }
 469         bnxt_print_link_info(bp->eth_dev);
 470
 471         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 472         if (!bp->mark_table)
 473                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 474
 475         return 0;
 476
 477 err_free:
 478         rte_free(intr_handle->intr_vec);
 479 err_disable:
 480         rte_intr_efd_disable(intr_handle);
 481 err_out:
 482         /* Some of the error status returned by FW may not be from errno.h */
 483         if (rc > 0)
 484                 rc = -EIO;
 485
 486         return rc;
 487 }
 488
 489 static int bnxt_shutdown_nic(struct bnxt *bp)
 490 {
 491         bnxt_free_all_hwrm_resources(bp);
 492         bnxt_free_all_filters(bp);
 493         bnxt_free_all_vnics(bp);
 494         return 0;
 495 }
 496
 497 /*
 498  * Device configuration and status function
 499  */
 500
 501 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 502                                 struct rte_eth_dev_info *dev_info)
 503 {
 504         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 505         struct bnxt *bp = eth_dev->data->dev_private;
 506         uint16_t max_vnics, i, j, vpool, vrxq;
 507         unsigned int max_rx_rings;
 508         int rc;
 509
 510         rc = is_bnxt_in_error(bp);
 511         if (rc)
 512                 return rc;
 513
 514         /* MAC Specifics */
 515         dev_info->max_mac_addrs = bp->max_l2_ctx;
 516         dev_info->max_hash_mac_addrs = 0;
 517
 518         /* PF/VF specifics */
 519         if (BNXT_PF(bp))
 520                 dev_info->max_vfs = pdev->max_vfs;
 521
 522         max_rx_rings = BNXT_MAX_RINGS(bp);
 523         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 524         dev_info->max_rx_queues = max_rx_rings;
 525         dev_info->max_tx_queues = max_rx_rings;
 526         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 527         dev_info->hash_key_size = 40;
 528         max_vnics = bp->max_vnics;
 529
 530         /* MTU specifics */
 531         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 532         dev_info->max_mtu = BNXT_MAX_MTU;
 533
 534         /* Fast path specifics */
 535         dev_info->min_rx_bufsize = 1;
 536         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 537
 538         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 539         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 540                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 541         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 542         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 543
 544         /* *INDENT-OFF* */
 545         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 546                 .rx_thresh = {
 547                         .pthresh = 8,
 548                         .hthresh = 8,
 549                         .wthresh = 0,
 550                 },
 551                 .rx_free_thresh = 32,
 552                 /* If no descriptors available, pkts are dropped by default */
 553                 .rx_drop_en = 1,
 554         };
 555
 556         dev_info->default_txconf = (struct rte_eth_txconf) {
 557                 .tx_thresh = {
 558                         .pthresh = 32,
 559                         .hthresh = 0,
 560                         .wthresh = 0,
 561                 },
 562                 .tx_free_thresh = 32,
 563                 .tx_rs_thresh = 32,
 564         };
 565         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 566
 567         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 568         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 569         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 570         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 571         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 572
 573         /* *INDENT-ON* */
 574
 575         /*
 576          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 577          *       need further investigation.
 578          */
 579
 580         /* VMDq resources */
 581         vpool = 64; /* ETH_64_POOLS */
 582         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 583         for (i = 0; i < 4; vpool >>= 1, i++) {
 584                 if (max_vnics > vpool) {
 585                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 586                                 if (dev_info->max_rx_queues > vrxq) {
 587                                         if (vpool > vrxq)
 588                                                 vpool = vrxq;
 589                                         goto found;
 590                                 }
 591                         }
 592                         /* Not enough resources to support VMDq */
 593                         break;
 594                 }
 595         }
 596         /* Not enough resources to support VMDq */
 597         vpool = 0;
 598         vrxq = 0;
 599 found:
 600         dev_info->max_vmdq_pools = vpool;
 601         dev_info->vmdq_queue_num = vrxq;
 602
 603         dev_info->vmdq_pool_base = 0;
 604         dev_info->vmdq_queue_base = 0;
 605
 606         return 0;
 607 }
 608
 609 /* Configure the device based on the configuration provided */
 610 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 611 {
 612         struct bnxt *bp = eth_dev->data->dev_private;
 613         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 614         int rc;
 615
 616         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 617         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 618         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 619         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 620
 621         rc = is_bnxt_in_error(bp);
 622         if (rc)
 623                 return rc;
 624
 625         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 626                 rc = bnxt_hwrm_check_vf_rings(bp);
 627                 if (rc) {
 628                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 629                         return -ENOSPC;
 630                 }
 631
 632                 /* If a resource has already been allocated - in this case
 633                  * it is the async completion ring, free it. Reallocate it after
 634                  * resource reservation. This will ensure the resource counts
 635                  * are calculated correctly.
 636                  */
 637
 638                 pthread_mutex_lock(&bp->def_cp_lock);
 639
 640                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 641                         bnxt_disable_int(bp);
 642                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 643                 }
 644
 645                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 646                 if (rc) {
 647                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 648                         pthread_mutex_unlock(&bp->def_cp_lock);
 649                         return -ENOSPC;
 650                 }
 651
 652                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 653                         rc = bnxt_alloc_async_cp_ring(bp);
 654                         if (rc) {
 655                                 pthread_mutex_unlock(&bp->def_cp_lock);
 656                                 return rc;
 657                         }
 658                         bnxt_enable_int(bp);
 659                 }
 660
 661                 pthread_mutex_unlock(&bp->def_cp_lock);
 662         } else {
 663                 /* legacy driver needs to get updated values */
 664                 rc = bnxt_hwrm_func_qcaps(bp);
 665                 if (rc) {
 666                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 667                         return rc;
 668                 }
 669         }
 670
 671         /* Inherit new configurations */
 672         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 673             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 674             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 675                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 676             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 677             bp->max_stat_ctx)
 678                 goto resource_error;
 679
 680         if (BNXT_HAS_RING_GRPS(bp) &&
 681             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 682                 goto resource_error;
 683
 684         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 685             bp->max_vnics < eth_dev->data->nb_rx_queues)
 686                 goto resource_error;
 687
 688         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 689         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 690
 691         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 692                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 693         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
 694
 695         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 696                 eth_dev->data->mtu =
 697                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 698                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 699                         BNXT_NUM_VLANS;
 700                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 701         }
 702         return 0;
 703
 704 resource_error:
 705         PMD_DRV_LOG(ERR,
 706                     "Insufficient resources to support requested config\n");
 707         PMD_DRV_LOG(ERR,
 708                     "Num Queues Requested: Tx %d, Rx %d\n",
 709                     eth_dev->data->nb_tx_queues,
 710                     eth_dev->data->nb_rx_queues);
 711         PMD_DRV_LOG(ERR,
 712                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 713                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 714                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 715         return -ENOSPC;
 716 }
 717
 718 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 719 {
 720         struct rte_eth_link *link = &eth_dev->data->dev_link;
 721
 722         if (link->link_status)
 723                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 724                         eth_dev->data->port_id,
 725                         (uint32_t)link->link_speed,
 726                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 727                         ("full-duplex") : ("half-duplex\n"));
 728         else
 729                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 730                         eth_dev->data->port_id);
 731 }
 732
 733 /*
 734  * Determine whether the current configuration requires support for scattered
 735  * receive; return 1 if scattered receive is required and 0 if not.
 736  */
 737 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 738 {
 739         uint16_t buf_size;
 740         int i;
 741
 742         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 743                 return 1;
 744
 745         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 746                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 747
 748                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 749                                       RTE_PKTMBUF_HEADROOM);
 750                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 751                         return 1;
 752         }
 753         return 0;
 754 }
 755
 756 static eth_rx_burst_t
 757 bnxt_receive_function(struct rte_eth_dev *eth_dev)
 758 {
 759         struct bnxt *bp = eth_dev->data->dev_private;
 760
 761 #ifdef RTE_ARCH_X86
 762 #ifndef RTE_LIBRTE_IEEE1588
 763         /*
 764          * Vector mode receive can be enabled only if scatter rx is not
 765          * in use and rx offloads are limited to VLAN stripping and
 766          * CRC stripping.
 767          */
 768         if (!eth_dev->data->scattered_rx &&
 769             !(eth_dev->data->dev_conf.rxmode.offloads &
 770               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 771                 DEV_RX_OFFLOAD_KEEP_CRC |
 772                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 773                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 774                 DEV_RX_OFFLOAD_UDP_CKSUM |
 775                 DEV_RX_OFFLOAD_TCP_CKSUM |
 776                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 777                 DEV_RX_OFFLOAD_RSS_HASH |
 778                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 779                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 780                             eth_dev->data->port_id);
 781                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
 782                 return bnxt_recv_pkts_vec;
 783         }
 784         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 785                     eth_dev->data->port_id);
 786         PMD_DRV_LOG(INFO,
 787                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 788                     eth_dev->data->port_id,
 789                     eth_dev->data->scattered_rx,
 790                     eth_dev->data->dev_conf.rxmode.offloads);
 791 #endif
 792 #endif
 793         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
 794         return bnxt_recv_pkts;
 795 }
 796
 797 static eth_tx_burst_t
 798 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 799 {
 800 #ifdef RTE_ARCH_X86
 801 #ifndef RTE_LIBRTE_IEEE1588
 802         /*
 803          * Vector mode transmit can be enabled only if not using scatter rx
 804          * or tx offloads.
 805          */
 806         if (!eth_dev->data->scattered_rx &&
 807             !eth_dev->data->dev_conf.txmode.offloads) {
 808                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 809                             eth_dev->data->port_id);
 810                 return bnxt_xmit_pkts_vec;
 811         }
 812         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 813                     eth_dev->data->port_id);
 814         PMD_DRV_LOG(INFO,
 815                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 816                     eth_dev->data->port_id,
 817                     eth_dev->data->scattered_rx,
 818                     eth_dev->data->dev_conf.txmode.offloads);
 819 #endif
 820 #endif
 821         return bnxt_xmit_pkts;
 822 }
 823
 824 static int bnxt_handle_if_change_status(struct bnxt *bp)
 825 {
 826         int rc;
 827
 828         /* Since fw has undergone a reset and lost all contexts,
 829          * set fatal flag to not issue hwrm during cleanup
 830          */
 831         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 832         bnxt_uninit_resources(bp, true);
 833
 834         /* clear fatal flag so that re-init happens */
 835         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 836         rc = bnxt_init_resources(bp, true);
 837
 838         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 839
 840         return rc;
 841 }
 842
 843 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 844 {
 845         struct bnxt *bp = eth_dev->data->dev_private;
 846         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 847         int vlan_mask = 0;
 848         int rc;
 849
 850         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
 851                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
 852                 return -EINVAL;
 853         }
 854
 855         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 856                 PMD_DRV_LOG(ERR,
 857                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 858                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 859         }
 860
 861         rc = bnxt_hwrm_if_change(bp, 1);
 862         if (!rc) {
 863                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 864                         rc = bnxt_handle_if_change_status(bp);
 865                         if (rc)
 866                                 return rc;
 867                 }
 868         }
 869         bnxt_enable_int(bp);
 870
 871         rc = bnxt_init_chip(bp);
 872         if (rc)
 873                 goto error;
 874
 875         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 876         eth_dev->data->dev_started = 1;
 877
 878         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
 879
 880         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 881                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 882         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 883                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 884         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 885         if (rc)
 886                 goto error;
 887
 888         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 889         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 890
 891         pthread_mutex_lock(&bp->def_cp_lock);
 892         bnxt_schedule_fw_health_check(bp);
 893         pthread_mutex_unlock(&bp->def_cp_lock);
 894         return 0;
 895
 896 error:
 897         bnxt_hwrm_if_change(bp, 0);
 898         bnxt_shutdown_nic(bp);
 899         bnxt_free_tx_mbufs(bp);
 900         bnxt_free_rx_mbufs(bp);
 901         eth_dev->data->dev_started = 0;
 902         return rc;
 903 }
 904
 905 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 906 {
 907         struct bnxt *bp = eth_dev->data->dev_private;
 908         int rc = 0;
 909
 910         if (!bp->link_info.link_up)
 911                 rc = bnxt_set_hwrm_link_config(bp, true);
 912         if (!rc)
 913                 eth_dev->data->dev_link.link_status = 1;
 914
 915         bnxt_print_link_info(eth_dev);
 916         return rc;
 917 }
 918
 919 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 920 {
 921         struct bnxt *bp = eth_dev->data->dev_private;
 922
 923         eth_dev->data->dev_link.link_status = 0;
 924         bnxt_set_hwrm_link_config(bp, false);
 925         bp->link_info.link_up = 0;
 926
 927         return 0;
 928 }
 929
 930 /* Unload the driver, release resources */
 931 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 932 {
 933         struct bnxt *bp = eth_dev->data->dev_private;
 934         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 935         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 936
 937         eth_dev->data->dev_started = 0;
 938         /* Prevent crashes when queues are still in use */
 939         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 940         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 941
 942         bnxt_disable_int(bp);
 943
 944         /* disable uio/vfio intr/eventfd mapping */
 945         rte_intr_disable(intr_handle);
 946
 947         bnxt_cancel_fw_health_check(bp);
 948
 949         bnxt_dev_set_link_down_op(eth_dev);
 950
 951         /* Wait for link to be reset and the async notification to process.
 952          * During reset recovery, there is no need to wait and
 953          * VF/NPAR functions do not have privilege to change PHY config.
 954          */
 955         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
 956                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
 957
 958         /* Clean queue intr-vector mapping */
 959         rte_intr_efd_disable(intr_handle);
 960         if (intr_handle->intr_vec != NULL) {
 961                 rte_free(intr_handle->intr_vec);
 962                 intr_handle->intr_vec = NULL;
 963         }
 964
 965         bnxt_hwrm_port_clr_stats(bp);
 966         bnxt_free_tx_mbufs(bp);
 967         bnxt_free_rx_mbufs(bp);
 968         /* Process any remaining notifications in default completion queue */
 969         bnxt_int_handler(eth_dev);
 970         bnxt_shutdown_nic(bp);
 971         bnxt_hwrm_if_change(bp, 0);
 972
 973         rte_free(bp->mark_table);
 974         bp->mark_table = NULL;
 975
 976         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
 977         bp->rx_cosq_cnt = 0;
 978 }
 979
 980 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 981 {
 982         struct bnxt *bp = eth_dev->data->dev_private;
 983
 984         /* cancel the recovery handler before remove dev */
 985         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
 986         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
 987
 988         if (eth_dev->data->dev_started)
 989                 bnxt_dev_stop_op(eth_dev);
 990
 991         bnxt_uninit_resources(bp, false);
 992
 993         eth_dev->dev_ops = NULL;
 994         eth_dev->rx_pkt_burst = NULL;
 995         eth_dev->tx_pkt_burst = NULL;
 996
 997         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
 998         bp->tx_mem_zone = NULL;
 999         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1000         bp->rx_mem_zone = NULL;
1001
1002         rte_free(bp->pf.vf_info);
1003         bp->pf.vf_info = NULL;
1004
1005         rte_free(bp->grp_info);
1006         bp->grp_info = NULL;
1007 }
1008
1009 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1010                                     uint32_t index)
1011 {
1012         struct bnxt *bp = eth_dev->data->dev_private;
1013         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1014         struct bnxt_vnic_info *vnic;
1015         struct bnxt_filter_info *filter, *temp_filter;
1016         uint32_t i;
1017
1018         if (is_bnxt_in_error(bp))
1019                 return;
1020
1021         /*
1022          * Loop through all VNICs from the specified filter flow pools to
1023          * remove the corresponding MAC addr filter
1024          */
1025         for (i = 0; i < bp->nr_vnics; i++) {
1026                 if (!(pool_mask & (1ULL << i)))
1027                         continue;
1028
1029                 vnic = &bp->vnic_info[i];
1030                 filter = STAILQ_FIRST(&vnic->filter);
1031                 while (filter) {
1032                         temp_filter = STAILQ_NEXT(filter, next);
1033                         if (filter->mac_index == index) {
1034                                 STAILQ_REMOVE(&vnic->filter, filter,
1035                                                 bnxt_filter_info, next);
1036                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1037                                 bnxt_free_filter(bp, filter);
1038                         }
1039                         filter = temp_filter;
1040                 }
1041         }
1042 }
1043
1044 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1045                                struct rte_ether_addr *mac_addr, uint32_t index,
1046                                uint32_t pool)
1047 {
1048         struct bnxt_filter_info *filter;
1049         int rc = 0;
1050
1051         /* Attach requested MAC address to the new l2_filter */
1052         STAILQ_FOREACH(filter, &vnic->filter, next) {
1053                 if (filter->mac_index == index) {
1054                         PMD_DRV_LOG(DEBUG,
1055                                     "MAC addr already existed for pool %d\n",
1056                                     pool);
1057                         return 0;
1058                 }
1059         }
1060
1061         filter = bnxt_alloc_filter(bp);
1062         if (!filter) {
1063                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1064                 return -ENODEV;
1065         }
1066
1067         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1068          * if the MAC that's been programmed now is a different one, then,
1069          * copy that addr to filter->l2_addr
1070          */
1071         if (mac_addr)
1072                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1073         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1074
1075         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1076         if (!rc) {
1077                 filter->mac_index = index;
1078                 if (filter->mac_index == 0)
1079                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1080                 else
1081                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1082         } else {
1083                 bnxt_free_filter(bp, filter);
1084         }
1085
1086         return rc;
1087 }
1088
1089 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1090                                 struct rte_ether_addr *mac_addr,
1091                                 uint32_t index, uint32_t pool)
1092 {
1093         struct bnxt *bp = eth_dev->data->dev_private;
1094         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1095         int rc = 0;
1096
1097         rc = is_bnxt_in_error(bp);
1098         if (rc)
1099                 return rc;
1100
1101         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1102                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1103                 return -ENOTSUP;
1104         }
1105
1106         if (!vnic) {
1107                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1108                 return -EINVAL;
1109         }
1110
1111         /* Filter settings will get applied when port is started */
1112         if (!eth_dev->data->dev_started)
1113                 return 0;
1114
1115         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1116
1117         return rc;
1118 }
1119
1120 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1121                      bool exp_link_status)
1122 {
1123         int rc = 0;
1124         struct bnxt *bp = eth_dev->data->dev_private;
1125         struct rte_eth_link new;
1126         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1127                   BNXT_LINK_DOWN_WAIT_CNT;
1128
1129         rc = is_bnxt_in_error(bp);
1130         if (rc)
1131                 return rc;
1132
1133         memset(&new, 0, sizeof(new));
1134         do {
1135                 /* Retrieve link info from hardware */
1136                 rc = bnxt_get_hwrm_link_config(bp, &new);
1137                 if (rc) {
1138                         new.link_speed = ETH_LINK_SPEED_100M;
1139                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1140                         PMD_DRV_LOG(ERR,
1141                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1142                         goto out;
1143                 }
1144
1145                 if (!wait_to_complete || new.link_status == exp_link_status)
1146                         break;
1147
1148                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1149         } while (cnt--);
1150
1151 out:
1152         /* Timed out or success */
1153         if (new.link_status != eth_dev->data->dev_link.link_status ||
1154         new.link_speed != eth_dev->data->dev_link.link_speed) {
1155                 rte_eth_linkstatus_set(eth_dev, &new);
1156
1157                 _rte_eth_dev_callback_process(eth_dev,
1158                                               RTE_ETH_EVENT_INTR_LSC,
1159                                               NULL);
1160
1161                 bnxt_print_link_info(eth_dev);
1162         }
1163
1164         return rc;
1165 }
1166
1167 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1168                                int wait_to_complete)
1169 {
1170         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1171 }
1172
1173 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1174 {
1175         struct bnxt *bp = eth_dev->data->dev_private;
1176         struct bnxt_vnic_info *vnic;
1177         uint32_t old_flags;
1178         int rc;
1179
1180         rc = is_bnxt_in_error(bp);
1181         if (rc)
1182                 return rc;
1183
1184         /* Filter settings will get applied when port is started */
1185         if (!eth_dev->data->dev_started)
1186                 return 0;
1187
1188         if (bp->vnic_info == NULL)
1189                 return 0;
1190
1191         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1192
1193         old_flags = vnic->flags;
1194         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1195         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1196         if (rc != 0)
1197                 vnic->flags = old_flags;
1198
1199         return rc;
1200 }
1201
1202 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1203 {
1204         struct bnxt *bp = eth_dev->data->dev_private;
1205         struct bnxt_vnic_info *vnic;
1206         uint32_t old_flags;
1207         int rc;
1208
1209         rc = is_bnxt_in_error(bp);
1210         if (rc)
1211                 return rc;
1212
1213         /* Filter settings will get applied when port is started */
1214         if (!eth_dev->data->dev_started)
1215                 return 0;
1216
1217         if (bp->vnic_info == NULL)
1218                 return 0;
1219
1220         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1221
1222         old_flags = vnic->flags;
1223         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1224         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1225         if (rc != 0)
1226                 vnic->flags = old_flags;
1227
1228         return rc;
1229 }
1230
1231 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1232 {
1233         struct bnxt *bp = eth_dev->data->dev_private;
1234         struct bnxt_vnic_info *vnic;
1235         uint32_t old_flags;
1236         int rc;
1237
1238         rc = is_bnxt_in_error(bp);
1239         if (rc)
1240                 return rc;
1241
1242         /* Filter settings will get applied when port is started */
1243         if (!eth_dev->data->dev_started)
1244                 return 0;
1245
1246         if (bp->vnic_info == NULL)
1247                 return 0;
1248
1249         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1250
1251         old_flags = vnic->flags;
1252         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1253         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1254         if (rc != 0)
1255                 vnic->flags = old_flags;
1256
1257         return rc;
1258 }
1259
1260 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1261 {
1262         struct bnxt *bp = eth_dev->data->dev_private;
1263         struct bnxt_vnic_info *vnic;
1264         uint32_t old_flags;
1265         int rc;
1266
1267         rc = is_bnxt_in_error(bp);
1268         if (rc)
1269                 return rc;
1270
1271         /* Filter settings will get applied when port is started */
1272         if (!eth_dev->data->dev_started)
1273                 return 0;
1274
1275         if (bp->vnic_info == NULL)
1276                 return 0;
1277
1278         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1279
1280         old_flags = vnic->flags;
1281         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1282         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1283         if (rc != 0)
1284                 vnic->flags = old_flags;
1285
1286         return rc;
1287 }
1288
1289 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1290 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1291 {
1292         if (qid >= bp->rx_nr_rings)
1293                 return NULL;
1294
1295         return bp->eth_dev->data->rx_queues[qid];
1296 }
1297
1298 /* Return rxq corresponding to a given rss table ring/group ID. */
1299 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1300 {
1301         struct bnxt_rx_queue *rxq;
1302         unsigned int i;
1303
1304         if (!BNXT_HAS_RING_GRPS(bp)) {
1305                 for (i = 0; i < bp->rx_nr_rings; i++) {
1306                         rxq = bp->eth_dev->data->rx_queues[i];
1307                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1308                                 return rxq->index;
1309                 }
1310         } else {
1311                 for (i = 0; i < bp->rx_nr_rings; i++) {
1312                         if (bp->grp_info[i].fw_grp_id == fwr)
1313                                 return i;
1314                 }
1315         }
1316
1317         return INVALID_HW_RING_ID;
1318 }
1319
1320 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1321                             struct rte_eth_rss_reta_entry64 *reta_conf,
1322                             uint16_t reta_size)
1323 {
1324         struct bnxt *bp = eth_dev->data->dev_private;
1325         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1326         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1327         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1328         uint16_t idx, sft;
1329         int i, rc;
1330
1331         rc = is_bnxt_in_error(bp);
1332         if (rc)
1333                 return rc;
1334
1335         if (!vnic->rss_table)
1336                 return -EINVAL;
1337
1338         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1339                 return -EINVAL;
1340
1341         if (reta_size != tbl_size) {
1342                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1343                         "(%d) must equal the size supported by the hardware "
1344                         "(%d)\n", reta_size, tbl_size);
1345                 return -EINVAL;
1346         }
1347
1348         for (i = 0; i < reta_size; i++) {
1349                 struct bnxt_rx_queue *rxq;
1350
1351                 idx = i / RTE_RETA_GROUP_SIZE;
1352                 sft = i % RTE_RETA_GROUP_SIZE;
1353
1354                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1355                         continue;
1356
1357                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1358                 if (!rxq) {
1359                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1360                         return -EINVAL;
1361                 }
1362
1363                 if (BNXT_CHIP_THOR(bp)) {
1364                         vnic->rss_table[i * 2] =
1365                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1366                         vnic->rss_table[i * 2 + 1] =
1367                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1368                 } else {
1369                         vnic->rss_table[i] =
1370                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1371                 }
1372         }
1373
1374         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1375         return 0;
1376 }
1377
1378 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1379                               struct rte_eth_rss_reta_entry64 *reta_conf,
1380                               uint16_t reta_size)
1381 {
1382         struct bnxt *bp = eth_dev->data->dev_private;
1383         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1384         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1385         uint16_t idx, sft, i;
1386         int rc;
1387
1388         rc = is_bnxt_in_error(bp);
1389         if (rc)
1390                 return rc;
1391
1392         /* Retrieve from the default VNIC */
1393         if (!vnic)
1394                 return -EINVAL;
1395         if (!vnic->rss_table)
1396                 return -EINVAL;
1397
1398         if (reta_size != tbl_size) {
1399                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1400                         "(%d) must equal the size supported by the hardware "
1401                         "(%d)\n", reta_size, tbl_size);
1402                 return -EINVAL;
1403         }
1404
1405         for (idx = 0, i = 0; i < reta_size; i++) {
1406                 idx = i / RTE_RETA_GROUP_SIZE;
1407                 sft = i % RTE_RETA_GROUP_SIZE;
1408
1409                 if (reta_conf[idx].mask & (1ULL << sft)) {
1410                         uint16_t qid;
1411
1412                         if (BNXT_CHIP_THOR(bp))
1413                                 qid = bnxt_rss_to_qid(bp,
1414                                                       vnic->rss_table[i * 2]);
1415                         else
1416                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1417
1418                         if (qid == INVALID_HW_RING_ID) {
1419                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1420                                 return -EINVAL;
1421                         }
1422                         reta_conf[idx].reta[sft] = qid;
1423                 }
1424         }
1425
1426         return 0;
1427 }
1428
1429 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1430                                    struct rte_eth_rss_conf *rss_conf)
1431 {
1432         struct bnxt *bp = eth_dev->data->dev_private;
1433         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1434         struct bnxt_vnic_info *vnic;
1435         int rc;
1436
1437         rc = is_bnxt_in_error(bp);
1438         if (rc)
1439                 return rc;
1440
1441         /*
1442          * If RSS enablement were different than dev_configure,
1443          * then return -EINVAL
1444          */
1445         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1446                 if (!rss_conf->rss_hf)
1447                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1448         } else {
1449                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1450                         return -EINVAL;
1451         }
1452
1453         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1454         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1455
1456         /* Update the default RSS VNIC(s) */
1457         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1458         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1459
1460         /*
1461          * If hashkey is not specified, use the previously configured
1462          * hashkey
1463          */
1464         if (!rss_conf->rss_key)
1465                 goto rss_config;
1466
1467         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1468                 PMD_DRV_LOG(ERR,
1469                             "Invalid hashkey length, should be 16 bytes\n");
1470                 return -EINVAL;
1471         }
1472         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1473
1474 rss_config:
1475         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1476         return 0;
1477 }
1478
1479 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1480                                      struct rte_eth_rss_conf *rss_conf)
1481 {
1482         struct bnxt *bp = eth_dev->data->dev_private;
1483         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1484         int len, rc;
1485         uint32_t hash_types;
1486
1487         rc = is_bnxt_in_error(bp);
1488         if (rc)
1489                 return rc;
1490
1491         /* RSS configuration is the same for all VNICs */
1492         if (vnic && vnic->rss_hash_key) {
1493                 if (rss_conf->rss_key) {
1494                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1495                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1496                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1497                 }
1498
1499                 hash_types = vnic->hash_type;
1500                 rss_conf->rss_hf = 0;
1501                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1502                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1503                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1504                 }
1505                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1506                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1507                         hash_types &=
1508                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1509                 }
1510                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1511                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1512                         hash_types &=
1513                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1514                 }
1515                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1516                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1517                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1518                 }
1519                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1520                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1521                         hash_types &=
1522                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1523                 }
1524                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1525                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1526                         hash_types &=
1527                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1528                 }
1529                 if (hash_types) {
1530                         PMD_DRV_LOG(ERR,
1531                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1532                                 vnic->hash_type);
1533                         return -ENOTSUP;
1534                 }
1535         } else {
1536                 rss_conf->rss_hf = 0;
1537         }
1538         return 0;
1539 }
1540
1541 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1542                                struct rte_eth_fc_conf *fc_conf)
1543 {
1544         struct bnxt *bp = dev->data->dev_private;
1545         struct rte_eth_link link_info;
1546         int rc;
1547
1548         rc = is_bnxt_in_error(bp);
1549         if (rc)
1550                 return rc;
1551
1552         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1553         if (rc)
1554                 return rc;
1555
1556         memset(fc_conf, 0, sizeof(*fc_conf));
1557         if (bp->link_info.auto_pause)
1558                 fc_conf->autoneg = 1;
1559         switch (bp->link_info.pause) {
1560         case 0:
1561                 fc_conf->mode = RTE_FC_NONE;
1562                 break;
1563         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1564                 fc_conf->mode = RTE_FC_TX_PAUSE;
1565                 break;
1566         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1567                 fc_conf->mode = RTE_FC_RX_PAUSE;
1568                 break;
1569         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1570                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1571                 fc_conf->mode = RTE_FC_FULL;
1572                 break;
1573         }
1574         return 0;
1575 }
1576
1577 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1578                                struct rte_eth_fc_conf *fc_conf)
1579 {
1580         struct bnxt *bp = dev->data->dev_private;
1581         int rc;
1582
1583         rc = is_bnxt_in_error(bp);
1584         if (rc)
1585                 return rc;
1586
1587         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1588                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1589                 return -ENOTSUP;
1590         }
1591
1592         switch (fc_conf->mode) {
1593         case RTE_FC_NONE:
1594                 bp->link_info.auto_pause = 0;
1595                 bp->link_info.force_pause = 0;
1596                 break;
1597         case RTE_FC_RX_PAUSE:
1598                 if (fc_conf->autoneg) {
1599                         bp->link_info.auto_pause =
1600                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1601                         bp->link_info.force_pause = 0;
1602                 } else {
1603                         bp->link_info.auto_pause = 0;
1604                         bp->link_info.force_pause =
1605                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1606                 }
1607                 break;
1608         case RTE_FC_TX_PAUSE:
1609                 if (fc_conf->autoneg) {
1610                         bp->link_info.auto_pause =
1611                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1612                         bp->link_info.force_pause = 0;
1613                 } else {
1614                         bp->link_info.auto_pause = 0;
1615                         bp->link_info.force_pause =
1616                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1617                 }
1618                 break;
1619         case RTE_FC_FULL:
1620                 if (fc_conf->autoneg) {
1621                         bp->link_info.auto_pause =
1622                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1623                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1624                         bp->link_info.force_pause = 0;
1625                 } else {
1626                         bp->link_info.auto_pause = 0;
1627                         bp->link_info.force_pause =
1628                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1629                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1630                 }
1631                 break;
1632         }
1633         return bnxt_set_hwrm_link_config(bp, true);
1634 }
1635
1636 /* Add UDP tunneling port */
1637 static int
1638 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1639                          struct rte_eth_udp_tunnel *udp_tunnel)
1640 {
1641         struct bnxt *bp = eth_dev->data->dev_private;
1642         uint16_t tunnel_type = 0;
1643         int rc = 0;
1644
1645         rc = is_bnxt_in_error(bp);
1646         if (rc)
1647                 return rc;
1648
1649         switch (udp_tunnel->prot_type) {
1650         case RTE_TUNNEL_TYPE_VXLAN:
1651                 if (bp->vxlan_port_cnt) {
1652                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1653                                 udp_tunnel->udp_port);
1654                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1655                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1656                                 return -ENOSPC;
1657                         }
1658                         bp->vxlan_port_cnt++;
1659                         return 0;
1660                 }
1661                 tunnel_type =
1662                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1663                 bp->vxlan_port_cnt++;
1664                 break;
1665         case RTE_TUNNEL_TYPE_GENEVE:
1666                 if (bp->geneve_port_cnt) {
1667                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1668                                 udp_tunnel->udp_port);
1669                         if (bp->geneve_port != udp_tunnel->udp_port) {
1670                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1671                                 return -ENOSPC;
1672                         }
1673                         bp->geneve_port_cnt++;
1674                         return 0;
1675                 }
1676                 tunnel_type =
1677                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1678                 bp->geneve_port_cnt++;
1679                 break;
1680         default:
1681                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1682                 return -ENOTSUP;
1683         }
1684         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1685                                              tunnel_type);
1686         return rc;
1687 }
1688
1689 static int
1690 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1691                          struct rte_eth_udp_tunnel *udp_tunnel)
1692 {
1693         struct bnxt *bp = eth_dev->data->dev_private;
1694         uint16_t tunnel_type = 0;
1695         uint16_t port = 0;
1696         int rc = 0;
1697
1698         rc = is_bnxt_in_error(bp);
1699         if (rc)
1700                 return rc;
1701
1702         switch (udp_tunnel->prot_type) {
1703         case RTE_TUNNEL_TYPE_VXLAN:
1704                 if (!bp->vxlan_port_cnt) {
1705                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1706                         return -EINVAL;
1707                 }
1708                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1709                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1710                                 udp_tunnel->udp_port, bp->vxlan_port);
1711                         return -EINVAL;
1712                 }
1713                 if (--bp->vxlan_port_cnt)
1714                         return 0;
1715
1716                 tunnel_type =
1717                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1718                 port = bp->vxlan_fw_dst_port_id;
1719                 break;
1720         case RTE_TUNNEL_TYPE_GENEVE:
1721                 if (!bp->geneve_port_cnt) {
1722                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1723                         return -EINVAL;
1724                 }
1725                 if (bp->geneve_port != udp_tunnel->udp_port) {
1726                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1727                                 udp_tunnel->udp_port, bp->geneve_port);
1728                         return -EINVAL;
1729                 }
1730                 if (--bp->geneve_port_cnt)
1731                         return 0;
1732
1733                 tunnel_type =
1734                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1735                 port = bp->geneve_fw_dst_port_id;
1736                 break;
1737         default:
1738                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1739                 return -ENOTSUP;
1740         }
1741
1742         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1743         if (!rc) {
1744                 if (tunnel_type ==
1745                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1746                         bp->vxlan_port = 0;
1747                 if (tunnel_type ==
1748                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1749                         bp->geneve_port = 0;
1750         }
1751         return rc;
1752 }
1753
1754 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1755 {
1756         struct bnxt_filter_info *filter;
1757         struct bnxt_vnic_info *vnic;
1758         int rc = 0;
1759         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1760
1761         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1762         filter = STAILQ_FIRST(&vnic->filter);
1763         while (filter) {
1764                 /* Search for this matching MAC+VLAN filter */
1765                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1766                         /* Delete the filter */
1767                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1768                         if (rc)
1769                                 return rc;
1770                         STAILQ_REMOVE(&vnic->filter, filter,
1771                                       bnxt_filter_info, next);
1772                         bnxt_free_filter(bp, filter);
1773                         PMD_DRV_LOG(INFO,
1774                                     "Deleted vlan filter for %d\n",
1775                                     vlan_id);
1776                         return 0;
1777                 }
1778                 filter = STAILQ_NEXT(filter, next);
1779         }
1780         return -ENOENT;
1781 }
1782
1783 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1784 {
1785         struct bnxt_filter_info *filter;
1786         struct bnxt_vnic_info *vnic;
1787         int rc = 0;
1788         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1789                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1790         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1791
1792         /* Implementation notes on the use of VNIC in this command:
1793          *
1794          * By default, these filters belong to default vnic for the function.
1795          * Once these filters are set up, only destination VNIC can be modified.
1796          * If the destination VNIC is not specified in this command,
1797          * then the HWRM shall only create an l2 context id.
1798          */
1799
1800         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1801         filter = STAILQ_FIRST(&vnic->filter);
1802         /* Check if the VLAN has already been added */
1803         while (filter) {
1804                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1805                         return -EEXIST;
1806
1807                 filter = STAILQ_NEXT(filter, next);
1808         }
1809
1810         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1811          * command to create MAC+VLAN filter with the right flags, enables set.
1812          */
1813         filter = bnxt_alloc_filter(bp);
1814         if (!filter) {
1815                 PMD_DRV_LOG(ERR,
1816                             "MAC/VLAN filter alloc failed\n");
1817                 return -ENOMEM;
1818         }
1819         /* MAC + VLAN ID filter */
1820         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1821          * untagged packets are received
1822          *
1823          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1824          * packets and only the programmed vlan's packets are received
1825          */
1826         filter->l2_ivlan = vlan_id;
1827         filter->l2_ivlan_mask = 0x0FFF;
1828         filter->enables |= en;
1829         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1830
1831         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1832         if (rc) {
1833                 /* Free the newly allocated filter as we were
1834                  * not able to create the filter in hardware.
1835                  */
1836                 bnxt_free_filter(bp, filter);
1837                 return rc;
1838         }
1839
1840         filter->mac_index = 0;
1841         /* Add this new filter to the list */
1842         if (vlan_id == 0)
1843                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1844         else
1845                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1846
1847         PMD_DRV_LOG(INFO,
1848                     "Added Vlan filter for %d\n", vlan_id);
1849         return rc;
1850 }
1851
1852 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1853                 uint16_t vlan_id, int on)
1854 {
1855         struct bnxt *bp = eth_dev->data->dev_private;
1856         int rc;
1857
1858         rc = is_bnxt_in_error(bp);
1859         if (rc)
1860                 return rc;
1861
1862         /* These operations apply to ALL existing MAC/VLAN filters */
1863         if (on)
1864                 return bnxt_add_vlan_filter(bp, vlan_id);
1865         else
1866                 return bnxt_del_vlan_filter(bp, vlan_id);
1867 }
1868
1869 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1870                                     struct bnxt_vnic_info *vnic)
1871 {
1872         struct bnxt_filter_info *filter;
1873         int rc;
1874
1875         filter = STAILQ_FIRST(&vnic->filter);
1876         while (filter) {
1877                 if (filter->mac_index == 0 &&
1878                     !memcmp(filter->l2_addr, bp->mac_addr,
1879                             RTE_ETHER_ADDR_LEN)) {
1880                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1881                         if (!rc) {
1882                                 STAILQ_REMOVE(&vnic->filter, filter,
1883                                               bnxt_filter_info, next);
1884                                 bnxt_free_filter(bp, filter);
1885                         }
1886                         return rc;
1887                 }
1888                 filter = STAILQ_NEXT(filter, next);
1889         }
1890         return 0;
1891 }
1892
1893 static int
1894 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
1895 {
1896         struct bnxt_vnic_info *vnic;
1897         unsigned int i;
1898         int rc;
1899
1900         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1901         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1902                 /* Remove any VLAN filters programmed */
1903                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1904                         bnxt_del_vlan_filter(bp, i);
1905
1906                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1907                 if (rc)
1908                         return rc;
1909         } else {
1910                 /* Default filter will allow packets that match the
1911                  * dest mac. So, it has to be deleted, otherwise, we
1912                  * will endup receiving vlan packets for which the
1913                  * filter is not programmed, when hw-vlan-filter
1914                  * configuration is ON
1915                  */
1916                 bnxt_del_dflt_mac_filter(bp, vnic);
1917                 /* This filter will allow only untagged packets */
1918                 bnxt_add_vlan_filter(bp, 0);
1919         }
1920         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1921                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1922
1923         return 0;
1924 }
1925
1926 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
1927 {
1928         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
1929         unsigned int i;
1930         int rc;
1931
1932         /* Destroy vnic filters and vnic */
1933         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1934             DEV_RX_OFFLOAD_VLAN_FILTER) {
1935                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1936                         bnxt_del_vlan_filter(bp, i);
1937         }
1938         bnxt_del_dflt_mac_filter(bp, vnic);
1939
1940         rc = bnxt_hwrm_vnic_free(bp, vnic);
1941         if (rc)
1942                 return rc;
1943
1944         rte_free(vnic->fw_grp_ids);
1945         vnic->fw_grp_ids = NULL;
1946
1947         return 0;
1948 }
1949
1950 static int
1951 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
1952 {
1953         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1954         int rc;
1955
1956         /* Destroy, recreate and reconfigure the default vnic */
1957         rc = bnxt_free_one_vnic(bp, 0);
1958         if (rc)
1959                 return rc;
1960
1961         /* default vnic 0 */
1962         rc = bnxt_setup_one_vnic(bp, 0);
1963         if (rc)
1964                 return rc;
1965
1966         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1967             DEV_RX_OFFLOAD_VLAN_FILTER) {
1968                 rc = bnxt_add_vlan_filter(bp, 0);
1969                 if (rc)
1970                         return rc;
1971                 rc = bnxt_restore_vlan_filters(bp);
1972                 if (rc)
1973                         return rc;
1974         } else {
1975                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1976                 if (rc)
1977                         return rc;
1978         }
1979
1980         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1981         if (rc)
1982                 return rc;
1983
1984         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1985                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1986
1987         return rc;
1988 }
1989
1990 static int
1991 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1992 {
1993         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1994         struct bnxt *bp = dev->data->dev_private;
1995         int rc;
1996
1997         rc = is_bnxt_in_error(bp);
1998         if (rc)
1999                 return rc;
2000
2001         /* Filter settings will get applied when port is started */
2002         if (!dev->data->dev_started)
2003                 return 0;
2004
2005         if (mask & ETH_VLAN_FILTER_MASK) {
2006                 /* Enable or disable VLAN filtering */
2007                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2008                 if (rc)
2009                         return rc;
2010         }
2011
2012         if (mask & ETH_VLAN_STRIP_MASK) {
2013                 /* Enable or disable VLAN stripping */
2014                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2015                 if (rc)
2016                         return rc;
2017         }
2018
2019         if (mask & ETH_VLAN_EXTEND_MASK) {
2020                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2021                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2022                 else
2023                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2024         }
2025
2026         return 0;
2027 }
2028
2029 static int
2030 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2031                       uint16_t tpid)
2032 {
2033         struct bnxt *bp = dev->data->dev_private;
2034         int qinq = dev->data->dev_conf.rxmode.offloads &
2035                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2036
2037         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2038             vlan_type != ETH_VLAN_TYPE_OUTER) {
2039                 PMD_DRV_LOG(ERR,
2040                             "Unsupported vlan type.");
2041                 return -EINVAL;
2042         }
2043         if (!qinq) {
2044                 PMD_DRV_LOG(ERR,
2045                             "QinQ not enabled. Needs to be ON as we can "
2046                             "accelerate only outer vlan\n");
2047                 return -EINVAL;
2048         }
2049
2050         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2051                 switch (tpid) {
2052                 case RTE_ETHER_TYPE_QINQ:
2053                         bp->outer_tpid_bd =
2054                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2055                                 break;
2056                 case RTE_ETHER_TYPE_VLAN:
2057                         bp->outer_tpid_bd =
2058                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2059                                 break;
2060                 case 0x9100:
2061                         bp->outer_tpid_bd =
2062                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2063                                 break;
2064                 case 0x9200:
2065                         bp->outer_tpid_bd =
2066                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2067                                 break;
2068                 case 0x9300:
2069                         bp->outer_tpid_bd =
2070                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2071                                 break;
2072                 default:
2073                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2074                         return -EINVAL;
2075                 }
2076                 bp->outer_tpid_bd |= tpid;
2077                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2078         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2079                 PMD_DRV_LOG(ERR,
2080                             "Can accelerate only outer vlan in QinQ\n");
2081                 return -EINVAL;
2082         }
2083
2084         return 0;
2085 }
2086
2087 static int
2088 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2089                              struct rte_ether_addr *addr)
2090 {
2091         struct bnxt *bp = dev->data->dev_private;
2092         /* Default Filter is tied to VNIC 0 */
2093         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2094         int rc;
2095
2096         rc = is_bnxt_in_error(bp);
2097         if (rc)
2098                 return rc;
2099
2100         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2101                 return -EPERM;
2102
2103         if (rte_is_zero_ether_addr(addr))
2104                 return -EINVAL;
2105
2106         /* Filter settings will get applied when port is started */
2107         if (!dev->data->dev_started)
2108                 return 0;
2109
2110         /* Check if the requested MAC is already added */
2111         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2112                 return 0;
2113
2114         /* Destroy filter and re-create it */
2115         bnxt_del_dflt_mac_filter(bp, vnic);
2116
2117         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2118         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2119                 /* This filter will allow only untagged packets */
2120                 rc = bnxt_add_vlan_filter(bp, 0);
2121         } else {
2122                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2123         }
2124
2125         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2126         return rc;
2127 }
2128
2129 static int
2130 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2131                           struct rte_ether_addr *mc_addr_set,
2132                           uint32_t nb_mc_addr)
2133 {
2134         struct bnxt *bp = eth_dev->data->dev_private;
2135         char *mc_addr_list = (char *)mc_addr_set;
2136         struct bnxt_vnic_info *vnic;
2137         uint32_t off = 0, i = 0;
2138         int rc;
2139
2140         rc = is_bnxt_in_error(bp);
2141         if (rc)
2142                 return rc;
2143
2144         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2145
2146         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2147                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2148                 goto allmulti;
2149         }
2150
2151         /* TODO Check for Duplicate mcast addresses */
2152         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2153         for (i = 0; i < nb_mc_addr; i++) {
2154                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2155                         RTE_ETHER_ADDR_LEN);
2156                 off += RTE_ETHER_ADDR_LEN;
2157         }
2158
2159         vnic->mc_addr_cnt = i;
2160         if (vnic->mc_addr_cnt)
2161                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2162         else
2163                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2164
2165 allmulti:
2166         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2167 }
2168
2169 static int
2170 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2171 {
2172         struct bnxt *bp = dev->data->dev_private;
2173         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2174         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2175         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2176         int ret;
2177
2178         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2179                         fw_major, fw_minor, fw_updt);
2180
2181         ret += 1; /* add the size of '\0' */
2182         if (fw_size < (uint32_t)ret)
2183                 return ret;
2184         else
2185                 return 0;
2186 }
2187
2188 static void
2189 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2190         struct rte_eth_rxq_info *qinfo)
2191 {
2192         struct bnxt *bp = dev->data->dev_private;
2193         struct bnxt_rx_queue *rxq;
2194
2195         if (is_bnxt_in_error(bp))
2196                 return;
2197
2198         rxq = dev->data->rx_queues[queue_id];
2199
2200         qinfo->mp = rxq->mb_pool;
2201         qinfo->scattered_rx = dev->data->scattered_rx;
2202         qinfo->nb_desc = rxq->nb_rx_desc;
2203
2204         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2205         qinfo->conf.rx_drop_en = 0;
2206         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2207 }
2208
2209 static void
2210 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2211         struct rte_eth_txq_info *qinfo)
2212 {
2213         struct bnxt *bp = dev->data->dev_private;
2214         struct bnxt_tx_queue *txq;
2215
2216         if (is_bnxt_in_error(bp))
2217                 return;
2218
2219         txq = dev->data->tx_queues[queue_id];
2220
2221         qinfo->nb_desc = txq->nb_tx_desc;
2222
2223         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2224         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2225         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2226
2227         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2228         qinfo->conf.tx_rs_thresh = 0;
2229         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2230 }
2231
2232 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2233 {
2234         struct bnxt *bp = eth_dev->data->dev_private;
2235         uint32_t new_pkt_size;
2236         uint32_t rc = 0;
2237         uint32_t i;
2238
2239         rc = is_bnxt_in_error(bp);
2240         if (rc)
2241                 return rc;
2242
2243         /* Exit if receive queues are not configured yet */
2244         if (!eth_dev->data->nb_rx_queues)
2245                 return rc;
2246
2247         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2248                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2249
2250 #ifdef RTE_ARCH_X86
2251         /*
2252          * If vector-mode tx/rx is active, disallow any MTU change that would
2253          * require scattered receive support.
2254          */
2255         if (eth_dev->data->dev_started &&
2256             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2257              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2258             (new_pkt_size >
2259              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2260                 PMD_DRV_LOG(ERR,
2261                             "MTU change would require scattered rx support. ");
2262                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2263                 return -EINVAL;
2264         }
2265 #endif
2266
2267         if (new_mtu > RTE_ETHER_MTU) {
2268                 bp->flags |= BNXT_FLAG_JUMBO;
2269                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2270                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2271         } else {
2272                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2273                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2274                 bp->flags &= ~BNXT_FLAG_JUMBO;
2275         }
2276
2277         /* Is there a change in mtu setting? */
2278         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2279                 return rc;
2280
2281         for (i = 0; i < bp->nr_vnics; i++) {
2282                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2283                 uint16_t size = 0;
2284
2285                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2286                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2287                 if (rc)
2288                         break;
2289
2290                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2291                 size -= RTE_PKTMBUF_HEADROOM;
2292
2293                 if (size < new_mtu) {
2294                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2295                         if (rc)
2296                                 return rc;
2297                 }
2298         }
2299
2300         if (!rc)
2301                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2302
2303         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2304
2305         return rc;
2306 }
2307
2308 static int
2309 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2310 {
2311         struct bnxt *bp = dev->data->dev_private;
2312         uint16_t vlan = bp->vlan;
2313         int rc;
2314
2315         rc = is_bnxt_in_error(bp);
2316         if (rc)
2317                 return rc;
2318
2319         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2320                 PMD_DRV_LOG(ERR,
2321                         "PVID cannot be modified for this function\n");
2322                 return -ENOTSUP;
2323         }
2324         bp->vlan = on ? pvid : 0;
2325
2326         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2327         if (rc)
2328                 bp->vlan = vlan;
2329         return rc;
2330 }
2331
2332 static int
2333 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2334 {
2335         struct bnxt *bp = dev->data->dev_private;
2336         int rc;
2337
2338         rc = is_bnxt_in_error(bp);
2339         if (rc)
2340                 return rc;
2341
2342         return bnxt_hwrm_port_led_cfg(bp, true);
2343 }
2344
2345 static int
2346 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2347 {
2348         struct bnxt *bp = dev->data->dev_private;
2349         int rc;
2350
2351         rc = is_bnxt_in_error(bp);
2352         if (rc)
2353                 return rc;
2354
2355         return bnxt_hwrm_port_led_cfg(bp, false);
2356 }
2357
2358 static uint32_t
2359 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2360 {
2361         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2362         uint32_t desc = 0, raw_cons = 0, cons;
2363         struct bnxt_cp_ring_info *cpr;
2364         struct bnxt_rx_queue *rxq;
2365         struct rx_pkt_cmpl *rxcmp;
2366         int rc;
2367
2368         rc = is_bnxt_in_error(bp);
2369         if (rc)
2370                 return rc;
2371
2372         rxq = dev->data->rx_queues[rx_queue_id];
2373         cpr = rxq->cp_ring;
2374         raw_cons = cpr->cp_raw_cons;
2375
2376         while (1) {
2377                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2378                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2379                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2380
2381                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2382                         break;
2383                 } else {
2384                         raw_cons++;
2385                         desc++;
2386                 }
2387         }
2388
2389         return desc;
2390 }
2391
2392 static int
2393 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2394 {
2395         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2396         struct bnxt_rx_ring_info *rxr;
2397         struct bnxt_cp_ring_info *cpr;
2398         struct bnxt_sw_rx_bd *rx_buf;
2399         struct rx_pkt_cmpl *rxcmp;
2400         uint32_t cons, cp_cons;
2401         int rc;
2402
2403         if (!rxq)
2404                 return -EINVAL;
2405
2406         rc = is_bnxt_in_error(rxq->bp);
2407         if (rc)
2408                 return rc;
2409
2410         cpr = rxq->cp_ring;
2411         rxr = rxq->rx_ring;
2412
2413         if (offset >= rxq->nb_rx_desc)
2414                 return -EINVAL;
2415
2416         cons = RING_CMP(cpr->cp_ring_struct, offset);
2417         cp_cons = cpr->cp_raw_cons;
2418         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2419
2420         if (cons > cp_cons) {
2421                 if (CMPL_VALID(rxcmp, cpr->valid))
2422                         return RTE_ETH_RX_DESC_DONE;
2423         } else {
2424                 if (CMPL_VALID(rxcmp, !cpr->valid))
2425                         return RTE_ETH_RX_DESC_DONE;
2426         }
2427         rx_buf = &rxr->rx_buf_ring[cons];
2428         if (rx_buf->mbuf == NULL)
2429                 return RTE_ETH_RX_DESC_UNAVAIL;
2430
2431
2432         return RTE_ETH_RX_DESC_AVAIL;
2433 }
2434
2435 static int
2436 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2437 {
2438         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2439         struct bnxt_tx_ring_info *txr;
2440         struct bnxt_cp_ring_info *cpr;
2441         struct bnxt_sw_tx_bd *tx_buf;
2442         struct tx_pkt_cmpl *txcmp;
2443         uint32_t cons, cp_cons;
2444         int rc;
2445
2446         if (!txq)
2447                 return -EINVAL;
2448
2449         rc = is_bnxt_in_error(txq->bp);
2450         if (rc)
2451                 return rc;
2452
2453         cpr = txq->cp_ring;
2454         txr = txq->tx_ring;
2455
2456         if (offset >= txq->nb_tx_desc)
2457                 return -EINVAL;
2458
2459         cons = RING_CMP(cpr->cp_ring_struct, offset);
2460         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2461         cp_cons = cpr->cp_raw_cons;
2462
2463         if (cons > cp_cons) {
2464                 if (CMPL_VALID(txcmp, cpr->valid))
2465                         return RTE_ETH_TX_DESC_UNAVAIL;
2466         } else {
2467                 if (CMPL_VALID(txcmp, !cpr->valid))
2468                         return RTE_ETH_TX_DESC_UNAVAIL;
2469         }
2470         tx_buf = &txr->tx_buf_ring[cons];
2471         if (tx_buf->mbuf == NULL)
2472                 return RTE_ETH_TX_DESC_DONE;
2473
2474         return RTE_ETH_TX_DESC_FULL;
2475 }
2476
2477 static struct bnxt_filter_info *
2478 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2479                                 struct rte_eth_ethertype_filter *efilter,
2480                                 struct bnxt_vnic_info *vnic0,
2481                                 struct bnxt_vnic_info *vnic,
2482                                 int *ret)
2483 {
2484         struct bnxt_filter_info *mfilter = NULL;
2485         int match = 0;
2486         *ret = 0;
2487
2488         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2489                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2490                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2491                         " ethertype filter.", efilter->ether_type);
2492                 *ret = -EINVAL;
2493                 goto exit;
2494         }
2495         if (efilter->queue >= bp->rx_nr_rings) {
2496                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2497                 *ret = -EINVAL;
2498                 goto exit;
2499         }
2500
2501         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2502         vnic = &bp->vnic_info[efilter->queue];
2503         if (vnic == NULL) {
2504                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2505                 *ret = -EINVAL;
2506                 goto exit;
2507         }
2508
2509         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2510                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2511                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2512                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2513                              mfilter->flags ==
2514                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2515                              mfilter->ethertype == efilter->ether_type)) {
2516                                 match = 1;
2517                                 break;
2518                         }
2519                 }
2520         } else {
2521                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2522                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2523                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2524                              mfilter->ethertype == efilter->ether_type &&
2525                              mfilter->flags ==
2526                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2527                                 match = 1;
2528                                 break;
2529                         }
2530         }
2531
2532         if (match)
2533                 *ret = -EEXIST;
2534
2535 exit:
2536         return mfilter;
2537 }
2538
2539 static int
2540 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2541                         enum rte_filter_op filter_op,
2542                         void *arg)
2543 {
2544         struct bnxt *bp = dev->data->dev_private;
2545         struct rte_eth_ethertype_filter *efilter =
2546                         (struct rte_eth_ethertype_filter *)arg;
2547         struct bnxt_filter_info *bfilter, *filter1;
2548         struct bnxt_vnic_info *vnic, *vnic0;
2549         int ret;
2550
2551         if (filter_op == RTE_ETH_FILTER_NOP)
2552                 return 0;
2553
2554         if (arg == NULL) {
2555                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2556                             filter_op);
2557                 return -EINVAL;
2558         }
2559
2560         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2561         vnic = &bp->vnic_info[efilter->queue];
2562
2563         switch (filter_op) {
2564         case RTE_ETH_FILTER_ADD:
2565                 bnxt_match_and_validate_ether_filter(bp, efilter,
2566                                                         vnic0, vnic, &ret);
2567                 if (ret < 0)
2568                         return ret;
2569
2570                 bfilter = bnxt_get_unused_filter(bp);
2571                 if (bfilter == NULL) {
2572                         PMD_DRV_LOG(ERR,
2573                                 "Not enough resources for a new filter.\n");
2574                         return -ENOMEM;
2575                 }
2576                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2577                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2578                        RTE_ETHER_ADDR_LEN);
2579                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2580                        RTE_ETHER_ADDR_LEN);
2581                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2582                 bfilter->ethertype = efilter->ether_type;
2583                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2584
2585                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2586                 if (filter1 == NULL) {
2587                         ret = -EINVAL;
2588                         goto cleanup;
2589                 }
2590                 bfilter->enables |=
2591                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2592                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2593
2594                 bfilter->dst_id = vnic->fw_vnic_id;
2595
2596                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2597                         bfilter->flags =
2598                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2599                 }
2600
2601                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2602                 if (ret)
2603                         goto cleanup;
2604                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2605                 break;
2606         case RTE_ETH_FILTER_DELETE:
2607                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2608                                                         vnic0, vnic, &ret);
2609                 if (ret == -EEXIST) {
2610                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2611
2612                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2613                                       next);
2614                         bnxt_free_filter(bp, filter1);
2615                 } else if (ret == 0) {
2616                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2617                 }
2618                 break;
2619         default:
2620                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2621                 ret = -EINVAL;
2622                 goto error;
2623         }
2624         return ret;
2625 cleanup:
2626         bnxt_free_filter(bp, bfilter);
2627 error:
2628         return ret;
2629 }
2630
2631 static inline int
2632 parse_ntuple_filter(struct bnxt *bp,
2633                     struct rte_eth_ntuple_filter *nfilter,
2634                     struct bnxt_filter_info *bfilter)
2635 {
2636         uint32_t en = 0;
2637
2638         if (nfilter->queue >= bp->rx_nr_rings) {
2639                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2640                 return -EINVAL;
2641         }
2642
2643         switch (nfilter->dst_port_mask) {
2644         case UINT16_MAX:
2645                 bfilter->dst_port_mask = -1;
2646                 bfilter->dst_port = nfilter->dst_port;
2647                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2648                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2649                 break;
2650         default:
2651                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2652                 return -EINVAL;
2653         }
2654
2655         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2656         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2657
2658         switch (nfilter->proto_mask) {
2659         case UINT8_MAX:
2660                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2661                         bfilter->ip_protocol = 17;
2662                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2663                         bfilter->ip_protocol = 6;
2664                 else
2665                         return -EINVAL;
2666                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2667                 break;
2668         default:
2669                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2670                 return -EINVAL;
2671         }
2672
2673         switch (nfilter->dst_ip_mask) {
2674         case UINT32_MAX:
2675                 bfilter->dst_ipaddr_mask[0] = -1;
2676                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2677                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2678                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2679                 break;
2680         default:
2681                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2682                 return -EINVAL;
2683         }
2684
2685         switch (nfilter->src_ip_mask) {
2686         case UINT32_MAX:
2687                 bfilter->src_ipaddr_mask[0] = -1;
2688                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2689                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2690                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2691                 break;
2692         default:
2693                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2694                 return -EINVAL;
2695         }
2696
2697         switch (nfilter->src_port_mask) {
2698         case UINT16_MAX:
2699                 bfilter->src_port_mask = -1;
2700                 bfilter->src_port = nfilter->src_port;
2701                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2702                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2703                 break;
2704         default:
2705                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2706                 return -EINVAL;
2707         }
2708
2709         bfilter->enables = en;
2710         return 0;
2711 }
2712
2713 static struct bnxt_filter_info*
2714 bnxt_match_ntuple_filter(struct bnxt *bp,
2715                          struct bnxt_filter_info *bfilter,
2716                          struct bnxt_vnic_info **mvnic)
2717 {
2718         struct bnxt_filter_info *mfilter = NULL;
2719         int i;
2720
2721         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2722                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2723                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2724                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2725                             bfilter->src_ipaddr_mask[0] ==
2726                             mfilter->src_ipaddr_mask[0] &&
2727                             bfilter->src_port == mfilter->src_port &&
2728                             bfilter->src_port_mask == mfilter->src_port_mask &&
2729                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2730                             bfilter->dst_ipaddr_mask[0] ==
2731                             mfilter->dst_ipaddr_mask[0] &&
2732                             bfilter->dst_port == mfilter->dst_port &&
2733                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2734                             bfilter->flags == mfilter->flags &&
2735                             bfilter->enables == mfilter->enables) {
2736                                 if (mvnic)
2737                                         *mvnic = vnic;
2738                                 return mfilter;
2739                         }
2740                 }
2741         }
2742         return NULL;
2743 }
2744
2745 static int
2746 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2747                        struct rte_eth_ntuple_filter *nfilter,
2748                        enum rte_filter_op filter_op)
2749 {
2750         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2751         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2752         int ret;
2753
2754         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2755                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2756                 return -EINVAL;
2757         }
2758
2759         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2760                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2761                 return -EINVAL;
2762         }
2763
2764         bfilter = bnxt_get_unused_filter(bp);
2765         if (bfilter == NULL) {
2766                 PMD_DRV_LOG(ERR,
2767                         "Not enough resources for a new filter.\n");
2768                 return -ENOMEM;
2769         }
2770         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2771         if (ret < 0)
2772                 goto free_filter;
2773
2774         vnic = &bp->vnic_info[nfilter->queue];
2775         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2776         filter1 = STAILQ_FIRST(&vnic0->filter);
2777         if (filter1 == NULL) {
2778                 ret = -EINVAL;
2779                 goto free_filter;
2780         }
2781
2782         bfilter->dst_id = vnic->fw_vnic_id;
2783         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2784         bfilter->enables |=
2785                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2786         bfilter->ethertype = 0x800;
2787         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2788
2789         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2790
2791         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2792             bfilter->dst_id == mfilter->dst_id) {
2793                 PMD_DRV_LOG(ERR, "filter exists.\n");
2794                 ret = -EEXIST;
2795                 goto free_filter;
2796         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2797                    bfilter->dst_id != mfilter->dst_id) {
2798                 mfilter->dst_id = vnic->fw_vnic_id;
2799                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2800                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2801                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2802                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2803                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2804                 goto free_filter;
2805         }
2806         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2807                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2808                 ret = -ENOENT;
2809                 goto free_filter;
2810         }
2811
2812         if (filter_op == RTE_ETH_FILTER_ADD) {
2813                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2814                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2815                 if (ret)
2816                         goto free_filter;
2817                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2818         } else {
2819                 if (mfilter == NULL) {
2820                         /* This should not happen. But for Coverity! */
2821                         ret = -ENOENT;
2822                         goto free_filter;
2823                 }
2824                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2825
2826                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2827                 bnxt_free_filter(bp, mfilter);
2828                 bnxt_free_filter(bp, bfilter);
2829         }
2830
2831         return 0;
2832 free_filter:
2833         bnxt_free_filter(bp, bfilter);
2834         return ret;
2835 }
2836
2837 static int
2838 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2839                         enum rte_filter_op filter_op,
2840                         void *arg)
2841 {
2842         struct bnxt *bp = dev->data->dev_private;
2843         int ret;
2844
2845         if (filter_op == RTE_ETH_FILTER_NOP)
2846                 return 0;
2847
2848         if (arg == NULL) {
2849                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2850                             filter_op);
2851                 return -EINVAL;
2852         }
2853
2854         switch (filter_op) {
2855         case RTE_ETH_FILTER_ADD:
2856                 ret = bnxt_cfg_ntuple_filter(bp,
2857                         (struct rte_eth_ntuple_filter *)arg,
2858                         filter_op);
2859                 break;
2860         case RTE_ETH_FILTER_DELETE:
2861                 ret = bnxt_cfg_ntuple_filter(bp,
2862                         (struct rte_eth_ntuple_filter *)arg,
2863                         filter_op);
2864                 break;
2865         default:
2866                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2867                 ret = -EINVAL;
2868                 break;
2869         }
2870         return ret;
2871 }
2872
2873 static int
2874 bnxt_parse_fdir_filter(struct bnxt *bp,
2875                        struct rte_eth_fdir_filter *fdir,
2876                        struct bnxt_filter_info *filter)
2877 {
2878         enum rte_fdir_mode fdir_mode =
2879                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2880         struct bnxt_vnic_info *vnic0, *vnic;
2881         struct bnxt_filter_info *filter1;
2882         uint32_t en = 0;
2883         int i;
2884
2885         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2886                 return -EINVAL;
2887
2888         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2889         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2890
2891         switch (fdir->input.flow_type) {
2892         case RTE_ETH_FLOW_IPV4:
2893         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2894                 /* FALLTHROUGH */
2895                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2896                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2897                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2898                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2899                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2900                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2901                 filter->ip_addr_type =
2902                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2903                 filter->src_ipaddr_mask[0] = 0xffffffff;
2904                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2905                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2906                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2907                 filter->ethertype = 0x800;
2908                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2909                 break;
2910         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2911                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2912                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2913                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2914                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2915                 filter->dst_port_mask = 0xffff;
2916                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2917                 filter->src_port_mask = 0xffff;
2918                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2919                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2920                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2921                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2922                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2923                 filter->ip_protocol = 6;
2924                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2925                 filter->ip_addr_type =
2926                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2927                 filter->src_ipaddr_mask[0] = 0xffffffff;
2928                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2929                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2930                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2931                 filter->ethertype = 0x800;
2932                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2933                 break;
2934         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2935                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2936                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2937                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2938                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2939                 filter->dst_port_mask = 0xffff;
2940                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2941                 filter->src_port_mask = 0xffff;
2942                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2943                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2944                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2945                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2946                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2947                 filter->ip_protocol = 17;
2948                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2949                 filter->ip_addr_type =
2950                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2951                 filter->src_ipaddr_mask[0] = 0xffffffff;
2952                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2953                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2954                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2955                 filter->ethertype = 0x800;
2956                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2957                 break;
2958         case RTE_ETH_FLOW_IPV6:
2959         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2960                 /* FALLTHROUGH */
2961                 filter->ip_addr_type =
2962                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2963                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2964                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2965                 rte_memcpy(filter->src_ipaddr,
2966                            fdir->input.flow.ipv6_flow.src_ip, 16);
2967                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2968                 rte_memcpy(filter->dst_ipaddr,
2969                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2970                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2971                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2972                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2973                 memset(filter->src_ipaddr_mask, 0xff, 16);
2974                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2975                 filter->ethertype = 0x86dd;
2976                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2977                 break;
2978         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2979                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2980                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2981                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2982                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2983                 filter->dst_port_mask = 0xffff;
2984                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2985                 filter->src_port_mask = 0xffff;
2986                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2987                 filter->ip_addr_type =
2988                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2989                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2990                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2991                 rte_memcpy(filter->src_ipaddr,
2992                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2993                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2994                 rte_memcpy(filter->dst_ipaddr,
2995                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2996                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2997                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2998                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2999                 memset(filter->src_ipaddr_mask, 0xff, 16);
3000                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3001                 filter->ethertype = 0x86dd;
3002                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3003                 break;
3004         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3005                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3006                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3007                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3008                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3009                 filter->dst_port_mask = 0xffff;
3010                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3011                 filter->src_port_mask = 0xffff;
3012                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3013                 filter->ip_addr_type =
3014                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3015                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3016                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3017                 rte_memcpy(filter->src_ipaddr,
3018                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3019                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3020                 rte_memcpy(filter->dst_ipaddr,
3021                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3022                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3023                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3024                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3025                 memset(filter->src_ipaddr_mask, 0xff, 16);
3026                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3027                 filter->ethertype = 0x86dd;
3028                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3029                 break;
3030         case RTE_ETH_FLOW_L2_PAYLOAD:
3031                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3032                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3033                 break;
3034         case RTE_ETH_FLOW_VXLAN:
3035                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3036                         return -EINVAL;
3037                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3038                 filter->tunnel_type =
3039                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3040                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3041                 break;
3042         case RTE_ETH_FLOW_NVGRE:
3043                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3044                         return -EINVAL;
3045                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3046                 filter->tunnel_type =
3047                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3048                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3049                 break;
3050         case RTE_ETH_FLOW_UNKNOWN:
3051         case RTE_ETH_FLOW_RAW:
3052         case RTE_ETH_FLOW_FRAG_IPV4:
3053         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3054         case RTE_ETH_FLOW_FRAG_IPV6:
3055         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3056         case RTE_ETH_FLOW_IPV6_EX:
3057         case RTE_ETH_FLOW_IPV6_TCP_EX:
3058         case RTE_ETH_FLOW_IPV6_UDP_EX:
3059         case RTE_ETH_FLOW_GENEVE:
3060                 /* FALLTHROUGH */
3061         default:
3062                 return -EINVAL;
3063         }
3064
3065         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3066         vnic = &bp->vnic_info[fdir->action.rx_queue];
3067         if (vnic == NULL) {
3068                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3069                 return -EINVAL;
3070         }
3071
3072         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3073                 rte_memcpy(filter->dst_macaddr,
3074                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3075                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3076         }
3077
3078         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3079                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3080                 filter1 = STAILQ_FIRST(&vnic0->filter);
3081                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3082         } else {
3083                 filter->dst_id = vnic->fw_vnic_id;
3084                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3085                         if (filter->dst_macaddr[i] == 0x00)
3086                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3087                         else
3088                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3089         }
3090
3091         if (filter1 == NULL)
3092                 return -EINVAL;
3093
3094         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3095         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3096
3097         filter->enables = en;
3098
3099         return 0;
3100 }
3101
3102 static struct bnxt_filter_info *
3103 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3104                 struct bnxt_vnic_info **mvnic)
3105 {
3106         struct bnxt_filter_info *mf = NULL;
3107         int i;
3108
3109         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3110                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3111
3112                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3113                         if (mf->filter_type == nf->filter_type &&
3114                             mf->flags == nf->flags &&
3115                             mf->src_port == nf->src_port &&
3116                             mf->src_port_mask == nf->src_port_mask &&
3117                             mf->dst_port == nf->dst_port &&
3118                             mf->dst_port_mask == nf->dst_port_mask &&
3119                             mf->ip_protocol == nf->ip_protocol &&
3120                             mf->ip_addr_type == nf->ip_addr_type &&
3121                             mf->ethertype == nf->ethertype &&
3122                             mf->vni == nf->vni &&
3123                             mf->tunnel_type == nf->tunnel_type &&
3124                             mf->l2_ovlan == nf->l2_ovlan &&
3125                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3126                             mf->l2_ivlan == nf->l2_ivlan &&
3127                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3128                             !memcmp(mf->l2_addr, nf->l2_addr,
3129                                     RTE_ETHER_ADDR_LEN) &&
3130                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3131                                     RTE_ETHER_ADDR_LEN) &&
3132                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3133                                     RTE_ETHER_ADDR_LEN) &&
3134                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3135                                     RTE_ETHER_ADDR_LEN) &&
3136                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3137                                     sizeof(nf->src_ipaddr)) &&
3138                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3139                                     sizeof(nf->src_ipaddr_mask)) &&
3140                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3141                                     sizeof(nf->dst_ipaddr)) &&
3142                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3143                                     sizeof(nf->dst_ipaddr_mask))) {
3144                                 if (mvnic)
3145                                         *mvnic = vnic;
3146                                 return mf;
3147                         }
3148                 }
3149         }
3150         return NULL;
3151 }
3152
3153 static int
3154 bnxt_fdir_filter(struct rte_eth_dev *dev,
3155                  enum rte_filter_op filter_op,
3156                  void *arg)
3157 {
3158         struct bnxt *bp = dev->data->dev_private;
3159         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3160         struct bnxt_filter_info *filter, *match;
3161         struct bnxt_vnic_info *vnic, *mvnic;
3162         int ret = 0, i;
3163
3164         if (filter_op == RTE_ETH_FILTER_NOP)
3165                 return 0;
3166
3167         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3168                 return -EINVAL;
3169
3170         switch (filter_op) {
3171         case RTE_ETH_FILTER_ADD:
3172         case RTE_ETH_FILTER_DELETE:
3173                 /* FALLTHROUGH */
3174                 filter = bnxt_get_unused_filter(bp);
3175                 if (filter == NULL) {
3176                         PMD_DRV_LOG(ERR,
3177                                 "Not enough resources for a new flow.\n");
3178                         return -ENOMEM;
3179                 }
3180
3181                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3182                 if (ret != 0)
3183                         goto free_filter;
3184                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3185
3186                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3187                         vnic = &bp->vnic_info[0];
3188                 else
3189                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3190
3191                 match = bnxt_match_fdir(bp, filter, &mvnic);
3192                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3193                         if (match->dst_id == vnic->fw_vnic_id) {
3194                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3195                                 ret = -EEXIST;
3196                                 goto free_filter;
3197                         } else {
3198                                 match->dst_id = vnic->fw_vnic_id;
3199                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3200                                                                   match->dst_id,
3201                                                                   match);
3202                                 STAILQ_REMOVE(&mvnic->filter, match,
3203                                               bnxt_filter_info, next);
3204                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3205                                 PMD_DRV_LOG(ERR,
3206                                         "Filter with matching pattern exist\n");
3207                                 PMD_DRV_LOG(ERR,
3208                                         "Updated it to new destination q\n");
3209                                 goto free_filter;
3210                         }
3211                 }
3212                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3213                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3214                         ret = -ENOENT;
3215                         goto free_filter;
3216                 }
3217
3218                 if (filter_op == RTE_ETH_FILTER_ADD) {
3219                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3220                                                           filter->dst_id,
3221                                                           filter);
3222                         if (ret)
3223                                 goto free_filter;
3224                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3225                 } else {
3226                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3227                         STAILQ_REMOVE(&vnic->filter, match,
3228                                       bnxt_filter_info, next);
3229                         bnxt_free_filter(bp, match);
3230                         bnxt_free_filter(bp, filter);
3231                 }
3232                 break;
3233         case RTE_ETH_FILTER_FLUSH:
3234                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3235                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3236
3237                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3238                                 if (filter->filter_type ==
3239                                     HWRM_CFA_NTUPLE_FILTER) {
3240                                         ret =
3241                                         bnxt_hwrm_clear_ntuple_filter(bp,
3242                                                                       filter);
3243                                         STAILQ_REMOVE(&vnic->filter, filter,
3244                                                       bnxt_filter_info, next);
3245                                 }
3246                         }
3247                 }
3248                 return ret;
3249         case RTE_ETH_FILTER_UPDATE:
3250         case RTE_ETH_FILTER_STATS:
3251         case RTE_ETH_FILTER_INFO:
3252                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3253                 break;
3254         default:
3255                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3256                 ret = -EINVAL;
3257                 break;
3258         }
3259         return ret;
3260
3261 free_filter:
3262         bnxt_free_filter(bp, filter);
3263         return ret;
3264 }
3265
3266 static int
3267 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3268                     enum rte_filter_type filter_type,
3269                     enum rte_filter_op filter_op, void *arg)
3270 {
3271         int ret = 0;
3272
3273         ret = is_bnxt_in_error(dev->data->dev_private);
3274         if (ret)
3275                 return ret;
3276
3277         switch (filter_type) {
3278         case RTE_ETH_FILTER_TUNNEL:
3279                 PMD_DRV_LOG(ERR,
3280                         "filter type: %d: To be implemented\n", filter_type);
3281                 break;
3282         case RTE_ETH_FILTER_FDIR:
3283                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3284                 break;
3285         case RTE_ETH_FILTER_NTUPLE:
3286                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3287                 break;
3288         case RTE_ETH_FILTER_ETHERTYPE:
3289                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3290                 break;
3291         case RTE_ETH_FILTER_GENERIC:
3292                 if (filter_op != RTE_ETH_FILTER_GET)
3293                         return -EINVAL;
3294                 *(const void **)arg = &bnxt_flow_ops;
3295                 break;
3296         default:
3297                 PMD_DRV_LOG(ERR,
3298                         "Filter type (%d) not supported", filter_type);
3299                 ret = -EINVAL;
3300                 break;
3301         }
3302         return ret;
3303 }
3304
3305 static const uint32_t *
3306 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3307 {
3308         static const uint32_t ptypes[] = {
3309                 RTE_PTYPE_L2_ETHER_VLAN,
3310                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3311                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3312                 RTE_PTYPE_L4_ICMP,
3313                 RTE_PTYPE_L4_TCP,
3314                 RTE_PTYPE_L4_UDP,
3315                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3316                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3317                 RTE_PTYPE_INNER_L4_ICMP,
3318                 RTE_PTYPE_INNER_L4_TCP,
3319                 RTE_PTYPE_INNER_L4_UDP,
3320                 RTE_PTYPE_UNKNOWN
3321         };
3322
3323         if (!dev->rx_pkt_burst)
3324                 return NULL;
3325
3326         return ptypes;
3327 }
3328
3329 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3330                          int reg_win)
3331 {
3332         uint32_t reg_base = *reg_arr & 0xfffff000;
3333         uint32_t win_off;
3334         int i;
3335
3336         for (i = 0; i < count; i++) {
3337                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3338                         return -ERANGE;
3339         }
3340         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3341         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3342         return 0;
3343 }
3344
3345 static int bnxt_map_ptp_regs(struct bnxt *bp)
3346 {
3347         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3348         uint32_t *reg_arr;
3349         int rc, i;
3350
3351         reg_arr = ptp->rx_regs;
3352         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3353         if (rc)
3354                 return rc;
3355
3356         reg_arr = ptp->tx_regs;
3357         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3358         if (rc)
3359                 return rc;
3360
3361         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3362                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3363
3364         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3365                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3366
3367         return 0;
3368 }
3369
3370 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3371 {
3372         rte_write32(0, (uint8_t *)bp->bar0 +
3373                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3374         rte_write32(0, (uint8_t *)bp->bar0 +
3375                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3376 }
3377
3378 static uint64_t bnxt_cc_read(struct bnxt *bp)
3379 {
3380         uint64_t ns;
3381
3382         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3383                               BNXT_GRCPF_REG_SYNC_TIME));
3384         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3385                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3386         return ns;
3387 }
3388
3389 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3390 {
3391         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3392         uint32_t fifo;
3393
3394         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3395                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3396         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3397                 return -EAGAIN;
3398
3399         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3400                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3401         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3402                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3403         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3404                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3405
3406         return 0;
3407 }
3408
3409 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3410 {
3411         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3412         struct bnxt_pf_info *pf = &bp->pf;
3413         uint16_t port_id;
3414         uint32_t fifo;
3415
3416         if (!ptp)
3417                 return -ENODEV;
3418
3419         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3420                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3421         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3422                 return -EAGAIN;
3423
3424         port_id = pf->port_id;
3425         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3426                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3427
3428         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3429                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3430         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3431 /*              bnxt_clr_rx_ts(bp);       TBD  */
3432                 return -EBUSY;
3433         }
3434
3435         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3436                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3437         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3438                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3439
3440         return 0;
3441 }
3442
3443 static int
3444 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3445 {
3446         uint64_t ns;
3447         struct bnxt *bp = dev->data->dev_private;
3448         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3449
3450         if (!ptp)
3451                 return 0;
3452
3453         ns = rte_timespec_to_ns(ts);
3454         /* Set the timecounters to a new value. */
3455         ptp->tc.nsec = ns;
3456
3457         return 0;
3458 }
3459
3460 static int
3461 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3462 {
3463         struct bnxt *bp = dev->data->dev_private;
3464         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3465         uint64_t ns, systime_cycles = 0;
3466         int rc = 0;
3467
3468         if (!ptp)
3469                 return 0;
3470
3471         if (BNXT_CHIP_THOR(bp))
3472                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3473                                              &systime_cycles);
3474         else
3475                 systime_cycles = bnxt_cc_read(bp);
3476
3477         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3478         *ts = rte_ns_to_timespec(ns);
3479
3480         return rc;
3481 }
3482 static int
3483 bnxt_timesync_enable(struct rte_eth_dev *dev)
3484 {
3485         struct bnxt *bp = dev->data->dev_private;
3486         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3487         uint32_t shift = 0;
3488         int rc;
3489
3490         if (!ptp)
3491                 return 0;
3492
3493         ptp->rx_filter = 1;
3494         ptp->tx_tstamp_en = 1;
3495         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3496
3497         rc = bnxt_hwrm_ptp_cfg(bp);
3498         if (rc)
3499                 return rc;
3500
3501         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3502         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3503         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3504
3505         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3506         ptp->tc.cc_shift = shift;
3507         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3508
3509         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3510         ptp->rx_tstamp_tc.cc_shift = shift;
3511         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3512
3513         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3514         ptp->tx_tstamp_tc.cc_shift = shift;
3515         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3516
3517         if (!BNXT_CHIP_THOR(bp))
3518                 bnxt_map_ptp_regs(bp);
3519
3520         return 0;
3521 }
3522
3523 static int
3524 bnxt_timesync_disable(struct rte_eth_dev *dev)
3525 {
3526         struct bnxt *bp = dev->data->dev_private;
3527         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3528
3529         if (!ptp)
3530                 return 0;
3531
3532         ptp->rx_filter = 0;
3533         ptp->tx_tstamp_en = 0;
3534         ptp->rxctl = 0;
3535
3536         bnxt_hwrm_ptp_cfg(bp);
3537
3538         if (!BNXT_CHIP_THOR(bp))
3539                 bnxt_unmap_ptp_regs(bp);
3540
3541         return 0;
3542 }
3543
3544 static int
3545 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3546                                  struct timespec *timestamp,
3547                                  uint32_t flags __rte_unused)
3548 {
3549         struct bnxt *bp = dev->data->dev_private;
3550         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3551         uint64_t rx_tstamp_cycles = 0;
3552         uint64_t ns;
3553
3554         if (!ptp)
3555                 return 0;
3556
3557         if (BNXT_CHIP_THOR(bp))
3558                 rx_tstamp_cycles = ptp->rx_timestamp;
3559         else
3560                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3561
3562         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3563         *timestamp = rte_ns_to_timespec(ns);
3564         return  0;
3565 }
3566
3567 static int
3568 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3569                                  struct timespec *timestamp)
3570 {
3571         struct bnxt *bp = dev->data->dev_private;
3572         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3573         uint64_t tx_tstamp_cycles = 0;
3574         uint64_t ns;
3575         int rc = 0;
3576
3577         if (!ptp)
3578                 return 0;
3579
3580         if (BNXT_CHIP_THOR(bp))
3581                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3582                                              &tx_tstamp_cycles);
3583         else
3584                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3585
3586         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3587         *timestamp = rte_ns_to_timespec(ns);
3588
3589         return rc;
3590 }
3591
3592 static int
3593 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3594 {
3595         struct bnxt *bp = dev->data->dev_private;
3596         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3597
3598         if (!ptp)
3599                 return 0;
3600
3601         ptp->tc.nsec += delta;
3602
3603         return 0;
3604 }
3605
3606 static int
3607 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3608 {
3609         struct bnxt *bp = dev->data->dev_private;
3610         int rc;
3611         uint32_t dir_entries;
3612         uint32_t entry_length;
3613
3614         rc = is_bnxt_in_error(bp);
3615         if (rc)
3616                 return rc;
3617
3618         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3619                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3620                     bp->pdev->addr.devid, bp->pdev->addr.function);
3621
3622         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3623         if (rc != 0)
3624                 return rc;
3625
3626         return dir_entries * entry_length;
3627 }
3628
3629 static int
3630 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3631                 struct rte_dev_eeprom_info *in_eeprom)
3632 {
3633         struct bnxt *bp = dev->data->dev_private;
3634         uint32_t index;
3635         uint32_t offset;
3636         int rc;
3637
3638         rc = is_bnxt_in_error(bp);
3639         if (rc)
3640                 return rc;
3641
3642         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3643                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3644                     bp->pdev->addr.devid, bp->pdev->addr.function,
3645                     in_eeprom->offset, in_eeprom->length);
3646
3647         if (in_eeprom->offset == 0) /* special offset value to get directory */
3648                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3649                                                 in_eeprom->data);
3650
3651         index = in_eeprom->offset >> 24;
3652         offset = in_eeprom->offset & 0xffffff;
3653
3654         if (index != 0)
3655                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3656                                            in_eeprom->length, in_eeprom->data);
3657
3658         return 0;
3659 }
3660
3661 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3662 {
3663         switch (dir_type) {
3664         case BNX_DIR_TYPE_CHIMP_PATCH:
3665         case BNX_DIR_TYPE_BOOTCODE:
3666         case BNX_DIR_TYPE_BOOTCODE_2:
3667         case BNX_DIR_TYPE_APE_FW:
3668         case BNX_DIR_TYPE_APE_PATCH:
3669         case BNX_DIR_TYPE_KONG_FW:
3670         case BNX_DIR_TYPE_KONG_PATCH:
3671         case BNX_DIR_TYPE_BONO_FW:
3672         case BNX_DIR_TYPE_BONO_PATCH:
3673                 /* FALLTHROUGH */
3674                 return true;
3675         }
3676
3677         return false;
3678 }
3679
3680 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3681 {
3682         switch (dir_type) {
3683         case BNX_DIR_TYPE_AVS:
3684         case BNX_DIR_TYPE_EXP_ROM_MBA:
3685         case BNX_DIR_TYPE_PCIE:
3686         case BNX_DIR_TYPE_TSCF_UCODE:
3687         case BNX_DIR_TYPE_EXT_PHY:
3688         case BNX_DIR_TYPE_CCM:
3689         case BNX_DIR_TYPE_ISCSI_BOOT:
3690         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3691         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3692                 /* FALLTHROUGH */
3693                 return true;
3694         }
3695
3696         return false;
3697 }
3698
3699 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3700 {
3701         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3702                 bnxt_dir_type_is_other_exec_format(dir_type);
3703 }
3704
3705 static int
3706 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3707                 struct rte_dev_eeprom_info *in_eeprom)
3708 {
3709         struct bnxt *bp = dev->data->dev_private;
3710         uint8_t index, dir_op;
3711         uint16_t type, ext, ordinal, attr;
3712         int rc;
3713
3714         rc = is_bnxt_in_error(bp);
3715         if (rc)
3716                 return rc;
3717
3718         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3719                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3720                     bp->pdev->addr.devid, bp->pdev->addr.function,
3721                     in_eeprom->offset, in_eeprom->length);
3722
3723         if (!BNXT_PF(bp)) {
3724                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3725                 return -EINVAL;
3726         }
3727
3728         type = in_eeprom->magic >> 16;
3729
3730         if (type == 0xffff) { /* special value for directory operations */
3731                 index = in_eeprom->magic & 0xff;
3732                 dir_op = in_eeprom->magic >> 8;
3733                 if (index == 0)
3734                         return -EINVAL;
3735                 switch (dir_op) {
3736                 case 0x0e: /* erase */
3737                         if (in_eeprom->offset != ~in_eeprom->magic)
3738                                 return -EINVAL;
3739                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3740                 default:
3741                         return -EINVAL;
3742                 }
3743         }
3744
3745         /* Create or re-write an NVM item: */
3746         if (bnxt_dir_type_is_executable(type) == true)
3747                 return -EOPNOTSUPP;
3748         ext = in_eeprom->magic & 0xffff;
3749         ordinal = in_eeprom->offset >> 16;
3750         attr = in_eeprom->offset & 0xffff;
3751
3752         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3753                                      in_eeprom->data, in_eeprom->length);
3754 }
3755
3756 /*
3757  * Initialization
3758  */
3759
3760 static const struct eth_dev_ops bnxt_dev_ops = {
3761         .dev_infos_get = bnxt_dev_info_get_op,
3762         .dev_close = bnxt_dev_close_op,
3763         .dev_configure = bnxt_dev_configure_op,
3764         .dev_start = bnxt_dev_start_op,
3765         .dev_stop = bnxt_dev_stop_op,
3766         .dev_set_link_up = bnxt_dev_set_link_up_op,
3767         .dev_set_link_down = bnxt_dev_set_link_down_op,
3768         .stats_get = bnxt_stats_get_op,
3769         .stats_reset = bnxt_stats_reset_op,
3770         .rx_queue_setup = bnxt_rx_queue_setup_op,
3771         .rx_queue_release = bnxt_rx_queue_release_op,
3772         .tx_queue_setup = bnxt_tx_queue_setup_op,
3773         .tx_queue_release = bnxt_tx_queue_release_op,
3774         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3775         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3776         .reta_update = bnxt_reta_update_op,
3777         .reta_query = bnxt_reta_query_op,
3778         .rss_hash_update = bnxt_rss_hash_update_op,
3779         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3780         .link_update = bnxt_link_update_op,
3781         .promiscuous_enable = bnxt_promiscuous_enable_op,
3782         .promiscuous_disable = bnxt_promiscuous_disable_op,
3783         .allmulticast_enable = bnxt_allmulticast_enable_op,
3784         .allmulticast_disable = bnxt_allmulticast_disable_op,
3785         .mac_addr_add = bnxt_mac_addr_add_op,
3786         .mac_addr_remove = bnxt_mac_addr_remove_op,
3787         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3788         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3789         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3790         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3791         .vlan_filter_set = bnxt_vlan_filter_set_op,
3792         .vlan_offload_set = bnxt_vlan_offload_set_op,
3793         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3794         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3795         .mtu_set = bnxt_mtu_set_op,
3796         .mac_addr_set = bnxt_set_default_mac_addr_op,
3797         .xstats_get = bnxt_dev_xstats_get_op,
3798         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3799         .xstats_reset = bnxt_dev_xstats_reset_op,
3800         .fw_version_get = bnxt_fw_version_get,
3801         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3802         .rxq_info_get = bnxt_rxq_info_get_op,
3803         .txq_info_get = bnxt_txq_info_get_op,
3804         .dev_led_on = bnxt_dev_led_on_op,
3805         .dev_led_off = bnxt_dev_led_off_op,
3806         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3807         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3808         .rx_queue_count = bnxt_rx_queue_count_op,
3809         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3810         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3811         .rx_queue_start = bnxt_rx_queue_start,
3812         .rx_queue_stop = bnxt_rx_queue_stop,
3813         .tx_queue_start = bnxt_tx_queue_start,
3814         .tx_queue_stop = bnxt_tx_queue_stop,
3815         .filter_ctrl = bnxt_filter_ctrl_op,
3816         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3817         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3818         .get_eeprom           = bnxt_get_eeprom_op,
3819         .set_eeprom           = bnxt_set_eeprom_op,
3820         .timesync_enable      = bnxt_timesync_enable,
3821         .timesync_disable     = bnxt_timesync_disable,
3822         .timesync_read_time   = bnxt_timesync_read_time,
3823         .timesync_write_time   = bnxt_timesync_write_time,
3824         .timesync_adjust_time = bnxt_timesync_adjust_time,
3825         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3826         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3827 };
3828
3829 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3830 {
3831         uint32_t offset;
3832
3833         /* Only pre-map the reset GRC registers using window 3 */
3834         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3835                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3836
3837         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3838
3839         return offset;
3840 }
3841
3842 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3843 {
3844         struct bnxt_error_recovery_info *info = bp->recovery_info;
3845         uint32_t reg_base = 0xffffffff;
3846         int i;
3847
3848         /* Only pre-map the monitoring GRC registers using window 2 */
3849         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3850                 uint32_t reg = info->status_regs[i];
3851
3852                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3853                         continue;
3854
3855                 if (reg_base == 0xffffffff)
3856                         reg_base = reg & 0xfffff000;
3857                 if ((reg & 0xfffff000) != reg_base)
3858                         return -ERANGE;
3859
3860                 /* Use mask 0xffc as the Lower 2 bits indicates
3861                  * address space location
3862                  */
3863                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3864                                                 (reg & 0xffc);
3865         }
3866
3867         if (reg_base == 0xffffffff)
3868                 return 0;
3869
3870         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3871                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3872
3873         return 0;
3874 }
3875
3876 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3877 {
3878         struct bnxt_error_recovery_info *info = bp->recovery_info;
3879         uint32_t delay = info->delay_after_reset[index];
3880         uint32_t val = info->reset_reg_val[index];
3881         uint32_t reg = info->reset_reg[index];
3882         uint32_t type, offset;
3883
3884         type = BNXT_FW_STATUS_REG_TYPE(reg);
3885         offset = BNXT_FW_STATUS_REG_OFF(reg);
3886
3887         switch (type) {
3888         case BNXT_FW_STATUS_REG_TYPE_CFG:
3889                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3890                 break;
3891         case BNXT_FW_STATUS_REG_TYPE_GRC:
3892                 offset = bnxt_map_reset_regs(bp, offset);
3893                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3894                 break;
3895         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3896                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3897                 break;
3898         }
3899         /* wait on a specific interval of time until core reset is complete */
3900         if (delay)
3901                 rte_delay_ms(delay);
3902 }
3903
3904 static void bnxt_dev_cleanup(struct bnxt *bp)
3905 {
3906         bnxt_set_hwrm_link_config(bp, false);
3907         bp->link_info.link_up = 0;
3908         if (bp->eth_dev->data->dev_started)
3909                 bnxt_dev_stop_op(bp->eth_dev);
3910
3911         bnxt_uninit_resources(bp, true);
3912 }
3913
3914 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3915 {
3916         struct rte_eth_dev *dev = bp->eth_dev;
3917         struct rte_vlan_filter_conf *vfc;
3918         int vidx, vbit, rc;
3919         uint16_t vlan_id;
3920
3921         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3922                 vfc = &dev->data->vlan_filter_conf;
3923                 vidx = vlan_id / 64;
3924                 vbit = vlan_id % 64;
3925
3926                 /* Each bit corresponds to a VLAN id */
3927                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3928                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3929                         if (rc)
3930                                 return rc;
3931                 }
3932         }
3933
3934         return 0;
3935 }
3936
3937 static int bnxt_restore_mac_filters(struct bnxt *bp)
3938 {
3939         struct rte_eth_dev *dev = bp->eth_dev;
3940         struct rte_eth_dev_info dev_info;
3941         struct rte_ether_addr *addr;
3942         uint64_t pool_mask;
3943         uint32_t pool = 0;
3944         uint16_t i;
3945         int rc;
3946
3947         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
3948                 return 0;
3949
3950         rc = bnxt_dev_info_get_op(dev, &dev_info);
3951         if (rc)
3952                 return rc;
3953
3954         /* replay MAC address configuration */
3955         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3956                 addr = &dev->data->mac_addrs[i];
3957
3958                 /* skip zero address */
3959                 if (rte_is_zero_ether_addr(addr))
3960                         continue;
3961
3962                 pool = 0;
3963                 pool_mask = dev->data->mac_pool_sel[i];
3964
3965                 do {
3966                         if (pool_mask & 1ULL) {
3967                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3968                                 if (rc)
3969                                         return rc;
3970                         }
3971                         pool_mask >>= 1;
3972                         pool++;
3973                 } while (pool_mask);
3974         }
3975
3976         return 0;
3977 }
3978
3979 static int bnxt_restore_filters(struct bnxt *bp)
3980 {
3981         struct rte_eth_dev *dev = bp->eth_dev;
3982         int ret = 0;
3983
3984         if (dev->data->all_multicast) {
3985                 ret = bnxt_allmulticast_enable_op(dev);
3986                 if (ret)
3987                         return ret;
3988         }
3989         if (dev->data->promiscuous) {
3990                 ret = bnxt_promiscuous_enable_op(dev);
3991                 if (ret)
3992                         return ret;
3993         }
3994
3995         ret = bnxt_restore_mac_filters(bp);
3996         if (ret)
3997                 return ret;
3998
3999         ret = bnxt_restore_vlan_filters(bp);
4000         /* TODO restore other filters as well */
4001         return ret;
4002 }
4003
4004 static void bnxt_dev_recover(void *arg)
4005 {
4006         struct bnxt *bp = arg;
4007         int timeout = bp->fw_reset_max_msecs;
4008         int rc = 0;
4009
4010         /* Clear Error flag so that device re-init should happen */
4011         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4012
4013         do {
4014                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4015                 if (rc == 0)
4016                         break;
4017                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4018                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4019         } while (rc && timeout);
4020
4021         if (rc) {
4022                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4023                 goto err;
4024         }
4025
4026         rc = bnxt_init_resources(bp, true);
4027         if (rc) {
4028                 PMD_DRV_LOG(ERR,
4029                             "Failed to initialize resources after reset\n");
4030                 goto err;
4031         }
4032         /* clear reset flag as the device is initialized now */
4033         bp->flags &= ~BNXT_FLAG_FW_RESET;
4034
4035         rc = bnxt_dev_start_op(bp->eth_dev);
4036         if (rc) {
4037                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4038                 goto err_start;
4039         }
4040
4041         rc = bnxt_restore_filters(bp);
4042         if (rc)
4043                 goto err_start;
4044
4045         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4046         return;
4047 err_start:
4048         bnxt_dev_stop_op(bp->eth_dev);
4049 err:
4050         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4051         bnxt_uninit_resources(bp, false);
4052         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4053 }
4054
4055 void bnxt_dev_reset_and_resume(void *arg)
4056 {
4057         struct bnxt *bp = arg;
4058         int rc;
4059
4060         bnxt_dev_cleanup(bp);
4061
4062         bnxt_wait_for_device_shutdown(bp);
4063
4064         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4065                                bnxt_dev_recover, (void *)bp);
4066         if (rc)
4067                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4068 }
4069
4070 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4071 {
4072         struct bnxt_error_recovery_info *info = bp->recovery_info;
4073         uint32_t reg = info->status_regs[index];
4074         uint32_t type, offset, val = 0;
4075
4076         type = BNXT_FW_STATUS_REG_TYPE(reg);
4077         offset = BNXT_FW_STATUS_REG_OFF(reg);
4078
4079         switch (type) {
4080         case BNXT_FW_STATUS_REG_TYPE_CFG:
4081                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4082                 break;
4083         case BNXT_FW_STATUS_REG_TYPE_GRC:
4084                 offset = info->mapped_status_regs[index];
4085                 /* FALLTHROUGH */
4086         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4087                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4088                                        offset));
4089                 break;
4090         }
4091
4092         return val;
4093 }
4094
4095 static int bnxt_fw_reset_all(struct bnxt *bp)
4096 {
4097         struct bnxt_error_recovery_info *info = bp->recovery_info;
4098         uint32_t i;
4099         int rc = 0;
4100
4101         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4102                 /* Reset through master function driver */
4103                 for (i = 0; i < info->reg_array_cnt; i++)
4104                         bnxt_write_fw_reset_reg(bp, i);
4105                 /* Wait for time specified by FW after triggering reset */
4106                 rte_delay_ms(info->master_func_wait_period_after_reset);
4107         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4108                 /* Reset with the help of Kong processor */
4109                 rc = bnxt_hwrm_fw_reset(bp);
4110                 if (rc)
4111                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4112         }
4113
4114         return rc;
4115 }
4116
4117 static void bnxt_fw_reset_cb(void *arg)
4118 {
4119         struct bnxt *bp = arg;
4120         struct bnxt_error_recovery_info *info = bp->recovery_info;
4121         int rc = 0;
4122
4123         /* Only Master function can do FW reset */
4124         if (bnxt_is_master_func(bp) &&
4125             bnxt_is_recovery_enabled(bp)) {
4126                 rc = bnxt_fw_reset_all(bp);
4127                 if (rc) {
4128                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4129                         return;
4130                 }
4131         }
4132
4133         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4134          * EXCEPTION_FATAL_ASYNC event to all the functions
4135          * (including MASTER FUNC). After receiving this Async, all the active
4136          * drivers should treat this case as FW initiated recovery
4137          */
4138         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4139                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4140                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4141
4142                 /* To recover from error */
4143                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4144                                   (void *)bp);
4145         }
4146 }
4147
4148 /* Driver should poll FW heartbeat, reset_counter with the frequency
4149  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4150  * When the driver detects heartbeat stop or change in reset_counter,
4151  * it has to trigger a reset to recover from the error condition.
4152  * A “master PF” is the function who will have the privilege to
4153  * initiate the chimp reset. The master PF will be elected by the
4154  * firmware and will be notified through async message.
4155  */
4156 static void bnxt_check_fw_health(void *arg)
4157 {
4158         struct bnxt *bp = arg;
4159         struct bnxt_error_recovery_info *info = bp->recovery_info;
4160         uint32_t val = 0, wait_msec;
4161
4162         if (!info || !bnxt_is_recovery_enabled(bp) ||
4163             is_bnxt_in_error(bp))
4164                 return;
4165
4166         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4167         if (val == info->last_heart_beat)
4168                 goto reset;
4169
4170         info->last_heart_beat = val;
4171
4172         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4173         if (val != info->last_reset_counter)
4174                 goto reset;
4175
4176         info->last_reset_counter = val;
4177
4178         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4179                           bnxt_check_fw_health, (void *)bp);
4180
4181         return;
4182 reset:
4183         /* Stop DMA to/from device */
4184         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4185         bp->flags |= BNXT_FLAG_FW_RESET;
4186
4187         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4188
4189         if (bnxt_is_master_func(bp))
4190                 wait_msec = info->master_func_wait_period;
4191         else
4192                 wait_msec = info->normal_func_wait_period;
4193
4194         rte_eal_alarm_set(US_PER_MS * wait_msec,
4195                           bnxt_fw_reset_cb, (void *)bp);
4196 }
4197
4198 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4199 {
4200         uint32_t polling_freq;
4201
4202         if (!bnxt_is_recovery_enabled(bp))
4203                 return;
4204
4205         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4206                 return;
4207
4208         polling_freq = bp->recovery_info->driver_polling_freq;
4209
4210         rte_eal_alarm_set(US_PER_MS * polling_freq,
4211                           bnxt_check_fw_health, (void *)bp);
4212         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4213 }
4214
4215 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4216 {
4217         if (!bnxt_is_recovery_enabled(bp))
4218                 return;
4219
4220         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4221         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4222 }
4223
4224 static bool bnxt_vf_pciid(uint16_t device_id)
4225 {
4226         switch (device_id) {
4227         case BROADCOM_DEV_ID_57304_VF:
4228         case BROADCOM_DEV_ID_57406_VF:
4229         case BROADCOM_DEV_ID_5731X_VF:
4230         case BROADCOM_DEV_ID_5741X_VF:
4231         case BROADCOM_DEV_ID_57414_VF:
4232         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4233         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4234         case BROADCOM_DEV_ID_58802_VF:
4235         case BROADCOM_DEV_ID_57500_VF1:
4236         case BROADCOM_DEV_ID_57500_VF2:
4237                 /* FALLTHROUGH */
4238                 return true;
4239         default:
4240                 return false;
4241         }
4242 }
4243
4244 static bool bnxt_thor_device(uint16_t device_id)
4245 {
4246         switch (device_id) {
4247         case BROADCOM_DEV_ID_57508:
4248         case BROADCOM_DEV_ID_57504:
4249         case BROADCOM_DEV_ID_57502:
4250         case BROADCOM_DEV_ID_57508_MF1:
4251         case BROADCOM_DEV_ID_57504_MF1:
4252         case BROADCOM_DEV_ID_57502_MF1:
4253         case BROADCOM_DEV_ID_57508_MF2:
4254         case BROADCOM_DEV_ID_57504_MF2:
4255         case BROADCOM_DEV_ID_57502_MF2:
4256         case BROADCOM_DEV_ID_57500_VF1:
4257         case BROADCOM_DEV_ID_57500_VF2:
4258                 /* FALLTHROUGH */
4259                 return true;
4260         default:
4261                 return false;
4262         }
4263 }
4264
4265 bool bnxt_stratus_device(struct bnxt *bp)
4266 {
4267         uint16_t device_id = bp->pdev->id.device_id;
4268
4269         switch (device_id) {
4270         case BROADCOM_DEV_ID_STRATUS_NIC:
4271         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4272         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4273                 /* FALLTHROUGH */
4274                 return true;
4275         default:
4276                 return false;
4277         }
4278 }
4279
4280 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4281 {
4282         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4283         struct bnxt *bp = eth_dev->data->dev_private;
4284
4285         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4286         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4287         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4288         if (!bp->bar0 || !bp->doorbell_base) {
4289                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4290                 return -ENODEV;
4291         }
4292
4293         bp->eth_dev = eth_dev;
4294         bp->pdev = pci_dev;
4295
4296         return 0;
4297 }
4298
4299 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4300                                   struct bnxt_ctx_pg_info *ctx_pg,
4301                                   uint32_t mem_size,
4302                                   const char *suffix,
4303                                   uint16_t idx)
4304 {
4305         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4306         const struct rte_memzone *mz = NULL;
4307         char mz_name[RTE_MEMZONE_NAMESIZE];
4308         rte_iova_t mz_phys_addr;
4309         uint64_t valid_bits = 0;
4310         uint32_t sz;
4311         int i;
4312
4313         if (!mem_size)
4314                 return 0;
4315
4316         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4317                          BNXT_PAGE_SIZE;
4318         rmem->page_size = BNXT_PAGE_SIZE;
4319         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4320         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4321         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4322
4323         valid_bits = PTU_PTE_VALID;
4324
4325         if (rmem->nr_pages > 1) {
4326                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4327                          "bnxt_ctx_pg_tbl%s_%x_%d",
4328                          suffix, idx, bp->eth_dev->data->port_id);
4329                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4330                 mz = rte_memzone_lookup(mz_name);
4331                 if (!mz) {
4332                         mz = rte_memzone_reserve_aligned(mz_name,
4333                                                 rmem->nr_pages * 8,
4334                                                 SOCKET_ID_ANY,
4335                                                 RTE_MEMZONE_2MB |
4336                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4337                                                 RTE_MEMZONE_IOVA_CONTIG,
4338                                                 BNXT_PAGE_SIZE);
4339                         if (mz == NULL)
4340                                 return -ENOMEM;
4341                 }
4342
4343                 memset(mz->addr, 0, mz->len);
4344                 mz_phys_addr = mz->iova;
4345
4346                 rmem->pg_tbl = mz->addr;
4347                 rmem->pg_tbl_map = mz_phys_addr;
4348                 rmem->pg_tbl_mz = mz;
4349         }
4350
4351         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4352                  suffix, idx, bp->eth_dev->data->port_id);
4353         mz = rte_memzone_lookup(mz_name);
4354         if (!mz) {
4355                 mz = rte_memzone_reserve_aligned(mz_name,
4356                                                  mem_size,
4357                                                  SOCKET_ID_ANY,
4358                                                  RTE_MEMZONE_1GB |
4359                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4360                                                  RTE_MEMZONE_IOVA_CONTIG,
4361                                                  BNXT_PAGE_SIZE);
4362                 if (mz == NULL)
4363                         return -ENOMEM;
4364         }
4365
4366         memset(mz->addr, 0, mz->len);
4367         mz_phys_addr = mz->iova;
4368
4369         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4370                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4371                 rmem->dma_arr[i] = mz_phys_addr + sz;
4372
4373                 if (rmem->nr_pages > 1) {
4374                         if (i == rmem->nr_pages - 2 &&
4375                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4376                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4377                         else if (i == rmem->nr_pages - 1 &&
4378                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4379                                 valid_bits |= PTU_PTE_LAST;
4380
4381                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4382                                                            valid_bits);
4383                 }
4384         }
4385
4386         rmem->mz = mz;
4387         if (rmem->vmem_size)
4388                 rmem->vmem = (void **)mz->addr;
4389         rmem->dma_arr[0] = mz_phys_addr;
4390         return 0;
4391 }
4392
4393 static void bnxt_free_ctx_mem(struct bnxt *bp)
4394 {
4395         int i;
4396
4397         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4398                 return;
4399
4400         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4401         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4402         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4403         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4404         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4405         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4406         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4407         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4408         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4409         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4410         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4411
4412         for (i = 0; i < BNXT_MAX_Q; i++) {
4413                 if (bp->ctx->tqm_mem[i])
4414                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4415         }
4416
4417         rte_free(bp->ctx);
4418         bp->ctx = NULL;
4419 }
4420
4421 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4422
4423 #define min_t(type, x, y) ({                    \
4424         type __min1 = (x);                      \
4425         type __min2 = (y);                      \
4426         __min1 < __min2 ? __min1 : __min2; })
4427
4428 #define max_t(type, x, y) ({                    \
4429         type __max1 = (x);                      \
4430         type __max2 = (y);                      \
4431         __max1 > __max2 ? __max1 : __max2; })
4432
4433 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4434
4435 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4436 {
4437         struct bnxt_ctx_pg_info *ctx_pg;
4438         struct bnxt_ctx_mem_info *ctx;
4439         uint32_t mem_size, ena, entries;
4440         int i, rc;
4441
4442         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4443         if (rc) {
4444                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4445                 return rc;
4446         }
4447         ctx = bp->ctx;
4448         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4449                 return 0;
4450
4451         ctx_pg = &ctx->qp_mem;
4452         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4453         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4454         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4455         if (rc)
4456                 return rc;
4457
4458         ctx_pg = &ctx->srq_mem;
4459         ctx_pg->entries = ctx->srq_max_l2_entries;
4460         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4461         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4462         if (rc)
4463                 return rc;
4464
4465         ctx_pg = &ctx->cq_mem;
4466         ctx_pg->entries = ctx->cq_max_l2_entries;
4467         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4468         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4469         if (rc)
4470                 return rc;
4471
4472         ctx_pg = &ctx->vnic_mem;
4473         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4474                 ctx->vnic_max_ring_table_entries;
4475         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4476         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4477         if (rc)
4478                 return rc;
4479
4480         ctx_pg = &ctx->stat_mem;
4481         ctx_pg->entries = ctx->stat_max_entries;
4482         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4483         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4484         if (rc)
4485                 return rc;
4486
4487         entries = ctx->qp_max_l2_entries +
4488                   ctx->vnic_max_vnic_entries +
4489                   ctx->tqm_min_entries_per_ring;
4490         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4491         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4492                           ctx->tqm_max_entries_per_ring);
4493         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4494                 ctx_pg = ctx->tqm_mem[i];
4495                 /* use min tqm entries for now. */
4496                 ctx_pg->entries = entries;
4497                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4498                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4499                 if (rc)
4500                         return rc;
4501                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4502         }
4503
4504         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4505         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4506         if (rc)
4507                 PMD_DRV_LOG(ERR,
4508                             "Failed to configure context mem: rc = %d\n", rc);
4509         else
4510                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4511
4512         return rc;
4513 }
4514
4515 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4516 {
4517         struct rte_pci_device *pci_dev = bp->pdev;
4518         char mz_name[RTE_MEMZONE_NAMESIZE];
4519         const struct rte_memzone *mz = NULL;
4520         uint32_t total_alloc_len;
4521         rte_iova_t mz_phys_addr;
4522
4523         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4524                 return 0;
4525
4526         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4527                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4528                  pci_dev->addr.bus, pci_dev->addr.devid,
4529                  pci_dev->addr.function, "rx_port_stats");
4530         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4531         mz = rte_memzone_lookup(mz_name);
4532         total_alloc_len =
4533                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4534                                        sizeof(struct rx_port_stats_ext) + 512);
4535         if (!mz) {
4536                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4537                                          SOCKET_ID_ANY,
4538                                          RTE_MEMZONE_2MB |
4539                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4540                                          RTE_MEMZONE_IOVA_CONTIG);
4541                 if (mz == NULL)
4542                         return -ENOMEM;
4543         }
4544         memset(mz->addr, 0, mz->len);
4545         mz_phys_addr = mz->iova;
4546
4547         bp->rx_mem_zone = (const void *)mz;
4548         bp->hw_rx_port_stats = mz->addr;
4549         bp->hw_rx_port_stats_map = mz_phys_addr;
4550
4551         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4552                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4553                  pci_dev->addr.bus, pci_dev->addr.devid,
4554                  pci_dev->addr.function, "tx_port_stats");
4555         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4556         mz = rte_memzone_lookup(mz_name);
4557         total_alloc_len =
4558                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4559                                        sizeof(struct tx_port_stats_ext) + 512);
4560         if (!mz) {
4561                 mz = rte_memzone_reserve(mz_name,
4562                                          total_alloc_len,
4563                                          SOCKET_ID_ANY,
4564                                          RTE_MEMZONE_2MB |
4565                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4566                                          RTE_MEMZONE_IOVA_CONTIG);
4567                 if (mz == NULL)
4568                         return -ENOMEM;
4569         }
4570         memset(mz->addr, 0, mz->len);
4571         mz_phys_addr = mz->iova;
4572
4573         bp->tx_mem_zone = (const void *)mz;
4574         bp->hw_tx_port_stats = mz->addr;
4575         bp->hw_tx_port_stats_map = mz_phys_addr;
4576         bp->flags |= BNXT_FLAG_PORT_STATS;
4577
4578         /* Display extended statistics if FW supports it */
4579         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4580             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4581             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4582                 return 0;
4583
4584         bp->hw_rx_port_stats_ext = (void *)
4585                 ((uint8_t *)bp->hw_rx_port_stats +
4586                  sizeof(struct rx_port_stats));
4587         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4588                 sizeof(struct rx_port_stats);
4589         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4590
4591         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4592             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4593                 bp->hw_tx_port_stats_ext = (void *)
4594                         ((uint8_t *)bp->hw_tx_port_stats +
4595                          sizeof(struct tx_port_stats));
4596                 bp->hw_tx_port_stats_ext_map =
4597                         bp->hw_tx_port_stats_map +
4598                         sizeof(struct tx_port_stats);
4599                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4600         }
4601
4602         return 0;
4603 }
4604
4605 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4606 {
4607         struct bnxt *bp = eth_dev->data->dev_private;
4608         int rc = 0;
4609
4610         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4611                                                RTE_ETHER_ADDR_LEN *
4612                                                bp->max_l2_ctx,
4613                                                0);
4614         if (eth_dev->data->mac_addrs == NULL) {
4615                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4616                 return -ENOMEM;
4617         }
4618
4619         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4620                 if (BNXT_PF(bp))
4621                         return -EINVAL;
4622
4623                 /* Generate a random MAC address, if none was assigned by PF */
4624                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4625                 bnxt_eth_hw_addr_random(bp->mac_addr);
4626                 PMD_DRV_LOG(INFO,
4627                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4628                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4629                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4630
4631                 rc = bnxt_hwrm_set_mac(bp);
4632                 if (!rc)
4633                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4634                                RTE_ETHER_ADDR_LEN);
4635                 return rc;
4636         }
4637
4638         /* Copy the permanent MAC from the FUNC_QCAPS response */
4639         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4640         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4641
4642         return rc;
4643 }
4644
4645 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4646 {
4647         int rc = 0;
4648
4649         /* MAC is already configured in FW */
4650         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4651                 return 0;
4652
4653         /* Restore the old MAC configured */
4654         rc = bnxt_hwrm_set_mac(bp);
4655         if (rc)
4656                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4657
4658         return rc;
4659 }
4660
4661 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4662 {
4663         if (!BNXT_PF(bp))
4664                 return;
4665
4666 #define ALLOW_FUNC(x)   \
4667         { \
4668                 uint32_t arg = (x); \
4669                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4670                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4671         }
4672
4673         /* Forward all requests if firmware is new enough */
4674         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4675              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4676             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4677                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4678         } else {
4679                 PMD_DRV_LOG(WARNING,
4680                             "Firmware too old for VF mailbox functionality\n");
4681                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4682         }
4683
4684         /*
4685          * The following are used for driver cleanup. If we disallow these,
4686          * VF drivers can't clean up cleanly.
4687          */
4688         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4689         ALLOW_FUNC(HWRM_VNIC_FREE);
4690         ALLOW_FUNC(HWRM_RING_FREE);
4691         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4692         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4693         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4694         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4695         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4696         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4697 }
4698
4699 static int bnxt_init_fw(struct bnxt *bp)
4700 {
4701         uint16_t mtu;
4702         int rc = 0;
4703
4704         bp->fw_cap = 0;
4705
4706         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4707         if (rc)
4708                 return rc;
4709
4710         rc = bnxt_hwrm_func_reset(bp);
4711         if (rc)
4712                 return -EIO;
4713
4714         rc = bnxt_hwrm_vnic_qcaps(bp);
4715         if (rc)
4716                 return rc;
4717
4718         rc = bnxt_hwrm_queue_qportcfg(bp);
4719         if (rc)
4720                 return rc;
4721
4722         /* Get the MAX capabilities for this function.
4723          * This function also allocates context memory for TQM rings and
4724          * informs the firmware about this allocated backing store memory.
4725          */
4726         rc = bnxt_hwrm_func_qcaps(bp);
4727         if (rc)
4728                 return rc;
4729
4730         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4731         if (rc)
4732                 return rc;
4733
4734         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4735         if (rc)
4736                 return rc;
4737
4738         /* Get the adapter error recovery support info */
4739         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4740         if (rc)
4741                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4742
4743         bnxt_hwrm_port_led_qcaps(bp);
4744
4745         return 0;
4746 }
4747
4748 static int
4749 bnxt_init_locks(struct bnxt *bp)
4750 {
4751         int err;
4752
4753         err = pthread_mutex_init(&bp->flow_lock, NULL);
4754         if (err) {
4755                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4756                 return err;
4757         }
4758
4759         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4760         if (err)
4761                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4762         return err;
4763 }
4764
4765 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4766 {
4767         int rc;
4768
4769         rc = bnxt_init_fw(bp);
4770         if (rc)
4771                 return rc;
4772
4773         if (!reconfig_dev) {
4774                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4775                 if (rc)
4776                         return rc;
4777         } else {
4778                 rc = bnxt_restore_dflt_mac(bp);
4779                 if (rc)
4780                         return rc;
4781         }
4782
4783         bnxt_config_vf_req_fwd(bp);
4784
4785         rc = bnxt_hwrm_func_driver_register(bp);
4786         if (rc) {
4787                 PMD_DRV_LOG(ERR, "Failed to register driver");
4788                 return -EBUSY;
4789         }
4790
4791         if (BNXT_PF(bp)) {
4792                 if (bp->pdev->max_vfs) {
4793                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4794                         if (rc) {
4795                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4796                                 return rc;
4797                         }
4798                 } else {
4799                         rc = bnxt_hwrm_allocate_pf_only(bp);
4800                         if (rc) {
4801                                 PMD_DRV_LOG(ERR,
4802                                             "Failed to allocate PF resources");
4803                                 return rc;
4804                         }
4805                 }
4806         }
4807
4808         rc = bnxt_alloc_mem(bp, reconfig_dev);
4809         if (rc)
4810                 return rc;
4811
4812         rc = bnxt_setup_int(bp);
4813         if (rc)
4814                 return rc;
4815
4816         rc = bnxt_request_int(bp);
4817         if (rc)
4818                 return rc;
4819
4820         rc = bnxt_init_locks(bp);
4821         if (rc)
4822                 return rc;
4823
4824         return 0;
4825 }
4826
4827 static int
4828 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4829 {
4830         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4831         static int version_printed;
4832         struct bnxt *bp;
4833         int rc;
4834
4835         if (version_printed++ == 0)
4836                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4837
4838         eth_dev->dev_ops = &bnxt_dev_ops;
4839         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4840         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4841
4842         /*
4843          * For secondary processes, we don't initialise any further
4844          * as primary has already done this work.
4845          */
4846         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4847                 return 0;
4848
4849         rte_eth_copy_pci_info(eth_dev, pci_dev);
4850
4851         bp = eth_dev->data->dev_private;
4852
4853         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
4854
4855         if (bnxt_vf_pciid(pci_dev->id.device_id))
4856                 bp->flags |= BNXT_FLAG_VF;
4857
4858         if (bnxt_thor_device(pci_dev->id.device_id))
4859                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4860
4861         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4862             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4863             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4864             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4865                 bp->flags |= BNXT_FLAG_STINGRAY;
4866
4867         rc = bnxt_init_board(eth_dev);
4868         if (rc) {
4869                 PMD_DRV_LOG(ERR,
4870                             "Failed to initialize board rc: %x\n", rc);
4871                 return rc;
4872         }
4873
4874         rc = bnxt_alloc_hwrm_resources(bp);
4875         if (rc) {
4876                 PMD_DRV_LOG(ERR,
4877                             "Failed to allocate hwrm resource rc: %x\n", rc);
4878                 goto error_free;
4879         }
4880         rc = bnxt_init_resources(bp, false);
4881         if (rc)
4882                 goto error_free;
4883
4884         rc = bnxt_alloc_stats_mem(bp);
4885         if (rc)
4886                 goto error_free;
4887
4888         /* Pass the information to the rte_eth_dev_close() that it should also
4889          * release the private port resources.
4890          */
4891         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
4892
4893         PMD_DRV_LOG(INFO,
4894                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4895                     pci_dev->mem_resource[0].phys_addr,
4896                     pci_dev->mem_resource[0].addr);
4897
4898         return 0;
4899
4900 error_free:
4901         bnxt_dev_uninit(eth_dev);
4902         return rc;
4903 }
4904
4905 static void
4906 bnxt_uninit_locks(struct bnxt *bp)
4907 {
4908         pthread_mutex_destroy(&bp->flow_lock);
4909         pthread_mutex_destroy(&bp->def_cp_lock);
4910 }
4911
4912 static int
4913 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4914 {
4915         int rc;
4916
4917         bnxt_free_int(bp);
4918         bnxt_free_mem(bp, reconfig_dev);
4919         bnxt_hwrm_func_buf_unrgtr(bp);
4920         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4921         bp->flags &= ~BNXT_FLAG_REGISTERED;
4922         bnxt_free_ctx_mem(bp);
4923         if (!reconfig_dev) {
4924                 bnxt_free_hwrm_resources(bp);
4925
4926                 if (bp->recovery_info != NULL) {
4927                         rte_free(bp->recovery_info);
4928                         bp->recovery_info = NULL;
4929                 }
4930         }
4931
4932         bnxt_uninit_locks(bp);
4933         rte_free(bp->ptp_cfg);
4934         bp->ptp_cfg = NULL;
4935         return rc;
4936 }
4937
4938 static int
4939 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4940 {
4941         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4942                 return -EPERM;
4943
4944         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4945
4946         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
4947                 bnxt_dev_close_op(eth_dev);
4948
4949         return 0;
4950 }
4951
4952 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4953         struct rte_pci_device *pci_dev)
4954 {
4955         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4956                 bnxt_dev_init);
4957 }
4958
4959 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4960 {
4961         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4962                 return rte_eth_dev_pci_generic_remove(pci_dev,
4963                                 bnxt_dev_uninit);
4964         else
4965                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4966 }
4967
4968 static struct rte_pci_driver bnxt_rte_pmd = {
4969         .id_table = bnxt_pci_id_map,
4970         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4971         .probe = bnxt_pci_probe,
4972         .remove = bnxt_pci_remove,
4973 };
4974
4975 static bool
4976 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4977 {
4978         if (strcmp(dev->device->driver->name, drv->driver.name))
4979                 return false;
4980
4981         return true;
4982 }
4983
4984 bool is_bnxt_supported(struct rte_eth_dev *dev)
4985 {
4986         return is_device_supported(dev, &bnxt_rte_pmd);
4987 }
4988
4989 RTE_INIT(bnxt_init_log)
4990 {
4991         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4992         if (bnxt_logtype_driver >= 0)
4993                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4994 }
4995
4996 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4997 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4998 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");