drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29 #include "bnxt_util.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  37
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  42 #define BROADCOM_DEV_ID_57301 0x16c8
  43 #define BROADCOM_DEV_ID_57302 0x16c9
  44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  47 #define BROADCOM_DEV_ID_NS2 0x16cd
  48 #define BROADCOM_DEV_ID_57311 0x16ce
  49 #define BROADCOM_DEV_ID_57312 0x16cf
  50 #define BROADCOM_DEV_ID_57402 0x16d0
  51 #define BROADCOM_DEV_ID_57404 0x16d1
  52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  56 #define BROADCOM_DEV_ID_57412 0x16d6
  57 #define BROADCOM_DEV_ID_57414 0x16d7
  58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  61 #define BROADCOM_DEV_ID_57412_MF 0x16de
  62 #define BROADCOM_DEV_ID_57314 0x16df
  63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  74 #define BROADCOM_DEV_ID_57508 0x1750
  75 #define BROADCOM_DEV_ID_57504 0x1751
  76 #define BROADCOM_DEV_ID_57502 0x1752
  77 #define BROADCOM_DEV_ID_57500_VF 0x1807
  78 #define BROADCOM_DEV_ID_58802 0xd802
  79 #define BROADCOM_DEV_ID_58804 0xd804
  80 #define BROADCOM_DEV_ID_58808 0x16f0
  81 #define BROADCOM_DEV_ID_58802_VF 0xd800
  82
  83 static const struct rte_pci_id bnxt_pci_id_map[] = {
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  85                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  87                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF) },
 130         { .vendor_id = 0, /* sentinel */ },
 131 };
 132
 133 #define BNXT_ETH_RSS_SUPPORT (  \
 134         ETH_RSS_IPV4 |          \
 135         ETH_RSS_NONFRAG_IPV4_TCP |      \
 136         ETH_RSS_NONFRAG_IPV4_UDP |      \
 137         ETH_RSS_IPV6 |          \
 138         ETH_RSS_NONFRAG_IPV6_TCP |      \
 139         ETH_RSS_NONFRAG_IPV6_UDP)
 140
 141 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 142                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 143                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 144                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 145                                      DEV_TX_OFFLOAD_TCP_TSO | \
 146                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 147                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 148                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 149                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 150                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 152
 153 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 154                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 155                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 156                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 157                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 158                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 159                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 160                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 161                                      DEV_RX_OFFLOAD_TCP_LRO)
 162
 163 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 164 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 165 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 166 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 167
 168 /***********************/
 169
 170 /*
 171  * High level utility functions
 172  */
 173
 174 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 175 {
 176         if (!BNXT_CHIP_THOR(bp))
 177                 return 1;
 178
 179         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 180                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 181                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 182 }
 183
 184 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 185 {
 186         if (!BNXT_CHIP_THOR(bp))
 187                 return HW_HASH_INDEX_SIZE;
 188
 189         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 190 }
 191
 192 static void bnxt_free_mem(struct bnxt *bp)
 193 {
 194         bnxt_free_filter_mem(bp);
 195         bnxt_free_vnic_attributes(bp);
 196         bnxt_free_vnic_mem(bp);
 197
 198         bnxt_free_stats(bp);
 199         bnxt_free_tx_rings(bp);
 200         bnxt_free_rx_rings(bp);
 201 }
 202
 203 static int bnxt_alloc_mem(struct bnxt *bp)
 204 {
 205         int rc;
 206
 207         rc = bnxt_alloc_vnic_mem(bp);
 208         if (rc)
 209                 goto alloc_mem_err;
 210
 211         rc = bnxt_alloc_vnic_attributes(bp);
 212         if (rc)
 213                 goto alloc_mem_err;
 214
 215         rc = bnxt_alloc_filter_mem(bp);
 216         if (rc)
 217                 goto alloc_mem_err;
 218
 219         return 0;
 220
 221 alloc_mem_err:
 222         bnxt_free_mem(bp);
 223         return rc;
 224 }
 225
 226 static int bnxt_init_chip(struct bnxt *bp)
 227 {
 228         struct bnxt_rx_queue *rxq;
 229         struct rte_eth_link new;
 230         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 231         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 232         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 233         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 234         uint32_t intr_vector = 0;
 235         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 236         uint32_t vec = BNXT_MISC_VEC_ID;
 237         unsigned int i, j;
 238         int rc;
 239
 240         /* disable uio/vfio intr/eventfd mapping */
 241         rte_intr_disable(intr_handle);
 242
 243         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 244                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 245                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 246                 bp->flags |= BNXT_FLAG_JUMBO;
 247         } else {
 248                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 249                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 250                 bp->flags &= ~BNXT_FLAG_JUMBO;
 251         }
 252
 253         /* THOR does not support ring groups.
 254          * But we will use the array to save RSS context IDs.
 255          */
 256         if (BNXT_CHIP_THOR(bp))
 257                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 258
 259         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 260         if (rc) {
 261                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 262                 goto err_out;
 263         }
 264
 265         rc = bnxt_alloc_hwrm_rings(bp);
 266         if (rc) {
 267                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 268                 goto err_out;
 269         }
 270
 271         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 272         if (rc) {
 273                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 274                 goto err_out;
 275         }
 276
 277         rc = bnxt_mq_rx_configure(bp);
 278         if (rc) {
 279                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 280                 goto err_out;
 281         }
 282
 283         /* VNIC configuration */
 284         for (i = 0; i < bp->nr_vnics; i++) {
 285                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 286                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 287                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 288
 289                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 290                 if (!vnic->fw_grp_ids) {
 291                         PMD_DRV_LOG(ERR,
 292                                     "Failed to alloc %d bytes for group ids\n",
 293                                     size);
 294                         rc = -ENOMEM;
 295                         goto err_out;
 296                 }
 297                 memset(vnic->fw_grp_ids, -1, size);
 298
 299                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 300                             i, vnic, vnic->fw_grp_ids);
 301
 302                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 303                 if (rc) {
 304                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 305                                 i, rc);
 306                         goto err_out;
 307                 }
 308
 309                 /* Alloc RSS context only if RSS mode is enabled */
 310                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 311                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 312
 313                         rc = 0;
 314                         for (j = 0; j < nr_ctxs; j++) {
 315                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 316                                 if (rc)
 317                                         break;
 318                         }
 319                         if (rc) {
 320                                 PMD_DRV_LOG(ERR,
 321                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 322                                   i, j, rc);
 323                                 goto err_out;
 324                         }
 325                         vnic->num_lb_ctxts = nr_ctxs;
 326                 }
 327
 328                 /*
 329                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 330                  * setting is not available at this time, it will not be
 331                  * configured correctly in the CFA.
 332                  */
 333                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 334                         vnic->vlan_strip = true;
 335                 else
 336                         vnic->vlan_strip = false;
 337
 338                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 339                 if (rc) {
 340                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 341                                 i, rc);
 342                         goto err_out;
 343                 }
 344
 345                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 346                 if (rc) {
 347                         PMD_DRV_LOG(ERR,
 348                                 "HWRM vnic %d filter failure rc: %x\n",
 349                                 i, rc);
 350                         goto err_out;
 351                 }
 352
 353                 for (j = 0; j < bp->rx_nr_rings; j++) {
 354                         rxq = bp->eth_dev->data->rx_queues[j];
 355
 356                         PMD_DRV_LOG(DEBUG,
 357                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 358                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 359
 360                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 361                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 362                 }
 363
 364                 rc = bnxt_vnic_rss_configure(bp, vnic);
 365                 if (rc) {
 366                         PMD_DRV_LOG(ERR,
 367                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 368                         goto err_out;
 369                 }
 370
 371                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 372
 373                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 374                     DEV_RX_OFFLOAD_TCP_LRO)
 375                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 376                 else
 377                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 378         }
 379         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 380         if (rc) {
 381                 PMD_DRV_LOG(ERR,
 382                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 383                 goto err_out;
 384         }
 385
 386         /* check and configure queue intr-vector mapping */
 387         if ((rte_intr_cap_multiple(intr_handle) ||
 388              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 389             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 390                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 391                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 392                 if (intr_vector > bp->rx_cp_nr_rings) {
 393                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 394                                         bp->rx_cp_nr_rings);
 395                         return -ENOTSUP;
 396                 }
 397                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 398                         return -1;
 399         }
 400
 401         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 402                 intr_handle->intr_vec =
 403                         rte_zmalloc("intr_vec",
 404                                     bp->eth_dev->data->nb_rx_queues *
 405                                     sizeof(int), 0);
 406                 if (intr_handle->intr_vec == NULL) {
 407                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 408                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 409                         return -ENOMEM;
 410                 }
 411                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 412                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 413                          intr_handle->intr_vec, intr_handle->nb_efd,
 414                         intr_handle->max_intr);
 415                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 416                      queue_id++) {
 417                         intr_handle->intr_vec[queue_id] = vec;
 418                         if (vec < base + intr_handle->nb_efd - 1)
 419                                 vec++;
 420                 }
 421         }
 422
 423         /* enable uio/vfio intr/eventfd mapping */
 424         rte_intr_enable(intr_handle);
 425
 426         rc = bnxt_get_hwrm_link_config(bp, &new);
 427         if (rc) {
 428                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 429                 goto err_out;
 430         }
 431
 432         if (!bp->link_info.link_up) {
 433                 rc = bnxt_set_hwrm_link_config(bp, true);
 434                 if (rc) {
 435                         PMD_DRV_LOG(ERR,
 436                                 "HWRM link config failure rc: %x\n", rc);
 437                         goto err_out;
 438                 }
 439         }
 440         bnxt_print_link_info(bp->eth_dev);
 441
 442         return 0;
 443
 444 err_out:
 445         bnxt_free_all_hwrm_resources(bp);
 446
 447         /* Some of the error status returned by FW may not be from errno.h */
 448         if (rc > 0)
 449                 rc = -EIO;
 450
 451         return rc;
 452 }
 453
 454 static int bnxt_shutdown_nic(struct bnxt *bp)
 455 {
 456         bnxt_free_all_hwrm_resources(bp);
 457         bnxt_free_all_filters(bp);
 458         bnxt_free_all_vnics(bp);
 459         return 0;
 460 }
 461
 462 static int bnxt_init_nic(struct bnxt *bp)
 463 {
 464         int rc;
 465
 466         rc = bnxt_init_ring_grps(bp);
 467         if (rc)
 468                 return rc;
 469
 470         bnxt_init_vnics(bp);
 471         bnxt_init_filters(bp);
 472
 473         return 0;
 474 }
 475
 476 /*
 477  * Device configuration and status function
 478  */
 479
 480 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 481                                   struct rte_eth_dev_info *dev_info)
 482 {
 483         struct bnxt *bp = eth_dev->data->dev_private;
 484         uint16_t max_vnics, i, j, vpool, vrxq;
 485         unsigned int max_rx_rings;
 486
 487         /* MAC Specifics */
 488         dev_info->max_mac_addrs = bp->max_l2_ctx;
 489         dev_info->max_hash_mac_addrs = 0;
 490
 491         /* PF/VF specifics */
 492         if (BNXT_PF(bp))
 493                 dev_info->max_vfs = bp->pdev->max_vfs;
 494         max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx);
 495         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 496         dev_info->max_rx_queues = max_rx_rings;
 497         dev_info->max_tx_queues = max_rx_rings;
 498         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 499         dev_info->hash_key_size = 40;
 500         max_vnics = bp->max_vnics;
 501
 502         /* Fast path specifics */
 503         dev_info->min_rx_bufsize = 1;
 504         dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
 505                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
 506
 507         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 508         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 509                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 510         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 511         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 512
 513         /* *INDENT-OFF* */
 514         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 515                 .rx_thresh = {
 516                         .pthresh = 8,
 517                         .hthresh = 8,
 518                         .wthresh = 0,
 519                 },
 520                 .rx_free_thresh = 32,
 521                 /* If no descriptors available, pkts are dropped by default */
 522                 .rx_drop_en = 1,
 523         };
 524
 525         dev_info->default_txconf = (struct rte_eth_txconf) {
 526                 .tx_thresh = {
 527                         .pthresh = 32,
 528                         .hthresh = 0,
 529                         .wthresh = 0,
 530                 },
 531                 .tx_free_thresh = 32,
 532                 .tx_rs_thresh = 32,
 533         };
 534         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 535
 536         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 537         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 538         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 539         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 540         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 541
 542         /* *INDENT-ON* */
 543
 544         /*
 545          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 546          *       need further investigation.
 547          */
 548
 549         /* VMDq resources */
 550         vpool = 64; /* ETH_64_POOLS */
 551         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 552         for (i = 0; i < 4; vpool >>= 1, i++) {
 553                 if (max_vnics > vpool) {
 554                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 555                                 if (dev_info->max_rx_queues > vrxq) {
 556                                         if (vpool > vrxq)
 557                                                 vpool = vrxq;
 558                                         goto found;
 559                                 }
 560                         }
 561                         /* Not enough resources to support VMDq */
 562                         break;
 563                 }
 564         }
 565         /* Not enough resources to support VMDq */
 566         vpool = 0;
 567         vrxq = 0;
 568 found:
 569         dev_info->max_vmdq_pools = vpool;
 570         dev_info->vmdq_queue_num = vrxq;
 571
 572         dev_info->vmdq_pool_base = 0;
 573         dev_info->vmdq_queue_base = 0;
 574 }
 575
 576 /* Configure the device based on the configuration provided */
 577 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 578 {
 579         struct bnxt *bp = eth_dev->data->dev_private;
 580         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 581         int rc;
 582
 583         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 584         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 585         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 586         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 587
 588         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 589                 rc = bnxt_hwrm_check_vf_rings(bp);
 590                 if (rc) {
 591                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 592                         return -ENOSPC;
 593                 }
 594
 595                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 596                 if (rc) {
 597                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 598                         return -ENOSPC;
 599                 }
 600         } else {
 601                 /* legacy driver needs to get updated values */
 602                 rc = bnxt_hwrm_func_qcaps(bp);
 603                 if (rc) {
 604                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 605                         return rc;
 606                 }
 607         }
 608
 609         /* Inherit new configurations */
 610         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 611             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 612             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 613             bp->max_cp_rings ||
 614             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 615             bp->max_stat_ctx)
 616                 goto resource_error;
 617
 618         if (BNXT_HAS_RING_GRPS(bp) &&
 619             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 620                 goto resource_error;
 621
 622         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 623             bp->max_vnics < eth_dev->data->nb_rx_queues)
 624                 goto resource_error;
 625
 626         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 627         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 628
 629         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 630                 eth_dev->data->mtu =
 631                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 632                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 633                         BNXT_NUM_VLANS;
 634                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 635         }
 636         return 0;
 637
 638 resource_error:
 639         PMD_DRV_LOG(ERR,
 640                     "Insufficient resources to support requested config\n");
 641         PMD_DRV_LOG(ERR,
 642                     "Num Queues Requested: Tx %d, Rx %d\n",
 643                     eth_dev->data->nb_tx_queues,
 644                     eth_dev->data->nb_rx_queues);
 645         PMD_DRV_LOG(ERR,
 646                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 647                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 648                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 649         return -ENOSPC;
 650 }
 651
 652 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 653 {
 654         struct rte_eth_link *link = &eth_dev->data->dev_link;
 655
 656         if (link->link_status)
 657                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 658                         eth_dev->data->port_id,
 659                         (uint32_t)link->link_speed,
 660                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 661                         ("full-duplex") : ("half-duplex\n"));
 662         else
 663                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 664                         eth_dev->data->port_id);
 665 }
 666
 667 /*
 668  * Determine whether the current configuration requires support for scattered
 669  * receive; return 1 if scattered receive is required and 0 if not.
 670  */
 671 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 672 {
 673         uint16_t buf_size;
 674         int i;
 675
 676         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 677                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 678
 679                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 680                                       RTE_PKTMBUF_HEADROOM);
 681                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 682                         return 1;
 683         }
 684         return 0;
 685 }
 686
 687 static eth_rx_burst_t
 688 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 689 {
 690 #ifdef RTE_ARCH_X86
 691         /*
 692          * Vector mode receive can be enabled only if scatter rx is not
 693          * in use and rx offloads are limited to VLAN stripping and
 694          * CRC stripping.
 695          */
 696         if (!eth_dev->data->scattered_rx &&
 697             !(eth_dev->data->dev_conf.rxmode.offloads &
 698               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 699                 DEV_RX_OFFLOAD_KEEP_CRC |
 700                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 701                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 702                 DEV_RX_OFFLOAD_UDP_CKSUM |
 703                 DEV_RX_OFFLOAD_TCP_CKSUM |
 704                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 705                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 706                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 707                             eth_dev->data->port_id);
 708                 return bnxt_recv_pkts_vec;
 709         }
 710         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 711                     eth_dev->data->port_id);
 712         PMD_DRV_LOG(INFO,
 713                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 714                     eth_dev->data->port_id,
 715                     eth_dev->data->scattered_rx,
 716                     eth_dev->data->dev_conf.rxmode.offloads);
 717 #endif
 718         return bnxt_recv_pkts;
 719 }
 720
 721 static eth_tx_burst_t
 722 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 723 {
 724 #ifdef RTE_ARCH_X86
 725         /*
 726          * Vector mode receive can be enabled only if scatter tx is not
 727          * in use and tx offloads other than VLAN insertion are not
 728          * in use.
 729          */
 730         if (!eth_dev->data->scattered_rx &&
 731             !(eth_dev->data->dev_conf.txmode.offloads &
 732               ~DEV_TX_OFFLOAD_VLAN_INSERT)) {
 733                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 734                             eth_dev->data->port_id);
 735                 return bnxt_xmit_pkts_vec;
 736         }
 737         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 738                     eth_dev->data->port_id);
 739         PMD_DRV_LOG(INFO,
 740                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 741                     eth_dev->data->port_id,
 742                     eth_dev->data->scattered_rx,
 743                     eth_dev->data->dev_conf.txmode.offloads);
 744 #endif
 745         return bnxt_xmit_pkts;
 746 }
 747
 748 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 749 {
 750         struct bnxt *bp = eth_dev->data->dev_private;
 751         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 752         int vlan_mask = 0;
 753         int rc;
 754
 755         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 756                 PMD_DRV_LOG(ERR,
 757                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 758                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 759         }
 760         bp->dev_stopped = 0;
 761
 762         rc = bnxt_init_chip(bp);
 763         if (rc)
 764                 goto error;
 765
 766         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 767
 768         bnxt_link_update_op(eth_dev, 1);
 769
 770         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 771                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 772         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 773                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 774         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 775         if (rc)
 776                 goto error;
 777
 778         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 779         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 780         bp->flags |= BNXT_FLAG_INIT_DONE;
 781         return 0;
 782
 783 error:
 784         bnxt_shutdown_nic(bp);
 785         bnxt_free_tx_mbufs(bp);
 786         bnxt_free_rx_mbufs(bp);
 787         return rc;
 788 }
 789
 790 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 791 {
 792         struct bnxt *bp = eth_dev->data->dev_private;
 793         int rc = 0;
 794
 795         if (!bp->link_info.link_up)
 796                 rc = bnxt_set_hwrm_link_config(bp, true);
 797         if (!rc)
 798                 eth_dev->data->dev_link.link_status = 1;
 799
 800         bnxt_print_link_info(eth_dev);
 801         return 0;
 802 }
 803
 804 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 805 {
 806         struct bnxt *bp = eth_dev->data->dev_private;
 807
 808         eth_dev->data->dev_link.link_status = 0;
 809         bnxt_set_hwrm_link_config(bp, false);
 810         bp->link_info.link_up = 0;
 811
 812         return 0;
 813 }
 814
 815 /* Unload the driver, release resources */
 816 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 817 {
 818         struct bnxt *bp = eth_dev->data->dev_private;
 819
 820         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 821         if (bp->eth_dev->data->dev_started) {
 822                 /* TBD: STOP HW queues DMA */
 823                 eth_dev->data->dev_link.link_status = 0;
 824         }
 825         bnxt_set_hwrm_link_config(bp, false);
 826         bnxt_hwrm_port_clr_stats(bp);
 827         bnxt_free_tx_mbufs(bp);
 828         bnxt_free_rx_mbufs(bp);
 829         bnxt_shutdown_nic(bp);
 830         bp->dev_stopped = 1;
 831 }
 832
 833 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 834 {
 835         struct bnxt *bp = eth_dev->data->dev_private;
 836
 837         if (bp->dev_stopped == 0)
 838                 bnxt_dev_stop_op(eth_dev);
 839
 840         if (eth_dev->data->mac_addrs != NULL) {
 841                 rte_free(eth_dev->data->mac_addrs);
 842                 eth_dev->data->mac_addrs = NULL;
 843         }
 844         if (bp->grp_info != NULL) {
 845                 rte_free(bp->grp_info);
 846                 bp->grp_info = NULL;
 847         }
 848
 849         bnxt_dev_uninit(eth_dev);
 850 }
 851
 852 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 853                                     uint32_t index)
 854 {
 855         struct bnxt *bp = eth_dev->data->dev_private;
 856         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 857         struct bnxt_vnic_info *vnic;
 858         struct bnxt_filter_info *filter, *temp_filter;
 859         uint32_t i;
 860
 861         /*
 862          * Loop through all VNICs from the specified filter flow pools to
 863          * remove the corresponding MAC addr filter
 864          */
 865         for (i = 0; i < bp->nr_vnics; i++) {
 866                 if (!(pool_mask & (1ULL << i)))
 867                         continue;
 868
 869                 vnic = &bp->vnic_info[i];
 870                 filter = STAILQ_FIRST(&vnic->filter);
 871                 while (filter) {
 872                         temp_filter = STAILQ_NEXT(filter, next);
 873                         if (filter->mac_index == index) {
 874                                 STAILQ_REMOVE(&vnic->filter, filter,
 875                                                 bnxt_filter_info, next);
 876                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 877                                 filter->mac_index = INVALID_MAC_INDEX;
 878                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 879                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 880                                                    filter, next);
 881                         }
 882                         filter = temp_filter;
 883                 }
 884         }
 885 }
 886
 887 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 888                                 struct rte_ether_addr *mac_addr,
 889                                 uint32_t index, uint32_t pool)
 890 {
 891         struct bnxt *bp = eth_dev->data->dev_private;
 892         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
 893         struct bnxt_filter_info *filter;
 894
 895         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
 896                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
 897                 return -ENOTSUP;
 898         }
 899
 900         if (!vnic) {
 901                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
 902                 return -EINVAL;
 903         }
 904         /* Attach requested MAC address to the new l2_filter */
 905         STAILQ_FOREACH(filter, &vnic->filter, next) {
 906                 if (filter->mac_index == index) {
 907                         PMD_DRV_LOG(ERR,
 908                                 "MAC addr already existed for pool %d\n", pool);
 909                         return 0;
 910                 }
 911         }
 912         filter = bnxt_alloc_filter(bp);
 913         if (!filter) {
 914                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
 915                 return -ENODEV;
 916         }
 917         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 918         filter->mac_index = index;
 919         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
 920         return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 921 }
 922
 923 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 924 {
 925         int rc = 0;
 926         struct bnxt *bp = eth_dev->data->dev_private;
 927         struct rte_eth_link new;
 928         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 929
 930         memset(&new, 0, sizeof(new));
 931         do {
 932                 /* Retrieve link info from hardware */
 933                 rc = bnxt_get_hwrm_link_config(bp, &new);
 934                 if (rc) {
 935                         new.link_speed = ETH_LINK_SPEED_100M;
 936                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 937                         PMD_DRV_LOG(ERR,
 938                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 939                         goto out;
 940                 }
 941                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 942
 943                 if (!wait_to_complete)
 944                         break;
 945         } while (!new.link_status && cnt--);
 946
 947 out:
 948         /* Timed out or success */
 949         if (new.link_status != eth_dev->data->dev_link.link_status ||
 950         new.link_speed != eth_dev->data->dev_link.link_speed) {
 951                 memcpy(&eth_dev->data->dev_link, &new,
 952                         sizeof(struct rte_eth_link));
 953
 954                 _rte_eth_dev_callback_process(eth_dev,
 955                                               RTE_ETH_EVENT_INTR_LSC,
 956                                               NULL);
 957
 958                 bnxt_print_link_info(eth_dev);
 959         }
 960
 961         return rc;
 962 }
 963
 964 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
 965 {
 966         struct bnxt *bp = eth_dev->data->dev_private;
 967         struct bnxt_vnic_info *vnic;
 968
 969         if (bp->vnic_info == NULL)
 970                 return;
 971
 972         vnic = &bp->vnic_info[0];
 973
 974         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
 975         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 976 }
 977
 978 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
 979 {
 980         struct bnxt *bp = eth_dev->data->dev_private;
 981         struct bnxt_vnic_info *vnic;
 982
 983         if (bp->vnic_info == NULL)
 984                 return;
 985
 986         vnic = &bp->vnic_info[0];
 987
 988         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
 989         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 990 }
 991
 992 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
 993 {
 994         struct bnxt *bp = eth_dev->data->dev_private;
 995         struct bnxt_vnic_info *vnic;
 996
 997         if (bp->vnic_info == NULL)
 998                 return;
 999
1000         vnic = &bp->vnic_info[0];
1001
1002         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1003         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1004 }
1005
1006 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1007 {
1008         struct bnxt *bp = eth_dev->data->dev_private;
1009         struct bnxt_vnic_info *vnic;
1010
1011         if (bp->vnic_info == NULL)
1012                 return;
1013
1014         vnic = &bp->vnic_info[0];
1015
1016         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1017         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1018 }
1019
1020 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1021 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1022 {
1023         if (qid >= bp->rx_nr_rings)
1024                 return NULL;
1025
1026         return bp->eth_dev->data->rx_queues[qid];
1027 }
1028
1029 /* Return rxq corresponding to a given rss table ring/group ID. */
1030 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1031 {
1032         struct bnxt_rx_queue *rxq;
1033         unsigned int i;
1034
1035         if (!BNXT_HAS_RING_GRPS(bp)) {
1036                 for (i = 0; i < bp->rx_nr_rings; i++) {
1037                         rxq = bp->eth_dev->data->rx_queues[i];
1038                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1039                                 return rxq->index;
1040                 }
1041         } else {
1042                 for (i = 0; i < bp->rx_nr_rings; i++) {
1043                         if (bp->grp_info[i].fw_grp_id == fwr)
1044                                 return i;
1045                 }
1046         }
1047
1048         return INVALID_HW_RING_ID;
1049 }
1050
1051 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1052                             struct rte_eth_rss_reta_entry64 *reta_conf,
1053                             uint16_t reta_size)
1054 {
1055         struct bnxt *bp = eth_dev->data->dev_private;
1056         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1057         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1058         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1059         uint16_t idx, sft;
1060         int i;
1061
1062         if (!vnic->rss_table)
1063                 return -EINVAL;
1064
1065         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1066                 return -EINVAL;
1067
1068         if (reta_size != tbl_size) {
1069                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1070                         "(%d) must equal the size supported by the hardware "
1071                         "(%d)\n", reta_size, tbl_size);
1072                 return -EINVAL;
1073         }
1074
1075         for (i = 0; i < reta_size; i++) {
1076                 struct bnxt_rx_queue *rxq;
1077
1078                 idx = i / RTE_RETA_GROUP_SIZE;
1079                 sft = i % RTE_RETA_GROUP_SIZE;
1080
1081                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1082                         continue;
1083
1084                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1085                 if (!rxq) {
1086                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1087                         return -EINVAL;
1088                 }
1089
1090                 if (BNXT_CHIP_THOR(bp)) {
1091                         vnic->rss_table[i * 2] =
1092                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1093                         vnic->rss_table[i * 2 + 1] =
1094                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1095                 } else {
1096                         vnic->rss_table[i] =
1097                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1098                 }
1099
1100                 vnic->rss_table[i] =
1101                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1102         }
1103
1104         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1105         return 0;
1106 }
1107
1108 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1109                               struct rte_eth_rss_reta_entry64 *reta_conf,
1110                               uint16_t reta_size)
1111 {
1112         struct bnxt *bp = eth_dev->data->dev_private;
1113         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1114         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1115         uint16_t idx, sft, i;
1116
1117         /* Retrieve from the default VNIC */
1118         if (!vnic)
1119                 return -EINVAL;
1120         if (!vnic->rss_table)
1121                 return -EINVAL;
1122
1123         if (reta_size != tbl_size) {
1124                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1125                         "(%d) must equal the size supported by the hardware "
1126                         "(%d)\n", reta_size, tbl_size);
1127                 return -EINVAL;
1128         }
1129
1130         for (idx = 0, i = 0; i < reta_size; i++) {
1131                 idx = i / RTE_RETA_GROUP_SIZE;
1132                 sft = i % RTE_RETA_GROUP_SIZE;
1133
1134                 if (reta_conf[idx].mask & (1ULL << sft)) {
1135                         uint16_t qid;
1136
1137                         if (BNXT_CHIP_THOR(bp))
1138                                 qid = bnxt_rss_to_qid(bp,
1139                                                       vnic->rss_table[i * 2]);
1140                         else
1141                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1142
1143                         if (qid == INVALID_HW_RING_ID) {
1144                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1145                                 return -EINVAL;
1146                         }
1147                         reta_conf[idx].reta[sft] = qid;
1148                 }
1149         }
1150
1151         return 0;
1152 }
1153
1154 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1155                                    struct rte_eth_rss_conf *rss_conf)
1156 {
1157         struct bnxt *bp = eth_dev->data->dev_private;
1158         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1159         struct bnxt_vnic_info *vnic;
1160         uint16_t hash_type = 0;
1161         unsigned int i;
1162
1163         /*
1164          * If RSS enablement were different than dev_configure,
1165          * then return -EINVAL
1166          */
1167         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1168                 if (!rss_conf->rss_hf)
1169                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1170         } else {
1171                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1172                         return -EINVAL;
1173         }
1174
1175         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1176         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1177
1178         if (rss_conf->rss_hf & ETH_RSS_IPV4)
1179                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1180         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1181                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1182         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1183                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1184         if (rss_conf->rss_hf & ETH_RSS_IPV6)
1185                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1186         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1187                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1188         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1189                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1190
1191         /* Update the RSS VNIC(s) */
1192         for (i = 0; i < bp->nr_vnics; i++) {
1193                 vnic = &bp->vnic_info[i];
1194                 vnic->hash_type = hash_type;
1195
1196                 /*
1197                  * Use the supplied key if the key length is
1198                  * acceptable and the rss_key is not NULL
1199                  */
1200                 if (rss_conf->rss_key &&
1201                     rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1202                         memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1203                                rss_conf->rss_key_len);
1204
1205                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1206         }
1207         return 0;
1208 }
1209
1210 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1211                                      struct rte_eth_rss_conf *rss_conf)
1212 {
1213         struct bnxt *bp = eth_dev->data->dev_private;
1214         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1215         int len;
1216         uint32_t hash_types;
1217
1218         /* RSS configuration is the same for all VNICs */
1219         if (vnic && vnic->rss_hash_key) {
1220                 if (rss_conf->rss_key) {
1221                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1222                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1223                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1224                 }
1225
1226                 hash_types = vnic->hash_type;
1227                 rss_conf->rss_hf = 0;
1228                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1229                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1230                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1231                 }
1232                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1233                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1234                         hash_types &=
1235                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1236                 }
1237                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1238                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1239                         hash_types &=
1240                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1241                 }
1242                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1243                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1244                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1245                 }
1246                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1247                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1248                         hash_types &=
1249                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1250                 }
1251                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1252                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1253                         hash_types &=
1254                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1255                 }
1256                 if (hash_types) {
1257                         PMD_DRV_LOG(ERR,
1258                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1259                                 vnic->hash_type);
1260                         return -ENOTSUP;
1261                 }
1262         } else {
1263                 rss_conf->rss_hf = 0;
1264         }
1265         return 0;
1266 }
1267
1268 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1269                                struct rte_eth_fc_conf *fc_conf)
1270 {
1271         struct bnxt *bp = dev->data->dev_private;
1272         struct rte_eth_link link_info;
1273         int rc;
1274
1275         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1276         if (rc)
1277                 return rc;
1278
1279         memset(fc_conf, 0, sizeof(*fc_conf));
1280         if (bp->link_info.auto_pause)
1281                 fc_conf->autoneg = 1;
1282         switch (bp->link_info.pause) {
1283         case 0:
1284                 fc_conf->mode = RTE_FC_NONE;
1285                 break;
1286         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1287                 fc_conf->mode = RTE_FC_TX_PAUSE;
1288                 break;
1289         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1290                 fc_conf->mode = RTE_FC_RX_PAUSE;
1291                 break;
1292         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1293                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1294                 fc_conf->mode = RTE_FC_FULL;
1295                 break;
1296         }
1297         return 0;
1298 }
1299
1300 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1301                                struct rte_eth_fc_conf *fc_conf)
1302 {
1303         struct bnxt *bp = dev->data->dev_private;
1304
1305         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1306                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1307                 return -ENOTSUP;
1308         }
1309
1310         switch (fc_conf->mode) {
1311         case RTE_FC_NONE:
1312                 bp->link_info.auto_pause = 0;
1313                 bp->link_info.force_pause = 0;
1314                 break;
1315         case RTE_FC_RX_PAUSE:
1316                 if (fc_conf->autoneg) {
1317                         bp->link_info.auto_pause =
1318                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1319                         bp->link_info.force_pause = 0;
1320                 } else {
1321                         bp->link_info.auto_pause = 0;
1322                         bp->link_info.force_pause =
1323                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1324                 }
1325                 break;
1326         case RTE_FC_TX_PAUSE:
1327                 if (fc_conf->autoneg) {
1328                         bp->link_info.auto_pause =
1329                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1330                         bp->link_info.force_pause = 0;
1331                 } else {
1332                         bp->link_info.auto_pause = 0;
1333                         bp->link_info.force_pause =
1334                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1335                 }
1336                 break;
1337         case RTE_FC_FULL:
1338                 if (fc_conf->autoneg) {
1339                         bp->link_info.auto_pause =
1340                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1341                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1342                         bp->link_info.force_pause = 0;
1343                 } else {
1344                         bp->link_info.auto_pause = 0;
1345                         bp->link_info.force_pause =
1346                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1347                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1348                 }
1349                 break;
1350         }
1351         return bnxt_set_hwrm_link_config(bp, true);
1352 }
1353
1354 /* Add UDP tunneling port */
1355 static int
1356 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1357                          struct rte_eth_udp_tunnel *udp_tunnel)
1358 {
1359         struct bnxt *bp = eth_dev->data->dev_private;
1360         uint16_t tunnel_type = 0;
1361         int rc = 0;
1362
1363         switch (udp_tunnel->prot_type) {
1364         case RTE_TUNNEL_TYPE_VXLAN:
1365                 if (bp->vxlan_port_cnt) {
1366                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1367                                 udp_tunnel->udp_port);
1368                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1369                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1370                                 return -ENOSPC;
1371                         }
1372                         bp->vxlan_port_cnt++;
1373                         return 0;
1374                 }
1375                 tunnel_type =
1376                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1377                 bp->vxlan_port_cnt++;
1378                 break;
1379         case RTE_TUNNEL_TYPE_GENEVE:
1380                 if (bp->geneve_port_cnt) {
1381                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1382                                 udp_tunnel->udp_port);
1383                         if (bp->geneve_port != udp_tunnel->udp_port) {
1384                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1385                                 return -ENOSPC;
1386                         }
1387                         bp->geneve_port_cnt++;
1388                         return 0;
1389                 }
1390                 tunnel_type =
1391                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1392                 bp->geneve_port_cnt++;
1393                 break;
1394         default:
1395                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1396                 return -ENOTSUP;
1397         }
1398         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1399                                              tunnel_type);
1400         return rc;
1401 }
1402
1403 static int
1404 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1405                          struct rte_eth_udp_tunnel *udp_tunnel)
1406 {
1407         struct bnxt *bp = eth_dev->data->dev_private;
1408         uint16_t tunnel_type = 0;
1409         uint16_t port = 0;
1410         int rc = 0;
1411
1412         switch (udp_tunnel->prot_type) {
1413         case RTE_TUNNEL_TYPE_VXLAN:
1414                 if (!bp->vxlan_port_cnt) {
1415                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1416                         return -EINVAL;
1417                 }
1418                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1419                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1420                                 udp_tunnel->udp_port, bp->vxlan_port);
1421                         return -EINVAL;
1422                 }
1423                 if (--bp->vxlan_port_cnt)
1424                         return 0;
1425
1426                 tunnel_type =
1427                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1428                 port = bp->vxlan_fw_dst_port_id;
1429                 break;
1430         case RTE_TUNNEL_TYPE_GENEVE:
1431                 if (!bp->geneve_port_cnt) {
1432                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1433                         return -EINVAL;
1434                 }
1435                 if (bp->geneve_port != udp_tunnel->udp_port) {
1436                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1437                                 udp_tunnel->udp_port, bp->geneve_port);
1438                         return -EINVAL;
1439                 }
1440                 if (--bp->geneve_port_cnt)
1441                         return 0;
1442
1443                 tunnel_type =
1444                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1445                 port = bp->geneve_fw_dst_port_id;
1446                 break;
1447         default:
1448                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1449                 return -ENOTSUP;
1450         }
1451
1452         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1453         if (!rc) {
1454                 if (tunnel_type ==
1455                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1456                         bp->vxlan_port = 0;
1457                 if (tunnel_type ==
1458                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1459                         bp->geneve_port = 0;
1460         }
1461         return rc;
1462 }
1463
1464 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1465 {
1466         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1467         struct bnxt_vnic_info *vnic;
1468         unsigned int i;
1469         int rc = 0;
1470         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1471
1472         /* Cycle through all VNICs */
1473         for (i = 0; i < bp->nr_vnics; i++) {
1474                 /*
1475                  * For each VNIC and each associated filter(s)
1476                  * if VLAN exists && VLAN matches vlan_id
1477                  *      remove the MAC+VLAN filter
1478                  *      add a new MAC only filter
1479                  * else
1480                  *      VLAN filter doesn't exist, just skip and continue
1481                  */
1482                 vnic = &bp->vnic_info[i];
1483                 filter = STAILQ_FIRST(&vnic->filter);
1484                 while (filter) {
1485                         temp_filter = STAILQ_NEXT(filter, next);
1486
1487                         if (filter->enables & chk &&
1488                             filter->l2_ovlan == vlan_id) {
1489                                 /* Must delete the filter */
1490                                 STAILQ_REMOVE(&vnic->filter, filter,
1491                                               bnxt_filter_info, next);
1492                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1493                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1494                                                    filter, next);
1495
1496                                 /*
1497                                  * Need to examine to see if the MAC
1498                                  * filter already existed or not before
1499                                  * allocating a new one
1500                                  */
1501
1502                                 new_filter = bnxt_alloc_filter(bp);
1503                                 if (!new_filter) {
1504                                         PMD_DRV_LOG(ERR,
1505                                                         "MAC/VLAN filter alloc failed\n");
1506                                         rc = -ENOMEM;
1507                                         goto exit;
1508                                 }
1509                                 STAILQ_INSERT_TAIL(&vnic->filter,
1510                                                 new_filter, next);
1511                                 /* Inherit MAC from previous filter */
1512                                 new_filter->mac_index =
1513                                         filter->mac_index;
1514                                 memcpy(new_filter->l2_addr, filter->l2_addr,
1515                                        RTE_ETHER_ADDR_LEN);
1516                                 /* MAC only filter */
1517                                 rc = bnxt_hwrm_set_l2_filter(bp,
1518                                                              vnic->fw_vnic_id,
1519                                                              new_filter);
1520                                 if (rc)
1521                                         goto exit;
1522                                 PMD_DRV_LOG(INFO,
1523                                             "Del Vlan filter for %d\n",
1524                                             vlan_id);
1525                         }
1526                         filter = temp_filter;
1527                 }
1528         }
1529 exit:
1530         return rc;
1531 }
1532
1533 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1534 {
1535         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1536         struct bnxt_vnic_info *vnic;
1537         unsigned int i;
1538         int rc = 0;
1539         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1540                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1541         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1542
1543         /* Cycle through all VNICs */
1544         for (i = 0; i < bp->nr_vnics; i++) {
1545                 /*
1546                  * For each VNIC and each associated filter(s)
1547                  * if VLAN exists:
1548                  *   if VLAN matches vlan_id
1549                  *      VLAN filter already exists, just skip and continue
1550                  *   else
1551                  *      add a new MAC+VLAN filter
1552                  * else
1553                  *   Remove the old MAC only filter
1554                  *    Add a new MAC+VLAN filter
1555                  */
1556                 vnic = &bp->vnic_info[i];
1557                 filter = STAILQ_FIRST(&vnic->filter);
1558                 while (filter) {
1559                         temp_filter = STAILQ_NEXT(filter, next);
1560
1561                         if (filter->enables & chk) {
1562                                 if (filter->l2_ivlan == vlan_id)
1563                                         goto cont;
1564                         } else {
1565                                 /* Must delete the MAC filter */
1566                                 STAILQ_REMOVE(&vnic->filter, filter,
1567                                                 bnxt_filter_info, next);
1568                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1569                                 filter->l2_ovlan = 0;
1570                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1571                                                    filter, next);
1572                         }
1573                         new_filter = bnxt_alloc_filter(bp);
1574                         if (!new_filter) {
1575                                 PMD_DRV_LOG(ERR,
1576                                                 "MAC/VLAN filter alloc failed\n");
1577                                 rc = -ENOMEM;
1578                                 goto exit;
1579                         }
1580                         STAILQ_INSERT_TAIL(&vnic->filter, new_filter, next);
1581                         /* Inherit MAC from the previous filter */
1582                         new_filter->mac_index = filter->mac_index;
1583                         memcpy(new_filter->l2_addr, filter->l2_addr,
1584                                RTE_ETHER_ADDR_LEN);
1585                         /* MAC + VLAN ID filter */
1586                         new_filter->l2_ivlan = vlan_id;
1587                         new_filter->l2_ivlan_mask = 0xF000;
1588                         new_filter->enables |= en;
1589                         rc = bnxt_hwrm_set_l2_filter(bp,
1590                                         vnic->fw_vnic_id,
1591                                         new_filter);
1592                         if (rc)
1593                                 goto exit;
1594                         PMD_DRV_LOG(INFO,
1595                                     "Added Vlan filter for %d\n", vlan_id);
1596 cont:
1597                         filter = temp_filter;
1598                 }
1599         }
1600 exit:
1601         return rc;
1602 }
1603
1604 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1605                 uint16_t vlan_id, int on)
1606 {
1607         struct bnxt *bp = eth_dev->data->dev_private;
1608
1609         /* These operations apply to ALL existing MAC/VLAN filters */
1610         if (on)
1611                 return bnxt_add_vlan_filter(bp, vlan_id);
1612         else
1613                 return bnxt_del_vlan_filter(bp, vlan_id);
1614 }
1615
1616 static int
1617 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1618 {
1619         struct bnxt *bp = dev->data->dev_private;
1620         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1621         unsigned int i;
1622
1623         if (mask & ETH_VLAN_FILTER_MASK) {
1624                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1625                         /* Remove any VLAN filters programmed */
1626                         for (i = 0; i < 4095; i++)
1627                                 bnxt_del_vlan_filter(bp, i);
1628                 }
1629                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1630                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1631         }
1632
1633         if (mask & ETH_VLAN_STRIP_MASK) {
1634                 /* Enable or disable VLAN stripping */
1635                 for (i = 0; i < bp->nr_vnics; i++) {
1636                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1637                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1638                                 vnic->vlan_strip = true;
1639                         else
1640                                 vnic->vlan_strip = false;
1641                         bnxt_hwrm_vnic_cfg(bp, vnic);
1642                 }
1643                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1644                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1645         }
1646
1647         if (mask & ETH_VLAN_EXTEND_MASK)
1648                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1649
1650         return 0;
1651 }
1652
1653 static int
1654 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1655                         struct rte_ether_addr *addr)
1656 {
1657         struct bnxt *bp = dev->data->dev_private;
1658         /* Default Filter is tied to VNIC 0 */
1659         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1660         struct bnxt_filter_info *filter;
1661         int rc;
1662
1663         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1664                 return -EPERM;
1665
1666         memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1667
1668         STAILQ_FOREACH(filter, &vnic->filter, next) {
1669                 /* Default Filter is at Index 0 */
1670                 if (filter->mac_index != 0)
1671                         continue;
1672                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1673                 if (rc)
1674                         return rc;
1675                 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1676                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1677                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1678                 filter->enables |=
1679                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1680                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1681                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1682                 if (rc)
1683                         return rc;
1684                 filter->mac_index = 0;
1685                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1686         }
1687
1688         return 0;
1689 }
1690
1691 static int
1692 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1693                           struct rte_ether_addr *mc_addr_set,
1694                           uint32_t nb_mc_addr)
1695 {
1696         struct bnxt *bp = eth_dev->data->dev_private;
1697         char *mc_addr_list = (char *)mc_addr_set;
1698         struct bnxt_vnic_info *vnic;
1699         uint32_t off = 0, i = 0;
1700
1701         vnic = &bp->vnic_info[0];
1702
1703         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1704                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1705                 goto allmulti;
1706         }
1707
1708         /* TODO Check for Duplicate mcast addresses */
1709         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1710         for (i = 0; i < nb_mc_addr; i++) {
1711                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1712                         RTE_ETHER_ADDR_LEN);
1713                 off += RTE_ETHER_ADDR_LEN;
1714         }
1715
1716         vnic->mc_addr_cnt = i;
1717
1718 allmulti:
1719         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1720 }
1721
1722 static int
1723 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1724 {
1725         struct bnxt *bp = dev->data->dev_private;
1726         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1727         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1728         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1729         int ret;
1730
1731         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1732                         fw_major, fw_minor, fw_updt);
1733
1734         ret += 1; /* add the size of '\0' */
1735         if (fw_size < (uint32_t)ret)
1736                 return ret;
1737         else
1738                 return 0;
1739 }
1740
1741 static void
1742 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1743         struct rte_eth_rxq_info *qinfo)
1744 {
1745         struct bnxt_rx_queue *rxq;
1746
1747         rxq = dev->data->rx_queues[queue_id];
1748
1749         qinfo->mp = rxq->mb_pool;
1750         qinfo->scattered_rx = dev->data->scattered_rx;
1751         qinfo->nb_desc = rxq->nb_rx_desc;
1752
1753         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1754         qinfo->conf.rx_drop_en = 0;
1755         qinfo->conf.rx_deferred_start = 0;
1756 }
1757
1758 static void
1759 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1760         struct rte_eth_txq_info *qinfo)
1761 {
1762         struct bnxt_tx_queue *txq;
1763
1764         txq = dev->data->tx_queues[queue_id];
1765
1766         qinfo->nb_desc = txq->nb_tx_desc;
1767
1768         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1769         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1770         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1771
1772         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1773         qinfo->conf.tx_rs_thresh = 0;
1774         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1775 }
1776
1777 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1778 {
1779         struct bnxt *bp = eth_dev->data->dev_private;
1780         struct rte_eth_dev_info dev_info;
1781         uint32_t new_pkt_size;
1782         uint32_t rc = 0;
1783         uint32_t i;
1784
1785         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1786                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1787
1788         bnxt_dev_info_get_op(eth_dev, &dev_info);
1789
1790         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1791                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1792                         RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1793                 return -EINVAL;
1794         }
1795
1796 #ifdef RTE_ARCH_X86
1797         /*
1798          * If vector-mode tx/rx is active, disallow any MTU change that would
1799          * require scattered receive support.
1800          */
1801         if (eth_dev->data->dev_started &&
1802             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1803              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1804             (new_pkt_size >
1805              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1806                 PMD_DRV_LOG(ERR,
1807                             "MTU change would require scattered rx support. ");
1808                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1809                 return -EINVAL;
1810         }
1811 #endif
1812
1813         if (new_mtu > RTE_ETHER_MTU) {
1814                 bp->flags |= BNXT_FLAG_JUMBO;
1815                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1816                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1817         } else {
1818                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1819                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1820                 bp->flags &= ~BNXT_FLAG_JUMBO;
1821         }
1822
1823         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
1824
1825         eth_dev->data->mtu = new_mtu;
1826         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1827
1828         for (i = 0; i < bp->nr_vnics; i++) {
1829                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1830                 uint16_t size = 0;
1831
1832                 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1833                                         RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1834                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1835                 if (rc)
1836                         break;
1837
1838                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1839                 size -= RTE_PKTMBUF_HEADROOM;
1840
1841                 if (size < new_mtu) {
1842                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1843                         if (rc)
1844                                 return rc;
1845                 }
1846         }
1847
1848         return rc;
1849 }
1850
1851 static int
1852 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1853 {
1854         struct bnxt *bp = dev->data->dev_private;
1855         uint16_t vlan = bp->vlan;
1856         int rc;
1857
1858         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1859                 PMD_DRV_LOG(ERR,
1860                         "PVID cannot be modified for this function\n");
1861                 return -ENOTSUP;
1862         }
1863         bp->vlan = on ? pvid : 0;
1864
1865         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1866         if (rc)
1867                 bp->vlan = vlan;
1868         return rc;
1869 }
1870
1871 static int
1872 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1873 {
1874         struct bnxt *bp = dev->data->dev_private;
1875
1876         return bnxt_hwrm_port_led_cfg(bp, true);
1877 }
1878
1879 static int
1880 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1881 {
1882         struct bnxt *bp = dev->data->dev_private;
1883
1884         return bnxt_hwrm_port_led_cfg(bp, false);
1885 }
1886
1887 static uint32_t
1888 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1889 {
1890         uint32_t desc = 0, raw_cons = 0, cons;
1891         struct bnxt_cp_ring_info *cpr;
1892         struct bnxt_rx_queue *rxq;
1893         struct rx_pkt_cmpl *rxcmp;
1894         uint16_t cmp_type;
1895         uint8_t cmp = 1;
1896         bool valid;
1897
1898         rxq = dev->data->rx_queues[rx_queue_id];
1899         cpr = rxq->cp_ring;
1900         valid = cpr->valid;
1901
1902         while (raw_cons < rxq->nb_rx_desc) {
1903                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1904                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1905
1906                 if (!CMPL_VALID(rxcmp, valid))
1907                         goto nothing_to_do;
1908                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1909                 cmp_type = CMP_TYPE(rxcmp);
1910                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1911                         cmp = (rte_le_to_cpu_32(
1912                                         ((struct rx_tpa_end_cmpl *)
1913                                          (rxcmp))->agg_bufs_v1) &
1914                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1915                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1916                         desc++;
1917                 } else if (cmp_type == 0x11) {
1918                         desc++;
1919                         cmp = (rxcmp->agg_bufs_v1 &
1920                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1921                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1922                 } else {
1923                         cmp = 1;
1924                 }
1925 nothing_to_do:
1926                 raw_cons += cmp ? cmp : 2;
1927         }
1928
1929         return desc;
1930 }
1931
1932 static int
1933 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1934 {
1935         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1936         struct bnxt_rx_ring_info *rxr;
1937         struct bnxt_cp_ring_info *cpr;
1938         struct bnxt_sw_rx_bd *rx_buf;
1939         struct rx_pkt_cmpl *rxcmp;
1940         uint32_t cons, cp_cons;
1941
1942         if (!rxq)
1943                 return -EINVAL;
1944
1945         cpr = rxq->cp_ring;
1946         rxr = rxq->rx_ring;
1947
1948         if (offset >= rxq->nb_rx_desc)
1949                 return -EINVAL;
1950
1951         cons = RING_CMP(cpr->cp_ring_struct, offset);
1952         cp_cons = cpr->cp_raw_cons;
1953         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1954
1955         if (cons > cp_cons) {
1956                 if (CMPL_VALID(rxcmp, cpr->valid))
1957                         return RTE_ETH_RX_DESC_DONE;
1958         } else {
1959                 if (CMPL_VALID(rxcmp, !cpr->valid))
1960                         return RTE_ETH_RX_DESC_DONE;
1961         }
1962         rx_buf = &rxr->rx_buf_ring[cons];
1963         if (rx_buf->mbuf == NULL)
1964                 return RTE_ETH_RX_DESC_UNAVAIL;
1965
1966
1967         return RTE_ETH_RX_DESC_AVAIL;
1968 }
1969
1970 static int
1971 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1972 {
1973         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1974         struct bnxt_tx_ring_info *txr;
1975         struct bnxt_cp_ring_info *cpr;
1976         struct bnxt_sw_tx_bd *tx_buf;
1977         struct tx_pkt_cmpl *txcmp;
1978         uint32_t cons, cp_cons;
1979
1980         if (!txq)
1981                 return -EINVAL;
1982
1983         cpr = txq->cp_ring;
1984         txr = txq->tx_ring;
1985
1986         if (offset >= txq->nb_tx_desc)
1987                 return -EINVAL;
1988
1989         cons = RING_CMP(cpr->cp_ring_struct, offset);
1990         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1991         cp_cons = cpr->cp_raw_cons;
1992
1993         if (cons > cp_cons) {
1994                 if (CMPL_VALID(txcmp, cpr->valid))
1995                         return RTE_ETH_TX_DESC_UNAVAIL;
1996         } else {
1997                 if (CMPL_VALID(txcmp, !cpr->valid))
1998                         return RTE_ETH_TX_DESC_UNAVAIL;
1999         }
2000         tx_buf = &txr->tx_buf_ring[cons];
2001         if (tx_buf->mbuf == NULL)
2002                 return RTE_ETH_TX_DESC_DONE;
2003
2004         return RTE_ETH_TX_DESC_FULL;
2005 }
2006
2007 static struct bnxt_filter_info *
2008 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2009                                 struct rte_eth_ethertype_filter *efilter,
2010                                 struct bnxt_vnic_info *vnic0,
2011                                 struct bnxt_vnic_info *vnic,
2012                                 int *ret)
2013 {
2014         struct bnxt_filter_info *mfilter = NULL;
2015         int match = 0;
2016         *ret = 0;
2017
2018         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2019                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2020                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2021                         " ethertype filter.", efilter->ether_type);
2022                 *ret = -EINVAL;
2023                 goto exit;
2024         }
2025         if (efilter->queue >= bp->rx_nr_rings) {
2026                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2027                 *ret = -EINVAL;
2028                 goto exit;
2029         }
2030
2031         vnic0 = &bp->vnic_info[0];
2032         vnic = &bp->vnic_info[efilter->queue];
2033         if (vnic == NULL) {
2034                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2035                 *ret = -EINVAL;
2036                 goto exit;
2037         }
2038
2039         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2040                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2041                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2042                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2043                              mfilter->flags ==
2044                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2045                              mfilter->ethertype == efilter->ether_type)) {
2046                                 match = 1;
2047                                 break;
2048                         }
2049                 }
2050         } else {
2051                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2052                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2053                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2054                              mfilter->ethertype == efilter->ether_type &&
2055                              mfilter->flags ==
2056                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2057                                 match = 1;
2058                                 break;
2059                         }
2060         }
2061
2062         if (match)
2063                 *ret = -EEXIST;
2064
2065 exit:
2066         return mfilter;
2067 }
2068
2069 static int
2070 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2071                         enum rte_filter_op filter_op,
2072                         void *arg)
2073 {
2074         struct bnxt *bp = dev->data->dev_private;
2075         struct rte_eth_ethertype_filter *efilter =
2076                         (struct rte_eth_ethertype_filter *)arg;
2077         struct bnxt_filter_info *bfilter, *filter1;
2078         struct bnxt_vnic_info *vnic, *vnic0;
2079         int ret;
2080
2081         if (filter_op == RTE_ETH_FILTER_NOP)
2082                 return 0;
2083
2084         if (arg == NULL) {
2085                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2086                             filter_op);
2087                 return -EINVAL;
2088         }
2089
2090         vnic0 = &bp->vnic_info[0];
2091         vnic = &bp->vnic_info[efilter->queue];
2092
2093         switch (filter_op) {
2094         case RTE_ETH_FILTER_ADD:
2095                 bnxt_match_and_validate_ether_filter(bp, efilter,
2096                                                         vnic0, vnic, &ret);
2097                 if (ret < 0)
2098                         return ret;
2099
2100                 bfilter = bnxt_get_unused_filter(bp);
2101                 if (bfilter == NULL) {
2102                         PMD_DRV_LOG(ERR,
2103                                 "Not enough resources for a new filter.\n");
2104                         return -ENOMEM;
2105                 }
2106                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2107                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2108                        RTE_ETHER_ADDR_LEN);
2109                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2110                        RTE_ETHER_ADDR_LEN);
2111                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2112                 bfilter->ethertype = efilter->ether_type;
2113                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2114
2115                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2116                 if (filter1 == NULL) {
2117                         ret = -1;
2118                         goto cleanup;
2119                 }
2120                 bfilter->enables |=
2121                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2122                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2123
2124                 bfilter->dst_id = vnic->fw_vnic_id;
2125
2126                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2127                         bfilter->flags =
2128                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2129                 }
2130
2131                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2132                 if (ret)
2133                         goto cleanup;
2134                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2135                 break;
2136         case RTE_ETH_FILTER_DELETE:
2137                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2138                                                         vnic0, vnic, &ret);
2139                 if (ret == -EEXIST) {
2140                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2141
2142                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2143                                       next);
2144                         bnxt_free_filter(bp, filter1);
2145                 } else if (ret == 0) {
2146                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2147                 }
2148                 break;
2149         default:
2150                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2151                 ret = -EINVAL;
2152                 goto error;
2153         }
2154         return ret;
2155 cleanup:
2156         bnxt_free_filter(bp, bfilter);
2157 error:
2158         return ret;
2159 }
2160
2161 static inline int
2162 parse_ntuple_filter(struct bnxt *bp,
2163                     struct rte_eth_ntuple_filter *nfilter,
2164                     struct bnxt_filter_info *bfilter)
2165 {
2166         uint32_t en = 0;
2167
2168         if (nfilter->queue >= bp->rx_nr_rings) {
2169                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2170                 return -EINVAL;
2171         }
2172
2173         switch (nfilter->dst_port_mask) {
2174         case UINT16_MAX:
2175                 bfilter->dst_port_mask = -1;
2176                 bfilter->dst_port = nfilter->dst_port;
2177                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2178                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2179                 break;
2180         default:
2181                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2182                 return -EINVAL;
2183         }
2184
2185         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2186         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2187
2188         switch (nfilter->proto_mask) {
2189         case UINT8_MAX:
2190                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2191                         bfilter->ip_protocol = 17;
2192                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2193                         bfilter->ip_protocol = 6;
2194                 else
2195                         return -EINVAL;
2196                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2197                 break;
2198         default:
2199                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2200                 return -EINVAL;
2201         }
2202
2203         switch (nfilter->dst_ip_mask) {
2204         case UINT32_MAX:
2205                 bfilter->dst_ipaddr_mask[0] = -1;
2206                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2207                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2208                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2209                 break;
2210         default:
2211                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2212                 return -EINVAL;
2213         }
2214
2215         switch (nfilter->src_ip_mask) {
2216         case UINT32_MAX:
2217                 bfilter->src_ipaddr_mask[0] = -1;
2218                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2219                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2220                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2221                 break;
2222         default:
2223                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2224                 return -EINVAL;
2225         }
2226
2227         switch (nfilter->src_port_mask) {
2228         case UINT16_MAX:
2229                 bfilter->src_port_mask = -1;
2230                 bfilter->src_port = nfilter->src_port;
2231                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2232                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2233                 break;
2234         default:
2235                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2236                 return -EINVAL;
2237         }
2238
2239         //TODO Priority
2240         //nfilter->priority = (uint8_t)filter->priority;
2241
2242         bfilter->enables = en;
2243         return 0;
2244 }
2245
2246 static struct bnxt_filter_info*
2247 bnxt_match_ntuple_filter(struct bnxt *bp,
2248                          struct bnxt_filter_info *bfilter,
2249                          struct bnxt_vnic_info **mvnic)
2250 {
2251         struct bnxt_filter_info *mfilter = NULL;
2252         int i;
2253
2254         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2255                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2256                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2257                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2258                             bfilter->src_ipaddr_mask[0] ==
2259                             mfilter->src_ipaddr_mask[0] &&
2260                             bfilter->src_port == mfilter->src_port &&
2261                             bfilter->src_port_mask == mfilter->src_port_mask &&
2262                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2263                             bfilter->dst_ipaddr_mask[0] ==
2264                             mfilter->dst_ipaddr_mask[0] &&
2265                             bfilter->dst_port == mfilter->dst_port &&
2266                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2267                             bfilter->flags == mfilter->flags &&
2268                             bfilter->enables == mfilter->enables) {
2269                                 if (mvnic)
2270                                         *mvnic = vnic;
2271                                 return mfilter;
2272                         }
2273                 }
2274         }
2275         return NULL;
2276 }
2277
2278 static int
2279 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2280                        struct rte_eth_ntuple_filter *nfilter,
2281                        enum rte_filter_op filter_op)
2282 {
2283         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2284         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2285         int ret;
2286
2287         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2288                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2289                 return -EINVAL;
2290         }
2291
2292         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2293                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2294                 return -EINVAL;
2295         }
2296
2297         bfilter = bnxt_get_unused_filter(bp);
2298         if (bfilter == NULL) {
2299                 PMD_DRV_LOG(ERR,
2300                         "Not enough resources for a new filter.\n");
2301                 return -ENOMEM;
2302         }
2303         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2304         if (ret < 0)
2305                 goto free_filter;
2306
2307         vnic = &bp->vnic_info[nfilter->queue];
2308         vnic0 = &bp->vnic_info[0];
2309         filter1 = STAILQ_FIRST(&vnic0->filter);
2310         if (filter1 == NULL) {
2311                 ret = -1;
2312                 goto free_filter;
2313         }
2314
2315         bfilter->dst_id = vnic->fw_vnic_id;
2316         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2317         bfilter->enables |=
2318                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2319         bfilter->ethertype = 0x800;
2320         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2321
2322         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2323
2324         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2325             bfilter->dst_id == mfilter->dst_id) {
2326                 PMD_DRV_LOG(ERR, "filter exists.\n");
2327                 ret = -EEXIST;
2328                 goto free_filter;
2329         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2330                    bfilter->dst_id != mfilter->dst_id) {
2331                 mfilter->dst_id = vnic->fw_vnic_id;
2332                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2333                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2334                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2335                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2336                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2337                 goto free_filter;
2338         }
2339         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2340                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2341                 ret = -ENOENT;
2342                 goto free_filter;
2343         }
2344
2345         if (filter_op == RTE_ETH_FILTER_ADD) {
2346                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2347                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2348                 if (ret)
2349                         goto free_filter;
2350                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2351         } else {
2352                 if (mfilter == NULL) {
2353                         /* This should not happen. But for Coverity! */
2354                         ret = -ENOENT;
2355                         goto free_filter;
2356                 }
2357                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2358
2359                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2360                 bnxt_free_filter(bp, mfilter);
2361                 mfilter->fw_l2_filter_id = -1;
2362                 bnxt_free_filter(bp, bfilter);
2363                 bfilter->fw_l2_filter_id = -1;
2364         }
2365
2366         return 0;
2367 free_filter:
2368         bfilter->fw_l2_filter_id = -1;
2369         bnxt_free_filter(bp, bfilter);
2370         return ret;
2371 }
2372
2373 static int
2374 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2375                         enum rte_filter_op filter_op,
2376                         void *arg)
2377 {
2378         struct bnxt *bp = dev->data->dev_private;
2379         int ret;
2380
2381         if (filter_op == RTE_ETH_FILTER_NOP)
2382                 return 0;
2383
2384         if (arg == NULL) {
2385                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2386                             filter_op);
2387                 return -EINVAL;
2388         }
2389
2390         switch (filter_op) {
2391         case RTE_ETH_FILTER_ADD:
2392                 ret = bnxt_cfg_ntuple_filter(bp,
2393                         (struct rte_eth_ntuple_filter *)arg,
2394                         filter_op);
2395                 break;
2396         case RTE_ETH_FILTER_DELETE:
2397                 ret = bnxt_cfg_ntuple_filter(bp,
2398                         (struct rte_eth_ntuple_filter *)arg,
2399                         filter_op);
2400                 break;
2401         default:
2402                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2403                 ret = -EINVAL;
2404                 break;
2405         }
2406         return ret;
2407 }
2408
2409 static int
2410 bnxt_parse_fdir_filter(struct bnxt *bp,
2411                        struct rte_eth_fdir_filter *fdir,
2412                        struct bnxt_filter_info *filter)
2413 {
2414         enum rte_fdir_mode fdir_mode =
2415                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2416         struct bnxt_vnic_info *vnic0, *vnic;
2417         struct bnxt_filter_info *filter1;
2418         uint32_t en = 0;
2419         int i;
2420
2421         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2422                 return -EINVAL;
2423
2424         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2425         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2426
2427         switch (fdir->input.flow_type) {
2428         case RTE_ETH_FLOW_IPV4:
2429         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2430                 /* FALLTHROUGH */
2431                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2432                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2433                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2434                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2435                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2436                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2437                 filter->ip_addr_type =
2438                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2439                 filter->src_ipaddr_mask[0] = 0xffffffff;
2440                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2441                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2442                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2443                 filter->ethertype = 0x800;
2444                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2445                 break;
2446         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2447                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2448                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2449                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2450                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2451                 filter->dst_port_mask = 0xffff;
2452                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2453                 filter->src_port_mask = 0xffff;
2454                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2455                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2456                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2457                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2458                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2459                 filter->ip_protocol = 6;
2460                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2461                 filter->ip_addr_type =
2462                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2463                 filter->src_ipaddr_mask[0] = 0xffffffff;
2464                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2465                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2466                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2467                 filter->ethertype = 0x800;
2468                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2469                 break;
2470         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2471                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2472                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2473                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2474                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2475                 filter->dst_port_mask = 0xffff;
2476                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2477                 filter->src_port_mask = 0xffff;
2478                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2479                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2480                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2481                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2482                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2483                 filter->ip_protocol = 17;
2484                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2485                 filter->ip_addr_type =
2486                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2487                 filter->src_ipaddr_mask[0] = 0xffffffff;
2488                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2489                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2490                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2491                 filter->ethertype = 0x800;
2492                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2493                 break;
2494         case RTE_ETH_FLOW_IPV6:
2495         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2496                 /* FALLTHROUGH */
2497                 filter->ip_addr_type =
2498                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2499                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2500                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2501                 rte_memcpy(filter->src_ipaddr,
2502                            fdir->input.flow.ipv6_flow.src_ip, 16);
2503                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2504                 rte_memcpy(filter->dst_ipaddr,
2505                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2506                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2507                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2508                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2509                 memset(filter->src_ipaddr_mask, 0xff, 16);
2510                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2511                 filter->ethertype = 0x86dd;
2512                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2513                 break;
2514         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2515                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2516                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2517                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2518                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2519                 filter->dst_port_mask = 0xffff;
2520                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2521                 filter->src_port_mask = 0xffff;
2522                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2523                 filter->ip_addr_type =
2524                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2525                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2526                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2527                 rte_memcpy(filter->src_ipaddr,
2528                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2529                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2530                 rte_memcpy(filter->dst_ipaddr,
2531                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2532                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2533                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2534                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2535                 memset(filter->src_ipaddr_mask, 0xff, 16);
2536                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2537                 filter->ethertype = 0x86dd;
2538                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2539                 break;
2540         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2541                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2542                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2543                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2544                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2545                 filter->dst_port_mask = 0xffff;
2546                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2547                 filter->src_port_mask = 0xffff;
2548                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2549                 filter->ip_addr_type =
2550                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2551                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2552                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2553                 rte_memcpy(filter->src_ipaddr,
2554                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2555                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2556                 rte_memcpy(filter->dst_ipaddr,
2557                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2558                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2559                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2560                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2561                 memset(filter->src_ipaddr_mask, 0xff, 16);
2562                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2563                 filter->ethertype = 0x86dd;
2564                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2565                 break;
2566         case RTE_ETH_FLOW_L2_PAYLOAD:
2567                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2568                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2569                 break;
2570         case RTE_ETH_FLOW_VXLAN:
2571                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2572                         return -EINVAL;
2573                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2574                 filter->tunnel_type =
2575                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2576                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2577                 break;
2578         case RTE_ETH_FLOW_NVGRE:
2579                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2580                         return -EINVAL;
2581                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2582                 filter->tunnel_type =
2583                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2584                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2585                 break;
2586         case RTE_ETH_FLOW_UNKNOWN:
2587         case RTE_ETH_FLOW_RAW:
2588         case RTE_ETH_FLOW_FRAG_IPV4:
2589         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2590         case RTE_ETH_FLOW_FRAG_IPV6:
2591         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2592         case RTE_ETH_FLOW_IPV6_EX:
2593         case RTE_ETH_FLOW_IPV6_TCP_EX:
2594         case RTE_ETH_FLOW_IPV6_UDP_EX:
2595         case RTE_ETH_FLOW_GENEVE:
2596                 /* FALLTHROUGH */
2597         default:
2598                 return -EINVAL;
2599         }
2600
2601         vnic0 = &bp->vnic_info[0];
2602         vnic = &bp->vnic_info[fdir->action.rx_queue];
2603         if (vnic == NULL) {
2604                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2605                 return -EINVAL;
2606         }
2607
2608
2609         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2610                 rte_memcpy(filter->dst_macaddr,
2611                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2612                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2613         }
2614
2615         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2616                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2617                 filter1 = STAILQ_FIRST(&vnic0->filter);
2618                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2619         } else {
2620                 filter->dst_id = vnic->fw_vnic_id;
2621                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2622                         if (filter->dst_macaddr[i] == 0x00)
2623                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2624                         else
2625                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2626         }
2627
2628         if (filter1 == NULL)
2629                 return -EINVAL;
2630
2631         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2632         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2633
2634         filter->enables = en;
2635
2636         return 0;
2637 }
2638
2639 static struct bnxt_filter_info *
2640 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2641                 struct bnxt_vnic_info **mvnic)
2642 {
2643         struct bnxt_filter_info *mf = NULL;
2644         int i;
2645
2646         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2647                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2648
2649                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2650                         if (mf->filter_type == nf->filter_type &&
2651                             mf->flags == nf->flags &&
2652                             mf->src_port == nf->src_port &&
2653                             mf->src_port_mask == nf->src_port_mask &&
2654                             mf->dst_port == nf->dst_port &&
2655                             mf->dst_port_mask == nf->dst_port_mask &&
2656                             mf->ip_protocol == nf->ip_protocol &&
2657                             mf->ip_addr_type == nf->ip_addr_type &&
2658                             mf->ethertype == nf->ethertype &&
2659                             mf->vni == nf->vni &&
2660                             mf->tunnel_type == nf->tunnel_type &&
2661                             mf->l2_ovlan == nf->l2_ovlan &&
2662                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2663                             mf->l2_ivlan == nf->l2_ivlan &&
2664                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2665                             !memcmp(mf->l2_addr, nf->l2_addr,
2666                                     RTE_ETHER_ADDR_LEN) &&
2667                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2668                                     RTE_ETHER_ADDR_LEN) &&
2669                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2670                                     RTE_ETHER_ADDR_LEN) &&
2671                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2672                                     RTE_ETHER_ADDR_LEN) &&
2673                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2674                                     sizeof(nf->src_ipaddr)) &&
2675                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2676                                     sizeof(nf->src_ipaddr_mask)) &&
2677                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2678                                     sizeof(nf->dst_ipaddr)) &&
2679                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2680                                     sizeof(nf->dst_ipaddr_mask))) {
2681                                 if (mvnic)
2682                                         *mvnic = vnic;
2683                                 return mf;
2684                         }
2685                 }
2686         }
2687         return NULL;
2688 }
2689
2690 static int
2691 bnxt_fdir_filter(struct rte_eth_dev *dev,
2692                  enum rte_filter_op filter_op,
2693                  void *arg)
2694 {
2695         struct bnxt *bp = dev->data->dev_private;
2696         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2697         struct bnxt_filter_info *filter, *match;
2698         struct bnxt_vnic_info *vnic, *mvnic;
2699         int ret = 0, i;
2700
2701         if (filter_op == RTE_ETH_FILTER_NOP)
2702                 return 0;
2703
2704         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2705                 return -EINVAL;
2706
2707         switch (filter_op) {
2708         case RTE_ETH_FILTER_ADD:
2709         case RTE_ETH_FILTER_DELETE:
2710                 /* FALLTHROUGH */
2711                 filter = bnxt_get_unused_filter(bp);
2712                 if (filter == NULL) {
2713                         PMD_DRV_LOG(ERR,
2714                                 "Not enough resources for a new flow.\n");
2715                         return -ENOMEM;
2716                 }
2717
2718                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2719                 if (ret != 0)
2720                         goto free_filter;
2721                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2722
2723                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2724                         vnic = &bp->vnic_info[0];
2725                 else
2726                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2727
2728                 match = bnxt_match_fdir(bp, filter, &mvnic);
2729                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2730                         if (match->dst_id == vnic->fw_vnic_id) {
2731                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2732                                 ret = -EEXIST;
2733                                 goto free_filter;
2734                         } else {
2735                                 match->dst_id = vnic->fw_vnic_id;
2736                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2737                                                                   match->dst_id,
2738                                                                   match);
2739                                 STAILQ_REMOVE(&mvnic->filter, match,
2740                                               bnxt_filter_info, next);
2741                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2742                                 PMD_DRV_LOG(ERR,
2743                                         "Filter with matching pattern exist\n");
2744                                 PMD_DRV_LOG(ERR,
2745                                         "Updated it to new destination q\n");
2746                                 goto free_filter;
2747                         }
2748                 }
2749                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2750                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2751                         ret = -ENOENT;
2752                         goto free_filter;
2753                 }
2754
2755                 if (filter_op == RTE_ETH_FILTER_ADD) {
2756                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2757                                                           filter->dst_id,
2758                                                           filter);
2759                         if (ret)
2760                                 goto free_filter;
2761                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2762                 } else {
2763                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2764                         STAILQ_REMOVE(&vnic->filter, match,
2765                                       bnxt_filter_info, next);
2766                         bnxt_free_filter(bp, match);
2767                         filter->fw_l2_filter_id = -1;
2768                         bnxt_free_filter(bp, filter);
2769                 }
2770                 break;
2771         case RTE_ETH_FILTER_FLUSH:
2772                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2773                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2774
2775                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2776                                 if (filter->filter_type ==
2777                                     HWRM_CFA_NTUPLE_FILTER) {
2778                                         ret =
2779                                         bnxt_hwrm_clear_ntuple_filter(bp,
2780                                                                       filter);
2781                                         STAILQ_REMOVE(&vnic->filter, filter,
2782                                                       bnxt_filter_info, next);
2783                                 }
2784                         }
2785                 }
2786                 return ret;
2787         case RTE_ETH_FILTER_UPDATE:
2788         case RTE_ETH_FILTER_STATS:
2789         case RTE_ETH_FILTER_INFO:
2790                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2791                 break;
2792         default:
2793                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2794                 ret = -EINVAL;
2795                 break;
2796         }
2797         return ret;
2798
2799 free_filter:
2800         filter->fw_l2_filter_id = -1;
2801         bnxt_free_filter(bp, filter);
2802         return ret;
2803 }
2804
2805 static int
2806 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2807                     enum rte_filter_type filter_type,
2808                     enum rte_filter_op filter_op, void *arg)
2809 {
2810         int ret = 0;
2811
2812         switch (filter_type) {
2813         case RTE_ETH_FILTER_TUNNEL:
2814                 PMD_DRV_LOG(ERR,
2815                         "filter type: %d: To be implemented\n", filter_type);
2816                 break;
2817         case RTE_ETH_FILTER_FDIR:
2818                 ret = bnxt_fdir_filter(dev, filter_op, arg);
2819                 break;
2820         case RTE_ETH_FILTER_NTUPLE:
2821                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2822                 break;
2823         case RTE_ETH_FILTER_ETHERTYPE:
2824                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2825                 break;
2826         case RTE_ETH_FILTER_GENERIC:
2827                 if (filter_op != RTE_ETH_FILTER_GET)
2828                         return -EINVAL;
2829                 *(const void **)arg = &bnxt_flow_ops;
2830                 break;
2831         default:
2832                 PMD_DRV_LOG(ERR,
2833                         "Filter type (%d) not supported", filter_type);
2834                 ret = -EINVAL;
2835                 break;
2836         }
2837         return ret;
2838 }
2839
2840 static const uint32_t *
2841 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2842 {
2843         static const uint32_t ptypes[] = {
2844                 RTE_PTYPE_L2_ETHER_VLAN,
2845                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2846                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2847                 RTE_PTYPE_L4_ICMP,
2848                 RTE_PTYPE_L4_TCP,
2849                 RTE_PTYPE_L4_UDP,
2850                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2851                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2852                 RTE_PTYPE_INNER_L4_ICMP,
2853                 RTE_PTYPE_INNER_L4_TCP,
2854                 RTE_PTYPE_INNER_L4_UDP,
2855                 RTE_PTYPE_UNKNOWN
2856         };
2857
2858         if (!dev->rx_pkt_burst)
2859                 return NULL;
2860
2861         return ptypes;
2862 }
2863
2864 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2865                          int reg_win)
2866 {
2867         uint32_t reg_base = *reg_arr & 0xfffff000;
2868         uint32_t win_off;
2869         int i;
2870
2871         for (i = 0; i < count; i++) {
2872                 if ((reg_arr[i] & 0xfffff000) != reg_base)
2873                         return -ERANGE;
2874         }
2875         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2876         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
2877         return 0;
2878 }
2879
2880 static int bnxt_map_ptp_regs(struct bnxt *bp)
2881 {
2882         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2883         uint32_t *reg_arr;
2884         int rc, i;
2885
2886         reg_arr = ptp->rx_regs;
2887         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2888         if (rc)
2889                 return rc;
2890
2891         reg_arr = ptp->tx_regs;
2892         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2893         if (rc)
2894                 return rc;
2895
2896         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2897                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2898
2899         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2900                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2901
2902         return 0;
2903 }
2904
2905 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2906 {
2907         rte_write32(0, (uint8_t *)bp->bar0 +
2908                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
2909         rte_write32(0, (uint8_t *)bp->bar0 +
2910                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
2911 }
2912
2913 static uint64_t bnxt_cc_read(struct bnxt *bp)
2914 {
2915         uint64_t ns;
2916
2917         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2918                               BNXT_GRCPF_REG_SYNC_TIME));
2919         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2920                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2921         return ns;
2922 }
2923
2924 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2925 {
2926         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2927         uint32_t fifo;
2928
2929         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2930                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2931         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2932                 return -EAGAIN;
2933
2934         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2935                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2936         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2937                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2938         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2939                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2940
2941         return 0;
2942 }
2943
2944 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2945 {
2946         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2947         struct bnxt_pf_info *pf = &bp->pf;
2948         uint16_t port_id;
2949         uint32_t fifo;
2950
2951         if (!ptp)
2952                 return -ENODEV;
2953
2954         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2955                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2956         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2957                 return -EAGAIN;
2958
2959         port_id = pf->port_id;
2960         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2961                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
2962
2963         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2964                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2965         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2966 /*              bnxt_clr_rx_ts(bp);       TBD  */
2967                 return -EBUSY;
2968         }
2969
2970         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2971                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2972         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2973                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2974
2975         return 0;
2976 }
2977
2978 static int
2979 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2980 {
2981         uint64_t ns;
2982         struct bnxt *bp = dev->data->dev_private;
2983         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2984
2985         if (!ptp)
2986                 return 0;
2987
2988         ns = rte_timespec_to_ns(ts);
2989         /* Set the timecounters to a new value. */
2990         ptp->tc.nsec = ns;
2991
2992         return 0;
2993 }
2994
2995 static int
2996 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2997 {
2998         uint64_t ns, systime_cycles;
2999         struct bnxt *bp = dev->data->dev_private;
3000         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3001
3002         if (!ptp)
3003                 return 0;
3004
3005         systime_cycles = bnxt_cc_read(bp);
3006         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3007         *ts = rte_ns_to_timespec(ns);
3008
3009         return 0;
3010 }
3011 static int
3012 bnxt_timesync_enable(struct rte_eth_dev *dev)
3013 {
3014         struct bnxt *bp = dev->data->dev_private;
3015         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3016         uint32_t shift = 0;
3017
3018         if (!ptp)
3019                 return 0;
3020
3021         ptp->rx_filter = 1;
3022         ptp->tx_tstamp_en = 1;
3023         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3024
3025         if (!bnxt_hwrm_ptp_cfg(bp))
3026                 bnxt_map_ptp_regs(bp);
3027
3028         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3029         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3030         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3031
3032         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3033         ptp->tc.cc_shift = shift;
3034         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3035
3036         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3037         ptp->rx_tstamp_tc.cc_shift = shift;
3038         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3039
3040         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3041         ptp->tx_tstamp_tc.cc_shift = shift;
3042         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3043
3044         return 0;
3045 }
3046
3047 static int
3048 bnxt_timesync_disable(struct rte_eth_dev *dev)
3049 {
3050         struct bnxt *bp = dev->data->dev_private;
3051         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3052
3053         if (!ptp)
3054                 return 0;
3055
3056         ptp->rx_filter = 0;
3057         ptp->tx_tstamp_en = 0;
3058         ptp->rxctl = 0;
3059
3060         bnxt_hwrm_ptp_cfg(bp);
3061
3062         bnxt_unmap_ptp_regs(bp);
3063
3064         return 0;
3065 }
3066
3067 static int
3068 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3069                                  struct timespec *timestamp,
3070                                  uint32_t flags __rte_unused)
3071 {
3072         struct bnxt *bp = dev->data->dev_private;
3073         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3074         uint64_t rx_tstamp_cycles = 0;
3075         uint64_t ns;
3076
3077         if (!ptp)
3078                 return 0;
3079
3080         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3081         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3082         *timestamp = rte_ns_to_timespec(ns);
3083         return  0;
3084 }
3085
3086 static int
3087 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3088                                  struct timespec *timestamp)
3089 {
3090         struct bnxt *bp = dev->data->dev_private;
3091         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3092         uint64_t tx_tstamp_cycles = 0;
3093         uint64_t ns;
3094
3095         if (!ptp)
3096                 return 0;
3097
3098         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3099         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3100         *timestamp = rte_ns_to_timespec(ns);
3101
3102         return 0;
3103 }
3104
3105 static int
3106 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3107 {
3108         struct bnxt *bp = dev->data->dev_private;
3109         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3110
3111         if (!ptp)
3112                 return 0;
3113
3114         ptp->tc.nsec += delta;
3115
3116         return 0;
3117 }
3118
3119 static int
3120 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3121 {
3122         struct bnxt *bp = dev->data->dev_private;
3123         int rc;
3124         uint32_t dir_entries;
3125         uint32_t entry_length;
3126
3127         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3128                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3129                 bp->pdev->addr.devid, bp->pdev->addr.function);
3130
3131         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3132         if (rc != 0)
3133                 return rc;
3134
3135         return dir_entries * entry_length;
3136 }
3137
3138 static int
3139 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3140                 struct rte_dev_eeprom_info *in_eeprom)
3141 {
3142         struct bnxt *bp = dev->data->dev_private;
3143         uint32_t index;
3144         uint32_t offset;
3145
3146         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3147                 "len = %d\n", bp->pdev->addr.domain,
3148                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3149                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3150
3151         if (in_eeprom->offset == 0) /* special offset value to get directory */
3152                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3153                                                 in_eeprom->data);
3154
3155         index = in_eeprom->offset >> 24;
3156         offset = in_eeprom->offset & 0xffffff;
3157
3158         if (index != 0)
3159                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3160                                            in_eeprom->length, in_eeprom->data);
3161
3162         return 0;
3163 }
3164
3165 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3166 {
3167         switch (dir_type) {
3168         case BNX_DIR_TYPE_CHIMP_PATCH:
3169         case BNX_DIR_TYPE_BOOTCODE:
3170         case BNX_DIR_TYPE_BOOTCODE_2:
3171         case BNX_DIR_TYPE_APE_FW:
3172         case BNX_DIR_TYPE_APE_PATCH:
3173         case BNX_DIR_TYPE_KONG_FW:
3174         case BNX_DIR_TYPE_KONG_PATCH:
3175         case BNX_DIR_TYPE_BONO_FW:
3176         case BNX_DIR_TYPE_BONO_PATCH:
3177                 /* FALLTHROUGH */
3178                 return true;
3179         }
3180
3181         return false;
3182 }
3183
3184 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3185 {
3186         switch (dir_type) {
3187         case BNX_DIR_TYPE_AVS:
3188         case BNX_DIR_TYPE_EXP_ROM_MBA:
3189         case BNX_DIR_TYPE_PCIE:
3190         case BNX_DIR_TYPE_TSCF_UCODE:
3191         case BNX_DIR_TYPE_EXT_PHY:
3192         case BNX_DIR_TYPE_CCM:
3193         case BNX_DIR_TYPE_ISCSI_BOOT:
3194         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3195         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3196                 /* FALLTHROUGH */
3197                 return true;
3198         }
3199
3200         return false;
3201 }
3202
3203 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3204 {
3205         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3206                 bnxt_dir_type_is_other_exec_format(dir_type);
3207 }
3208
3209 static int
3210 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3211                 struct rte_dev_eeprom_info *in_eeprom)
3212 {
3213         struct bnxt *bp = dev->data->dev_private;
3214         uint8_t index, dir_op;
3215         uint16_t type, ext, ordinal, attr;
3216
3217         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3218                 "len = %d\n", bp->pdev->addr.domain,
3219                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3220                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3221
3222         if (!BNXT_PF(bp)) {
3223                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3224                 return -EINVAL;
3225         }
3226
3227         type = in_eeprom->magic >> 16;
3228
3229         if (type == 0xffff) { /* special value for directory operations */
3230                 index = in_eeprom->magic & 0xff;
3231                 dir_op = in_eeprom->magic >> 8;
3232                 if (index == 0)
3233                         return -EINVAL;
3234                 switch (dir_op) {
3235                 case 0x0e: /* erase */
3236                         if (in_eeprom->offset != ~in_eeprom->magic)
3237                                 return -EINVAL;
3238                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3239                 default:
3240                         return -EINVAL;
3241                 }
3242         }
3243
3244         /* Create or re-write an NVM item: */
3245         if (bnxt_dir_type_is_executable(type) == true)
3246                 return -EOPNOTSUPP;
3247         ext = in_eeprom->magic & 0xffff;
3248         ordinal = in_eeprom->offset >> 16;
3249         attr = in_eeprom->offset & 0xffff;
3250
3251         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3252                                      in_eeprom->data, in_eeprom->length);
3253         return 0;
3254 }
3255
3256 /*
3257  * Initialization
3258  */
3259
3260 static const struct eth_dev_ops bnxt_dev_ops = {
3261         .dev_infos_get = bnxt_dev_info_get_op,
3262         .dev_close = bnxt_dev_close_op,
3263         .dev_configure = bnxt_dev_configure_op,
3264         .dev_start = bnxt_dev_start_op,
3265         .dev_stop = bnxt_dev_stop_op,
3266         .dev_set_link_up = bnxt_dev_set_link_up_op,
3267         .dev_set_link_down = bnxt_dev_set_link_down_op,
3268         .stats_get = bnxt_stats_get_op,
3269         .stats_reset = bnxt_stats_reset_op,
3270         .rx_queue_setup = bnxt_rx_queue_setup_op,
3271         .rx_queue_release = bnxt_rx_queue_release_op,
3272         .tx_queue_setup = bnxt_tx_queue_setup_op,
3273         .tx_queue_release = bnxt_tx_queue_release_op,
3274         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3275         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3276         .reta_update = bnxt_reta_update_op,
3277         .reta_query = bnxt_reta_query_op,
3278         .rss_hash_update = bnxt_rss_hash_update_op,
3279         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3280         .link_update = bnxt_link_update_op,
3281         .promiscuous_enable = bnxt_promiscuous_enable_op,
3282         .promiscuous_disable = bnxt_promiscuous_disable_op,
3283         .allmulticast_enable = bnxt_allmulticast_enable_op,
3284         .allmulticast_disable = bnxt_allmulticast_disable_op,
3285         .mac_addr_add = bnxt_mac_addr_add_op,
3286         .mac_addr_remove = bnxt_mac_addr_remove_op,
3287         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3288         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3289         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3290         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3291         .vlan_filter_set = bnxt_vlan_filter_set_op,
3292         .vlan_offload_set = bnxt_vlan_offload_set_op,
3293         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3294         .mtu_set = bnxt_mtu_set_op,
3295         .mac_addr_set = bnxt_set_default_mac_addr_op,
3296         .xstats_get = bnxt_dev_xstats_get_op,
3297         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3298         .xstats_reset = bnxt_dev_xstats_reset_op,
3299         .fw_version_get = bnxt_fw_version_get,
3300         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3301         .rxq_info_get = bnxt_rxq_info_get_op,
3302         .txq_info_get = bnxt_txq_info_get_op,
3303         .dev_led_on = bnxt_dev_led_on_op,
3304         .dev_led_off = bnxt_dev_led_off_op,
3305         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3306         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3307         .rx_queue_count = bnxt_rx_queue_count_op,
3308         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3309         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3310         .rx_queue_start = bnxt_rx_queue_start,
3311         .rx_queue_stop = bnxt_rx_queue_stop,
3312         .tx_queue_start = bnxt_tx_queue_start,
3313         .tx_queue_stop = bnxt_tx_queue_stop,
3314         .filter_ctrl = bnxt_filter_ctrl_op,
3315         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3316         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3317         .get_eeprom           = bnxt_get_eeprom_op,
3318         .set_eeprom           = bnxt_set_eeprom_op,
3319         .timesync_enable      = bnxt_timesync_enable,
3320         .timesync_disable     = bnxt_timesync_disable,
3321         .timesync_read_time   = bnxt_timesync_read_time,
3322         .timesync_write_time   = bnxt_timesync_write_time,
3323         .timesync_adjust_time = bnxt_timesync_adjust_time,
3324         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3325         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3326 };
3327
3328 static bool bnxt_vf_pciid(uint16_t id)
3329 {
3330         if (id == BROADCOM_DEV_ID_57304_VF ||
3331             id == BROADCOM_DEV_ID_57406_VF ||
3332             id == BROADCOM_DEV_ID_5731X_VF ||
3333             id == BROADCOM_DEV_ID_5741X_VF ||
3334             id == BROADCOM_DEV_ID_57414_VF ||
3335             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3336             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3337             id == BROADCOM_DEV_ID_58802_VF ||
3338             id == BROADCOM_DEV_ID_57500_VF)
3339                 return true;
3340         return false;
3341 }
3342
3343 bool bnxt_stratus_device(struct bnxt *bp)
3344 {
3345         uint16_t id = bp->pdev->id.device_id;
3346
3347         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3348             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3349             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3350                 return true;
3351         return false;
3352 }
3353
3354 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3355 {
3356         struct bnxt *bp = eth_dev->data->dev_private;
3357         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3358         int rc;
3359
3360         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3361         if (!pci_dev->mem_resource[0].addr) {
3362                 PMD_DRV_LOG(ERR,
3363                         "Cannot find PCI device base address, aborting\n");
3364                 rc = -ENODEV;
3365                 goto init_err_disable;
3366         }
3367
3368         bp->eth_dev = eth_dev;
3369         bp->pdev = pci_dev;
3370
3371         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3372         if (!bp->bar0) {
3373                 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3374                 rc = -ENOMEM;
3375                 goto init_err_release;
3376         }
3377
3378         if (!pci_dev->mem_resource[2].addr) {
3379                 PMD_DRV_LOG(ERR,
3380                             "Cannot find PCI device BAR 2 address, aborting\n");
3381                 rc = -ENODEV;
3382                 goto init_err_release;
3383         } else {
3384                 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3385         }
3386
3387         return 0;
3388
3389 init_err_release:
3390         if (bp->bar0)
3391                 bp->bar0 = NULL;
3392         if (bp->doorbell_base)
3393                 bp->doorbell_base = NULL;
3394
3395 init_err_disable:
3396
3397         return rc;
3398 }
3399
3400 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3401                                   struct bnxt_ctx_pg_info *ctx_pg,
3402                                   uint32_t mem_size,
3403                                   const char *suffix,
3404                                   uint16_t idx)
3405 {
3406         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3407         const struct rte_memzone *mz = NULL;
3408         char mz_name[RTE_MEMZONE_NAMESIZE];
3409         rte_iova_t mz_phys_addr;
3410         uint64_t valid_bits = 0;
3411         uint32_t sz;
3412         int i;
3413
3414         if (!mem_size)
3415                 return 0;
3416
3417         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3418                          BNXT_PAGE_SIZE;
3419         rmem->page_size = BNXT_PAGE_SIZE;
3420         rmem->pg_arr = ctx_pg->ctx_pg_arr;
3421         rmem->dma_arr = ctx_pg->ctx_dma_arr;
3422         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3423
3424         valid_bits = PTU_PTE_VALID;
3425
3426         if (rmem->nr_pages > 1) {
3427                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_pg_tbl%s_%x",
3428                          suffix, idx);
3429                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3430                 mz = rte_memzone_lookup(mz_name);
3431                 if (!mz) {
3432                         mz = rte_memzone_reserve_aligned(mz_name,
3433                                                 rmem->nr_pages * 8,
3434                                                 SOCKET_ID_ANY,
3435                                                 RTE_MEMZONE_2MB |
3436                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
3437                                                 RTE_MEMZONE_IOVA_CONTIG,
3438                                                 BNXT_PAGE_SIZE);
3439                         if (mz == NULL)
3440                                 return -ENOMEM;
3441                 }
3442
3443                 memset(mz->addr, 0, mz->len);
3444                 mz_phys_addr = mz->iova;
3445                 if ((unsigned long)mz->addr == mz_phys_addr) {
3446                         PMD_DRV_LOG(WARNING,
3447                                 "Memzone physical address same as virtual.\n");
3448                         PMD_DRV_LOG(WARNING,
3449                                     "Using rte_mem_virt2iova()\n");
3450                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3451                         if (mz_phys_addr == 0) {
3452                                 PMD_DRV_LOG(ERR,
3453                                         "unable to map addr to phys memory\n");
3454                                 return -ENOMEM;
3455                         }
3456                 }
3457                 rte_mem_lock_page(((char *)mz->addr));
3458
3459                 rmem->pg_tbl = mz->addr;
3460                 rmem->pg_tbl_map = mz_phys_addr;
3461                 rmem->pg_tbl_mz = mz;
3462         }
3463
3464         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x", suffix, idx);
3465         mz = rte_memzone_lookup(mz_name);
3466         if (!mz) {
3467                 mz = rte_memzone_reserve_aligned(mz_name,
3468                                                  mem_size,
3469                                                  SOCKET_ID_ANY,
3470                                                  RTE_MEMZONE_1GB |
3471                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
3472                                                  RTE_MEMZONE_IOVA_CONTIG,
3473                                                  BNXT_PAGE_SIZE);
3474                 if (mz == NULL)
3475                         return -ENOMEM;
3476         }
3477
3478         memset(mz->addr, 0, mz->len);
3479         mz_phys_addr = mz->iova;
3480         if ((unsigned long)mz->addr == mz_phys_addr) {
3481                 PMD_DRV_LOG(WARNING,
3482                             "Memzone physical address same as virtual.\n");
3483                 PMD_DRV_LOG(WARNING,
3484                             "Using rte_mem_virt2iova()\n");
3485                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
3486                         rte_mem_lock_page(((char *)mz->addr) + sz);
3487                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3488                 if (mz_phys_addr == RTE_BAD_IOVA) {
3489                         PMD_DRV_LOG(ERR,
3490                                     "unable to map addr to phys memory\n");
3491                         return -ENOMEM;
3492                 }
3493         }
3494
3495         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
3496                 rte_mem_lock_page(((char *)mz->addr) + sz);
3497                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
3498                 rmem->dma_arr[i] = mz_phys_addr + sz;
3499
3500                 if (rmem->nr_pages > 1) {
3501                         if (i == rmem->nr_pages - 2 &&
3502                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3503                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
3504                         else if (i == rmem->nr_pages - 1 &&
3505                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3506                                 valid_bits |= PTU_PTE_LAST;
3507
3508                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
3509                                                            valid_bits);
3510                 }
3511         }
3512
3513         rmem->mz = mz;
3514         if (rmem->vmem_size)
3515                 rmem->vmem = (void **)mz->addr;
3516         rmem->dma_arr[0] = mz_phys_addr;
3517         return 0;
3518 }
3519
3520 static void bnxt_free_ctx_mem(struct bnxt *bp)
3521 {
3522         int i;
3523
3524         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
3525                 return;
3526
3527         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
3528         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
3529         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
3530         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
3531         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
3532         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
3533         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
3534         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
3535         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
3536         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
3537         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
3538
3539         for (i = 0; i < BNXT_MAX_Q; i++) {
3540                 if (bp->ctx->tqm_mem[i])
3541                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
3542         }
3543
3544         rte_free(bp->ctx);
3545         bp->ctx = NULL;
3546 }
3547
3548 #define roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
3549
3550 #define min_t(type, x, y) ({                    \
3551         type __min1 = (x);                      \
3552         type __min2 = (y);                      \
3553         __min1 < __min2 ? __min1 : __min2; })
3554
3555 #define max_t(type, x, y) ({                    \
3556         type __max1 = (x);                      \
3557         type __max2 = (y);                      \
3558         __max1 > __max2 ? __max1 : __max2; })
3559
3560 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
3561
3562 int bnxt_alloc_ctx_mem(struct bnxt *bp)
3563 {
3564         struct bnxt_ctx_pg_info *ctx_pg;
3565         struct bnxt_ctx_mem_info *ctx;
3566         uint32_t mem_size, ena, entries;
3567         int i, rc;
3568
3569         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
3570         if (rc) {
3571                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
3572                 return rc;
3573         }
3574         ctx = bp->ctx;
3575         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
3576                 return 0;
3577
3578         ctx_pg = &ctx->qp_mem;
3579         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
3580         mem_size = ctx->qp_entry_size * ctx_pg->entries;
3581         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
3582         if (rc)
3583                 return rc;
3584
3585         ctx_pg = &ctx->srq_mem;
3586         ctx_pg->entries = ctx->srq_max_l2_entries;
3587         mem_size = ctx->srq_entry_size * ctx_pg->entries;
3588         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
3589         if (rc)
3590                 return rc;
3591
3592         ctx_pg = &ctx->cq_mem;
3593         ctx_pg->entries = ctx->cq_max_l2_entries;
3594         mem_size = ctx->cq_entry_size * ctx_pg->entries;
3595         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
3596         if (rc)
3597                 return rc;
3598
3599         ctx_pg = &ctx->vnic_mem;
3600         ctx_pg->entries = ctx->vnic_max_vnic_entries +
3601                 ctx->vnic_max_ring_table_entries;
3602         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
3603         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
3604         if (rc)
3605                 return rc;
3606
3607         ctx_pg = &ctx->stat_mem;
3608         ctx_pg->entries = ctx->stat_max_entries;
3609         mem_size = ctx->stat_entry_size * ctx_pg->entries;
3610         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
3611         if (rc)
3612                 return rc;
3613
3614         entries = ctx->qp_max_l2_entries;
3615         entries = roundup(entries, ctx->tqm_entries_multiple);
3616         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
3617                           ctx->tqm_max_entries_per_ring);
3618         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
3619                 ctx_pg = ctx->tqm_mem[i];
3620                 /* use min tqm entries for now. */
3621                 ctx_pg->entries = entries;
3622                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
3623                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
3624                 if (rc)
3625                         return rc;
3626                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
3627         }
3628
3629         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
3630         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
3631         if (rc)
3632                 PMD_DRV_LOG(ERR,
3633                             "Failed to configure context mem: rc = %d\n", rc);
3634         else
3635                 ctx->flags |= BNXT_CTX_FLAG_INITED;
3636
3637         return 0;
3638 }
3639
3640 #define ALLOW_FUNC(x)   \
3641         { \
3642                 typeof(x) arg = (x); \
3643                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3644                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3645         }
3646 static int
3647 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3648 {
3649         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3650         char mz_name[RTE_MEMZONE_NAMESIZE];
3651         const struct rte_memzone *mz = NULL;
3652         static int version_printed;
3653         uint32_t total_alloc_len;
3654         rte_iova_t mz_phys_addr;
3655         struct bnxt *bp;
3656         uint16_t mtu;
3657         int rc;
3658
3659         if (version_printed++ == 0)
3660                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3661
3662         rte_eth_copy_pci_info(eth_dev, pci_dev);
3663
3664         bp = eth_dev->data->dev_private;
3665
3666         bp->dev_stopped = 1;
3667
3668         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3669                 goto skip_init;
3670
3671         if (bnxt_vf_pciid(pci_dev->id.device_id))
3672                 bp->flags |= BNXT_FLAG_VF;
3673
3674         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
3675             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
3676             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
3677             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF)
3678                 bp->flags |= BNXT_FLAG_THOR_CHIP;
3679
3680         rc = bnxt_init_board(eth_dev);
3681         if (rc) {
3682                 PMD_DRV_LOG(ERR,
3683                         "Board initialization failed rc: %x\n", rc);
3684                 goto error;
3685         }
3686 skip_init:
3687         eth_dev->dev_ops = &bnxt_dev_ops;
3688         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3689         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3690         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3691                 return 0;
3692
3693         if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3694                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3695                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3696                          pci_dev->addr.bus, pci_dev->addr.devid,
3697                          pci_dev->addr.function, "rx_port_stats");
3698                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3699                 mz = rte_memzone_lookup(mz_name);
3700                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3701                                         sizeof(struct rx_port_stats) +
3702                                         sizeof(struct rx_port_stats_ext) +
3703                                         512);
3704                 if (!mz) {
3705                         mz = rte_memzone_reserve(mz_name, total_alloc_len,
3706                                         SOCKET_ID_ANY,
3707                                         RTE_MEMZONE_2MB |
3708                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3709                                         RTE_MEMZONE_IOVA_CONTIG);
3710                         if (mz == NULL)
3711                                 return -ENOMEM;
3712                 }
3713                 memset(mz->addr, 0, mz->len);
3714                 mz_phys_addr = mz->iova;
3715                 if ((unsigned long)mz->addr == mz_phys_addr) {
3716                         PMD_DRV_LOG(INFO,
3717                                 "Memzone physical address same as virtual using rte_mem_virt2iova()\n");
3718                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3719                         if (mz_phys_addr == 0) {
3720                                 PMD_DRV_LOG(ERR,
3721                                 "unable to map address to physical memory\n");
3722                                 return -ENOMEM;
3723                         }
3724                 }
3725
3726                 bp->rx_mem_zone = (const void *)mz;
3727                 bp->hw_rx_port_stats = mz->addr;
3728                 bp->hw_rx_port_stats_map = mz_phys_addr;
3729
3730                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3731                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3732                          pci_dev->addr.bus, pci_dev->addr.devid,
3733                          pci_dev->addr.function, "tx_port_stats");
3734                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3735                 mz = rte_memzone_lookup(mz_name);
3736                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3737                                         sizeof(struct tx_port_stats) +
3738                                         sizeof(struct tx_port_stats_ext) +
3739                                         512);
3740                 if (!mz) {
3741                         mz = rte_memzone_reserve(mz_name,
3742                                         total_alloc_len,
3743                                         SOCKET_ID_ANY,
3744                                         RTE_MEMZONE_2MB |
3745                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3746                                         RTE_MEMZONE_IOVA_CONTIG);
3747                         if (mz == NULL)
3748                                 return -ENOMEM;
3749                 }
3750                 memset(mz->addr, 0, mz->len);
3751                 mz_phys_addr = mz->iova;
3752                 if ((unsigned long)mz->addr == mz_phys_addr) {
3753                         PMD_DRV_LOG(WARNING,
3754                                 "Memzone physical address same as virtual.\n");
3755                         PMD_DRV_LOG(WARNING,
3756                                 "Using rte_mem_virt2iova()\n");
3757                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3758                         if (mz_phys_addr == 0) {
3759                                 PMD_DRV_LOG(ERR,
3760                                 "unable to map address to physical memory\n");
3761                                 return -ENOMEM;
3762                         }
3763                 }
3764
3765                 bp->tx_mem_zone = (const void *)mz;
3766                 bp->hw_tx_port_stats = mz->addr;
3767                 bp->hw_tx_port_stats_map = mz_phys_addr;
3768
3769                 bp->flags |= BNXT_FLAG_PORT_STATS;
3770
3771                 /* Display extended statistics if FW supports it */
3772                 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3773                     bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0)
3774                         goto skip_ext_stats;
3775
3776                 bp->hw_rx_port_stats_ext = (void *)
3777                         ((uint8_t *)bp->hw_rx_port_stats +
3778                          sizeof(struct rx_port_stats));
3779                 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3780                         sizeof(struct rx_port_stats);
3781                 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3782
3783
3784                 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2) {
3785                         bp->hw_tx_port_stats_ext = (void *)
3786                                 ((uint8_t *)bp->hw_tx_port_stats +
3787                                  sizeof(struct tx_port_stats));
3788                         bp->hw_tx_port_stats_ext_map =
3789                                 bp->hw_tx_port_stats_map +
3790                                 sizeof(struct tx_port_stats);
3791                         bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3792                 }
3793         }
3794
3795 skip_ext_stats:
3796         rc = bnxt_alloc_hwrm_resources(bp);
3797         if (rc) {
3798                 PMD_DRV_LOG(ERR,
3799                         "hwrm resource allocation failure rc: %x\n", rc);
3800                 goto error_free;
3801         }
3802         rc = bnxt_hwrm_ver_get(bp);
3803         if (rc)
3804                 goto error_free;
3805
3806         rc = bnxt_hwrm_func_reset(bp);
3807         if (rc) {
3808                 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3809                 rc = -EIO;
3810                 goto error_free;
3811         }
3812
3813         rc = bnxt_hwrm_queue_qportcfg(bp);
3814         if (rc) {
3815                 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3816                 goto error_free;
3817         }
3818         /* Get the MAX capabilities for this function */
3819         rc = bnxt_hwrm_func_qcaps(bp);
3820         if (rc) {
3821                 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3822                 goto error_free;
3823         }
3824         if (bp->max_tx_rings == 0) {
3825                 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3826                 rc = -EBUSY;
3827                 goto error_free;
3828         }
3829         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3830                                         RTE_ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3831         if (eth_dev->data->mac_addrs == NULL) {
3832                 PMD_DRV_LOG(ERR,
3833                         "Failed to alloc %u bytes needed to store MAC addr tbl",
3834                         RTE_ETHER_ADDR_LEN * bp->max_l2_ctx);
3835                 rc = -ENOMEM;
3836                 goto error_free;
3837         }
3838
3839         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
3840                 PMD_DRV_LOG(ERR,
3841                             "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3842                             bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3843                             bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3844                             bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3845                 rc = -EINVAL;
3846                 goto error_free;
3847         }
3848         /* Copy the permanent MAC from the qcap response address now. */
3849         memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3850         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
3851
3852         /* THOR does not support ring groups.
3853          * But we will use the array to save RSS context IDs.
3854          */
3855         if (BNXT_CHIP_THOR(bp)) {
3856                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
3857         } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3858                 /* 1 ring is for default completion ring */
3859                 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3860                 rc = -ENOSPC;
3861                 goto error_free;
3862         }
3863
3864         bp->grp_info = rte_zmalloc("bnxt_grp_info",
3865                                 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3866         if (!bp->grp_info) {
3867                 PMD_DRV_LOG(ERR,
3868                         "Failed to alloc %zu bytes to store group info table\n",
3869                         sizeof(*bp->grp_info) * bp->max_ring_grps);
3870                 rc = -ENOMEM;
3871                 goto error_free;
3872         }
3873
3874         /* Forward all requests if firmware is new enough */
3875         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3876             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3877             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3878                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3879         } else {
3880                 PMD_DRV_LOG(WARNING,
3881                         "Firmware too old for VF mailbox functionality\n");
3882                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3883         }
3884
3885         /*
3886          * The following are used for driver cleanup.  If we disallow these,
3887          * VF drivers can't clean up cleanly.
3888          */
3889         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3890         ALLOW_FUNC(HWRM_VNIC_FREE);
3891         ALLOW_FUNC(HWRM_RING_FREE);
3892         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3893         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3894         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3895         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3896         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3897         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3898         rc = bnxt_hwrm_func_driver_register(bp);
3899         if (rc) {
3900                 PMD_DRV_LOG(ERR,
3901                         "Failed to register driver");
3902                 rc = -EBUSY;
3903                 goto error_free;
3904         }
3905
3906         PMD_DRV_LOG(INFO,
3907                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3908                 pci_dev->mem_resource[0].phys_addr,
3909                 pci_dev->mem_resource[0].addr);
3910
3911         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
3912         if (rc) {
3913                 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3914                 goto error_free;
3915         }
3916
3917         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
3918             mtu != eth_dev->data->mtu)
3919                 eth_dev->data->mtu = mtu;
3920
3921         if (BNXT_PF(bp)) {
3922                 //if (bp->pf.active_vfs) {
3923                         // TODO: Deallocate VF resources?
3924                 //}
3925                 if (bp->pdev->max_vfs) {
3926                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3927                         if (rc) {
3928                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3929                                 goto error_free;
3930                         }
3931                 } else {
3932                         rc = bnxt_hwrm_allocate_pf_only(bp);
3933                         if (rc) {
3934                                 PMD_DRV_LOG(ERR,
3935                                         "Failed to allocate PF resources\n");
3936                                 goto error_free;
3937                         }
3938                 }
3939         }
3940
3941         bnxt_hwrm_port_led_qcaps(bp);
3942
3943         rc = bnxt_setup_int(bp);
3944         if (rc)
3945                 goto error_free;
3946
3947         rc = bnxt_alloc_mem(bp);
3948         if (rc)
3949                 goto error_free_int;
3950
3951         rc = bnxt_request_int(bp);
3952         if (rc)
3953                 goto error_free_int;
3954
3955         bnxt_enable_int(bp);
3956         bnxt_init_nic(bp);
3957
3958         return 0;
3959
3960 error_free_int:
3961         bnxt_disable_int(bp);
3962         bnxt_hwrm_func_buf_unrgtr(bp);
3963         bnxt_free_int(bp);
3964         bnxt_free_mem(bp);
3965 error_free:
3966         bnxt_dev_uninit(eth_dev);
3967 error:
3968         return rc;
3969 }
3970
3971 static int
3972 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3973 {
3974         struct bnxt *bp = eth_dev->data->dev_private;
3975         int rc;
3976
3977         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3978                 return -EPERM;
3979
3980         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
3981         bnxt_disable_int(bp);
3982         bnxt_free_int(bp);
3983         bnxt_free_mem(bp);
3984         if (bp->grp_info != NULL) {
3985                 rte_free(bp->grp_info);
3986                 bp->grp_info = NULL;
3987         }
3988         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3989         bnxt_free_hwrm_resources(bp);
3990
3991         if (bp->tx_mem_zone) {
3992                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3993                 bp->tx_mem_zone = NULL;
3994         }
3995
3996         if (bp->rx_mem_zone) {
3997                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3998                 bp->rx_mem_zone = NULL;
3999         }
4000
4001         if (bp->dev_stopped == 0)
4002                 bnxt_dev_close_op(eth_dev);
4003         if (bp->pf.vf_info)
4004                 rte_free(bp->pf.vf_info);
4005         bnxt_free_ctx_mem(bp);
4006         eth_dev->dev_ops = NULL;
4007         eth_dev->rx_pkt_burst = NULL;
4008         eth_dev->tx_pkt_burst = NULL;
4009
4010         return rc;
4011 }
4012
4013 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4014         struct rte_pci_device *pci_dev)
4015 {
4016         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4017                 bnxt_dev_init);
4018 }
4019
4020 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4021 {
4022         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4023                 return rte_eth_dev_pci_generic_remove(pci_dev,
4024                                 bnxt_dev_uninit);
4025         else
4026                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4027 }
4028
4029 static struct rte_pci_driver bnxt_rte_pmd = {
4030         .id_table = bnxt_pci_id_map,
4031         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
4032                 RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_IOVA_AS_VA,
4033         .probe = bnxt_pci_probe,
4034         .remove = bnxt_pci_remove,
4035 };
4036
4037 static bool
4038 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4039 {
4040         if (strcmp(dev->device->driver->name, drv->driver.name))
4041                 return false;
4042
4043         return true;
4044 }
4045
4046 bool is_bnxt_supported(struct rte_eth_dev *dev)
4047 {
4048         return is_device_supported(dev, &bnxt_rte_pmd);
4049 }
4050
4051 RTE_INIT(bnxt_init_log)
4052 {
4053         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4054         if (bnxt_logtype_driver >= 0)
4055                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4056 }
4057
4058 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4059 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4060 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");